fpga-icestorm-0~20160913git266e758/000077500000000000000000000000001276746530600163725ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/.gitignore000066400000000000000000000000431276746530600203570ustar00rootroot00000000000000icestorm-win32.zip icestorm-win32/ fpga-icestorm-0~20160913git266e758/CodeOfConduct000066400000000000000000000061731276746530600210030ustar00rootroot00000000000000Contributor Covenant Code of Conduct Our Pledge In the interest of fostering an open and welcoming environment, we as contributors and maintainers pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level of experience, nationality, personal appearance, race, religion, or sexual identity and orientation. Our Standards Examples of behavior that contributes to creating a positive environment include: * Using welcoming and inclusive language * Being respectful of differing viewpoints and experiences * Gracefully accepting constructive criticism * Focusing on what is best for the community * Showing empathy towards other community members Examples of unacceptable behavior by participants include: * The use of sexualized language or imagery and unwelcome sexual attention or advances * Trolling, insulting/derogatory comments, and personal or political attacks * Public or private harassment * Publishing others' private information, such as a physical or electronic address, without explicit permission * Other conduct which could reasonably be considered inappropriate in a professional setting Our Responsibilities Project maintainers are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. Project maintainers have the right and responsibility to remove, edit, or reject comments, commits, code, wiki edits, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any contributor for other behaviors that they deem inappropriate, threatening, offensive, or harmful. Scope This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. Examples of representing a project or community include using an official project e-mail address, posting via an official social media account, or acting as an appointed representative at an online or offline event. Representation of a project may be further defined and clarified by project maintainers. Enforcement Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at clifford@clifford.at (and/or cliffordvienna@gmail.com if you think your mail to the other address got stuck in the spam filter). All complaints will be reviewed and investigated and will result in a response that is deemed necessary and appropriate to the circumstances. The project team is obligated to maintain confidentiality with regard to the reporter of an incident. Further details of specific enforcement policies may be posted separately. Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership. Attribution This Code of Conduct is adapted from the Contributor Covenant, version 1.4, available at http://contributor-covenant.org/version/1/4/ fpga-icestorm-0~20160913git266e758/Makefile000066400000000000000000000020521276746530600200310ustar00rootroot00000000000000include config.mk all: $(MAKE) -C icebox $(MAKE) -C icepack $(MAKE) -C iceprog $(MAKE) -C icemulti $(MAKE) -C icepll $(MAKE) -C icetime $(MAKE) -C icebram clean: $(MAKE) -C icebox clean $(MAKE) -C icepack clean $(MAKE) -C iceprog clean $(MAKE) -C icemulti clean $(MAKE) -C icepll clean $(MAKE) -C icetime clean $(MAKE) -C icebram clean install: $(MAKE) -C icebox install $(MAKE) -C icepack install $(MAKE) -C iceprog install $(MAKE) -C icemulti install $(MAKE) -C icepll install $(MAKE) -C icetime install $(MAKE) -C icebram install uninstall: $(MAKE) -C icebox uninstall $(MAKE) -C icepack uninstall $(MAKE) -C iceprog uninstall $(MAKE) -C icemulti uninstall $(MAKE) -C icepll uninstall $(MAKE) -C icetime uninstall $(MAKE) -C icebram uninstall mxebin: clean $(MAKE) MXE=1 rm -rf icestorm-win32 && mkdir icestorm-win32 cp icebox/chipdb-*.txt icepack/*.exe iceprog/*.exe icestorm-win32/ cp icemulti/*.exe icepll/*.exe icetime/*.exe icestorm-win32/ zip -r icestorm-win32.zip icestorm-win32/ .PHONY: all clean install uninstall fpga-icestorm-0~20160913git266e758/README000066400000000000000000000017521276746530600172570ustar00rootroot00000000000000Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. See http://www.clifford.at/icestorm/ for more information. Most of Project IceStorm is licensed under the ISC license: # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. fpga-icestorm-0~20160913git266e758/config.mk000066400000000000000000000003751276746530600201750ustar00rootroot00000000000000CXX ?= clang CC ?= $(CXX) PKG_CONFIG ?= pkg-config DESTDIR ?= PREFIX ?= /usr/local ifeq ($(MXE),1) EXE = .exe CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config endif fpga-icestorm-0~20160913git266e758/docs/000077500000000000000000000000001276746530600173225ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/docs/checkerboard.png000066400000000000000000000020731276746530600224460ustar00rootroot00000000000000PNG  IHDR ngAMA asRGB cHRMz&u0`:pQ<PLTE^bKGDޕz pHYsHHFk>IDATx;n0P%ΧvhZ@\,qY=S8 (Jg=|~5 ô?|nr\l7i[J9Wc?8WVvb`„ &L0a„ &L0a„ٟ2,_NժۗRsm՝ &L0a„ &L0a„ 33C /56JB՝ &L0a„ &L0a„ 33C /5 a„ &L0a„ &L0a„!ؗV0a„ &L0a„ &L0aLKM+a0a„ &L0a„ &L0abf0L0a„ &L0a„ &L0S13Rp&L0a„ &L0a„ &L}ie8 &L0a„ &L0a„ &T̟n99Zusm՝ &L0a„ &L0a„ 33C /5](v[`„ &L0a„ &L0a„!ؗV0a„ &L0a„ &L0aLKM+a0a„ &L0a„ &L0abf0L0a„ &L0a„ &L0S13Rp&L0a„ &L0a„ &L}ie8 &L0a„ &L0a„ &T Դ2 &L0a„ &L0a„ f*n checkerboard_0.ppm ../icepack/icepack -ucc -B0 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 0" > checkerboard_1.ppm ../icepack/icepack -uc -B1 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 1" > checkerboard_2.ppm ../icepack/icepack -ucc -B1 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 0 0" > checkerboard_3.ppm ../icepack/icepack -uc -B2 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 0 1" > checkerboard_4.ppm ../icepack/icepack -ucc -B2 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 1 0" > checkerboard_5.ppm ../icepack/icepack -uc -B3 ../tests/example.bin | pbm_to_ppm "0 0 0" "1 1 1" > checkerboard_6.ppm ../icepack/icepack -ucc -B3 ../tests/example.bin | pbm_to_ppm "0 0 0" "0 1 0" > checkerboard_7.ppm convert -evaluate-sequence add checkerboard_[01234567].ppm checkerboard.png rm -f checkerboard_[01234567].ppm fpga-icestorm-0~20160913git266e758/docs/colbuf.svg000066400000000000000000000274571276746530600213340ustar00rootroot00000000000000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 fpga-icestorm-0~20160913git266e758/docs/format.html000066400000000000000000000146761276746530600215160ustar00rootroot00000000000000 Project IceStorm – Bitstream File Format Documentation

Project IceStorm – Bitstream File Format Documentation

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. This is work in progress.

General Description of the File Format

The bitstream file starts with the bytes 0xFF 0x00, followed by a sequence of zero-terminated comment strings, followed by 0x00 0xFF. However, there seems to be a bug in the Lattice "bitstream" tool that moves the terminating 0x00 0xFF a few bytes into the comment string in some cases.

After the comment sections the token 0x7EAA997E (MSB first) starts the actual bit stream. The bitstream consists of one-byte commands, followed by a payload word, followed by an optional block of data. The MSB nibble of the command byte is the command opcode, the LSB nibble is the length of the command payload in bytes. The commands that do not require a payload are using the opcode 0, with the command encoded in the payload field. Note that this "payload" in this context refers to a single integer argument, not the blocks of data that follows the command in case of the CRAM and BRAM commands.

The following commands are known:

OpcodeDescription
0payload=1: CRAM Data
payload=3: BRAM Data
payload=5: Reset CRC
payload=6: Wakeup
payload=8: Reboot
1Set bank number
2CRC check
4Set boot address
5Set internal oscillator frequency range
payload=0: low
payload=1: medium
payload=2: high
6Set bank width
7Set bank height
8Set bank offset
9payload=0: Disable warm boot
payload=16: Enable cold boot
payload=32: Enable warm boot

Use iceunpack -vv to display the commands as they are interpreted by the tool.

Note: The format itself seems to be very flexible. At the moment it is unclear what the FPGA devices will do when presented with a bitstream that use the commands in a different way than the bitstreams generated by the lattice tools.

Writing SRAM content

Most bytes in the bitstream are SRAM data bytes that should be written to the various SRAM banks in the FPGA. The following sequence is used to program an SRAM cell:

The bank width and height parameters reflect the width and height of the SRAM bank. A large SRAM can be written in smaller junks. In this case height parameter may be smaller and the offset parameter reflects the vertical start position.

There are four CRAM and four BRAM banks in an iCE40 FPGA. The different devices from the family use different widths and heights, but the same number of banks.

The CRAM banks hold the configuration bits for the FPGA fabric and hard IP blocks, the BRAM corresponds to the contents of the block ram resources.

The ordering of the data bits is in MSB first row-major order.

Organization of the CRAM

Mapping of tile config bits to 2D CRAM

The chip is organized into four quadrants. Each CRAM memory bank contains the configuration bits for one quadrant. The address 0 is always the corner of the quadrant, i.e. in one quadrant the bit addresses increase with the tile x/y coordinates, in another they increase with the tile x coordinate but decrease with the tile y coordinate, and so on.

For an iCE40 1k device, that has 12 x 16 tiles (not counting the io tiles), the CRAM bank 0 is the one containing the corner tile (1 1), the CRAM bank 1 contains the corner tile (1 16), the CRAM bank 2 contains the corner tile (12 1) and the CRAM bank 3 contains the corner tile (12 16). The entire CRAM of such a device is depicted on the right (bank 0 is in the lower left corner in blue/green).

The checkerboard pattern in the picture visualizes which bits are associated with which tile. The height of the configuration block is 16 for all tile types, but the width is different for each tile type. IO tiles have configurations that are 18 bits wide, LOGIC tiles are 54 bits wide, and RAM tiles are 42 bits wide. (Notice the two slightly smaller columns for the RAM tiles.)

The IO tiles on the top and bottom of the chip use a strange permutation pattern for their bits. It can be seen in the picture that their columns are spread out horizontally. What cannot be seen in the picture is the columns also are not in order and the bit positions are vertically permuted as well. The CramIndexConverter class in icepack.cc encapsulates the calculations that are necessary to convert between tile-relative bit addresses and CRAM bank-relative bit addresses.

The black pixels in the image correspond to CRAM bits that are not associated with any IO, LOGIC or RAM tile. Some of them are unused, others are used by hard IPs or other global resources. The iceunpack tool reports such bits, when set, with the ".extra_bit bank x y" statement in the ASCII output format.

Organization of the BRAM

This part of the documentation has not been written yet.

CRC Check

The CRC is a 16 bit CRC. The (truncated) polynomial is 0x1021 (CRC-16-CCITT). The "Reset CRC" command sets the CRC to 0xFFFF. No zero padding is performed.

fpga-icestorm-0~20160913git266e758/docs/index.html000066400000000000000000000553741276746530600213350ustar00rootroot00000000000000 Project IceStorm

Project IceStorm

2016-01-17: First release of IceTime timing analysis. Video: https://youtu.be/IG5CpFJRnOk
2015-12-27: Presentation of the IceStorm flow at 32C3 (Video on Youtube).
2015-07-19: Released support for 8k chips. Moved IceStorm source code to GitHub.
2015-05-27: We have a working fully Open Source flow with Yosys and Arachne-pnr! Video: http://youtu.be/yUiNlmvVOq8
2015-04-13: Complete rewrite of IceUnpack, added IcePack, some major documentation updates
2015-03-22: First public release and short YouTube video demonstrating our work: http://youtu.be/u1ZHcSNDQMM

What is Project IceStorm?

Project IceStorm aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. The IceStorm flow (Yosys, Arachne-pnr, and IceStorm) is a fully open source Verilog-to-Bitstream flow for iCE40 FPGAs.

The focus of the project is on the iCE40 LP/HX 1K/4K/8K chips. (Most of the work was done on HX1K-TQ144 and HX8K-CT256 parts.)

Why the Lattice iCE40?

It has a very minimalistic architecture with a very regular structure. There are not many different kinds of tiles or special function units. This makes it both ideal for reverse engineering and as a reference platform for general purpose FPGA tool development.

Also, with the Lattice iCEstick there is a cheap and easy to use development platform available, which makes the part interesting for all kinds of projects. (The iCEstick features an HX1K device. Lattice also sells an iCE40-HX8K Breakout Board featuring an HX8K chip.)

What is the Status of the Project?

We are pretty confident that we have the 1K and 8K devices completely reverse engineered. For example, it seems we can create correct functional Verilog models for all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 and the iCE40 HX8K-CT256 using our icebox_vlog tool.

Here is a list of currently supported parts and the corresponding options for arachne-pnr (place and route) and icetime (timing analysis):

PartPackagePin SpacingI/Osarachne-pnr optsicetime opts
iCE40-LP1K-SWG16TR16-ball WLCSP (1.40 x 1.48 mm)0.35 mm10-d 1k -P swg16tr-d lp1k
iCE40-LP1K-CM3636-ball ucBGA (2.5 x 2.5 mm)0.40 mm25-d 1k -P cm36-d lp1k
iCE40-LP1K-CM4949-ball ucBGA (3 x 3 mm)0.40 mm35-d 1k -P cm49-d lp1k
iCE40-LP1K-CM8181-ball ucBGA (4 x 4 mm)0.40 mm63-d 1k -P cm81-d lp1k
iCE40-LP4K-CM8181-ball ucBGA (4 x 4 mm)0.40 mm63-d 8k -P cm81:4k-d lp8k
iCE40-LP8K-CM8181-ball ucBGA (4 x 4 mm)0.40 mm63-d 8k -P cm81-d lp8k
iCE40-LP1K-CM121121-ball ucBGA (5 x 5 mm)0.40 mm95-d 1k -P cm121-d lp1k
iCE40-LP4K-CM121121-ball ucBGA (5 x 5 mm)0.40 mm93-d 8k -P cm121:4k-d lp8k
iCE40-LP8K-CM121121-ball ucBGA (5 x 5 mm)0.40 mm93-d 8k -P cm121-d lp8k
iCE40-LP4K-CM225225-ball ucBGA (7 x 7 mm)0.40 mm167-d 8k -P cm225:4k-d lp8k
iCE40-LP8K-CM225225-ball ucBGA (7 x 7 mm)0.40 mm178-d 8k -P cm225-d lp8k
iCE40-HX8K-CM225225-ball ucBGA (7 x 7 mm)0.40 mm178-d 8k -P cm225-d hx8k
iCE40-LP1K-QN8484-pin QFNS (7 x 7 mm)0.50 mm67-d 1k -P qn84-d lp1k
iCE40-LP1K-CB8181-ball csBGA (5 x 5 mm)0.50 mm62-d 1k -P cb81-d lp1k
iCE40-LP1K-CB121121-ball csBGA (6 x 6 mm)0.50 mm92-d 1k -P cb121-d lp1k
iCE40-HX1K-CB132132-ball csBGA (8 x 8 mm)0.50 mm95-d 1k -P cb132-d hx1k
iCE40-HX4K-CB132132-ball csBGA (8 x 8 mm)0.50 mm95-d 8k -P cb132:4k-d hx8k
iCE40-HX8K-CB132132-ball csBGA (8 x 8 mm)0.50 mm95-d 8k -P cb132-d hx8k
iCE40-HX1K-VQ100100-pin VQFP (14 x 14 mm)0.50 mm72-d 1k -P vq100-d hx1k
iCE40-HX1K-TQ144144-pin TQFP (20 x 20 mm)0.50 mm96-d 1k -P tq144-d hx1k
iCE40-HX4K-TQ144144-pin TQFP (20 x 20 mm)0.50 mm107-d 8k -P tq144:4k-d hx8k
iCE40-HX8K-CT256256-ball caBGA (14 x 14 mm)0.80 mm206-d 8k -P ct256-d hx8k

Current work focuses on further improving our timing analysis flow.

How do I use the Fully Open Source iCE40 Flow?

Synthesis for iCE40 FPGAs can be done with Yosys. Place-and-route can be done with arachne-pnr. Here is an example script for implementing and programming the rot example from arachne-pnr (this example targets the iCEstick development board): 

yosys -p "synth_ice40 -blif rot.blif" rot.v
arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc
icepack rot.asc rot.bin
iceprog rot.bin

A simple timing analysis report can be generated using the icetime utility: 

icetime -tmd hx1k rot.asc

Where are the Tools? How to install?

Installing prerequisites (this command is for Ubuntu 14.04): 

sudo apt-get install build-essential clang bison flex libreadline-dev \
                     gawk tcl-dev libffi-dev git mercurial graphviz   \
                     xdot pkg-config python python3 libftdi-dev

On Fedora 24 the following command installs all prerequisites: 

sudo dnf install make automake gcc gcc-c++ kernel-devel clang bison \
                 flex readline-devel gawk tcl-devel libffi-devel git mercurial \
                 graphviz python-xdot pkgconfig python python3 libftdi-devel

Installing the IceStorm Tools (icepack, icebox, iceprog, icetime, chip databases): 

git clone https://github.com/cliffordwolf/icestorm.git icestorm
cd icestorm
make -j$(nproc)
sudo make install

Installing Arachne-PNR (the place&route tool): 

git clone https://github.com/cseed/arachne-pnr.git arachne-pnr
cd arachne-pnr
make -j$(nproc)
sudo make install

Installing Yosys (Verilog synthesis): 

git clone https://github.com/cliffordwolf/yosys.git yosys
cd yosys
make -j$(nproc)
sudo make install

The Arachne-PNR build converts the IceStorm text chip databases into the arachne-pnr binary chip databases. Always rebuild Arachne-PNR after updating your IceStorm installation.

Notes for Linux: Create a file /etc/udev/rules.d/53-lattice-ftdi.rules with the following line in it to allow uploading bit-streams to a Lattice iCEstick and/or a Lattice iCE40-HX8K Breakout Board as unprivileged user: 

ACTION=="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6010", MODE:="666"

Notes for Archlinux: just install icestorm-git, arachne-pnr-git and yosys-git from the Arch User Repository (no need to follow the install instructions above).

Notes for OSX: Please follow the additional instructions for OSX to install on OSX.

Please file an issue on github if you have additional notes to share regarding the install procedures on the operating system of your choice.

What are the IceStorm Tools?

The IceStorm Tools are a couple of small programs for working with iCE40 bitstream files and our ASCII representation of it. The complete Open Source iCE40 Flow consists of the IceStorm Tools, Arachne-PNR, and Yosys.

IcePack/IceUnpack

The iceunpack program converts an iCE40 .bin file into the IceStorm ASCII format that has blocks of 0 and 1 for the config bits for each tile in the chip. The icepack program converts such an ASCII file back to an iCE40 .bin file. All other IceStorm Tools operate on the ASCII file format, not the bitstream binaries.

IceTime

The icetime program is an iCE40 timing analysis tool. It reads designs in IceStorm ASCII format and writes times timing netlists that can be used in external timing analysers. It also includes a simple topological timing analyser that can be used to create timing reports.

IceBox

A python library and various tools for working with IceStorm ASCII files and accessing the device database. For example icebox_vlog converts our ASCII file dump of a bitstream into a Verilog file that implements an equivalent circuit.

IceProg

A small driver program for the FTDI-based programmer used on the iCEstick and HX8K development boards.

IceMulti

A tool for packing multiple bitstream files into one iCE40 multiboot image file.

IcePLL

A small program for calculating iCE40 PLL configuration parameters.

IceBRAM

A small program for swapping the BRAM contents in IceStorm ASCII files. E.g. for changing the firmware image in a SoC design without re-running synthesis and place&route.

ChipDB

The IceStorm Makefile builds and installs two files: chipdb-1k.txt and chipdb-8k.txt. This files contain all the relevant information for arachne-pnr to place&route a design and create an IceStorm ASCII file for the placed and routed design.

IcePack/IceUnpack, IceBox, IceProg, IceTime, and IcePLL are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser. IceMulti is written by Marcus Comstedt.

Where do I get support or meet other IceStorm users?

If you have a question regarding the IceStorm flow, use the yosys tag on stackoverflow to ask your question. If your question is a general question about Verilog HDL design, please consider using the verilog tag on stackoverflow instead.

For general discussions go to the Yosys Subreddit or #yosys on freenode IRC.

If you have a bug report please file an issue on github. (IceStorm Issue Tracker, Yosys Issue Tracker, Arachne-PNR Issue Tracker)

Where is the Documentation?

Recommended reading: Lattice iCE40 LP/HX Family Datasheet, Lattice iCE Technology Library (Especially the three pages on "Architecture Overview", "PLB Blocks", "Routing", and "Clock/Control Distribution Network" in the Lattice iCE40 LP/HX Family Datasheet. Read that first, then come back here.)

The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.

The iceunpack program can be used to convert the bitstream into an ASCII file that has a block of 0 and 1 characters for each tile. For example: 

.logic_tile 12 12
000000000000000000000000000000000000000000000000000000
000000000000000000000011010000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001011000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000001000001000010101010000000000
000000000000000000000000000101010000101010100000000000

This bits are referred to as By[x] in the documentation. For example, B0 is the first line, B0[0] the first bit in the first line, and B15[53] the last bit in the last line.

The icebox_explain program can be used to turn this block of config bits into a description of the cell configuration: 

.logic_tile 12 12
LC_7 0101010110101010 0000
buffer local_g0_2 lutff_7/in_3
buffer local_g1_4 lutff_7/in_0
buffer sp12_h_r_18 local_g0_2
buffer sp12_h_r_20 local_g1_4

IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API to export this database into a format that fits the target application. See icebox_chipdb for an example program that does that.

The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm tool icebox_explain on the resulting bitstream files, and analyze the results using the HTML export of the database mentioned above. icebox_vlog can be used to convert the bitstream to Verilog. The output file of this tool will also outline the signal paths in comments added to the generated Verilog code.

For example, consider the following Verilog and PCF files: 

// example.v
module top (input a, b, output y);
  assign y = a & b;
endmodule

# example.pcf
set_io a 1
set_io b 10
set_io y 11

And run them through Yosys, Arachne-PNR and IcePack: 

$ yosys -p 'synth_ice40 -top top -blif example.blif' example.v
$ arachne-pnr -d 1k -o example.asc -p example.pcf example.blif
$ icepack example.asc example.bin

We would get something like the following icebox_explain output: 

$ icebox_explain example.asc
Reading file 'example.asc'..
Fabric size (without IO tiles): 12 x 16

.io_tile 0 10
IOB_1 PINTYPE_0
IOB_1 PINTYPE_3
IOB_1 PINTYPE_4
IoCtrl IE_0
IoCtrl IE_1
IoCtrl REN_0
buffer local_g0_5 io_1/D_OUT_0
buffer logic_op_tnr_5 local_g0_5

.io_tile 0 14
IOB_1 PINTYPE_0
IoCtrl IE_1
IoCtrl REN_0
buffer io_1/D_IN_0 span4_vert_b_6

.io_tile 0 11
IOB_0 PINTYPE_0
IoCtrl IE_0
IoCtrl REN_1
routing span4_vert_t_14 span4_horz_13

.logic_tile 1 11
LC_5 0001000000000000 0000
buffer local_g0_0 lutff_5/in_1
buffer local_g3_0 lutff_5/in_0
buffer neigh_op_lft_0 local_g0_0
buffer sp4_h_r_24 local_g3_0

And something like the following icebox_vlog output: 

$ icebox_vlog -p example.pcf example.asc
// Reading file 'example.asc'..

module chip (output y, input b, input a);

wire y;
// io_0_10_1
// (0, 10, 'io_1/D_OUT_0')
// (0, 10, 'io_1/PAD')
// (0, 10, 'local_g0_5')
// (0, 10, 'logic_op_tnr_5')
// (0, 11, 'logic_op_rgt_5')
// (0, 12, 'logic_op_bnr_5')
// (1, 10, 'neigh_op_top_5')
// (1, 11, 'lutff_5/out')
// (1, 12, 'neigh_op_bot_5')
// (2, 10, 'neigh_op_tnl_5')
// (2, 11, 'neigh_op_lft_5')
// (2, 12, 'neigh_op_bnl_5')

wire b;
// io_0_11_0
// (0, 11, 'io_0/D_IN_0')
// (0, 11, 'io_0/PAD')
// (1, 10, 'neigh_op_tnl_0')
// (1, 10, 'neigh_op_tnl_4')
// (1, 11, 'local_g0_0')
// (1, 11, 'lutff_5/in_1')
// (1, 11, 'neigh_op_lft_0')
// (1, 11, 'neigh_op_lft_4')
// (1, 12, 'neigh_op_bnl_0')
// (1, 12, 'neigh_op_bnl_4')

wire a;
// io_0_14_1
// (0, 11, 'span4_horz_13')
// (0, 11, 'span4_vert_t_14')
// (0, 12, 'span4_vert_b_14')
// (0, 13, 'span4_vert_b_10')
// (0, 14, 'io_1/D_IN_0')
// (0, 14, 'io_1/PAD')
// (0, 14, 'span4_vert_b_6')
// (0, 15, 'span4_vert_b_2')
// (1, 11, 'local_g3_0')
// (1, 11, 'lutff_5/in_0')
// (1, 11, 'sp4_h_r_24')
// (1, 13, 'neigh_op_tnl_2')
// (1, 13, 'neigh_op_tnl_6')
// (1, 14, 'neigh_op_lft_2')
// (1, 14, 'neigh_op_lft_6')
// (1, 15, 'neigh_op_bnl_2')
// (1, 15, 'neigh_op_bnl_6')
// (2, 11, 'sp4_h_r_37')
// (3, 11, 'sp4_h_l_37')

assign y = /* LUT    1 11  5 */ b ? a : 0;

endmodule

Links

Links to related projects. Contact me at clifford@clifford.at if you have an interesting and relevant link.

iCE40 Boards

Lectures and Tutorials

Other FPGA reverse engineering projects

In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/, e.g. using the following BibTeX code: 

@MISC{IceStorm,
	author = {Clifford Wolf and Mathias Lasser},
	title = {Project IceStorm},
	howpublished = "\url{http://www.clifford.at/icestorm/}"
}

Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.
Buy an iCEstick or iCE40-HX8K Breakout Board from Lattice and see what you can do with the tools and information provided here.

fpga-icestorm-0~20160913git266e758/docs/io_tile.html000066400000000000000000001103541276746530600216400ustar00rootroot00000000000000 Project IceStorm – IO Tile Documentation

Project IceStorm – IO Tile Documentation

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. This is work in progress.

Span-4 and Span-12 Wires

IO Tile Span-Wires

The image on the right shows the span-wires of a left (or right) io cell (click to enlarge).

A left/right io cell has 16 connections named span4_vert_t_0 to span4_vert_t_15 on its top edge and 16 connections named span4_vert_b_0 to span4_vert_b_15 on its bottom edge. The nets span4_vert_t_0 to span4_vert_t_11 are connected to span4_vert_b_4 to span4_vert_b_15. The span-4 and span-12 wires of the adjacent logic cell are connected to the nets span4_horz_0 to span4_horz_47 and span12_horz_0 to span12_horz_23.

A top/bottom io cell has 16 connections named span4_vert_l_0 to span4_vert_l_15 on its top edge and 16 connections named span4_vert_r_0 to span4_vert_r_15 on its bottom edge. The nets span4_vert_l_0 to span4_vert_l_11 are connected to span4_vert_r_4 to span4_vert_r_15. The span-4 and span-12 wires of the adjacent logic cell are connected to the nets span4_vert_0 to span4_vert_47 and span12_vert_0 to span12_vert_23.

The vertical span4 wires of left/right io cells are connected "around the corner" to the horizontal span4 wires of the top/bottom io cells. For example span4_vert_b_0 of IO cell (0 1) is connected to span4_horz_l_0 (span4_horz_r_4) of IO cell (1 0).

Note that unlike the span-wires connection LOGIC and RAM tiles, the span-wires connecting IO tiles to each other are not pairwise crossed out.

IO Blocks

Each IO tile contains two IO blocks. Each IO block essentially implements the SB_IO primitive from the Lattice iCE Technology Library. Some inputs are shared between the two IO blocks. The following table lists how the wires in the logic tile map to the SB_IO primitive ports:

SB_IO PortIO Block 0IO Block 1
D_IN_0io_0/D_IN_0io_1/D_IN_0
D_IN_1io_0/D_IN_1io_1/D_IN_1
D_OUT_0io_0/D_OUT_0io_1/D_OUT_0
D_OUT_1io_0/D_OUT_1io_1/D_OUT_1
OUTPUT_ENABLEio_0/OUT_ENBio_1/OUT_ENB
CLOCK_ENABLEio_global/cen
INPUT_CLKio_global/inclk
OUTPUT_CLKio_global/outclk
LATCH_INPUT_VALUEio_global/latch

Like the inputs to logic cells, the inputs to IO blocks are routed to the IO block via a two-stage process. A signal is first routed to one of 16 local tracks in the IO tile and then from the local track to the IO block.

The io_global/latch signal is shared among all IO tiles on an edge of the chip and is driven by fabout from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the io_global/latch signal are: (0, 7), (13, 10), (5, 0), and (8, 17)

A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four D_IN signals created by its two IO blocks. The D_IN signals map to logic function indices as follows:

Function IndexD_IN Wire
0io_0/D_IN_0
1io_0/D_IN_1
2io_1/D_IN_0
3io_1/D_IN_1
4io_0/D_IN_0
5io_0/D_IN_1
6io_1/D_IN_0
7io_1/D_IN_1

For example the signal io_1/D_IN_0 in IO tile (0, 5) can be seen as neigh_op_lft_2 and neigh_op_lft_6 in LOGIC tile (1, 5).

Each IO Tile has 2 NegClk configuration bits, suggesting that the clock signals can be inverted independently for the the two IO blocks in the tile. However, the Lattice tools refuse to pack two IO blocks with different clock polarity into the same IO tile. In our tests we only managed to either set or clear both NegClk bits.

Each IO block has two IoCtrl IE bits that enable the input buffers and two IoCtrl REN bits that enable the pull up resistors. Both bits are active low, i.e. an unused IO tile will have both IE bits set and both REN bits cleared (the default behavior is to enable pullup resistors on all unused pins). Note that icebox_explain.py will ignore all IO tiles that only have the two IoCtrl IE bits set.

However, the IoCtrl IE_0/IE_1 and IoCtrl REN_0/REN_1 do not necessarily configure the IO PIN that are connected to the IO block in the same tile, and if they do the numbers (0/1) do not necessarily match. As a general rule, the pins on the right and bottom side of the chips match up with the IO blocks and for the pins on the left and top side the numbers must be swapped. But in some cases the IO block and the set of IE/REN are not even located in the same tile. The following table lists the correlation between IO blocks and IE/REN bits for the 1K chip:

IO BlockIE/REN Block
0 14 10 14 0
0 14 00 14 1
0 13 10 13 0
0 13 00 13 1
0 12 10 12 0
0 12 00 12 1
0 11 10 11 0
0 11 00 11 1
0 10 10 10 0
0 10 00 10 1
0 9 10 9 0
0 9 00 9 1
0 8 10 8 0
0 8 00 8 1
0 6 10 6 0
0 6 00 6 1
0 5 10 5 0
0 5 00 5 1
0 4 10 4 0
0 4 00 4 1
0 3 10 3 0
0 3 00 3 1
0 2 10 2 0
0 2 00 2 1
IO BlockIE/REN Block
1 0 0 1 0 0
1 0 1 1 0 1
2 0 0 2 0 0
2 0 1 2 0 1
3 0 0 3 0 0
3 0 1 3 0 1
4 0 0 4 0 0
4 0 1 4 0 1
5 0 0 5 0 0
5 0 1 5 0 1
6 0 1 6 0 0
7 0 0 6 0 1
6 0 0 7 0 0
7 0 1 7 0 1
8 0 0 8 0 0
8 0 1 8 0 1
9 0 0 9 0 0
9 0 1 9 0 1
10 0 010 0 0
10 0 110 0 1
11 0 011 0 0
11 0 111 0 1
12 0 012 0 0
12 0 112 0 1
IO BlockIE/REN Block
13 1 013 1 0
13 1 113 1 1
13 2 013 2 0
13 2 113 2 1
13 3 113 3 1
13 4 013 4 0
13 4 113 4 1
13 6 013 6 0
13 6 113 6 1
13 7 013 7 0
13 7 113 7 1
13 8 013 8 0
13 8 113 8 1
13 9 013 9 0
13 9 113 9 1
13 11 013 10 0
13 11 113 10 1
13 12 013 11 0
13 12 113 11 1
13 13 013 13 0
13 13 113 13 1
13 14 013 14 0
13 14 113 14 1
13 15 013 15 0
13 15 113 15 1
IO BlockIE/REN Block
12 17 112 17 1
12 17 012 17 0
11 17 111 17 1
11 17 011 17 0
10 17 1 9 17 1
10 17 0 9 17 0
9 17 110 17 1
9 17 010 17 0
8 17 1 8 17 1
8 17 0 8 17 0
7 17 1 7 17 1
7 17 0 7 17 0
6 17 1 6 17 1
5 17 1 5 17 1
5 17 0 5 17 0
4 17 1 4 17 1
4 17 0 4 17 0
3 17 1 3 17 1
3 17 0 3 17 0
2 17 1 2 17 1
2 17 0 2 17 0
1 17 1 1 17 1
1 17 0 1 17 0

When an input pin pair is used as LVDS pair (IO standard SB_LVDS_INPUT, bank 3 / left edge only), then the four bits IoCtrl IE_0/IE_1 and IoCtrl REN_0/REN_1 are all set, as well as the IoCtrl LVDS bit.

In the iCE 8k devices the IoCtrl IE bits are active high. So an unused IO tile on an 8k chip has all bits cleared.

Global Nets

iCE40 FPGAs have 8 global nets. Each global net can be driven directly from an IO pin. In the FPGA bitstream, routing of external signals to global nets is not controlled by bits in the IO tile. Instead bits that do not belong to any tile are used. In IceBox nomenclature such bits are called "extra bits".

The following table lists which pins / IO blocks may be used to drive which global net, and what .extra statements in the IceStorm ASCII file format to represent the corresponding configuration bits:

Glb NetPin
(HX1K-TQ144)		IO Tile +
Block #		IceBox Statement
0 9313 8 1.extra_bit 0 330 142
1 21 0 8 1.extra_bit 0 331 142
2128 7 17 0.extra_bit 1 330 143
3 50 7 0 0.extra_bit 1 331 143
4 20 0 9 0.extra_bit 1 330 142
5 9413 9 0.extra_bit 1 331 142
6 49 6 0 1.extra_bit 0 330 143
7129 6 17 1.extra_bit 0 331 143

Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal to the fabout net on an IO tile. The same set of I/O tiles is used for this, but in this case each of the I/O tiles corresponds to a different global net:

Glb Net 0 1 2 3 4 5 6 7
IO Tile 7 0 7 17 13 9 0 9 6 17 6 0 0 8 13 8

Column Buffers

Column Buffer Control Bits

Each LOGIC, IO, and RAMB tile has 8 ColBufCtrl bits, one for each global net. In most tiles this bits have no function, but in tiles in rows 4, 5, 12, and 13 (for RAM columns: rows 3, 5, 11, and 13) this bits control which global nets are driven to the column of tiles below and/or above that tile (including that tile), as illustrated in the image to the right (click to enlarge).

In 8k chips the rows 8, 9, 24, and 25 contain the column buffers. 8k RAMB and RAMT tiles can control column buffers, so the pattern looks the same for RAM, LOGIC, and IO columns.

Warmboot

The SB_WARMBOOT primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell are driven by the fabout signal from three IO tiles. In HX1K chips the tiles connected to the SB_WARMBOOT primitive are:

Warmboot PinIO Tile
BOOT12 0
S013 1
S113 2

PLL Cores

The PLL primitives in iCE40 FPGAs are configured using the PLLCONFIG_* bits in the IO tiles. The configuration for a single PLL cell is spread out over many IO tiles. For example, the PLL cell in the 1K chip are configured as follows (bits listed from LSB to MSB):

IO TileConfig BitSB_PLL40_* Parameter
0 3PLLCONFIG_5Select PLL Type:
000 = DISABLED
010 = SB_PLL40_PAD
100 = SB_PLL40_2_PAD
110 = SB_PLL40_2F_PAD
011 = SB_PLL40_CORE
111 = SB_PLL40_2F_CORE
0 5PLLCONFIG_1
0 5PLLCONFIG_3
0 5PLLCONFIG_5FEEDBACK_PATH
000 = "DELAY"
001 = "SIMPLE"
010 = "PHASE_AND_DELAY"
110 = "EXTERNAL"
0 2PLLCONFIG_9
0 3PLLCONFIG_1
0 4PLLCONFIG_4DELAY_ADJUSTMENT_MODE_FEEDBACK
0 = "FIXED"
1 = "DYNAMIC"
0 4PLLCONFIG_9DELAY_ADJUSTMENT_MODE_RELATIVE
0 = "FIXED"
1 = "DYNAMIC"
0 3PLLCONFIG_6PLLOUT_SELECT
PLLOUT_SELECT_PORTA
00 = "GENCLK"
01 = "GENCLK_HALF"
10 = "SHIFTREG_90deg"
11 = "SHIFTREG_0deg"
0 3PLLCONFIG_7
0 3PLLCONFIG_2PLLOUT_SELECT_PORTB
00 = "GENCLK"
01 = "GENCLK_HALF"
10 = "SHIFTREG_90deg"
11 = "SHIFTREG_0deg"
0 3PLLCONFIG_3
0 3PLLCONFIG_4SHIFTREG_DIV_MODE
0 3PLLCONFIG_8TEST_MODE
IO TileConfig BitSB_PLL40_* Parameter
0 3PLLCONFIG_9FDA_FEEDBACK
0 4PLLCONFIG_1
0 4PLLCONFIG_2
0 4PLLCONFIG_3
0 5PLLCONFIG_5FDA_RELATIVE
0 4PLLCONFIG_6
0 4PLLCONFIG_7
0 4PLLCONFIG_8
0 1PLLCONFIG_1DIVR
0 1PLLCONFIG_2
0 1PLLCONFIG_3
0 1PLLCONFIG_4
0 1PLLCONFIG_5DIVF
0 1PLLCONFIG_6
0 1PLLCONFIG_7
0 1PLLCONFIG_8
0 1PLLCONFIG_9
0 2PLLCONFIG_1
0 2PLLCONFIG_2
0 2PLLCONFIG_3DIVQ
0 2PLLCONFIG_4
0 2PLLCONFIG_5
0 2PLLCONFIG_6FILTER_RANGE
0 2PLLCONFIG_7
0 2PLLCONFIG_8

The PLL inputs are routed to the PLL via the fabout signal from various IO tiles. The non-clock PLL outputs are routed via otherwise unused neigh_op_* signals in fabric corners. For example in case of the 1k chip:

TileNet-SegmentSB_PLL40_* Port Name
0 1faboutREFERENCECLK
0 2faboutEXTFEEDBACK
0 4faboutDYNAMICDELAY
0 5fabout
0 6fabout
0 10fabout
0 11fabout
0 12fabout
0 13fabout
0 14fabout
1 1neigh_op_bnl_1LOCK
1 0faboutBYPASS
2 0faboutRESETB
5 0faboutLATCHINPUTVALUE
12 1neigh_op_bnl_1SDO
4 0faboutSDI
5 0faboutSCLK

The PLL clock outputs are fed directly into the input path of certain IO tiles. In case of the 1k chip the PORTA clock is fed into PIO 1 of IO Tile (6 0) and the PORTB clock is fed into PIO 0 of IO Tile (7 0). Because of this, those two PIOs can only be used as output Pins by the FPGA fabric when the PLL ports are being used.

fpga-icestorm-0~20160913git266e758/docs/iosp.svg000066400000000000000000001545661276746530600210360ustar00rootroot00000000000000 image/svg+xml span4_vert_t_0 span4_vert_t_1 span4_vert_t_2 span4_vert_t_4 span4_vert_t_5 span4_vert_t_6 span4_vert_t_7 span4_vert_t_8 span4_vert_t_9 span4_vert_t_13 span4_vert_t_10 span4_vert_t_11 span4_vert_t_12 span4_vert_t_3 span4_vert_t_14 span4_vert_t_15 span4_vert_b_0 span4_vert_b_1 span4_vert_b_2 span4_vert_b_3 span4_vert_b_4 span4_vert_b_5 span4_vert_b_6 span4_vert_b_7 span4_vert_b_8 span4_vert_b_9 span4_vert_b_10 span4_vert_b_11 span4_vert_b_12 span4_vert_b_13 span4_vert_b_14 span4_vert_b_15 span4_horz_0 .. span4_horz_47 span12_horz_0 .. span12_horz_23 fpga-icestorm-0~20160913git266e758/docs/logic_tile.html000066400000000000000000001026341276746530600223300ustar00rootroot00000000000000 Project IceStorm – LOGIC Tile Documentation

Project IceStorm – LOGIC Tile Documentation

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. This is work in progress.

Span-4 and Span-12 Wires

The span-4 and span-12 wires are the main interconnect resource in iCE40 FPGAs. They "span" (have a length of) 4 or 12 cells in horizontal or vertical direction.

The bits marked routing in the bitstream do enable switches (transfer gates) that can be used to connect wire segments bidirectionally to each other in order to create larger segments. The bits marked buffer in the bitstream enable tristate buffers that drive the signal in one direction from one wire to another. Both types of bits exist for routing between span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details.

Only directional tristate buffers are used to route signals between the span-wires and the logic cells.

Span-4 Horizontal

Span-4 Horizontal

The image on the right shows the horizontal span-4 wires of a logic or ram cell (click to enlarge).

On the left side of the cell there are 48 connections named sp4_h_l_0 to sp4_h_l_47. The lower 36 of those wires are connected to sp4_h_r_12 to sp4_h_r_47 on the right side of the cell. (IceStorm normalizes this wire names to sp4_h_r_0 to sp4_h_r_35. Note: the Lattice tools use a different normalization scheme for this wire names.) The wires connecting the left and right horizontal span-4 ports are pairwise crossed-out.

The wires sp4_h_l_36 to sp4_h_l_47 terminate in the cell, so do the wires sp4_h_r_0 to sp4_h_r_11.

This wires "span" 4 cells, i.e. they connect 5 cells if you count the cells on both ends of the wire.

For example, the wire sp4_h_r_0 in cell (x, y) has the following names:

Cell Coordinatessp4_h_l_* wire namesp4_h_r_* wire name
x, y-sp4_h_r_0
x+1, ysp4_h_l_0sp4_h_r_13
x+2, ysp4_h_l_13sp4_h_r_24
x+3, ysp4_h_l_24sp4_h_r_37
x+4, ysp4_h_l_37-

Span-4 Vertical

Span-4 Vertical

The image on the right shows the vertical span-4 wires of a logic or ram cell (click to enlarge).

Similar to the horizontal span-4 wires there are 48 connections on the top (sp4_v_t_0 to sp4_v_t_47) and 48 connections on the bottom (sp4_v_b_0 to sp4_v_b_47). The wires sp4_v_t_0 to sp4_v_t_35 are connected to sp4_v_b_12 to sp4_v_b_47 (with pairwise crossing out). Wire names are normalized to sp4_v_b_12 to sp4_v_b_47.

But in addition to that, each cell also has access to sp4_v_b_0 to sp4_v_b_47 of its right neighbour. This are the wires sp4_r_v_b_0 to sp4_r_v_b_47. So over all a single vertical span-4 wire connects 9 cells. For example, the wire sp4_v_b_0 in cell (x, y) has the following names:

Cell Coordinatessp4_v_t_* wire namesp4_v_b_* wire namesp4_r_v_b_* wire name
x, y-sp4_v_b_0-
x, y-1sp4_v_t_0sp4_v_b_13-
x, y-2sp4_v_t_13sp4_v_b_24-
x, y-3sp4_v_t_24sp4_v_b_37-
x, y-4sp4_v_t_37--
x-1, y--sp4_r_v_b_0
x-1, y-1--sp4_r_v_b_13
x-1, y-2--sp4_r_v_b_24
x-1, y-3--sp4_r_v_b_37

Span-12 Horizontal and Vertical

Similar to the span-4 wires there are also longer horizontal and vertical span-12 wires.

There are 24 connections sp12_v_t_0 to sp12_v_t_23 on the top of the cell and 24 connections sp12_v_b_0 to sp12_v_b_23 on the bottom of the cell. The wires sp12_v_t_0 to sp12_v_t_21 are connected to sp12_v_b_2 to sp12_v_b_23 (with pairwise crossing out). The connections sp12_v_b_0, sp12_v_b_1, sp12_v_t_22, and sp12_v_t_23 terminate in the cell. Wire names are normalized to sp12_v_b_2 to sp12_v_b_23.

There are also 24 connections sp12_h_l_0 to sp12_h_l_23 on the left of the cell and 24 connections sp12_h_r_0 to sp12_h_r_23 on the right of the cell. The wires sp12_h_l_0 to sp12_h_l_21 are connected to sp12_h_r_2 to sp12_h_r_23 (with pairwise crossing out). The connections sp12_h_r_0, sp12_h_r_1, sp12_h_l_22, and sp12_h_l_23 terminate in the cell. Wire names are normalized to sp12_v_r_2 to sp12_h_r_23.

Local Tracks

The local tracks are the gateway to the logic cell inputs. Signals from the span-wires and the logic cell outputs of the eight neighbour cells can be routed to the local tracks and signals from the local tracks can be routed to the logic cell inputs.

Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires each: local_g0_0 to local_g3_7.

The span wires, global signals, and neighbour outputs can be routed to the local tracks. But not every of those signals can be routed to every of the local tracks. Instead there is a different mix of 16 signals for each local track.

The buffer driving the local track has 5 configuration bits. One enable bit and 4 bits that select the input wire. For example for local_g0_0 (copy&paste from the bitstream doku):

B0[14]B1[14]B1[15]B1[16] B1[17] FunctionSource-NetDestination-Net
00001buffersp4_r_v_b_24local_g0_0
00011buffersp12_h_r_8local_g0_0
00101bufferneigh_op_bot_0local_g0_0
00111buffersp4_v_b_16local_g0_0
01001buffersp4_r_v_b_35local_g0_0
01011buffersp12_h_r_16local_g0_0
01101bufferneigh_op_top_0local_g0_0
01111buffersp4_h_r_0local_g0_0
10001bufferlutff_0/outlocal_g0_0
10011buffersp4_v_b_0local_g0_0
10101bufferneigh_op_lft_0local_g0_0
10111buffersp4_h_r_8local_g0_0
11001bufferneigh_op_bnr_0local_g0_0
11011buffersp4_v_b_8local_g0_0
11101buffersp12_h_r_0local_g0_0
11111buffersp4_h_r_16local_g0_0

Then the signals on the local tracks can be routed to the input pins of the logic cells. Like before, not every local track can be routed to every logic cell input pin. Instead there is a different mix of 16 local track for each logic cell input. For example for lutff_0/in_0:

B0[26]B1[26]B1[27]B1[28]B1[29] FunctionSource-NetDestination-Net
00001bufferlocal_g0_0lutff_0/in_0
00011bufferlocal_g2_0lutff_0/in_0
00101bufferlocal_g1_1lutff_0/in_0
00111bufferlocal_g3_1lutff_0/in_0
01001bufferlocal_g0_2lutff_0/in_0
01011bufferlocal_g2_2lutff_0/in_0
01101bufferlocal_g1_3lutff_0/in_0
01111bufferlocal_g3_3lutff_0/in_0
10001bufferlocal_g0_4lutff_0/in_0
10011bufferlocal_g2_4lutff_0/in_0
10101bufferlocal_g1_5lutff_0/in_0
10111bufferlocal_g3_5lutff_0/in_0
11001bufferlocal_g0_6lutff_0/in_0
11011bufferlocal_g2_6lutff_0/in_0
11101bufferlocal_g1_7lutff_0/in_0
11111bufferlocal_g3_7lutff_0/in_0

The 8 global nets on the iCE40 can be routed to the local track via the glb2local_0 to glb2local_3 nets using a similar two-stage process. The logic block clock-enable and set-reset inputs can be driven directly from one of 4 global nets or from one of 4 local tracks. The logic block clock input can be driven from any of the global nets and from a few local tracks. See the bitstream documentation for details.

Logic Block

Each logic tile has a logic block containing 8 logic cells. Each logic cell contains a 4-input LUT, a carry unit and a flip-flop. Clock, clock enable, and set/reset inputs are shared along the 8 logic cells. So is the bit that configures positive/negative edge for the flip flops. But the three configuration bits that specify if the flip flop should be used, if it is set or reset by the set/reset input, and if the set/reset is synchronous or asynchronous exist for each logic cell individually.

Each LUT i has four input wires lutff_i/in_0 to lutff_i/in_3. Input lutff_i/in_3 can be configured to be driven by the carry output of the previous logic cell, or by carry_in_mux in case of i=0. Input lutff_i/in_2 can be configured to be driven by the output of the previous LUT for i>0 (LUT cascade). The LUT uses its 4 input signals to calculate lutff_i/lout. The signal is then passed through the built-in FF and becomes lutff_i/out. With the exception of LUT cascades, only the signal after the FF is visible from outside the logic block.

The carry unit calculates lutff_i/cout = lutff_i/in_1 + lutff_i/in_2 + lutff_(i-1)/cout > 1. In case of i=0, carry_in_mux is used as third input. carry_in_mux can be configured to be constant 0, 1 or the lutff_7/cout signal from the logic tile below.

Part of the functionality described above is documented as part of the routing bitstream documentation (see the buffers for lutff_ inputs). The NegClk bit switches all 8 FFs in the tile to negative edge mode. The CarryInSet bit drives the carry_in_mux high (it defaults to low when not driven via the buffer from carry_in).

The remaining functions of the logic cell are configured via the LC_i bits. This are 20 bit per logic cell. We have arbitrarily labeled those bits as follows:

LabelLC_0LC_1LC_2LC_3LC_4LC_5LC_6LC_7
LC_i[0]B0[36]B2[36]B4[36]B6[36]B8[36]B10[36]B12[36]B14[36]
LC_i[1]B0[37]B2[37]B4[37]B6[37]B8[37]B10[37]B12[37]B14[37]
LC_i[2]B0[38]B2[38]B4[38]B6[38]B8[38]B10[38]B12[38]B14[38]
LC_i[3]B0[39]B2[39]B4[39]B6[39]B8[39]B10[39]B12[39]B14[39]
LC_i[4]B0[40]B2[40]B4[40]B6[40]B8[40]B10[40]B12[40]B14[40]
LC_i[5]B0[41]B2[41]B4[41]B6[41]B8[41]B10[41]B12[41]B14[41]
LC_i[6]B0[42]B2[42]B4[42]B6[42]B8[42]B10[42]B12[42]B14[42]
LC_i[7]B0[43]B2[43]B4[43]B6[43]B8[43]B10[43]B12[43]B14[43]
LC_i[8]B0[44]B2[44]B4[44]B6[44]B8[44]B10[44]B12[44]B14[44]
LC_i[9]B0[45]B2[45]B4[45]B6[45]B8[45]B10[45]B12[45]B14[45]
LC_i[10]B1[36]B3[36]B5[36]B7[36]B9[36]B11[36]B13[36]B15[36]
LC_i[11]B1[37]B3[37]B5[37]B7[37]B9[37]B11[37]B13[37]B15[37]
LC_i[12]B1[38]B3[38]B5[38]B7[38]B9[38]B11[38]B13[38]B15[38]
LC_i[13]B1[39]B3[39]B5[39]B7[39]B9[39]B11[39]B13[39]B15[39]
LC_i[14]B1[40]B3[40]B5[40]B7[40]B9[40]B11[40]B13[40]B15[40]
LC_i[15]B1[41]B3[41]B5[41]B7[41]B9[41]B11[41]B13[41]B15[41]
LC_i[16]B1[42]B3[42]B5[42]B7[42]B9[42]B11[42]B13[42]B15[42]
LC_i[17]B1[43]B3[43]B5[43]B7[43]B9[43]B11[43]B13[43]B15[43]
LC_i[18]B1[44]B3[44]B5[44]B7[44]B9[44]B11[44]B13[44]B15[44]
LC_i[19]B1[45]B3[45]B5[45]B7[45]B9[45]B11[45]B13[45]B15[45]

LC_i[8] is the CarryEnable bit. This bit must be set if the carry logic is used.

LC_i[9] is the DffEnable bit. It enables the output flip-flop for the LUT.

LC_i[18] is the Set_NoReset bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.

LC_i[19] is the AsyncSetReset bit. When this bit is set then the set/reset signal is asynchronous to the clock.

The LUT implements the following truth table:

in_3in_2in_1in_0lout
0000LC_i[4]
0001LC_i[14]
0010LC_i[15]
0011LC_i[5]
0100LC_i[6]
0101LC_i[16]
0110LC_i[17]
0111LC_i[7]
1000LC_i[3]
1001LC_i[13]
1010LC_i[12]
1011LC_i[2]
1100LC_i[1]
1101LC_i[11]
1110LC_i[10]
1111LC_i[0]

LUT inputs that are not connected to anything are driven low. The set/reset signal is also driven low if not connected to any other driver, and the clock enable signal is driven high when left unconnected.

fpga-icestorm-0~20160913git266e758/docs/notes_osx.html000066400000000000000000000045311276746530600222340ustar00rootroot00000000000000 Project IceStorm – Notes for Installing on OSX

Project IceStorm – Notes for Installing on OSX

The toolchain should be easy to install on OSX platforms. Below are a few troubleshooting items found on Mountain Lion (10.8.2).

Installing FTDI Library

The libftdi package (.so lib binary and the ftdi.h header) has been renamed to libftdi0, so either do:

iceprog make error on "ftdi.h not found"

Note that Mac Ports installs to /opt instead of /usr, so change the first two lines in iceprog/Makefile to: 

LDLIBS = -L/usr/local/lib -L/opt/local/lib -lftdi -lm
CFLAGS = -MD -O0 -ggdb -Wall -std=c99 -I/usr/local/include -I/opt/local/include/

Basically you are indicating where to find the lib with -L/opt/local/lib and where to find the .h with -I/opt/local/include/.

yosys make error on "<tuple> not found"

This is a compiler issue, i.e., you are probably running on clang and you can circumvent this error by compiling against another compiler. Edit the Makefile of yosys and replace the two first lines for this, i.e., comment the first line (clang) and uncomment the second (gcc): 

#CONFIG := clang
CONFIG := gcc

error "Can't find iCE FTDI USB device (vedor_id 0x0403, device_id 0x6010)." while uploading code to FPGA (e.g., "iceprog example.bin")

You need to unload the FTDI driver. (notes below are from Mountain Lion, 10.8.2). First check if it is running: 

kextstat | grep FTDIUSBSerialDriver

If you see if on the kextstat, we need to unload it: 

sudo kextunload -b com.FTDI.driver.FTDIUSBSerialDriver`

Repeat the kextstat command and check that the driver was successfully unloaded.

Try running iceprog example.bin again. It should be working now.

Note: On newer OSes perhaps you need to also kextunload the com.apple.driver.AppleUSBFTDI driver.

fpga-icestorm-0~20160913git266e758/docs/ram_tile.html000066400000000000000000000137561276746530600220200ustar00rootroot00000000000000 Project IceStorm – RAM Tile Documentation

Project IceStorm – RAM Tile Documentation

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. This is work in progress.

Span-4 and Span-12 Wires

Regarding the Span-4 and Span-12 Wires a RAM tile behaves exactly like a LOGIC tile. So for simple applications that do not need the block ram resources, the RAM tiles can be handled like a LOGIC tiles without logic cells in them.

Block RAM Resources

A pair or RAM tiles (odd and even y-coordinates) provides an interface to a block ram cell. Like with LOGIC tiles, signals entering the RAM tile have to be routed over local tracks to the block ram inputs. Tiles with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles with even y-coordinates are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a SB_RAM40_4K cell. The cell ports are spread out over the two tiles as follows:

SB_RAM40_4KRAMB TileRAMT Tile
RDATA[15:0]RDATA[7:0]RDATA[15:8]
RADDR[10:0]-RADDR[10:0]
WADDR[10:0]WADDR[10:0]-
MASK[15:0]MASK[7:0]MASK[15:8]
WDATA[15:0]WDATA[7:0]WDATA[15:8]
RCLKE-RCLKE
RCLK-RCLK
RE-RE
WCLKEWCLKE-
WCLKWCLK-
WEWE-

The configuration bit RamConfig PowerUp in the RAMB tile enables the memory. This bit is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that icebox_explain.py will ignore all RAMB tiles that only have the RamConfig PowerUp bit set.

In 8k chips the RamConfig PowerUp bit is active-high. So an unused RAM block has all bits cleared in the 8k config bitstream.

The RamConfig CBIT_* bits in the RAMT tile configure the read/write width of the memory. Those bits map to the SB_RAM40_4K cell parameters as follows:

SB_RAM40_4KRAMT Config Bit
WRITE_MODE[0]RamConfig CBIT_0
WRITE_MODE[1]RamConfig CBIT_1
READ_MODE[0]RamConfig CBIT_2
READ_MODE[1]RamConfig CBIT_3

The read/write mode selects the width of the read/write port:

MODEDATA WidthUsed WDATA/RDATA Bits
01615, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
1814, 12, 10, 8, 6, 4, 2, 0
2413, 9, 5, 1
3211, 3

The NegClk bit in the RAMB tile negates the polarity of the WCLK port, and the NegClk bit in the RAMT tile negates the polarity of the RCLK port.

A logic tile sends the output of its eight logic cells to its neighbour tiles. A RAM tile does the same thing with the RDATA outputs. Each RAMB tile exports its RDATA[7:0] outputs and each RAMT tile exports its RDATA[15:8] outputs via this mechanism.

fpga-icestorm-0~20160913git266e758/docs/sp4h.svg000066400000000000000000002624201276746530600207270ustar00rootroot00000000000000 image/svg+xml sp4_l_47 sp4_l_46 sp4_l_45 sp4_l_44 sp4_l_43 sp4_l_42 sp4_l_41 sp4_l_40 sp4_l_39 sp4_l_38 sp4_l_37 sp4_l_36 sp4_l_35 sp4_l_34 sp4_l_33 sp4_l_32 sp4_l_31 sp4_l_30 sp4_l_29 sp4_l_28 sp4_l_27 sp4_l_26 sp4_l_25 sp4_l_24 sp4_l_23 sp4_l_22 sp4_l_21 sp4_l_20 sp4_l_19 sp4_l_18 sp4_l_17 sp4_l_16 sp4_l_15 sp4_l_14 sp4_l_13 sp4_l_12 sp4_l_11 sp4_l_10 sp4_l_9 sp4_l_8 sp4_l_7 sp4_l_6 sp4_l_5 sp4_l_4 sp4_l_3 sp4_l_2 sp4_l_1 sp4_l_0 sp4_r_47 sp4_r_46 sp4_r_45 sp4_r_44 sp4_r_43 sp4_r_42 sp4_r_41 sp4_r_40 sp4_r_39 sp4_r_38 sp4_r_37 sp4_r_36 sp4_r_35 sp4_r_34 sp4_r_33 sp4_r_32 sp4_r_31 sp4_r_30 sp4_r_29 sp4_r_28 sp4_r_27 sp4_r_26 sp4_r_25 sp4_r_24 sp4_r_23 sp4_r_22 sp4_r_21 sp4_r_20 sp4_r_19 sp4_r_18 sp4_r_17 sp4_r_16 sp4_r_15 sp4_r_14 sp4_r_13 sp4_r_12 sp4_r_11 sp4_r_10 sp4_r_9 sp4_r_8 sp4_r_7 sp4_r_6 sp4_r_5 sp4_r_4 sp4_r_3 sp4_r_2 sp4_r_1 sp4_r_0 fpga-icestorm-0~20160913git266e758/docs/sp4v.svg000066400000000000000000005324341276746530600207520ustar00rootroot00000000000000 image/svg+xml sp4_v_t_1 sp4_v_t_0 sp4_v_t_3 sp4_v_t_2 sp4_v_t_5 sp4_v_t_4 sp4_v_t_7 sp4_v_t_6 sp4_v_t_9 sp4_v_t_8 sp4_v_t_11 sp4_v_t_10 sp4_v_t_13 sp4_v_t_12 sp4_v_t_15 sp4_v_t_14 sp4_v_t_17 sp4_v_t_15 sp4_v_t_19 sp4_v_t_18 sp4_v_t_21 sp4_v_t_20 sp4_v_t_23 sp4_v_t_22 sp4_v_t_25 sp4_v_t_24 sp4_v_t_27 sp4_v_t_26 sp4_v_t_29 sp4_v_t_28 sp4_v_t_31 sp4_v_t_30 sp4_v_t_33 sp4_v_t_32 sp4_v_t_35 sp4_v_t_34 sp4_v_t_37 sp4_v_t_36 sp4_v_t_39 sp4_v_t_38 sp4_v_t_41 sp4_v_t_40 sp4_v_t_43 sp4_v_t_42 sp4_v_t_45 sp4_v_t_44 sp4_v_t_47 sp4_v_t_46 sp4_v_b_1 sp4_v_b_0 sp4_v_b_3 sp4_v_b_2 sp4_v_b_5 sp4_v_b_4 sp4_v_b_7 sp4_v_b_6 sp4_v_b_9 sp4_v_b_8 sp4_v_b_11 sp4_v_b_10 sp4_v_b_13 sp4_v_b_12 sp4_v_b_15 sp4_v_b_14 sp4_v_b_17 sp4_v_b_15 sp4_v_b_19 sp4_v_b_18 sp4_v_b_21 sp4_v_b_20 sp4_v_b_23 sp4_v_b_22 sp4_v_b_25 sp4_v_b_24 sp4_v_b_27 sp4_v_b_26 sp4_v_b_29 sp4_v_b_28 sp4_v_b_31 sp4_v_b_30 sp4_v_b_33 sp4_v_b_32 sp4_v_b_35 sp4_v_b_34 sp4_v_b_37 sp4_v_b_36 sp4_r_v_b_0 ... sp4_r_v_b_11 sp4_r_v_b_12 ... sp4_r_v_b_23 sp4_r_v_b_24 ... sp4_r_v_b_35 sp4_r_v_b_36 ... sp4_r_v_b_47 sp4_v_b_39 sp4_v_b_38 sp4_v_b_41 sp4_v_b_40 sp4_v_b_43 sp4_v_b_42 sp4_v_b_45 sp4_v_b_44 sp4_v_b_47 sp4_v_b_46 fpga-icestorm-0~20160913git266e758/examples/000077500000000000000000000000001276746530600202105ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/examples/hx8kboard/000077500000000000000000000000001276746530600221025ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/examples/hx8kboard/.gitignore000066400000000000000000000000611276746530600240670ustar00rootroot00000000000000example.bin example.blif example.asc example.rpt fpga-icestorm-0~20160913git266e758/examples/hx8kboard/Makefile000066400000000000000000000010021276746530600235330ustar00rootroot00000000000000PROJ = example PIN_DEF = hx8kboard.pcf DEVICE = hx8k all: $(PROJ).rpt $(PROJ).bin %.blif: %.v yosys -p 'synth_ice40 -top top -blif $@' $< %.asc: $(PIN_DEF) %.blif arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ %.bin: %.asc icepack $< $@ %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< prog: $(PROJ).bin iceprog $< sudo-prog: $(PROJ).bin @echo 'Executing prog as root!!!' sudo iceprog $< clean: rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin .SECONDARY: .PHONY: all prog clean fpga-icestorm-0~20160913git266e758/examples/hx8kboard/example.v000066400000000000000000000006731276746530600237320ustar00rootroot00000000000000module top ( input clk, output LED0, output LED1, output LED2, output LED3, output LED4, output LED5, output LED6, output LED7 ); localparam BITS = 8; localparam LOG2DELAY = 22; reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; always@(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end assign {LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7} = outcnt ^ (outcnt >> 1); endmodule fpga-icestorm-0~20160913git266e758/examples/hx8kboard/hx8kboard.pcf000066400000000000000000000002171276746530600244660ustar00rootroot00000000000000set_io LED0 B5 set_io LED1 B4 set_io LED2 A2 set_io LED3 A1 set_io LED4 C5 set_io LED5 C4 set_io LED6 B3 set_io LED7 C3 set_io clk J3 fpga-icestorm-0~20160913git266e758/examples/iceblink/000077500000000000000000000000001276746530600217705ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/examples/iceblink/.gitignore000066400000000000000000000000611276746530600237550ustar00rootroot00000000000000example.bin example.blif example.asc example.rpt fpga-icestorm-0~20160913git266e758/examples/iceblink/Makefile000066400000000000000000000010111276746530600234210ustar00rootroot00000000000000PROJ = example PIN_DEF = iceblink.pcf DEVICE = hx1k all: $(PROJ).rpt $(PROJ).bin %.blif: %.v yosys -p 'synth_ice40 -top top -blif $@' $< %.asc: $(PIN_DEF) %.blif arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P vq100 %.bin: %.asc icepack $< $@ %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< prog: $(PROJ).bin iCEburn.py -e -v -w $< sudo-prog: $(PROJ).bin @echo 'Executing prog as root!!!' iCEburn.py -e -v -w $< clean: rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin .PHONY: all prog clean fpga-icestorm-0~20160913git266e758/examples/iceblink/README000066400000000000000000000006011276746530600226450ustar00rootroot00000000000000Note, there are at least two similar looking versions of the iCEblink40 evaluation board: -iCEblink40-HX1K -iCEblink40-LP1K This example assumes the iCEblink40-HX1K board. The iCEblink40 boards have an on-board programmer with USB interface from Digilent. You need iCEburn to program the FPGA via this interface (or the original vendor tools). https://github.com/davidcarne/iceBurn fpga-icestorm-0~20160913git266e758/examples/iceblink/example.v000066400000000000000000000007121276746530600236120ustar00rootroot00000000000000/* Binary counter displayed on LEDs (the 4 green ones on the right). * Changes value about once a second. */ module top ( input clk, output LED2, output LED3, output LED4, output LED5 ); localparam BITS = 4; localparam LOG2DELAY = 22; reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; always@(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end assign {LED2, LED3, LED4, LED5} = outcnt; endmodule fpga-icestorm-0~20160913git266e758/examples/iceblink/iceblink.pcf000066400000000000000000000001171276746530600242410ustar00rootroot00000000000000set_io LED2 59 set_io LED3 56 set_io LED4 53 set_io LED5 51 set_io clk 13 fpga-icestorm-0~20160913git266e758/examples/icestick/000077500000000000000000000000001276746530600220065ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/examples/icestick/.gitignore000066400000000000000000000000611276746530600237730ustar00rootroot00000000000000example.bin example.blif example.asc example.rpt fpga-icestorm-0~20160913git266e758/examples/icestick/Makefile000066400000000000000000000010011276746530600234360ustar00rootroot00000000000000PROJ = example PIN_DEF = icestick.pcf DEVICE = hx1k all: $(PROJ).rpt $(PROJ).bin %.blif: %.v yosys -p 'synth_ice40 -top top -blif $@' $< %.asc: $(PIN_DEF) %.blif arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ %.bin: %.asc icepack $< $@ %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< prog: $(PROJ).bin iceprog $< sudo-prog: $(PROJ).bin @echo 'Executing prog as root!!!' sudo iceprog $< clean: rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin .SECONDARY: .PHONY: all prog clean fpga-icestorm-0~20160913git266e758/examples/icestick/example.v000066400000000000000000000005771276746530600236410ustar00rootroot00000000000000module top ( input clk, output LED1, output LED2, output LED3, output LED4, output LED5 ); localparam BITS = 5; localparam LOG2DELAY = 22; reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; always@(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1); endmodule fpga-icestorm-0~20160913git266e758/examples/icestick/icestick.pcf000066400000000000000000000001371276746530600242770ustar00rootroot00000000000000set_io LED1 99 set_io LED2 98 set_io LED3 97 set_io LED4 96 set_io LED5 95 set_io clk 21 fpga-icestorm-0~20160913git266e758/icebox/000077500000000000000000000000001276746530600176435ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icebox/.gitignore000066400000000000000000000000501276746530600216260ustar00rootroot00000000000000chipdb-1k.txt chipdb-8k.txt __pycache__ fpga-icestorm-0~20160913git266e758/icebox/Makefile000066400000000000000000000032571276746530600213120ustar00rootroot00000000000000include ../config.mk all: chipdb-1k.txt chipdb-8k.txt chipdb-1k.txt: icebox.py iceboxdb.py icebox_chipdb.py python3 icebox_chipdb.py > chipdb-1k.new mv chipdb-1k.new chipdb-1k.txt chipdb-8k.txt: icebox.py iceboxdb.py icebox_chipdb.py python3 icebox_chipdb.py -8 > chipdb-8k.new mv chipdb-8k.new chipdb-8k.txt clean: rm -f chipdb-1k.txt chipdb-8k.txt rm -f icebox.pyc iceboxdb.pyc install: all mkdir -p $(DESTDIR)$(PREFIX)/share/icebox mkdir -p $(DESTDIR)$(PREFIX)/bin cp chipdb-1k.txt $(DESTDIR)$(PREFIX)/share/icebox/ cp chipdb-8k.txt $(DESTDIR)$(PREFIX)/share/icebox/ cp icebox.py $(DESTDIR)$(PREFIX)/bin/icebox.py cp iceboxdb.py $(DESTDIR)$(PREFIX)/bin/iceboxdb.py cp icebox_chipdb.py $(DESTDIR)$(PREFIX)/bin/icebox_chipdb cp icebox_diff.py $(DESTDIR)$(PREFIX)/bin/icebox_diff cp icebox_explain.py $(DESTDIR)$(PREFIX)/bin/icebox_explain cp icebox_colbuf.py $(DESTDIR)$(PREFIX)/bin/icebox_colbuf cp icebox_html.py $(DESTDIR)$(PREFIX)/bin/icebox_html cp icebox_maps.py $(DESTDIR)$(PREFIX)/bin/icebox_maps cp icebox_vlog.py $(DESTDIR)$(PREFIX)/bin/icebox_vlog uninstall: rm -f $(DESTDIR)$(PREFIX)/bin/icebox.py rm -f $(DESTDIR)$(PREFIX)/bin/iceboxdb.py rm -f $(DESTDIR)$(PREFIX)/bin/icebox_chipdb rm -f $(DESTDIR)$(PREFIX)/bin/icebox_diff rm -f $(DESTDIR)$(PREFIX)/bin/icebox_explain rm -f $(DESTDIR)$(PREFIX)/bin/icebox_colbuf rm -f $(DESTDIR)$(PREFIX)/bin/icebox_html rm -f $(DESTDIR)$(PREFIX)/bin/icebox_maps rm -f $(DESTDIR)$(PREFIX)/bin/icebox_vlog rm -f $(DESTDIR)$(PREFIX)/share/icebox/chipdb-1k.txt rm -f $(DESTDIR)$(PREFIX)/share/icebox/chipdb-8k.txt -rmdir $(DESTDIR)$(PREFIX)/share/icebox .PHONY: all clean install uninstall fpga-icestorm-0~20160913git266e758/icebox/icebox.py000066400000000000000000003554051276746530600215020ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import iceboxdb import re, sys class iceconfig: def __init__(self): self.clear() def clear(self): self.max_x = 0 self.max_y = 0 self.device = "" self.logic_tiles = dict() self.io_tiles = dict() self.ramb_tiles = dict() self.ramt_tiles = dict() self.ram_data = dict() self.extra_bits = set() self.symbols = dict() def setup_empty_1k(self): self.clear() self.device = "1k" self.max_x = 13 self.max_y = 17 for x in range(1, self.max_x): for y in range(1, self.max_y): if x in (3, 10): if y % 2 == 1: self.ramb_tiles[(x, y)] = ["0" * 42 for i in range(16)] else: self.ramt_tiles[(x, y)] = ["0" * 42 for i in range(16)] else: self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)] for x in range(1, self.max_x): self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)] self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)] for y in range(1, self.max_y): self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)] self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)] def setup_empty_8k(self): self.clear() self.device = "8k" self.max_x = 33 self.max_y = 33 for x in range(1, self.max_x): for y in range(1, self.max_y): if x in (8, 25): if y % 2 == 1: self.ramb_tiles[(x, y)] = ["0" * 42 for i in range(16)] else: self.ramt_tiles[(x, y)] = ["0" * 42 for i in range(16)] else: self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)] for x in range(1, self.max_x): self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)] self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)] for y in range(1, self.max_y): self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)] self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)] def lookup_extra_bit(self, bit): assert self.device in extra_bits_db if bit in extra_bits_db[self.device]: return extra_bits_db[self.device][bit] return ("UNKNOWN_FUNCTION",) def tile(self, x, y): if (x, y) in self.io_tiles: return self.io_tiles[(x, y)] if (x, y) in self.logic_tiles: return self.logic_tiles[(x, y)] if (x, y) in self.ramb_tiles: return self.ramb_tiles[(x, y)] if (x, y) in self.ramt_tiles: return self.ramt_tiles[(x, y)] return None def pinloc_db(self): if self.device == "1k": return pinloc_db["1k-tq144"] if self.device == "8k": return pinloc_db["8k-ct256"] assert False def gbufin_db(self): return gbufin_db[self.device] def iolatch_db(self): return iolatch_db[self.device] def padin_pio_db(self): return padin_pio_db[self.device] def extra_bits_db(self): return extra_bits_db[self.device] def ieren_db(self): return ieren_db[self.device] def pll_list(self): if self.device == "1k": return ["1k"] if self.device == "8k": return ["8k_0", "8k_1"] assert False def colbuf_db(self): if self.device == "1k": entries = list() for x in range(self.max_x+1): for y in range(self.max_y+1): src_y = None if 0 <= y <= 4: src_y = 4 if 5 <= y <= 8: src_y = 5 if 9 <= y <= 12: src_y = 12 if 13 <= y <= 17: src_y = 13 if x in [3, 10] and src_y == 4: src_y = 3 if x in [3, 10] and src_y == 12: src_y = 11 entries.append((x, src_y, x, y)) return entries if self.device == "8k": entries = list() for x in range(self.max_x+1): for y in range(self.max_y+1): src_y = None if 0 <= y <= 8: src_y = 8 if 9 <= y <= 16: src_y = 9 if 17 <= y <= 24: src_y = 24 if 25 <= y <= 33: src_y = 25 entries.append((x, src_y, x, y)) return entries assert False def tile_db(self, x, y): if x == 0: return iotile_l_db if y == 0: return iotile_b_db if x == self.max_x: return iotile_r_db if y == self.max_y: return iotile_t_db if self.device == "1k": if (x, y) in self.logic_tiles: return logictile_db if (x, y) in self.ramb_tiles: return rambtile_db if (x, y) in self.ramt_tiles: return ramttile_db if self.device == "8k": if (x, y) in self.logic_tiles: return logictile_8k_db if (x, y) in self.ramb_tiles: return rambtile_8k_db if (x, y) in self.ramt_tiles: return ramttile_8k_db assert False def tile_type(self, x, y): if x == 0: return "IO" if y == 0: return "IO" if x == self.max_x: return "IO" if y == self.max_y: return "IO" if (x, y) in self.ramb_tiles: return "RAMB" if (x, y) in self.ramt_tiles: return "RAMT" if (x, y) in self.logic_tiles: return "LOGIC" assert False def tile_pos(self, x, y): if x == 0 and 0 < y < self.max_y: return "l" if y == 0 and 0 < x < self.max_x: return "b" if x == self.max_x and 0 < y < self.max_y: return "r" if y == self.max_y and 0 < x < self.max_x: return "t" if 0 < x < self.max_x and 0 < y < self.max_y: return "x" return None def tile_has_entry(self, x, y, entry): if entry[1] in ("routing", "buffer"): return self.tile_has_net(x, y, entry[2]) and self.tile_has_net(x, y, entry[3]) return True def tile_has_net(self, x, y, netname): if netname.startswith("logic_op_"): if netname.startswith("logic_op_bot_"): if y == self.max_y and 0 < x < self.max_x: return True if netname.startswith("logic_op_bnl_"): if x == self.max_x and 1 < y < self.max_y: return True if y == self.max_y and 1 < x < self.max_x: return True if netname.startswith("logic_op_bnr_"): if x == 0 and 1 < y < self.max_y: return True if y == self.max_y and 0 < x < self.max_x-1: return True if netname.startswith("logic_op_top_"): if y == 0 and 0 < x < self.max_x: return True if netname.startswith("logic_op_tnl_"): if x == self.max_x and 0 < y < self.max_y-1: return True if y == 0 and 1 < x < self.max_x: return True if netname.startswith("logic_op_tnr_"): if x == 0 and 0 < y < self.max_y-1: return True if y == 0 and 0 < x < self.max_x-1: return True if netname.startswith("logic_op_lft_"): if x == self.max_x: return True if netname.startswith("logic_op_rgt_"): if x == 0: return True return False if not 0 <= x <= self.max_x: return False if not 0 <= y <= self.max_y: return False return pos_has_net(self.tile_pos(x, y), netname) def tile_follow_net(self, x, y, direction, netname): if x == 1 and y not in (0, self.max_y) and direction == 'l': return pos_follow_net("x", "L", netname) if y == 1 and x not in (0, self.max_x) and direction == 'b': return pos_follow_net("x", "B", netname) if x == self.max_x-1 and y not in (0, self.max_y) and direction == 'r': return pos_follow_net("x", "R", netname) if y == self.max_y-1 and x not in (0, self.max_x) and direction == 't': return pos_follow_net("x", "T", netname) return pos_follow_net(self.tile_pos(x, y), direction, netname) def follow_funcnet(self, x, y, func): neighbours = set() def do_direction(name, nx, ny): if 0 < nx < self.max_x and 0 < ny < self.max_y: neighbours.add((nx, ny, "neigh_op_%s_%d" % (name, func))) if nx in (0, self.max_x) and 0 < ny < self.max_y and nx != x: neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func))) if ny in (0, self.max_y) and 0 < nx < self.max_x and ny != y: neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func))) do_direction("bot", x, y+1) do_direction("bnl", x+1, y+1) do_direction("bnr", x-1, y+1) do_direction("top", x, y-1) do_direction("tnl", x+1, y-1) do_direction("tnr", x-1, y-1) do_direction("lft", x+1, y ) do_direction("rgt", x-1, y ) return neighbours def lookup_funcnet(self, nx, ny, x, y, func): npos = self.tile_pos(nx, ny) pos = self.tile_pos(x, y) if npos is not None and pos is not None: if npos == "x": if (nx, ny) in self.logic_tiles: return (nx, ny, "lutff_%d/out" % func) if (nx, ny) in self.ramb_tiles: if self.device == "1k": return (nx, ny, "ram/RDATA_%d" % func) elif self.device == "8k": return (nx, ny, "ram/RDATA_%d" % (15-func)) else: assert False if (nx, ny) in self.ramt_tiles: if self.device == "1k": return (nx, ny, "ram/RDATA_%d" % (8+func)) elif self.device == "8k": return (nx, ny, "ram/RDATA_%d" % (7-func)) else: assert False elif pos == "x" and npos in ("l", "r", "t", "b"): if func in (0, 4): return (nx, ny, "io_0/D_IN_0") if func in (1, 5): return (nx, ny, "io_0/D_IN_1") if func in (2, 6): return (nx, ny, "io_1/D_IN_0") if func in (3, 7): return (nx, ny, "io_1/D_IN_1") return None def rlookup_funcnet(self, x, y, netname): funcnets = set() if netname == "io_0/D_IN_0": for net in self.follow_funcnet(x, y, 0) | self.follow_funcnet(x, y, 4): if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) if netname == "io_0/D_IN_1": for net in self.follow_funcnet(x, y, 1) | self.follow_funcnet(x, y, 5): if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) if netname == "io_1/D_IN_0": for net in self.follow_funcnet(x, y, 2) | self.follow_funcnet(x, y, 6): if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) if netname == "io_1/D_IN_1": for net in self.follow_funcnet(x, y, 3) | self.follow_funcnet(x, y, 7): if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) match = re.match(r"lutff_(\d+)/out", netname) if match: funcnets |= self.follow_funcnet(x, y, int(match.group(1))) match = re.match(r"ram/RDATA_(\d+)", netname) if match: if self.device == "1k": funcnets |= self.follow_funcnet(x, y, int(match.group(1)) % 8) elif self.device == "8k": funcnets |= self.follow_funcnet(x, y, 7 - int(match.group(1)) % 8) else: assert False return funcnets def follow_net(self, netspec): x, y, netname = netspec neighbours = self.rlookup_funcnet(x, y, netname) if netname == "carry_in" and y > 1: neighbours.add((x, y-1, "lutff_7/cout")) if netname == "lutff_7/cout" and y+1 < self.max_y: neighbours.add((x, y+1, "carry_in")) if netname.startswith("glb_netwk_"): for nx in range(self.max_x+1): for ny in range(self.max_y+1): if self.tile_pos(nx, ny) is not None: neighbours.add((nx, ny, netname)) match = re.match(r"sp4_r_v_b_(\d+)", netname) if match and 0 < x < self.max_x-1: neighbours.add((x+1, y, sp4v_normalize("sp4_v_b_" + match.group(1)))) match = re.match(r"sp4_v_[bt]_(\d+)", netname) if match and 1 < x < self.max_x: n = sp4v_normalize(netname, "b") if n is not None: n = n.replace("sp4_", "sp4_r_") neighbours.add((x-1, y, n)) match = re.match(r"(logic|neigh)_op_(...)_(\d+)", netname) if match: if match.group(2) == "bot": nx, ny = (x, y-1) if match.group(2) == "bnl": nx, ny = (x-1, y-1) if match.group(2) == "bnr": nx, ny = (x+1, y-1) if match.group(2) == "top": nx, ny = (x, y+1) if match.group(2) == "tnl": nx, ny = (x-1, y+1) if match.group(2) == "tnr": nx, ny = (x+1, y+1) if match.group(2) == "lft": nx, ny = (x-1, y ) if match.group(2) == "rgt": nx, ny = (x+1, y ) n = self.lookup_funcnet(nx, ny, x, y, int(match.group(3))) if n is not None: neighbours.add(n) for direction in ["l", "r", "t", "b"]: n = self.tile_follow_net(x, y, direction, netname) if n is not None: if direction == "l": s = (x-1, y, n) if direction == "r": s = (x+1, y, n) if direction == "t": s = (x, y+1, n) if direction == "b": s = (x, y-1, n) if s[0] in (0, self.max_x) and s[1] in (0, self.max_y): if re.match("span4_(vert|horz)_[lrtb]_\d+$", n): vert_net = n.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") horz_net = n.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") if s[0] == 0 and s[1] == 0: if direction == "l": s = (0, 1, vert_net) if direction == "b": s = (1, 0, horz_net) if s[0] == self.max_x and s[1] == self.max_y: if direction == "r": s = (self.max_x, self.max_y-1, vert_net) if direction == "t": s = (self.max_x-1, self.max_y, horz_net) vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") if s[0] == 0 and s[1] == self.max_y: if direction == "l": s = (0, self.max_y-1, vert_net) if direction == "t": s = (1, self.max_y, horz_net) if s[0] == self.max_x and s[1] == 0: if direction == "r": s = (self.max_x, 1, vert_net) if direction == "b": s = (self.max_x-1, 0, horz_net) if self.tile_has_net(s[0], s[1], s[2]): neighbours.add((s[0], s[1], s[2])) return neighbours def group_segments(self, all_from_tiles=set(), extra_connections=list(), extra_segments=list(), connect_gb=True): seed_segments = set() seen_segments = set() connected_segments = dict() grouped_segments = set() for seg in extra_segments: seed_segments.add(seg) for conn in extra_connections: s1, s2 = conn connected_segments.setdefault(s1, set()).add(s2) connected_segments.setdefault(s2, set()).add(s1) seed_segments.add(s1) seed_segments.add(s2) for idx, tile in self.io_tiles.items(): tc = tileconfig(tile) pintypes = [ list("000000"), list("000000") ] for entry in self.tile_db(idx[0], idx[1]): if entry[1].startswith("IOB_") and entry[2].startswith("PINTYPE_") and tc.match(entry[0]): pintypes[int(entry[1][-1])][int(entry[2][-1])] = "1" if "".join(pintypes[0][2:6]) != "0000": seed_segments.add((idx[0], idx[1], "io_0/D_OUT_0")) if "".join(pintypes[1][2:6]) != "0000": seed_segments.add((idx[0], idx[1], "io_1/D_OUT_0")) def add_seed_segments(idx, tile, db): tc = tileconfig(tile) for entry in db: if entry[1] in ("routing", "buffer"): config_match = tc.match(entry[0]) if idx in all_from_tiles or config_match: if not self.tile_has_net(idx[0], idx[1], entry[2]): continue if not self.tile_has_net(idx[0], idx[1], entry[3]): continue s1 = (idx[0], idx[1], entry[2]) s2 = (idx[0], idx[1], entry[3]) if config_match: connected_segments.setdefault(s1, set()).add(s2) connected_segments.setdefault(s2, set()).add(s1) seed_segments.add(s1) seed_segments.add(s2) for idx, tile in self.io_tiles.items(): add_seed_segments(idx, tile, self.tile_db(idx[0], idx[1])) for idx, tile in self.logic_tiles.items(): if idx in all_from_tiles: seed_segments.add((idx[0], idx[1], "lutff_7/cout")) if self.device == "1k": add_seed_segments(idx, tile, logictile_db) elif self.device == "8k": add_seed_segments(idx, tile, logictile_8k_db) else: assert False for idx, tile in self.ramb_tiles.items(): if self.device == "1k": add_seed_segments(idx, tile, rambtile_db) elif self.device == "8k": add_seed_segments(idx, tile, rambtile_8k_db) else: assert False for idx, tile in self.ramt_tiles.items(): if self.device == "1k": add_seed_segments(idx, tile, ramttile_db) elif self.device == "8k": add_seed_segments(idx, tile, ramttile_8k_db) else: assert False for padin, pio in enumerate(self.padin_pio_db()): s1 = (pio[0], pio[1], "padin_%d" % pio[2]) s2 = (pio[0], pio[1], "glb_netwk_%d" % padin) if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles: connected_segments.setdefault(s1, set()).add(s2) connected_segments.setdefault(s2, set()).add(s1) seed_segments.add(s1) seed_segments.add(s2) for entry in self.iolatch_db(): if entry[0] == 0 or entry[0] == self.max_x: iocells = [(entry[0], i) for i in range(1, self.max_y)] if entry[1] == 0 or entry[1] == self.max_y: iocells = [(i, entry[1]) for i in range(1, self.max_x)] for cell in iocells: s1 = (entry[0], entry[1], "fabout") s2 = (cell[0], cell[1], "io_global/latch") if s1 in seed_segments or s2 in seed_segments or \ (entry[0], entry[1]) in all_from_tiles or (cell[0], cell[1]) in all_from_tiles: connected_segments.setdefault(s1, set()).add(s2) connected_segments.setdefault(s2, set()).add(s1) seed_segments.add(s1) seed_segments.add(s2) if connect_gb: for entry in self.gbufin_db(): s1 = (entry[0], entry[1], "fabout") s2 = (entry[0], entry[1], "glb_netwk_%d" % entry[2]) if s1 in seed_segments or (pio[0], pio[1]) in all_from_tiles: connected_segments.setdefault(s1, set()).add(s2) connected_segments.setdefault(s2, set()).add(s1) seed_segments.add(s1) seed_segments.add(s2) while seed_segments: queue = set() segments = set() queue.add(seed_segments.pop()) while queue: for s in self.expand_net(queue.pop()): if s not in segments: segments.add(s) assert s not in seen_segments seen_segments.add(s) seed_segments.discard(s) if s in connected_segments: for cs in connected_segments[s]: if not cs in segments: queue.add(cs) for s in segments: assert s not in seed_segments grouped_segments.add(tuple(sorted(segments))) return grouped_segments def expand_net(self, netspec): queue = set() segments = set() queue.add(netspec) while queue: n = queue.pop() segments.add(n) for k in self.follow_net(n): if k not in segments: queue.add(k) return segments def read_file(self, filename): self.clear() current_data = None expected_data_lines = 0 with open(filename, "r") as f: for linenum, linetext in enumerate(f): # print("DEBUG: input line %d: %s" % (linenum, linetext.strip())) line = linetext.strip().split() if len(line) == 0: assert expected_data_lines == 0 continue if line[0][0] != ".": if expected_data_lines == -1: continue if line[0][0] not in "0123456789abcdef": print("Warning: ignoring data block in line %d: %s" % (linenum, linetext.strip())) expected_data_lines = 0 continue assert expected_data_lines != 0 current_data.append(line[0]) expected_data_lines -= 1 continue assert expected_data_lines <= 0 if line[0] in (".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile", ".ram_data"): current_data = list() expected_data_lines = 16 self.max_x = max(self.max_x, int(line[1])) self.max_y = max(self.max_y, int(line[2])) if line[0] == ".io_tile": self.io_tiles[(int(line[1]), int(line[2]))] = current_data continue if line[0] == ".logic_tile": self.logic_tiles[(int(line[1]), int(line[2]))] = current_data continue if line[0] == ".ramb_tile": self.ramb_tiles[(int(line[1]), int(line[2]))] = current_data continue if line[0] == ".ramt_tile": self.ramt_tiles[(int(line[1]), int(line[2]))] = current_data continue if line[0] == ".ram_data": self.ram_data[(int(line[1]), int(line[2]))] = current_data continue if line[0] == ".extra_bit": self.extra_bits.add((int(line[1]), int(line[2]), int(line[3]))) continue if line[0] == ".device": assert line[1] in ["1k", "8k"] self.device = line[1] continue if line[0] == ".sym": self.symbols.setdefault(int(line[1]), set()).add(line[2]) continue if line[0] == ".comment": expected_data_lines = -1 continue print("Warning: ignoring line %d: %s" % (linenum, linetext.strip())) expected_data_lines = -1 def write_file(self, filename): with open(filename, "w") as f: print(".device %s" % self.device, file=f) for y in range(self.max_y+1): for x in range(self.max_x+1): if self.tile_pos(x, y) is not None: print(".%s_tile %d %d" % (self.tile_type(x, y).lower(), x, y), file=f) for line in self.tile(x, y): print(line, file=f) for x, y in sorted(self.ram_data): print(".ram_data %d %d" % (x, y), file=f) for line in self.ram_data[(x, y)]: print(line, file=f) class tileconfig: def __init__(self, tile): self.bits = set() for k, line in enumerate(tile): for i in range(len(line)): if line[i] == "1": self.bits.add("B%d[%d]" % (k, i)) else: self.bits.add("!B%d[%d]" % (k, i)) def match(self, pattern): for bit in pattern: if not bit in self.bits: return False return True if False: ## Lattice span net name normalization valid_sp4_h_l = set([1, 2, 4, 5, 7, 9, 10, 11, 15, 16, 17, 21, 24, 34, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47]) valid_sp4_h_r = set([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 19, 21, 24, 25, 27, 30, 31, 33, 34, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46]) valid_sp4_v_t = set([1, 3, 5, 9, 12, 14, 16, 17, 18, 21, 22, 23, 26, 28, 29, 30, 32, 33, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47]) valid_sp4_v_b = set([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 18, 19, 21, 22, 23, 24, 26, 30, 33, 36, 37, 38, 42, 46, 47]) valid_sp12_h_l = set([3, 4, 5, 12, 14, 16, 17, 18, 21, 22, 23]) valid_sp12_h_r = set([0, 1, 2, 3, 5, 8, 9, 10, 11, 12, 13, 14, 16, 20, 23]) valid_sp12_v_t = set([0, 1, 2, 3, 6, 9, 10, 12, 14, 21, 22, 23]) valid_sp12_v_b = set([0, 1, 6, 7, 8, 11, 12, 14, 16, 18, 19, 20, 21, 23]) else: ## IceStorm span net name normalization valid_sp4_h_l = set(range(36, 48)) valid_sp4_h_r = set(range(48)) valid_sp4_v_t = set(range(36, 48)) valid_sp4_v_b = set(range(48)) valid_sp12_h_l = set(range(22, 24)) valid_sp12_h_r = set(range(24)) valid_sp12_v_t = set(range(22, 24)) valid_sp12_v_b = set(range(24)) def sp4h_normalize(netname, edge=""): m = re.match("sp4_h_([lr])_(\d+)$", netname) assert m if not m: return None cur_edge = m.group(1) cur_index = int(m.group(2)) if cur_edge == edge: return netname if cur_edge == "r" and (edge == "l" or (edge == "" and cur_index not in valid_sp4_h_r)): if cur_index < 12: return None return "sp4_h_l_%d" % ((cur_index-12)^1) if cur_edge == "l" and (edge == "r" or (edge == "" and cur_index not in valid_sp4_h_l)): if cur_index >= 36: return None return "sp4_h_r_%d" % ((cur_index+12)^1) return netname def sp4v_normalize(netname, edge=""): m = re.match("sp4_v_([bt])_(\d+)$", netname) assert m if not m: return None cur_edge = m.group(1) cur_index = int(m.group(2)) if cur_edge == edge: return netname if cur_edge == "b" and (edge == "t" or (edge == "" and cur_index not in valid_sp4_v_b)): if cur_index < 12: return None return "sp4_v_t_%d" % ((cur_index-12)^1) if cur_edge == "t" and (edge == "b" or (edge == "" and cur_index not in valid_sp4_v_t)): if cur_index >= 36: return None return "sp4_v_b_%d" % ((cur_index+12)^1) return netname def sp12h_normalize(netname, edge=""): m = re.match("sp12_h_([lr])_(\d+)$", netname) assert m if not m: return None cur_edge = m.group(1) cur_index = int(m.group(2)) if cur_edge == edge: return netname if cur_edge == "r" and (edge == "l" or (edge == "" and cur_index not in valid_sp12_h_r)): if cur_index < 2: return None return "sp12_h_l_%d" % ((cur_index-2)^1) if cur_edge == "l" and (edge == "r" or (edge == "" and cur_index not in valid_sp12_h_l)): if cur_index >= 22: return None return "sp12_h_r_%d" % ((cur_index+2)^1) return netname def sp12v_normalize(netname, edge=""): m = re.match("sp12_v_([bt])_(\d+)$", netname) assert m if not m: return None cur_edge = m.group(1) cur_index = int(m.group(2)) if cur_edge == edge: return netname if cur_edge == "b" and (edge == "t" or (edge == "" and cur_index not in valid_sp12_v_b)): if cur_index < 2: return None return "sp12_v_t_%d" % ((cur_index-2)^1) if cur_edge == "t" and (edge == "b" or (edge == "" and cur_index not in valid_sp12_v_t)): if cur_index >= 22: return None return "sp12_v_b_%d" % ((cur_index+2)^1) return netname def netname_normalize(netname, edge="", ramb=False, ramt=False, ramb_8k=False, ramt_8k=False): if netname.startswith("sp4_v_"): return sp4v_normalize(netname, edge) if netname.startswith("sp4_h_"): return sp4h_normalize(netname, edge) if netname.startswith("sp12_v_"): return sp12v_normalize(netname, edge) if netname.startswith("sp12_h_"): return sp12h_normalize(netname, edge) if netname.startswith("input_2_"): netname = netname.replace("input_2_", "wire_logic_cluster/lc_") + "/in_2" netname = netname.replace("lc_trk_", "local_") netname = netname.replace("lc_", "lutff_") netname = netname.replace("wire_logic_cluster/", "") netname = netname.replace("wire_io_cluster/", "") netname = netname.replace("wire_bram/", "") if (ramb or ramt or ramb_8k or ramt_8k) and netname.startswith("input"): match = re.match(r"input(\d)_(\d)", netname) idx1, idx2 = (int(match.group(1)), int(match.group(2))) if ramb: netname="ram/WADDR_%d" % (idx1*4 + idx2) if ramt: netname="ram/RADDR_%d" % (idx1*4 + idx2) if ramb_8k: netname="ram/RADDR_%d" % ([7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, 10, 9, 8][idx1*4 + idx2]) if ramt_8k: netname="ram/WADDR_%d" % ([7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, 10, 9, 8][idx1*4 + idx2]) match = re.match(r"(...)_op_(.*)", netname) if match: netname = "neigh_op_%s_%s" % (match.group(1), match.group(2)) if re.match(r"lutff_7/(cen|clk|s_r)", netname): netname = netname.replace("lutff_7/", "lutff_global/") if re.match(r"io_1/(cen|inclk|outclk)", netname): netname = netname.replace("io_1/", "io_global/") if netname == "carry_in_mux/cout": return "carry_in_mux" return netname def pos_has_net(pos, netname): if pos in ("l", "r"): if re.search(r"_vert_\d+$", netname): return False if re.search(r"_horz_[rl]_\d+$", netname): return False if pos in ("t", "b"): if re.search(r"_horz_\d+$", netname): return False if re.search(r"_vert_[bt]_\d+$", netname): return False return True def pos_follow_net(pos, direction, netname): if pos == "x": m = re.match("sp4_h_[lr]_(\d+)$", netname) if m and direction in ("l", "L"): n = sp4h_normalize(netname, "l") if n is not None: if direction == "l": n = re.sub("_l_", "_r_", n) n = sp4h_normalize(n) else: n = re.sub("_l_", "_", n) n = re.sub("sp4_h_", "span4_horz_", n) return n if m and direction in ("r", "R"): n = sp4h_normalize(netname, "r") if n is not None: if direction == "r": n = re.sub("_r_", "_l_", n) n = sp4h_normalize(n) else: n = re.sub("_r_", "_", n) n = re.sub("sp4_h_", "span4_horz_", n) return n m = re.match("sp4_v_[tb]_(\d+)$", netname) if m and direction in ("t", "T"): n = sp4v_normalize(netname, "t") if n is not None: if direction == "t": n = re.sub("_t_", "_b_", n) n = sp4v_normalize(n) else: n = re.sub("_t_", "_", n) n = re.sub("sp4_v_", "span4_vert_", n) return n if m and direction in ("b", "B"): n = sp4v_normalize(netname, "b") if n is not None: if direction == "b": n = re.sub("_b_", "_t_", n) n = sp4v_normalize(n) else: n = re.sub("_b_", "_", n) n = re.sub("sp4_v_", "span4_vert_", n) return n m = re.match("sp12_h_[lr]_(\d+)$", netname) if m and direction in ("l", "L"): n = sp12h_normalize(netname, "l") if n is not None: if direction == "l": n = re.sub("_l_", "_r_", n) n = sp12h_normalize(n) else: n = re.sub("_l_", "_", n) n = re.sub("sp12_h_", "span12_horz_", n) return n if m and direction in ("r", "R"): n = sp12h_normalize(netname, "r") if n is not None: if direction == "r": n = re.sub("_r_", "_l_", n) n = sp12h_normalize(n) else: n = re.sub("_r_", "_", n) n = re.sub("sp12_h_", "span12_horz_", n) return n m = re.match("sp12_v_[tb]_(\d+)$", netname) if m and direction in ("t", "T"): n = sp12v_normalize(netname, "t") if n is not None: if direction == "t": n = re.sub("_t_", "_b_", n) n = sp12v_normalize(n) else: n = re.sub("_t_", "_", n) n = re.sub("sp12_v_", "span12_vert_", n) return n if m and direction in ("b", "B"): n = sp12v_normalize(netname, "b") if n is not None: if direction == "b": n = re.sub("_b_", "_t_", n) n = sp12v_normalize(n) else: n = re.sub("_b_", "_", n) n = re.sub("sp12_v_", "span12_vert_", n) return n if pos in ("l", "r" ): m = re.match("span4_vert_([bt])_(\d+)$", netname) if m: case, idx = direction + m.group(1), int(m.group(2)) if case == "tt": return "span4_vert_b_%d" % idx if case == "tb" and idx >= 4: return "span4_vert_b_%d" % (idx-4) if case == "bb" and idx < 12: return "span4_vert_b_%d" % (idx+4) if case == "bb" and idx >= 12: return "span4_vert_t_%d" % idx if pos in ("t", "b" ): m = re.match("span4_horz_([rl])_(\d+)$", netname) if m: case, idx = direction + m.group(1), int(m.group(2)) if case == "ll": return "span4_horz_r_%d" % idx if case == "lr" and idx >= 4: return "span4_horz_r_%d" % (idx-4) if case == "rr" and idx < 12: return "span4_horz_r_%d" % (idx+4) if case == "rr" and idx >= 12: return "span4_horz_l_%d" % idx if pos == "l" and direction == "r": m = re.match("span4_horz_(\d+)$", netname) if m: return sp4h_normalize("sp4_h_l_%s" % m.group(1)) m = re.match("span12_horz_(\d+)$", netname) if m: return sp12h_normalize("sp12_h_l_%s" % m.group(1)) if pos == "r" and direction == "l": m = re.match("span4_horz_(\d+)$", netname) if m: return sp4h_normalize("sp4_h_r_%s" % m.group(1)) m = re.match("span12_horz_(\d+)$", netname) if m: return sp12h_normalize("sp12_h_r_%s" % m.group(1)) if pos == "t" and direction == "b": m = re.match("span4_vert_(\d+)$", netname) if m: return sp4v_normalize("sp4_v_t_%s" % m.group(1)) m = re.match("span12_vert_(\d+)$", netname) if m: return sp12v_normalize("sp12_v_t_%s" % m.group(1)) if pos == "b" and direction == "t": m = re.match("span4_vert_(\d+)$", netname) if m: return sp4v_normalize("sp4_v_b_%s" % m.group(1)) m = re.match("span12_vert_(\d+)$", netname) if m: return sp12v_normalize("sp12_v_b_%s" % m.group(1)) return None def get_lutff_bits(tile, index): bits = list("--------------------") for k, line in enumerate(tile): for i in range(36, 46): lutff_idx = k // 2 lutff_bitnum = (i-36) + 10*(k%2) if lutff_idx == index: bits[lutff_bitnum] = line[i]; return bits def get_lutff_lut_bits(tile, index): lutff_bits = get_lutff_bits(tile, index) return [lutff_bits[i] for i in [4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0]] def get_lutff_seq_bits(tile, index): lutff_bits = get_lutff_bits(tile, index) return [lutff_bits[i] for i in [8, 9, 18, 19]] def get_carry_cascade_bit(tile): return tile[1][49] def get_carry_bit(tile): return tile[1][50] def get_negclk_bit(tile): return tile[0][0] def key_netname(netname): return re.sub(r"\d+", lambda m: "%09d" % int(m.group(0)), netname) def run_checks_neigh(): print("Running consistency checks on neighbour finder..") ic = iceconfig() ic.setup_empty_1k() # ic.setup_empty_8k() all_segments = set() def add_segments(idx, db): for entry in db: if entry[1] in ("routing", "buffer"): if not ic.tile_has_net(idx[0], idx[1], entry[2]): continue if not ic.tile_has_net(idx[0], idx[1], entry[3]): continue all_segments.add((idx[0], idx[1], entry[2])) all_segments.add((idx[0], idx[1], entry[3])) for x in range(ic.max_x+1): for y in range(ic.max_x+1): if x in (0, ic.max_x) and y in (0, ic.max_y): continue add_segments((x, y), ic.tile_db(x, y)) if (x, y) in ic.logic_tiles: all_segments.add((x, y, "lutff_7/cout")) for s1 in all_segments: # if s1[1] > 4: continue for s2 in ic.follow_net(s1): if s1 not in ic.follow_net(s2): print("ERROR: %s -> %s, but not vice versa!" % (s1, s2)) print("Neighbours of %s:" % (s1,)) for s in ic.follow_net(s1): print(" ", s) print("Neighbours of %s:" % (s2,)) for s in ic.follow_net(s2): print(" ", s) print() def run_checks(): run_checks_neigh() def parse_db(text, grep_8k=False): db = list() for line in text.split("\n"): line_1k = line.replace("1k_glb_netwk_", "glb_netwk_") line_8k = line.replace("8k_glb_netwk_", "glb_netwk_") if line_1k != line: if grep_8k: continue line = line_1k elif line_8k != line: if not grep_8k: continue line = line_8k line = line.split("\t") if len(line) == 0 or line[0] == "": continue line[0] = line[0].split(",") db.append(line) return db extra_bits_db = { "1k": { (0, 330, 142): ("padin_glb_netwk", "0"), (0, 331, 142): ("padin_glb_netwk", "1"), (1, 330, 143): ("padin_glb_netwk", "2"), (1, 331, 143): ("padin_glb_netwk", "3"), (1, 330, 142): ("padin_glb_netwk", "4"), (1, 331, 142): ("padin_glb_netwk", "5"), (0, 330, 143): ("padin_glb_netwk", "6"), (0, 331, 143): ("padin_glb_netwk", "7"), }, "8k": { (0, 870, 270): ("padin_glb_netwk", "0"), (0, 871, 270): ("padin_glb_netwk", "1"), (1, 870, 271): ("padin_glb_netwk", "2"), (1, 871, 271): ("padin_glb_netwk", "3"), (1, 870, 270): ("padin_glb_netwk", "4"), (1, 871, 270): ("padin_glb_netwk", "5"), (0, 870, 271): ("padin_glb_netwk", "6"), (0, 871, 271): ("padin_glb_netwk", "7"), } } gbufin_db = { "1k": [ (13, 8, 7), ( 0, 8, 6), ( 7, 17, 1), ( 7, 0, 0), ( 0, 9, 3), (13, 9, 2), ( 6, 0, 5), ( 6, 17, 4), ], "8k": [ (33, 16, 7), ( 0, 16, 6), (17, 33, 1), (17, 0, 0), ( 0, 17, 3), (33, 17, 2), (16, 0, 5), (16, 33, 4), ] } iolatch_db = { "1k": [ ( 0, 7), (13, 10), ( 5, 0), ( 8, 17), ], "8k": [ ( 0, 15), (33, 18), (18, 0), (15, 33), ], } warmbootinfo_db = { "1k": { "BOOT": ( 12, 0, "fabout" ), "S0": ( 13, 1, "fabout" ), "S1": ( 13, 2, "fabout" ), }, "8k": { "BOOT": ( 31, 0, "fabout" ), "S0": ( 33, 1, "fabout" ), "S1": ( 33, 2, "fabout" ), } } noplls_db = { "1k-swg16tr": [ "1k" ], "1k-cm36": [ "1k" ], "1k-cm49": [ "1k" ], "8k-cm81": [ "8k_1" ], "8k-cm81:4k": [ "8k_1" ], "1k-qn48": [ "1k" ], "1k-cb81": [ "1k" ], "1k-cb121": [ "1k" ], "1k-vq100": [ "1k" ], } pllinfo_db = { "1k": { "LOC" : (6, 0), # 3'b000 = "DISABLED" # 3'b010 = "SB_PLL40_PAD" # 3'b100 = "SB_PLL40_2_PAD" # 3'b110 = "SB_PLL40_2F_PAD" # 3'b011 = "SB_PLL40_CORE" # 3'b111 = "SB_PLL40_2F_CORE" "PLLTYPE_0": ( 0, 3, "PLLCONFIG_5"), "PLLTYPE_1": ( 0, 5, "PLLCONFIG_1"), "PLLTYPE_2": ( 0, 5, "PLLCONFIG_3"), # 3'b000 = "DELAY" # 3'b001 = "SIMPLE" # 3'b010 = "PHASE_AND_DELAY" # 3'b110 = "EXTERNAL" "FEEDBACK_PATH_0": ( 0, 5, "PLLCONFIG_5"), "FEEDBACK_PATH_1": ( 0, 2, "PLLCONFIG_9"), "FEEDBACK_PATH_2": ( 0, 3, "PLLCONFIG_1"), # 1'b0 = "FIXED" # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111) "DELAY_ADJMODE_FB": ( 0, 4, "PLLCONFIG_4"), # 1'b0 = "FIXED" # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111) "DELAY_ADJMODE_REL": ( 0, 4, "PLLCONFIG_9"), # 2'b00 = "GENCLK" # 2'b01 = "GENCLK_HALF" # 2'b10 = "SHIFTREG_90deg" # 2'b11 = "SHIFTREG_0deg" "PLLOUT_SELECT_A_0": ( 0, 3, "PLLCONFIG_6"), "PLLOUT_SELECT_A_1": ( 0, 3, "PLLCONFIG_7"), # 2'b00 = "GENCLK" # 2'b01 = "GENCLK_HALF" # 2'b10 = "SHIFTREG_90deg" # 2'b11 = "SHIFTREG_0deg" "PLLOUT_SELECT_B_0": ( 0, 3, "PLLCONFIG_2"), "PLLOUT_SELECT_B_1": ( 0, 3, "PLLCONFIG_3"), # Numeric Parameters "SHIFTREG_DIV_MODE": ( 0, 3, "PLLCONFIG_4"), "FDA_FEEDBACK_0": ( 0, 3, "PLLCONFIG_9"), "FDA_FEEDBACK_1": ( 0, 4, "PLLCONFIG_1"), "FDA_FEEDBACK_2": ( 0, 4, "PLLCONFIG_2"), "FDA_FEEDBACK_3": ( 0, 4, "PLLCONFIG_3"), "FDA_RELATIVE_0": ( 0, 4, "PLLCONFIG_5"), "FDA_RELATIVE_1": ( 0, 4, "PLLCONFIG_6"), "FDA_RELATIVE_2": ( 0, 4, "PLLCONFIG_7"), "FDA_RELATIVE_3": ( 0, 4, "PLLCONFIG_8"), "DIVR_0": ( 0, 1, "PLLCONFIG_1"), "DIVR_1": ( 0, 1, "PLLCONFIG_2"), "DIVR_2": ( 0, 1, "PLLCONFIG_3"), "DIVR_3": ( 0, 1, "PLLCONFIG_4"), "DIVF_0": ( 0, 1, "PLLCONFIG_5"), "DIVF_1": ( 0, 1, "PLLCONFIG_6"), "DIVF_2": ( 0, 1, "PLLCONFIG_7"), "DIVF_3": ( 0, 1, "PLLCONFIG_8"), "DIVF_4": ( 0, 1, "PLLCONFIG_9"), "DIVF_5": ( 0, 2, "PLLCONFIG_1"), "DIVF_6": ( 0, 2, "PLLCONFIG_2"), "DIVQ_0": ( 0, 2, "PLLCONFIG_3"), "DIVQ_1": ( 0, 2, "PLLCONFIG_4"), "DIVQ_2": ( 0, 2, "PLLCONFIG_5"), "FILTER_RANGE_0": ( 0, 2, "PLLCONFIG_6"), "FILTER_RANGE_1": ( 0, 2, "PLLCONFIG_7"), "FILTER_RANGE_2": ( 0, 2, "PLLCONFIG_8"), "TEST_MODE": ( 0, 3, "PLLCONFIG_8"), # PLL Ports "PLLOUT_A": ( 6, 0, 1), "PLLOUT_B": ( 7, 0, 0), "REFERENCECLK": ( 0, 1, "fabout"), "EXTFEEDBACK": ( 0, 2, "fabout"), "DYNAMICDELAY_0": ( 0, 4, "fabout"), "DYNAMICDELAY_1": ( 0, 5, "fabout"), "DYNAMICDELAY_2": ( 0, 6, "fabout"), "DYNAMICDELAY_3": ( 0, 10, "fabout"), "DYNAMICDELAY_4": ( 0, 11, "fabout"), "DYNAMICDELAY_5": ( 0, 12, "fabout"), "DYNAMICDELAY_6": ( 0, 13, "fabout"), "DYNAMICDELAY_7": ( 0, 14, "fabout"), "LOCK": ( 1, 1, "neigh_op_bnl_1"), "BYPASS": ( 1, 0, "fabout"), "RESETB": ( 2, 0, "fabout"), "LATCHINPUTVALUE": ( 5, 0, "fabout"), "SDO": (12, 1, "neigh_op_bnr_3"), "SDI": ( 4, 0, "fabout"), "SCLK": ( 3, 0, "fabout"), }, "8k_0": { "LOC" : (16, 0), # 3'b000 = "DISABLED" # 3'b010 = "SB_PLL40_PAD" # 3'b100 = "SB_PLL40_2_PAD" # 3'b110 = "SB_PLL40_2F_PAD" # 3'b011 = "SB_PLL40_CORE" # 3'b111 = "SB_PLL40_2F_CORE" "PLLTYPE_0": ( 16, 0, "PLLCONFIG_5"), "PLLTYPE_1": ( 18, 0, "PLLCONFIG_1"), "PLLTYPE_2": ( 18, 0, "PLLCONFIG_3"), # 3'b000 = "DELAY" # 3'b001 = "SIMPLE" # 3'b010 = "PHASE_AND_DELAY" # 3'b110 = "EXTERNAL" "FEEDBACK_PATH_0": ( 18, 0, "PLLCONFIG_5"), "FEEDBACK_PATH_1": ( 15, 0, "PLLCONFIG_9"), "FEEDBACK_PATH_2": ( 16, 0, "PLLCONFIG_1"), # 1'b0 = "FIXED" # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111) "DELAY_ADJMODE_FB": ( 17, 0, "PLLCONFIG_4"), # 1'b0 = "FIXED" # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111) "DELAY_ADJMODE_REL": ( 17, 0, "PLLCONFIG_9"), # 2'b00 = "GENCLK" # 2'b01 = "GENCLK_HALF" # 2'b10 = "SHIFTREG_90deg" # 2'b11 = "SHIFTREG_0deg" "PLLOUT_SELECT_A_0": ( 16, 0, "PLLCONFIG_6"), "PLLOUT_SELECT_A_1": ( 16, 0, "PLLCONFIG_7"), # 2'b00 = "GENCLK" # 2'b01 = "GENCLK_HALF" # 2'b10 = "SHIFTREG_90deg" # 2'b11 = "SHIFTREG_0deg" "PLLOUT_SELECT_B_0": ( 16, 0, "PLLCONFIG_2"), "PLLOUT_SELECT_B_1": ( 16, 0, "PLLCONFIG_3"), # Numeric Parameters "SHIFTREG_DIV_MODE": ( 16, 0, "PLLCONFIG_4"), "FDA_FEEDBACK_0": ( 16, 0, "PLLCONFIG_9"), "FDA_FEEDBACK_1": ( 17, 0, "PLLCONFIG_1"), "FDA_FEEDBACK_2": ( 17, 0, "PLLCONFIG_2"), "FDA_FEEDBACK_3": ( 17, 0, "PLLCONFIG_3"), "FDA_RELATIVE_0": ( 17, 0, "PLLCONFIG_5"), "FDA_RELATIVE_1": ( 17, 0, "PLLCONFIG_6"), "FDA_RELATIVE_2": ( 17, 0, "PLLCONFIG_7"), "FDA_RELATIVE_3": ( 17, 0, "PLLCONFIG_8"), "DIVR_0": ( 14, 0, "PLLCONFIG_1"), "DIVR_1": ( 14, 0, "PLLCONFIG_2"), "DIVR_2": ( 14, 0, "PLLCONFIG_3"), "DIVR_3": ( 14, 0, "PLLCONFIG_4"), "DIVF_0": ( 14, 0, "PLLCONFIG_5"), "DIVF_1": ( 14, 0, "PLLCONFIG_6"), "DIVF_2": ( 14, 0, "PLLCONFIG_7"), "DIVF_3": ( 14, 0, "PLLCONFIG_8"), "DIVF_4": ( 14, 0, "PLLCONFIG_9"), "DIVF_5": ( 15, 0, "PLLCONFIG_1"), "DIVF_6": ( 15, 0, "PLLCONFIG_2"), "DIVQ_0": ( 15, 0, "PLLCONFIG_3"), "DIVQ_1": ( 15, 0, "PLLCONFIG_4"), "DIVQ_2": ( 15, 0, "PLLCONFIG_5"), "FILTER_RANGE_0": ( 15, 0, "PLLCONFIG_6"), "FILTER_RANGE_1": ( 15, 0, "PLLCONFIG_7"), "FILTER_RANGE_2": ( 15, 0, "PLLCONFIG_8"), "TEST_MODE": ( 16, 0, "PLLCONFIG_8"), # PLL Ports "PLLOUT_A": ( 16, 0, 1), "PLLOUT_B": ( 17, 0, 0), "REFERENCECLK": ( 13, 0, "fabout"), "EXTFEEDBACK": ( 14, 0, "fabout"), "DYNAMICDELAY_0": ( 5, 0, "fabout"), "DYNAMICDELAY_1": ( 6, 0, "fabout"), "DYNAMICDELAY_2": ( 7, 0, "fabout"), "DYNAMICDELAY_3": ( 8, 0, "fabout"), "DYNAMICDELAY_4": ( 9, 0, "fabout"), "DYNAMICDELAY_5": ( 10, 0, "fabout"), "DYNAMICDELAY_6": ( 11, 0, "fabout"), "DYNAMICDELAY_7": ( 12, 0, "fabout"), "LOCK": ( 1, 1, "neigh_op_bnl_1"), "BYPASS": ( 19, 0, "fabout"), "RESETB": ( 20, 0, "fabout"), "LATCHINPUTVALUE": ( 15, 0, "fabout"), "SDO": ( 32, 1, "neigh_op_bnr_3"), "SDI": ( 22, 0, "fabout"), "SCLK": ( 21, 0, "fabout"), }, "8k_1": { "LOC" : (16, 33), # 3'b000 = "DISABLED" # 3'b010 = "SB_PLL40_PAD" # 3'b100 = "SB_PLL40_2_PAD" # 3'b110 = "SB_PLL40_2F_PAD" # 3'b011 = "SB_PLL40_CORE" # 3'b111 = "SB_PLL40_2F_CORE" "PLLTYPE_0": ( 16, 33, "PLLCONFIG_5"), "PLLTYPE_1": ( 18, 33, "PLLCONFIG_1"), "PLLTYPE_2": ( 18, 33, "PLLCONFIG_3"), # 3'b000 = "DELAY" # 3'b001 = "SIMPLE" # 3'b010 = "PHASE_AND_DELAY" # 3'b110 = "EXTERNAL" "FEEDBACK_PATH_0": ( 18, 33, "PLLCONFIG_5"), "FEEDBACK_PATH_1": ( 15, 33, "PLLCONFIG_9"), "FEEDBACK_PATH_2": ( 16, 33, "PLLCONFIG_1"), # 1'b0 = "FIXED" # 1'b1 = "DYNAMIC" (also set FDA_FEEDBACK=4'b1111) "DELAY_ADJMODE_FB": ( 17, 33, "PLLCONFIG_4"), # 1'b0 = "FIXED" # 1'b1 = "DYNAMIC" (also set FDA_RELATIVE=4'b1111) "DELAY_ADJMODE_REL": ( 17, 33, "PLLCONFIG_9"), # 2'b00 = "GENCLK" # 2'b01 = "GENCLK_HALF" # 2'b10 = "SHIFTREG_90deg" # 2'b11 = "SHIFTREG_0deg" "PLLOUT_SELECT_A_0": ( 16, 33, "PLLCONFIG_6"), "PLLOUT_SELECT_A_1": ( 16, 33, "PLLCONFIG_7"), # 2'b00 = "GENCLK" # 2'b01 = "GENCLK_HALF" # 2'b10 = "SHIFTREG_90deg" # 2'b11 = "SHIFTREG_0deg" "PLLOUT_SELECT_B_0": ( 16, 33, "PLLCONFIG_2"), "PLLOUT_SELECT_B_1": ( 16, 33, "PLLCONFIG_3"), # Numeric Parameters "SHIFTREG_DIV_MODE": ( 16, 33, "PLLCONFIG_4"), "FDA_FEEDBACK_0": ( 16, 33, "PLLCONFIG_9"), "FDA_FEEDBACK_1": ( 17, 33, "PLLCONFIG_1"), "FDA_FEEDBACK_2": ( 17, 33, "PLLCONFIG_2"), "FDA_FEEDBACK_3": ( 17, 33, "PLLCONFIG_3"), "FDA_RELATIVE_0": ( 17, 33, "PLLCONFIG_5"), "FDA_RELATIVE_1": ( 17, 33, "PLLCONFIG_6"), "FDA_RELATIVE_2": ( 17, 33, "PLLCONFIG_7"), "FDA_RELATIVE_3": ( 17, 33, "PLLCONFIG_8"), "DIVR_0": ( 14, 33, "PLLCONFIG_1"), "DIVR_1": ( 14, 33, "PLLCONFIG_2"), "DIVR_2": ( 14, 33, "PLLCONFIG_3"), "DIVR_3": ( 14, 33, "PLLCONFIG_4"), "DIVF_0": ( 14, 33, "PLLCONFIG_5"), "DIVF_1": ( 14, 33, "PLLCONFIG_6"), "DIVF_2": ( 14, 33, "PLLCONFIG_7"), "DIVF_3": ( 14, 33, "PLLCONFIG_8"), "DIVF_4": ( 14, 33, "PLLCONFIG_9"), "DIVF_5": ( 15, 33, "PLLCONFIG_1"), "DIVF_6": ( 15, 33, "PLLCONFIG_2"), "DIVQ_0": ( 15, 33, "PLLCONFIG_3"), "DIVQ_1": ( 15, 33, "PLLCONFIG_4"), "DIVQ_2": ( 15, 33, "PLLCONFIG_5"), "FILTER_RANGE_0": ( 15, 33, "PLLCONFIG_6"), "FILTER_RANGE_1": ( 15, 33, "PLLCONFIG_7"), "FILTER_RANGE_2": ( 15, 33, "PLLCONFIG_8"), "TEST_MODE": ( 16, 33, "PLLCONFIG_8"), # PLL Ports "PLLOUT_A": ( 16, 33, 1), "PLLOUT_B": ( 17, 33, 0), "REFERENCECLK": ( 13, 33, "fabout"), "EXTFEEDBACK": ( 14, 33, "fabout"), "DYNAMICDELAY_0": ( 5, 33, "fabout"), "DYNAMICDELAY_1": ( 6, 33, "fabout"), "DYNAMICDELAY_2": ( 7, 33, "fabout"), "DYNAMICDELAY_3": ( 8, 33, "fabout"), "DYNAMICDELAY_4": ( 9, 33, "fabout"), "DYNAMICDELAY_5": ( 10, 33, "fabout"), "DYNAMICDELAY_6": ( 11, 33, "fabout"), "DYNAMICDELAY_7": ( 12, 33, "fabout"), "LOCK": ( 1, 32, "neigh_op_tnl_1"), "BYPASS": ( 19, 33, "fabout"), "RESETB": ( 20, 33, "fabout"), "LATCHINPUTVALUE": ( 15, 33, "fabout"), "SDO": ( 32, 32, "neigh_op_tnr_1"), "SDI": ( 22, 33, "fabout"), "SCLK": ( 21, 33, "fabout"), }, } padin_pio_db = { "1k": [ (13, 8, 1), # glb_netwk_0 ( 0, 8, 1), # glb_netwk_1 ( 7, 17, 0), # glb_netwk_2 ( 7, 0, 0), # glb_netwk_3 ( 0, 9, 0), # glb_netwk_4 (13, 9, 0), # glb_netwk_5 ( 6, 0, 1), # glb_netwk_6 ( 6, 17, 1), # glb_netwk_7 ], "8k": [ (33, 16, 1), ( 0, 16, 1), (17, 33, 0), (17, 0, 0), ( 0, 17, 0), (33, 17, 0), (16, 0, 1), (16, 33, 1), ] } ieren_db = { "1k": [ # IO-block (X, Y, Z) <-> IeRen-block (X, Y, Z) ( 0, 2, 0, 0, 2, 1), ( 0, 2, 1, 0, 2, 0), ( 0, 3, 0, 0, 3, 1), ( 0, 3, 1, 0, 3, 0), ( 0, 4, 0, 0, 4, 1), ( 0, 4, 1, 0, 4, 0), ( 0, 5, 0, 0, 5, 1), ( 0, 5, 1, 0, 5, 0), ( 0, 6, 0, 0, 6, 1), ( 0, 6, 1, 0, 6, 0), ( 0, 8, 0, 0, 8, 1), ( 0, 8, 1, 0, 8, 0), ( 0, 9, 0, 0, 9, 1), ( 0, 9, 1, 0, 9, 0), ( 0, 10, 0, 0, 10, 1), ( 0, 10, 1, 0, 10, 0), ( 0, 11, 0, 0, 11, 1), ( 0, 11, 1, 0, 11, 0), ( 0, 12, 0, 0, 12, 1), ( 0, 12, 1, 0, 12, 0), ( 0, 13, 0, 0, 13, 1), ( 0, 13, 1, 0, 13, 0), ( 0, 14, 0, 0, 14, 1), ( 0, 14, 1, 0, 14, 0), ( 1, 0, 0, 1, 0, 0), ( 1, 0, 1, 1, 0, 1), ( 1, 17, 0, 1, 17, 0), ( 1, 17, 1, 1, 17, 1), ( 2, 0, 0, 2, 0, 0), ( 2, 0, 1, 2, 0, 1), ( 2, 17, 0, 2, 17, 0), ( 2, 17, 1, 2, 17, 1), ( 3, 0, 0, 3, 0, 0), ( 3, 0, 1, 3, 0, 1), ( 3, 17, 0, 3, 17, 0), ( 3, 17, 1, 3, 17, 1), ( 4, 0, 0, 4, 0, 0), ( 4, 0, 1, 4, 0, 1), ( 4, 17, 0, 4, 17, 0), ( 4, 17, 1, 4, 17, 1), ( 5, 0, 0, 5, 0, 0), ( 5, 0, 1, 5, 0, 1), ( 5, 17, 0, 5, 17, 0), ( 5, 17, 1, 5, 17, 1), ( 6, 0, 0, 7, 0, 0), ( 6, 0, 1, 6, 0, 0), ( 6, 17, 0, 6, 17, 0), ( 6, 17, 1, 6, 17, 1), ( 7, 0, 0, 6, 0, 1), ( 7, 0, 1, 7, 0, 1), ( 7, 17, 0, 7, 17, 0), ( 7, 17, 1, 7, 17, 1), ( 8, 0, 0, 8, 0, 0), ( 8, 0, 1, 8, 0, 1), ( 8, 17, 0, 8, 17, 0), ( 8, 17, 1, 8, 17, 1), ( 9, 0, 0, 9, 0, 0), ( 9, 0, 1, 9, 0, 1), ( 9, 17, 0, 10, 17, 0), ( 9, 17, 1, 10, 17, 1), (10, 0, 0, 10, 0, 0), (10, 0, 1, 10, 0, 1), (10, 17, 0, 9, 17, 0), (10, 17, 1, 9, 17, 1), (11, 0, 0, 11, 0, 0), (11, 0, 1, 11, 0, 1), (11, 17, 0, 11, 17, 0), (11, 17, 1, 11, 17, 1), (12, 0, 0, 12, 0, 0), (12, 0, 1, 12, 0, 1), (12, 17, 0, 12, 17, 0), (12, 17, 1, 12, 17, 1), (13, 1, 0, 13, 1, 0), (13, 1, 1, 13, 1, 1), (13, 2, 0, 13, 2, 0), (13, 2, 1, 13, 2, 1), (13, 3, 1, 13, 3, 1), (13, 4, 0, 13, 4, 0), (13, 4, 1, 13, 4, 1), (13, 6, 0, 13, 6, 0), (13, 6, 1, 13, 6, 1), (13, 7, 0, 13, 7, 0), (13, 7, 1, 13, 7, 1), (13, 8, 0, 13, 8, 0), (13, 8, 1, 13, 8, 1), (13, 9, 0, 13, 9, 0), (13, 9, 1, 13, 9, 1), (13, 11, 0, 13, 10, 0), (13, 11, 1, 13, 10, 1), (13, 12, 0, 13, 11, 0), (13, 12, 1, 13, 11, 1), (13, 13, 0, 13, 13, 0), (13, 13, 1, 13, 13, 1), (13, 14, 0, 13, 14, 0), (13, 14, 1, 13, 14, 1), (13, 15, 0, 13, 15, 0), (13, 15, 1, 13, 15, 1), ], "8k": [ ( 0, 3, 0, 0, 3, 0), ( 0, 3, 1, 0, 3, 1), ( 0, 4, 0, 0, 4, 0), ( 0, 4, 1, 0, 4, 1), ( 0, 5, 0, 0, 5, 0), ( 0, 5, 1, 0, 5, 1), ( 0, 6, 0, 0, 6, 0), ( 0, 6, 1, 0, 6, 1), ( 0, 7, 0, 0, 7, 0), ( 0, 7, 1, 0, 7, 1), ( 0, 8, 0, 0, 8, 0), ( 0, 8, 1, 0, 8, 1), ( 0, 9, 0, 0, 9, 0), ( 0, 9, 1, 0, 9, 1), ( 0, 10, 0, 0, 10, 0), ( 0, 10, 1, 0, 10, 1), ( 0, 11, 0, 0, 11, 0), ( 0, 11, 1, 0, 11, 1), ( 0, 12, 0, 0, 12, 0), ( 0, 12, 1, 0, 12, 1), ( 0, 13, 0, 0, 13, 0), ( 0, 13, 1, 0, 13, 1), ( 0, 14, 0, 0, 14, 0), ( 0, 14, 1, 0, 14, 1), ( 0, 16, 0, 0, 16, 0), ( 0, 16, 1, 0, 16, 1), ( 0, 17, 0, 0, 17, 0), ( 0, 17, 1, 0, 17, 1), ( 0, 18, 0, 0, 18, 0), ( 0, 18, 1, 0, 18, 1), ( 0, 19, 0, 0, 19, 0), ( 0, 19, 1, 0, 19, 1), ( 0, 20, 0, 0, 20, 0), ( 0, 20, 1, 0, 20, 1), ( 0, 21, 0, 0, 21, 0), ( 0, 21, 1, 0, 21, 1), ( 0, 22, 0, 0, 22, 0), ( 0, 22, 1, 0, 22, 1), ( 0, 23, 0, 0, 23, 0), ( 0, 23, 1, 0, 23, 1), ( 0, 24, 0, 0, 24, 0), ( 0, 24, 1, 0, 24, 1), ( 0, 25, 0, 0, 25, 0), ( 0, 25, 1, 0, 25, 1), ( 0, 27, 0, 0, 27, 0), ( 0, 27, 1, 0, 27, 1), ( 0, 28, 0, 0, 28, 0), ( 0, 28, 1, 0, 28, 1), ( 0, 30, 0, 0, 30, 0), ( 0, 30, 1, 0, 30, 1), ( 0, 31, 0, 0, 31, 0), ( 0, 31, 1, 0, 31, 1), ( 1, 33, 0, 1, 33, 0), ( 1, 33, 1, 1, 33, 1), ( 2, 0, 0, 2, 0, 0), ( 2, 0, 1, 2, 0, 1), ( 2, 33, 0, 2, 33, 0), ( 2, 33, 1, 2, 33, 1), ( 3, 0, 0, 3, 0, 0), ( 3, 0, 1, 3, 0, 1), ( 3, 33, 0, 3, 33, 0), ( 3, 33, 1, 3, 33, 1), ( 4, 0, 0, 4, 0, 0), ( 4, 0, 1, 4, 0, 1), ( 4, 33, 0, 4, 33, 0), ( 4, 33, 1, 4, 33, 1), ( 5, 0, 0, 5, 0, 0), ( 5, 0, 1, 5, 0, 1), ( 5, 33, 0, 5, 33, 0), ( 5, 33, 1, 5, 33, 1), ( 6, 0, 0, 6, 0, 0), ( 6, 0, 1, 6, 0, 1), ( 6, 33, 0, 6, 33, 0), ( 6, 33, 1, 6, 33, 1), ( 7, 0, 0, 7, 0, 0), ( 7, 0, 1, 7, 0, 1), ( 7, 33, 0, 7, 33, 0), ( 7, 33, 1, 7, 33, 1), ( 8, 0, 0, 8, 0, 0), ( 8, 0, 1, 8, 0, 1), ( 8, 33, 0, 8, 33, 0), ( 8, 33, 1, 8, 33, 1), ( 9, 0, 0, 9, 0, 0), ( 9, 0, 1, 9, 0, 1), ( 9, 33, 0, 9, 33, 0), ( 9, 33, 1, 9, 33, 1), (10, 0, 0, 10, 0, 0), (10, 0, 1, 10, 0, 1), (10, 33, 0, 10, 33, 0), (10, 33, 1, 10, 33, 1), (11, 0, 0, 11, 0, 0), (11, 0, 1, 11, 0, 1), (11, 33, 0, 11, 33, 0), (11, 33, 1, 11, 33, 1), (12, 0, 0, 12, 0, 0), (12, 0, 1, 12, 0, 1), (12, 33, 0, 12, 33, 0), (13, 0, 0, 13, 0, 0), (13, 0, 1, 13, 0, 1), (13, 33, 0, 13, 33, 0), (13, 33, 1, 13, 33, 1), (14, 0, 0, 14, 0, 0), (14, 0, 1, 14, 0, 1), (14, 33, 0, 14, 33, 0), (14, 33, 1, 14, 33, 1), (15, 0, 0, 15, 0, 0), (15, 0, 1, 15, 0, 1), (16, 0, 0, 16, 0, 0), (16, 0, 1, 16, 0, 1), (16, 33, 0, 16, 33, 0), (16, 33, 1, 16, 33, 1), (17, 0, 0, 17, 0, 0), (17, 0, 1, 17, 0, 1), (17, 33, 0, 17, 33, 0), (17, 33, 1, 17, 33, 1), (18, 33, 0, 18, 33, 0), (18, 33, 1, 18, 33, 1), (19, 0, 0, 19, 0, 0), (19, 0, 1, 19, 0, 1), (19, 33, 0, 19, 33, 0), (19, 33, 1, 19, 33, 1), (20, 0, 0, 20, 0, 0), (20, 0, 1, 20, 0, 1), (20, 33, 0, 20, 33, 0), (20, 33, 1, 20, 33, 1), (21, 0, 0, 21, 0, 0), (21, 0, 1, 21, 0, 1), (21, 33, 0, 21, 33, 0), (21, 33, 1, 21, 33, 1), (22, 0, 0, 22, 0, 0), (22, 0, 1, 22, 0, 1), (22, 33, 0, 22, 33, 0), (22, 33, 1, 22, 33, 1), (23, 0, 0, 23, 0, 0), (23, 0, 1, 23, 0, 1), (23, 33, 0, 23, 33, 0), (23, 33, 1, 23, 33, 1), (24, 0, 0, 24, 0, 0), (24, 0, 1, 24, 0, 1), (24, 33, 0, 24, 33, 0), (24, 33, 1, 24, 33, 1), (25, 0, 0, 25, 0, 0), (25, 33, 0, 25, 33, 0), (25, 33, 1, 25, 33, 1), (26, 0, 0, 26, 0, 0), (26, 0, 1, 26, 0, 1), (26, 33, 0, 26, 33, 0), (26, 33, 1, 26, 33, 1), (27, 0, 0, 27, 0, 0), (27, 0, 1, 27, 0, 1), (27, 33, 0, 27, 33, 0), (27, 33, 1, 27, 33, 1), (28, 0, 0, 28, 0, 0), (28, 33, 1, 28, 33, 1), (29, 0, 0, 29, 0, 0), (29, 0, 1, 29, 0, 1), (29, 33, 0, 29, 33, 0), (29, 33, 1, 29, 33, 1), (30, 0, 0, 30, 0, 0), (30, 0, 1, 30, 0, 1), (30, 33, 0, 30, 33, 0), (30, 33, 1, 30, 33, 1), (31, 0, 0, 31, 0, 0), (31, 0, 1, 31, 0, 1), (31, 33, 0, 31, 33, 0), (31, 33, 1, 31, 33, 1), (33, 1, 0, 33, 1, 0), (33, 1, 1, 33, 1, 1), (33, 2, 0, 33, 2, 0), (33, 2, 1, 33, 2, 1), (33, 3, 0, 33, 3, 0), (33, 3, 1, 33, 3, 1), (33, 4, 0, 33, 4, 0), (33, 4, 1, 33, 4, 1), (33, 5, 0, 33, 5, 0), (33, 5, 1, 33, 5, 1), (33, 6, 0, 33, 6, 0), (33, 6, 1, 33, 6, 1), (33, 7, 0, 33, 7, 0), (33, 7, 1, 33, 7, 1), (33, 8, 0, 33, 8, 0), (33, 9, 0, 33, 9, 0), (33, 9, 1, 33, 9, 1), (33, 10, 0, 33, 10, 0), (33, 10, 1, 33, 10, 1), (33, 11, 0, 33, 11, 0), (33, 11, 1, 33, 11, 1), (33, 12, 0, 33, 12, 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"A5", 8, 33, 0), ( "A6", 9, 33, 0), ( "A7", 12, 33, 0), ( "A9", 18, 33, 1), ("A10", 22, 33, 1), ("A11", 22, 33, 0), ("A15", 27, 33, 0), ("A16", 27, 33, 1), ( "B1", 0, 30, 0), ( "B2", 0, 31, 0), ( "B3", 3, 33, 0), ( "B4", 6, 33, 1), ( "B5", 7, 33, 1), ( "B6", 10, 33, 1), ( "B7", 11, 33, 0), ( "B8", 13, 33, 0), ( "B9", 16, 33, 0), ("B10", 24, 33, 0), ("B11", 23, 33, 1), ("B12", 24, 33, 1), ("B13", 26, 33, 1), ("B14", 30, 33, 0), ("B15", 31, 33, 0), ("B16", 33, 30, 0), ( "C1", 0, 28, 1), ( "C2", 0, 28, 0), ( "C3", 1, 33, 0), ( "C4", 3, 33, 1), ( "C5", 4, 33, 0), ( "C6", 10, 33, 0), ( "C7", 11, 33, 1), ( "C8", 17, 33, 0), ( "C9", 20, 33, 0), ("C10", 23, 33, 0), ("C11", 25, 33, 1), ("C12", 29, 33, 1), ("C13", 28, 33, 1), ("C14", 31, 33, 1), ("C16", 33, 28, 0), ( "D1", 0, 25, 0), ( "D2", 0, 27, 0), ( "D3", 1, 33, 1), ( "D4", 2, 33, 1), ( "D5", 5, 33, 0), ( "D6", 8, 33, 1), ( "D7", 9, 33, 1), ( "D8", 14, 33, 1), ( "D9", 19, 33, 0), ("D10", 20, 33, 1), ("D11", 25, 33, 0), ("D13", 30, 33, 1), ("D14", 33, 31, 0), ("D15", 33, 26, 0), ("D16", 33, 24, 0), ( "E2", 0, 23, 0), ( "E3", 0, 24, 0), ( "E4", 0, 31, 1), ( "E5", 2, 33, 0), ( "E6", 7, 33, 0), ( "E9", 19, 33, 1), ("E10", 26, 33, 0), ("E11", 29, 33, 0), ("E13", 33, 30, 1), ("E14", 33, 27, 1), ("E16", 33, 23, 0), ( "F1", 0, 20, 0), ( "F2", 0, 21, 0), ( "F3", 0, 22, 0), ( "F4", 0, 27, 1), ( "F5", 0, 30, 1), ( "F7", 16, 33, 1), ( "F9", 17, 33, 1), ("F11", 33, 26, 1), ("F12", 33, 25, 1), ("F13", 33, 28, 1), ("F14", 33, 25, 0), ("F15", 33, 22, 0), ("F16", 33, 21, 0), ( "G1", 0, 17, 0), ( "G2", 0, 19, 0), ( "G3", 0, 22, 1), ( "G4", 0, 24, 1), ( "G5", 0, 25, 1), ("G10", 33, 20, 1), ("G11", 33, 21, 1), ("G12", 33, 24, 1), ("G13", 33, 23, 1), ("G14", 33, 22, 1), ("G15", 33, 20, 0), ("G16", 33, 19, 0), ( "H1", 0, 16, 0), ( "H2", 0, 18, 0), ( "H3", 0, 21, 1), ( "H4", 0, 19, 1), ( "H5", 0, 23, 1), ( "H6", 0, 20, 1), ("H11", 33, 16, 1), ("H12", 33, 19, 1), ("H13", 33, 16, 0), ("H14", 33, 17, 1), ("H16", 33, 17, 0), ( "J1", 0, 14, 0), ( "J2", 0, 14, 1), ( "J3", 0, 16, 1), ( "J4", 0, 18, 1), ( "J5", 0, 17, 1), ("J10", 33, 7, 1), ("J11", 33, 9, 1), ("J12", 33, 14, 1), ("J13", 33, 15, 0), ("J14", 33, 13, 1), ("J15", 33, 11, 1), ("J16", 33, 15, 1), ( "K1", 0, 13, 1), ( "K3", 0, 13, 0), ( "K4", 0, 11, 1), ( "K5", 0, 9, 1), ( "K9", 17, 0, 0), ("K11", 29, 0, 0), ("K12", 33, 6, 1), ("K13", 33, 10, 1), ("K14", 33, 11, 0), ("K15", 33, 12, 0), ("K16", 33, 13, 0), ( "L1", 0, 12, 0), ( "L3", 0, 10, 0), ( "L4", 0, 12, 1), ( "L5", 0, 6, 1), ( "L6", 0, 10, 1), ( "L7", 0, 8, 1), ( "L9", 13, 0, 0), ("L10", 19, 0, 1), ("L11", 26, 0, 1), ("L12", 33, 4, 1), ("L13", 33, 5, 1), ("L14", 33, 6, 0), ("L16", 33, 10, 0), ( "M1", 0, 11, 0), ( "M2", 0, 9, 0), ( "M3", 0, 7, 0), ( "M4", 0, 5, 0), ( "M5", 0, 4, 0), ( "M6", 0, 7, 1), ( "M7", 8, 0, 0), ( "M8", 10, 0, 0), ( "M9", 16, 0, 0), ("M11", 23, 0, 1), ("M12", 27, 0, 1), ("M13", 33, 3, 1), ("M14", 33, 4, 0), ("M15", 33, 8, 0), ("M16", 33, 7, 0), ( "N2", 0, 8, 0), ( "N3", 0, 6, 0), ( "N4", 0, 3, 0), ( "N5", 4, 0, 0), ( "N6", 2, 0, 0), ( "N7", 9, 0, 0), ( "N9", 15, 0, 0), ("N10", 20, 0, 1), ("N12", 26, 0, 0), ("N16", 33, 5, 0), ( "P1", 0, 5, 1), ( "P2", 0, 4, 1), ( "P4", 3, 0, 0), ( "P5", 5, 0, 0), ( "P6", 9, 0, 1), ( "P7", 14, 0, 1), ( "P8", 12, 0, 0), ( "P9", 17, 0, 1), ("P10", 20, 0, 0), ("P11", 30, 0, 1), ("P12", 30, 0, 0), ("P13", 29, 0, 1), ("P14", 33, 2, 0), ("P15", 33, 2, 1), ("P16", 33, 3, 0), ( "R1", 0, 3, 1), ( "R2", 3, 0, 1), ( "R3", 5, 0, 1), ( "R4", 7, 0, 1), ( "R5", 6, 0, 0), ( "R6", 11, 0, 1), ( "R9", 16, 0, 1), ("R10", 19, 0, 0), ("R11", 31, 0, 0), ("R12", 31, 0, 1), ("R14", 33, 1, 0), ("R15", 33, 1, 1), ("R16", 28, 0, 0), ( "T1", 2, 0, 1), ( "T2", 4, 0, 1), ( "T3", 6, 0, 1), ( "T5", 10, 0, 1), ( "T6", 12, 0, 1), ( "T7", 13, 0, 1), ( "T8", 14, 0, 0), ( "T9", 15, 0, 1), ("T10", 21, 0, 0), ("T11", 21, 0, 1), ("T13", 24, 0, 0), ("T14", 23, 0, 0), ("T15", 22, 0, 1), ("T16", 27, 0, 0), ] } iotile_full_db = parse_db(iceboxdb.database_io_txt) logictile_db = parse_db(iceboxdb.database_logic_txt) logictile_8k_db = parse_db(iceboxdb.database_logic_txt, True) rambtile_db = parse_db(iceboxdb.database_ramb_txt) ramttile_db = parse_db(iceboxdb.database_ramt_txt) rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, True) ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, True) iotile_l_db = list() iotile_r_db = list() iotile_t_db = list() iotile_b_db = list() for entry in iotile_full_db: if entry[1] == "buffer" and entry[2].startswith("IO_L."): new_entry = entry[:] new_entry[2] = new_entry[2][5:] iotile_l_db.append(new_entry) elif entry[1] == "buffer" and entry[2].startswith("IO_R."): new_entry = entry[:] new_entry[2] = new_entry[2][5:] iotile_r_db.append(new_entry) elif entry[1] == "buffer" and entry[2].startswith("IO_T."): new_entry = entry[:] new_entry[2] = new_entry[2][5:] iotile_t_db.append(new_entry) elif entry[1] == "buffer" and entry[2].startswith("IO_B."): new_entry = entry[:] new_entry[2] = new_entry[2][5:] iotile_b_db.append(new_entry) else: iotile_l_db.append(entry) iotile_r_db.append(entry) iotile_t_db.append(entry) iotile_b_db.append(entry) logictile_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"]) logictile_db.append([["B1[50]"], "CarryInSet"]) logictile_8k_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"]) logictile_8k_db.append([["B1[50]"], "CarryInSet"]) for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, logictile_8k_db, rambtile_db, ramttile_db, rambtile_8k_db, ramttile_8k_db]: for entry in db: if entry[1] in ("buffer", "routing"): entry[2] = netname_normalize(entry[2], ramb=(db == rambtile_db), ramt=(db == ramttile_db), ramb_8k=(db == rambtile_8k_db), ramt_8k=(db == ramttile_8k_db)) entry[3] = netname_normalize(entry[3], ramb=(db == rambtile_db), ramt=(db == ramttile_db), ramb_8k=(db == rambtile_8k_db), ramt_8k=(db == ramttile_8k_db)) unique_entries = dict() while db: entry = db.pop() key = " ".join(entry[1:]) + str(entry) unique_entries[key] = entry for key in sorted(unique_entries): db.append(unique_entries[key]) if __name__ == "__main__": run_checks() fpga-icestorm-0~20160913git266e758/icebox/icebox_chipdb.py000077500000000000000000000177431276746530600230160ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import icebox import getopt, sys, re mode_8k = False def usage(): print(""" Usage: icebox_chipdb [options] [bitmap.asc] -8 create chipdb for 8k device """) sys.exit(0) try: opts, args = getopt.getopt(sys.argv[1:], "8") except: usage() for o, a in opts: if o == "-8": mode_8k = True else: usage() ic = icebox.iceconfig() if mode_8k: ic.setup_empty_8k() else: ic.setup_empty_1k() all_tiles = set() for x in range(ic.max_x+1): for y in range(ic.max_y+1): if ic.tile(x, y) is not None: all_tiles.add((x, y)) seg_to_net = dict() net_to_segs = list() print("""# # IceBox Chip Database Dump (iCE40 %s) # # # Quick File Format Reference: # ---------------------------- # # .device DEVICE WIDTH HEIGHT NUM_NETS # # declares the device type # # # .pins PACKAGE # PIN_NUM TILE_X TILE_Y PIO_NUM # ... # # associates a package pin with an IO tile and block, and global network # # # .gbufin # TILE_X TILE_Y GLB_NUM # ... # # associates an IO tile with the global network can drive via fabout # # # .gbufpin # TILE_X TILE_Y PIO_NUM GLB_NUM # ... # # associates an IO tile with the global network can drive via the pad # # # .iolatch # TILE_X TILE_Y # ... # # specifies the IO tiles that drive the latch signal for the bank via fabout # # # .ieren # PIO_TILE_X PIO_TILE_Y PIO_NUM IEREN_TILE_X IEREN_TILE_Y IEREN_NUM # ... # # associates an IO block with an IeRen-block # # # .colbuf # SOURCE_TILE_X SOURCE_TILE_Y DEST_TILE_X DEST_TILE_Y # ... # # declares the positions of the column buffers # # # .io_tile X Y # .logic_tile X Y # .ramb_tile X Y # .ramt_tile X Y # # declares the existence of a IO/LOGIC/RAM tile with the given coordinates # # # .io_tile_bits COLUMNS ROWS # .logic_tile_bits COLUMNS ROWS # .ramb_tile_bits COLUMNS ROWS # .ramt_tile_bits COLUMNS ROWS # FUNCTION_1 CONFIG_BITS_NAMES_1 # FUNCTION_2 CONFIG_BITS_NAMES_2 # ... # # declares non-routing configuration bits of IO/LOGIC/RAM tiles # # # .extra_cell X Y # KEY MULTI-FIELD-VALUE # .... # # declares a special-purpose cell that is not part of the FPGA fabric # # # .extra_bits # FUNCTION BANK_NUM ADDR_X ADDR_Y # ... # # declares non-routing global configuration bits # # # .net NET_INDEX # X1 Y1 name1 # X2 Y2 name2 # ... # # declares a net on the chip and lists its various names in different tiles # # # .buffer X Y DST_NET_INDEX CONFIG_BITS_NAMES # CONFIG_BITS_VALUES_1 SRC_NET_INDEX_1 # CONFIG_BITS_VALUES_2 SRC_NET_INDEX_2 # ... # # declares a buffer in the specified tile # # # .routing X Y DST_NET_INDEX CONFIG_BITS_NAMES # CONFIG_BITS_VALUES_1 SRC_NET_INDEX_1 # CONFIG_BITS_VALUES_2 SRC_NET_INDEX_2 # ... # # declares a routing switch in the specified tile # """ % ic.device) all_group_segments = ic.group_segments(all_tiles, connect_gb=False) print(".device %s %d %d %d" % (ic.device, ic.max_x+1, ic.max_y+1, len(all_group_segments))) print() for key in list(icebox.pinloc_db.keys()): key_dev, key_package = key.split("-") if key_dev == ic.device: print(".pins %s" % (key_package)) for entry in sorted(icebox.pinloc_db[key]): print("%s %d %d %d" % entry) print() print(".gbufin") for entry in sorted(ic.gbufin_db()): print(" ".join(["%d" % k for k in entry])) print() print(".gbufpin") for padin, pio in enumerate(ic.padin_pio_db()): entry = pio + (padin,) print(" ".join(["%d" % k for k in entry])) print() print(".iolatch") for entry in sorted(ic.iolatch_db()): print(" ".join(["%d" % k for k in entry])) print() print(".ieren") for entry in sorted(ic.ieren_db()): print(" ".join(["%d" % k for k in entry])) print() print(".colbuf") for entry in sorted(ic.colbuf_db()): print(" ".join(["%d" % k for k in entry])) print() for idx in sorted(ic.io_tiles): print(".io_tile %d %d" % idx) print() for idx in sorted(ic.logic_tiles): print(".logic_tile %d %d" % idx) print() for idx in sorted(ic.ramb_tiles): print(".ramb_tile %d %d" % idx) print() for idx in sorted(ic.ramt_tiles): print(".ramt_tile %d %d" % idx) print() def print_tile_nonrouting_bits(tile_type, idx): tx = idx[0] ty = idx[1] tile = ic.tile(tx, ty) print(".%s_tile_bits %d %d" % (tile_type, len(tile[0]), len(tile))) function_bits = dict() for entry in ic.tile_db(tx, ty): if not ic.tile_has_entry(tx, ty, entry): continue if entry[1] in ("routing", "buffer"): continue func = ".".join(entry[1:]) function_bits[func] = entry[0] for x in sorted(function_bits): print(" ".join([x] + function_bits[x])) print() print_tile_nonrouting_bits("logic", list(ic.logic_tiles.keys())[0]) print_tile_nonrouting_bits("io", list(ic.io_tiles.keys())[0]) print_tile_nonrouting_bits("ramb", list(ic.ramb_tiles.keys())[0]) print_tile_nonrouting_bits("ramt", list(ic.ramt_tiles.keys())[0]) print(".extra_cell 0 0 WARMBOOT") for key in sorted(icebox.warmbootinfo_db[ic.device]): print("%s %s" % (key, " ".join([str(k) for k in icebox.warmbootinfo_db[ic.device][key]]))) print() for pllid in ic.pll_list(): pllinfo = icebox.pllinfo_db[pllid] print(".extra_cell %d %d PLL" % pllinfo["LOC"]) locked_pkgs = [] for entry in icebox.noplls_db: if pllid in icebox.noplls_db[entry]: locked_pkgs.append(entry.split("-")[1]) if len(locked_pkgs) > 0: print("LOCKED %s" % " ".join(locked_pkgs)) for key in sorted(pllinfo): if key != "LOC": print("%s %s" % (key, " ".join([str(k) for k in pllinfo[key]]))) print() print(".extra_bits") extra_bits = dict() for idx in sorted(ic.extra_bits_db()): extra_bits[".".join(ic.extra_bits_db()[idx])] = " ".join(["%d" % k for k in idx]) for idx in sorted(extra_bits): print("%s %s" % (idx, extra_bits[idx])) print() for group in sorted(all_group_segments): netidx = len(net_to_segs) net_to_segs.append(group) print(".net %d" % netidx) for seg in group: print("%d %d %s" % seg) assert seg not in seg_to_net seg_to_net[seg] = netidx print() for idx in sorted(all_tiles): db = ic.tile_db(idx[0], idx[1]) db_by_bits = dict() for entry in db: if entry[1] in ("buffer", "routing") and ic.tile_has_net(idx[0], idx[1], entry[2]) and ic.tile_has_net(idx[0], idx[1], entry[3]): bits = tuple([entry[1]] + sorted([bit.replace("!", "") for bit in entry[0]])) db_by_bits.setdefault(bits, list()).append(entry) for bits in sorted(db_by_bits): dst_net = None for entry in sorted(db_by_bits[bits]): assert (idx[0], idx[1], entry[3]) in seg_to_net if dst_net is None: dst_net = seg_to_net[(idx[0], idx[1], entry[3])] else: assert dst_net == seg_to_net[(idx[0], idx[1], entry[3])] print(".%s %d %d %d %s" % (bits[0], idx[0], idx[1], dst_net, " ".join(bits[1:]))) for entry in sorted(db_by_bits[bits]): pattern = "" for bit in bits[1:]: pattern += "1" if bit in entry[0] else "0" assert (idx[0], idx[1], entry[2]) in seg_to_net print("%s %d" % (pattern, seg_to_net[(idx[0], idx[1], entry[2])])) print() fpga-icestorm-0~20160913git266e758/icebox/icebox_colbuf.py000077500000000000000000000115001276746530600230200ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import icebox import getopt, sys, re check_mode = False fixup_mode = False def usage(): print(""" Usage: icebox_colbuf [options] [input.asc [output.asc]] -c check colbuf bits -f fix colbuf bits """) sys.exit(1) try: opts, args = getopt.getopt(sys.argv[1:], "cf") except: usage() for o, a in opts: if o == "-c": check_mode = True elif o == "-f": fixup_mode = True else: usage() if len(args) == 0: args.append("/dev/stdin") if len(args) not in [1, 2]: usage() if check_mode == fixup_mode: print("Error: Use either -c or -f!") sys.exit(1) print("Reading file '%s'.." % args[0]) ic = icebox.iceconfig() ic.read_file(args[0]) def make_cache(stmt, raw_db): cache = list() for entry in raw_db: if entry[1] == stmt and entry[2].startswith("glb_netwk_"): cache_entry = [int(entry[2][-1]), []] for bit in entry[0]: value = "1" if bit.startswith("!"): value = "0" bit = bit[1:] match = re.match("B([0-9]+)\[([0-9]+)\]", bit) cache_entry[1].append((int(match.group(1)), int(match.group(2)), value)) cache.append(cache_entry) return cache def match_cache_entry(cache_entry, tile_dat): for entry in cache_entry[1]: if tile_dat[entry[0]][entry[1]] != entry[2]: return False return True def analyze_tile(ic, cache, tile_pos): glbs = set() tile_dat = ic.tile(tile_pos[0], tile_pos[1]) for cache_entry in cache: if match_cache_entry(cache_entry, tile_dat): glbs.add(cache_entry[0]) return glbs colbuf_map = dict() used_glbs_map = dict() driven_glbs_map = dict() for entry in ic.colbuf_db(): colbuf_map[(entry[2], entry[3])] = (entry[0], entry[1]) for tiles in [ic.io_tiles, ic.logic_tiles, ic.ramb_tiles, ic.ramt_tiles]: cache = None for tile in tiles: if cache is None: cache = make_cache("buffer", ic.tile_db(tile[0], tile[1])) glbs = analyze_tile(ic, cache, tile) if len(glbs): assert tile in colbuf_map s = used_glbs_map.setdefault(colbuf_map[tile], set()) used_glbs_map[colbuf_map[tile]] = s.union(glbs) cache = None for tile in tiles: if cache is None: cache = make_cache("ColBufCtrl", ic.tile_db(tile[0], tile[1])) glbs = analyze_tile(ic, cache, tile) if len(glbs): driven_glbs_map[tile] = glbs def set_colbuf(ic, tile, bit, value): tile_dat = ic.tile(tile[0], tile[1]) tile_db = ic.tile_db(tile[0], tile[1]) for entry in tile_db: if entry[1] == "ColBufCtrl" and entry[2] == "glb_netwk_%d" % bit: match = re.match("B([0-9]+)\[([0-9]+)\]", entry[0][0]) l = tile_dat[int(match.group(1))] n = int(match.group(2)) l = l[:n] + value + l[n+1:] tile_dat[int(match.group(1))] = l return assert False error_count = 0 correct_count = 0 for tile, bits in sorted(used_glbs_map.items()): for bit in bits: if tile not in driven_glbs_map or bit not in driven_glbs_map[tile]: print("Missing driver for glb_netwk_%d in tile %s" % (bit, tile)) set_colbuf(ic, tile, bit, "1") error_count += 1 for tile, bits in sorted(driven_glbs_map.items()): for bit in bits: if tile not in used_glbs_map or bit not in used_glbs_map[tile]: print("Unused driver for glb_netwk_%d in tile %s" % (bit, tile)) set_colbuf(ic, tile, bit, "0") error_count += 1 else: # print("Correct driver for glb_netwk_%d in tile %s" % (bit, tile)) correct_count += 1 print("Found %d correct driver bits." % correct_count) if error_count != 0: if not fixup_mode: print("Found %d errors!" % error_count) sys.exit(1) ic.write_file(args[0] if len(args) == 1 else args[1]) print("Corrected %d errors." % error_count) else: print("No errors found.") fpga-icestorm-0~20160913git266e758/icebox/icebox_diff.py000077500000000000000000000070711276746530600224660ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import icebox import sys import re if len(sys.argv) != 3: print(""" Usage: icebox_diff bitmap1.asc bitmap2.asc """) sys.exit(0) print("Reading file '%s'.." % sys.argv[1]) ic1 = icebox.iceconfig() ic1.read_file(sys.argv[1]) print("Reading file '%s'.." % sys.argv[2]) ic2 = icebox.iceconfig() ic2.read_file(sys.argv[2]) def format_bits(line_nr, this_line, other_line): text = "" for i in range(len(this_line)): if this_line[i] != other_line[i]: if this_line[i] == "1": text += "%8s" % ("B%d[%d]" % (line_nr, i)) else: text += "%8s" % "" return text def explained_bits(db, tile): bits = set() mapped_bits = set() for k, line in enumerate(tile): for i in range(len(line)): if line[i] == "1": bits.add("B%d[%d]" % (k, i)) else: bits.add("!B%d[%d]" % (k, i)) text = set() for entry in db: if re.match(r"LC_", entry[1]): continue if entry[1] in ("routing", "buffer"): continue match = True for bit in entry[0]: if not bit in bits: match = False if match: text.add("<%s> %s" % (",".join(entry[0]), " ".join(entry[1:]))) return text def diff_tiles(stmt, tiles1, tiles2): for i in sorted(set(list(tiles1.keys()) + list(tiles2.keys()))): if not i in tiles1: print("+ %s %d %d" % (stmt, i[0], i[1])) for line in tiles2[i]: print("+ %s" % line) print() continue if not i in tiles2: print("- %s %d %d" % (stmt, i[0], i[1])) for line in tiles1[i]: print("- %s" % line) print() continue if tiles1[i] == tiles2[i]: continue print(" %s %d %d" % (stmt, i[0], i[1])) for c in range(len(tiles1[i])): if tiles1[i][c] == tiles2[i][c]: print(" %s" % tiles1[i][c]) else: print("- %s%s" % (tiles1[i][c], format_bits(c, tiles1[i][c], tiles2[i][c]))) print("+ %s%s" % (tiles2[i][c], format_bits(c, tiles2[i][c], tiles1[i][c]))) bits1 = explained_bits(ic1.tile_db(i[0], i[1]), tiles1[i]) bits2 = explained_bits(ic2.tile_db(i[0], i[1]), tiles2[i]) for bit in sorted(bits1): if bit not in bits2: print("- %s" % bit) for bit in sorted(bits2): if bit not in bits1: print("+ %s" % bit) print() diff_tiles(".io_tile", ic1.io_tiles, ic2.io_tiles) diff_tiles(".logic_tile", ic1.logic_tiles, ic2.logic_tiles) diff_tiles(".ramb_tile", ic1.ramb_tiles, ic2.ramb_tiles) diff_tiles(".ramt_tile", ic1.ramt_tiles, ic2.ramt_tiles) fpga-icestorm-0~20160913git266e758/icebox/icebox_explain.py000077500000000000000000000133141276746530600232130ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import icebox import getopt, sys, re print_bits = False print_map = False single_tile = None print_all = False def usage(): print(""" Usage: icebox_explain [options] [bitmap.asc] -b print config bit names for each config statement -m print tile config bitmaps -A don't skip uninteresting tiles -t ' ' print only the specified tile """) sys.exit(0) try: opts, args = getopt.getopt(sys.argv[1:], "bmAt:") except: usage() for o, a in opts: if o == "-b": print_bits = True elif o == "-m": print_map = True elif o == "-A": print_all = True elif o == "-t": single_tile = tuple([int(s) for s in a.split()]) else: usage() if len(args) == 0: args.append("/dev/stdin") if len(args) != 1: usage() print("Reading file '%s'.." % args[0]) ic = icebox.iceconfig() ic.read_file(args[0]) print("Fabric size (without IO tiles): %d x %d" % (ic.max_x-1, ic.max_y-1)) def print_tile(stmt, ic, x, y, tile, db): if single_tile is not None and single_tile != (x, y): return bits = set() mapped_bits = set() for k, line in enumerate(tile): for i in range(len(line)): if line[i] == "1": bits.add("B%d[%d]" % (k, i)) else: bits.add("!B%d[%d]" % (k, i)) if re.search(r"logic_tile", stmt): active_luts = set([i for i in range(8) if "1" in icebox.get_lutff_bits(tile, i)]) text = set() used_lc = set() text_default_mask = 0 for entry in db: if re.match(r"LC_", entry[1]): continue if entry[1] in ("routing", "buffer"): if not ic.tile_has_net(x, y, entry[2]): continue if not ic.tile_has_net(x, y, entry[3]): continue match = True for bit in entry[0]: if not bit in bits: match = False if match: for bit in entry[0]: mapped_bits.add(bit) if entry[1] == "IoCtrl" and entry[2] == "IE_0": text_default_mask |= 1 if entry[1] == "IoCtrl" and entry[2] == "IE_1": text_default_mask |= 2 if entry[1] == "RamConfig" and entry[2] == "PowerUp": text_default_mask |= 4 if print_bits: text.add("<%s> %s" % (" ".join(entry[0]), " ".join(entry[1:]))) else: text.add(" ".join(entry[1:])) bitinfo = list() print_bitinfo = False for k, line in enumerate(tile): bitinfo.append("") extra_text = "" for i in range(len(line)): if 36 <= i <= 45 and re.search(r"logic_tile", stmt): lutff_idx = k // 2 lutff_bitnum = (i-36) + 10*(k%2) if line[i] == "1": used_lc.add(lutff_idx) bitinfo[-1] += "*" else: bitinfo[-1] += "-" elif line[i] == "1" and "B%d[%d]" % (k, i) not in mapped_bits: print_bitinfo = True extra_text += " B%d[%d]" % (k, i) bitinfo[-1] += "?" else: bitinfo[-1] += "+" if line[i] == "1" else "-" bitinfo[-1] += extra_text for lcidx in sorted(used_lc): lutff_options = "".join(icebox.get_lutff_seq_bits(tile, lcidx)) if lutff_options[0] == "1": lutff_options += " CarryEnable" if lutff_options[1] == "1": lutff_options += " DffEnable" if lutff_options[2] == "1": lutff_options += " Set_NoReset" if lutff_options[3] == "1": lutff_options += " AsyncSetReset" text.add("LC_%d %s %s" % (lcidx, "".join(icebox.get_lutff_lut_bits(tile, lcidx)), lutff_options)) if not print_bitinfo and not print_all: if text_default_mask == 3 and len(text) == 2: return if text_default_mask == 4 and len(text) == 1: return if len(text) or print_bitinfo or print_all: print("\n%s" % stmt) if print_bitinfo: print("Warning: No DB entries for some bits:") if print_bitinfo or print_map: for k, line in enumerate(bitinfo): print("%4s %s" % ("B%d" % k, line)) for line in sorted(text): print(line) for idx in ic.io_tiles: print_tile(".io_tile %d %d" % idx, ic, idx[0], idx[1], ic.io_tiles[idx], ic.tile_db(idx[0], idx[1])) for idx in ic.logic_tiles: print_tile(".logic_tile %d %d" % idx, ic, idx[0], idx[1], ic.logic_tiles[idx], ic.tile_db(idx[0], idx[1])) for idx in ic.ramb_tiles: print_tile(".ramb_tile %d %d" % idx, ic, idx[0], idx[1], ic.ramb_tiles[idx], ic.tile_db(idx[0], idx[1])) for idx in ic.ramt_tiles: print_tile(".ramt_tile %d %d" % idx, ic, idx[0], idx[1], ic.ramt_tiles[idx], ic.tile_db(idx[0], idx[1])) for bit in ic.extra_bits: print() print(".extra_bit %d %d %d" % bit) print(" ".join(ic.lookup_extra_bit(bit))) print() fpga-icestorm-0~20160913git266e758/icebox/icebox_html.py000077500000000000000000000612461276746530600225260ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import icebox import getopt, sys, os, re chipname = "iCE40 HX1K" chipdbfile = "chipdb-1k.txt" outdir = None mode8k = False tx, ty = 0, 0 def usage(): print("Usage: %s [options]" % sys.argv[0]) print(" -x tile_x_coordinate") print(" -y tile_y_coordinate") print(" -d outdir") print(" -8") sys.exit(0) try: opts, args = getopt.getopt(sys.argv[1:], "x:y:d:8") except: usage() for o, a in opts: if o == "-x": tx = int(a) elif o == "-y": ty = int(a) elif o == "-d": outdir = a elif o == "-8": mode8k = True chipname = "iCE40 HX8K" chipdbfile = "chipdb-8k.txt" else: usage() if len(args) != 0: usage() ic = icebox.iceconfig() mktiles = set() if mode8k: ic.setup_empty_8k() for x in list(range(1, 3)) + list(range(8-2, 8+3)) + list(range(15, 19)) + list(range(25-2, 25+3)) + list(range(33-2, 33)): mktiles.add((x, 0)) mktiles.add((x, 33)) for x in list(range(0, 3)) + list(range(8-1, 8+2)) + list(range(25-1, 25+2)) + list(range(33-2, 34)): mktiles.add((x, 1)) mktiles.add((x, 32)) for x in list(range(0, 2)) + list(range(8-1, 8+2)) + list(range(25-1, 25+2)) + list(range(34-2, 34)): mktiles.add((x, 2)) mktiles.add((x, 31)) for x in [0, 33]: mktiles.add((x, 15)) mktiles.add((x, 16)) mktiles.add((x, 17)) mktiles.add((x, 18)) for x in [16, 17]: mktiles.add((x, 16)) mktiles.add((x, 17)) else: ic.setup_empty_1k() for x in range(1, 13): mktiles.add((x, 0)) mktiles.add((x, 17)) for x in list(range(0, 6)) + list(range(8, 14)): mktiles.add((x, 1)) mktiles.add((x, 16)) for x in list(range(0, 5)) + list(range(9, 14)): mktiles.add((x, 2)) mktiles.add((x, 15)) for y in range(7, 11): mktiles.add((0, y)) mktiles.add((13, y)) for x in range(6, 8): for y in range(8, 10): mktiles.add((x, y)) expand_count=[0] def print_expand_div(title): print('[+] Show %s') def print_expand_all(): print('[+] Expand All' % (expand_count[0], expand_count[0])) expand_count[0] += 1 def print_index(): print("Project IceStorm – %s Overview" % chipname) print("

Project IceStorm – %s Overview

" % chipname) print("""Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. This is work in progress.""") print("""

This documentation is auto-generated by icebox_html.py from IceBox.
A machine-readable form of the database can be downloaded here.

""" % chipdbfile) print("""

The iCE40 FPGA fabric is organized into tiles. The configuration bits themself have the same meaning in all tiles of the same type. But the way the tiles are connected to each other depends on the types of neighbouring cells. Furthermore, some wire names are different for e.g. an IO tile on the left border and an IO tile on the top border.

""") print("""

Click on a highlighted tile below to view the bitstream details for the tile. The highlighted tiles cover all combinations of neighbouring cells that can be found in iCE40 FPGAs.

""") print('

') for y in range(ic.max_y, -1, -1): print("") for x in range(ic.max_x + 1): if mode8k: fontsize="8px" print('') elif (x, y) in mktiles: if ic.tile_type(x, y) == "IO": color = "#aee" if ic.tile_type(x, y) == "LOGIC": color = "#eae" if ic.tile_type(x, y) == "RAMB": color = "#eea" if ic.tile_type(x, y) == "RAMT": color = "#eea" print('bgcolor="%s">%s
(%d %d)' % (color, fontsize, x, y, ic.tile_type(x, y), x, y)) else: if ic.tile_type(x, y) == "IO": color = "#8aa" if ic.tile_type(x, y) == "LOGIC": color = "#a8a" if ic.tile_type(x, y) == "RAMB": color = "#aa8" if ic.tile_type(x, y) == "RAMT": color = "#aa8" print('bgcolor="%s">%s
(%d %d)' % (color, fontsize, ic.tile_type(x, y), x, y)) print("") print("
 

") def print_tile(tx, ty): tile = ic.tile(tx, ty) tile_type = ic.tile_type(tx, ty) print("Project IceStorm – %s %s Tile (%d %d)" % (chipname, tile_type, tx, ty)) print("

Project IceStorm – %s %s Tile (%d %d)

" % (chipname, tile_type, tx, ty)) print("""Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. This is work in progress.""") print("""

This page describes the %s Tile (%d %d), what nets and configuration bits it has and how it is connected to its neighbourhood.

""" % (tile_type, tx, ty)) visible_tiles = set() print('

') for y in range(ty+2, ty-3, -1): print("") for x in range(tx-2, tx+3): print('') else: if (x, y) in mktiles: if ic.tile_type(x, y) == "IO": color = "#aee" if ic.tile_type(x, y) == "LOGIC": color = "#eae" if ic.tile_type(x, y) == "RAMB": color = "#eea" if ic.tile_type(x, y) == "RAMT": color = "#eea" print('bgcolor="%s">%s Tile
(%d %d)' % (color, x, y, ic.tile_type(x, y), x, y)) else: if ic.tile_type(x, y) == "IO": color = "#8aa" if ic.tile_type(x, y) == "LOGIC": color = "#a8a" if ic.tile_type(x, y) == "RAMB": color = "#aa8" if ic.tile_type(x, y) == "RAMT": color = "#aa8" print('bgcolor="%s">%s Tile
(%d %d)' % (color, ic.tile_type(x, y), x, y)) visible_tiles.add((x, y)) print("") print("
 

") # print_expand_all() print("

Configuration Bitmap

") print("

A %s Tile has %d config bits in %d groups of %d bits each:
" % (tile_type, len(tile)*len(tile[0]), len(tile), len(tile[0]))) print(("%s

" % (", ".join(['%sB%d[%d:0]' % (" " if i < 10 else "", i, len(tile[i])-1) for i in range(len(tile))]))).replace(" B8", "
 B8")) bitmap_cells = list() for line_nr in range(len(tile)): line = list() bitmap_cells.append(line) for bit_nr in range(len(tile[line_nr])): line.append({"bgcolor": "#aaa", "label": "?"}) for entry in ic.tile_db(tx, ty): if not ic.tile_has_entry(tx, ty, entry): continue for bit in [bit.replace("!", "") for bit in entry[0]]: match = re.match(r"B(\d+)\[(\d+)\]$", bit) idx1 = int(match.group(1)) idx2 = int(match.group(2)) if entry[1] == "routing": bitmap_cells[idx1][idx2]["bgcolor"] = "#faa" bitmap_cells[idx1][idx2]["label"] = "R" bitmap_cells[idx1][idx2]["is_routing"] = True elif entry[1] == "buffer": bitmap_cells[idx1][idx2]["bgcolor"] = "#afa" bitmap_cells[idx1][idx2]["label"] = "B" bitmap_cells[idx1][idx2]["is_routing"] = True else: bitmap_cells[idx1][idx2]["bgcolor"] = "#aaf" if entry[1] == "ColBufCtrl": bitmap_cells[idx1][idx2]["label"] = "O" elif entry[1].startswith("LC_"): bitmap_cells[idx1][idx2]["label"] = "L" elif entry[1].startswith("NegClk"): bitmap_cells[idx1][idx2]["label"] = "N" elif entry[1].startswith("CarryInSet"): bitmap_cells[idx1][idx2]["label"] = "C" elif entry[1].startswith("IOB_"): bitmap_cells[idx1][idx2]["label"] = "I" elif entry[1].startswith("IoCtrl"): bitmap_cells[idx1][idx2]["label"] = "T" elif entry[1] == "Icegate": bitmap_cells[idx1][idx2]["label"] = "G" elif entry[1].startswith("Cascade"): bitmap_cells[idx1][idx2]["label"] = "A" elif entry[1].startswith("RamConfig"): bitmap_cells[idx1][idx2]["label"] = "M" elif entry[1].startswith("RamCascade"): bitmap_cells[idx1][idx2]["label"] = "M" elif entry[1].startswith("PLL"): bitmap_cells[idx1][idx2]["label"] = "P" else: assert False bitmap_cells[idx1][idx2]["label"] = '%s' % (idx1, idx2, bitmap_cells[idx1][idx2]["label"]) print('') print("") for cell_nr in range(len(line)): print('' % cell_nr) print("") for line_nr, line in enumerate(bitmap_cells): print("") print('' % line_nr) for cell in line: print('' % (cell["bgcolor"], cell["label"])) print('' % line_nr) print("") print("") for cell_nr in range(len(line)): print('' % cell_nr) print("") print("
%d
B%d%sB%d
%d
") print("

Nets and Connectivity

") print("""

This section lists all nets in the tile and how this nets are connected with nets from cells in its neighbourhood.

""") grouped_segs = ic.group_segments(set([(tx, ty)])) groups_indexed = dict() this_tile_nets = dict() for segs in sorted(grouped_segs): this_segs = list() neighbour_segs = dict() for s in segs: if s[0] == tx and s[1] == ty: this_segs.append(s[2]) match = re.match(r"(.*?_)(\d+)(.*)", s[2]) if match: this_tile_nets.setdefault(match.group(1) + "*" + match.group(3), set()).add(int(match.group(2))) else: this_tile_nets.setdefault(s[2], set()).add(-1) if (s[0], s[1]) in visible_tiles: neighbour_segs.setdefault((s[0], s[1]), list()).append(s[2]) if this_segs: this_name = ", ".join(sorted(this_segs)) assert this_name not in groups_indexed groups_indexed[this_name] = neighbour_segs print("

List of nets in %s Tile (%d %d)

" % (tile_type, tx, ty)) def net2cat(netname): cat = (99, "Unsorted") if netname.startswith("glb_netwk_"): cat = (10, "Global Networks") if netname.startswith("glb2local_"): cat = (10, "Global Networks") if netname.startswith("fabout"): cat = (10, "Global Networks") if netname.startswith("local_"): cat = (20, "Local Tracks") if netname.startswith("carry_in"): cat = (25, "Logic Block") if netname.startswith("io_"): cat = (25, "IO Block") if netname.startswith("ram"): cat = (25, "RAM Block") if netname.startswith("lutff_"): cat = (25, "Logic Block") if netname.startswith("lutff_0"): cat = (30, "Logic Unit 0") if netname.startswith("lutff_1"): cat = (30, "Logic Unit 1") if netname.startswith("lutff_2"): cat = (30, "Logic Unit 2") if netname.startswith("lutff_3"): cat = (30, "Logic Unit 3") if netname.startswith("lutff_4"): cat = (30, "Logic Unit 4") if netname.startswith("lutff_5"): cat = (30, "Logic Unit 5") if netname.startswith("lutff_6"): cat = (30, "Logic Unit 6") if netname.startswith("lutff_7"): cat = (30, "Logic Unit 7") if netname.startswith("neigh_op_"): cat = (40, "Neighbourhood") if netname.startswith("logic_op_"): cat = (40, "Neighbourhood") if netname.startswith("sp4_v_"): cat = (50, "Span-4 Vertical") if netname.startswith("span4_vert_"): cat = (50, "Span-4 Vertical") if netname.startswith("sp4_r_v_"): cat = (55, "Span-4 Right Vertical") if netname.startswith("sp4_h_"): cat = (60, "Span-4 Horizontal") if netname.startswith("span4_horz_"): cat = (60, "Span-4 Horizontal") if netname.startswith("sp12_v_"): cat = (70, "Span-12 Vertical") if netname.startswith("span12_vert_"): cat = (70, "Span-12 Vertical") if netname.startswith("sp12_h_"): cat = (80, "Span-12 Horizontal") if netname.startswith("span12_horz_"): cat = (80, "Span-12 Horizontal") return cat nets_in_cats = dict() for this_name in sorted(this_tile_nets): nets_in_cats.setdefault(net2cat(this_name), list()).append(this_name) for cat in sorted(nets_in_cats): print('

%s

' % cat[1]) print('

    ') for this_name in sorted(nets_in_cats[cat]): indices = [i for i in this_tile_nets[this_name] if i >= 0] if -1 in this_tile_nets[this_name]: print("
  • %s
    • " % this_name) if len(indices) == 1: print("
  • %s
    • " % this_name.replace("*", "%d" % indices[0])) elif len(indices) > 0: print("
  • %s
    • " % this_name.replace("*", "{" + ",".join(["%d" % i for i in sorted(indices)]) + "}")) print("

") print("

Nets and their permanent connections to nets in neighbour tiles

") # print_expand_div("connection details") all_cats = set() for this_name in sorted(groups_indexed): all_cats.add(net2cat(this_name)) for cat in sorted(all_cats): print('

%s

' % cat[1]) print('

    ') for this_name in sorted(groups_indexed): if net2cat(this_name) == cat: neighbour_segs = groups_indexed[this_name] print("
  • %s" % this_name) if neighbour_segs: print("
      ") for nidx in sorted(neighbour_segs): if nidx == (tx, ty): print("
    • (%d %d) %s
      • " % (nidx[0], nidx[1], ", ".join(sorted(neighbour_segs[nidx])))) else: print("
    • (%d %d) %s
      • " % (nidx[0], nidx[1], ", ".join(sorted(neighbour_segs[nidx])))) print("
    ") print("
    • ") print("

") # print_expand_end() print("

Routing Configuration

") print("""

This section lists the routing configuration bits in the tile. The entries titled "routing" configure transfer gates, the entries titled "buffer" configure tri-state drivers.

""") grpgrp = dict() config_groups = dict() other_config_groups = dict() for entry in ic.tile_db(tx, ty): if not ic.tile_has_entry(tx, ty, entry): continue if entry[1] in ("routing", "buffer"): cfggrp = entry[1] + " " + entry[3] + "," + ",".join(sorted([bit.replace("!", "") for bit in entry[0]])) config_groups.setdefault(cfggrp, list()).append(entry) grpgrp.setdefault(net2cat(entry[3]), set()).add(cfggrp) else: grp = other_config_groups.setdefault(" ".join(entry[1:]), set()) for bit in entry[0]: grp.add(bit) for cat in sorted(grpgrp): print('

%s

' % cat[1]) bits_in_cat = set() for cfggrp in sorted(grpgrp[cat]): grp = config_groups[cfggrp] for bit in cfggrp.split(",")[1:]: match = re.match(r"B(\d+)\[(\d+)\]", bit) bits_in_cat.add((int(match.group(1)), int(match.group(2)))) print('') print("") for cell_nr in range(len(bitmap_cells[0])): print('' % cell_nr) print("") for line_nr, line in enumerate(bitmap_cells): print("") print('' % line_nr) for cell_nr, cell in enumerate(line): color = cell["bgcolor"] if (line_nr, cell_nr) not in bits_in_cat: color="#aaa" print('' % (color, cell["label"])) print('' % line_nr) print("") print("") for cell_nr in range(len(line)): print('' % cell_nr) print("") print("
%d
B%d%sB%d
%d
") # print_expand_div("details") src_nets = set() dst_nets = set() links = dict() for cfggrp in sorted(grpgrp[cat]): grp = config_groups[cfggrp] for entry in grp: src_nets.add(entry[2]) dst_nets.add(entry[3]) if entry[1] == "buffer": assert (entry[2], entry[3]) not in links links[(entry[2], entry[3])] = 'B' else: assert (entry[2], entry[3]) not in links links[(entry[2], entry[3])] = 'R' print('
Connectivity Matrix
') print('') dst_net_prefix = "" dst_net_list = sorted(dst_nets, key=icebox.key_netname) if len(dst_net_list) > 1: while len(set([n[0] for n in dst_net_list])) == 1: dst_net_prefix += dst_net_list[0][0] for i in range(len(dst_net_list)): dst_net_list[i] = dst_net_list[i][1:] while dst_net_prefix != "" and dst_net_prefix[-1] != "_": for i in range(len(dst_net_list)): dst_net_list[i] = dst_net_prefix[-1] + dst_net_list[i] dst_net_prefix = dst_net_prefix[0:-1] print('' % (len(dst_net_list), dst_net_prefix)) print('') for dn in dst_net_list: print('' % dn) print("") for sn in sorted(src_nets, key=icebox.key_netname): print("") print('' % sn) for dn in sorted(dst_nets, key=icebox.key_netname): if (sn, dn) in links: print(links[(sn, dn)]) else: print('') print("") print("
%s
%s
%s 
") print('
Configuration Stamps
') for cfggrp in sorted(grpgrp[cat]): grp = config_groups[cfggrp] bits = cfggrp.split(",")[1:] print('

') for bit in bits: print('' % (re.sub(r"B(\d+)\[(\d+)\]", r"B.\1.\2", bit), bit)) group_lines = list() is_buffer = True for entry in grp: line = '' for bit in bits: if bit in entry[0]: line += '' else: line += '' is_buffer = entry[1] == "buffer" line += '' % (entry[1], entry[2], entry[3]) group_lines.append(line) if is_buffer: print('') else: print('') for line in sorted(group_lines): print(line) print('
%s
10%s%s%s
FunctionSource-NetDestination-Net
FunctionNetNet

') # print_expand_end() print("

Non-routing Configuration

") print("

This section lists the non-routing configuration bits in the tile.

") print('') print("") for cell_nr in range(len(bitmap_cells[0])): print('' % cell_nr) print("") for line_nr, line in enumerate(bitmap_cells): print("") print('' % line_nr) for cell_nr, cell in enumerate(line): color = cell["bgcolor"] if "is_routing" in cell: color="#aaa" print('' % (color, cell["label"])) print('' % line_nr) print("") print("") for cell_nr in range(len(line)): print('' % cell_nr) print("") print("
%d
B%d%sB%d
%d
") print('

') for cfggrp in sorted(other_config_groups): bits = " ".join(['%s' % (re.sub(r"B(\d+)\[(\d+)\]", r"B.\1.\2", bit), bit) for bit in sorted(other_config_groups[cfggrp])]) cfggrp = cfggrp.replace(" " + list(other_config_groups[cfggrp])[0], "") print('' % (cfggrp, bits)) print('
FunctionBits
%s%s

') if outdir is not None: stdout = sys.stdout if not os.path.exists(outdir): print("Creating %s/" % outdir, file=stdout) os.makedirs(outdir) print("Writing %s/index.html.." % outdir, file=stdout) sys.stdout = open("%s/index.html" % outdir, "w") print_index() for x in range(ic.max_x+1): for y in range(ic.max_y+1): if (x, y) in mktiles: print("Writing %s/tile_%d_%d.html.." % (outdir, x, y), file=stdout) sys.stdout = open("%s/tile_%d_%d.html" % (outdir, x, y), "w") print_tile(x, y) print("Writing %s/%s..." % (outdir, chipdbfile), file=stdout) if os.access("icebox_chipdb.py", os.R_OK): os.system("python3 icebox_chipdb.py %s > %s/%s" % ("-8" if mode8k else "", outdir, chipdbfile)) else: os.system("icebox_chipdb %s > %s/%s" % ("-8" if mode8k else "", outdir, chipdbfile)) sys.stdout = stdout elif (tx, ty) == (0, 0): print_index() else: print_tile(tx, ty) fpga-icestorm-0~20160913git266e758/icebox/icebox_maps.py000077500000000000000000000114511276746530600225130ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import icebox import getopt, sys, re mode = None def usage(): print("Usage:") print(" icebox_maps -m bitmaps") print(" icebox_maps -m io_tile_nets_l") print(" icebox_maps -m io_tile_nets_r") print(" icebox_maps -m io_tile_nets_t") print(" icebox_maps -m io_tile_nets_b") print(" icebox_maps -m logic_tile_nets") print(" icebox_maps -m ramb_tile_nets") print(" icebox_maps -m ramt_tile_nets") sys.exit(0) try: opts, args = getopt.getopt(sys.argv[1:], "m:") except: usage() for o, a in opts: if o == "-m": mode = a.strip() else: usage() if len(args) != 0: usage() def get_bit_group(x, y, db): bit = "B%d[%d]" % (y, x) nbit = "!B%d[%d]" % (y, x) funcs = set() for entry in db: if bit in entry[0] or nbit in entry[0]: if entry[1] in ("IOB_0", "IOB_1", "IoCtrl"): funcs.add("i") elif entry[1] == "routing": funcs.add("r") elif entry[1] == "buffer": funcs.add("b") elif re.match("LC_", entry[1]): funcs.add("l") elif entry[1] == "NegClk": funcs.add("N") elif entry[1] == "ColBufCtrl": funcs.add("o") elif entry[1] == "CarryInSet": funcs.add("C") elif entry[1] == "Cascade": funcs.add("a") else: funcs.add("?") if len(funcs) == 1: return funcs.pop() if len(funcs) > 1: return "X" return "-" def print_tilemap(stmt, db, n): print() print(stmt) for y in range(16): for x in range(n): print(get_bit_group(x, y, db), end="") print() def print_db_nets(stmt, db, pos): print() print(stmt, end="") netnames = set() for entry in db: if entry[1] in ("routing", "buffer"): if icebox.pos_has_net(pos[0], entry[2]): netnames.add(entry[2]) if icebox.pos_has_net(pos[0], entry[3]): netnames.add(entry[3]) last_prefix = "" for net in sorted(netnames, key=icebox.key_netname): match = re.match(r"(.*?)(\d+)$", net) if match: if last_prefix == match.group(1): print(",%s" % match.group(2), end="") else: print() print(net, end="") last_prefix = match.group(1) else: print() print(net, end="") last_prefix = "*" print() if mode == "bitmaps": print_tilemap(".io_tile_bitmap_l", icebox.iotile_l_db, 18) print_tilemap(".io_tile_bitmap_r", icebox.iotile_r_db, 18) print_tilemap(".io_tile_bitmap_t", icebox.iotile_t_db, 18) print_tilemap(".io_tile_bitmap_b", icebox.iotile_b_db, 18) print_tilemap(".logic_tile_bitmap", icebox.logictile_db, 54) print_tilemap(".ramb_tile_bitmap", icebox.rambtile_db, 42) print_tilemap(".ramt_tile_bitmap", icebox.ramttile_db, 42) print() print(".bitmap_legend") print("- ... unknown bit") print("? ... unknown bit type") print("X ... database conflict") print("i ... IOB_0 IOB_1 IoCtrl") print("a ... Carry_In_Mux Cascade") print("r ... routing") print("b ... buffer") print("l ... logic bits") print("o ... ColBufCtrl") print("C ... CarryInSet") print("N ... NegClk") print() elif mode == "io_tile_nets_l": print_db_nets(".io_tile_nets_l", icebox.iotile_l_db, "l") elif mode == "io_tile_nets_r": print_db_nets(".io_tile_nets_r", icebox.iotile_r_db, "r") elif mode == "io_tile_nets_t": print_db_nets(".io_tile_nets_t", icebox.iotile_t_db, "t") elif mode == "io_tile_nets_b": print_db_nets(".io_tile_nets_b", icebox.iotile_b_db, "b") elif mode == "logic_tile_nets": print_db_nets(".logic_tile_nets", icebox.logictile_db, "c") elif mode == "ramb_tile_nets": print_db_nets(".ramb_tile_nets", icebox.ramtile_db, "c") elif mode == "ramt_tile_nets": print_db_nets(".ramt_tile_nets", icebox.ramtile_db, "c") else: usage() fpga-icestorm-0~20160913git266e758/icebox/icebox_vlog.py000077500000000000000000001172001276746530600225210ustar00rootroot00000000000000#!/usr/bin/env python3 # # Copyright (C) 2015 Clifford Wolf # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. # # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # import icebox import getopt, sys, re strip_comments = False strip_interconn = False lookup_pins = False check_ieren = False check_driver = False lookup_symbols = False do_collect = False pcf_data = dict() portnames = set() unmatched_ports = set() modname = "chip" def usage(): print(""" Usage: icebox_vlog [options] [bitmap.asc] -s strip comments from output -S strip comments about interconn wires from output -l convert io tile port names to chip pin numbers -L lookup symbol names (using .sym statements in input) -n name for the exported module (default: "chip") -p use the set_io commands from the specified pcf file -P like -p, enable some hacks for pcf files created by the iCEcube2 placer. -c collect multi-bit ports -R enable IeRen database checks -D enable exactly-one-driver checks """) sys.exit(0) try: opts, args = getopt.getopt(sys.argv[1:], "sSlLap:P:n:cRD") except: usage() for o, a in opts: if o == "-s": strip_comments = True elif o == "-S": strip_interconn = True elif o == "-l": lookup_pins = True elif o == "-L": lookup_symbols = True elif o == "-n": modname = a elif o == "-a": pass # ignored for backward compatibility elif o in ("-p", "-P"): with open(a, "r") as f: for line in f: if o == "-P" and not re.search(" # ICE_(GB_)?IO", line): continue line = re.sub(r"#.*", "", line.strip()).split() if len(line) and line[0] == "set_io": p = line[1] if o == "-P": p = p.lower() p = re.sub(r"_ibuf$", "", p) p = re.sub(r"_obuft$", "", p) p = re.sub(r"_obuf$", "", p) p = re.sub(r"_gb_io$", "", p) p = re.sub(r"_pad(_[0-9]+|)$", r"\1", p) portnames.add(p) if not re.match(r"[a-zA-Z_][a-zA-Z0-9_]*$", p): p = "\\%s " % p unmatched_ports.add(p) if len(line) > 3: pinloc = tuple([int(s) for s in line[2:]]) else: pinloc = (line[2],) pcf_data[pinloc] = p elif o == "-c": do_collect = True elif o == "-R": check_ieren = True elif o == "-D": check_driver = True else: usage() if len(args) == 0: args.append("/dev/stdin") if len(args) != 1: usage() if not strip_comments: print("// Reading file '%s'.." % args[0]) ic = icebox.iceconfig() ic.read_file(args[0]) print() text_wires = list() text_ports = list() luts_queue = set() text_func = list() failed_drivers_check = list() netidx = [0, 0] nets = dict() seg2net = dict() iocells = set() iocells_in = set() iocells_out = set() iocells_special = set() iocells_type = dict() iocells_negclk = set() iocells_inbufs = set() iocells_skip = set() iocells_pll = set() def is_interconn(netname): if netname.startswith("sp4_"): return True if netname.startswith("sp12_"): return True if netname.startswith("span4_"): return True if netname.startswith("span12_"): return True if netname.startswith("logic_op_"): return True if netname.startswith("neigh_op_"): return True if netname.startswith("local_"): return True return False pll_config_bitidx = dict() pll_gbuf = dict() for entry in icebox.iotile_l_db: if entry[1] == "PLL": match = re.match(r"B(\d+)\[(\d+)\]", entry[0][0]); assert match pll_config_bitidx[entry[2]] = (int(match.group(1)), int(match.group(2))) def get_pll_bit(pllinfo, name): bit = pllinfo[name] assert bit[2] in pll_config_bitidx return ic.tile(bit[0], bit[1])[pll_config_bitidx[bit[2]][0]][pll_config_bitidx[bit[2]][1]] def get_pll_bits(pllinfo, name, n): return "".join([get_pll_bit(pllinfo, "%s_%d" % (name, i)) for i in range(n-1, -1, -1)]) for pllid in ic.pll_list(): pllinfo = icebox.pllinfo_db[pllid] plltype = get_pll_bits(pllinfo, "PLLTYPE", 3) if plltype != "000": if plltype in ["010", "100", "110"]: iocells_special.add(pllinfo["PLLOUT_A"]) else: iocells_skip.add(pllinfo["PLLOUT_A"]) iocells_pll.add(pllinfo["PLLOUT_A"]) if plltype not in ["010", "011"]: iocells_skip.add(pllinfo["PLLOUT_B"]) iocells_pll.add(pllinfo["PLLOUT_B"]) extra_connections = list() extra_segments = list() for bit in ic.extra_bits: entry = ic.lookup_extra_bit(bit) if entry[0] == "padin_glb_netwk": glb = int(entry[1]) pin_entry = ic.padin_pio_db()[glb] if pin_entry in iocells_pll: pll_gbuf[pin_entry] = (pin_entry[0], pin_entry[1], "padin_%d" % pin_entry[2]) extra_segments.append(pll_gbuf[pin_entry]) else: iocells.add((pin_entry[0], pin_entry[1], pin_entry[2])) iocells_in.add((pin_entry[0], pin_entry[1], pin_entry[2])) s1 = (pin_entry[0], pin_entry[1], "io_%d/PAD" % pin_entry[2]) s2 = (pin_entry[0], pin_entry[1], "padin_%d" % pin_entry[2]) extra_connections.append((s1, s2)) for idx, tile in list(ic.io_tiles.items()): tc = icebox.tileconfig(tile) iocells_type[(idx[0], idx[1], 0)] = ["0" for i in range(6)] iocells_type[(idx[0], idx[1], 1)] = ["0" for i in range(6)] for entry in ic.tile_db(idx[0], idx[1]): if check_ieren and entry[1] == "IoCtrl" and entry[2].startswith("IE_") and not tc.match(entry[0]): iren_idx = (idx[0], idx[1], 0 if entry[2] == "IE_0" else 1) for iren_entry in ic.ieren_db(): if iren_idx[0] == iren_entry[3] and iren_idx[1] == iren_entry[4] and iren_idx[2] == iren_entry[5]: iocells_inbufs.add((iren_entry[0], iren_entry[1], iren_entry[2])) if entry[1] == "NegClk" and tc.match(entry[0]): iocells_negclk.add((idx[0], idx[1], 0)) iocells_negclk.add((idx[0], idx[1], 1)) if entry[1].startswith("IOB_") and entry[2].startswith("PINTYPE_") and tc.match(entry[0]): match1 = re.match("IOB_(\d+)", entry[1]) match2 = re.match("PINTYPE_(\d+)", entry[2]) assert match1 and match2 iocells_type[(idx[0], idx[1], int(match1.group(1)))][int(match2.group(1))] = "1" iocells_type[(idx[0], idx[1], 0)] = "".join(iocells_type[(idx[0], idx[1], 0)]) iocells_type[(idx[0], idx[1], 1)] = "".join(iocells_type[(idx[0], idx[1], 1)]) for segs in sorted(ic.group_segments()): for seg in segs: if ic.tile_type(seg[0], seg[1]) == "IO": match = re.match("io_(\d+)/D_(IN|OUT)_(\d+)", seg[2]) if match: cell = (seg[0], seg[1], int(match.group(1))) if cell in iocells_skip: continue iocells.add(cell) if match.group(2) == "IN": if check_ieren: assert cell in iocells_inbufs if iocells_type[cell] != "100000" or match.group(3) != "0": iocells_special.add(cell) iocells_in.add(cell) if match.group(2) == "OUT" and iocells_type[cell][2:6] != "0000": if iocells_type[cell] != "100110" or match.group(3) != "0": iocells_special.add(cell) iocells_out.add(cell) extra_segments.append((seg[0], seg[1], "io_%d/PAD" % int(match.group(1)))) for cell in iocells: if iocells_type[cell] == "100110" and not cell in iocells_special: s1 = (cell[0], cell[1], "io_%d/PAD" % cell[2]) s2 = (cell[0], cell[1], "io_%d/D_OUT_0" % cell[2]) extra_connections.append((s1, s2)) del iocells_type[cell] elif iocells_type[cell] == "100000" and not cell in iocells_special: s1 = (cell[0], cell[1], "io_%d/PAD" % cell[2]) s2 = (cell[0], cell[1], "io_%d/D_IN_0" % cell[2]) extra_connections.append((s1, s2)) del iocells_type[cell] def next_netname(): while True: netidx[0] += 1 n = "n%d" % netidx[0] if n not in portnames: return n for segs in sorted(ic.group_segments(extra_connections=extra_connections, extra_segments=extra_segments)): n = next_netname() net_segs = set() renamed_net_to_port = False for s in segs: match = re.match("io_(\d+)/PAD", s[2]) if match: idx = (s[0], s[1], int(match.group(1))) p = "io_%d_%d_%d" % idx if lookup_pins or pcf_data: for entry in ic.pinloc_db(): if idx[0] == entry[1] and idx[1] == entry[2] and idx[2] == entry[3]: if (entry[0],) in pcf_data: p = pcf_data[(entry[0],)] unmatched_ports.discard(p) elif (entry[1], entry[2], entry[3]) in pcf_data: p = pcf_data[(entry[1], entry[2], entry[3])] unmatched_ports.discard(p) elif lookup_pins: p = "pin_%s" % entry[0] if not renamed_net_to_port: n = p if idx in iocells_in and idx not in iocells_out: text_ports.append("input %s" % p) elif idx not in iocells_in and idx in iocells_out: text_ports.append("output %s" % p) else: text_ports.append("inout %s" % p) text_wires.append("wire %s;" % n) renamed_net_to_port = True elif idx in iocells_in and idx not in iocells_out: text_ports.append("input %s" % p) text_wires.append("assign %s = %s;" % (n, p)) elif idx not in iocells_in and idx in iocells_out: text_ports.append("output %s" % p) text_wires.append("assign %s = %s;" % (p, n)) else: text_ports.append("inout %s" % p) text_wires.append("assign %s = %s;" % (p, n)) match = re.match("lutff_(\d+)/", s[2]) if match: luts_queue.add((s[0], s[1], int(match.group(1)))) nets[n] = segs for s in segs: seg2net[s] = n if not renamed_net_to_port: text_wires.append("wire %s;" % n) for s in segs: if not strip_interconn or not is_interconn(s[2]): if s[2].startswith("glb_netwk_"): net_segs.add((0, 0, s[2])) else: net_segs.add(s) count_drivers = 0 for s in segs: if re.match(r"ram/RDATA_", s[2]): count_drivers += 1 if re.match(r"io_./D_IN_", s[2]): count_drivers += 1 if re.match(r"lutff_./out", s[2]): count_drivers += 1 if count_drivers != 1 and check_driver: failed_drivers_check.append(n) if not strip_comments: for s in sorted(net_segs): text_wires.append("// %s" % (s,)) if count_drivers != 1 and check_driver: text_wires.append("// Number of drivers: %d" % count_drivers) text_wires.append("") def seg_to_net(seg, default=None): if seg not in seg2net: if default is not None: if default == "-": n = "open_%d" % netidx[1] netidx[1] += 1 text_wires.append("wire %s;" % n) return n return default n = next_netname() nets[n] = set([seg]) seg2net[seg] = n text_wires.append("wire %s;" % n) if not strip_comments: if not strip_interconn or not is_interconn(seg[2]): text_wires.append("// %s" % (seg,)) text_wires.append("") return seg2net[seg] if lookup_symbols: text_func.append("// Debug Symbols") with open("/usr/local/share/icebox/chipdb-%s.txt" % ic.device, "r") as f: current_net = -1 exported_names = dict() for line in f: line = line.split() if len(line) == 0: pass elif line[0] == ".net": current_net = int(line[1]) if current_net not in ic.symbols: current_net = -1 elif line[0].startswith("."): current_net = -1 elif current_net >= 0: seg = (int(line[0]), int(line[1]), line[2]) if seg in seg2net: for name in ic.symbols[current_net]: while name in exported_names: if exported_names[name] == seg2net[seg]: break name += "_" if name not in exported_names: text_func.append("wire \\_%s = %s;" % (name, seg2net[seg])) exported_names[name] = seg2net[seg] current_net = -1 text_func.append("") wb_boot = seg_to_net(icebox.warmbootinfo_db[ic.device]["BOOT"], "") wb_s0 = seg_to_net(icebox.warmbootinfo_db[ic.device]["S0"], "") wb_s1 = seg_to_net(icebox.warmbootinfo_db[ic.device]["S1"], "") if wb_boot != "" or wb_s0 != "" or wb_s1 != "": text_func.append("SB_WARMBOOT (") text_func.append(" .BOOT(%s)," % wb_boot) text_func.append(" .S0(%s)," % wb_s0) text_func.append(" .S1(%s)," % wb_s1) text_func.append(");") text_func.append("") def get_pll_feedback_path(pllinfo): v = get_pll_bits(pllinfo, "FEEDBACK_PATH", 3) if v == "000": return "DELAY" if v == "001": return "SIMPLE" if v == "010": return "PHASE_AND_DELAY" if v == "110": return "EXTERNAL" assert False def get_pll_adjmode(pllinfo, name): v = get_pll_bit(pllinfo, name) if v == "0": return "FIXED" if v == "1": return "DYNAMIC" assert False def get_pll_outsel(pllinfo, name): v = get_pll_bits(pllinfo, name, 2) if v == "00": return "GENCLK" if v == "01": return "GENCLK_HALF" if v == "10": return "SHIFTREG_90deg" if v == "11": return "SHIFTREG_0deg" assert False for pllid in ic.pll_list(): pllinfo = icebox.pllinfo_db[pllid] plltype = get_pll_bits(pllinfo, "PLLTYPE", 3) if plltype == "000": continue if not strip_comments: text_func.append("// plltype = %s" % plltype) for ti in sorted(ic.io_tiles): for bit in sorted(pll_config_bitidx): if ic.io_tiles[ti][pll_config_bitidx[bit][0]][pll_config_bitidx[bit][1]] == "1": resolved_bitname = "" for bitname in pllinfo: if pllinfo[bitname] == (ti[0], ti[1], bit): resolved_bitname = " " + bitname text_func.append("// (%2d, %2d, \"%s\")%s" % (ti[0], ti[1], bit, resolved_bitname)) if plltype in ["010", "100", "110"]: if plltype == "010": text_func.append("SB_PLL40_PAD #(") if plltype == "100": text_func.append("SB_PLL40_2_PAD #(") if plltype == "110": text_func.append("SB_PLL40_2F_PAD #(") text_func.append(" .FEEDBACK_PATH(\"%s\")," % get_pll_feedback_path(pllinfo)) text_func.append(" .DELAY_ADJUSTMENT_MODE_FEEDBACK(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_FB")) text_func.append(" .DELAY_ADJUSTMENT_MODE_RELATIVE(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_REL")) if plltype == "010": text_func.append(" .PLLOUT_SELECT(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A")) else: if plltype != "100": text_func.append(" .PLLOUT_SELECT_PORTA(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A")) text_func.append(" .PLLOUT_SELECT_PORTB(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_B")) text_func.append(" .SHIFTREG_DIV_MODE(1'b%s)," % get_pll_bit(pllinfo, "SHIFTREG_DIV_MODE")) text_func.append(" .FDA_FEEDBACK(4'b%s)," % get_pll_bits(pllinfo, "FDA_FEEDBACK", 4)) text_func.append(" .FDA_RELATIVE(4'b%s)," % get_pll_bits(pllinfo, "FDA_RELATIVE", 4)) text_func.append(" .DIVR(4'b%s)," % get_pll_bits(pllinfo, "DIVR", 4)) text_func.append(" .DIVF(7'b%s)," % get_pll_bits(pllinfo, "DIVF", 7)) text_func.append(" .DIVQ(3'b%s)," % get_pll_bits(pllinfo, "DIVQ", 3)) text_func.append(" .FILTER_RANGE(3'b%s)," % get_pll_bits(pllinfo, "FILTER_RANGE", 3)) if plltype == "010": text_func.append(" .ENABLE_ICEGATE(1'b0),") else: text_func.append(" .ENABLE_ICEGATE_PORTA(1'b0),") text_func.append(" .ENABLE_ICEGATE_PORTB(1'b0),") text_func.append(" .TEST_MODE(1'b%s)" % get_pll_bit(pllinfo, "TEST_MODE")) text_func.append(") PLL_%d_%d (" % pllinfo["LOC"]) if plltype == "010": pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/PAD" % pllinfo["PLLOUT_A"][2]) text_func.append(" .PACKAGEPIN(%s)," % seg_to_net(pad_segment)) del seg2net[pad_segment] text_func.append(" .PLLOUTCORE(%s)," % seg_to_net(pad_segment)) if pllinfo["PLLOUT_A"] in pll_gbuf: text_func.append(" .PLLOUTGLOBAL(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]])) else: pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/PAD" % pllinfo["PLLOUT_A"][2]) text_func.append(" .PACKAGEPIN(%s)," % seg_to_net(pad_segment)) del seg2net[pad_segment] text_func.append(" .PLLOUTCOREA(%s)," % seg_to_net(pad_segment)) if pllinfo["PLLOUT_A"] in pll_gbuf: text_func.append(" .PLLOUTGLOBALA(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]])) pad_segment = (pllinfo["PLLOUT_B"][0], pllinfo["PLLOUT_B"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_B"][2]) text_func.append(" .PLLOUTCOREB(%s)," % seg_to_net(pad_segment)) if pllinfo["PLLOUT_B"] in pll_gbuf: text_func.append(" .PLLOUTGLOBALB(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_B"]])) text_func.append(" .EXTFEEDBACK(%s)," % seg_to_net(pllinfo["EXTFEEDBACK"], "1'b0")) text_func.append(" .DYNAMICDELAY({%s})," % ", ".join([seg_to_net(pllinfo["DYNAMICDELAY_%d" % i], "1'b0") for i in range(7, -1, -1)])) text_func.append(" .LOCK(%s)," % seg_to_net(pllinfo["LOCK"])) text_func.append(" .BYPASS(%s)," % seg_to_net(pllinfo["BYPASS"], "1'b0")) text_func.append(" .RESETB(%s)," % seg_to_net(pllinfo["RESETB"], "1'b0")) text_func.append(" .LATCHINPUTVALUE(%s)," % seg_to_net(pllinfo["LATCHINPUTVALUE"], "1'b0")) text_func.append(" .SDO(%s)," % seg_to_net(pllinfo["SDO"])) text_func.append(" .SDI(%s)," % seg_to_net(pllinfo["SDI"], "1'b0")) text_func.append(" .SCLK(%s)" % seg_to_net(pllinfo["SCLK"], "1'b0")) text_func.append(");") if plltype in ["011", "111"]: if plltype == "011": text_func.append("SB_PLL40_CORE #(") if plltype == "111": text_func.append("SB_PLL40_2F_CORE #(") text_func.append(" .FEEDBACK_PATH(\"%s\")," % get_pll_feedback_path(pllinfo)) text_func.append(" .DELAY_ADJUSTMENT_MODE_FEEDBACK(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_FB")) text_func.append(" .DELAY_ADJUSTMENT_MODE_RELATIVE(\"%s\")," % get_pll_adjmode(pllinfo, "DELAY_ADJMODE_REL")) if plltype == "011": text_func.append(" .PLLOUT_SELECT(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A")) else: text_func.append(" .PLLOUT_SELECT_PORTA(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_A")) text_func.append(" .PLLOUT_SELECT_PORTB(\"%s\")," % get_pll_outsel(pllinfo, "PLLOUT_SELECT_B")) text_func.append(" .SHIFTREG_DIV_MODE(1'b%s)," % get_pll_bit(pllinfo, "SHIFTREG_DIV_MODE")) text_func.append(" .FDA_FEEDBACK(4'b%s)," % get_pll_bits(pllinfo, "FDA_FEEDBACK", 4)) text_func.append(" .FDA_RELATIVE(4'b%s)," % get_pll_bits(pllinfo, "FDA_RELATIVE", 4)) text_func.append(" .DIVR(4'b%s)," % get_pll_bits(pllinfo, "DIVR", 4)) text_func.append(" .DIVF(7'b%s)," % get_pll_bits(pllinfo, "DIVF", 7)) text_func.append(" .DIVQ(3'b%s)," % get_pll_bits(pllinfo, "DIVQ", 3)) text_func.append(" .FILTER_RANGE(3'b%s)," % get_pll_bits(pllinfo, "FILTER_RANGE", 3)) if plltype == "011": text_func.append(" .ENABLE_ICEGATE(1'b0),") else: text_func.append(" .ENABLE_ICEGATE_PORTA(1'b0),") text_func.append(" .ENABLE_ICEGATE_PORTB(1'b0),") text_func.append(" .TEST_MODE(1'b%s)" % get_pll_bit(pllinfo, "TEST_MODE")) text_func.append(") PLL_%d_%d (" % pllinfo["LOC"]) text_func.append(" .REFERENCECLK(%s)," % seg_to_net(pllinfo["REFERENCECLK"], "1'b0")) if plltype == "011": pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_A"][2]) text_func.append(" .PLLOUTCORE(%s)," % seg_to_net(pad_segment)) if pllinfo["PLLOUT_A"] in pll_gbuf: text_func.append(" .PLLOUTGLOBAL(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]])) else: pad_segment = (pllinfo["PLLOUT_A"][0], pllinfo["PLLOUT_A"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_A"][2]) text_func.append(" .PLLOUTCOREA(%s)," % seg_to_net(pad_segment)) if pllinfo["PLLOUT_A"] in pll_gbuf: text_func.append(" .PLLOUTGLOBALA(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_A"]])) pad_segment = (pllinfo["PLLOUT_B"][0], pllinfo["PLLOUT_B"][1], "io_%d/D_IN_0" % pllinfo["PLLOUT_B"][2]) text_func.append(" .PLLOUTCOREB(%s)," % seg_to_net(pad_segment)) if pllinfo["PLLOUT_B"] in pll_gbuf: text_func.append(" .PLLOUTGLOBALB(%s)," % seg_to_net(pll_gbuf[pllinfo["PLLOUT_B"]])) text_func.append(" .EXTFEEDBACK(%s)," % seg_to_net(pllinfo["EXTFEEDBACK"], "1'b0")) text_func.append(" .DYNAMICDELAY({%s})," % ", ".join([seg_to_net(pllinfo["DYNAMICDELAY_%d" % i], "1'b0") for i in range(7, -1, -1)])) text_func.append(" .LOCK(%s)," % seg_to_net(pllinfo["LOCK"])) text_func.append(" .BYPASS(%s)," % seg_to_net(pllinfo["BYPASS"], "1'b0")) text_func.append(" .RESETB(%s)," % seg_to_net(pllinfo["RESETB"], "1'b0")) text_func.append(" .LATCHINPUTVALUE(%s)," % seg_to_net(pllinfo["LATCHINPUTVALUE"], "1'b0")) text_func.append(" .SDO(%s)," % seg_to_net(pllinfo["SDO"])) text_func.append(" .SDI(%s)," % seg_to_net(pllinfo["SDI"], "1'b0")) text_func.append(" .SCLK(%s)" % seg_to_net(pllinfo["SCLK"], "1'b0")) text_func.append(");") text_func.append("") for cell in iocells: if cell in iocells_type: net_pad = seg_to_net((cell[0], cell[1], "io_%d/PAD" % cell[2])) net_din0 = seg_to_net((cell[0], cell[1], "io_%d/D_IN_0" % cell[2]), "") net_din1 = seg_to_net((cell[0], cell[1], "io_%d/D_IN_1" % cell[2]), "") net_dout0 = seg_to_net((cell[0], cell[1], "io_%d/D_OUT_0" % cell[2]), "0") net_dout1 = seg_to_net((cell[0], cell[1], "io_%d/D_OUT_1" % cell[2]), "0") net_oen = seg_to_net((cell[0], cell[1], "io_%d/OUT_ENB" % cell[2]), "1") net_cen = seg_to_net((cell[0], cell[1], "io_global/cen"), "1") net_iclk = seg_to_net((cell[0], cell[1], "io_global/inclk"), "0") net_oclk = seg_to_net((cell[0], cell[1], "io_global/outclk"), "0") net_latch = seg_to_net((cell[0], cell[1], "io_global/latch"), "0") iotype = iocells_type[cell] if cell in iocells_negclk: posedge = "negedge" negedge = "posedge" else: posedge = "posedge" negedge = "negedge" text_func.append("// IO Cell %s" % (cell,)) if not strip_comments: text_func.append("// PAD = %s" % net_pad) text_func.append("// D_IN_0 = %s" % net_din0) text_func.append("// D_IN_1 = %s" % net_din1) text_func.append("// D_OUT_0 = %s" % net_dout0) text_func.append("// D_OUT_1 = %s" % net_dout1) text_func.append("// OUT_ENB = %s" % net_oen) text_func.append("// CLK_EN = %s" % net_cen) text_func.append("// IN_CLK = %s" % net_iclk) text_func.append("// OUT_CLK = %s" % net_oclk) text_func.append("// LATCH = %s" % net_latch) text_func.append("// TYPE = %s (LSB:MSB)" % iotype) if net_din0 != "" or net_din1 != "": if net_cen == "1": icen_cond = "" else: icen_cond = "if (%s) " % net_cen if net_din0 != "": if iotype[1] == "0" and iotype[0] == "0": reg_din0 = next_netname() text_func.append("reg %s;" % reg_din0) text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_iclk, icen_cond, reg_din0, net_pad)) text_func.append("assign %s = %s;" % (net_din0, reg_din0)) if iotype[1] == "0" and iotype[0] == "1": text_func.append("assign %s = %s;" % (net_din0, net_pad)) if iotype[1] == "1" and iotype[0] == "0": reg_din0 = next_netname() reg_din0_latched = next_netname() text_func.append("reg %s, %s;" % (reg_din0, reg_din0_latched)) text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_iclk, icen_cond, reg_din0, net_pad)) text_func.append("always @* if (!%s) %s = %s;" % (net_latch, reg_din0_latched, reg_din0)) text_func.append("assign %s = %s;" % (net_din0, reg_din0_latched)) if iotype[1] == "1" and iotype[0] == "1": reg_din0 = next_netname() text_func.append("reg %s;" % reg_din0) text_func.append("always @* if (!%s) %s = %s;" % (net_latch, reg_din0, net_pad)) text_func.append("assign %s = %s;" % (net_din0, reg_din0)) if net_din1 != "": reg_din1 = next_netname() text_func.append("reg %s;" % reg_din1) text_func.append("always @(%s %s) %s%s <= %s;" % (negedge, net_iclk, icen_cond, reg_din1, net_pad)) text_func.append("assign %s = %s;" % (net_din1, reg_din1)) if iotype[5] != "0" or iotype[4] != "0": if net_cen == "1": ocen_cond = "" else: ocen_cond = "if (%s) " % net_cen # effective OEN: iotype[4], iotype[5] if iotype[5] == "0" and iotype[4] == "1": eff_oen = "1" if iotype[5] == "1" and iotype[4] == "0": eff_oen = net_oen if iotype[5] == "1" and iotype[4] == "1": eff_oen = next_netname() text_func.append("reg %s;" % eff_oen) text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_oclk, ocen_cond, eff_oen, net_oen)) # effective DOUT: iotype[2], iotype[3] if iotype[2] == "0" and iotype[3] == "0": ddr_posedge = next_netname() ddr_negedge = next_netname() text_func.append("reg %s, %s;" % (ddr_posedge, ddr_negedge)) text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_oclk, ocen_cond, ddr_posedge, net_dout0)) text_func.append("always @(%s %s) %s%s <= %s;" % (negedge, net_oclk, ocen_cond, ddr_negedge, net_dout1)) eff_dout = next_netname() text_func.append("wire %s;" % (eff_dout)) if cell in iocells_negclk: text_func.append("assign %s = %s ? %s : %s;" % (eff_dout, net_oclk, ddr_negedge, ddr_posedge)) else: text_func.append("assign %s = %s ? %s : %s;" % (eff_dout, net_oclk, ddr_posedge, ddr_negedge)) if iotype[2] == "0" and iotype[3] == "1": eff_dout = net_dout0 if iotype[2] == "1" and iotype[3] == "0": eff_dout = next_netname() text_func.append("reg %s;" % eff_dout) text_func.append("always @(%s %s) %s%s <= %s;" % (posedge, net_oclk, ocen_cond, eff_dout, net_dout0)) if iotype[2] == "1" and iotype[3] == "1": eff_dout = next_netname() text_func.append("reg %s;" % eff_dout) text_func.append("always @(%s %s) %s%s <= !%s;" % (posedge, net_oclk, ocen_cond, eff_dout, net_dout0)) if eff_oen == "1": text_func.append("assign %s = %s;" % (net_pad, eff_dout)) else: text_func.append("assign %s = %s ? %s : 1'bz;" % (net_pad, eff_oen, eff_dout)) text_func.append("") for p in unmatched_ports: text_ports.append("input %s" % p) ram_config_bitidx = dict() for tile in ic.ramb_tiles: for entry in ic.tile_db(tile[0], tile[1]): if entry[1] == "RamConfig": assert entry[2] not in ram_config_bitidx ram_config_bitidx[entry[2]] = ('B', entry[0]) for entry in ic.tile_db(tile[0], tile[1]+1): if entry[1] == "RamConfig": assert entry[2] not in ram_config_bitidx ram_config_bitidx[entry[2]] = ('T', entry[0]) break for tile in ic.ramb_tiles: ramb_config = icebox.tileconfig(ic.tile(tile[0], tile[1])) ramt_config = icebox.tileconfig(ic.tile(tile[0], tile[1]+1)) if ic.device == "8k": negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1" negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1" else: negclk_wr = icebox.get_negclk_bit(ic.tile(tile[0], tile[1])) == "1" negclk_rd = icebox.get_negclk_bit(ic.tile(tile[0], tile[1]+1)) == "1" def get_ram_config(name): assert name in ram_config_bitidx if ram_config_bitidx[name][0] == 'B': return ramb_config.match(ram_config_bitidx[name][1]) elif ram_config_bitidx[name][0] == 'T': return ramt_config.match(ram_config_bitidx[name][1]) else: assert False def get_ram_wire(name, msb, lsb, default="1'b0"): wire_bits = [] for i in range(msb, lsb-1, -1): if msb != lsb: n = "ram/%s_%d" % (name, i) else: n = "ram/" + name b = seg_to_net((tile[0], tile[1], n), default) b = seg_to_net((tile[0], tile[1]+1, n), b) wire_bits.append(b) if len(wire_bits) > 1: return "{%s}" % ", ".join(wire_bits) return wire_bits[0] if get_ram_config('PowerUp') == (ic.device == "8k"): if not strip_comments: text_func.append("// RAM TILE %d %d" % tile) text_func.append("SB_RAM40_4K%s%s #(" % ("NR" if negclk_rd else "", "NW" if negclk_wr else "")); text_func.append(" .READ_MODE(%d)," % ((1 if get_ram_config('CBIT_2') else 0) + (2 if get_ram_config('CBIT_3') else 0))); text_func.append(" .WRITE_MODE(%d)," % ((1 if get_ram_config('CBIT_0') else 0) + (2 if get_ram_config('CBIT_1') else 0))); for i in range(16): text_func.append(" .INIT_%X(256'h%s)%s" % (i, ic.ram_data[tile][i], "," if i < 15 else "")); text_func.append(") ram40_%d_%d (" % tile); text_func.append(" .WADDR(%s)," % get_ram_wire('WADDR', 10, 0)) text_func.append(" .RADDR(%s)," % get_ram_wire('RADDR', 10, 0)) text_func.append(" .MASK(%s)," % get_ram_wire('MASK', 15, 0)) text_func.append(" .WDATA(%s)," % get_ram_wire('WDATA', 15, 0)) text_func.append(" .RDATA(%s)," % get_ram_wire('RDATA', 15, 0, "-")) text_func.append(" .WE(%s)," % get_ram_wire('WE', 0, 0)) text_func.append(" .WCLKE(%s)," % get_ram_wire('WCLKE', 0, 0, "1'b1")) text_func.append(" .WCLK%s(%s)," % ("N" if negclk_wr else "", get_ram_wire('WCLK', 0, 0))) text_func.append(" .RE(%s)," % get_ram_wire('RE', 0, 0)) text_func.append(" .RCLKE(%s)," % get_ram_wire('RCLKE', 0, 0, "1'b1")) text_func.append(" .RCLK%s(%s)" % ("N" if negclk_rd else "", get_ram_wire('RCLK', 0, 0))) text_func.append(");") text_func.append("") wire_to_reg = set() lut_assigns = list() const_assigns = list() carry_assigns = list() always_stmts = list() max_net_len = 0 for lut in luts_queue: seq_bits = icebox.get_lutff_seq_bits(ic.logic_tiles[(lut[0], lut[1])], lut[2]) if seq_bits[0] == "1": seg_to_net((lut[0], lut[1], "lutff_%d/cout" % lut[2])) for lut in luts_queue: tile = ic.logic_tiles[(lut[0], lut[1])] lut_bits = icebox.get_lutff_lut_bits(tile, lut[2]) seq_bits = icebox.get_lutff_seq_bits(tile, lut[2]) net_in0 = seg_to_net((lut[0], lut[1], "lutff_%d/in_0" % lut[2]), "1'b0") net_in1 = seg_to_net((lut[0], lut[1], "lutff_%d/in_1" % lut[2]), "1'b0") net_in2 = seg_to_net((lut[0], lut[1], "lutff_%d/in_2" % lut[2]), "1'b0") net_in3 = seg_to_net((lut[0], lut[1], "lutff_%d/in_3" % lut[2]), "1'b0") net_out = seg_to_net((lut[0], lut[1], "lutff_%d/out" % lut[2])) net_lout = seg_to_net((lut[0], lut[1], "lutff_%d/lout" % lut[2])) if seq_bits[0] == "1": net_cout = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % lut[2])) net_in1 = seg_to_net((lut[0], lut[1], "lutff_%d/in_1" % lut[2]), "1'b0") net_in2 = seg_to_net((lut[0], lut[1], "lutff_%d/in_2" % lut[2]), "1'b0") if lut[2] == 0: net_cin = seg_to_net((lut[0], lut[1], "carry_in_mux")) if icebox.get_carry_cascade_bit(tile) == "0": if not strip_comments: text_wires.append("// Carry-In for (%d %d)" % (lut[0], lut[1])) text_wires.append("assign %s = %s;" % (net_cin, icebox.get_carry_bit(tile))) if not strip_comments: text_wires.append("") else: net_cin = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % (lut[2]-1)), "1'b0") carry_assigns.append([net_cout, "/* CARRY %2d %2d %2d */ (%s & %s) | ((%s | %s) & %s)" % (lut[0], lut[1], lut[2], net_in1, net_in2, net_in1, net_in2, net_cin)]) if seq_bits[1] == "1": net_cen = seg_to_net((lut[0], lut[1], "lutff_global/cen"), "1'b1") net_clk = seg_to_net((lut[0], lut[1], "lutff_global/clk"), "1'b0") net_sr = seg_to_net((lut[0], lut[1], "lutff_global/s_r"), "1'b0") if seq_bits[3] == "0": always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s) if (%s) %s <= %s ? 1'b%s : %s;" % (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos", net_clk, net_cen, net_out, net_sr, seq_bits[2], net_lout)) else: always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s, posedge %s) if (%s) %s <= 1'b%s; else if (%s) %s <= %s;" % (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos", net_clk, net_sr, net_sr, net_out, seq_bits[2], net_cen, net_out, net_lout)) wire_to_reg.add(net_out.strip()) else: always_stmts.append("/* FF %2d %2d %2d */ assign %s = %s;" % (lut[0], lut[1], lut[2], net_out, net_lout)) if not "1" in lut_bits: const_assigns.append([net_out, "1'b0"]) elif not "0" in lut_bits: const_assigns.append([net_out, "1'b1"]) else: def make_lut_expr(bits, sigs): if not sigs: return "1'b%s" % bits[0] l_expr = make_lut_expr(bits[0:len(bits)//2], sigs[1:]) h_expr = make_lut_expr(bits[len(bits)//2:len(bits)], sigs[1:]) if h_expr == l_expr: return h_expr if sigs[0] == "0": return l_expr if sigs[0] == "1": return h_expr if h_expr == "1" and l_expr == "0": return sigs[0] if h_expr == "0" and l_expr == "1": return "!" + sigs[0] return "%s ? %s : %s" % (sigs[0], h_expr, l_expr) lut_expr = make_lut_expr(lut_bits, [net_in3, net_in2, net_in1, net_in0]) lut_assigns.append([net_lout, "/* LUT %2d %2d %2d */ %s" % (lut[0], lut[1], lut[2], lut_expr)]) max_net_len = max(max_net_len, len(net_lout)) for a in const_assigns + lut_assigns + carry_assigns: text_func.append("assign %-*s = %s;" % (max_net_len, a[0], a[1])) if do_collect: new_text_ports = set() vec_ports_min = dict() vec_ports_max = dict() vec_ports_dir = dict() for port in text_ports: match = re.match(r"(input|output|inout) (.*)\[(\d+)\] ?$", port); if match: vec_ports_min[match.group(2)] = min(vec_ports_min.setdefault(match.group(2), int(match.group(3))), int(match.group(3))) vec_ports_max[match.group(2)] = max(vec_ports_max.setdefault(match.group(2), int(match.group(3))), int(match.group(3))) vec_ports_dir[match.group(2)] = match.group(1) else: new_text_ports.add(port) for port, direct in list(vec_ports_dir.items()): min_idx = vec_ports_min[port] max_idx = vec_ports_max[port] new_text_ports.add("%s [%d:%d] %s " % (direct, max_idx, min_idx, port)) text_ports = list(new_text_ports) print("module %s (%s);\n" % (modname, ", ".join(text_ports))) new_text_wires = list() new_text_regs = list() new_text_raw = list() for line in text_wires: match = re.match(r"wire ([^ ;]+)(.*)", line) if match: if strip_comments: name = match.group(1) if name.startswith("\\"): name += " " if match.group(1) in wire_to_reg: new_text_regs.append(name) else: new_text_wires.append(name) continue else: if match.group(1) in wire_to_reg: line = "reg " + match.group(1) + " = 0" + match.group(2) if strip_comments: new_text_raw.append(line) else: print(line) for names in [new_text_wires[x:x+10] for x in range(0, len(new_text_wires), 10)]: print("wire %s;" % ", ".join(names)) for names in [new_text_regs[x:x+10] for x in range(0, len(new_text_regs), 10)]: print("reg %s = 0;" % " = 0, ".join(names)) if strip_comments: for line in new_text_raw: print(line) print() if do_collect: for port, direct in list(vec_ports_dir.items()): min_idx = vec_ports_min[port] max_idx = vec_ports_max[port] for i in range(min_idx, max_idx+1): if direct == "input": print("assign %s[%d] = %s [%d];" % (port, i, port, i)) if direct == "output": print("assign %s [%d] = %s[%d] ;" % (port, i, port, i)) if direct == "inout": print("tran(%s [%d], %s[%d] );" % (port, i, port, i)) print() for line in text_func: print(line) for line in always_stmts: print(line) print() for p in unmatched_ports: print("// Warning: unmatched port '%s'" %p) if unmatched_ports: print() print("endmodule") print() if failed_drivers_check: print("// Single-driver-check failed for %d nets:" % len(failed_drivers_check)) print("// %s" % " ".join(failed_drivers_check)) assert False fpga-icestorm-0~20160913git266e758/icebox/iceboxdb.py000066400000000000000000020047361276746530600220100ustar00rootroot00000000000000database_io_txt = """ B1[9] ColBufCtrl glb_netwk_0 B0[9] ColBufCtrl glb_netwk_1 B3[9] ColBufCtrl glb_netwk_2 B2[9] ColBufCtrl glb_netwk_3 B5[9] ColBufCtrl glb_netwk_4 B4[9] ColBufCtrl glb_netwk_5 B7[9] ColBufCtrl glb_netwk_6 B6[9] ColBufCtrl glb_netwk_7 B3[17] IOB_0 PINTYPE_0 B3[16] IOB_0 PINTYPE_1 B0[17] IOB_0 PINTYPE_2 B0[16] IOB_0 PINTYPE_3 B4[16] IOB_0 PINTYPE_4 B4[17] IOB_0 PINTYPE_5 B13[17] IOB_1 PINTYPE_0 B13[16] IOB_1 PINTYPE_1 B10[17] IOB_1 PINTYPE_2 B10[16] IOB_1 PINTYPE_3 B14[16] IOB_1 PINTYPE_4 B14[17] IOB_1 PINTYPE_5 B11[3] Icegate B9[3] IoCtrl IE_0 B6[3] IoCtrl IE_1 B8[2] IoCtrl LVDS B6[2] IoCtrl REN_0 B1[3] IoCtrl REN_1 B9[13],B15[13] NegClk B0[2] PLL PLLCONFIG_1 B0[3] PLL PLLCONFIG_2 B3[3] PLL PLLCONFIG_3 B2[2] PLL PLLCONFIG_4 B2[3] PLL PLLCONFIG_5 B5[3] PLL PLLCONFIG_6 B4[2] PLL PLLCONFIG_7 B4[3] PLL PLLCONFIG_8 B7[3] PLL PLLCONFIG_9 B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnl_0 lc_trk_g0_0 B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnl_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_B.logic_op_tnl_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_B.logic_op_tnl_1 lc_trk_g1_1 B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_B.logic_op_tnl_2 lc_trk_g0_2 B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_B.logic_op_tnl_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_B.logic_op_tnl_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_B.logic_op_tnl_3 lc_trk_g1_3 B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_B.logic_op_tnl_4 lc_trk_g0_4 B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_B.logic_op_tnl_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_B.logic_op_tnl_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_B.logic_op_tnl_5 lc_trk_g1_5 B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_B.logic_op_tnl_6 lc_trk_g0_6 B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_B.logic_op_tnl_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_B.logic_op_tnl_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_B.logic_op_tnl_7 lc_trk_g1_7 !B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnr_0 lc_trk_g0_0 !B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnr_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_B.logic_op_tnr_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_B.logic_op_tnr_1 lc_trk_g1_1 !B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_B.logic_op_tnr_2 lc_trk_g0_2 !B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_B.logic_op_tnr_2 lc_trk_g1_2 B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_B.logic_op_tnr_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_B.logic_op_tnr_3 lc_trk_g1_3 !B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_B.logic_op_tnr_4 lc_trk_g0_4 !B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_B.logic_op_tnr_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_B.logic_op_tnr_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_B.logic_op_tnr_5 lc_trk_g1_5 !B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_B.logic_op_tnr_6 lc_trk_g0_6 !B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_B.logic_op_tnr_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_B.logic_op_tnr_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_B.logic_op_tnr_7 lc_trk_g1_7 B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_top_0 lc_trk_g0_0 B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_top_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_B.logic_op_top_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_B.logic_op_top_1 lc_trk_g1_1 B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_B.logic_op_top_2 lc_trk_g0_2 B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_B.logic_op_top_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_B.logic_op_top_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_B.logic_op_top_3 lc_trk_g1_3 B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_B.logic_op_top_4 lc_trk_g0_4 B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_B.logic_op_top_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_B.logic_op_top_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_B.logic_op_top_5 lc_trk_g1_5 B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_B.logic_op_top_6 lc_trk_g0_6 B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_B.logic_op_top_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_B.logic_op_top_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_B.logic_op_top_7 lc_trk_g1_7 !B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_L.logic_op_bnr_0 lc_trk_g0_0 !B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_L.logic_op_bnr_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_L.logic_op_bnr_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_L.logic_op_bnr_1 lc_trk_g1_1 !B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_L.logic_op_bnr_2 lc_trk_g0_2 !B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_L.logic_op_bnr_2 lc_trk_g1_2 B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_L.logic_op_bnr_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_L.logic_op_bnr_3 lc_trk_g1_3 !B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_L.logic_op_bnr_4 lc_trk_g0_4 !B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_L.logic_op_bnr_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_L.logic_op_bnr_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_L.logic_op_bnr_5 lc_trk_g1_5 !B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_L.logic_op_bnr_6 lc_trk_g0_6 !B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_L.logic_op_bnr_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_L.logic_op_bnr_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_L.logic_op_bnr_7 lc_trk_g1_7 B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_L.logic_op_rgt_0 lc_trk_g0_0 B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_L.logic_op_rgt_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_L.logic_op_rgt_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_L.logic_op_rgt_1 lc_trk_g1_1 B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_L.logic_op_rgt_2 lc_trk_g0_2 B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_L.logic_op_rgt_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_L.logic_op_rgt_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_L.logic_op_rgt_3 lc_trk_g1_3 B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_L.logic_op_rgt_4 lc_trk_g0_4 B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_L.logic_op_rgt_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_L.logic_op_rgt_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_L.logic_op_rgt_5 lc_trk_g1_5 B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_L.logic_op_rgt_6 lc_trk_g0_6 B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_L.logic_op_rgt_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_L.logic_op_rgt_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_L.logic_op_rgt_7 lc_trk_g1_7 B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_L.logic_op_tnr_0 lc_trk_g0_0 B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_L.logic_op_tnr_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_L.logic_op_tnr_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_L.logic_op_tnr_1 lc_trk_g1_1 B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_L.logic_op_tnr_2 lc_trk_g0_2 B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_L.logic_op_tnr_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_L.logic_op_tnr_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_L.logic_op_tnr_3 lc_trk_g1_3 B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_L.logic_op_tnr_4 lc_trk_g0_4 B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_L.logic_op_tnr_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_L.logic_op_tnr_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_L.logic_op_tnr_5 lc_trk_g1_5 B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_L.logic_op_tnr_6 lc_trk_g0_6 B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_L.logic_op_tnr_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_L.logic_op_tnr_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_L.logic_op_tnr_7 lc_trk_g1_7 !B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_R.logic_op_bnl_0 lc_trk_g0_0 !B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_R.logic_op_bnl_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_R.logic_op_bnl_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_R.logic_op_bnl_1 lc_trk_g1_1 !B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_R.logic_op_bnl_2 lc_trk_g0_2 !B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_R.logic_op_bnl_2 lc_trk_g1_2 B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_R.logic_op_bnl_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_R.logic_op_bnl_3 lc_trk_g1_3 !B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_R.logic_op_bnl_4 lc_trk_g0_4 !B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_R.logic_op_bnl_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_R.logic_op_bnl_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_R.logic_op_bnl_5 lc_trk_g1_5 !B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_R.logic_op_bnl_6 lc_trk_g0_6 !B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_R.logic_op_bnl_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_R.logic_op_bnl_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_R.logic_op_bnl_7 lc_trk_g1_7 B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_R.logic_op_lft_0 lc_trk_g0_0 B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_R.logic_op_lft_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_R.logic_op_lft_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_R.logic_op_lft_1 lc_trk_g1_1 B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_R.logic_op_lft_2 lc_trk_g0_2 B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_R.logic_op_lft_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_R.logic_op_lft_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_R.logic_op_lft_3 lc_trk_g1_3 B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_R.logic_op_lft_4 lc_trk_g0_4 B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_R.logic_op_lft_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_R.logic_op_lft_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_R.logic_op_lft_5 lc_trk_g1_5 B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_R.logic_op_lft_6 lc_trk_g0_6 B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_R.logic_op_lft_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_R.logic_op_lft_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_R.logic_op_lft_7 lc_trk_g1_7 B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_R.logic_op_tnl_0 lc_trk_g0_0 B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_R.logic_op_tnl_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_R.logic_op_tnl_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_R.logic_op_tnl_1 lc_trk_g1_1 B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_R.logic_op_tnl_2 lc_trk_g0_2 B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_R.logic_op_tnl_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_R.logic_op_tnl_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_R.logic_op_tnl_3 lc_trk_g1_3 B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_R.logic_op_tnl_4 lc_trk_g0_4 B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_R.logic_op_tnl_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_R.logic_op_tnl_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_R.logic_op_tnl_5 lc_trk_g1_5 B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_R.logic_op_tnl_6 lc_trk_g0_6 B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_R.logic_op_tnl_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_R.logic_op_tnl_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_R.logic_op_tnl_7 lc_trk_g1_7 B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bnl_0 lc_trk_g0_0 B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bnl_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_T.logic_op_bnl_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_T.logic_op_bnl_1 lc_trk_g1_1 B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bnl_2 lc_trk_g0_2 B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bnl_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_T.logic_op_bnl_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_T.logic_op_bnl_3 lc_trk_g1_3 B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bnl_4 lc_trk_g0_4 B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bnl_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_T.logic_op_bnl_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_T.logic_op_bnl_5 lc_trk_g1_5 B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bnl_6 lc_trk_g0_6 B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bnl_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_T.logic_op_bnl_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_T.logic_op_bnl_7 lc_trk_g1_7 !B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bnr_0 lc_trk_g0_0 !B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bnr_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_T.logic_op_bnr_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_T.logic_op_bnr_1 lc_trk_g1_1 !B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bnr_2 lc_trk_g0_2 !B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bnr_2 lc_trk_g1_2 B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_T.logic_op_bnr_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_T.logic_op_bnr_3 lc_trk_g1_3 !B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bnr_4 lc_trk_g0_4 !B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bnr_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_T.logic_op_bnr_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_T.logic_op_bnr_5 lc_trk_g1_5 !B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bnr_6 lc_trk_g0_6 !B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bnr_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_T.logic_op_bnr_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_T.logic_op_bnr_7 lc_trk_g1_7 B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bot_0 lc_trk_g0_0 B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bot_0 lc_trk_g1_0 !B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_T.logic_op_bot_1 lc_trk_g0_1 !B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_T.logic_op_bot_1 lc_trk_g1_1 B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bot_2 lc_trk_g0_2 B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bot_2 lc_trk_g1_2 !B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_T.logic_op_bot_3 lc_trk_g0_3 !B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_T.logic_op_bot_3 lc_trk_g1_3 B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bot_4 lc_trk_g0_4 B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bot_4 lc_trk_g1_4 !B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_T.logic_op_bot_5 lc_trk_g0_5 !B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_T.logic_op_bot_5 lc_trk_g1_5 B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bot_6 lc_trk_g0_6 B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bot_6 lc_trk_g1_6 !B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_T.logic_op_bot_7 lc_trk_g0_7 !B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_T.logic_op_bot_7 lc_trk_g1_7 !B8[12],!B8[13],!B8[14],!B9[12],B9[15] buffer glb_netwk_0 wire_io_cluster/io_1/inclk !B14[12],!B14[13],!B14[14],!B15[12],B15[15] buffer glb_netwk_0 wire_io_cluster/io_1/outclk !B10[14],B10[15],!B11[14],!B11[15] buffer glb_netwk_1 wire_io_cluster/io_1/cen !B8[12],!B8[13],!B8[14],B9[12],B9[15] buffer glb_netwk_1 wire_io_cluster/io_1/inclk !B14[12],!B14[13],!B14[14],B15[12],B15[15] buffer glb_netwk_1 wire_io_cluster/io_1/outclk B8[12],!B8[13],!B8[14],!B9[12],B9[15] buffer glb_netwk_2 wire_io_cluster/io_1/inclk B14[12],!B14[13],!B14[14],!B15[12],B15[15] buffer glb_netwk_2 wire_io_cluster/io_1/outclk B10[14],B10[15],!B11[14],!B11[15] buffer glb_netwk_3 wire_io_cluster/io_1/cen B8[12],!B8[13],!B8[14],B9[12],B9[15] buffer glb_netwk_3 wire_io_cluster/io_1/inclk B14[12],!B14[13],!B14[14],B15[12],B15[15] buffer glb_netwk_3 wire_io_cluster/io_1/outclk !B8[12],!B8[13],B8[14],!B9[12],B9[15] buffer glb_netwk_4 wire_io_cluster/io_1/inclk !B14[12],!B14[13],B14[14],!B15[12],B15[15] buffer glb_netwk_4 wire_io_cluster/io_1/outclk !B10[14],B10[15],!B11[14],B11[15] buffer glb_netwk_5 wire_io_cluster/io_1/cen !B8[12],!B8[13],B8[14],B9[12],B9[15] buffer glb_netwk_5 wire_io_cluster/io_1/inclk !B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_5 wire_io_cluster/io_1/outclk B8[12],!B8[13],B8[14],!B9[12],B9[15] buffer glb_netwk_6 wire_io_cluster/io_1/inclk B14[12],!B14[13],B14[14],!B15[12],B15[15] buffer glb_netwk_6 wire_io_cluster/io_1/outclk B10[14],B10[15],!B11[14],B11[15] buffer glb_netwk_7 wire_io_cluster/io_1/cen B8[12],!B8[13],B8[14],B9[12],B9[15] buffer glb_netwk_7 wire_io_cluster/io_1/inclk B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_7 wire_io_cluster/io_1/outclk !B4[12],!B4[13],!B5[12],B5[13] buffer lc_trk_g0_0 wire_io_cluster/io_0/D_OUT_0 !B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/D_OUT_1 !B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/OUT_ENB !B8[12],B8[13],!B8[14],!B9[12],B9[15] buffer lc_trk_g0_0 wire_io_cluster/io_1/inclk !B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_1 fabout !B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/D_OUT_1 !B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/OUT_ENB !B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g0_1 wire_io_cluster/io_1/D_OUT_0 !B14[12],B14[13],!B14[14],!B15[12],B15[15] buffer lc_trk_g0_1 wire_io_cluster/io_1/outclk !B4[12],!B4[13],B5[12],B5[13] buffer lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0 !B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/D_OUT_1 !B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/OUT_ENB !B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_2 wire_io_cluster/io_1/cen B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_3 fabout !B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/D_OUT_1 !B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/OUT_ENB !B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0 !B8[12],B8[13],!B8[14],B9[12],B9[15] buffer lc_trk_g0_3 wire_io_cluster/io_1/inclk !B4[12],B4[13],!B5[12],B5[13] buffer lc_trk_g0_4 wire_io_cluster/io_0/D_OUT_0 B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/D_OUT_1 B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/OUT_ENB !B14[12],B14[13],!B14[14],B15[12],B15[15] buffer lc_trk_g0_4 wire_io_cluster/io_1/outclk !B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_5 fabout B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/D_OUT_1 B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/OUT_ENB !B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0 B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_5 wire_io_cluster/io_1/cen !B4[12],B4[13],B5[12],B5[13] buffer lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0 B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1 B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_7 fabout B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1 B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB !B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0 !B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_0 fabout !B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/D_OUT_1 !B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/OUT_ENB B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g1_0 wire_io_cluster/io_1/D_OUT_0 B8[12],B8[13],!B8[14],!B9[12],B9[15] buffer lc_trk_g1_0 wire_io_cluster/io_1/inclk B4[12],!B4[13],!B5[12],B5[13] buffer lc_trk_g1_1 wire_io_cluster/io_0/D_OUT_0 !B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/D_OUT_1 !B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/OUT_ENB B14[12],B14[13],!B14[14],!B15[12],B15[15] buffer lc_trk_g1_1 wire_io_cluster/io_1/outclk B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_2 fabout !B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1 !B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0 !B10[14],B10[15],B11[14],B11[15] buffer lc_trk_g1_2 wire_io_cluster/io_1/cen B4[12],!B4[13],B5[12],B5[13] buffer lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0 !B14[10],B14[11],B15[10],B15[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1 !B10[10],B10[11],B11[10],B11[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB B8[12],B8[13],!B8[14],B9[12],B9[15] buffer lc_trk_g1_3 wire_io_cluster/io_1/inclk !B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_4 fabout B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1 B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0 B14[12],B14[13],!B14[14],B15[12],B15[15] buffer lc_trk_g1_4 wire_io_cluster/io_1/outclk B4[12],B4[13],!B5[12],B5[13] buffer lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0 B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1 B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB B10[14],B10[15],B11[14],B11[15] buffer lc_trk_g1_5 wire_io_cluster/io_1/cen B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_6 fabout B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1 B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0 B4[12],B4[13],B5[12],B5[13] buffer lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0 B14[10],B14[11],B15[10],B15[11] buffer lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1 B10[10],B10[11],B11[10],B11[11] buffer lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span12_horz_0 lc_trk_g0_0 B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span12_horz_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],B0[8],B1[8] buffer span12_horz_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],B8[8],B9[8] buffer span12_horz_1 lc_trk_g1_1 !B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span12_horz_10 lc_trk_g0_2 !B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span12_horz_10 lc_trk_g1_2 !B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span12_horz_11 lc_trk_g0_3 !B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span12_horz_11 lc_trk_g1_3 !B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span12_horz_12 lc_trk_g0_4 !B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span12_horz_12 lc_trk_g1_4 !B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span12_horz_13 lc_trk_g0_5 !B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span12_horz_13 lc_trk_g1_5 !B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span12_horz_14 lc_trk_g0_6 !B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span12_horz_14 lc_trk_g1_6 !B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span12_horz_15 lc_trk_g0_7 !B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span12_horz_15 lc_trk_g1_7 !B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span12_horz_16 lc_trk_g0_0 !B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span12_horz_16 lc_trk_g1_0 !B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span12_horz_17 lc_trk_g0_1 !B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span12_horz_17 lc_trk_g1_1 !B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span12_horz_18 lc_trk_g0_2 !B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span12_horz_18 lc_trk_g1_2 !B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span12_horz_19 lc_trk_g0_3 !B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span12_horz_19 lc_trk_g1_3 B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span12_horz_2 lc_trk_g0_2 B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span12_horz_2 lc_trk_g1_2 !B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span12_horz_20 lc_trk_g0_4 !B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span12_horz_20 lc_trk_g1_4 !B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span12_horz_21 lc_trk_g0_5 !B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span12_horz_21 lc_trk_g1_5 !B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span12_horz_22 lc_trk_g0_6 !B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span12_horz_22 lc_trk_g1_6 !B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span12_horz_23 lc_trk_g0_7 !B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span12_horz_23 lc_trk_g1_7 B2[5],!B2[6],B2[7],B2[8],B3[8] buffer span12_horz_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],B10[8],B11[8] buffer span12_horz_3 lc_trk_g1_3 B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span12_horz_4 lc_trk_g0_4 B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span12_horz_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],B4[8],B5[8] buffer span12_horz_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],B12[8],B13[8] buffer span12_horz_5 lc_trk_g1_5 B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span12_horz_6 lc_trk_g0_6 B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span12_horz_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],B6[8],B7[8] buffer span12_horz_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],B14[8],B15[8] buffer span12_horz_7 lc_trk_g1_7 !B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span12_horz_8 lc_trk_g0_0 !B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span12_horz_8 lc_trk_g1_0 !B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span12_horz_9 lc_trk_g0_1 !B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span12_horz_9 lc_trk_g1_1 B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span12_vert_0 lc_trk_g0_0 B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span12_vert_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],B0[8],B1[8] buffer span12_vert_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],B8[8],B9[8] buffer span12_vert_1 lc_trk_g1_1 !B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span12_vert_10 lc_trk_g0_2 !B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span12_vert_10 lc_trk_g1_2 !B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span12_vert_11 lc_trk_g0_3 !B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span12_vert_11 lc_trk_g1_3 !B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span12_vert_12 lc_trk_g0_4 !B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span12_vert_12 lc_trk_g1_4 !B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span12_vert_13 lc_trk_g0_5 !B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span12_vert_13 lc_trk_g1_5 !B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span12_vert_14 lc_trk_g0_6 !B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span12_vert_14 lc_trk_g1_6 !B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span12_vert_15 lc_trk_g0_7 !B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span12_vert_15 lc_trk_g1_7 !B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span12_vert_16 lc_trk_g0_0 !B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span12_vert_16 lc_trk_g1_0 !B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span12_vert_17 lc_trk_g0_1 !B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span12_vert_17 lc_trk_g1_1 !B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span12_vert_18 lc_trk_g0_2 !B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span12_vert_18 lc_trk_g1_2 !B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span12_vert_19 lc_trk_g0_3 !B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span12_vert_19 lc_trk_g1_3 B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span12_vert_2 lc_trk_g0_2 B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span12_vert_2 lc_trk_g1_2 !B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span12_vert_20 lc_trk_g0_4 !B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span12_vert_20 lc_trk_g1_4 !B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span12_vert_21 lc_trk_g0_5 !B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span12_vert_21 lc_trk_g1_5 !B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span12_vert_22 lc_trk_g0_6 !B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span12_vert_22 lc_trk_g1_6 !B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span12_vert_23 lc_trk_g0_7 !B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span12_vert_23 lc_trk_g1_7 B2[5],!B2[6],B2[7],B2[8],B3[8] buffer span12_vert_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],B10[8],B11[8] buffer span12_vert_3 lc_trk_g1_3 B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span12_vert_4 lc_trk_g0_4 B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span12_vert_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],B4[8],B5[8] buffer span12_vert_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],B12[8],B13[8] buffer span12_vert_5 lc_trk_g1_5 B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span12_vert_6 lc_trk_g0_6 B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span12_vert_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],B6[8],B7[8] buffer span12_vert_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],B14[8],B15[8] buffer span12_vert_7 lc_trk_g1_7 !B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span12_vert_8 lc_trk_g0_0 !B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span12_vert_8 lc_trk_g1_0 !B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span12_vert_9 lc_trk_g0_1 !B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span12_vert_9 lc_trk_g1_1 B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span4_horz_0 lc_trk_g0_0 B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span4_horz_0 lc_trk_g1_0 !B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_1 lc_trk_g0_1 !B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_1 lc_trk_g1_1 B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span4_horz_10 lc_trk_g0_2 B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span4_horz_10 lc_trk_g1_2 !B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_horz_11 lc_trk_g0_3 !B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_horz_11 lc_trk_g1_3 B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span4_horz_12 lc_trk_g0_4 B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span4_horz_12 lc_trk_g1_4 !B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_horz_13 lc_trk_g0_5 !B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_horz_13 lc_trk_g1_5 B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span4_horz_14 lc_trk_g0_6 B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span4_horz_14 lc_trk_g1_6 !B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_horz_15 lc_trk_g0_7 !B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_horz_15 lc_trk_g1_7 !B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_horz_16 lc_trk_g0_0 !B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_horz_16 lc_trk_g1_0 B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span4_horz_17 lc_trk_g0_1 B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span4_horz_17 lc_trk_g1_1 !B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_horz_18 lc_trk_g0_2 !B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_horz_18 lc_trk_g1_2 B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span4_horz_19 lc_trk_g0_3 B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span4_horz_19 lc_trk_g1_3 B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span4_horz_2 lc_trk_g0_2 B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span4_horz_2 lc_trk_g1_2 !B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_horz_20 lc_trk_g0_4 !B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_horz_20 lc_trk_g1_4 B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span4_horz_21 lc_trk_g0_5 B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span4_horz_21 lc_trk_g1_5 !B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_horz_22 lc_trk_g0_6 !B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_horz_22 lc_trk_g1_6 B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span4_horz_23 lc_trk_g0_7 B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span4_horz_23 lc_trk_g1_7 !B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_horz_24 lc_trk_g0_0 !B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_horz_24 lc_trk_g1_0 B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span4_horz_25 lc_trk_g0_1 B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span4_horz_25 lc_trk_g1_1 !B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_horz_26 lc_trk_g0_2 !B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_horz_26 lc_trk_g1_2 B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span4_horz_27 lc_trk_g0_3 B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span4_horz_27 lc_trk_g1_3 !B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_horz_28 lc_trk_g0_4 !B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_horz_28 lc_trk_g1_4 B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span4_horz_29 lc_trk_g0_5 B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span4_horz_29 lc_trk_g1_5 !B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_3 lc_trk_g0_3 !B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_3 lc_trk_g1_3 !B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_horz_30 lc_trk_g0_6 !B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_horz_30 lc_trk_g1_6 B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span4_horz_31 lc_trk_g0_7 B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span4_horz_31 lc_trk_g1_7 B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_horz_32 lc_trk_g0_0 B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_horz_32 lc_trk_g1_0 B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_33 lc_trk_g0_1 B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_33 lc_trk_g1_1 B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_horz_34 lc_trk_g0_2 B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_horz_34 lc_trk_g1_2 B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_35 lc_trk_g0_3 B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_35 lc_trk_g1_3 B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_horz_36 lc_trk_g0_4 B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_horz_36 lc_trk_g1_4 B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_37 lc_trk_g0_5 B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_37 lc_trk_g1_5 B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_horz_38 lc_trk_g0_6 B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_horz_38 lc_trk_g1_6 B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_39 lc_trk_g0_7 B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_39 lc_trk_g1_7 B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span4_horz_4 lc_trk_g0_4 B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span4_horz_4 lc_trk_g1_4 B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_horz_40 lc_trk_g0_0 B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_horz_40 lc_trk_g1_0 B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_horz_41 lc_trk_g0_1 B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_horz_41 lc_trk_g1_1 B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_horz_42 lc_trk_g0_2 B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_horz_42 lc_trk_g1_2 B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_horz_43 lc_trk_g0_3 B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_horz_43 lc_trk_g1_3 B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_horz_44 lc_trk_g0_4 B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_horz_44 lc_trk_g1_4 B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_horz_45 lc_trk_g0_5 B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_horz_45 lc_trk_g1_5 B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_horz_46 lc_trk_g0_6 B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_horz_46 lc_trk_g1_6 B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_horz_47 lc_trk_g0_7 B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_horz_47 lc_trk_g1_7 !B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_5 lc_trk_g0_5 !B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_5 lc_trk_g1_5 B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span4_horz_6 lc_trk_g0_6 B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span4_horz_6 lc_trk_g1_6 !B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_7 lc_trk_g0_7 !B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_7 lc_trk_g1_7 B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span4_horz_8 lc_trk_g0_0 B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span4_horz_8 lc_trk_g1_0 !B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_horz_9 lc_trk_g0_1 !B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_horz_9 lc_trk_g1_1 !B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span4_horz_r_0 lc_trk_g0_0 !B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span4_horz_r_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],!B0[8],B1[8] buffer span4_horz_r_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],!B8[8],B9[8] buffer span4_horz_r_1 lc_trk_g1_1 B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer span4_horz_r_10 lc_trk_g0_2 B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer span4_horz_r_10 lc_trk_g1_2 B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_r_11 lc_trk_g0_3 B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_r_11 lc_trk_g1_3 B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer span4_horz_r_12 lc_trk_g0_4 B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer span4_horz_r_12 lc_trk_g1_4 B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_r_13 lc_trk_g0_5 B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_r_13 lc_trk_g1_5 B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer span4_horz_r_14 lc_trk_g0_6 B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer span4_horz_r_14 lc_trk_g1_6 B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_r_15 lc_trk_g0_7 B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_r_15 lc_trk_g1_7 !B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span4_horz_r_2 lc_trk_g0_2 !B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span4_horz_r_2 lc_trk_g1_2 B2[5],!B2[6],B2[7],!B2[8],B3[8] buffer span4_horz_r_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],!B10[8],B11[8] buffer span4_horz_r_3 lc_trk_g1_3 !B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span4_horz_r_4 lc_trk_g0_4 !B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span4_horz_r_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],!B4[8],B5[8] buffer span4_horz_r_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],!B12[8],B13[8] buffer span4_horz_r_5 lc_trk_g1_5 !B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span4_horz_r_6 lc_trk_g0_6 !B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span4_horz_r_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],!B6[8],B7[8] buffer span4_horz_r_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],!B14[8],B15[8] buffer span4_horz_r_7 lc_trk_g1_7 B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer span4_horz_r_8 lc_trk_g0_0 B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer span4_horz_r_8 lc_trk_g1_0 B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_r_9 lc_trk_g0_1 B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_r_9 lc_trk_g1_1 B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span4_vert_0 lc_trk_g0_0 B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span4_vert_0 lc_trk_g1_0 !B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_1 lc_trk_g0_1 !B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_1 lc_trk_g1_1 B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span4_vert_10 lc_trk_g0_2 B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span4_vert_10 lc_trk_g1_2 !B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_vert_11 lc_trk_g0_3 !B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_vert_11 lc_trk_g1_3 B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span4_vert_12 lc_trk_g0_4 B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span4_vert_12 lc_trk_g1_4 !B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_vert_13 lc_trk_g0_5 !B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_vert_13 lc_trk_g1_5 B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span4_vert_14 lc_trk_g0_6 B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span4_vert_14 lc_trk_g1_6 !B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_vert_15 lc_trk_g0_7 !B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_vert_15 lc_trk_g1_7 !B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_vert_16 lc_trk_g0_0 !B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_vert_16 lc_trk_g1_0 B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span4_vert_17 lc_trk_g0_1 B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span4_vert_17 lc_trk_g1_1 !B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_vert_18 lc_trk_g0_2 !B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_vert_18 lc_trk_g1_2 B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span4_vert_19 lc_trk_g0_3 B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span4_vert_19 lc_trk_g1_3 B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span4_vert_2 lc_trk_g0_2 B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span4_vert_2 lc_trk_g1_2 !B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_vert_20 lc_trk_g0_4 !B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_vert_20 lc_trk_g1_4 B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span4_vert_21 lc_trk_g0_5 B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span4_vert_21 lc_trk_g1_5 !B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_vert_22 lc_trk_g0_6 !B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_vert_22 lc_trk_g1_6 B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span4_vert_23 lc_trk_g0_7 B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span4_vert_23 lc_trk_g1_7 !B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_vert_24 lc_trk_g0_0 !B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_vert_24 lc_trk_g1_0 B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span4_vert_25 lc_trk_g0_1 B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span4_vert_25 lc_trk_g1_1 !B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_vert_26 lc_trk_g0_2 !B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_vert_26 lc_trk_g1_2 B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span4_vert_27 lc_trk_g0_3 B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span4_vert_27 lc_trk_g1_3 !B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_vert_28 lc_trk_g0_4 !B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_vert_28 lc_trk_g1_4 B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span4_vert_29 lc_trk_g0_5 B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span4_vert_29 lc_trk_g1_5 !B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_3 lc_trk_g0_3 !B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_3 lc_trk_g1_3 !B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_vert_30 lc_trk_g0_6 !B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_vert_30 lc_trk_g1_6 B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span4_vert_31 lc_trk_g0_7 B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span4_vert_31 lc_trk_g1_7 B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_vert_32 lc_trk_g0_0 B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_vert_32 lc_trk_g1_0 B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_33 lc_trk_g0_1 B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_33 lc_trk_g1_1 B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_vert_34 lc_trk_g0_2 B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_vert_34 lc_trk_g1_2 B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_35 lc_trk_g0_3 B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_35 lc_trk_g1_3 B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_vert_36 lc_trk_g0_4 B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_vert_36 lc_trk_g1_4 B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_37 lc_trk_g0_5 B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_37 lc_trk_g1_5 B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_vert_38 lc_trk_g0_6 B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_vert_38 lc_trk_g1_6 B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_39 lc_trk_g0_7 B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_39 lc_trk_g1_7 B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span4_vert_4 lc_trk_g0_4 B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span4_vert_4 lc_trk_g1_4 B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_vert_40 lc_trk_g0_0 B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_vert_40 lc_trk_g1_0 B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_vert_41 lc_trk_g0_1 B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_vert_41 lc_trk_g1_1 B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_vert_42 lc_trk_g0_2 B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_vert_42 lc_trk_g1_2 B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_vert_43 lc_trk_g0_3 B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_vert_43 lc_trk_g1_3 B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_vert_44 lc_trk_g0_4 B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_vert_44 lc_trk_g1_4 B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_vert_45 lc_trk_g0_5 B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_vert_45 lc_trk_g1_5 B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_vert_46 lc_trk_g0_6 B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_vert_46 lc_trk_g1_6 B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_vert_47 lc_trk_g0_7 B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_vert_47 lc_trk_g1_7 !B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_5 lc_trk_g0_5 !B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_5 lc_trk_g1_5 B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span4_vert_6 lc_trk_g0_6 B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span4_vert_6 lc_trk_g1_6 !B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_7 lc_trk_g0_7 !B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_7 lc_trk_g1_7 B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span4_vert_8 lc_trk_g0_0 B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span4_vert_8 lc_trk_g1_0 !B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_vert_9 lc_trk_g0_1 !B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_vert_9 lc_trk_g1_1 !B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span4_vert_b_0 lc_trk_g0_0 !B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span4_vert_b_0 lc_trk_g1_0 B0[5],!B0[6],B0[7],!B0[8],B1[8] buffer span4_vert_b_1 lc_trk_g0_1 B8[5],!B8[6],B8[7],!B8[8],B9[8] buffer span4_vert_b_1 lc_trk_g1_1 B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer span4_vert_b_10 lc_trk_g0_2 B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer span4_vert_b_10 lc_trk_g1_2 B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_b_11 lc_trk_g0_3 B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_b_11 lc_trk_g1_3 B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer span4_vert_b_12 lc_trk_g0_4 B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer span4_vert_b_12 lc_trk_g1_4 B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_b_13 lc_trk_g0_5 B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_b_13 lc_trk_g1_5 B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer span4_vert_b_14 lc_trk_g0_6 B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer span4_vert_b_14 lc_trk_g1_6 B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_b_15 lc_trk_g0_7 B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_b_15 lc_trk_g1_7 !B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span4_vert_b_2 lc_trk_g0_2 !B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span4_vert_b_2 lc_trk_g1_2 B2[5],!B2[6],B2[7],!B2[8],B3[8] buffer span4_vert_b_3 lc_trk_g0_3 B10[5],!B10[6],B10[7],!B10[8],B11[8] buffer span4_vert_b_3 lc_trk_g1_3 !B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span4_vert_b_4 lc_trk_g0_4 !B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span4_vert_b_4 lc_trk_g1_4 B4[5],!B4[6],B4[7],!B4[8],B5[8] buffer span4_vert_b_5 lc_trk_g0_5 B12[5],!B12[6],B12[7],!B12[8],B13[8] buffer span4_vert_b_5 lc_trk_g1_5 !B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span4_vert_b_6 lc_trk_g0_6 !B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span4_vert_b_6 lc_trk_g1_6 B6[5],!B6[6],B6[7],!B6[8],B7[8] buffer span4_vert_b_7 lc_trk_g0_7 B14[5],!B14[6],B14[7],!B14[8],B15[8] buffer span4_vert_b_7 lc_trk_g1_7 B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer span4_vert_b_8 lc_trk_g0_0 B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer span4_vert_b_8 lc_trk_g1_0 B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_b_9 lc_trk_g0_1 B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_b_9 lc_trk_g1_1 B1[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_0 B5[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_16 B2[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_8 B1[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_0 B5[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_16 B2[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_8 B1[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_0 B0[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_16 B0[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_24 B1[2] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_32 B3[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_40 B1[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_8 B3[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_0 B3[2] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_12 B2[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_4 B2[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_8 B1[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_0 B0[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_16 B0[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_24 B1[2] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_32 B3[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_40 B1[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_8 B3[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_0 B3[2] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_12 B2[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_4 B2[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_8 B7[17] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_10 B6[16] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_18 B7[16] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_2 B7[17] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_10 B6[16] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_18 B7[16] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_2 B5[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_10 B4[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_18 B5[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_2 B4[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_26 B5[2] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_34 B7[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_42 B7[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_1 B7[2] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_13 B6[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_5 B6[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_9 B5[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_10 B4[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_18 B5[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_2 B4[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_26 B5[2] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_34 B7[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_42 B7[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_1 B7[2] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_13 B6[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_5 B6[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_9 B9[17] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_12 B8[16] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_20 B9[16] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_4 B9[17] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_12 B8[16] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_20 B9[16] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_4 B9[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_12 B8[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_20 B8[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_28 B9[2] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_36 B9[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_4 B11[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_44 B10[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_10 B11[2] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_14 B11[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_2 B10[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_6 B9[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_12 B8[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_20 B8[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_28 B9[2] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_36 B9[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_4 B11[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_44 B10[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_10 B11[2] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_14 B11[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_2 B10[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_6 B12[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_14 B15[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_22 B11[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_6 B12[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_14 B15[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_22 B11[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_6 B13[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_14 B12[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_22 B12[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_30 B13[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_38 B15[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_46 B13[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_6 B14[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_11 B15[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_15 B15[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_3 B14[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_7 B13[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_14 B12[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_22 B12[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_30 B13[2] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_38 B15[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_46 B13[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_6 B14[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_11 B15[2] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_15 B15[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_3 B14[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_7 B1[11],B1[12] routing span4_horz_1 span4_horz_25 B1[13],B1[14] routing span4_horz_1 span4_vert_b_0 B0[11],B0[12] routing span4_horz_1 span4_vert_t_12 B7[11],B7[12] routing span4_horz_13 span4_horz_37 B7[13],B7[14] routing span4_horz_13 span4_vert_b_2 B6[11],B6[12] routing span4_horz_13 span4_vert_t_14 B13[11],B13[12] routing span4_horz_19 span4_horz_43 B13[13],B13[14] routing span4_horz_19 span4_vert_b_3 B12[11],B12[12] routing span4_horz_19 span4_vert_t_15 B0[13],!B0[14] routing span4_horz_25 span4_horz_1 B1[13],!B1[14] routing span4_horz_25 span4_vert_b_0 !B0[11],B0[12] routing span4_horz_25 span4_vert_t_12 B2[13],!B2[14] routing span4_horz_31 span4_horz_7 B3[13],!B3[14] routing span4_horz_31 span4_vert_b_1 !B2[11],B2[12] routing span4_horz_31 span4_vert_t_13 B6[13],!B6[14] routing span4_horz_37 span4_horz_13 B7[13],!B7[14] routing span4_horz_37 span4_vert_b_2 !B6[11],B6[12] routing span4_horz_37 span4_vert_t_14 B12[13],!B12[14] routing span4_horz_43 span4_horz_19 B13[13],!B13[14] routing span4_horz_43 span4_vert_b_3 !B12[11],B12[12] routing span4_horz_43 span4_vert_t_15 B3[11],B3[12] routing span4_horz_7 span4_horz_31 B3[13],B3[14] routing span4_horz_7 span4_vert_b_1 B2[11],B2[12] routing span4_horz_7 span4_vert_t_13 !B1[13],B1[14] routing span4_horz_l_12 span4_horz_r_0 !B0[13],B0[14] routing span4_horz_l_12 span4_vert_1 B1[11],!B1[12] routing span4_horz_l_12 span4_vert_25 !B3[13],B3[14] routing span4_horz_l_13 span4_horz_r_1 B3[11],!B3[12] routing span4_horz_l_13 span4_vert_31 !B2[13],B2[14] routing span4_horz_l_13 span4_vert_7 !B7[13],B7[14] routing span4_horz_l_14 span4_horz_r_2 !B6[13],B6[14] routing span4_horz_l_14 span4_vert_13 B7[11],!B7[12] routing span4_horz_l_14 span4_vert_37 !B13[13],B13[14] routing span4_horz_l_15 span4_horz_r_3 !B12[13],B12[14] routing span4_horz_l_15 span4_vert_19 B13[11],!B13[12] routing span4_horz_l_15 span4_vert_43 B0[11],!B0[12] routing span4_horz_r_0 span4_horz_l_12 B0[13],B0[14] routing span4_horz_r_0 span4_vert_1 !B1[11],B1[12] routing span4_horz_r_0 span4_vert_25 B2[11],!B2[12] routing span4_horz_r_1 span4_horz_l_13 !B3[11],B3[12] routing span4_horz_r_1 span4_vert_31 B2[13],B2[14] routing span4_horz_r_1 span4_vert_7 B6[11],!B6[12] routing span4_horz_r_2 span4_horz_l_14 B6[13],B6[14] routing span4_horz_r_2 span4_vert_13 !B7[11],B7[12] routing span4_horz_r_2 span4_vert_37 B12[11],!B12[12] routing span4_horz_r_3 span4_horz_l_15 B12[13],B12[14] routing span4_horz_r_3 span4_vert_19 !B13[11],B13[12] routing span4_horz_r_3 span4_vert_43 B0[11],B0[12] routing span4_vert_1 span4_horz_l_12 B1[13],B1[14] routing span4_vert_1 span4_horz_r_0 B1[11],B1[12] routing span4_vert_1 span4_vert_25 B6[11],B6[12] routing span4_vert_13 span4_horz_l_14 B7[13],B7[14] routing span4_vert_13 span4_horz_r_2 B7[11],B7[12] routing span4_vert_13 span4_vert_37 B12[11],B12[12] routing span4_vert_19 span4_horz_l_15 B13[13],B13[14] routing span4_vert_19 span4_horz_r_3 B13[11],B13[12] routing span4_vert_19 span4_vert_43 !B0[11],B0[12] routing span4_vert_25 span4_horz_l_12 B1[13],!B1[14] routing span4_vert_25 span4_horz_r_0 B0[13],!B0[14] routing span4_vert_25 span4_vert_1 !B2[11],B2[12] routing span4_vert_31 span4_horz_l_13 B3[13],!B3[14] routing span4_vert_31 span4_horz_r_1 B2[13],!B2[14] routing span4_vert_31 span4_vert_7 !B6[11],B6[12] routing span4_vert_37 span4_horz_l_14 B7[13],!B7[14] routing span4_vert_37 span4_horz_r_2 B6[13],!B6[14] routing span4_vert_37 span4_vert_13 !B12[11],B12[12] routing span4_vert_43 span4_horz_l_15 B13[13],!B13[14] routing span4_vert_43 span4_horz_r_3 B12[13],!B12[14] routing span4_vert_43 span4_vert_19 B2[11],B2[12] routing span4_vert_7 span4_horz_l_13 B3[13],B3[14] routing span4_vert_7 span4_horz_r_1 B3[11],B3[12] routing span4_vert_7 span4_vert_31 B0[13],B0[14] routing span4_vert_b_0 span4_horz_1 !B1[11],B1[12] routing span4_vert_b_0 span4_horz_25 B0[11],!B0[12] routing span4_vert_b_0 span4_vert_t_12 !B3[11],B3[12] routing span4_vert_b_1 span4_horz_31 B2[13],B2[14] routing span4_vert_b_1 span4_horz_7 B2[11],!B2[12] routing span4_vert_b_1 span4_vert_t_13 B6[13],B6[14] routing span4_vert_b_2 span4_horz_13 !B7[11],B7[12] routing span4_vert_b_2 span4_horz_37 B6[11],!B6[12] routing span4_vert_b_2 span4_vert_t_14 B12[13],B12[14] routing span4_vert_b_3 span4_horz_19 !B13[11],B13[12] routing span4_vert_b_3 span4_horz_43 B12[11],!B12[12] routing span4_vert_b_3 span4_vert_t_15 !B0[13],B0[14] routing span4_vert_t_12 span4_horz_1 B1[11],!B1[12] routing span4_vert_t_12 span4_horz_25 !B1[13],B1[14] routing span4_vert_t_12 span4_vert_b_0 B3[11],!B3[12] routing span4_vert_t_13 span4_horz_31 !B2[13],B2[14] routing span4_vert_t_13 span4_horz_7 !B3[13],B3[14] routing span4_vert_t_13 span4_vert_b_1 !B6[13],B6[14] routing span4_vert_t_14 span4_horz_13 B7[11],!B7[12] routing span4_vert_t_14 span4_horz_37 !B7[13],B7[14] routing span4_vert_t_14 span4_vert_b_2 !B12[13],B12[14] routing span4_vert_t_15 span4_horz_19 B13[11],!B13[12] routing span4_vert_t_15 span4_horz_43 !B13[13],B13[14] routing span4_vert_t_15 span4_vert_b_3 """ database_logic_txt = """ B0[1] ColBufCtrl 1k_glb_netwk_0 B1[2] ColBufCtrl 1k_glb_netwk_1 B5[2] ColBufCtrl 1k_glb_netwk_2 B7[2] ColBufCtrl 1k_glb_netwk_3 B9[2] ColBufCtrl 1k_glb_netwk_4 B11[2] ColBufCtrl 1k_glb_netwk_5 B13[2] ColBufCtrl 1k_glb_netwk_6 B15[2] ColBufCtrl 1k_glb_netwk_7 B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 B11[7] ColBufCtrl 8k_glb_netwk_2 B10[7] ColBufCtrl 8k_glb_netwk_3 B13[7] ColBufCtrl 8k_glb_netwk_4 B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 B0[36],B0[37],B0[38],B0[39],B0[40],B0[41],B0[42],B0[43],B0[44],B0[45],B1[36],B1[37],B1[38],B1[39],B1[40],B1[41],B1[42],B1[43],B1[44],B1[45] LC_0 B2[36],B2[37],B2[38],B2[39],B2[40],B2[41],B2[42],B2[43],B2[44],B2[45],B3[36],B3[37],B3[38],B3[39],B3[40],B3[41],B3[42],B3[43],B3[44],B3[45] LC_1 B4[36],B4[37],B4[38],B4[39],B4[40],B4[41],B4[42],B4[43],B4[44],B4[45],B5[36],B5[37],B5[38],B5[39],B5[40],B5[41],B5[42],B5[43],B5[44],B5[45] LC_2 B6[36],B6[37],B6[38],B6[39],B6[40],B6[41],B6[42],B6[43],B6[44],B6[45],B7[36],B7[37],B7[38],B7[39],B7[40],B7[41],B7[42],B7[43],B7[44],B7[45] LC_3 B8[36],B8[37],B8[38],B8[39],B8[40],B8[41],B8[42],B8[43],B8[44],B8[45],B9[36],B9[37],B9[38],B9[39],B9[40],B9[41],B9[42],B9[43],B9[44],B9[45] LC_4 B10[36],B10[37],B10[38],B10[39],B10[40],B10[41],B10[42],B10[43],B10[44],B10[45],B11[36],B11[37],B11[38],B11[39],B11[40],B11[41],B11[42],B11[43],B11[44],B11[45] LC_5 B12[36],B12[37],B12[38],B12[39],B12[40],B12[41],B12[42],B12[43],B12[44],B12[45],B13[36],B13[37],B13[38],B13[39],B13[40],B13[41],B13[42],B13[43],B13[44],B13[45] LC_6 B14[36],B14[37],B14[38],B14[39],B14[40],B14[41],B14[42],B14[43],B14[44],B14[45],B15[36],B15[37],B15[38],B15[39],B15[40],B15[41],B15[42],B15[43],B15[44],B15[45] LC_7 B0[0] NegClk B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 !B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 !B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 !B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 !B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 !B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 !B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer bot_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer bot_op_1 lc_trk_g1_1 !B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 !B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 !B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer bot_op_3 lc_trk_g0_3 !B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer bot_op_3 lc_trk_g1_3 !B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 !B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer bot_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer bot_op_5 lc_trk_g1_5 !B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 !B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 !B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer bot_op_7 lc_trk_g0_7 !B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer bot_op_7 lc_trk_g1_7 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 !B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 !B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 !B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 !B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 !B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_logic_cluster/lc_7/clk !B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_logic_cluster/lc_7/s_r !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_logic_cluster/lc_7/cen !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_logic_cluster/lc_7/clk B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_logic_cluster/lc_7/clk !B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_logic_cluster/lc_7/s_r B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 !B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_logic_cluster/lc_7/cen B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_logic_cluster/lc_7/clk !B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 !B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 !B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_logic_cluster/lc_7/clk B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_logic_cluster/lc_7/s_r !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 !B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_logic_cluster/lc_7/cen !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_logic_cluster/lc_7/clk B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_logic_cluster/lc_7/clk B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_logic_cluster/lc_7/s_r B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_logic_cluster/lc_7/cen B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_logic_cluster/lc_7/clk !B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_0 input_2_0 !B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_0 input_2_2 !B8[35],B9[32],!B9[33],!B9[34],!B9[35] buffer lc_trk_g0_0 input_2_4 !B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input_2_6 !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_0/in_0 !B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_1/in_1 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_2/in_0 !B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_3/in_1 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_4/in_0 !B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_5/in_1 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_6/in_0 !B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_logic_cluster/lc_7/clk !B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_7/in_1 !B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_1 input_2_1 !B6[35],B7[32],!B7[33],!B7[34],!B7[35] buffer lc_trk_g0_1 input_2_3 !B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input_2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input_2_7 !B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_0/in_1 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_1/in_0 !B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_2/in_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_3/in_0 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_4/in_1 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_5/in_0 !B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_6/in_1 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_7/in_0 !B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_2 input_2_0 !B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_2 input_2_2 !B8[35],B9[32],!B9[33],!B9[34],B9[35] buffer lc_trk_g0_2 input_2_4 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input_2_6 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_0/in_0 !B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_1/in_1 !B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_1/in_3 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_2/in_0 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_3/in_1 !B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_3/in_3 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_4/in_0 !B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_5/in_1 !B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_5/in_3 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_6/in_0 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/cen !B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/in_1 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/in_3 !B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_3 input_2_1 !B6[35],B7[32],!B7[33],!B7[34],B7[35] buffer lc_trk_g0_3 input_2_3 !B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input_2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input_2_7 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_0/in_1 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_0/in_3 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_1/in_0 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_2/in_1 !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_2/in_3 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_3/in_0 !B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_4/in_1 !B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_4/in_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_5/in_0 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_6/in_1 !B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_6/in_3 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_4 input_2_0 B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_4 input_2_2 B8[35],B9[32],!B9[33],!B9[34],!B9[35] buffer lc_trk_g0_4 input_2_4 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input_2_6 B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_0/in_0 !B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_1/in_3 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_2/in_0 !B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_3/in_3 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_4/in_0 !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_5/in_3 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_6/in_0 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/in_3 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/s_r B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_5 input_2_1 B6[35],B7[32],!B7[33],!B7[34],!B7[35] buffer lc_trk_g0_5 input_2_3 B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input_2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input_2_7 !B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_0/in_3 B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_1/in_0 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_2/in_3 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_3/in_0 !B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_4/in_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_5/in_0 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_6/in_3 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_6 input_2_0 B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_6 input_2_2 B8[35],B9[32],!B9[33],!B9[34],B9[35] buffer lc_trk_g0_6 input_2_4 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input_2_6 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_0/in_0 !B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_1/in_3 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_2/in_0 !B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_3/in_3 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_4/in_0 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_5/in_3 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_6/in_0 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_7/in_3 B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_7 input_2_1 B6[35],B7[32],!B7[33],!B7[34],B7[35] buffer lc_trk_g0_7 input_2_3 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input_2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input_2_7 !B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_0/in_3 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_1/in_0 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_2/in_3 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_3/in_0 !B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_4/in_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_5/in_0 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_6/in_3 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_7/in_0 !B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_0 input_2_1 !B6[35],B7[32],!B7[33],B7[34],!B7[35] buffer lc_trk_g1_0 input_2_3 !B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input_2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input_2_7 B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_0/in_1 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_0/in_3 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_1/in_0 B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_2/in_1 !B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_2/in_3 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_3/in_0 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_4/in_1 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_4/in_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_5/in_0 B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_6/in_1 !B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_6/in_3 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_7/in_0 !B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_1 input_2_0 !B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_1 input_2_2 !B8[35],B9[32],!B9[33],B9[34],!B9[35] buffer lc_trk_g1_1 input_2_4 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input_2_6 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_0/in_0 B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_1/in_1 !B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_1/in_3 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_2/in_0 B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_3/in_1 !B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_3/in_3 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_4/in_0 B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_5/in_1 !B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_5/in_3 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_6/in_0 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/clk B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/in_1 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/in_3 !B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_2 input_2_1 !B6[35],B7[32],!B7[33],B7[34],B7[35] buffer lc_trk_g1_2 input_2_3 !B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input_2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input_2_7 B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_0/in_1 !B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_0/in_3 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_1/in_0 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_2/in_1 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_2/in_3 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_3/in_0 B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_4/in_1 !B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_4/in_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_5/in_0 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_6/in_1 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_6/in_3 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_7/in_0 !B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_3 input_2_0 !B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_3 input_2_2 !B8[35],B9[32],!B9[33],B9[34],B9[35] buffer lc_trk_g1_3 input_2_4 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input_2_6 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_0/in_0 B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_1/in_1 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_1/in_3 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_2/in_0 B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_3/in_1 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_3/in_3 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_4/in_0 B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_5/in_1 !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_5/in_3 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_6/in_0 !B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/cen B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/in_1 !B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/in_3 B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_4 input_2_1 B6[35],B7[32],!B7[33],B7[34],!B7[35] buffer lc_trk_g1_4 input_2_3 B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input_2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input_2_7 B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_0/in_3 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_1/in_0 B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_2/in_3 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_3/in_0 B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_4/in_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_5/in_0 B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_6/in_3 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_5 input_2_0 B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_5 input_2_2 B8[35],B9[32],!B9[33],B9[34],!B9[35] buffer lc_trk_g1_5 input_2_4 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input_2_6 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_0/in_0 B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_1/in_3 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_2/in_0 B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_3/in_3 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_4/in_0 B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_5/in_3 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_6/in_0 B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/in_3 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/s_r B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_6 input_2_1 B6[35],B7[32],!B7[33],B7[34],B7[35] buffer lc_trk_g1_6 input_2_3 B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input_2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input_2_7 B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_0/in_3 B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_1/in_0 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_2/in_3 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_3/in_0 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_4/in_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_5/in_0 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_6/in_3 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_7 input_2_0 B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_7 input_2_2 B8[35],B9[32],!B9[33],B9[34],B9[35] buffer lc_trk_g1_7 input_2_4 B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input_2_6 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_0/in_0 B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_1/in_3 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_2/in_0 B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_3/in_3 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_4/in_0 B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_5/in_3 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_6/in_0 B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_7/in_3 !B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_0 input_2_0 !B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_0 input_2_2 !B8[35],B9[32],B9[33],!B9[34],!B9[35] buffer lc_trk_g2_0 input_2_4 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input_2_6 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_0/in_0 !B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_1/in_1 !B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_1/in_3 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_2/in_0 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_3/in_1 !B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_3/in_3 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_4/in_0 !B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_5/in_1 !B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_5/in_3 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_6/in_0 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/clk !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/in_1 !B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/in_3 !B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_1 input_2_1 !B6[35],B7[32],B7[33],!B7[34],!B7[35] buffer lc_trk_g2_1 input_2_3 !B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input_2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input_2_7 !B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_0/in_1 !B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_0/in_3 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_1/in_0 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_2/in_1 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_2/in_3 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_3/in_0 !B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_4/in_1 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_4/in_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_5/in_0 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_6/in_1 !B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_6/in_3 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_7/in_0 !B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_2 input_2_0 !B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_2 input_2_2 !B8[35],B9[32],B9[33],!B9[34],B9[35] buffer lc_trk_g2_2 input_2_4 !B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input_2_6 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_0/in_0 !B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_1/in_1 !B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_1/in_3 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_2/in_0 !B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_3/in_1 !B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_3/in_3 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_4/in_0 !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_5/in_1 !B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_5/in_3 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_6/in_0 B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/cen !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/in_1 !B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/in_3 !B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_3 input_2_1 !B6[35],B7[32],B7[33],!B7[34],B7[35] buffer lc_trk_g2_3 input_2_3 !B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input_2_5 !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input_2_7 !B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_0/in_1 !B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_0/in_3 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_1/in_0 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_2/in_1 !B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_2/in_3 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_3/in_0 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_4/in_1 !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_4/in_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_5/in_0 !B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_6/in_1 !B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_6/in_3 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_4 input_2_0 B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_4 input_2_2 B8[35],B9[32],B9[33],!B9[34],!B9[35] buffer lc_trk_g2_4 input_2_4 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input_2_6 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_0/in_0 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_1/in_3 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_2/in_0 !B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_3/in_3 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_4/in_0 !B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_5/in_3 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_6/in_0 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/in_3 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/s_r B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_5 input_2_1 B6[35],B7[32],B7[33],!B7[34],!B7[35] buffer lc_trk_g2_5 input_2_3 B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input_2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input_2_7 !B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_0/in_3 B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_1/in_0 !B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_2/in_3 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_3/in_0 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_4/in_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_5/in_0 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_6/in_3 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_6 input_2_0 B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_6 input_2_2 B8[35],B9[32],B9[33],!B9[34],B9[35] buffer lc_trk_g2_6 input_2_4 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input_2_6 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_0/in_0 !B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_1/in_3 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_2/in_0 !B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_3/in_3 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_4/in_0 !B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_5/in_3 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_6/in_0 !B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_7/in_3 B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_7 input_2_1 B6[35],B7[32],B7[33],!B7[34],B7[35] buffer lc_trk_g2_7 input_2_3 B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input_2_5 B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input_2_7 !B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_0/in_3 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_1/in_0 !B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_2/in_3 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_3/in_0 !B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_4/in_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_5/in_0 !B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_6/in_3 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_7/in_0 !B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_0 input_2_1 !B6[35],B7[32],B7[33],B7[34],!B7[35] buffer lc_trk_g3_0 input_2_3 !B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input_2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input_2_7 B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_0/in_1 !B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_0/in_3 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_1/in_0 B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_2/in_1 !B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_2/in_3 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_3/in_0 B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_4/in_1 !B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_4/in_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_5/in_0 B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_6/in_1 !B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_6/in_3 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_7/in_0 !B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_1 input_2_0 !B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_1 input_2_2 !B8[35],B9[32],B9[33],B9[34],!B9[35] buffer lc_trk_g3_1 input_2_4 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input_2_6 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_0/in_0 B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_1/in_1 !B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_1/in_3 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_2/in_0 B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_3/in_1 !B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_3/in_3 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_4/in_0 B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_5/in_1 !B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_5/in_3 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_6/in_0 B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/clk B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/in_1 !B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/in_3 !B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_2 input_2_1 !B6[35],B7[32],B7[33],B7[34],B7[35] buffer lc_trk_g3_2 input_2_3 !B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input_2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input_2_7 B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_0/in_1 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_0/in_3 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_1/in_0 B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_2/in_1 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_2/in_3 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_3/in_0 B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_4/in_1 !B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_4/in_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_5/in_0 B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_6/in_1 !B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_6/in_3 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_7/in_0 !B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_3 input_2_0 !B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_3 input_2_2 !B8[35],B9[32],B9[33],B9[34],B9[35] buffer lc_trk_g3_3 input_2_4 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input_2_6 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_0/in_0 B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_1/in_1 !B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_1/in_3 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_2/in_0 B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_3/in_1 !B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_3/in_3 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_4/in_0 B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_5/in_1 !B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_5/in_3 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_6/in_0 B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/cen B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/in_1 !B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/in_3 B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_4 input_2_1 B6[35],B7[32],B7[33],B7[34],!B7[35] buffer lc_trk_g3_4 input_2_3 B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input_2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input_2_7 B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_0/in_3 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_1/in_0 B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_2/in_3 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_3/in_0 B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_4/in_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_5/in_0 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_6/in_3 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_5 input_2_0 B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_5 input_2_2 B8[35],B9[32],B9[33],B9[34],!B9[35] buffer lc_trk_g3_5 input_2_4 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input_2_6 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_0/in_0 B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_1/in_3 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_2/in_0 B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_3/in_3 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_4/in_0 B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_5/in_3 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_6/in_0 B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/in_3 B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/s_r B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_6 input_2_1 B6[35],B7[32],B7[33],B7[34],B7[35] buffer lc_trk_g3_6 input_2_3 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input_2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input_2_7 B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_7 input_2_0 B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_7 input_2_2 B8[35],B9[32],B9[33],B9[34],B9[35] buffer lc_trk_g3_7 input_2_4 B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input_2_6 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 !B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 B10[2] buffer sp12_h_l_17 sp4_h_r_21 !B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 B14[2] buffer sp12_h_l_21 sp4_h_l_10 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_r_14 B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_l_2 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_l_1 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 B3[1] buffer sp12_h_r_10 sp4_h_l_4 !B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_l_7 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 B6[2] buffer sp12_h_r_14 sp4_h_r_19 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 !B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 B8[2] buffer sp12_h_r_16 sp4_h_l_9 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 B12[19] buffer sp12_h_r_2 sp4_h_r_13 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_l_11 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_l_5 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_t_1 !B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 B4[19] buffer sp12_v_b_11 sp4_v_b_17 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 !B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 !B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 B8[19] buffer sp12_v_b_19 sp4_v_b_21 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 B11[19] buffer sp12_v_b_21 sp4_v_b_22 !B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 B10[19] buffer sp12_v_b_23 sp4_v_b_23 B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 B2[19] buffer sp12_v_b_7 sp4_v_b_15 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_8 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_8 lc_trk_g3_0 B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 B0[19] buffer sp12_v_t_0 sp4_v_b_13 B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 !B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 B7[19] buffer sp12_v_t_10 sp4_v_b_18 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 B6[19] buffer sp12_v_t_12 sp4_v_b_19 !B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 B9[19] buffer sp12_v_t_14 sp4_v_t_9 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_t_2 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_t_2 lc_trk_g3_5 B3[19] buffer sp12_v_t_2 sp4_v_t_3 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_t_6 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_t_6 lc_trk_g3_1 B5[19] buffer sp12_v_t_6 sp4_v_t_5 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 !B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 !B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_l_24 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_l_24 lc_trk_g3_5 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_34 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_34 lc_trk_g3_7 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_l_4 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_l_4 lc_trk_g1_1 B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_r_14 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_r_14 lc_trk_g1_6 B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 !B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 !B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_r_38 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_r_38 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_r_39 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_r_39 lc_trk_g3_7 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_r_41 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_r_41 lc_trk_g3_1 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 !B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 !B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 !B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 !B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 !B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 !B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 !B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 !B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 !B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 !B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 !B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 !B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 !B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 !B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 !B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 !B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 !B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 !B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 !B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 !B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 !B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 !B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 !B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 !B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 !B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 !B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 !B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 !B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 !B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 !B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 !B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 !B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 !B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 !B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 !B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 !B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 !B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 !B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 !B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 !B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_b_15 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_b_15 lc_trk_g1_7 B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 !B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_b_18 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_b_18 lc_trk_g1_2 !B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_b_21 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_b_21 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_24 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_24 lc_trk_g3_0 B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 !B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_36 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_36 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_b_42 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_b_42 lc_trk_g3_2 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 !B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 !B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_t_12 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_t_12 lc_trk_g3_1 B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_t_16 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_t_16 lc_trk_g3_5 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_17 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_17 lc_trk_g3_4 B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_t_28 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_t_28 lc_trk_g3_1 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_t_29 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_t_29 lc_trk_g3_0 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_t_3 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_t_3 lc_trk_g1_6 !B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_t_32 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_t_32 lc_trk_g3_5 !B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 !B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_t_5 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_t_5 lc_trk_g1_0 !B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_t_9 lc_trk_g0_4 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_t_9 lc_trk_g1_4 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 !B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 !B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer top_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer top_op_1 lc_trk_g1_1 !B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 !B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 !B0[21],B0[22],!B0[23],B0[24],B1[21] buffer top_op_3 lc_trk_g0_3 !B4[21],B4[22],!B4[23],B4[24],B5[21] buffer top_op_3 lc_trk_g1_3 !B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer top_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer top_op_5 lc_trk_g1_5 !B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 !B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 !B2[21],B2[22],!B2[23],B2[24],B3[21] buffer top_op_7 lc_trk_g0_7 !B6[21],B6[22],!B6[23],B6[24],B7[21] buffer top_op_7 lc_trk_g1_7 !B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer wire_logic_cluster/carry_in_mux/cout wire_logic_cluster/lc_0/in_3 !B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer wire_logic_cluster/lc_0/cout wire_logic_cluster/lc_1/in_3 B2[50] buffer wire_logic_cluster/lc_0/lout input_2_1 B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer wire_logic_cluster/lc_0/out lc_trk_g0_0 B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer wire_logic_cluster/lc_0/out lc_trk_g1_0 B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer wire_logic_cluster/lc_0/out lc_trk_g2_0 B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer wire_logic_cluster/lc_0/out lc_trk_g3_0 B0[47] buffer wire_logic_cluster/lc_0/out sp12_h_r_8 B0[51] buffer wire_logic_cluster/lc_0/out sp12_v_b_0 B0[52] buffer wire_logic_cluster/lc_0/out sp12_v_b_16 B1[47] buffer wire_logic_cluster/lc_0/out sp4_h_l_21 B0[46] buffer wire_logic_cluster/lc_0/out sp4_h_l_5 B1[46] buffer wire_logic_cluster/lc_0/out sp4_h_r_0 B1[52] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_1 B0[53] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_17 B1[53] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_33 B0[48] buffer wire_logic_cluster/lc_0/out sp4_v_b_0 B1[51] buffer wire_logic_cluster/lc_0/out sp4_v_t_21 B1[48] buffer wire_logic_cluster/lc_0/out sp4_v_t_5 !B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer wire_logic_cluster/lc_1/cout wire_logic_cluster/lc_2/in_3 B4[50] buffer wire_logic_cluster/lc_1/lout input_2_2 !B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer wire_logic_cluster/lc_1/out lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer wire_logic_cluster/lc_1/out lc_trk_g1_1 !B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer wire_logic_cluster/lc_1/out lc_trk_g2_1 !B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer wire_logic_cluster/lc_1/out lc_trk_g3_1 B2[47] buffer wire_logic_cluster/lc_1/out sp12_h_r_10 B2[52] buffer wire_logic_cluster/lc_1/out sp12_v_b_18 B2[51] buffer wire_logic_cluster/lc_1/out sp12_v_t_1 B2[46] buffer wire_logic_cluster/lc_1/out sp4_h_l_7 B3[46] buffer wire_logic_cluster/lc_1/out sp4_h_r_2 B3[47] buffer wire_logic_cluster/lc_1/out sp4_h_r_34 B2[53] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_19 B3[52] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_3 B3[53] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_35 B3[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_18 B2[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_2 B3[51] buffer wire_logic_cluster/lc_1/out sp4_v_t_23 !B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer wire_logic_cluster/lc_2/cout wire_logic_cluster/lc_3/in_3 B6[50] buffer wire_logic_cluster/lc_2/lout input_2_3 B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer wire_logic_cluster/lc_2/out lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer wire_logic_cluster/lc_2/out lc_trk_g1_2 B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer wire_logic_cluster/lc_2/out lc_trk_g2_2 B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer wire_logic_cluster/lc_2/out lc_trk_g3_2 B4[47] buffer wire_logic_cluster/lc_2/out sp12_h_r_12 B4[52] buffer wire_logic_cluster/lc_2/out sp12_v_b_20 B4[51] buffer wire_logic_cluster/lc_2/out sp12_v_t_3 B4[46] buffer wire_logic_cluster/lc_2/out sp4_h_l_9 B5[47] buffer wire_logic_cluster/lc_2/out sp4_h_r_36 B5[46] buffer wire_logic_cluster/lc_2/out sp4_h_r_4 B4[53] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_21 B5[53] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_37 B5[52] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_5 B5[51] buffer wire_logic_cluster/lc_2/out sp4_v_b_36 B4[48] buffer wire_logic_cluster/lc_2/out sp4_v_b_4 B5[48] buffer wire_logic_cluster/lc_2/out sp4_v_t_9 !B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer wire_logic_cluster/lc_3/cout wire_logic_cluster/lc_4/in_3 B8[50] buffer wire_logic_cluster/lc_3/lout input_2_4 B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer wire_logic_cluster/lc_3/out lc_trk_g0_3 B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer wire_logic_cluster/lc_3/out lc_trk_g1_3 B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer wire_logic_cluster/lc_3/out lc_trk_g2_3 B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer wire_logic_cluster/lc_3/out lc_trk_g3_3 B6[47] buffer wire_logic_cluster/lc_3/out sp12_h_r_14 B6[51] buffer wire_logic_cluster/lc_3/out sp12_v_b_6 B6[52] buffer wire_logic_cluster/lc_3/out sp12_v_t_21 B6[46] buffer wire_logic_cluster/lc_3/out sp4_h_l_11 B7[47] buffer wire_logic_cluster/lc_3/out sp4_h_r_38 B7[46] buffer wire_logic_cluster/lc_3/out sp4_h_r_6 B6[53] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_23 B7[53] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_39 B7[52] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_7 B7[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_22 B7[51] buffer wire_logic_cluster/lc_3/out sp4_v_b_38 B6[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_6 !B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer wire_logic_cluster/lc_4/cout wire_logic_cluster/lc_5/in_3 B10[50] buffer wire_logic_cluster/lc_4/lout input_2_5 B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer wire_logic_cluster/lc_4/out lc_trk_g0_4 B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer wire_logic_cluster/lc_4/out lc_trk_g1_4 B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer wire_logic_cluster/lc_4/out lc_trk_g2_4 B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer wire_logic_cluster/lc_4/out lc_trk_g3_4 B8[47] buffer wire_logic_cluster/lc_4/out sp12_h_r_0 B8[48] buffer wire_logic_cluster/lc_4/out sp12_h_r_16 B8[52] buffer wire_logic_cluster/lc_4/out sp12_v_b_8 B8[46] buffer wire_logic_cluster/lc_4/out sp4_h_r_24 B9[47] buffer wire_logic_cluster/lc_4/out sp4_h_r_40 B9[46] buffer wire_logic_cluster/lc_4/out sp4_h_r_8 B8[53] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_25 B9[53] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_41 B9[52] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_9 B9[51] buffer wire_logic_cluster/lc_4/out sp4_v_b_24 B9[48] buffer wire_logic_cluster/lc_4/out sp4_v_b_8 B8[51] buffer wire_logic_cluster/lc_4/out sp4_v_t_29 !B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer wire_logic_cluster/lc_5/cout wire_logic_cluster/lc_6/in_3 B12[50] buffer wire_logic_cluster/lc_5/lout input_2_6 !B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer wire_logic_cluster/lc_5/out lc_trk_g0_5 !B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer wire_logic_cluster/lc_5/out lc_trk_g1_5 !B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer wire_logic_cluster/lc_5/out lc_trk_g2_5 !B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer wire_logic_cluster/lc_5/out lc_trk_g3_5 B10[48] buffer wire_logic_cluster/lc_5/out sp12_h_l_17 B10[47] buffer wire_logic_cluster/lc_5/out sp12_h_r_2 B10[52] buffer wire_logic_cluster/lc_5/out sp12_v_t_9 B10[46] buffer wire_logic_cluster/lc_5/out sp4_h_l_15 B11[46] buffer wire_logic_cluster/lc_5/out sp4_h_r_10 B11[47] buffer wire_logic_cluster/lc_5/out sp4_h_r_42 B11[52] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_11 B10[53] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_27 B11[53] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_43 B11[48] buffer wire_logic_cluster/lc_5/out sp4_v_b_10 B11[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_26 B10[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_42 !B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer wire_logic_cluster/lc_6/cout wire_logic_cluster/lc_7/in_3 B14[50] buffer wire_logic_cluster/lc_6/lout input_2_7 B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer wire_logic_cluster/lc_6/out lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer wire_logic_cluster/lc_6/out lc_trk_g1_6 B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer wire_logic_cluster/lc_6/out lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer wire_logic_cluster/lc_6/out lc_trk_g3_6 B12[47] buffer wire_logic_cluster/lc_6/out sp12_h_l_3 B12[48] buffer wire_logic_cluster/lc_6/out sp12_h_r_20 B12[52] buffer wire_logic_cluster/lc_6/out sp12_v_b_12 B13[46] buffer wire_logic_cluster/lc_6/out sp4_h_l_1 B12[46] buffer wire_logic_cluster/lc_6/out sp4_h_l_17 B13[47] buffer wire_logic_cluster/lc_6/out sp4_h_r_44 B13[52] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_13 B12[53] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_29 B13[53] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_45 B13[48] buffer wire_logic_cluster/lc_6/out sp4_v_t_1 B13[51] buffer wire_logic_cluster/lc_6/out sp4_v_t_17 B12[51] buffer wire_logic_cluster/lc_6/out sp4_v_t_33 B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer wire_logic_cluster/lc_7/out lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer wire_logic_cluster/lc_7/out lc_trk_g1_7 B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer wire_logic_cluster/lc_7/out lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer wire_logic_cluster/lc_7/out lc_trk_g3_7 B14[48] buffer wire_logic_cluster/lc_7/out sp12_h_l_21 B14[47] buffer wire_logic_cluster/lc_7/out sp12_h_l_5 B14[52] buffer wire_logic_cluster/lc_7/out sp12_v_b_14 B15[46] buffer wire_logic_cluster/lc_7/out sp4_h_r_14 B14[46] buffer wire_logic_cluster/lc_7/out sp4_h_r_30 B15[47] buffer wire_logic_cluster/lc_7/out sp4_h_r_46 B15[52] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_15 B14[53] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_31 B15[53] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_47 B15[51] buffer wire_logic_cluster/lc_7/out sp4_v_b_30 B14[51] buffer wire_logic_cluster/lc_7/out sp4_v_b_46 B15[48] buffer wire_logic_cluster/lc_7/out sp4_v_t_3 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 !B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 !B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 !B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 !B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 !B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 !B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 !B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 !B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 !B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 !B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 !B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 !B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 !B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 !B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 !B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 !B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 !B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 !B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 !B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 !B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 !B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 !B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 !B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 !B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 !B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 !B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 !B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 !B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 !B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 !B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 !B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 !B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 !B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 !B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 !B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 !B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 !B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 !B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 !B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 !B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 !B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 !B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 !B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 !B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 !B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 !B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 !B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 !B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 !B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 !B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 !B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 !B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 !B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 !B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 !B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 !B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 !B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 !B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 !B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 !B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 !B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 !B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 !B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 !B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 !B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 !B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 !B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 !B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 !B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 !B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 !B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 !B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 !B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 !B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 !B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 !B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 !B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 !B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 !B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 !B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 !B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 !B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 !B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 !B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 !B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 !B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 !B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 !B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 !B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 !B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 !B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 !B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 !B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 !B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 !B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 !B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 !B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 !B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 !B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 !B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 !B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 !B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 !B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 !B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 !B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 !B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 !B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 !B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 !B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 !B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 !B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 !B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 !B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 !B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 !B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 !B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 !B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 !B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 !B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 !B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 !B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 !B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 !B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 !B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 !B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 !B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 !B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 !B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 !B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 !B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 !B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 !B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 !B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 !B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 !B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 !B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 !B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 !B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 !B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 !B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 !B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 !B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 !B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 !B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 !B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 !B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 !B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 !B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ database_ramb_txt = """ B0[1] ColBufCtrl 1k_glb_netwk_0 B1[2] ColBufCtrl 1k_glb_netwk_1 B5[2] ColBufCtrl 1k_glb_netwk_2 B7[2] ColBufCtrl 1k_glb_netwk_3 B9[2] ColBufCtrl 1k_glb_netwk_4 B11[2] ColBufCtrl 1k_glb_netwk_5 B13[2] ColBufCtrl 1k_glb_netwk_6 B15[2] ColBufCtrl 1k_glb_netwk_7 B0[0] NegClk B1[7] RamConfig PowerUp B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 !B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 !B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 !B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 !B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 !B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 !B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 !B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 !B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 !B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 !B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 !B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 !B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 !B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 !B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 !B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 !B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 !B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK !B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/WE !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK !B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/WCLKE B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK !B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK !B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE !B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 !B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 !B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 !B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/WCLKE !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 !B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_0 input2_0 !B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_0 input2_2 !B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK !B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_1 !B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_3 !B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_5 !B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_7 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 !B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_1 input2_1 !B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_0 !B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_2 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_4 !B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_6 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_2 input2_0 !B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_2 input2_2 !B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_1 !B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_3 !B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_5 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_7 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE !B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_1 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_3 !B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_5 !B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_7 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 !B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_3 input2_1 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_0 !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_2 !B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_4 !B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_6 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_0 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_2 !B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_4 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_6 B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_4 input2_0 B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_4 input2_2 B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_1 B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_3 B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_5 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_7 !B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_1 !B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_3 !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_5 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_7 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_5 input2_1 B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_0 B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_2 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_4 B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_6 !B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_0 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_2 !B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_4 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_6 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_6 input2_0 B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_6 input2_2 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_1 B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_3 B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_5 B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_7 !B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_1 !B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_3 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_5 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_7 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_7 input2_1 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_0 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_2 B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_4 B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_6 !B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_0 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_2 !B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_4 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_6 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 !B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_0 input2_1 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_0 !B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_2 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_4 !B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_6 B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_0 B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_2 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_4 B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_6 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_1 input2_0 !B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_1 input2_2 !B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_1 !B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_3 !B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_5 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_7 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_1 B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_3 B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_5 B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_7 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 !B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_2 input2_1 !B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_0 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_2 !B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_4 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_6 B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_0 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_2 B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_4 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_6 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_3 input2_0 !B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_3 input2_2 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_1 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_3 !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_5 !B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_7 !B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_1 B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_3 B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_5 B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_7 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_4 input2_1 B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_0 B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_2 B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_4 B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_6 B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_0 B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_2 B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_4 B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_6 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_5 input2_0 B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_5 input2_2 B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_1 B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_3 B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_5 B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_7 B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_1 B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_3 B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_5 B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_7 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_6 input2_1 B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_0 B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_2 B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_4 B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_6 B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_0 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_2 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_4 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_6 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_7 input2_0 B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_7 input2_2 B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_1 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_3 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_5 B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_7 B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_1 B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_3 B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_5 B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_7 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_0 input2_0 !B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_0 input2_2 !B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_1 !B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_3 !B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_5 !B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_7 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK !B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_1 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_3 !B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_5 !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_7 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_1 input2_1 !B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_0 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_2 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_4 !B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_6 !B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_0 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_2 !B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_4 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_6 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 !B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_2 input2_0 !B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_2 input2_2 !B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_1 !B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_3 !B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_5 !B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_7 B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE !B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_1 !B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_3 !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_5 !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_7 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 !B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_3 input2_1 !B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_0 !B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_2 !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_4 !B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_6 !B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_0 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_2 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_4 !B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_6 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_4 input2_0 B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_4 input2_2 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_1 B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_3 B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_5 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_7 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_1 !B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_3 !B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_5 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_7 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_5 input2_1 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_0 B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_2 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_4 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_6 !B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_0 !B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_2 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_4 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_6 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_6 input2_0 B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_6 input2_2 B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_1 B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_3 B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_5 B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_7 !B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_1 !B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_3 !B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_5 !B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_7 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_7 input2_1 B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_0 B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_2 B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_4 B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_6 !B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_0 !B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_2 !B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_4 !B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_6 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 !B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_0 input2_1 !B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_0 !B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_2 !B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_4 !B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_6 B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_0 B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_2 B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_4 B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_6 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_1 input2_0 !B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_1 input2_2 !B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_1 !B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_3 !B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_5 !B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_7 B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_1 B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_3 B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_5 B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_7 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_2 input2_1 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_0 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_2 !B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_4 !B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_6 B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_0 B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_2 B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_4 B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_6 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_3 input2_0 !B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_3 input2_2 !B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_1 !B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_3 !B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_5 !B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_7 B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_1 B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_3 B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_5 B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_7 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_4 input2_1 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_0 B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_2 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_4 B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_6 B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_0 B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_2 B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_4 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_6 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_5 input2_0 B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_5 input2_2 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_1 B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_3 B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_5 B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_7 B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_1 B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_3 B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_5 B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_7 B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_6 input2_1 B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_0 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_2 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_4 B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_6 B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_0 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_2 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_4 B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_6 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_7 input2_0 B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_7 input2_2 B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_1 B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_3 B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_5 B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_7 B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_1 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_3 B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_5 B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_7 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 B12[19] buffer sp12_h_l_1 sp4_h_r_13 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 !B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 !B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 B8[2] buffer sp12_h_l_15 sp4_h_l_9 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 B10[2] buffer sp12_h_l_17 sp4_h_r_21 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_r_15 !B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 B3[1] buffer sp12_h_l_9 sp4_h_r_17 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_l_1 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_r_18 !B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 B6[2] buffer sp12_h_r_14 sp4_h_l_6 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_l_11 !B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 B14[2] buffer sp12_h_r_22 sp4_h_r_23 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_r_16 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_b_12 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 !B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 B7[19] buffer sp12_v_b_13 sp4_v_t_7 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 !B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 B8[19] buffer sp12_v_b_19 sp4_v_t_8 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 B0[19] buffer sp12_v_b_3 sp4_v_b_13 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 B3[19] buffer sp12_v_b_5 sp4_v_b_14 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 B5[19] buffer sp12_v_b_9 sp4_v_b_16 B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 !B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 B6[19] buffer sp12_v_t_12 sp4_v_t_6 !B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 B9[19] buffer sp12_v_t_14 sp4_v_b_20 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 B11[19] buffer sp12_v_t_18 sp4_v_t_11 !B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 B10[19] buffer sp12_v_t_20 sp4_v_b_23 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 B2[19] buffer sp12_v_t_4 sp4_v_t_2 B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 !B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 B4[19] buffer sp12_v_t_8 sp4_v_t_4 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 !B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 !B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 !B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4 B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 !B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 !B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 !B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 !B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 !B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 !B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 !B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 !B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 !B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 !B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 !B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 !B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 !B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 !B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 !B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 !B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 !B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 !B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 !B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 !B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 !B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 !B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 !B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 !B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 !B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 !B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 !B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 !B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 !B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 !B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 !B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 !B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 !B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 !B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 !B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 !B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 !B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 !B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 !B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 !B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 !B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 !B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 !B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 !B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 !B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 !B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 !B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 !B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 !B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 !B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 !B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 !B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 B0[37] buffer wire_bram/ram/RDATA_0 sp12_h_r_8 B0[39] buffer wire_bram/ram/RDATA_0 sp12_v_b_0 B1[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_16 B1[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_0 B1[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_16 B0[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_32 B1[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_1 B0[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_17 B0[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_33 B1[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_0 B1[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_16 B0[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_32 B2[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_9 B3[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_18 B2[39] buffer wire_bram/ram/RDATA_1 sp12_v_t_1 B3[37] buffer wire_bram/ram/RDATA_1 sp4_h_r_18 B3[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_34 B2[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_19 B3[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_2 B2[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_34 B3[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_7 B4[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_12 B5[40] buffer wire_bram/ram/RDATA_2 sp12_v_b_20 B4[39] buffer wire_bram/ram/RDATA_2 sp12_v_b_4 B5[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_9 B4[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_36 B5[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_4 B4[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_21 B4[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_37 B5[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_5 B5[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_20 B5[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_4 B4[38] buffer wire_bram/ram/RDATA_2 sp4_v_t_25 B6[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_14 B7[40] buffer wire_bram/ram/RDATA_3 sp12_v_b_22 B6[39] buffer wire_bram/ram/RDATA_3 sp12_v_t_5 B7[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_11 B6[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_27 B7[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_6 B6[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_23 B6[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_39 B7[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_7 B7[38] buffer wire_bram/ram/RDATA_3 sp4_v_b_6 B7[39] buffer wire_bram/ram/RDATA_3 sp4_v_t_11 B6[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_27 B9[38] buffer wire_bram/ram/RDATA_4 sp12_h_l_15 B8[37] buffer wire_bram/ram/RDATA_4 sp12_h_r_0 B9[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_24 B8[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_40 B9[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_9 B8[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_40 B9[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_8 B8[38] buffer wire_bram/ram/RDATA_4 sp4_v_t_13 B10[37] buffer wire_bram/ram/RDATA_5 sp12_h_l_1 B11[38] buffer wire_bram/ram/RDATA_5 sp12_h_l_17 B11[40] buffer wire_bram/ram/RDATA_5 sp12_v_b_10 B11[37] buffer wire_bram/ram/RDATA_5 sp4_h_l_15 B11[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_10 B10[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_11 B10[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_10 B10[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_15 B10[39] buffer wire_bram/ram/RDATA_5 sp4_v_t_31 B12[37] buffer wire_bram/ram/RDATA_6 sp12_h_l_3 B13[38] buffer wire_bram/ram/RDATA_6 sp12_h_r_20 B13[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_11 B13[36] buffer wire_bram/ram/RDATA_6 sp4_h_l_1 B13[37] buffer wire_bram/ram/RDATA_6 sp4_h_r_28 B12[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_44 B13[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_13 B12[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_29 B12[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_45 B13[39] buffer wire_bram/ram/RDATA_6 sp4_v_b_12 B12[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_28 B12[39] buffer wire_bram/ram/RDATA_6 sp4_v_b_44 B14[37] buffer wire_bram/ram/RDATA_7 sp12_h_l_5 B15[38] buffer wire_bram/ram/RDATA_7 sp12_h_r_22 B15[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_14 B15[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_19 B15[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_3 B14[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_15 B14[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_47 B15[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_14 B14[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_46 B14[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_19 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 !B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 !B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 !B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 !B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 !B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 !B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 !B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 !B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 !B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 !B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 !B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 !B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 !B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 !B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 !B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 !B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 !B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 !B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 !B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 !B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 !B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 !B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 !B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 !B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 !B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 !B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 !B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 !B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 !B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 !B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 !B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 !B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 !B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 !B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 !B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 !B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 !B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 !B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 !B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 !B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 !B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 !B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 !B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 !B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 !B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 !B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 !B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 !B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 !B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 !B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 !B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 !B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 !B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 !B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 !B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 !B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 !B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 !B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 !B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 !B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 !B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 !B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 !B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 !B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 !B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 !B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 !B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 !B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 !B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 !B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 !B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 !B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 !B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 !B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 !B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 !B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 !B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 !B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 !B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 !B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 !B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 !B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 !B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 !B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 !B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 !B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 !B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 !B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 !B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 !B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 !B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 !B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 !B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 !B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 !B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 !B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 !B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 !B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 !B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 !B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 !B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 !B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 !B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 !B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 !B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 !B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 !B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 !B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 !B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 !B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 !B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 !B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 !B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 !B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 !B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 !B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 !B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 !B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 !B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 !B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 !B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 !B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 !B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 !B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 !B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 !B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 !B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 !B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 !B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 !B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 !B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 !B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 !B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 !B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 !B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 !B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 !B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 !B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 !B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 !B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 !B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 !B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 !B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 !B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 !B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 !B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 !B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 !B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ database_ramt_txt = """ B0[0] NegClk B5[7] RamCascade CBIT_4 B4[7] RamCascade CBIT_5 B7[7] RamCascade CBIT_6 B6[7] RamCascade CBIT_7 B1[7] RamConfig CBIT_0 B0[7] RamConfig CBIT_1 B3[7] RamConfig CBIT_2 B2[7] RamConfig CBIT_3 B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 !B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 !B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 !B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 !B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 !B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 !B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 !B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 !B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 !B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 !B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK !B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/RE !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK !B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/RCLKE B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK !B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK !B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/RCLKE !B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 !B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 !B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 !B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/RCLKE !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 !B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_0 input2_0 !B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_0 input2_2 !B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK !B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_11 !B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_13 !B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_15 !B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_9 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 !B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_1 input2_1 !B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_10 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_12 !B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_14 !B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_8 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_2 input2_0 !B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_2 input2_2 !B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_11 !B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_13 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_15 !B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_9 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_11 !B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_13 !B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_15 !B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_9 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 !B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_3 input2_1 !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_10 !B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_12 !B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_14 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_8 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_10 !B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_12 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_14 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_8 B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_4 input2_0 B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_4 input2_2 B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_11 B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_13 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_15 B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_9 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE !B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_11 !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_13 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_15 !B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_9 B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_5 input2_1 B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_10 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_12 B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_14 B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_8 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_10 !B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_12 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_14 !B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_8 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_6 input2_0 B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_6 input2_2 B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_11 B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_13 B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_15 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_9 !B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_11 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_13 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_15 !B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_9 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_7 input2_1 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_10 B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_12 B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_14 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_8 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_10 !B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_12 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_14 !B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_8 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 !B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_0 input2_1 !B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_10 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_12 !B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_14 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_8 B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_10 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_12 B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_14 B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_8 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_1 input2_0 !B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_1 input2_2 !B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_11 !B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_13 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_15 !B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_9 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_11 B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_13 B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_15 B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_9 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 !B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_2 input2_1 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_10 !B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_12 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_14 !B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_8 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_10 B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_12 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_14 B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_8 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_3 input2_0 !B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_3 input2_2 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_11 !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_13 !B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_15 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_9 !B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_11 B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_13 B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_15 B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_9 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_4 input2_1 B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_10 B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_12 B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_14 B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_8 B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_10 B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_12 B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_14 B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_8 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_5 input2_0 B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_5 input2_2 B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_11 B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_13 B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_15 B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_9 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_11 B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_13 B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_15 B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_9 B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_6 input2_1 B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_10 B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_12 B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_14 B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_8 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_10 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_12 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_14 B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_8 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_7 input2_0 B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_7 input2_2 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_11 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_13 B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_15 B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_9 B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_11 B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_13 B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_15 B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_9 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_0 input2_0 !B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_0 input2_2 !B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_11 !B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_13 !B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_15 !B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_9 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_11 !B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_13 !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_15 !B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_9 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_1 input2_1 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_10 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_12 !B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_14 !B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_8 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_10 !B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_12 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_14 !B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_8 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 !B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_2 input2_0 !B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_2 input2_2 !B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_11 !B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_13 !B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_15 !B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_9 B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE !B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_11 !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_13 !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_15 !B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_9 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 !B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_3 input2_1 !B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_10 !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_12 !B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_14 !B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_8 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_10 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_12 !B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_14 !B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_8 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_4 input2_0 B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_4 input2_2 B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_11 B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_13 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_15 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_9 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE !B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_11 !B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_13 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_15 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_9 B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_5 input2_1 B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_10 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_12 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_14 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_8 !B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_10 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_12 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_14 !B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_8 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_6 input2_0 B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_6 input2_2 B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_11 B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_13 B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_15 B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_9 !B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_11 !B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_13 !B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_15 !B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_9 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_7 input2_1 B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_10 B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_12 B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_14 B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_8 !B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_10 !B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_12 !B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_14 !B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_8 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 !B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_0 input2_1 !B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_10 !B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_12 !B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_14 !B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_8 B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_10 B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_12 B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_14 B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_8 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_1 input2_0 !B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_1 input2_2 !B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_11 !B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_13 !B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_15 !B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_9 B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_11 B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_13 B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_15 B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_9 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_2 input2_1 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_10 !B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_12 !B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_14 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_8 B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_10 B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_12 B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_14 B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_8 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_3 input2_0 !B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_3 input2_2 !B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_11 !B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_13 !B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_15 !B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_9 B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_11 B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_13 B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_15 B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_9 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_4 input2_1 B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_10 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_12 B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_14 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_8 B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_10 B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_12 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_14 B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_8 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_5 input2_0 B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_5 input2_2 B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_11 B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_13 B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_15 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_9 B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_11 B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_13 B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_15 B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_9 B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_6 input2_1 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_10 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_12 B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_14 B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_8 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_10 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_12 B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_14 B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_8 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_7 input2_0 B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_7 input2_2 B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_11 B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_13 B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_15 B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_9 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_11 B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_13 B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_15 B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_9 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 !B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 B6[2] buffer sp12_h_l_13 sp4_h_r_19 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 B14[2] buffer sp12_h_l_21 sp4_h_l_10 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_l_2 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_r_12 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 B3[1] buffer sp12_h_r_10 sp4_h_r_17 !B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_l_7 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 !B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 B8[2] buffer sp12_h_r_16 sp4_h_r_20 !B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 B10[2] buffer sp12_h_r_18 sp4_h_l_8 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 B12[19] buffer sp12_h_r_2 sp4_h_r_13 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_r_22 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_l_5 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_t_1 !B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 B4[19] buffer sp12_v_b_11 sp4_v_b_17 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 !B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 !B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 B9[19] buffer sp12_v_b_17 sp4_v_b_20 B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 B11[19] buffer sp12_v_b_21 sp4_v_b_22 !B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 B10[19] buffer sp12_v_b_23 sp4_v_t_10 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 B3[19] buffer sp12_v_b_5 sp4_v_b_14 B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 B2[19] buffer sp12_v_b_7 sp4_v_t_2 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 B5[19] buffer sp12_v_b_9 sp4_v_b_16 B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 B0[19] buffer sp12_v_t_0 sp4_v_b_13 !B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 B7[19] buffer sp12_v_t_10 sp4_v_t_7 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 B6[19] buffer sp12_v_t_12 sp4_v_b_19 !B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 B8[19] buffer sp12_v_t_16 sp4_v_t_8 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 !B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 !B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 !B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 !B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 !B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 !B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 !B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 !B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 !B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 !B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 !B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 !B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 !B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 !B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 !B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 !B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 !B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 !B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 !B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 !B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 !B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 !B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 !B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 !B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 !B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 !B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 !B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 !B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 !B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 !B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 !B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 !B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 !B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 !B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 !B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 !B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 !B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 !B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 !B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 !B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 !B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 !B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 !B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 !B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 !B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 !B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 !B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 !B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 !B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 !B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 !B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 !B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 !B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 !B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 !B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 !B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 !B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 !B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 !B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 !B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 !B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4 !B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 !B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 B4[37] buffer wire_bram/ram/RDATA_10 sp12_h_r_12 B5[40] buffer wire_bram/ram/RDATA_10 sp12_v_t_19 B4[39] buffer wire_bram/ram/RDATA_10 sp12_v_t_3 B5[37] buffer wire_bram/ram/RDATA_10 sp4_h_r_20 B4[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_36 B5[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_4 B4[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_21 B4[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_37 B5[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_5 B5[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_20 B5[38] buffer wire_bram/ram/RDATA_10 sp4_v_b_4 B4[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_25 B6[37] buffer wire_bram/ram/RDATA_11 sp12_h_l_13 B6[39] buffer wire_bram/ram/RDATA_11 sp12_v_b_6 B7[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_21 B6[36] buffer wire_bram/ram/RDATA_11 sp4_h_l_27 B7[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_22 B7[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_6 B6[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_23 B6[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_39 B7[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_7 B7[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_22 B6[38] buffer wire_bram/ram/RDATA_11 sp4_v_b_38 B7[38] buffer wire_bram/ram/RDATA_11 sp4_v_b_6 B8[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_0 B9[38] buffer wire_bram/ram/RDATA_12 sp12_h_r_16 B9[40] buffer wire_bram/ram/RDATA_12 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_13 B8[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_29 B9[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_9 B8[39] buffer wire_bram/ram/RDATA_12 sp4_v_b_40 B9[39] buffer wire_bram/ram/RDATA_12 sp4_v_b_8 B8[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_13 B11[38] buffer wire_bram/ram/RDATA_13 sp12_h_r_18 B10[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_2 B11[40] buffer wire_bram/ram/RDATA_13 sp12_v_t_9 B11[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_15 B11[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_10 B10[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_11 B10[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_10 B10[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_26 B10[39] buffer wire_bram/ram/RDATA_13 sp4_v_t_31 B12[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_3 B13[38] buffer wire_bram/ram/RDATA_14 sp12_h_r_20 B13[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_12 B13[37] buffer wire_bram/ram/RDATA_14 sp4_h_l_17 B13[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_12 B12[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_44 B13[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_13 B12[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_29 B12[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_45 B12[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_28 B13[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_1 B12[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_33 B15[38] buffer wire_bram/ram/RDATA_15 sp12_h_l_21 B14[37] buffer wire_bram/ram/RDATA_15 sp12_h_l_5 B15[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_14 B15[36] buffer wire_bram/ram/RDATA_15 sp4_h_l_3 B15[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_30 B14[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_15 B14[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_47 B15[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_14 B14[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_30 B14[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_46 B0[37] buffer wire_bram/ram/RDATA_8 sp12_h_r_8 B0[39] buffer wire_bram/ram/RDATA_8 sp12_v_b_0 B1[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_16 B0[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_21 B1[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_5 B1[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_0 B1[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_1 B0[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_17 B0[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_33 B1[38] buffer wire_bram/ram/RDATA_8 sp4_v_b_0 B1[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_16 B0[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_21 B2[37] buffer wire_bram/ram/RDATA_9 sp12_h_r_10 B2[39] buffer wire_bram/ram/RDATA_9 sp12_v_b_2 B3[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_17 B3[37] buffer wire_bram/ram/RDATA_9 sp4_h_l_7 B3[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_34 B2[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_19 B3[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_2 B2[38] buffer wire_bram/ram/RDATA_9 sp4_v_t_23 B3[39] buffer wire_bram/ram/RDATA_9 sp4_v_t_7 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 !B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 !B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 !B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 !B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 !B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 !B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 !B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 !B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 !B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 !B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 !B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 !B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 !B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 !B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 !B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 !B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 !B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 !B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 !B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 !B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 !B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 !B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 !B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 !B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 !B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 !B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 !B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 !B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 !B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 !B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 !B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 !B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 !B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 !B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 !B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 !B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 !B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 !B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 !B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 !B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 !B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 !B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 !B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 !B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 !B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 !B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 !B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 !B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 !B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 !B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 !B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 !B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 !B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 !B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 !B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 !B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 !B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 !B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 !B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 !B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 !B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 !B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 !B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 !B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 !B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 !B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 !B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 !B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 !B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 !B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 !B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 !B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 !B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 !B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 !B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 !B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 !B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 !B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 !B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 !B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 !B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 !B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 !B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 !B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 !B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 !B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 !B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 !B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 !B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 !B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 !B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 !B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 !B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 !B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 !B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 !B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 !B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 !B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 !B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 !B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 !B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 !B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 !B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 !B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 !B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 !B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 !B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 !B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 !B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 !B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 !B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 !B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 !B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 !B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 !B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 !B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 !B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 !B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 !B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 !B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 !B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 !B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 !B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 !B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 !B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 !B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 !B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 !B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 !B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 !B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 !B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 !B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 !B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 !B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 !B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 !B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 !B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 !B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 !B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 !B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 !B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 !B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 !B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 !B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 !B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 !B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 !B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 !B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ database_ramb_8k_txt = """ B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 B11[7] ColBufCtrl 8k_glb_netwk_2 B10[7] ColBufCtrl 8k_glb_netwk_3 B13[7] ColBufCtrl 8k_glb_netwk_4 B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 B0[0] NegClk B1[7] RamConfig PowerUp B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 !B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 !B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 !B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 !B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 !B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 !B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 !B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 !B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 !B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 !B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 !B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 !B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 !B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/RCLK !B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/RE !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK !B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/RCLKE B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK !B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK !B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/RCLKE !B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 !B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 !B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 !B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/RCLKE B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/RCLKE !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 !B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 !B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK !B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10 !B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_8 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 !B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 !B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 !B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 !B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE !B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 !B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 !B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11 !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 !B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 !B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 !B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 !B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 !B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 !B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 !B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 !B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 !B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 !B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 !B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 !B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 !B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 !B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 !B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 !B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 !B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 !B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 !B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15 B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13 B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8 B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 !B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_10 !B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_12 !B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 !B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK !B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 !B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 !B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10 !B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_12 !B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14 !B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8 B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 !B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10 B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE !B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 !B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 !B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 !B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 !B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 !B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 !B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 !B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 !B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 !B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 !B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13 B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 !B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 !B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 !B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 !B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_14 B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_8 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 !B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 !B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 !B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 !B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12 !B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 !B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14 B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14 B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8 B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15 B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14 B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 B12[19] buffer sp12_h_l_1 sp4_h_r_13 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 !B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 !B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 B8[2] buffer sp12_h_l_15 sp4_h_l_9 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 B10[2] buffer sp12_h_l_17 sp4_h_r_21 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_r_15 !B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 B3[1] buffer sp12_h_l_9 sp4_h_r_17 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_l_1 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_r_18 !B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 B6[2] buffer sp12_h_r_14 sp4_h_l_6 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_l_11 !B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 B14[2] buffer sp12_h_r_22 sp4_h_r_23 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_r_16 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_b_12 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 !B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 B7[19] buffer sp12_v_b_13 sp4_v_t_7 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 !B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 B8[19] buffer sp12_v_b_19 sp4_v_t_8 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 B0[19] buffer sp12_v_b_3 sp4_v_b_13 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 B3[19] buffer sp12_v_b_5 sp4_v_b_14 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 B5[19] buffer sp12_v_b_9 sp4_v_b_16 B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 !B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 B6[19] buffer sp12_v_t_12 sp4_v_t_6 !B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 B9[19] buffer sp12_v_t_14 sp4_v_b_20 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 B11[19] buffer sp12_v_t_18 sp4_v_t_11 !B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 B10[19] buffer sp12_v_t_20 sp4_v_b_23 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 B2[19] buffer sp12_v_t_4 sp4_v_t_2 B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 !B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 B4[19] buffer sp12_v_t_8 sp4_v_t_4 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 !B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 !B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 !B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4 B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 !B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 !B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 !B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 !B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 !B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 !B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 !B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 !B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 !B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 !B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 !B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 !B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 !B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 !B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 !B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 !B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 !B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 !B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 !B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 !B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 !B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 !B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 !B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 !B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 !B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 !B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 !B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 !B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 !B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 !B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 !B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 !B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 !B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 !B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 !B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 !B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 !B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 !B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 !B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 !B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 !B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 !B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 !B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 !B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 !B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 !B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 !B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 !B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 !B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 !B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 !B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 !B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10 B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15 B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40 B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20 B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4 B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9 B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36 B5[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_4 B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21 B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37 B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5 B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20 B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4 B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25 B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17 B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33 B1[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_0 B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16 B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32 B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29 B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 !B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 !B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 !B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 !B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 !B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 !B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 !B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 !B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 !B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 !B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 !B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 !B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 !B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 !B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 !B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 !B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 !B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 !B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 !B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 !B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 !B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 !B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 !B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 !B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 !B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 !B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 !B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 !B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 !B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 !B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 !B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 !B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 !B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 !B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 !B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 !B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 !B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 !B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 !B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 !B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 !B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 !B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 !B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 !B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 !B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 !B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 !B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 !B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 !B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 !B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 !B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 !B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 !B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 !B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 !B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 !B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 !B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 !B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 !B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 !B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 !B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 !B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 !B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 !B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 !B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 !B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 !B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 !B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 !B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 !B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 !B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 !B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 !B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 !B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 !B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 !B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 !B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 !B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 !B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 !B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 !B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 !B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 !B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 !B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 !B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 !B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 !B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 !B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 !B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 !B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 !B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 !B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 !B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 !B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 !B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 !B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 !B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 !B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 !B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 !B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 !B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 !B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 !B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 !B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 !B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 !B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 !B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 !B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 !B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 !B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 !B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 !B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 !B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 !B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 !B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 !B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 !B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 !B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 !B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 !B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 !B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 !B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 !B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 !B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 !B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 !B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 !B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 !B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 !B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 !B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 !B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 !B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 !B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 !B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 !B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 !B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 !B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 !B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 !B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 !B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 !B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 !B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 !B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 !B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 !B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 !B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 !B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 !B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ database_ramt_8k_txt = """ B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 B11[7] ColBufCtrl 8k_glb_netwk_2 B10[7] ColBufCtrl 8k_glb_netwk_3 B13[7] ColBufCtrl 8k_glb_netwk_4 B12[7] ColBufCtrl 8k_glb_netwk_5 B15[7] ColBufCtrl 8k_glb_netwk_6 B14[7] ColBufCtrl 8k_glb_netwk_7 B0[0] NegClk B5[7] RamCascade CBIT_4 B4[7] RamCascade CBIT_5 B7[7] RamCascade CBIT_6 B6[7] RamCascade CBIT_7 B1[7] RamConfig CBIT_0 B0[7] RamConfig CBIT_1 B3[7] RamConfig CBIT_2 B2[7] RamConfig CBIT_3 B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 !B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 !B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 !B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 !B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 !B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 !B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 !B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 !B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 !B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 !B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 !B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 !B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 !B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 !B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 !B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_0 glb2local_3 !B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_bram/ram/WCLK !B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_bram/ram/WE !B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 !B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 !B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 !B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 !B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK !B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_bram/ram/WCLKE B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK !B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK !B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_bram/ram/WCLKE !B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 !B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 !B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 !B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 !B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE !B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 !B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 !B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 !B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 !B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_bram/ram/WCLKE B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_bram/ram/WCLKE !B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 !B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 !B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 !B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 !B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 !B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK !B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 !B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 !B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 !B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 !B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 !B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 !B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 !B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 !B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7 !B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 !B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 !B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 !B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 !B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 !B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 !B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 !B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 !B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 !B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE !B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 !B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 !B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 !B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 !B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 !B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 !B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 !B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 !B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1 !B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 !B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 !B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6 !B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 !B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 !B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_7 B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2 B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4 B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 !B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 !B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 !B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4 !B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6 B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 !B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 !B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 !B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 !B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 !B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 !B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 !B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 !B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 !B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 !B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 !B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 !B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 !B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 !B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5 B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 !B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 !B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 !B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 !B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 !B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 !B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 !B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 !B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 !B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6 !B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_4 B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 !B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 !B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 !B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 !B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 !B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 !B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 !B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 !B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 !B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 !B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 !B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 !B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 !B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 !B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 !B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 !B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0 !B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 !B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 !B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 !B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_5 B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5 B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7 B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 !B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7 B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7 B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6 B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 !B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 !B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 !B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 !B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 !B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 !B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 !B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 !B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4 !B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK !B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 !B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 !B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 !B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 !B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 !B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 !B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 !B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 !B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 !B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 !B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 !B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7 !B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 !B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 !B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 !B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 !B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 !B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 !B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 !B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 !B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE !B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 !B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4 !B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6 !B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 !B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 !B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 !B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 !B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 !B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 !B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5 !B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 !B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7 B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 !B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 !B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 !B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5 !B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_7 B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0 B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_2 B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6 !B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0 !B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2 !B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4 !B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6 B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 !B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1 !B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3 !B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5 !B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7 !B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 !B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 !B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 !B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 !B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 !B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 !B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 !B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7 !B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 !B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 !B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 !B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 !B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 !B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0 !B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_2 !B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4 !B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_6 B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0 B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2 B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4 B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 !B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 !B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 !B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 !B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 !B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 !B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 !B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 !B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 !B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 !B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5 B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_7 !B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 !B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 !B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 !B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 !B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 !B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0 !B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2 !B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4 !B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6 B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0 B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2 B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4 B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6 B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5 B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7 B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4 B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6 B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0 B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2 B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4 B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6 B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0 B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 !B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 !B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 B6[2] buffer sp12_h_l_13 sp4_h_r_19 !B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 !B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 !B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 !B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 B14[2] buffer sp12_h_l_21 sp4_h_l_10 B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 B15[19] buffer sp12_h_l_3 sp4_h_l_3 B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 B14[19] buffer sp12_h_l_5 sp4_h_l_2 !B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 B13[19] buffer sp12_h_r_0 sp4_h_r_12 B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 !B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 B3[1] buffer sp12_h_r_10 sp4_h_r_17 !B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 !B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 !B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 !B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 B4[2] buffer sp12_h_r_12 sp4_h_l_7 !B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 !B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 !B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 B8[2] buffer sp12_h_r_16 sp4_h_r_20 !B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 !B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 !B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 !B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 B10[2] buffer sp12_h_r_18 sp4_h_l_8 B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 B12[19] buffer sp12_h_r_2 sp4_h_r_13 !B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 !B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 B12[2] buffer sp12_h_r_20 sp4_h_r_22 !B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 !B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 !B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 !B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 B0[2] buffer sp12_h_r_8 sp4_h_l_5 B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 B1[19] buffer sp12_v_b_1 sp4_v_t_1 !B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 B4[19] buffer sp12_v_b_11 sp4_v_b_17 !B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 !B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 !B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 !B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 !B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 B9[19] buffer sp12_v_b_17 sp4_v_b_20 B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 !B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 B11[19] buffer sp12_v_b_21 sp4_v_b_22 !B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 B10[19] buffer sp12_v_b_23 sp4_v_t_10 B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 B3[19] buffer sp12_v_b_5 sp4_v_b_14 B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 B2[19] buffer sp12_v_b_7 sp4_v_t_2 !B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 !B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 B5[19] buffer sp12_v_b_9 sp4_v_b_16 B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 B0[19] buffer sp12_v_t_0 sp4_v_b_13 !B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 !B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 B7[19] buffer sp12_v_t_10 sp4_v_t_7 !B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 !B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 B6[19] buffer sp12_v_t_12 sp4_v_b_19 !B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 !B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 B8[19] buffer sp12_v_t_16 sp4_v_t_8 !B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 !B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 !B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 !B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 !B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 !B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 !B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 !B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 !B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 !B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 !B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 !B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 !B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 !B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 !B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 !B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 !B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 !B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 !B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 !B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 !B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 !B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 !B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 !B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 !B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 !B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 !B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 !B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 !B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 !B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 !B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 !B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 !B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 !B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 !B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 !B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 !B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 !B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 !B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 !B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 !B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 !B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 !B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 !B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 !B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 !B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 !B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 !B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 !B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 !B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 !B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 !B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 !B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 !B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 !B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 !B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 !B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 !B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 !B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 !B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 !B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 !B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 !B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 !B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 !B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 !B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 !B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 !B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 !B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 !B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 !B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 !B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 !B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 !B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 !B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 !B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 !B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 !B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 !B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 !B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 !B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 !B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 !B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 !B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 !B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 !B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 !B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 !B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 !B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 !B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 !B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 !B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 !B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 !B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 !B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 !B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 !B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 !B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 !B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 !B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 !B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 !B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 !B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 !B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 !B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 !B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 !B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 !B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 !B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 !B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 !B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 !B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 !B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 !B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 !B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 !B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 !B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 !B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 !B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 !B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 !B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 !B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 !B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 !B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 !B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 !B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0 !B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 !B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 !B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 !B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 !B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4 !B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 !B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46 B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14 B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30 B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46 B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3 B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20 B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12 B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17 B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12 B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44 B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13 B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29 B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45 B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28 B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1 B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33 B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18 B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8 B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40 B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8 B8[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_13 B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13 B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6 B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21 B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27 B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22 B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6 B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23 B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39 B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7 B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22 B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38 B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6 B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12 B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19 B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3 B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20 B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36 B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4 B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21 B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37 B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5 B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20 B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4 B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25 B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23 B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7 B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8 B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 !B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 !B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 !B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 !B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 !B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 !B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 !B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 !B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 !B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 !B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 !B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 !B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 !B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 !B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 !B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 !B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 !B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 !B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 !B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 !B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 !B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 !B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 !B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 !B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 !B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 !B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 !B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 !B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 !B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 !B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 !B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 !B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 !B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 !B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 !B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 !B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 !B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 !B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 !B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 !B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 !B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 !B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 !B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 !B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 !B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 !B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 !B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 !B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 !B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 !B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 !B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 !B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 !B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 !B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 !B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 !B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 !B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 !B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 !B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 !B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 !B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 !B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 !B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 !B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 !B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 !B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 !B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 !B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 !B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 !B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 !B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 !B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 !B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 !B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 !B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 !B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 !B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 !B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 !B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 !B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 !B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 !B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 !B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 !B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 !B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 !B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 !B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 !B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 !B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 !B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 !B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 !B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 !B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 !B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 !B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 !B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 !B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 !B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 !B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 !B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 !B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 !B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 !B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 !B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 !B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 !B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 !B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 !B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 !B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 !B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 !B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 !B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 !B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 !B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 !B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 !B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 !B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 !B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 !B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 !B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 !B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 !B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 !B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 !B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 !B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 !B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 !B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 !B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 !B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 !B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 !B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 !B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 !B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 !B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 !B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 !B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 !B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 !B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 !B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 !B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 !B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 !B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 !B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 !B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 !B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 !B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 !B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 !B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 !B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 !B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 !B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ fpga-icestorm-0~20160913git266e758/icebram/000077500000000000000000000000001276746530600177745ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icebram/.gitignore000066400000000000000000000002061276746530600217620ustar00rootroot00000000000000demo.asc demo.blif demo.pcf demo.v demo.vvp demo_dat0.hex demo_dat1.hex demo_new.asc demo_new.v demo_tb.v icebram icebram.d icebram.o fpga-icestorm-0~20160913git266e758/icebram/Makefile000066400000000000000000000010421276746530600214310ustar00rootroot00000000000000include ../config.mk LDLIBS = -lm -lstdc++ CXXFLAGS = -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include ifeq ($(STATIC),1) LDFLAGS += -static endif all: icebram$(EXE) icebram$(EXE): icebram.o $(CC) -o $@ $(LDFLAGS) $^ $(LDLIBS) test: icebram bash rundemo.sh install: all mkdir -p $(DESTDIR)$(PREFIX)/bin cp icebram $(DESTDIR)$(PREFIX)/bin/icebram uninstall: rm -f $(DESTDIR)$(PREFIX)/bin/icebram clean: rm -f icebram rm -f icebram.exe rm -f demo.* demo_*.* rm -f *.o *.d -include *.d .PHONY: all test install uninstall clean fpga-icestorm-0~20160913git266e758/icebram/icebram.cc000066400000000000000000000213731276746530600217130ustar00rootroot00000000000000// // Copyright (C) 2016 Clifford Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. // #include #include #include #include #include #include #include #include #include #include #include #include using std::map; using std::pair; using std::vector; using std::string; using std::ifstream; using std::getline; uint64_t x; uint64_t xorshift64star(void) { x ^= x >> 12; // a x ^= x << 25; // b x ^= x >> 27; // c return x * UINT64_C(2685821657736338717); } void parse_hexfile_line(const char *filename, int linenr, vector> &hexfile, string &line) { vector digits; for (char c : line) { if ('0' <= c && c <= '9') digits.push_back(c - '0'); else if ('a' <= c && c <= 'f') digits.push_back(10 + c - 'a'); else if ('A' <= c && c <= 'F') digits.push_back(10 + c - 'A'); else goto error; } hexfile.push_back(vector(digits.size() * 4)); for (int i = 0; i < int(digits.size()) * 4; i++) if ((digits.at(digits.size() - i/4 -1) & (1 << (i%4))) != 0) hexfile.back().at(i) = true; return; error: fprintf(stderr, "Can't parse line %d of %s: %s\n", linenr, filename, line.c_str()); exit(1); } void help(const char *cmd) { printf("\n"); printf("Usage: %s [options] \n", cmd); printf(" %s [options] -g \n", cmd); printf("\n"); printf("Replace BRAM initialization data in a .asc file. This can be used\n"); printf("for example to replace firmware images without re-running synthesis\n"); printf("and place&route.\n"); printf("\n"); printf(" -g\n"); printf(" generate a hex file with random contents.\n"); printf(" use this to generate the hex file used during synthesis, then\n"); printf(" use the same file as later.\n"); printf("\n"); printf(" -v\n"); printf(" verbose output\n"); printf("\n"); exit(1); } int main(int argc, char **argv) { bool verbose = false; bool generate = false; int opt; while ((opt = getopt(argc, argv, "vg")) != -1) { switch (opt) { case 'v': verbose = true; break; case 'g': generate = true; break; default: help(argv[0]); } } if (generate) { if (optind+2 != argc) help(argv[0]); int width = atoi(argv[optind]); int depth = atoi(argv[optind+1]); if (width <= 0 || width % 4 != 0) { fprintf(stderr, "Hexfile width (%d bits) is not divisible by 4 or nonpositive!\n", width); exit(1); } if (depth <= 0 || depth % 256 != 0) { fprintf(stderr, "Hexfile number of words (%d) is not divisible by 256 or nonpositive!\n", depth); exit(1); } x = uint64_t(getpid()) << 32; x ^= uint64_t(depth) << 16; x ^= uint64_t(width) << 10; xorshift64star(); xorshift64star(); xorshift64star(); struct timeval tv; gettimeofday(&tv, NULL); x ^= uint64_t(tv.tv_sec) << 20; x ^= uint64_t(tv.tv_usec); xorshift64star(); xorshift64star(); xorshift64star(); for (int i = 0; i < depth; i++) { for (int j = 0; j < width / 4; j++) { int digit = xorshift64star() & 15; std::cout << "0123456789abcdef"[digit]; } std::cout << std::endl; } exit(0); } if (optind+2 != argc) help(argv[0]); // ------------------------------------------------------- // Load from_hexfile and to_hexfile const char *from_hexfile_n = argv[optind]; ifstream from_hexfile_f(from_hexfile_n); vector> from_hexfile; const char *to_hexfile_n = argv[optind+1]; ifstream to_hexfile_f(to_hexfile_n); vector> to_hexfile; string line; for (int i = 1; getline(from_hexfile_f, line); i++) parse_hexfile_line(from_hexfile_n, i, from_hexfile, line); for (int i = 1; getline(to_hexfile_f, line); i++) parse_hexfile_line(to_hexfile_n, i, to_hexfile, line); if (from_hexfile.size() != to_hexfile.size()) { fprintf(stderr, "Hexfiles have different number of words! (%d vs. %d)\n", int(from_hexfile.size()), int(to_hexfile.size())); exit(1); } if (from_hexfile.size() % 256 != 0) { fprintf(stderr, "Hexfile number of words (%d) is not divisible by 256!\n", int(from_hexfile.size())); exit(1); } for (size_t i = 1; i < from_hexfile.size(); i++) if (from_hexfile.at(i-1).size() != from_hexfile.at(i).size()) { fprintf(stderr, "Inconsistent word width at line %d of %s!\n", int(i), from_hexfile_n); exit(1); } for (size_t i = 1; i < to_hexfile.size(); i++) { while (to_hexfile.at(i-1).size() > to_hexfile.at(i).size()) to_hexfile.at(i).push_back(false); if (to_hexfile.at(i-1).size() != to_hexfile.at(i).size()) { fprintf(stderr, "Inconsistent word width at line %d of %s!\n", int(i+1), to_hexfile_n); exit(1); } } if (from_hexfile.size() == 0 || from_hexfile.at(0).size() == 0) { fprintf(stderr, "Empty from/to hexfiles!\n"); exit(1); } if (verbose) fprintf(stderr, "Loaded pattern for %d bits wide and %d words deep memory.\n", int(from_hexfile.at(0).size()), int(from_hexfile.size())); // ------------------------------------------------------- // Create bitslices from pattern data map, pair, int>> pattern; for (int i = 0; i < int(from_hexfile.at(0).size()); i++) { vector pattern_from, pattern_to; for (int j = 0; j < int(from_hexfile.size()); j++) { pattern_from.push_back(from_hexfile.at(j).at(i)); pattern_to.push_back(to_hexfile.at(j).at(i)); if (pattern_from.size() == 256) { if (pattern.count(pattern_from)) { fprintf(stderr, "Conflicting from pattern for bit slice from_hexfile[%d:%d][%d]!\n", j, j-255, i); exit(1); } pattern[pattern_from] = std::make_pair(pattern_to, 0); pattern_from.clear(), pattern_to.clear(); } } assert(pattern_from.empty()); assert(pattern_to.empty()); } if (verbose) fprintf(stderr, "Extracted %d bit slices from from/to hexfile data.\n", int(pattern.size())); // ------------------------------------------------------- // Read ascfile from stdin vector ascfile_lines; map>> ascfile_hexdata; for (int i = 1; getline(std::cin, line); i++) { next_asc_stmt: ascfile_lines.push_back(line); if (line.substr(0, 9) == ".ram_data") { auto &hexdata = ascfile_hexdata[line]; for (; getline(std::cin, line); i++) { if (line.substr(0, 1) == ".") goto next_asc_stmt; parse_hexfile_line("stdin", i, hexdata, line); } } } if (verbose) fprintf(stderr, "Found %d initialized bram cells in asc file.\n", int(ascfile_hexdata.size())); // ------------------------------------------------------- // Replace bram data int max_replace_cnt = 0; for (auto &bram_it : ascfile_hexdata) { auto &bram_data = bram_it.second; for (int i = 0; i < 16; i++) { vector from_bitslice; for (int j = 0; j < 256; j++) from_bitslice.push_back(bram_data.at(j / 16).at(16 * (j % 16) + i)); auto p = pattern.find(from_bitslice); if (p != pattern.end()) { auto &to_bitslice = p->second.first; for (int j = 0; j < 256; j++) bram_data.at(j / 16).at(16 * (j % 16) + i) = to_bitslice.at(j); max_replace_cnt = std::max(++p->second.second, max_replace_cnt); } } } int min_replace_cnt = max_replace_cnt; for (auto &it : pattern) min_replace_cnt = std::min(min_replace_cnt, it.second.second); if (min_replace_cnt != max_replace_cnt) { fprintf(stderr, "Found some bitslices up to %d times, others only %d times!\n", max_replace_cnt, min_replace_cnt); exit(1); } if (verbose) fprintf(stderr, "Found and replaced %d instances of the memory.\n", max_replace_cnt); // ------------------------------------------------------- // Write ascfile to stdout for (size_t i = 0; i < ascfile_lines.size(); i++) { auto &line = ascfile_lines.at(i); std::cout << line << std::endl; if (ascfile_hexdata.count(line)) { for (auto &word : ascfile_hexdata.at(line)) { for (int k = word.size()-4; k >= 0; k -= 4) { int digit = (word[k+3] ? 8 : 0) + (word[k+2] ? 4 : 0) + (word[k+1] ? 2 : 0) + (word[k] ? 1 : 0); std::cout << "0123456789abcdef"[digit]; } std::cout << std::endl; } } } return 0; } fpga-icestorm-0~20160913git266e758/icebram/makedemo.py000066400000000000000000000063451276746530600221400ustar00rootroot00000000000000#!/usr/bin/env python3 import numpy as np while True: bram_width = 4 * np.random.randint(1, 9) bram_depth = 256 * np.random.randint(1, 9) numrports = np.random.randint(1, 5) if bram_width * bram_depth * numrports < 16*4096: break with open("demo.v", "wt") as f: print("// bram_width = %d" % bram_width, file=f) print("// bram_depth = %d" % bram_depth, file=f) print("// numrports = %d" % numrports, file=f) print("module demo (", file=f) for i in range(numrports): print(" input [%d:0] raddr%d," % (np.ceil(np.log2(bram_depth))-1, i), file=f) print(" output reg [%d:0] rdata%d," % (bram_width-1, i), file=f) print(" input [%d:0] waddr," % (np.ceil(np.log2(bram_depth))-1), file=f) print(" input [%d:0] wdata," % (bram_width-1), file=f) print(" input wen, clk", file=f) print(");", file=f) print(" reg [%d:0] memory [0:%d];" % (bram_width-1, bram_depth-1), file=f) print(" initial $readmemh(\"demo_dat0.hex\", memory);", file=f) for i in range(numrports): print(" always @(posedge clk) rdata%d <= memory[raddr%d];" % (i, i), file=f) print(" always @(posedge clk) if (wen) memory[waddr] <= wdata;", file=f) print("endmodule", file=f) with open("demo_tb.v", "wt") as f: print("module demo_tb;", file=f) print(" reg clk = 0;", file=f) print(" always #5 clk = ~clk;", file=f) print(" integer i, errcnt = 0;", file=f) print(" reg [%d:0] addr;" % (np.ceil(np.log2(bram_depth))-1), file=f) for i in range(numrports): print(" wire [%d:0] rdata%d;" % (bram_width-1, i), file=f) print(" reg [%d:0] refmem [0:%d];" % (bram_width-1, bram_depth-1), file=f) print(" initial $readmemh(\"demo_dat1.hex\", refmem);", file=f) print(" demo uut (", file=f) for i in range(numrports): print(" .raddr%d(addr+%d'd%d)," % (i, np.ceil(np.log2(bram_depth)), i), file=f) print(" .rdata%d(rdata%d)," % (i, i), file=f) print(" .wen(1'b0),", file=f) print(" .clk(clk)", file=f) print(" );", file=f) print(" initial begin", file=f) print(" repeat (10) @(negedge clk);", file=f) print(" for (i = 0; i < %d; i = i + %d) begin" % (bram_depth, numrports), file=f) print(" addr <= i;", file=f) print(" @(posedge clk);", file=f) print(" @(negedge clk);", file=f) for i in range(numrports): print(" if (i+%d < %d && refmem[i+%d] !== rdata%d) begin errcnt = errcnt+1; " % (i, bram_depth, i, i) + "$display(\"ERROR @%%x: %%0%dx != %%0%dx\", i+%d, refmem[i+%d], rdata%d); end" % (bram_width/4, bram_width/4, i, i, i), file=f) print(" end", file=f) print(" if (errcnt == 0)", file=f) print(" $display(\"All tests OK.\");", file=f) print(" else", file=f) print(" $display(\"Found %1d ERROR(s).\", errcnt);", file=f) print(" $finish;", file=f) print(" end", file=f) print("endmodule", file=f) with open("demo_dat0.hex", "wt") as f: for i in range(bram_depth): print("%0*x" % (bram_width//4, np.random.randint(1 << bram_width)), file=f) with open("demo_dat1.hex", "wt") as f: for i in range(bram_depth): print("%0*x" % (bram_width//4, np.random.randint(1 << bram_width)), file=f) fpga-icestorm-0~20160913git266e758/icebram/rundemo.sh000066400000000000000000000005641276746530600220060ustar00rootroot00000000000000#!/bin/bash set -ex python3 makedemo.py yosys -p 'synth_ice40 -blif demo.blif' demo.v arachne-pnr -d 8k -w demo.pcf -o demo.asc demo.blif ./icebram -v demo_dat0.hex demo_dat1.hex < demo.asc > demo_new.asc icebox_vlog -n demo -p demo.pcf -c demo_new.asc > demo_new.v iverilog -o demo.vvp demo_tb.v demo_new.v $( yosys-config --datdir/ice40/cells_sim.v ) vvp -N demo.vvp fpga-icestorm-0~20160913git266e758/icefuzz/000077500000000000000000000000001276746530600200515ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icefuzz/.gitignore000066400000000000000000000001671276746530600220450ustar00rootroot00000000000000*.bin *.glb *.psb *.tmp/ *.asc *.vsb *.sdf /work_*/ __pycache__ bitdata_*.txt data_*.txt database_*.txt timings_*.html fpga-icestorm-0~20160913git266e758/icefuzz/Makefile000066400000000000000000000112211276746530600215060ustar00rootroot00000000000000include ../config.mk export LC_ALL=C export ICE_SBTIMER_LP=1 TESTS = TESTS += binop TESTS += pin2pin TESTS += mesh TESTS += fanout TESTS += logic TESTS += cluster TESTS += iopack TESTS += io TESTS += gbio TESTS += gbio2 TESTS += prim TESTS += fflogic TESTS += ram40 TESTS += mem TESTS += pll TESTS += aig EIGTHK = _8k database: bitdata_io.txt bitdata_logic.txt bitdata_ramb$(EIGTHK).txt bitdata_ramt$(EIGTHK).txt ifeq ($(EIGTHK),_8k) cp cached_ramb.txt bitdata_ramb.txt cp cached_ramt.txt bitdata_ramt.txt else cp cached_ramb_8k.txt bitdata_ramb_8k.txt cp cached_ramt_8k.txt bitdata_ramt_8k.txt endif python3 database.py python3 export.py diff -U0 cached_io.txt bitdata_io.txt || cp -v bitdata_io.txt cached_io.txt diff -U0 cached_logic.txt bitdata_logic.txt || cp -v bitdata_logic.txt cached_logic.txt diff -U0 cached_ramb.txt bitdata_ramb.txt || cp -v bitdata_ramb.txt cached_ramb.txt diff -U0 cached_ramt.txt bitdata_ramt.txt || cp -v bitdata_ramt.txt cached_ramt.txt diff -U0 cached_ramb_8k.txt bitdata_ramb_8k.txt || cp -v bitdata_ramb_8k.txt cached_ramb_8k.txt diff -U0 cached_ramt_8k.txt bitdata_ramt_8k.txt || cp -v bitdata_ramt_8k.txt cached_ramt_8k.txt timings: ifeq ($(EIGTHK),_8k) cp tmedges.txt tmedges.tmp set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_hx8k.txt work_*/*.sdf > timings_hx8k.new mv timings_hx8k.new timings_hx8k.txt python3 timings.py -t timings_lp8k.txt work_*/*.slp > timings_lp8k.new mv timings_lp8k.new timings_lp8k.txt else cp tmedges.txt tmedges.tmp set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_hx1k.txt work_*/*.sdf > timings_hx1k.new mv timings_hx1k.new timings_hx1k.txt python3 timings.py -t timings_lp1k.txt work_*/*.slp > timings_lp1k.new mv timings_lp1k.new timings_lp1k.txt endif timings_html: python3 timings.py -h tmedges.txt -t timings_hx1k.txt -l "HX1K with default temp/volt settings" > timings_hx1k.html python3 timings.py -h tmedges.txt -t timings_hx8k.txt -l "HX8K with default temp/volt settings" > timings_hx8k.html python3 timings.py -h tmedges.txt -t timings_lp1k.txt -l "LP1K with default temp/volt settings" > timings_lp1k.html python3 timings.py -h tmedges.txt -t timings_lp8k.txt -l "LP8K with default temp/volt settings" > timings_lp8k.html data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new gawk '{ print "ramb$(EIGTHK)", $$0; }' cached_ramb$(EIGTHK).txt >> data_cached.new gawk '{ print "ramt$(EIGTHK)", $$0; }' cached_ramt$(EIGTHK).txt >> data_cached.new mv data_cached.new data_cached.txt bitdata_io.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) grep ^io $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_logic.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) grep ^logic $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_ramb$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) grep ^ramb$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ bitdata_ramt$(EIGTHK).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) grep ^ramt$(EIGTHK) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) ../icepack/icepack: $(MAKE) -C ../icepack define data_template data_$(1).txt: make_$(1).py ../icepack/icepack ifeq ($(EIGTHK),_8k) ICE8KPINS=1 python3 make_$(1).py +ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1) python3 extract.py -8 work_$(1)/*.glb > $$@ else python3 make_$(1).py +$(MAKE) -C work_$(1) python3 extract.py work_$(1)/*.glb > $$@ endif endef $(foreach test,$(TESTS),$(eval $(call data_template,$(test)))) %.ok: %.bin bash check.sh $< check: $(addsuffix .ok,$(basename $(wildcard work_binop/*.bin))) check: $(addsuffix .ok,$(basename $(wildcard work_pin2pin/*.bin))) check: $(addsuffix .ok,$(basename $(wildcard work_mesh/*.bin))) check: $(addsuffix .ok,$(basename $(wildcard work_fanout/*.bin))) check: $(addsuffix .ok,$(basename $(wildcard work_logic/*.bin))) check: $(addsuffix .ok,$(basename $(wildcard work_cluster/*.bin))) check: $(addsuffix .ok,$(basename $(wildcard work_iopack/*.bin))) check: $(addsuffix .ok,$(basename $(wildcard work_pll/*.bin))) clean: rm -rf work_* rm -rf data_*.txt rm -rf bitdata_*.txt rm -rf database_*.txt rm -rf timings_*.html .PHONY: database datafiles check clean fpga-icestorm-0~20160913git266e758/icefuzz/cached_io.txt000066400000000000000000003744271276746530600225310ustar00rootroot00000000000000(0 0) Enable bit of Mux _out_links/OutMux2_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_16 (0 0) Enable bit of Mux _out_links/OutMux2_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_16 (0 1) Enable bit of Mux _out_links/OutMux0_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_0 (0 1) Enable bit of Mux _out_links/OutMux0_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_0 (0 10) Enable bit of Mux _out_links/OutMux7_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_6 (0 10) Enable bit of Mux _out_links/OutMux7_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_6 (0 11) Enable bit of Mux _out_links/OutMux5_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_44 (0 11) Enable bit of Mux _out_links/OutMux5_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_44 (0 12) Enable bit of Mux _out_links/OutMux2_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_22 (0 12) Enable bit of Mux _out_links/OutMux2_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_22 (0 13) Enable bit of Mux _out_links/OutMux0_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_6 (0 13) Enable bit of Mux _out_links/OutMux0_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_6 (0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_7 (0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_7 (0 15) Enable bit of Mux _out_links/OutMux5_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_46 (0 15) Enable bit of Mux _out_links/OutMux5_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_46 (0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_4 (0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_4 (0 3) Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_40 (0 3) Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_40 (0 4) Enable bit of Mux _out_links/OutMux2_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_18 (0 4) Enable bit of Mux _out_links/OutMux2_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_18 (0 5) Enable bit of Mux _out_links/OutMux0_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_2 (0 5) Enable bit of Mux _out_links/OutMux0_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_2 (0 6) Enable bit of Mux _out_links/OutMux7_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_5 (0 6) Enable bit of Mux _out_links/OutMux7_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_5 (0 7) Enable bit of Mux _out_links/OutMux5_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_42 (0 7) Enable bit of Mux _out_links/OutMux5_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_42 (0 8) Enable bit of Mux _out_links/OutMux2_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_20 (0 8) Enable bit of Mux _out_links/OutMux2_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_20 (0 9) Enable bit of Mux _out_links/OutMux0_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_4 (0 9) Enable bit of Mux _out_links/OutMux0_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_4 (1 0) Enable bit of Mux _out_links/OutMux3_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_24 (1 0) Enable bit of Mux _out_links/OutMux3_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_24 (1 1) Enable bit of Mux _out_links/OutMux1_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_8 (1 1) Enable bit of Mux _out_links/OutMux1_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_8 (1 10) Enable bit of Mux _out_links/OutMux8_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_10 (1 10) Enable bit of Mux _out_links/OutMux8_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_10 (1 11) Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_2 (1 11) Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_2 (1 12) Enable bit of Mux _out_links/OutMux3_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_30 (1 12) Enable bit of Mux _out_links/OutMux3_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_30 (1 13) Enable bit of Mux _out_links/OutMux1_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_14 (1 13) Enable bit of Mux _out_links/OutMux1_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_14 (1 14) Enable bit of Mux _out_links/OutMux8_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_11 (1 14) Enable bit of Mux _out_links/OutMux8_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_11 (1 15) Enable bit of Mux _out_links/OutMux6_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_3 (1 15) Enable bit of Mux _out_links/OutMux6_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_3 (1 2) Enable bit of Mux _out_links/OutMux8_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_8 (1 2) Enable bit of Mux _out_links/OutMux8_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_8 (1 3) Enable bit of Mux _out_links/OutMux6_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_0 (1 3) Enable bit of Mux _out_links/OutMux6_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_0 (1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_26 (1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_26 (1 5) Enable bit of Mux _out_links/OutMux1_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_10 (1 5) Enable bit of Mux _out_links/OutMux1_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_10 (1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_9 (1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_9 (1 7) Enable bit of Mux _out_links/OutMux6_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_1 (1 7) Enable bit of Mux _out_links/OutMux6_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_1 (1 8) Enable bit of Mux _out_links/OutMux3_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_28 (1 8) Enable bit of Mux _out_links/OutMux3_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_28 (1 9) Enable bit of Mux _out_links/OutMux1_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_12 (1 9) Enable bit of Mux _out_links/OutMux1_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_12 (10 10) routing lc_trk_g0_4 wire_io_cluster/io_1/OUT_ENB (10 10) routing lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB (10 10) routing lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB (10 10) routing lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB (10 11) routing lc_trk_g0_2 wire_io_cluster/io_1/OUT_ENB (10 11) routing lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB (10 11) routing lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB (10 11) routing lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB (10 14) routing lc_trk_g0_4 wire_io_cluster/io_1/D_OUT_1 (10 14) routing lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1 (10 14) routing lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1 (10 14) routing lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1 (10 15) routing lc_trk_g0_2 wire_io_cluster/io_1/D_OUT_1 (10 15) routing lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1 (10 15) routing lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1 (10 15) routing lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1 (10 4) routing lc_trk_g0_5 wire_io_cluster/io_0/OUT_ENB (10 4) routing lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB (10 4) routing lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB (10 4) routing lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB (10 5) routing lc_trk_g0_3 wire_io_cluster/io_0/OUT_ENB (10 5) routing lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB (10 5) routing lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB (10 5) routing lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB (10 8) routing lc_trk_g0_5 wire_io_cluster/io_0/D_OUT_1 (10 8) routing lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1 (10 8) routing lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1 (10 8) routing lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1 (10 9) routing lc_trk_g0_3 wire_io_cluster/io_0/D_OUT_1 (10 9) routing lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1 (10 9) routing lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1 (10 9) routing lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1 (11 0) routing span4_horz_1 span4_vert_t_12 (11 0) routing span4_horz_r_0 span4_horz_l_12 (11 0) routing span4_vert_1 span4_horz_l_12 (11 0) routing span4_vert_b_0 span4_vert_t_12 (11 1) routing span4_horz_1 span4_horz_25 (11 1) routing span4_horz_l_12 span4_vert_25 (11 1) routing span4_vert_1 span4_vert_25 (11 1) routing span4_vert_t_12 span4_horz_25 (11 10) routing lc_trk_g1_1 wire_io_cluster/io_1/OUT_ENB (11 10) routing lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB (11 10) routing lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB (11 10) routing lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_0 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_2 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_4 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_1 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB (11 11) Enable bit of Mux _io_cluster/in_mux1_0 => lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB (11 12) routing span4_horz_19 span4_vert_t_15 (11 12) routing span4_horz_r_3 span4_horz_l_15 (11 12) routing span4_vert_19 span4_horz_l_15 (11 12) routing span4_vert_b_3 span4_vert_t_15 (11 13) routing span4_horz_19 span4_horz_43 (11 13) routing span4_horz_l_15 span4_vert_43 (11 13) routing span4_vert_19 span4_vert_43 (11 13) routing span4_vert_t_15 span4_horz_43 (11 14) routing lc_trk_g1_1 wire_io_cluster/io_1/D_OUT_1 (11 14) routing lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1 (11 14) routing lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1 (11 14) routing lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_0 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_2 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_4 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_1 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1 (11 15) Enable bit of Mux _io_cluster/in_mux1_2 => lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1 (11 2) routing span4_horz_7 span4_vert_t_13 (11 2) routing span4_horz_r_1 span4_horz_l_13 (11 2) routing span4_vert_7 span4_horz_l_13 (11 2) routing span4_vert_b_1 span4_vert_t_13 (11 3) routing span4_horz_7 span4_horz_31 (11 3) routing span4_horz_l_13 span4_vert_31 (11 3) routing span4_vert_7 span4_vert_31 (11 3) routing span4_vert_t_13 span4_horz_31 (11 4) routing lc_trk_g1_0 wire_io_cluster/io_0/OUT_ENB (11 4) routing lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB (11 4) routing lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB (11 4) routing lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_1 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_3 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_5 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_0 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB (11 5) Enable bit of Mux _io_cluster/in_mux0_0 => lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB (11 6) routing span4_horz_13 span4_vert_t_14 (11 6) routing span4_horz_r_2 span4_horz_l_14 (11 6) routing span4_vert_13 span4_horz_l_14 (11 6) routing span4_vert_b_2 span4_vert_t_14 (11 7) routing span4_horz_13 span4_horz_37 (11 7) routing span4_horz_l_14 span4_vert_37 (11 7) routing span4_vert_13 span4_vert_37 (11 7) routing span4_vert_t_14 span4_horz_37 (11 8) routing lc_trk_g1_0 wire_io_cluster/io_0/D_OUT_1 (11 8) routing lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1 (11 8) routing lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1 (11 8) routing lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_1 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_3 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_5 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_0 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1 (11 9) Enable bit of Mux _io_cluster/in_mux0_2 => lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1 (12 0) routing span4_horz_1 span4_vert_t_12 (12 0) routing span4_horz_25 span4_vert_t_12 (12 0) routing span4_vert_1 span4_horz_l_12 (12 0) routing span4_vert_25 span4_horz_l_12 (12 1) routing span4_horz_1 span4_horz_25 (12 1) routing span4_horz_r_0 span4_vert_25 (12 1) routing span4_vert_1 span4_vert_25 (12 1) routing span4_vert_b_0 span4_horz_25 (12 10) routing lc_trk_g1_0 wire_io_cluster/io_1/D_OUT_0 (12 10) routing lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0 (12 10) routing lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0 (12 10) routing lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0 (12 11) routing lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0 (12 11) routing lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0 (12 11) routing lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0 (12 11) routing lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0 (12 12) routing span4_horz_19 span4_vert_t_15 (12 12) routing span4_horz_43 span4_vert_t_15 (12 12) routing span4_vert_19 span4_horz_l_15 (12 12) routing span4_vert_43 span4_horz_l_15 (12 13) routing span4_horz_19 span4_horz_43 (12 13) routing span4_horz_r_3 span4_vert_43 (12 13) routing span4_vert_19 span4_vert_43 (12 13) routing span4_vert_b_3 span4_horz_43 (12 14) routing glb_netwk_2 wire_io_cluster/io_1/outclk (12 14) routing glb_netwk_3 wire_io_cluster/io_1/outclk (12 14) routing glb_netwk_6 wire_io_cluster/io_1/outclk (12 14) routing glb_netwk_7 wire_io_cluster/io_1/outclk (12 14) routing lc_trk_g1_1 wire_io_cluster/io_1/outclk (12 14) routing lc_trk_g1_4 wire_io_cluster/io_1/outclk (12 15) routing glb_netwk_1 wire_io_cluster/io_1/outclk (12 15) routing glb_netwk_3 wire_io_cluster/io_1/outclk (12 15) routing glb_netwk_5 wire_io_cluster/io_1/outclk (12 15) routing glb_netwk_7 wire_io_cluster/io_1/outclk (12 15) routing lc_trk_g0_4 wire_io_cluster/io_1/outclk (12 15) routing lc_trk_g1_4 wire_io_cluster/io_1/outclk (12 2) routing span4_horz_31 span4_vert_t_13 (12 2) routing span4_horz_7 span4_vert_t_13 (12 2) routing span4_vert_31 span4_horz_l_13 (12 2) routing span4_vert_7 span4_horz_l_13 (12 3) routing span4_horz_7 span4_horz_31 (12 3) routing span4_horz_r_1 span4_vert_31 (12 3) routing span4_vert_7 span4_vert_31 (12 3) routing span4_vert_b_1 span4_horz_31 (12 4) routing lc_trk_g1_1 wire_io_cluster/io_0/D_OUT_0 (12 4) routing lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0 (12 4) routing lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0 (12 4) routing lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0 (12 5) routing lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0 (12 5) routing lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0 (12 5) routing lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0 (12 5) routing lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0 (12 6) routing span4_horz_13 span4_vert_t_14 (12 6) routing span4_horz_37 span4_vert_t_14 (12 6) routing span4_vert_13 span4_horz_l_14 (12 6) routing span4_vert_37 span4_horz_l_14 (12 7) routing span4_horz_13 span4_horz_37 (12 7) routing span4_horz_r_2 span4_vert_37 (12 7) routing span4_vert_13 span4_vert_37 (12 7) routing span4_vert_b_2 span4_horz_37 (12 8) routing glb_netwk_2 wire_io_cluster/io_1/inclk (12 8) routing glb_netwk_3 wire_io_cluster/io_1/inclk (12 8) routing glb_netwk_6 wire_io_cluster/io_1/inclk (12 8) routing glb_netwk_7 wire_io_cluster/io_1/inclk (12 8) routing lc_trk_g1_0 wire_io_cluster/io_1/inclk (12 8) routing lc_trk_g1_3 wire_io_cluster/io_1/inclk (12 9) routing glb_netwk_1 wire_io_cluster/io_1/inclk (12 9) routing glb_netwk_3 wire_io_cluster/io_1/inclk (12 9) routing glb_netwk_5 wire_io_cluster/io_1/inclk (12 9) routing glb_netwk_7 wire_io_cluster/io_1/inclk (12 9) routing lc_trk_g0_3 wire_io_cluster/io_1/inclk (12 9) routing lc_trk_g1_3 wire_io_cluster/io_1/inclk (13 0) routing span4_horz_25 span4_horz_1 (13 0) routing span4_horz_r_0 span4_vert_1 (13 0) routing span4_vert_25 span4_vert_1 (13 0) routing span4_vert_b_0 span4_horz_1 (13 1) routing span4_horz_1 span4_vert_b_0 (13 1) routing span4_horz_25 span4_vert_b_0 (13 1) routing span4_vert_1 span4_horz_r_0 (13 1) routing span4_vert_25 span4_horz_r_0 (13 10) routing lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0 (13 10) routing lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0 (13 10) routing lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0 (13 10) routing lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_1 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_0 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0 (13 11) Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0 (13 12) routing span4_horz_43 span4_horz_19 (13 12) routing span4_horz_r_3 span4_vert_19 (13 12) routing span4_vert_43 span4_vert_19 (13 12) routing span4_vert_b_3 span4_horz_19 (13 13) routing span4_horz_19 span4_vert_b_3 (13 13) routing span4_horz_43 span4_vert_b_3 (13 13) routing span4_vert_19 span4_horz_r_3 (13 13) routing span4_vert_43 span4_horz_r_3 (13 14) routing lc_trk_g0_1 wire_io_cluster/io_1/outclk (13 14) routing lc_trk_g0_4 wire_io_cluster/io_1/outclk (13 14) routing lc_trk_g1_1 wire_io_cluster/io_1/outclk (13 14) routing lc_trk_g1_4 wire_io_cluster/io_1/outclk (13 15) Negative Clock bit (13 2) routing span4_horz_31 span4_horz_7 (13 2) routing span4_horz_r_1 span4_vert_7 (13 2) routing span4_vert_31 span4_vert_7 (13 2) routing span4_vert_b_1 span4_horz_7 (13 3) routing span4_horz_31 span4_vert_b_1 (13 3) routing span4_horz_7 span4_vert_b_1 (13 3) routing span4_vert_31 span4_horz_r_1 (13 3) routing span4_vert_7 span4_horz_r_1 (13 4) routing lc_trk_g0_4 wire_io_cluster/io_0/D_OUT_0 (13 4) routing lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0 (13 4) routing lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0 (13 4) routing lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_0 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_4 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_1 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0 (13 5) Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0 (13 6) routing span4_horz_37 span4_horz_13 (13 6) routing span4_horz_r_2 span4_vert_13 (13 6) routing span4_vert_37 span4_vert_13 (13 6) routing span4_vert_b_2 span4_horz_13 (13 7) routing span4_horz_13 span4_vert_b_2 (13 7) routing span4_horz_37 span4_vert_b_2 (13 7) routing span4_vert_13 span4_horz_r_2 (13 7) routing span4_vert_37 span4_horz_r_2 (13 8) routing lc_trk_g0_0 wire_io_cluster/io_1/inclk (13 8) routing lc_trk_g0_3 wire_io_cluster/io_1/inclk (13 8) routing lc_trk_g1_0 wire_io_cluster/io_1/inclk (13 8) routing lc_trk_g1_3 wire_io_cluster/io_1/inclk (13 9) Negative Clock bit (14 0) routing span4_horz_l_12 span4_vert_1 (14 0) routing span4_horz_r_0 span4_vert_1 (14 0) routing span4_vert_b_0 span4_horz_1 (14 0) routing span4_vert_t_12 span4_horz_1 (14 1) routing span4_horz_1 span4_vert_b_0 (14 1) routing span4_horz_l_12 span4_horz_r_0 (14 1) routing span4_vert_1 span4_horz_r_0 (14 1) routing span4_vert_t_12 span4_vert_b_0 (14 10) routing glb_netwk_3 wire_io_cluster/io_1/cen (14 10) routing glb_netwk_7 wire_io_cluster/io_1/cen (14 10) routing lc_trk_g0_5 wire_io_cluster/io_1/cen (14 10) routing lc_trk_g1_5 wire_io_cluster/io_1/cen (14 11) routing lc_trk_g0_2 wire_io_cluster/io_1/cen (14 11) routing lc_trk_g0_5 wire_io_cluster/io_1/cen (14 11) routing lc_trk_g1_2 wire_io_cluster/io_1/cen (14 11) routing lc_trk_g1_5 wire_io_cluster/io_1/cen (14 12) routing span4_horz_l_15 span4_vert_19 (14 12) routing span4_horz_r_3 span4_vert_19 (14 12) routing span4_vert_b_3 span4_horz_19 (14 12) routing span4_vert_t_15 span4_horz_19 (14 13) routing span4_horz_19 span4_vert_b_3 (14 13) routing span4_horz_l_15 span4_horz_r_3 (14 13) routing span4_vert_19 span4_horz_r_3 (14 13) routing span4_vert_t_15 span4_vert_b_3 (14 14) routing glb_netwk_4 wire_io_cluster/io_1/outclk (14 14) routing glb_netwk_5 wire_io_cluster/io_1/outclk (14 14) routing glb_netwk_6 wire_io_cluster/io_1/outclk (14 14) routing glb_netwk_7 wire_io_cluster/io_1/outclk (14 2) routing span4_horz_l_13 span4_vert_7 (14 2) routing span4_horz_r_1 span4_vert_7 (14 2) routing span4_vert_b_1 span4_horz_7 (14 2) routing span4_vert_t_13 span4_horz_7 (14 3) routing span4_horz_7 span4_vert_b_1 (14 3) routing span4_horz_l_13 span4_horz_r_1 (14 3) routing span4_vert_7 span4_horz_r_1 (14 3) routing span4_vert_t_13 span4_vert_b_1 (14 4) routing lc_trk_g0_3 fabout (14 4) routing lc_trk_g0_3 wire_gbuf/in (14 4) routing lc_trk_g0_7 fabout (14 4) routing lc_trk_g0_7 wire_gbuf/in (14 4) routing lc_trk_g1_2 fabout (14 4) routing lc_trk_g1_2 wire_gbuf/in (14 4) routing lc_trk_g1_6 fabout (14 4) routing lc_trk_g1_6 wire_gbuf/in (14 5) routing lc_trk_g1_0 fabout (14 5) routing lc_trk_g1_0 wire_gbuf/in (14 5) routing lc_trk_g1_2 fabout (14 5) routing lc_trk_g1_2 wire_gbuf/in (14 5) routing lc_trk_g1_4 fabout (14 5) routing lc_trk_g1_4 wire_gbuf/in (14 5) routing lc_trk_g1_6 fabout (14 5) routing lc_trk_g1_6 wire_gbuf/in (14 6) routing span4_horz_l_14 span4_vert_13 (14 6) routing span4_horz_r_2 span4_vert_13 (14 6) routing span4_vert_b_2 span4_horz_13 (14 6) routing span4_vert_t_14 span4_horz_13 (14 7) routing span4_horz_13 span4_vert_b_2 (14 7) routing span4_horz_l_14 span4_horz_r_2 (14 7) routing span4_vert_13 span4_horz_r_2 (14 7) routing span4_vert_t_14 span4_vert_b_2 (14 8) routing glb_netwk_4 wire_io_cluster/io_1/inclk (14 8) routing glb_netwk_5 wire_io_cluster/io_1/inclk (14 8) routing glb_netwk_6 wire_io_cluster/io_1/inclk (14 8) routing glb_netwk_7 wire_io_cluster/io_1/inclk (15 10) Enable bit of Mux _clock_links/ceb_mux => glb_netwk_1 wire_io_cluster/io_1/cen (15 10) Enable bit of Mux _clock_links/ceb_mux => glb_netwk_3 wire_io_cluster/io_1/cen (15 10) Enable bit of Mux _clock_links/ceb_mux => glb_netwk_5 wire_io_cluster/io_1/cen (15 10) Enable bit of Mux _clock_links/ceb_mux => glb_netwk_7 wire_io_cluster/io_1/cen (15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g0_2 wire_io_cluster/io_1/cen (15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g0_5 wire_io_cluster/io_1/cen (15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g1_2 wire_io_cluster/io_1/cen (15 10) Enable bit of Mux _clock_links/ceb_mux => lc_trk_g1_5 wire_io_cluster/io_1/cen (15 11) routing glb_netwk_5 wire_io_cluster/io_1/cen (15 11) routing glb_netwk_7 wire_io_cluster/io_1/cen (15 11) routing lc_trk_g1_2 wire_io_cluster/io_1/cen (15 11) routing lc_trk_g1_5 wire_io_cluster/io_1/cen (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_0 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_1 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_2 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_3 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_4 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_5 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_6 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => glb_netwk_7 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g0_1 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g0_4 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g1_1 wire_io_cluster/io_1/outclk (15 15) Enable bit of Mux _clock_links/clk_mux => lc_trk_g1_4 wire_io_cluster/io_1/outclk (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_1 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_1 wire_gbuf/in (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_3 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_3 wire_gbuf/in (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_5 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_5 wire_gbuf/in (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_7 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g0_7 wire_gbuf/in (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_0 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_0 wire_gbuf/in (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_2 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_2 wire_gbuf/in (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_4 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_4 wire_gbuf/in (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_6 fabout (15 4) Enable bit of Mux _fablink/Mux => lc_trk_g1_6 wire_gbuf/in (15 5) routing lc_trk_g0_5 fabout (15 5) routing lc_trk_g0_5 wire_gbuf/in (15 5) routing lc_trk_g0_7 fabout (15 5) routing lc_trk_g0_7 wire_gbuf/in (15 5) routing lc_trk_g1_4 fabout (15 5) routing lc_trk_g1_4 wire_gbuf/in (15 5) routing lc_trk_g1_6 fabout (15 5) routing lc_trk_g1_6 wire_gbuf/in (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_0 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_1 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_2 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_3 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_4 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_5 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_6 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => glb_netwk_7 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g0_0 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g0_3 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g1_0 wire_io_cluster/io_1/inclk (15 9) Enable bit of Mux _clock_links/inclk_mux => lc_trk_g1_3 wire_io_cluster/io_1/inclk (16 0) IOB_0 IO Functioning bit (16 0) IOB_0 PINTYPE_3 (16 10) IOB_1 IO Functioning bit (16 10) IOB_1 PINTYPE_3 (16 13) IOB_1 IO Functioning bit (16 13) IOB_1 PINTYPE_1 (16 14) IOB_1 IO Functioning bit (16 14) IOB_1 PINTYPE_4 (16 3) IOB_0 IO Functioning bit (16 3) IOB_0 PINTYPE_1 (16 4) IOB_0 IO Functioning bit (16 4) IOB_0 PINTYPE_4 (16 6) Enable bit of Mux _out_links/OutMuxc_1 => wire_io_cluster/io_0/D_IN_1 span12_horz_18 (16 6) Enable bit of Mux _out_links/OutMuxc_1 => wire_io_cluster/io_0/D_IN_1 span12_vert_18 (16 7) Enable bit of Mux _out_links/OutMuxa_1 => wire_io_cluster/io_0/D_IN_1 span12_horz_2 (16 7) Enable bit of Mux _out_links/OutMuxa_1 => wire_io_cluster/io_0/D_IN_1 span12_vert_2 (16 8) Enable bit of Mux _out_links/OutMuxc_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_20 (16 8) Enable bit of Mux _out_links/OutMuxc_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_20 (16 9) Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_4 (16 9) Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_4 (17 0) IOB_0 IO Functioning bit (17 0) IOB_0 PINTYPE_2 (17 1) Enable bit of Mux _out_links/OutMuxa_0 => wire_io_cluster/io_0/D_IN_0 span12_horz_0 (17 1) Enable bit of Mux _out_links/OutMuxa_0 => wire_io_cluster/io_0/D_IN_0 span12_vert_0 (17 10) IOB_1 IO Functioning bit (17 10) IOB_1 PINTYPE_2 (17 11) Enable bit of Mux _out_links/OutMuxa_3 => wire_io_cluster/io_1/D_IN_1 span12_horz_6 (17 11) Enable bit of Mux _out_links/OutMuxa_3 => wire_io_cluster/io_1/D_IN_1 span12_vert_6 (17 12) Enable bit of Mux _out_links/OutMuxb_3 => wire_io_cluster/io_1/D_IN_1 span12_horz_14 (17 12) Enable bit of Mux _out_links/OutMuxb_3 => wire_io_cluster/io_1/D_IN_1 span12_vert_14 (17 13) IOB_1 IO Functioning bit (17 13) IOB_1 PINTYPE_0 (17 14) IOB_1 IO Functioning bit (17 14) IOB_1 PINTYPE_5 (17 15) Enable bit of Mux _out_links/OutMuxc_3 => wire_io_cluster/io_1/D_IN_1 span12_horz_22 (17 15) Enable bit of Mux _out_links/OutMuxc_3 => wire_io_cluster/io_1/D_IN_1 span12_vert_22 (17 2) Enable bit of Mux _out_links/OutMuxb_0 => wire_io_cluster/io_0/D_IN_0 span12_horz_8 (17 2) Enable bit of Mux _out_links/OutMuxb_0 => wire_io_cluster/io_0/D_IN_0 span12_vert_8 (17 3) IOB_0 IO Functioning bit (17 3) IOB_0 PINTYPE_0 (17 4) IOB_0 IO Functioning bit (17 4) IOB_0 PINTYPE_5 (17 5) Enable bit of Mux _out_links/OutMuxc_0 => wire_io_cluster/io_0/D_IN_0 span12_horz_16 (17 5) Enable bit of Mux _out_links/OutMuxc_0 => wire_io_cluster/io_0/D_IN_0 span12_vert_16 (17 7) Enable bit of Mux _out_links/OutMuxb_1 => wire_io_cluster/io_0/D_IN_1 span12_horz_10 (17 7) Enable bit of Mux _out_links/OutMuxb_1 => wire_io_cluster/io_0/D_IN_1 span12_vert_10 (17 9) Enable bit of Mux _out_links/OutMuxb_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_12 (17 9) Enable bit of Mux _out_links/OutMuxb_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_12 (2 0) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_1 (2 0) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_1 (2 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_1 (2 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_1 (2 0) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_1 (2 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_1 (2 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_1 (2 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_1 (2 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_1 (2 0) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_1 (2 1) Enable bit of Mux _out_links/OutMux4_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_32 (2 1) Enable bit of Mux _out_links/OutMux4_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_32 (2 11) Enable bit of Mux _out_links/OutMux9_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_14 (2 11) Enable bit of Mux _out_links/OutMux9_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_b_14 (2 13) Enable bit of Mux _out_links/OutMux4_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_38 (2 13) Enable bit of Mux _out_links/OutMux4_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_38 (2 15) Enable bit of Mux _out_links/OutMux9_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_15 (2 15) Enable bit of Mux _out_links/OutMux9_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_15 (2 2) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_4 (2 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_4 (2 2) PLL config bit: CLOCK_T_18_33_IOUP_cf_bit_4 (2 3) Enable bit of Mux _out_links/OutMux9_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_12 (2 3) Enable bit of Mux _out_links/OutMux9_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_12 (2 4) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_7 (2 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_7 (2 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_7 (2 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_7 (2 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_7 (2 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_7 (2 4) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_7 (2 4) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_7 (2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_34 (2 5) Enable bit of Mux _out_links/OutMux4_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_34 (2 6) IO control bit: BIODOWN_REN_0 (2 6) IO control bit: BIOLEFT_REN_0 (2 6) IO control bit: BIORIGHT_REN_0 (2 6) IO control bit: BIOUP_REN_0 (2 6) IO control bit: GIODOWN0_REN_0 (2 6) IO control bit: GIODOWN1_REN_0 (2 6) IO control bit: GIOLEFT0_REN_0 (2 6) IO control bit: GIOLEFT1_REN_0 (2 6) IO control bit: GIORIGHT0_REN_0 (2 6) IO control bit: GIORIGHT1_REN_0 (2 6) IO control bit: GIOUP0_REN_0 (2 6) IO control bit: GIOUP1_REN_0 (2 6) IO control bit: IODOWN_REN_0 (2 6) IO control bit: IOLEFT_REN_0 (2 6) IO control bit: IORIGHT_REN_0 (2 6) IO control bit: IOUP_REN_0 (2 7) Enable bit of Mux _out_links/OutMux9_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_13 (2 7) Enable bit of Mux _out_links/OutMux9_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_13 (2 8) IO control bit: BIOLEFT_LVDS_en (2 9) Enable bit of Mux _out_links/OutMux4_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_36 (2 9) Enable bit of Mux _out_links/OutMux4_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_36 (3 0) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_2 (3 0) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_2 (3 0) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_2 (3 0) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_2 (3 0) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_2 (3 0) PLL config bit: CLOCK_T_18_33_IOUP_cf_bit_2 (3 1) IO control bit: BIODOWN_REN_1 (3 1) IO control bit: BIOLEFT_REN_1 (3 1) IO control bit: BIORIGHT_REN_1 (3 1) IO control bit: BIOUP_REN_1 (3 1) IO control bit: GIODOWN0_REN_1 (3 1) IO control bit: GIODOWN1_REN_1 (3 1) IO control bit: GIOLEFT0_REN_1 (3 1) IO control bit: GIOLEFT1_REN_1 (3 1) IO control bit: GIORIGHT0_REN_1 (3 1) IO control bit: GIORIGHT1_REN_1 (3 1) IO control bit: GIOUP0_REN_1 (3 1) IO control bit: GIOUP1_REN_1 (3 1) IO control bit: IODOWN_REN_1 (3 1) IO control bit: IOLEFT_REN_1 (3 1) IO control bit: IORIGHT_REN_1 (3 1) IO control bit: IOUP_REN_1 (3 11) Icegate Enable bit: GIODOWN0_padin_latch_enable (3 11) Icegate Enable bit: GIODOWN1_padin_latch_enable (3 11) Icegate Enable bit: GIOLEFT0_padin_latch_enable (3 11) Icegate Enable bit: GIOLEFT1_padin_latch_enable (3 11) Icegate Enable bit: GIORIGHT0_padin_latch_enable (3 11) Icegate Enable bit: GIORIGHT1_padin_latch_enable (3 11) Icegate Enable bit: GIOUP0_padin_latch_enable (3 11) Icegate Enable bit: GIOUP1_padin_latch_enable (3 2) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_5 (3 2) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_5 (3 2) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_5 (3 3) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_0_5_IOLEFT_cf_bit_3 (3 3) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_3 (3 3) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_3 (3 3) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_3 (3 3) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_3 (3 3) PLL config bit: CLOCK_T_18_0_IODOWN_cf_bit_3 (3 4) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_8 (3 4) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_8 (3 4) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_8 (3 4) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_8 (3 4) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_8 (3 4) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_8 (3 4) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_8 (3 5) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_6 (3 5) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_6 (3 5) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_6 (3 5) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_6 (3 5) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_6 (3 6) IO control bit: BIODOWN_IE_1 (3 6) IO control bit: BIOLEFT_IE_1 (3 6) IO control bit: BIORIGHT_IE_1 (3 6) IO control bit: BIOUP_IE_1 (3 6) IO control bit: GIODOWN0_IE_1 (3 6) IO control bit: GIODOWN1_IE_1 (3 6) IO control bit: GIOLEFT0_IE_1 (3 6) IO control bit: GIOLEFT1_IE_1 (3 6) IO control bit: GIORIGHT0_IE_1 (3 6) IO control bit: GIORIGHT1_IE_1 (3 6) IO control bit: GIOUP0_IE_1 (3 6) IO control bit: GIOUP1_IE_1 (3 6) IO control bit: IODOWN_IE_1 (3 6) IO control bit: IOLEFT_IE_1 (3 6) IO control bit: IORIGHT_IE_1 (3 6) IO control bit: IOUP_IE_1 (3 7) PLL config bit: CLOCK_T_0_1_IOLEFT_cf_bit_9 (3 7) PLL config bit: CLOCK_T_0_2_IOLEFT_cf_bit_9 (3 7) PLL config bit: CLOCK_T_0_3_IOLEFT_cf_bit_9 (3 7) PLL config bit: CLOCK_T_0_4_IOLEFT_cf_bit_9 (3 7) PLL config bit: CLOCK_T_14_0_IODOWN_cf_bit_9 (3 7) PLL config bit: CLOCK_T_15_0_IODOWN_cf_bit_9 (3 7) PLL config bit: CLOCK_T_16_0_IODOWN_cf_bit_9 (3 7) PLL config bit: CLOCK_T_17_0_IODOWN_cf_bit_9 (3 9) IO control bit: BIODOWN_IE_0 (3 9) IO control bit: BIOLEFT_IE_0 (3 9) IO control bit: BIORIGHT_IE_0 (3 9) IO control bit: BIOUP_IE_0 (3 9) IO control bit: GIODOWN0_IE_0 (3 9) IO control bit: GIODOWN1_IE_0 (3 9) IO control bit: GIOLEFT0_IE_0 (3 9) IO control bit: GIOLEFT1_IE_0 (3 9) IO control bit: GIORIGHT0_IE_0 (3 9) IO control bit: GIORIGHT1_IE_0 (3 9) IO control bit: GIOUP0_IE_0 (3 9) IO control bit: GIOUP1_IE_0 (3 9) IO control bit: IODOWN_IE_0 (3 9) IO control bit: IOLEFT_IE_0 (3 9) IO control bit: IORIGHT_IE_0 (3 9) IO control bit: IOUP_IE_0 (4 0) routing IO_B.logic_op_tnl_0 lc_trk_g0_0 (4 0) routing IO_B.logic_op_top_0 lc_trk_g0_0 (4 0) routing IO_L.logic_op_rgt_0 lc_trk_g0_0 (4 0) routing IO_L.logic_op_tnr_0 lc_trk_g0_0 (4 0) routing IO_R.logic_op_lft_0 lc_trk_g0_0 (4 0) routing IO_R.logic_op_tnl_0 lc_trk_g0_0 (4 0) routing IO_T.logic_op_bnl_0 lc_trk_g0_0 (4 0) routing IO_T.logic_op_bot_0 lc_trk_g0_0 (4 0) routing span12_horz_0 lc_trk_g0_0 (4 0) routing span12_vert_0 lc_trk_g0_0 (4 0) routing span4_horz_0 lc_trk_g0_0 (4 0) routing span4_horz_32 lc_trk_g0_0 (4 0) routing span4_horz_40 lc_trk_g0_0 (4 0) routing span4_horz_8 lc_trk_g0_0 (4 0) routing span4_horz_r_8 lc_trk_g0_0 (4 0) routing span4_vert_0 lc_trk_g0_0 (4 0) routing span4_vert_32 lc_trk_g0_0 (4 0) routing span4_vert_40 lc_trk_g0_0 (4 0) routing span4_vert_8 lc_trk_g0_0 (4 0) routing span4_vert_b_8 lc_trk_g0_0 (4 1) routing IO_B.logic_op_top_0 lc_trk_g0_0 (4 1) routing IO_L.logic_op_rgt_0 lc_trk_g0_0 (4 1) routing IO_R.logic_op_lft_0 lc_trk_g0_0 (4 1) routing IO_T.logic_op_bot_0 lc_trk_g0_0 (4 1) routing span12_horz_0 lc_trk_g0_0 (4 1) routing span12_horz_16 lc_trk_g0_0 (4 1) routing span12_vert_0 lc_trk_g0_0 (4 1) routing span12_vert_16 lc_trk_g0_0 (4 1) routing span4_horz_24 lc_trk_g0_0 (4 1) routing span4_horz_40 lc_trk_g0_0 (4 1) routing span4_horz_8 lc_trk_g0_0 (4 1) routing span4_horz_r_0 lc_trk_g0_0 (4 1) routing span4_vert_24 lc_trk_g0_0 (4 1) routing span4_vert_40 lc_trk_g0_0 (4 1) routing span4_vert_8 lc_trk_g0_0 (4 1) routing span4_vert_b_0 lc_trk_g0_0 (4 10) routing IO_B.logic_op_tnl_2 lc_trk_g1_2 (4 10) routing IO_B.logic_op_top_2 lc_trk_g1_2 (4 10) routing IO_L.logic_op_rgt_2 lc_trk_g1_2 (4 10) routing IO_L.logic_op_tnr_2 lc_trk_g1_2 (4 10) routing IO_R.logic_op_lft_2 lc_trk_g1_2 (4 10) routing IO_R.logic_op_tnl_2 lc_trk_g1_2 (4 10) routing IO_T.logic_op_bnl_2 lc_trk_g1_2 (4 10) routing IO_T.logic_op_bot_2 lc_trk_g1_2 (4 10) routing span12_horz_2 lc_trk_g1_2 (4 10) routing span12_vert_2 lc_trk_g1_2 (4 10) routing span4_horz_10 lc_trk_g1_2 (4 10) routing span4_horz_2 lc_trk_g1_2 (4 10) routing span4_horz_34 lc_trk_g1_2 (4 10) routing span4_horz_42 lc_trk_g1_2 (4 10) routing span4_horz_r_10 lc_trk_g1_2 (4 10) routing span4_vert_10 lc_trk_g1_2 (4 10) routing span4_vert_2 lc_trk_g1_2 (4 10) routing span4_vert_34 lc_trk_g1_2 (4 10) routing span4_vert_42 lc_trk_g1_2 (4 10) routing span4_vert_b_10 lc_trk_g1_2 (4 11) routing IO_B.logic_op_top_2 lc_trk_g1_2 (4 11) routing IO_L.logic_op_rgt_2 lc_trk_g1_2 (4 11) routing IO_R.logic_op_lft_2 lc_trk_g1_2 (4 11) routing IO_T.logic_op_bot_2 lc_trk_g1_2 (4 11) routing span12_horz_18 lc_trk_g1_2 (4 11) routing span12_horz_2 lc_trk_g1_2 (4 11) routing span12_vert_18 lc_trk_g1_2 (4 11) routing span12_vert_2 lc_trk_g1_2 (4 11) routing span4_horz_10 lc_trk_g1_2 (4 11) routing span4_horz_26 lc_trk_g1_2 (4 11) routing span4_horz_42 lc_trk_g1_2 (4 11) routing span4_horz_r_2 lc_trk_g1_2 (4 11) routing span4_vert_10 lc_trk_g1_2 (4 11) routing span4_vert_26 lc_trk_g1_2 (4 11) routing span4_vert_42 lc_trk_g1_2 (4 11) routing span4_vert_b_2 lc_trk_g1_2 (4 12) routing IO_B.logic_op_tnl_4 lc_trk_g1_4 (4 12) routing IO_B.logic_op_top_4 lc_trk_g1_4 (4 12) routing IO_L.logic_op_rgt_4 lc_trk_g1_4 (4 12) routing IO_L.logic_op_tnr_4 lc_trk_g1_4 (4 12) routing IO_R.logic_op_lft_4 lc_trk_g1_4 (4 12) routing IO_R.logic_op_tnl_4 lc_trk_g1_4 (4 12) routing IO_T.logic_op_bnl_4 lc_trk_g1_4 (4 12) routing IO_T.logic_op_bot_4 lc_trk_g1_4 (4 12) routing span12_horz_4 lc_trk_g1_4 (4 12) routing span12_vert_4 lc_trk_g1_4 (4 12) routing span4_horz_12 lc_trk_g1_4 (4 12) routing span4_horz_36 lc_trk_g1_4 (4 12) routing span4_horz_4 lc_trk_g1_4 (4 12) routing span4_horz_44 lc_trk_g1_4 (4 12) routing span4_horz_r_12 lc_trk_g1_4 (4 12) routing span4_vert_12 lc_trk_g1_4 (4 12) routing span4_vert_36 lc_trk_g1_4 (4 12) routing span4_vert_4 lc_trk_g1_4 (4 12) routing span4_vert_44 lc_trk_g1_4 (4 12) routing span4_vert_b_12 lc_trk_g1_4 (4 13) routing IO_B.logic_op_top_4 lc_trk_g1_4 (4 13) routing IO_L.logic_op_rgt_4 lc_trk_g1_4 (4 13) routing IO_R.logic_op_lft_4 lc_trk_g1_4 (4 13) routing IO_T.logic_op_bot_4 lc_trk_g1_4 (4 13) routing span12_horz_20 lc_trk_g1_4 (4 13) routing span12_horz_4 lc_trk_g1_4 (4 13) routing span12_vert_20 lc_trk_g1_4 (4 13) routing span12_vert_4 lc_trk_g1_4 (4 13) routing span4_horz_12 lc_trk_g1_4 (4 13) routing span4_horz_28 lc_trk_g1_4 (4 13) routing span4_horz_44 lc_trk_g1_4 (4 13) routing span4_horz_r_4 lc_trk_g1_4 (4 13) routing span4_vert_12 lc_trk_g1_4 (4 13) routing span4_vert_28 lc_trk_g1_4 (4 13) routing span4_vert_44 lc_trk_g1_4 (4 13) routing span4_vert_b_4 lc_trk_g1_4 (4 14) routing IO_B.logic_op_tnl_6 lc_trk_g1_6 (4 14) routing IO_B.logic_op_top_6 lc_trk_g1_6 (4 14) routing IO_L.logic_op_rgt_6 lc_trk_g1_6 (4 14) routing IO_L.logic_op_tnr_6 lc_trk_g1_6 (4 14) routing IO_R.logic_op_lft_6 lc_trk_g1_6 (4 14) routing IO_R.logic_op_tnl_6 lc_trk_g1_6 (4 14) routing IO_T.logic_op_bnl_6 lc_trk_g1_6 (4 14) routing IO_T.logic_op_bot_6 lc_trk_g1_6 (4 14) routing span12_horz_6 lc_trk_g1_6 (4 14) routing span12_vert_6 lc_trk_g1_6 (4 14) routing span4_horz_14 lc_trk_g1_6 (4 14) routing span4_horz_38 lc_trk_g1_6 (4 14) routing span4_horz_46 lc_trk_g1_6 (4 14) routing span4_horz_6 lc_trk_g1_6 (4 14) routing span4_horz_r_14 lc_trk_g1_6 (4 14) routing span4_vert_14 lc_trk_g1_6 (4 14) routing span4_vert_38 lc_trk_g1_6 (4 14) routing span4_vert_46 lc_trk_g1_6 (4 14) routing span4_vert_6 lc_trk_g1_6 (4 14) routing span4_vert_b_14 lc_trk_g1_6 (4 15) routing IO_B.logic_op_top_6 lc_trk_g1_6 (4 15) routing IO_L.logic_op_rgt_6 lc_trk_g1_6 (4 15) routing IO_R.logic_op_lft_6 lc_trk_g1_6 (4 15) routing IO_T.logic_op_bot_6 lc_trk_g1_6 (4 15) routing span12_horz_22 lc_trk_g1_6 (4 15) routing span12_horz_6 lc_trk_g1_6 (4 15) routing span12_vert_22 lc_trk_g1_6 (4 15) routing span12_vert_6 lc_trk_g1_6 (4 15) routing span4_horz_14 lc_trk_g1_6 (4 15) routing span4_horz_30 lc_trk_g1_6 (4 15) routing span4_horz_46 lc_trk_g1_6 (4 15) routing span4_horz_r_6 lc_trk_g1_6 (4 15) routing span4_vert_14 lc_trk_g1_6 (4 15) routing span4_vert_30 lc_trk_g1_6 (4 15) routing span4_vert_46 lc_trk_g1_6 (4 15) routing span4_vert_b_6 lc_trk_g1_6 (4 2) routing IO_B.logic_op_tnl_2 lc_trk_g0_2 (4 2) routing IO_B.logic_op_top_2 lc_trk_g0_2 (4 2) routing IO_L.logic_op_rgt_2 lc_trk_g0_2 (4 2) routing IO_L.logic_op_tnr_2 lc_trk_g0_2 (4 2) routing IO_R.logic_op_lft_2 lc_trk_g0_2 (4 2) routing IO_R.logic_op_tnl_2 lc_trk_g0_2 (4 2) routing IO_T.logic_op_bnl_2 lc_trk_g0_2 (4 2) routing IO_T.logic_op_bot_2 lc_trk_g0_2 (4 2) routing span12_horz_2 lc_trk_g0_2 (4 2) routing span12_vert_2 lc_trk_g0_2 (4 2) routing span4_horz_10 lc_trk_g0_2 (4 2) routing span4_horz_2 lc_trk_g0_2 (4 2) routing span4_horz_34 lc_trk_g0_2 (4 2) routing span4_horz_42 lc_trk_g0_2 (4 2) routing span4_horz_r_10 lc_trk_g0_2 (4 2) routing span4_vert_10 lc_trk_g0_2 (4 2) routing span4_vert_2 lc_trk_g0_2 (4 2) routing span4_vert_34 lc_trk_g0_2 (4 2) routing span4_vert_42 lc_trk_g0_2 (4 2) routing span4_vert_b_10 lc_trk_g0_2 (4 3) routing IO_B.logic_op_top_2 lc_trk_g0_2 (4 3) routing IO_L.logic_op_rgt_2 lc_trk_g0_2 (4 3) routing IO_R.logic_op_lft_2 lc_trk_g0_2 (4 3) routing IO_T.logic_op_bot_2 lc_trk_g0_2 (4 3) routing span12_horz_18 lc_trk_g0_2 (4 3) routing span12_horz_2 lc_trk_g0_2 (4 3) routing span12_vert_18 lc_trk_g0_2 (4 3) routing span12_vert_2 lc_trk_g0_2 (4 3) routing span4_horz_10 lc_trk_g0_2 (4 3) routing span4_horz_26 lc_trk_g0_2 (4 3) routing span4_horz_42 lc_trk_g0_2 (4 3) routing span4_horz_r_2 lc_trk_g0_2 (4 3) routing span4_vert_10 lc_trk_g0_2 (4 3) routing span4_vert_26 lc_trk_g0_2 (4 3) routing span4_vert_42 lc_trk_g0_2 (4 3) routing span4_vert_b_2 lc_trk_g0_2 (4 4) routing IO_B.logic_op_tnl_4 lc_trk_g0_4 (4 4) routing IO_B.logic_op_top_4 lc_trk_g0_4 (4 4) routing IO_L.logic_op_rgt_4 lc_trk_g0_4 (4 4) routing IO_L.logic_op_tnr_4 lc_trk_g0_4 (4 4) routing IO_R.logic_op_lft_4 lc_trk_g0_4 (4 4) routing IO_R.logic_op_tnl_4 lc_trk_g0_4 (4 4) routing IO_T.logic_op_bnl_4 lc_trk_g0_4 (4 4) routing IO_T.logic_op_bot_4 lc_trk_g0_4 (4 4) routing span12_horz_4 lc_trk_g0_4 (4 4) routing span12_vert_4 lc_trk_g0_4 (4 4) routing span4_horz_12 lc_trk_g0_4 (4 4) routing span4_horz_36 lc_trk_g0_4 (4 4) routing span4_horz_4 lc_trk_g0_4 (4 4) routing span4_horz_44 lc_trk_g0_4 (4 4) routing span4_horz_r_12 lc_trk_g0_4 (4 4) routing span4_vert_12 lc_trk_g0_4 (4 4) routing span4_vert_36 lc_trk_g0_4 (4 4) routing span4_vert_4 lc_trk_g0_4 (4 4) routing span4_vert_44 lc_trk_g0_4 (4 4) routing span4_vert_b_12 lc_trk_g0_4 (4 5) routing IO_B.logic_op_top_4 lc_trk_g0_4 (4 5) routing IO_L.logic_op_rgt_4 lc_trk_g0_4 (4 5) routing IO_R.logic_op_lft_4 lc_trk_g0_4 (4 5) routing IO_T.logic_op_bot_4 lc_trk_g0_4 (4 5) routing span12_horz_20 lc_trk_g0_4 (4 5) routing span12_horz_4 lc_trk_g0_4 (4 5) routing span12_vert_20 lc_trk_g0_4 (4 5) routing span12_vert_4 lc_trk_g0_4 (4 5) routing span4_horz_12 lc_trk_g0_4 (4 5) routing span4_horz_28 lc_trk_g0_4 (4 5) routing span4_horz_44 lc_trk_g0_4 (4 5) routing span4_horz_r_4 lc_trk_g0_4 (4 5) routing span4_vert_12 lc_trk_g0_4 (4 5) routing span4_vert_28 lc_trk_g0_4 (4 5) routing span4_vert_44 lc_trk_g0_4 (4 5) routing span4_vert_b_4 lc_trk_g0_4 (4 6) routing IO_B.logic_op_tnl_6 lc_trk_g0_6 (4 6) routing IO_B.logic_op_top_6 lc_trk_g0_6 (4 6) routing IO_L.logic_op_rgt_6 lc_trk_g0_6 (4 6) routing IO_L.logic_op_tnr_6 lc_trk_g0_6 (4 6) routing IO_R.logic_op_lft_6 lc_trk_g0_6 (4 6) routing IO_R.logic_op_tnl_6 lc_trk_g0_6 (4 6) routing IO_T.logic_op_bnl_6 lc_trk_g0_6 (4 6) routing IO_T.logic_op_bot_6 lc_trk_g0_6 (4 6) routing span12_horz_6 lc_trk_g0_6 (4 6) routing span12_vert_6 lc_trk_g0_6 (4 6) routing span4_horz_14 lc_trk_g0_6 (4 6) routing span4_horz_38 lc_trk_g0_6 (4 6) routing span4_horz_46 lc_trk_g0_6 (4 6) routing span4_horz_6 lc_trk_g0_6 (4 6) routing span4_horz_r_14 lc_trk_g0_6 (4 6) routing span4_vert_14 lc_trk_g0_6 (4 6) routing span4_vert_38 lc_trk_g0_6 (4 6) routing span4_vert_46 lc_trk_g0_6 (4 6) routing span4_vert_6 lc_trk_g0_6 (4 6) routing span4_vert_b_14 lc_trk_g0_6 (4 7) routing IO_B.logic_op_top_6 lc_trk_g0_6 (4 7) routing IO_L.logic_op_rgt_6 lc_trk_g0_6 (4 7) routing IO_R.logic_op_lft_6 lc_trk_g0_6 (4 7) routing IO_T.logic_op_bot_6 lc_trk_g0_6 (4 7) routing span12_horz_22 lc_trk_g0_6 (4 7) routing span12_horz_6 lc_trk_g0_6 (4 7) routing span12_vert_22 lc_trk_g0_6 (4 7) routing span12_vert_6 lc_trk_g0_6 (4 7) routing span4_horz_14 lc_trk_g0_6 (4 7) routing span4_horz_30 lc_trk_g0_6 (4 7) routing span4_horz_46 lc_trk_g0_6 (4 7) routing span4_horz_r_6 lc_trk_g0_6 (4 7) routing span4_vert_14 lc_trk_g0_6 (4 7) routing span4_vert_30 lc_trk_g0_6 (4 7) routing span4_vert_46 lc_trk_g0_6 (4 7) routing span4_vert_b_6 lc_trk_g0_6 (4 8) routing IO_B.logic_op_tnl_0 lc_trk_g1_0 (4 8) routing IO_B.logic_op_top_0 lc_trk_g1_0 (4 8) routing IO_L.logic_op_rgt_0 lc_trk_g1_0 (4 8) routing IO_L.logic_op_tnr_0 lc_trk_g1_0 (4 8) routing IO_R.logic_op_lft_0 lc_trk_g1_0 (4 8) routing IO_R.logic_op_tnl_0 lc_trk_g1_0 (4 8) routing IO_T.logic_op_bnl_0 lc_trk_g1_0 (4 8) routing IO_T.logic_op_bot_0 lc_trk_g1_0 (4 8) routing span12_horz_0 lc_trk_g1_0 (4 8) routing span12_vert_0 lc_trk_g1_0 (4 8) routing span4_horz_0 lc_trk_g1_0 (4 8) routing span4_horz_32 lc_trk_g1_0 (4 8) routing span4_horz_40 lc_trk_g1_0 (4 8) routing span4_horz_8 lc_trk_g1_0 (4 8) routing span4_horz_r_8 lc_trk_g1_0 (4 8) routing span4_vert_0 lc_trk_g1_0 (4 8) routing span4_vert_32 lc_trk_g1_0 (4 8) routing span4_vert_40 lc_trk_g1_0 (4 8) routing span4_vert_8 lc_trk_g1_0 (4 8) routing span4_vert_b_8 lc_trk_g1_0 (4 9) routing IO_B.logic_op_top_0 lc_trk_g1_0 (4 9) routing IO_L.logic_op_rgt_0 lc_trk_g1_0 (4 9) routing IO_R.logic_op_lft_0 lc_trk_g1_0 (4 9) routing IO_T.logic_op_bot_0 lc_trk_g1_0 (4 9) routing span12_horz_0 lc_trk_g1_0 (4 9) routing span12_horz_16 lc_trk_g1_0 (4 9) routing span12_vert_0 lc_trk_g1_0 (4 9) routing span12_vert_16 lc_trk_g1_0 (4 9) routing span4_horz_24 lc_trk_g1_0 (4 9) routing span4_horz_40 lc_trk_g1_0 (4 9) routing span4_horz_8 lc_trk_g1_0 (4 9) routing span4_horz_r_0 lc_trk_g1_0 (4 9) routing span4_vert_24 lc_trk_g1_0 (4 9) routing span4_vert_40 lc_trk_g1_0 (4 9) routing span4_vert_8 lc_trk_g1_0 (4 9) routing span4_vert_b_0 lc_trk_g1_0 (5 0) routing IO_B.logic_op_tnr_1 lc_trk_g0_1 (5 0) routing IO_L.logic_op_bnr_1 lc_trk_g0_1 (5 0) routing IO_R.logic_op_bnl_1 lc_trk_g0_1 (5 0) routing IO_T.logic_op_bnr_1 lc_trk_g0_1 (5 0) routing span12_horz_1 lc_trk_g0_1 (5 0) routing span12_vert_1 lc_trk_g0_1 (5 0) routing span4_horz_17 lc_trk_g0_1 (5 0) routing span4_horz_25 lc_trk_g0_1 (5 0) routing span4_horz_33 lc_trk_g0_1 (5 0) routing span4_horz_41 lc_trk_g0_1 (5 0) routing span4_horz_r_1 lc_trk_g0_1 (5 0) routing span4_horz_r_9 lc_trk_g0_1 (5 0) routing span4_vert_17 lc_trk_g0_1 (5 0) routing span4_vert_25 lc_trk_g0_1 (5 0) routing span4_vert_33 lc_trk_g0_1 (5 0) routing span4_vert_41 lc_trk_g0_1 (5 0) routing span4_vert_b_1 lc_trk_g0_1 (5 0) routing span4_vert_b_9 lc_trk_g0_1 (5 1) routing IO_B.logic_op_tnr_0 lc_trk_g0_0 (5 1) routing IO_L.logic_op_bnr_0 lc_trk_g0_0 (5 1) routing IO_R.logic_op_bnl_0 lc_trk_g0_0 (5 1) routing IO_T.logic_op_bnr_0 lc_trk_g0_0 (5 1) routing span12_horz_0 lc_trk_g0_0 (5 1) routing span12_vert_0 lc_trk_g0_0 (5 1) routing span4_horz_16 lc_trk_g0_0 (5 1) routing span4_horz_24 lc_trk_g0_0 (5 1) routing span4_horz_32 lc_trk_g0_0 (5 1) routing span4_horz_40 lc_trk_g0_0 (5 1) routing span4_horz_r_0 lc_trk_g0_0 (5 1) routing span4_horz_r_8 lc_trk_g0_0 (5 1) routing span4_vert_16 lc_trk_g0_0 (5 1) routing span4_vert_24 lc_trk_g0_0 (5 1) routing span4_vert_32 lc_trk_g0_0 (5 1) routing span4_vert_40 lc_trk_g0_0 (5 1) routing span4_vert_b_0 lc_trk_g0_0 (5 1) routing span4_vert_b_8 lc_trk_g0_0 (5 10) routing IO_B.logic_op_tnr_3 lc_trk_g1_3 (5 10) routing IO_L.logic_op_bnr_3 lc_trk_g1_3 (5 10) routing IO_R.logic_op_bnl_3 lc_trk_g1_3 (5 10) routing IO_T.logic_op_bnr_3 lc_trk_g1_3 (5 10) routing span12_horz_3 lc_trk_g1_3 (5 10) routing span12_vert_3 lc_trk_g1_3 (5 10) routing span4_horz_19 lc_trk_g1_3 (5 10) routing span4_horz_27 lc_trk_g1_3 (5 10) routing span4_horz_35 lc_trk_g1_3 (5 10) routing span4_horz_43 lc_trk_g1_3 (5 10) routing span4_horz_r_11 lc_trk_g1_3 (5 10) routing span4_horz_r_3 lc_trk_g1_3 (5 10) routing span4_vert_19 lc_trk_g1_3 (5 10) routing span4_vert_27 lc_trk_g1_3 (5 10) routing span4_vert_35 lc_trk_g1_3 (5 10) routing span4_vert_43 lc_trk_g1_3 (5 10) routing span4_vert_b_11 lc_trk_g1_3 (5 10) routing span4_vert_b_3 lc_trk_g1_3 (5 11) routing IO_B.logic_op_tnr_2 lc_trk_g1_2 (5 11) routing IO_L.logic_op_bnr_2 lc_trk_g1_2 (5 11) routing IO_R.logic_op_bnl_2 lc_trk_g1_2 (5 11) routing IO_T.logic_op_bnr_2 lc_trk_g1_2 (5 11) routing span12_horz_2 lc_trk_g1_2 (5 11) routing span12_vert_2 lc_trk_g1_2 (5 11) routing span4_horz_18 lc_trk_g1_2 (5 11) routing span4_horz_26 lc_trk_g1_2 (5 11) routing span4_horz_34 lc_trk_g1_2 (5 11) routing span4_horz_42 lc_trk_g1_2 (5 11) routing span4_horz_r_10 lc_trk_g1_2 (5 11) routing span4_horz_r_2 lc_trk_g1_2 (5 11) routing span4_vert_18 lc_trk_g1_2 (5 11) routing span4_vert_26 lc_trk_g1_2 (5 11) routing span4_vert_34 lc_trk_g1_2 (5 11) routing span4_vert_42 lc_trk_g1_2 (5 11) routing span4_vert_b_10 lc_trk_g1_2 (5 11) routing span4_vert_b_2 lc_trk_g1_2 (5 12) routing IO_B.logic_op_tnr_5 lc_trk_g1_5 (5 12) routing IO_L.logic_op_bnr_5 lc_trk_g1_5 (5 12) routing IO_R.logic_op_bnl_5 lc_trk_g1_5 (5 12) routing IO_T.logic_op_bnr_5 lc_trk_g1_5 (5 12) routing span12_horz_5 lc_trk_g1_5 (5 12) routing span12_vert_5 lc_trk_g1_5 (5 12) routing span4_horz_21 lc_trk_g1_5 (5 12) routing span4_horz_29 lc_trk_g1_5 (5 12) routing span4_horz_37 lc_trk_g1_5 (5 12) routing span4_horz_45 lc_trk_g1_5 (5 12) routing span4_horz_r_13 lc_trk_g1_5 (5 12) routing span4_horz_r_5 lc_trk_g1_5 (5 12) routing span4_vert_21 lc_trk_g1_5 (5 12) routing span4_vert_29 lc_trk_g1_5 (5 12) routing span4_vert_37 lc_trk_g1_5 (5 12) routing span4_vert_45 lc_trk_g1_5 (5 12) routing span4_vert_b_13 lc_trk_g1_5 (5 12) routing span4_vert_b_5 lc_trk_g1_5 (5 13) routing IO_B.logic_op_tnr_4 lc_trk_g1_4 (5 13) routing IO_L.logic_op_bnr_4 lc_trk_g1_4 (5 13) routing IO_R.logic_op_bnl_4 lc_trk_g1_4 (5 13) routing IO_T.logic_op_bnr_4 lc_trk_g1_4 (5 13) routing span12_horz_4 lc_trk_g1_4 (5 13) routing span12_vert_4 lc_trk_g1_4 (5 13) routing span4_horz_20 lc_trk_g1_4 (5 13) routing span4_horz_28 lc_trk_g1_4 (5 13) routing span4_horz_36 lc_trk_g1_4 (5 13) routing span4_horz_44 lc_trk_g1_4 (5 13) routing span4_horz_r_12 lc_trk_g1_4 (5 13) routing span4_horz_r_4 lc_trk_g1_4 (5 13) routing span4_vert_20 lc_trk_g1_4 (5 13) routing span4_vert_28 lc_trk_g1_4 (5 13) routing span4_vert_36 lc_trk_g1_4 (5 13) routing span4_vert_44 lc_trk_g1_4 (5 13) routing span4_vert_b_12 lc_trk_g1_4 (5 13) routing span4_vert_b_4 lc_trk_g1_4 (5 14) routing IO_B.logic_op_tnr_7 lc_trk_g1_7 (5 14) routing IO_L.logic_op_bnr_7 lc_trk_g1_7 (5 14) routing IO_R.logic_op_bnl_7 lc_trk_g1_7 (5 14) routing IO_T.logic_op_bnr_7 lc_trk_g1_7 (5 14) routing span12_horz_7 lc_trk_g1_7 (5 14) routing span12_vert_7 lc_trk_g1_7 (5 14) routing span4_horz_23 lc_trk_g1_7 (5 14) routing span4_horz_31 lc_trk_g1_7 (5 14) routing span4_horz_39 lc_trk_g1_7 (5 14) routing span4_horz_47 lc_trk_g1_7 (5 14) routing span4_horz_r_15 lc_trk_g1_7 (5 14) routing span4_horz_r_7 lc_trk_g1_7 (5 14) routing span4_vert_23 lc_trk_g1_7 (5 14) routing span4_vert_31 lc_trk_g1_7 (5 14) routing span4_vert_39 lc_trk_g1_7 (5 14) routing span4_vert_47 lc_trk_g1_7 (5 14) routing span4_vert_b_15 lc_trk_g1_7 (5 14) routing span4_vert_b_7 lc_trk_g1_7 (5 15) routing IO_B.logic_op_tnr_6 lc_trk_g1_6 (5 15) routing IO_L.logic_op_bnr_6 lc_trk_g1_6 (5 15) routing IO_R.logic_op_bnl_6 lc_trk_g1_6 (5 15) routing IO_T.logic_op_bnr_6 lc_trk_g1_6 (5 15) routing span12_horz_6 lc_trk_g1_6 (5 15) routing span12_vert_6 lc_trk_g1_6 (5 15) routing span4_horz_22 lc_trk_g1_6 (5 15) routing span4_horz_30 lc_trk_g1_6 (5 15) routing span4_horz_38 lc_trk_g1_6 (5 15) routing span4_horz_46 lc_trk_g1_6 (5 15) routing span4_horz_r_14 lc_trk_g1_6 (5 15) routing span4_horz_r_6 lc_trk_g1_6 (5 15) routing span4_vert_22 lc_trk_g1_6 (5 15) routing span4_vert_30 lc_trk_g1_6 (5 15) routing span4_vert_38 lc_trk_g1_6 (5 15) routing span4_vert_46 lc_trk_g1_6 (5 15) routing span4_vert_b_14 lc_trk_g1_6 (5 15) routing span4_vert_b_6 lc_trk_g1_6 (5 2) routing IO_B.logic_op_tnr_3 lc_trk_g0_3 (5 2) routing IO_L.logic_op_bnr_3 lc_trk_g0_3 (5 2) routing IO_R.logic_op_bnl_3 lc_trk_g0_3 (5 2) routing IO_T.logic_op_bnr_3 lc_trk_g0_3 (5 2) routing span12_horz_3 lc_trk_g0_3 (5 2) routing span12_vert_3 lc_trk_g0_3 (5 2) routing span4_horz_19 lc_trk_g0_3 (5 2) routing span4_horz_27 lc_trk_g0_3 (5 2) routing span4_horz_35 lc_trk_g0_3 (5 2) routing span4_horz_43 lc_trk_g0_3 (5 2) routing span4_horz_r_11 lc_trk_g0_3 (5 2) routing span4_horz_r_3 lc_trk_g0_3 (5 2) routing span4_vert_19 lc_trk_g0_3 (5 2) routing span4_vert_27 lc_trk_g0_3 (5 2) routing span4_vert_35 lc_trk_g0_3 (5 2) routing span4_vert_43 lc_trk_g0_3 (5 2) routing span4_vert_b_11 lc_trk_g0_3 (5 2) routing span4_vert_b_3 lc_trk_g0_3 (5 3) routing IO_B.logic_op_tnr_2 lc_trk_g0_2 (5 3) routing IO_L.logic_op_bnr_2 lc_trk_g0_2 (5 3) routing IO_R.logic_op_bnl_2 lc_trk_g0_2 (5 3) routing IO_T.logic_op_bnr_2 lc_trk_g0_2 (5 3) routing span12_horz_2 lc_trk_g0_2 (5 3) routing span12_vert_2 lc_trk_g0_2 (5 3) routing span4_horz_18 lc_trk_g0_2 (5 3) routing span4_horz_26 lc_trk_g0_2 (5 3) routing span4_horz_34 lc_trk_g0_2 (5 3) routing span4_horz_42 lc_trk_g0_2 (5 3) routing span4_horz_r_10 lc_trk_g0_2 (5 3) routing span4_horz_r_2 lc_trk_g0_2 (5 3) routing span4_vert_18 lc_trk_g0_2 (5 3) routing span4_vert_26 lc_trk_g0_2 (5 3) routing span4_vert_34 lc_trk_g0_2 (5 3) routing span4_vert_42 lc_trk_g0_2 (5 3) routing span4_vert_b_10 lc_trk_g0_2 (5 3) routing span4_vert_b_2 lc_trk_g0_2 (5 4) routing IO_B.logic_op_tnr_5 lc_trk_g0_5 (5 4) routing IO_L.logic_op_bnr_5 lc_trk_g0_5 (5 4) routing IO_R.logic_op_bnl_5 lc_trk_g0_5 (5 4) routing IO_T.logic_op_bnr_5 lc_trk_g0_5 (5 4) routing span12_horz_5 lc_trk_g0_5 (5 4) routing span12_vert_5 lc_trk_g0_5 (5 4) routing span4_horz_21 lc_trk_g0_5 (5 4) routing span4_horz_29 lc_trk_g0_5 (5 4) routing span4_horz_37 lc_trk_g0_5 (5 4) routing span4_horz_45 lc_trk_g0_5 (5 4) routing span4_horz_r_13 lc_trk_g0_5 (5 4) routing span4_horz_r_5 lc_trk_g0_5 (5 4) routing span4_vert_21 lc_trk_g0_5 (5 4) routing span4_vert_29 lc_trk_g0_5 (5 4) routing span4_vert_37 lc_trk_g0_5 (5 4) routing span4_vert_45 lc_trk_g0_5 (5 4) routing span4_vert_b_13 lc_trk_g0_5 (5 4) routing span4_vert_b_5 lc_trk_g0_5 (5 5) routing IO_B.logic_op_tnr_4 lc_trk_g0_4 (5 5) routing IO_L.logic_op_bnr_4 lc_trk_g0_4 (5 5) routing IO_R.logic_op_bnl_4 lc_trk_g0_4 (5 5) routing IO_T.logic_op_bnr_4 lc_trk_g0_4 (5 5) routing span12_horz_4 lc_trk_g0_4 (5 5) routing span12_vert_4 lc_trk_g0_4 (5 5) routing span4_horz_20 lc_trk_g0_4 (5 5) routing span4_horz_28 lc_trk_g0_4 (5 5) routing span4_horz_36 lc_trk_g0_4 (5 5) routing span4_horz_44 lc_trk_g0_4 (5 5) routing span4_horz_r_12 lc_trk_g0_4 (5 5) routing span4_horz_r_4 lc_trk_g0_4 (5 5) routing span4_vert_20 lc_trk_g0_4 (5 5) routing span4_vert_28 lc_trk_g0_4 (5 5) routing span4_vert_36 lc_trk_g0_4 (5 5) routing span4_vert_44 lc_trk_g0_4 (5 5) routing span4_vert_b_12 lc_trk_g0_4 (5 5) routing span4_vert_b_4 lc_trk_g0_4 (5 6) routing IO_B.logic_op_tnr_7 lc_trk_g0_7 (5 6) routing IO_L.logic_op_bnr_7 lc_trk_g0_7 (5 6) routing IO_R.logic_op_bnl_7 lc_trk_g0_7 (5 6) routing IO_T.logic_op_bnr_7 lc_trk_g0_7 (5 6) routing span12_horz_7 lc_trk_g0_7 (5 6) routing span12_vert_7 lc_trk_g0_7 (5 6) routing span4_horz_23 lc_trk_g0_7 (5 6) routing span4_horz_31 lc_trk_g0_7 (5 6) routing span4_horz_39 lc_trk_g0_7 (5 6) routing span4_horz_47 lc_trk_g0_7 (5 6) routing span4_horz_r_15 lc_trk_g0_7 (5 6) routing span4_horz_r_7 lc_trk_g0_7 (5 6) routing span4_vert_23 lc_trk_g0_7 (5 6) routing span4_vert_31 lc_trk_g0_7 (5 6) routing span4_vert_39 lc_trk_g0_7 (5 6) routing span4_vert_47 lc_trk_g0_7 (5 6) routing span4_vert_b_15 lc_trk_g0_7 (5 6) routing span4_vert_b_7 lc_trk_g0_7 (5 7) routing IO_B.logic_op_tnr_6 lc_trk_g0_6 (5 7) routing IO_L.logic_op_bnr_6 lc_trk_g0_6 (5 7) routing IO_R.logic_op_bnl_6 lc_trk_g0_6 (5 7) routing IO_T.logic_op_bnr_6 lc_trk_g0_6 (5 7) routing span12_horz_6 lc_trk_g0_6 (5 7) routing span12_vert_6 lc_trk_g0_6 (5 7) routing span4_horz_22 lc_trk_g0_6 (5 7) routing span4_horz_30 lc_trk_g0_6 (5 7) routing span4_horz_38 lc_trk_g0_6 (5 7) routing span4_horz_46 lc_trk_g0_6 (5 7) routing span4_horz_r_14 lc_trk_g0_6 (5 7) routing span4_horz_r_6 lc_trk_g0_6 (5 7) routing span4_vert_22 lc_trk_g0_6 (5 7) routing span4_vert_30 lc_trk_g0_6 (5 7) routing span4_vert_38 lc_trk_g0_6 (5 7) routing span4_vert_46 lc_trk_g0_6 (5 7) routing span4_vert_b_14 lc_trk_g0_6 (5 7) routing span4_vert_b_6 lc_trk_g0_6 (5 8) routing IO_B.logic_op_tnr_1 lc_trk_g1_1 (5 8) routing IO_L.logic_op_bnr_1 lc_trk_g1_1 (5 8) routing IO_R.logic_op_bnl_1 lc_trk_g1_1 (5 8) routing IO_T.logic_op_bnr_1 lc_trk_g1_1 (5 8) routing span12_horz_1 lc_trk_g1_1 (5 8) routing span12_vert_1 lc_trk_g1_1 (5 8) routing span4_horz_17 lc_trk_g1_1 (5 8) routing span4_horz_25 lc_trk_g1_1 (5 8) routing span4_horz_33 lc_trk_g1_1 (5 8) routing span4_horz_41 lc_trk_g1_1 (5 8) routing span4_horz_r_1 lc_trk_g1_1 (5 8) routing span4_horz_r_9 lc_trk_g1_1 (5 8) routing span4_vert_17 lc_trk_g1_1 (5 8) routing span4_vert_25 lc_trk_g1_1 (5 8) routing span4_vert_33 lc_trk_g1_1 (5 8) routing span4_vert_41 lc_trk_g1_1 (5 8) routing span4_vert_b_1 lc_trk_g1_1 (5 8) routing span4_vert_b_9 lc_trk_g1_1 (5 9) routing IO_B.logic_op_tnr_0 lc_trk_g1_0 (5 9) routing IO_L.logic_op_bnr_0 lc_trk_g1_0 (5 9) routing IO_R.logic_op_bnl_0 lc_trk_g1_0 (5 9) routing IO_T.logic_op_bnr_0 lc_trk_g1_0 (5 9) routing span12_horz_0 lc_trk_g1_0 (5 9) routing span12_vert_0 lc_trk_g1_0 (5 9) routing span4_horz_16 lc_trk_g1_0 (5 9) routing span4_horz_24 lc_trk_g1_0 (5 9) routing span4_horz_32 lc_trk_g1_0 (5 9) routing span4_horz_40 lc_trk_g1_0 (5 9) routing span4_horz_r_0 lc_trk_g1_0 (5 9) routing span4_horz_r_8 lc_trk_g1_0 (5 9) routing span4_vert_16 lc_trk_g1_0 (5 9) routing span4_vert_24 lc_trk_g1_0 (5 9) routing span4_vert_32 lc_trk_g1_0 (5 9) routing span4_vert_40 lc_trk_g1_0 (5 9) routing span4_vert_b_0 lc_trk_g1_0 (5 9) routing span4_vert_b_8 lc_trk_g1_0 (6 0) routing span12_horz_17 lc_trk_g0_1 (6 0) routing span12_horz_9 lc_trk_g0_1 (6 0) routing span12_vert_17 lc_trk_g0_1 (6 0) routing span12_vert_9 lc_trk_g0_1 (6 0) routing span4_horz_1 lc_trk_g0_1 (6 0) routing span4_horz_17 lc_trk_g0_1 (6 0) routing span4_horz_25 lc_trk_g0_1 (6 0) routing span4_horz_33 lc_trk_g0_1 (6 0) routing span4_horz_41 lc_trk_g0_1 (6 0) routing span4_horz_9 lc_trk_g0_1 (6 0) routing span4_vert_1 lc_trk_g0_1 (6 0) routing span4_vert_17 lc_trk_g0_1 (6 0) routing span4_vert_25 lc_trk_g0_1 (6 0) routing span4_vert_33 lc_trk_g0_1 (6 0) routing span4_vert_41 lc_trk_g0_1 (6 0) routing span4_vert_9 lc_trk_g0_1 (6 1) routing span12_horz_16 lc_trk_g0_0 (6 1) routing span12_horz_8 lc_trk_g0_0 (6 1) routing span12_vert_16 lc_trk_g0_0 (6 1) routing span12_vert_8 lc_trk_g0_0 (6 1) routing span4_horz_0 lc_trk_g0_0 (6 1) routing span4_horz_16 lc_trk_g0_0 (6 1) routing span4_horz_24 lc_trk_g0_0 (6 1) routing span4_horz_32 lc_trk_g0_0 (6 1) routing span4_horz_40 lc_trk_g0_0 (6 1) routing span4_horz_8 lc_trk_g0_0 (6 1) routing span4_vert_0 lc_trk_g0_0 (6 1) routing span4_vert_16 lc_trk_g0_0 (6 1) routing span4_vert_24 lc_trk_g0_0 (6 1) routing span4_vert_32 lc_trk_g0_0 (6 1) routing span4_vert_40 lc_trk_g0_0 (6 1) routing span4_vert_8 lc_trk_g0_0 (6 10) routing span12_horz_11 lc_trk_g1_3 (6 10) routing span12_horz_19 lc_trk_g1_3 (6 10) routing span12_vert_11 lc_trk_g1_3 (6 10) routing span12_vert_19 lc_trk_g1_3 (6 10) routing span4_horz_11 lc_trk_g1_3 (6 10) routing span4_horz_19 lc_trk_g1_3 (6 10) routing span4_horz_27 lc_trk_g1_3 (6 10) routing span4_horz_3 lc_trk_g1_3 (6 10) routing span4_horz_35 lc_trk_g1_3 (6 10) routing span4_horz_43 lc_trk_g1_3 (6 10) routing span4_vert_11 lc_trk_g1_3 (6 10) routing span4_vert_19 lc_trk_g1_3 (6 10) routing span4_vert_27 lc_trk_g1_3 (6 10) routing span4_vert_3 lc_trk_g1_3 (6 10) routing span4_vert_35 lc_trk_g1_3 (6 10) routing span4_vert_43 lc_trk_g1_3 (6 11) routing span12_horz_10 lc_trk_g1_2 (6 11) routing span12_horz_18 lc_trk_g1_2 (6 11) routing span12_vert_10 lc_trk_g1_2 (6 11) routing span12_vert_18 lc_trk_g1_2 (6 11) routing span4_horz_10 lc_trk_g1_2 (6 11) routing span4_horz_18 lc_trk_g1_2 (6 11) routing span4_horz_2 lc_trk_g1_2 (6 11) routing span4_horz_26 lc_trk_g1_2 (6 11) routing span4_horz_34 lc_trk_g1_2 (6 11) routing span4_horz_42 lc_trk_g1_2 (6 11) routing span4_vert_10 lc_trk_g1_2 (6 11) routing span4_vert_18 lc_trk_g1_2 (6 11) routing span4_vert_2 lc_trk_g1_2 (6 11) routing span4_vert_26 lc_trk_g1_2 (6 11) routing span4_vert_34 lc_trk_g1_2 (6 11) routing span4_vert_42 lc_trk_g1_2 (6 12) routing span12_horz_13 lc_trk_g1_5 (6 12) routing span12_horz_21 lc_trk_g1_5 (6 12) routing span12_vert_13 lc_trk_g1_5 (6 12) routing span12_vert_21 lc_trk_g1_5 (6 12) routing span4_horz_13 lc_trk_g1_5 (6 12) routing span4_horz_21 lc_trk_g1_5 (6 12) routing span4_horz_29 lc_trk_g1_5 (6 12) routing span4_horz_37 lc_trk_g1_5 (6 12) routing span4_horz_45 lc_trk_g1_5 (6 12) routing span4_horz_5 lc_trk_g1_5 (6 12) routing span4_vert_13 lc_trk_g1_5 (6 12) routing span4_vert_21 lc_trk_g1_5 (6 12) routing span4_vert_29 lc_trk_g1_5 (6 12) routing span4_vert_37 lc_trk_g1_5 (6 12) routing span4_vert_45 lc_trk_g1_5 (6 12) routing span4_vert_5 lc_trk_g1_5 (6 13) routing span12_horz_12 lc_trk_g1_4 (6 13) routing span12_horz_20 lc_trk_g1_4 (6 13) routing span12_vert_12 lc_trk_g1_4 (6 13) routing span12_vert_20 lc_trk_g1_4 (6 13) routing span4_horz_12 lc_trk_g1_4 (6 13) routing span4_horz_20 lc_trk_g1_4 (6 13) routing span4_horz_28 lc_trk_g1_4 (6 13) routing span4_horz_36 lc_trk_g1_4 (6 13) routing span4_horz_4 lc_trk_g1_4 (6 13) routing span4_horz_44 lc_trk_g1_4 (6 13) routing span4_vert_12 lc_trk_g1_4 (6 13) routing span4_vert_20 lc_trk_g1_4 (6 13) routing span4_vert_28 lc_trk_g1_4 (6 13) routing span4_vert_36 lc_trk_g1_4 (6 13) routing span4_vert_4 lc_trk_g1_4 (6 13) routing span4_vert_44 lc_trk_g1_4 (6 14) routing span12_horz_15 lc_trk_g1_7 (6 14) routing span12_horz_23 lc_trk_g1_7 (6 14) routing span12_vert_15 lc_trk_g1_7 (6 14) routing span12_vert_23 lc_trk_g1_7 (6 14) routing span4_horz_15 lc_trk_g1_7 (6 14) routing span4_horz_23 lc_trk_g1_7 (6 14) routing span4_horz_31 lc_trk_g1_7 (6 14) routing span4_horz_39 lc_trk_g1_7 (6 14) routing span4_horz_47 lc_trk_g1_7 (6 14) routing span4_horz_7 lc_trk_g1_7 (6 14) routing span4_vert_15 lc_trk_g1_7 (6 14) routing span4_vert_23 lc_trk_g1_7 (6 14) routing span4_vert_31 lc_trk_g1_7 (6 14) routing span4_vert_39 lc_trk_g1_7 (6 14) routing span4_vert_47 lc_trk_g1_7 (6 14) routing span4_vert_7 lc_trk_g1_7 (6 15) routing span12_horz_14 lc_trk_g1_6 (6 15) routing span12_horz_22 lc_trk_g1_6 (6 15) routing span12_vert_14 lc_trk_g1_6 (6 15) routing span12_vert_22 lc_trk_g1_6 (6 15) routing span4_horz_14 lc_trk_g1_6 (6 15) routing span4_horz_22 lc_trk_g1_6 (6 15) routing span4_horz_30 lc_trk_g1_6 (6 15) routing span4_horz_38 lc_trk_g1_6 (6 15) routing span4_horz_46 lc_trk_g1_6 (6 15) routing span4_horz_6 lc_trk_g1_6 (6 15) routing span4_vert_14 lc_trk_g1_6 (6 15) routing span4_vert_22 lc_trk_g1_6 (6 15) routing span4_vert_30 lc_trk_g1_6 (6 15) routing span4_vert_38 lc_trk_g1_6 (6 15) routing span4_vert_46 lc_trk_g1_6 (6 15) routing span4_vert_6 lc_trk_g1_6 (6 2) routing span12_horz_11 lc_trk_g0_3 (6 2) routing span12_horz_19 lc_trk_g0_3 (6 2) routing span12_vert_11 lc_trk_g0_3 (6 2) routing span12_vert_19 lc_trk_g0_3 (6 2) routing span4_horz_11 lc_trk_g0_3 (6 2) routing span4_horz_19 lc_trk_g0_3 (6 2) routing span4_horz_27 lc_trk_g0_3 (6 2) routing span4_horz_3 lc_trk_g0_3 (6 2) routing span4_horz_35 lc_trk_g0_3 (6 2) routing span4_horz_43 lc_trk_g0_3 (6 2) routing span4_vert_11 lc_trk_g0_3 (6 2) routing span4_vert_19 lc_trk_g0_3 (6 2) routing span4_vert_27 lc_trk_g0_3 (6 2) routing span4_vert_3 lc_trk_g0_3 (6 2) routing span4_vert_35 lc_trk_g0_3 (6 2) routing span4_vert_43 lc_trk_g0_3 (6 3) routing span12_horz_10 lc_trk_g0_2 (6 3) routing span12_horz_18 lc_trk_g0_2 (6 3) routing span12_vert_10 lc_trk_g0_2 (6 3) routing span12_vert_18 lc_trk_g0_2 (6 3) routing span4_horz_10 lc_trk_g0_2 (6 3) routing span4_horz_18 lc_trk_g0_2 (6 3) routing span4_horz_2 lc_trk_g0_2 (6 3) routing span4_horz_26 lc_trk_g0_2 (6 3) routing span4_horz_34 lc_trk_g0_2 (6 3) routing span4_horz_42 lc_trk_g0_2 (6 3) routing span4_vert_10 lc_trk_g0_2 (6 3) routing span4_vert_18 lc_trk_g0_2 (6 3) routing span4_vert_2 lc_trk_g0_2 (6 3) routing span4_vert_26 lc_trk_g0_2 (6 3) routing span4_vert_34 lc_trk_g0_2 (6 3) routing span4_vert_42 lc_trk_g0_2 (6 4) routing span12_horz_13 lc_trk_g0_5 (6 4) routing span12_horz_21 lc_trk_g0_5 (6 4) routing span12_vert_13 lc_trk_g0_5 (6 4) routing span12_vert_21 lc_trk_g0_5 (6 4) routing span4_horz_13 lc_trk_g0_5 (6 4) routing span4_horz_21 lc_trk_g0_5 (6 4) routing span4_horz_29 lc_trk_g0_5 (6 4) routing span4_horz_37 lc_trk_g0_5 (6 4) routing span4_horz_45 lc_trk_g0_5 (6 4) routing span4_horz_5 lc_trk_g0_5 (6 4) routing span4_vert_13 lc_trk_g0_5 (6 4) routing span4_vert_21 lc_trk_g0_5 (6 4) routing span4_vert_29 lc_trk_g0_5 (6 4) routing span4_vert_37 lc_trk_g0_5 (6 4) routing span4_vert_45 lc_trk_g0_5 (6 4) routing span4_vert_5 lc_trk_g0_5 (6 5) routing span12_horz_12 lc_trk_g0_4 (6 5) routing span12_horz_20 lc_trk_g0_4 (6 5) routing span12_vert_12 lc_trk_g0_4 (6 5) routing span12_vert_20 lc_trk_g0_4 (6 5) routing span4_horz_12 lc_trk_g0_4 (6 5) routing span4_horz_20 lc_trk_g0_4 (6 5) routing span4_horz_28 lc_trk_g0_4 (6 5) routing span4_horz_36 lc_trk_g0_4 (6 5) routing span4_horz_4 lc_trk_g0_4 (6 5) routing span4_horz_44 lc_trk_g0_4 (6 5) routing span4_vert_12 lc_trk_g0_4 (6 5) routing span4_vert_20 lc_trk_g0_4 (6 5) routing span4_vert_28 lc_trk_g0_4 (6 5) routing span4_vert_36 lc_trk_g0_4 (6 5) routing span4_vert_4 lc_trk_g0_4 (6 5) routing span4_vert_44 lc_trk_g0_4 (6 6) routing span12_horz_15 lc_trk_g0_7 (6 6) routing span12_horz_23 lc_trk_g0_7 (6 6) routing span12_vert_15 lc_trk_g0_7 (6 6) routing span12_vert_23 lc_trk_g0_7 (6 6) routing span4_horz_15 lc_trk_g0_7 (6 6) routing span4_horz_23 lc_trk_g0_7 (6 6) routing span4_horz_31 lc_trk_g0_7 (6 6) routing span4_horz_39 lc_trk_g0_7 (6 6) routing span4_horz_47 lc_trk_g0_7 (6 6) routing span4_horz_7 lc_trk_g0_7 (6 6) routing span4_vert_15 lc_trk_g0_7 (6 6) routing span4_vert_23 lc_trk_g0_7 (6 6) routing span4_vert_31 lc_trk_g0_7 (6 6) routing span4_vert_39 lc_trk_g0_7 (6 6) routing span4_vert_47 lc_trk_g0_7 (6 6) routing span4_vert_7 lc_trk_g0_7 (6 7) routing span12_horz_14 lc_trk_g0_6 (6 7) routing span12_horz_22 lc_trk_g0_6 (6 7) routing span12_vert_14 lc_trk_g0_6 (6 7) routing span12_vert_22 lc_trk_g0_6 (6 7) routing span4_horz_14 lc_trk_g0_6 (6 7) routing span4_horz_22 lc_trk_g0_6 (6 7) routing span4_horz_30 lc_trk_g0_6 (6 7) routing span4_horz_38 lc_trk_g0_6 (6 7) routing span4_horz_46 lc_trk_g0_6 (6 7) routing span4_horz_6 lc_trk_g0_6 (6 7) routing span4_vert_14 lc_trk_g0_6 (6 7) routing span4_vert_22 lc_trk_g0_6 (6 7) routing span4_vert_30 lc_trk_g0_6 (6 7) routing span4_vert_38 lc_trk_g0_6 (6 7) routing span4_vert_46 lc_trk_g0_6 (6 7) routing span4_vert_6 lc_trk_g0_6 (6 8) routing span12_horz_17 lc_trk_g1_1 (6 8) routing span12_horz_9 lc_trk_g1_1 (6 8) routing span12_vert_17 lc_trk_g1_1 (6 8) routing span12_vert_9 lc_trk_g1_1 (6 8) routing span4_horz_1 lc_trk_g1_1 (6 8) routing span4_horz_17 lc_trk_g1_1 (6 8) routing span4_horz_25 lc_trk_g1_1 (6 8) routing span4_horz_33 lc_trk_g1_1 (6 8) routing span4_horz_41 lc_trk_g1_1 (6 8) routing span4_horz_9 lc_trk_g1_1 (6 8) routing span4_vert_1 lc_trk_g1_1 (6 8) routing span4_vert_17 lc_trk_g1_1 (6 8) routing span4_vert_25 lc_trk_g1_1 (6 8) routing span4_vert_33 lc_trk_g1_1 (6 8) routing span4_vert_41 lc_trk_g1_1 (6 8) routing span4_vert_9 lc_trk_g1_1 (6 9) routing span12_horz_16 lc_trk_g1_0 (6 9) routing span12_horz_8 lc_trk_g1_0 (6 9) routing span12_vert_16 lc_trk_g1_0 (6 9) routing span12_vert_8 lc_trk_g1_0 (6 9) routing span4_horz_0 lc_trk_g1_0 (6 9) routing span4_horz_16 lc_trk_g1_0 (6 9) routing span4_horz_24 lc_trk_g1_0 (6 9) routing span4_horz_32 lc_trk_g1_0 (6 9) routing span4_horz_40 lc_trk_g1_0 (6 9) routing span4_horz_8 lc_trk_g1_0 (6 9) routing span4_vert_0 lc_trk_g1_0 (6 9) routing span4_vert_16 lc_trk_g1_0 (6 9) routing span4_vert_24 lc_trk_g1_0 (6 9) routing span4_vert_32 lc_trk_g1_0 (6 9) routing span4_vert_40 lc_trk_g1_0 (6 9) routing span4_vert_8 lc_trk_g1_0 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_bnl_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_bnr_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_bot_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_lft_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_rgt_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_tnl_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_tnr_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => logic_op_top_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_horz_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_horz_17 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_horz_9 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_vert_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_vert_17 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span12_vert_9 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_17 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_25 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_33 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_41 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_9 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_r_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_horz_r_9 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_17 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_25 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_33 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_41 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_9 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_b_1 lc_trk_g0_1 (7 0) Enable bit of Mux _local_links/g0_mux_1 => span4_vert_b_9 lc_trk_g0_1 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_bnl_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_bnr_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_bot_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_lft_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_rgt_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_tnl_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_tnr_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => logic_op_top_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_horz_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_horz_16 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_horz_8 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_vert_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_vert_16 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span12_vert_8 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_16 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_24 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_32 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_40 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_8 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_r_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_horz_r_8 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_16 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_24 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_32 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_40 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_8 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_b_0 lc_trk_g0_0 (7 1) Enable bit of Mux _local_links/g0_mux_0 => span4_vert_b_8 lc_trk_g0_0 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_bnl_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_bnr_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_bot_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_lft_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_rgt_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_tnl_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_tnr_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => logic_op_top_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_horz_11 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_horz_19 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_horz_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_vert_11 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_vert_19 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span12_vert_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_11 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_19 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_27 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_35 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_43 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_r_11 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_horz_r_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_11 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_19 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_27 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_3 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_35 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_43 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_b_11 lc_trk_g1_3 (7 10) Enable bit of Mux _local_links/g1_mux_3 => span4_vert_b_3 lc_trk_g1_3 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_bnl_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_bnr_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_bot_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_lft_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_rgt_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_tnl_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_tnr_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => logic_op_top_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_horz_10 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_horz_18 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_horz_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_vert_10 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_vert_18 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span12_vert_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_10 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_18 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_26 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_34 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_42 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_r_10 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_horz_r_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_10 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_18 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_2 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_26 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_34 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_42 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_b_10 lc_trk_g1_2 (7 11) Enable bit of Mux _local_links/g1_mux_2 => span4_vert_b_2 lc_trk_g1_2 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_bnl_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_bnr_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_bot_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_lft_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_rgt_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_tnl_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_tnr_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => logic_op_top_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_horz_13 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_horz_21 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_horz_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_vert_13 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_vert_21 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span12_vert_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_13 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_21 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_29 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_37 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_45 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_r_13 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_horz_r_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_13 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_21 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_29 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_37 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_45 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_5 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_b_13 lc_trk_g1_5 (7 12) Enable bit of Mux _local_links/g1_mux_5 => span4_vert_b_5 lc_trk_g1_5 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_bnl_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_bnr_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_bot_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_lft_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_rgt_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_tnl_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_tnr_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => logic_op_top_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_horz_12 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_horz_20 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_horz_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_vert_12 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_vert_20 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span12_vert_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_12 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_20 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_28 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_36 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_44 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_r_12 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_horz_r_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_12 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_20 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_28 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_36 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_4 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_44 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_b_12 lc_trk_g1_4 (7 13) Enable bit of Mux _local_links/g1_mux_4 => span4_vert_b_4 lc_trk_g1_4 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_bnl_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_bnr_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_bot_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_lft_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_rgt_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_tnl_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_tnr_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => logic_op_top_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_horz_15 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_horz_23 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_horz_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_vert_15 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_vert_23 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span12_vert_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_15 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_23 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_31 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_39 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_47 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_r_15 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_horz_r_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_15 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_23 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_31 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_39 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_47 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_7 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_b_15 lc_trk_g1_7 (7 14) Enable bit of Mux _local_links/g1_mux_7 => span4_vert_b_7 lc_trk_g1_7 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_bnl_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_bnr_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_bot_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_lft_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_rgt_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_tnl_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_tnr_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => logic_op_top_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_horz_14 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_horz_22 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_horz_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_vert_14 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_vert_22 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span12_vert_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_14 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_22 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_30 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_38 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_46 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_r_14 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_horz_r_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_14 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_22 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_30 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_38 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_46 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_6 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_b_14 lc_trk_g1_6 (7 15) Enable bit of Mux _local_links/g1_mux_6 => span4_vert_b_6 lc_trk_g1_6 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_bnl_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_bnr_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_bot_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_lft_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_rgt_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_tnl_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_tnr_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => logic_op_top_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_horz_11 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_horz_19 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_horz_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_vert_11 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_vert_19 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span12_vert_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_11 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_19 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_27 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_35 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_43 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_r_11 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_horz_r_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_11 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_19 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_27 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_3 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_35 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_43 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_b_11 lc_trk_g0_3 (7 2) Enable bit of Mux _local_links/g0_mux_3 => span4_vert_b_3 lc_trk_g0_3 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_bnl_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_bnr_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_bot_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_lft_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_rgt_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_tnl_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_tnr_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => logic_op_top_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_horz_10 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_horz_18 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_horz_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_vert_10 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_vert_18 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span12_vert_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_10 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_18 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_26 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_34 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_42 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_r_10 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_horz_r_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_10 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_18 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_2 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_26 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_34 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_42 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_b_10 lc_trk_g0_2 (7 3) Enable bit of Mux _local_links/g0_mux_2 => span4_vert_b_2 lc_trk_g0_2 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_bnl_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_bnr_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_bot_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_lft_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_rgt_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_tnl_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_tnr_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => logic_op_top_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_horz_13 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_horz_21 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_horz_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_vert_13 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_vert_21 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span12_vert_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_13 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_21 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_29 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_37 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_45 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_r_13 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_horz_r_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_13 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_21 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_29 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_37 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_45 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_5 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_b_13 lc_trk_g0_5 (7 4) Enable bit of Mux _local_links/g0_mux_5 => span4_vert_b_5 lc_trk_g0_5 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_bnl_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_bnr_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_bot_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_lft_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_rgt_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_tnl_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_tnr_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => logic_op_top_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_horz_12 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_horz_20 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_horz_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_vert_12 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_vert_20 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span12_vert_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_12 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_20 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_28 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_36 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_44 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_r_12 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_horz_r_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_12 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_20 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_28 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_36 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_4 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_44 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_b_12 lc_trk_g0_4 (7 5) Enable bit of Mux _local_links/g0_mux_4 => span4_vert_b_4 lc_trk_g0_4 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_bnl_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_bnr_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_bot_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_lft_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_rgt_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_tnl_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_tnr_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => logic_op_top_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_horz_15 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_horz_23 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_horz_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_vert_15 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_vert_23 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span12_vert_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_15 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_23 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_31 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_39 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_47 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_r_15 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_horz_r_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_15 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_23 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_31 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_39 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_47 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_7 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_b_15 lc_trk_g0_7 (7 6) Enable bit of Mux _local_links/g0_mux_7 => span4_vert_b_7 lc_trk_g0_7 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_bnl_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_bnr_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_bot_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_lft_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_rgt_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_tnl_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_tnr_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => logic_op_top_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_horz_14 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_horz_22 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_horz_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_vert_14 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_vert_22 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span12_vert_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_14 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_22 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_30 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_38 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_46 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_r_14 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_horz_r_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_14 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_22 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_30 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_38 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_46 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_6 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_b_14 lc_trk_g0_6 (7 7) Enable bit of Mux _local_links/g0_mux_6 => span4_vert_b_6 lc_trk_g0_6 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_bnl_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_bnr_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_bot_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_lft_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_rgt_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_tnl_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_tnr_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => logic_op_top_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_horz_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_horz_17 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_horz_9 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_vert_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_vert_17 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span12_vert_9 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_17 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_25 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_33 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_41 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_9 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_r_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_horz_r_9 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_17 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_25 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_33 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_41 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_9 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_b_1 lc_trk_g1_1 (7 8) Enable bit of Mux _local_links/g1_mux_1 => span4_vert_b_9 lc_trk_g1_1 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_bnl_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_bnr_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_bot_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_lft_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_rgt_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_tnl_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_tnr_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => logic_op_top_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_horz_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_horz_16 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_horz_8 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_vert_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_vert_16 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span12_vert_8 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_16 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_24 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_32 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_40 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_8 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_r_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_horz_r_8 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_16 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_24 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_32 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_40 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_8 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_b_0 lc_trk_g1_0 (7 9) Enable bit of Mux _local_links/g1_mux_0 => span4_vert_b_8 lc_trk_g1_0 (8 0) routing IO_B.logic_op_tnl_1 lc_trk_g0_1 (8 0) routing IO_B.logic_op_top_1 lc_trk_g0_1 (8 0) routing IO_L.logic_op_rgt_1 lc_trk_g0_1 (8 0) routing IO_L.logic_op_tnr_1 lc_trk_g0_1 (8 0) routing IO_R.logic_op_lft_1 lc_trk_g0_1 (8 0) routing IO_R.logic_op_tnl_1 lc_trk_g0_1 (8 0) routing IO_T.logic_op_bnl_1 lc_trk_g0_1 (8 0) routing IO_T.logic_op_bot_1 lc_trk_g0_1 (8 0) routing span12_horz_1 lc_trk_g0_1 (8 0) routing span12_vert_1 lc_trk_g0_1 (8 0) routing span4_horz_1 lc_trk_g0_1 (8 0) routing span4_horz_33 lc_trk_g0_1 (8 0) routing span4_horz_41 lc_trk_g0_1 (8 0) routing span4_horz_9 lc_trk_g0_1 (8 0) routing span4_horz_r_9 lc_trk_g0_1 (8 0) routing span4_vert_1 lc_trk_g0_1 (8 0) routing span4_vert_33 lc_trk_g0_1 (8 0) routing span4_vert_41 lc_trk_g0_1 (8 0) routing span4_vert_9 lc_trk_g0_1 (8 0) routing span4_vert_b_9 lc_trk_g0_1 (8 1) routing IO_B.logic_op_top_1 lc_trk_g0_1 (8 1) routing IO_L.logic_op_rgt_1 lc_trk_g0_1 (8 1) routing IO_R.logic_op_lft_1 lc_trk_g0_1 (8 1) routing IO_T.logic_op_bot_1 lc_trk_g0_1 (8 1) routing span12_horz_1 lc_trk_g0_1 (8 1) routing span12_horz_17 lc_trk_g0_1 (8 1) routing span12_vert_1 lc_trk_g0_1 (8 1) routing span12_vert_17 lc_trk_g0_1 (8 1) routing span4_horz_25 lc_trk_g0_1 (8 1) routing span4_horz_41 lc_trk_g0_1 (8 1) routing span4_horz_9 lc_trk_g0_1 (8 1) routing span4_horz_r_1 lc_trk_g0_1 (8 1) routing span4_vert_25 lc_trk_g0_1 (8 1) routing span4_vert_41 lc_trk_g0_1 (8 1) routing span4_vert_9 lc_trk_g0_1 (8 1) routing span4_vert_b_1 lc_trk_g0_1 (8 10) routing IO_B.logic_op_tnl_3 lc_trk_g1_3 (8 10) routing IO_B.logic_op_top_3 lc_trk_g1_3 (8 10) routing IO_L.logic_op_rgt_3 lc_trk_g1_3 (8 10) routing IO_L.logic_op_tnr_3 lc_trk_g1_3 (8 10) routing IO_R.logic_op_lft_3 lc_trk_g1_3 (8 10) routing IO_R.logic_op_tnl_3 lc_trk_g1_3 (8 10) routing IO_T.logic_op_bnl_3 lc_trk_g1_3 (8 10) routing IO_T.logic_op_bot_3 lc_trk_g1_3 (8 10) routing span12_horz_3 lc_trk_g1_3 (8 10) routing span12_vert_3 lc_trk_g1_3 (8 10) routing span4_horz_11 lc_trk_g1_3 (8 10) routing span4_horz_3 lc_trk_g1_3 (8 10) routing span4_horz_35 lc_trk_g1_3 (8 10) routing span4_horz_43 lc_trk_g1_3 (8 10) routing span4_horz_r_11 lc_trk_g1_3 (8 10) routing span4_vert_11 lc_trk_g1_3 (8 10) routing span4_vert_3 lc_trk_g1_3 (8 10) routing span4_vert_35 lc_trk_g1_3 (8 10) routing span4_vert_43 lc_trk_g1_3 (8 10) routing span4_vert_b_11 lc_trk_g1_3 (8 11) routing IO_B.logic_op_top_3 lc_trk_g1_3 (8 11) routing IO_L.logic_op_rgt_3 lc_trk_g1_3 (8 11) routing IO_R.logic_op_lft_3 lc_trk_g1_3 (8 11) routing IO_T.logic_op_bot_3 lc_trk_g1_3 (8 11) routing span12_horz_19 lc_trk_g1_3 (8 11) routing span12_horz_3 lc_trk_g1_3 (8 11) routing span12_vert_19 lc_trk_g1_3 (8 11) routing span12_vert_3 lc_trk_g1_3 (8 11) routing span4_horz_11 lc_trk_g1_3 (8 11) routing span4_horz_27 lc_trk_g1_3 (8 11) routing span4_horz_43 lc_trk_g1_3 (8 11) routing span4_horz_r_3 lc_trk_g1_3 (8 11) routing span4_vert_11 lc_trk_g1_3 (8 11) routing span4_vert_27 lc_trk_g1_3 (8 11) routing span4_vert_43 lc_trk_g1_3 (8 11) routing span4_vert_b_3 lc_trk_g1_3 (8 12) routing IO_B.logic_op_tnl_5 lc_trk_g1_5 (8 12) routing IO_B.logic_op_top_5 lc_trk_g1_5 (8 12) routing IO_L.logic_op_rgt_5 lc_trk_g1_5 (8 12) routing IO_L.logic_op_tnr_5 lc_trk_g1_5 (8 12) routing IO_R.logic_op_lft_5 lc_trk_g1_5 (8 12) routing IO_R.logic_op_tnl_5 lc_trk_g1_5 (8 12) routing IO_T.logic_op_bnl_5 lc_trk_g1_5 (8 12) routing IO_T.logic_op_bot_5 lc_trk_g1_5 (8 12) routing span12_horz_5 lc_trk_g1_5 (8 12) routing span12_vert_5 lc_trk_g1_5 (8 12) routing span4_horz_13 lc_trk_g1_5 (8 12) routing span4_horz_37 lc_trk_g1_5 (8 12) routing span4_horz_45 lc_trk_g1_5 (8 12) routing span4_horz_5 lc_trk_g1_5 (8 12) routing span4_horz_r_13 lc_trk_g1_5 (8 12) routing span4_vert_13 lc_trk_g1_5 (8 12) routing span4_vert_37 lc_trk_g1_5 (8 12) routing span4_vert_45 lc_trk_g1_5 (8 12) routing span4_vert_5 lc_trk_g1_5 (8 12) routing span4_vert_b_13 lc_trk_g1_5 (8 13) routing IO_B.logic_op_top_5 lc_trk_g1_5 (8 13) routing IO_L.logic_op_rgt_5 lc_trk_g1_5 (8 13) routing IO_R.logic_op_lft_5 lc_trk_g1_5 (8 13) routing IO_T.logic_op_bot_5 lc_trk_g1_5 (8 13) routing span12_horz_21 lc_trk_g1_5 (8 13) routing span12_horz_5 lc_trk_g1_5 (8 13) routing span12_vert_21 lc_trk_g1_5 (8 13) routing span12_vert_5 lc_trk_g1_5 (8 13) routing span4_horz_13 lc_trk_g1_5 (8 13) routing span4_horz_29 lc_trk_g1_5 (8 13) routing span4_horz_45 lc_trk_g1_5 (8 13) routing span4_horz_r_5 lc_trk_g1_5 (8 13) routing span4_vert_13 lc_trk_g1_5 (8 13) routing span4_vert_29 lc_trk_g1_5 (8 13) routing span4_vert_45 lc_trk_g1_5 (8 13) routing span4_vert_b_5 lc_trk_g1_5 (8 14) routing IO_B.logic_op_tnl_7 lc_trk_g1_7 (8 14) routing IO_B.logic_op_top_7 lc_trk_g1_7 (8 14) routing IO_L.logic_op_rgt_7 lc_trk_g1_7 (8 14) routing IO_L.logic_op_tnr_7 lc_trk_g1_7 (8 14) routing IO_R.logic_op_lft_7 lc_trk_g1_7 (8 14) routing IO_R.logic_op_tnl_7 lc_trk_g1_7 (8 14) routing IO_T.logic_op_bnl_7 lc_trk_g1_7 (8 14) routing IO_T.logic_op_bot_7 lc_trk_g1_7 (8 14) routing span12_horz_7 lc_trk_g1_7 (8 14) routing span12_vert_7 lc_trk_g1_7 (8 14) routing span4_horz_15 lc_trk_g1_7 (8 14) routing span4_horz_39 lc_trk_g1_7 (8 14) routing span4_horz_47 lc_trk_g1_7 (8 14) routing span4_horz_7 lc_trk_g1_7 (8 14) routing span4_horz_r_15 lc_trk_g1_7 (8 14) routing span4_vert_15 lc_trk_g1_7 (8 14) routing span4_vert_39 lc_trk_g1_7 (8 14) routing span4_vert_47 lc_trk_g1_7 (8 14) routing span4_vert_7 lc_trk_g1_7 (8 14) routing span4_vert_b_15 lc_trk_g1_7 (8 15) routing IO_B.logic_op_top_7 lc_trk_g1_7 (8 15) routing IO_L.logic_op_rgt_7 lc_trk_g1_7 (8 15) routing IO_R.logic_op_lft_7 lc_trk_g1_7 (8 15) routing IO_T.logic_op_bot_7 lc_trk_g1_7 (8 15) routing span12_horz_23 lc_trk_g1_7 (8 15) routing span12_horz_7 lc_trk_g1_7 (8 15) routing span12_vert_23 lc_trk_g1_7 (8 15) routing span12_vert_7 lc_trk_g1_7 (8 15) routing span4_horz_15 lc_trk_g1_7 (8 15) routing span4_horz_31 lc_trk_g1_7 (8 15) routing span4_horz_47 lc_trk_g1_7 (8 15) routing span4_horz_r_7 lc_trk_g1_7 (8 15) routing span4_vert_15 lc_trk_g1_7 (8 15) routing span4_vert_31 lc_trk_g1_7 (8 15) routing span4_vert_47 lc_trk_g1_7 (8 15) routing span4_vert_b_7 lc_trk_g1_7 (8 2) routing IO_B.logic_op_tnl_3 lc_trk_g0_3 (8 2) routing IO_B.logic_op_top_3 lc_trk_g0_3 (8 2) routing IO_L.logic_op_rgt_3 lc_trk_g0_3 (8 2) routing IO_L.logic_op_tnr_3 lc_trk_g0_3 (8 2) routing IO_R.logic_op_lft_3 lc_trk_g0_3 (8 2) routing IO_R.logic_op_tnl_3 lc_trk_g0_3 (8 2) routing IO_T.logic_op_bnl_3 lc_trk_g0_3 (8 2) routing IO_T.logic_op_bot_3 lc_trk_g0_3 (8 2) routing span12_horz_3 lc_trk_g0_3 (8 2) routing span12_vert_3 lc_trk_g0_3 (8 2) routing span4_horz_11 lc_trk_g0_3 (8 2) routing span4_horz_3 lc_trk_g0_3 (8 2) routing span4_horz_35 lc_trk_g0_3 (8 2) routing span4_horz_43 lc_trk_g0_3 (8 2) routing span4_horz_r_11 lc_trk_g0_3 (8 2) routing span4_vert_11 lc_trk_g0_3 (8 2) routing span4_vert_3 lc_trk_g0_3 (8 2) routing span4_vert_35 lc_trk_g0_3 (8 2) routing span4_vert_43 lc_trk_g0_3 (8 2) routing span4_vert_b_11 lc_trk_g0_3 (8 3) routing IO_B.logic_op_top_3 lc_trk_g0_3 (8 3) routing IO_L.logic_op_rgt_3 lc_trk_g0_3 (8 3) routing IO_R.logic_op_lft_3 lc_trk_g0_3 (8 3) routing IO_T.logic_op_bot_3 lc_trk_g0_3 (8 3) routing span12_horz_19 lc_trk_g0_3 (8 3) routing span12_horz_3 lc_trk_g0_3 (8 3) routing span12_vert_19 lc_trk_g0_3 (8 3) routing span12_vert_3 lc_trk_g0_3 (8 3) routing span4_horz_11 lc_trk_g0_3 (8 3) routing span4_horz_27 lc_trk_g0_3 (8 3) routing span4_horz_43 lc_trk_g0_3 (8 3) routing span4_horz_r_3 lc_trk_g0_3 (8 3) routing span4_vert_11 lc_trk_g0_3 (8 3) routing span4_vert_27 lc_trk_g0_3 (8 3) routing span4_vert_43 lc_trk_g0_3 (8 3) routing span4_vert_b_3 lc_trk_g0_3 (8 4) routing IO_B.logic_op_tnl_5 lc_trk_g0_5 (8 4) routing IO_B.logic_op_top_5 lc_trk_g0_5 (8 4) routing IO_L.logic_op_rgt_5 lc_trk_g0_5 (8 4) routing IO_L.logic_op_tnr_5 lc_trk_g0_5 (8 4) routing IO_R.logic_op_lft_5 lc_trk_g0_5 (8 4) routing IO_R.logic_op_tnl_5 lc_trk_g0_5 (8 4) routing IO_T.logic_op_bnl_5 lc_trk_g0_5 (8 4) routing IO_T.logic_op_bot_5 lc_trk_g0_5 (8 4) routing span12_horz_5 lc_trk_g0_5 (8 4) routing span12_vert_5 lc_trk_g0_5 (8 4) routing span4_horz_13 lc_trk_g0_5 (8 4) routing span4_horz_37 lc_trk_g0_5 (8 4) routing span4_horz_45 lc_trk_g0_5 (8 4) routing span4_horz_5 lc_trk_g0_5 (8 4) routing span4_horz_r_13 lc_trk_g0_5 (8 4) routing span4_vert_13 lc_trk_g0_5 (8 4) routing span4_vert_37 lc_trk_g0_5 (8 4) routing span4_vert_45 lc_trk_g0_5 (8 4) routing span4_vert_5 lc_trk_g0_5 (8 4) routing span4_vert_b_13 lc_trk_g0_5 (8 5) routing IO_B.logic_op_top_5 lc_trk_g0_5 (8 5) routing IO_L.logic_op_rgt_5 lc_trk_g0_5 (8 5) routing IO_R.logic_op_lft_5 lc_trk_g0_5 (8 5) routing IO_T.logic_op_bot_5 lc_trk_g0_5 (8 5) routing span12_horz_21 lc_trk_g0_5 (8 5) routing span12_horz_5 lc_trk_g0_5 (8 5) routing span12_vert_21 lc_trk_g0_5 (8 5) routing span12_vert_5 lc_trk_g0_5 (8 5) routing span4_horz_13 lc_trk_g0_5 (8 5) routing span4_horz_29 lc_trk_g0_5 (8 5) routing span4_horz_45 lc_trk_g0_5 (8 5) routing span4_horz_r_5 lc_trk_g0_5 (8 5) routing span4_vert_13 lc_trk_g0_5 (8 5) routing span4_vert_29 lc_trk_g0_5 (8 5) routing span4_vert_45 lc_trk_g0_5 (8 5) routing span4_vert_b_5 lc_trk_g0_5 (8 6) routing IO_B.logic_op_tnl_7 lc_trk_g0_7 (8 6) routing IO_B.logic_op_top_7 lc_trk_g0_7 (8 6) routing IO_L.logic_op_rgt_7 lc_trk_g0_7 (8 6) routing IO_L.logic_op_tnr_7 lc_trk_g0_7 (8 6) routing IO_R.logic_op_lft_7 lc_trk_g0_7 (8 6) routing IO_R.logic_op_tnl_7 lc_trk_g0_7 (8 6) routing IO_T.logic_op_bnl_7 lc_trk_g0_7 (8 6) routing IO_T.logic_op_bot_7 lc_trk_g0_7 (8 6) routing span12_horz_7 lc_trk_g0_7 (8 6) routing span12_vert_7 lc_trk_g0_7 (8 6) routing span4_horz_15 lc_trk_g0_7 (8 6) routing span4_horz_39 lc_trk_g0_7 (8 6) routing span4_horz_47 lc_trk_g0_7 (8 6) routing span4_horz_7 lc_trk_g0_7 (8 6) routing span4_horz_r_15 lc_trk_g0_7 (8 6) routing span4_vert_15 lc_trk_g0_7 (8 6) routing span4_vert_39 lc_trk_g0_7 (8 6) routing span4_vert_47 lc_trk_g0_7 (8 6) routing span4_vert_7 lc_trk_g0_7 (8 6) routing span4_vert_b_15 lc_trk_g0_7 (8 7) routing IO_B.logic_op_top_7 lc_trk_g0_7 (8 7) routing IO_L.logic_op_rgt_7 lc_trk_g0_7 (8 7) routing IO_R.logic_op_lft_7 lc_trk_g0_7 (8 7) routing IO_T.logic_op_bot_7 lc_trk_g0_7 (8 7) routing span12_horz_23 lc_trk_g0_7 (8 7) routing span12_horz_7 lc_trk_g0_7 (8 7) routing span12_vert_23 lc_trk_g0_7 (8 7) routing span12_vert_7 lc_trk_g0_7 (8 7) routing span4_horz_15 lc_trk_g0_7 (8 7) routing span4_horz_31 lc_trk_g0_7 (8 7) routing span4_horz_47 lc_trk_g0_7 (8 7) routing span4_horz_r_7 lc_trk_g0_7 (8 7) routing span4_vert_15 lc_trk_g0_7 (8 7) routing span4_vert_31 lc_trk_g0_7 (8 7) routing span4_vert_47 lc_trk_g0_7 (8 7) routing span4_vert_b_7 lc_trk_g0_7 (8 8) routing IO_B.logic_op_tnl_1 lc_trk_g1_1 (8 8) routing IO_B.logic_op_top_1 lc_trk_g1_1 (8 8) routing IO_L.logic_op_rgt_1 lc_trk_g1_1 (8 8) routing IO_L.logic_op_tnr_1 lc_trk_g1_1 (8 8) routing IO_R.logic_op_lft_1 lc_trk_g1_1 (8 8) routing IO_R.logic_op_tnl_1 lc_trk_g1_1 (8 8) routing IO_T.logic_op_bnl_1 lc_trk_g1_1 (8 8) routing IO_T.logic_op_bot_1 lc_trk_g1_1 (8 8) routing span12_horz_1 lc_trk_g1_1 (8 8) routing span12_vert_1 lc_trk_g1_1 (8 8) routing span4_horz_1 lc_trk_g1_1 (8 8) routing span4_horz_33 lc_trk_g1_1 (8 8) routing span4_horz_41 lc_trk_g1_1 (8 8) routing span4_horz_9 lc_trk_g1_1 (8 8) routing span4_horz_r_9 lc_trk_g1_1 (8 8) routing span4_vert_1 lc_trk_g1_1 (8 8) routing span4_vert_33 lc_trk_g1_1 (8 8) routing span4_vert_41 lc_trk_g1_1 (8 8) routing span4_vert_9 lc_trk_g1_1 (8 8) routing span4_vert_b_9 lc_trk_g1_1 (8 9) routing IO_B.logic_op_top_1 lc_trk_g1_1 (8 9) routing IO_L.logic_op_rgt_1 lc_trk_g1_1 (8 9) routing IO_R.logic_op_lft_1 lc_trk_g1_1 (8 9) routing IO_T.logic_op_bot_1 lc_trk_g1_1 (8 9) routing span12_horz_1 lc_trk_g1_1 (8 9) routing span12_horz_17 lc_trk_g1_1 (8 9) routing span12_vert_1 lc_trk_g1_1 (8 9) routing span12_vert_17 lc_trk_g1_1 (8 9) routing span4_horz_25 lc_trk_g1_1 (8 9) routing span4_horz_41 lc_trk_g1_1 (8 9) routing span4_horz_9 lc_trk_g1_1 (8 9) routing span4_horz_r_1 lc_trk_g1_1 (8 9) routing span4_vert_25 lc_trk_g1_1 (8 9) routing span4_vert_41 lc_trk_g1_1 (8 9) routing span4_vert_9 lc_trk_g1_1 (8 9) routing span4_vert_b_1 lc_trk_g1_1 (9 0) Column buffer control bit: BIOLEFT_half_column_clock_enable_1 (9 0) Column buffer control bit: IOLEFT_half_column_clock_enable_1 (9 0) Column buffer control bit: IORIGHT_half_column_clock_enable_1 (9 1) Column buffer control bit: BIOLEFT_half_column_clock_enable_0 (9 1) Column buffer control bit: IOLEFT_half_column_clock_enable_0 (9 1) Column buffer control bit: IORIGHT_half_column_clock_enable_0 (9 2) Column buffer control bit: BIOLEFT_half_column_clock_enable_3 (9 2) Column buffer control bit: IOLEFT_half_column_clock_enable_3 (9 2) Column buffer control bit: IORIGHT_half_column_clock_enable_3 (9 3) Column buffer control bit: BIOLEFT_half_column_clock_enable_2 (9 3) Column buffer control bit: IOLEFT_half_column_clock_enable_2 (9 3) Column buffer control bit: IORIGHT_half_column_clock_enable_2 (9 4) Column buffer control bit: BIOLEFT_half_column_clock_enable_5 (9 4) Column buffer control bit: IOLEFT_half_column_clock_enable_5 (9 4) Column buffer control bit: IORIGHT_half_column_clock_enable_5 (9 5) Column buffer control bit: BIOLEFT_half_column_clock_enable_4 (9 5) Column buffer control bit: IOLEFT_half_column_clock_enable_4 (9 5) Column buffer control bit: IORIGHT_half_column_clock_enable_4 (9 6) Column buffer control bit: BIOLEFT_half_column_clock_enable_7 (9 6) Column buffer control bit: IOLEFT_half_column_clock_enable_7 (9 6) Column buffer control bit: IORIGHT_half_column_clock_enable_7 (9 7) Column buffer control bit: BIOLEFT_half_column_clock_enable_6 (9 7) Column buffer control bit: IOLEFT_half_column_clock_enable_6 (9 7) Column buffer control bit: IORIGHT_half_column_clock_enable_6 fpga-icestorm-0~20160913git266e758/icefuzz/cached_logic.txt000066400000000000000000007107721276746530600232140ustar00rootroot00000000000000(0 0) Negative Clock bit (0 10) routing glb_netwk_2 glb2local_2 (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 (0 10) routing glb_netwk_7 glb2local_2 (0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 (0 11) routing glb_netwk_7 glb2local_2 (0 12) routing glb_netwk_2 glb2local_3 (0 12) routing glb_netwk_3 glb2local_3 (0 12) routing glb_netwk_6 glb2local_3 (0 12) routing glb_netwk_7 glb2local_3 (0 13) routing glb_netwk_1 glb2local_3 (0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 (0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_logic_cluster/lc_7/s_r (0 14) routing glb_netwk_6 wire_logic_cluster/lc_7/s_r (0 14) routing lc_trk_g2_4 wire_logic_cluster/lc_7/s_r (0 14) routing lc_trk_g3_5 wire_logic_cluster/lc_7/s_r (0 15) routing glb_netwk_2 wire_logic_cluster/lc_7/s_r (0 15) routing glb_netwk_6 wire_logic_cluster/lc_7/s_r (0 15) routing lc_trk_g1_5 wire_logic_cluster/lc_7/s_r (0 15) routing lc_trk_g3_5 wire_logic_cluster/lc_7/s_r (0 2) routing glb_netwk_2 wire_logic_cluster/lc_7/clk (0 2) routing glb_netwk_3 wire_logic_cluster/lc_7/clk (0 2) routing glb_netwk_6 wire_logic_cluster/lc_7/clk (0 2) routing glb_netwk_7 wire_logic_cluster/lc_7/clk (0 2) routing lc_trk_g2_0 wire_logic_cluster/lc_7/clk (0 2) routing lc_trk_g3_1 wire_logic_cluster/lc_7/clk (0 3) routing glb_netwk_1 wire_logic_cluster/lc_7/clk (0 3) routing glb_netwk_3 wire_logic_cluster/lc_7/clk (0 3) routing glb_netwk_5 wire_logic_cluster/lc_7/clk (0 3) routing glb_netwk_7 wire_logic_cluster/lc_7/clk (0 3) routing lc_trk_g1_1 wire_logic_cluster/lc_7/clk (0 3) routing lc_trk_g3_1 wire_logic_cluster/lc_7/clk (0 4) routing glb_netwk_5 wire_logic_cluster/lc_7/cen (0 4) routing glb_netwk_7 wire_logic_cluster/lc_7/cen (0 4) routing lc_trk_g2_2 wire_logic_cluster/lc_7/cen (0 4) routing lc_trk_g3_3 wire_logic_cluster/lc_7/cen (0 5) routing glb_netwk_3 wire_logic_cluster/lc_7/cen (0 5) routing glb_netwk_7 wire_logic_cluster/lc_7/cen (0 5) routing lc_trk_g1_3 wire_logic_cluster/lc_7/cen (0 5) routing lc_trk_g3_3 wire_logic_cluster/lc_7/cen (0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 (0 6) routing glb_netwk_6 glb2local_0 (0 6) routing glb_netwk_7 glb2local_0 (0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 (0 7) routing glb_netwk_7 glb2local_0 (0 8) routing glb_netwk_2 glb2local_1 (0 8) routing glb_netwk_3 glb2local_1 (0 8) routing glb_netwk_6 glb2local_1 (0 8) routing glb_netwk_7 glb2local_1 (0 9) routing glb_netwk_1 glb2local_1 (0 9) routing glb_netwk_3 glb2local_1 (0 9) routing glb_netwk_5 glb2local_1 (0 9) routing glb_netwk_7 glb2local_1 (1 0) Column buffer control bit: LH_colbuf_cntl_0 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 (1 11) routing glb_netwk_7 glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 (1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 (1 13) routing glb_netwk_6 glb2local_3 (1 13) routing glb_netwk_7 glb2local_3 (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_logic_cluster/lc_7/s_r (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_logic_cluster/lc_7/s_r (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_logic_cluster/lc_7/s_r (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_logic_cluster/lc_7/s_r (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_logic_cluster/lc_7/s_r (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_logic_cluster/lc_7/s_r (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_logic_cluster/lc_7/s_r (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_logic_cluster/lc_7/s_r (1 15) routing lc_trk_g0_4 wire_logic_cluster/lc_7/s_r (1 15) routing lc_trk_g1_5 wire_logic_cluster/lc_7/s_r (1 15) routing lc_trk_g2_4 wire_logic_cluster/lc_7/s_r (1 15) routing lc_trk_g3_5 wire_logic_cluster/lc_7/s_r (1 2) routing glb_netwk_4 wire_logic_cluster/lc_7/clk (1 2) routing glb_netwk_5 wire_logic_cluster/lc_7/clk (1 2) routing glb_netwk_6 wire_logic_cluster/lc_7/clk (1 2) routing glb_netwk_7 wire_logic_cluster/lc_7/clk (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_l_4 (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_logic_cluster/lc_7/cen (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_logic_cluster/lc_7/cen (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_logic_cluster/lc_7/cen (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_logic_cluster/lc_7/cen (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_logic_cluster/lc_7/cen (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_logic_cluster/lc_7/cen (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_logic_cluster/lc_7/cen (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_logic_cluster/lc_7/cen (1 5) routing lc_trk_g0_2 wire_logic_cluster/lc_7/cen (1 5) routing lc_trk_g1_3 wire_logic_cluster/lc_7/cen (1 5) routing lc_trk_g2_2 wire_logic_cluster/lc_7/cen (1 5) routing lc_trk_g3_3 wire_logic_cluster/lc_7/cen (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 (1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 (1 7) routing glb_netwk_6 glb2local_0 (1 7) routing glb_netwk_7 glb2local_0 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 (1 9) routing glb_netwk_4 glb2local_1 (1 9) routing glb_netwk_5 glb2local_1 (1 9) routing glb_netwk_6 glb2local_1 (1 9) routing glb_netwk_7 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 (10 0) routing sp4_v_t_45 sp4_h_r_1 (10 1) routing sp4_h_l_42 sp4_v_b_1 (10 1) routing sp4_h_r_8 sp4_v_b_1 (10 1) routing sp4_v_t_40 sp4_v_b_1 (10 1) routing sp4_v_t_47 sp4_v_b_1 (10 10) routing sp4_h_r_11 sp4_h_l_42 (10 10) routing sp4_h_r_4 sp4_h_l_42 (10 10) routing sp4_v_b_2 sp4_h_l_42 (10 10) routing sp4_v_t_36 sp4_h_l_42 (10 11) routing sp4_h_l_39 sp4_v_t_42 (10 11) routing sp4_h_r_1 sp4_v_t_42 (10 11) routing sp4_v_b_11 sp4_v_t_42 (10 11) routing sp4_v_b_4 sp4_v_t_42 (10 12) routing sp4_h_l_39 sp4_h_r_10 (10 12) routing sp4_h_l_42 sp4_h_r_10 (10 12) routing sp4_v_b_4 sp4_h_r_10 (10 12) routing sp4_v_t_40 sp4_h_r_10 (10 13) routing sp4_h_l_41 sp4_v_b_10 (10 13) routing sp4_h_r_5 sp4_v_b_10 (10 13) routing sp4_v_t_39 sp4_v_b_10 (10 13) routing sp4_v_t_42 sp4_v_b_10 (10 14) routing sp4_h_r_2 sp4_h_l_47 (10 14) routing sp4_h_r_7 sp4_h_l_47 (10 14) routing sp4_v_b_5 sp4_h_l_47 (10 14) routing sp4_v_t_41 sp4_h_l_47 (10 15) routing sp4_h_l_40 sp4_v_t_47 (10 15) routing sp4_h_r_4 sp4_v_t_47 (10 15) routing sp4_v_b_2 sp4_v_t_47 (10 15) routing sp4_v_b_7 sp4_v_t_47 (10 2) routing sp4_h_r_10 sp4_h_l_36 (10 2) routing sp4_h_r_5 sp4_h_l_36 (10 2) routing sp4_v_b_8 sp4_h_l_36 (10 2) routing sp4_v_t_42 sp4_h_l_36 (10 3) routing sp4_h_l_45 sp4_v_t_36 (10 3) routing sp4_h_r_7 sp4_v_t_36 (10 3) routing sp4_v_b_10 sp4_v_t_36 (10 3) routing sp4_v_b_5 sp4_v_t_36 (10 4) routing sp4_h_l_36 sp4_h_r_4 (10 4) routing sp4_h_l_45 sp4_h_r_4 (10 4) routing sp4_v_b_10 sp4_h_r_4 (10 4) routing sp4_v_t_46 sp4_h_r_4 (10 5) routing sp4_h_l_47 sp4_v_b_4 (10 5) routing sp4_h_r_11 sp4_v_b_4 (10 5) routing sp4_v_t_36 sp4_v_b_4 (10 5) routing sp4_v_t_45 sp4_v_b_4 (10 6) routing sp4_h_r_1 sp4_h_l_41 (10 6) routing sp4_h_r_8 sp4_h_l_41 (10 6) routing sp4_v_b_11 sp4_h_l_41 (10 6) routing sp4_v_t_47 sp4_h_l_41 (10 7) routing sp4_h_l_46 sp4_v_t_41 (10 7) routing sp4_h_r_10 sp4_v_t_41 (10 7) routing sp4_v_b_1 sp4_v_t_41 (10 7) routing sp4_v_b_8 sp4_v_t_41 (10 8) routing sp4_h_l_41 sp4_h_r_7 (10 8) routing sp4_h_l_46 sp4_h_r_7 (10 8) routing sp4_v_b_1 sp4_h_r_7 (10 8) routing sp4_v_t_39 sp4_h_r_7 (10 9) routing sp4_h_l_36 sp4_v_b_7 (10 9) routing sp4_h_r_2 sp4_v_b_7 (10 9) routing sp4_v_t_41 sp4_v_b_7 (10 9) routing sp4_v_t_46 sp4_v_b_7 (11 0) routing sp4_h_l_45 sp4_v_b_2 (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 (11 1) routing sp4_h_l_39 sp4_h_r_2 (11 1) routing sp4_h_l_43 sp4_h_r_2 (11 1) routing sp4_v_b_2 sp4_h_r_2 (11 1) routing sp4_v_b_8 sp4_h_r_2 (11 10) routing sp4_h_l_38 sp4_v_t_45 (11 10) routing sp4_h_r_2 sp4_v_t_45 (11 10) routing sp4_v_b_0 sp4_v_t_45 (11 10) routing sp4_v_b_5 sp4_v_t_45 (11 11) routing sp4_h_r_0 sp4_h_l_45 (11 11) routing sp4_h_r_8 sp4_h_l_45 (11 11) routing sp4_v_t_39 sp4_h_l_45 (11 11) routing sp4_v_t_45 sp4_h_l_45 (11 12) routing sp4_h_l_40 sp4_v_b_11 (11 12) routing sp4_h_r_6 sp4_v_b_11 (11 12) routing sp4_v_t_38 sp4_v_b_11 (11 12) routing sp4_v_t_45 sp4_v_b_11 (11 13) routing sp4_h_l_38 sp4_h_r_11 (11 13) routing sp4_h_l_46 sp4_h_r_11 (11 13) routing sp4_v_b_11 sp4_h_r_11 (11 13) routing sp4_v_b_5 sp4_h_r_11 (11 14) routing sp4_h_l_43 sp4_v_t_46 (11 14) routing sp4_h_r_5 sp4_v_t_46 (11 14) routing sp4_v_b_3 sp4_v_t_46 (11 14) routing sp4_v_b_8 sp4_v_t_46 (11 15) routing sp4_h_r_11 sp4_h_l_46 (11 15) routing sp4_h_r_3 sp4_h_l_46 (11 15) routing sp4_v_t_40 sp4_h_l_46 (11 15) routing sp4_v_t_46 sp4_h_l_46 (11 2) routing sp4_h_l_44 sp4_v_t_39 (11 2) routing sp4_h_r_8 sp4_v_t_39 (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 (11 3) routing sp4_h_r_2 sp4_h_l_39 (11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 (11 4) routing sp4_h_r_0 sp4_v_b_5 (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 (11 5) routing sp4_h_l_40 sp4_h_r_5 (11 5) routing sp4_h_l_44 sp4_h_r_5 (11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 (11 6) routing sp4_h_r_11 sp4_v_t_40 (11 6) routing sp4_v_b_2 sp4_v_t_40 (11 6) routing sp4_v_b_9 sp4_v_t_40 (11 7) routing sp4_h_r_5 sp4_h_l_40 (11 7) routing sp4_h_r_9 sp4_h_l_40 (11 7) routing sp4_v_t_40 sp4_h_l_40 (11 7) routing sp4_v_t_46 sp4_h_l_40 (11 8) routing sp4_h_l_39 sp4_v_b_8 (11 8) routing sp4_h_r_3 sp4_v_b_8 (11 8) routing sp4_v_t_37 sp4_v_b_8 (11 8) routing sp4_v_t_40 sp4_v_b_8 (11 9) routing sp4_h_l_37 sp4_h_r_8 (11 9) routing sp4_h_l_45 sp4_h_r_8 (11 9) routing sp4_v_b_2 sp4_h_r_8 (11 9) routing sp4_v_b_8 sp4_h_r_8 (12 0) routing sp4_h_l_46 sp4_h_r_2 (12 0) routing sp4_v_b_2 sp4_h_r_2 (12 0) routing sp4_v_b_8 sp4_h_r_2 (12 0) routing sp4_v_t_39 sp4_h_r_2 (12 1) routing sp4_h_l_39 sp4_v_b_2 (12 1) routing sp4_h_l_45 sp4_v_b_2 (12 1) routing sp4_h_r_2 sp4_v_b_2 (12 1) routing sp4_v_t_46 sp4_v_b_2 (12 10) routing sp4_h_r_5 sp4_h_l_45 (12 10) routing sp4_v_b_8 sp4_h_l_45 (12 10) routing sp4_v_t_39 sp4_h_l_45 (12 10) routing sp4_v_t_45 sp4_h_l_45 (12 11) routing sp4_h_l_45 sp4_v_t_45 (12 11) routing sp4_h_r_2 sp4_v_t_45 (12 11) routing sp4_h_r_8 sp4_v_t_45 (12 11) routing sp4_v_b_5 sp4_v_t_45 (12 12) routing sp4_h_l_45 sp4_h_r_11 (12 12) routing sp4_v_b_11 sp4_h_r_11 (12 12) routing sp4_v_b_5 sp4_h_r_11 (12 12) routing sp4_v_t_46 sp4_h_r_11 (12 13) routing sp4_h_l_40 sp4_v_b_11 (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 (12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 (12 14) routing sp4_v_t_46 sp4_h_l_46 (12 15) routing sp4_h_l_46 sp4_v_t_46 (12 15) routing sp4_h_r_11 sp4_v_t_46 (12 15) routing sp4_h_r_5 sp4_v_t_46 (12 15) routing sp4_v_b_8 sp4_v_t_46 (12 2) routing sp4_h_r_11 sp4_h_l_39 (12 2) routing sp4_v_b_2 sp4_h_l_39 (12 2) routing sp4_v_t_39 sp4_h_l_39 (12 2) routing sp4_v_t_45 sp4_h_l_39 (12 3) routing sp4_h_l_39 sp4_v_t_39 (12 3) routing sp4_h_r_2 sp4_v_t_39 (12 3) routing sp4_h_r_8 sp4_v_t_39 (12 3) routing sp4_v_b_11 sp4_v_t_39 (12 4) routing sp4_h_l_39 sp4_h_r_5 (12 4) routing sp4_v_b_11 sp4_h_r_5 (12 4) routing sp4_v_b_5 sp4_h_r_5 (12 4) routing sp4_v_t_40 sp4_h_r_5 (12 5) routing sp4_h_l_40 sp4_v_b_5 (12 5) routing sp4_h_l_46 sp4_v_b_5 (12 5) routing sp4_h_r_5 sp4_v_b_5 (12 5) routing sp4_v_t_39 sp4_v_b_5 (12 6) routing sp4_h_r_2 sp4_h_l_40 (12 6) routing sp4_v_b_5 sp4_h_l_40 (12 6) routing sp4_v_t_40 sp4_h_l_40 (12 6) routing sp4_v_t_46 sp4_h_l_40 (12 7) routing sp4_h_l_40 sp4_v_t_40 (12 7) routing sp4_h_r_11 sp4_v_t_40 (12 7) routing sp4_h_r_5 sp4_v_t_40 (12 7) routing sp4_v_b_2 sp4_v_t_40 (12 8) routing sp4_h_l_40 sp4_h_r_8 (12 8) routing sp4_v_b_2 sp4_h_r_8 (12 8) routing sp4_v_b_8 sp4_h_r_8 (12 8) routing sp4_v_t_45 sp4_h_r_8 (12 9) routing sp4_h_l_39 sp4_v_b_8 (12 9) routing sp4_h_l_45 sp4_v_b_8 (12 9) routing sp4_h_r_8 sp4_v_b_8 (12 9) routing sp4_v_t_40 sp4_v_b_8 (13 0) routing sp4_h_l_39 sp4_v_b_2 (13 0) routing sp4_h_l_45 sp4_v_b_2 (13 0) routing sp4_v_t_39 sp4_v_b_2 (13 0) routing sp4_v_t_43 sp4_v_b_2 (13 1) routing sp4_h_l_43 sp4_h_r_2 (13 1) routing sp4_h_l_46 sp4_h_r_2 (13 1) routing sp4_v_b_8 sp4_h_r_2 (13 1) routing sp4_v_t_44 sp4_h_r_2 (13 10) routing sp4_h_r_2 sp4_v_t_45 (13 10) routing sp4_h_r_8 sp4_v_t_45 (13 10) routing sp4_v_b_0 sp4_v_t_45 (13 10) routing sp4_v_b_8 sp4_v_t_45 (13 11) routing sp4_h_r_0 sp4_h_l_45 (13 11) routing sp4_h_r_5 sp4_h_l_45 (13 11) routing sp4_v_b_3 sp4_h_l_45 (13 11) routing sp4_v_t_39 sp4_h_l_45 (13 12) routing sp4_h_l_40 sp4_v_b_11 (13 12) routing sp4_h_l_46 sp4_v_b_11 (13 12) routing sp4_v_t_38 sp4_v_b_11 (13 12) routing sp4_v_t_46 sp4_v_b_11 (13 13) routing sp4_h_l_38 sp4_h_r_11 (13 13) routing sp4_h_l_45 sp4_h_r_11 (13 13) routing sp4_v_b_5 sp4_h_r_11 (13 13) routing sp4_v_t_43 sp4_h_r_11 (13 14) routing sp4_h_r_11 sp4_v_t_46 (13 14) routing sp4_h_r_5 sp4_v_t_46 (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 (13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 (13 2) routing sp4_h_r_8 sp4_v_t_39 (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 (13 3) routing sp4_h_r_11 sp4_h_l_39 (13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 (13 4) routing sp4_h_l_46 sp4_v_b_5 (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 (13 5) routing sp4_h_l_39 sp4_h_r_5 (13 5) routing sp4_h_l_44 sp4_h_r_5 (13 5) routing sp4_v_b_11 sp4_h_r_5 (13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 (13 6) routing sp4_h_r_5 sp4_v_t_40 (13 6) routing sp4_v_b_5 sp4_v_t_40 (13 6) routing sp4_v_b_9 sp4_v_t_40 (13 7) routing sp4_h_r_2 sp4_h_l_40 (13 7) routing sp4_h_r_9 sp4_h_l_40 (13 7) routing sp4_v_b_0 sp4_h_l_40 (13 7) routing sp4_v_t_46 sp4_h_l_40 (13 8) routing sp4_h_l_39 sp4_v_b_8 (13 8) routing sp4_h_l_45 sp4_v_b_8 (13 8) routing sp4_v_t_37 sp4_v_b_8 (13 8) routing sp4_v_t_45 sp4_v_b_8 (13 9) routing sp4_h_l_37 sp4_h_r_8 (13 9) routing sp4_h_l_40 sp4_h_r_8 (13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 (14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_l_5 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 0) routing wire_logic_cluster/lc_0/out lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 (14 1) routing sp12_h_r_0 lc_trk_g0_0 (14 1) routing sp12_h_r_16 lc_trk_g0_0 (14 1) routing sp4_h_l_5 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing top_op_0 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 (14 10) routing rgt_op_4 lc_trk_g2_4 (14 10) routing sp12_v_t_3 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 (14 10) routing sp4_v_b_36 lc_trk_g2_4 (14 10) routing sp4_v_t_17 lc_trk_g2_4 (14 10) routing wire_logic_cluster/lc_4/out lc_trk_g2_4 (14 11) routing bnl_op_4 lc_trk_g2_4 (14 11) routing sp12_v_b_20 lc_trk_g2_4 (14 11) routing sp12_v_t_3 lc_trk_g2_4 (14 11) routing sp4_h_l_17 lc_trk_g2_4 (14 11) routing sp4_h_r_44 lc_trk_g2_4 (14 11) routing sp4_r_v_b_36 lc_trk_g2_4 (14 11) routing sp4_v_b_36 lc_trk_g2_4 (14 11) routing tnl_op_4 lc_trk_g2_4 (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 (14 12) routing sp12_v_b_0 lc_trk_g3_0 (14 12) routing sp4_h_l_21 lc_trk_g3_0 (14 12) routing sp4_h_r_40 lc_trk_g3_0 (14 12) routing sp4_v_b_24 lc_trk_g3_0 (14 12) routing sp4_v_t_21 lc_trk_g3_0 (14 12) routing wire_logic_cluster/lc_0/out lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 (14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 (14 13) routing sp4_h_r_24 lc_trk_g3_0 (14 13) routing sp4_h_r_40 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing tnl_op_0 lc_trk_g3_0 (14 14) routing bnl_op_4 lc_trk_g3_4 (14 14) routing rgt_op_4 lc_trk_g3_4 (14 14) routing sp12_v_t_3 lc_trk_g3_4 (14 14) routing sp4_h_r_36 lc_trk_g3_4 (14 14) routing sp4_h_r_44 lc_trk_g3_4 (14 14) routing sp4_v_b_36 lc_trk_g3_4 (14 14) routing sp4_v_t_17 lc_trk_g3_4 (14 14) routing wire_logic_cluster/lc_4/out lc_trk_g3_4 (14 15) routing bnl_op_4 lc_trk_g3_4 (14 15) routing sp12_v_b_20 lc_trk_g3_4 (14 15) routing sp12_v_t_3 lc_trk_g3_4 (14 15) routing sp4_h_l_17 lc_trk_g3_4 (14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_b_36 lc_trk_g3_4 (14 15) routing tnl_op_4 lc_trk_g3_4 (14 2) routing bnr_op_4 lc_trk_g0_4 (14 2) routing lft_op_4 lc_trk_g0_4 (14 2) routing sp12_h_l_3 lc_trk_g0_4 (14 2) routing sp4_h_l_1 lc_trk_g0_4 (14 2) routing sp4_h_l_9 lc_trk_g0_4 (14 2) routing sp4_v_b_4 lc_trk_g0_4 (14 2) routing sp4_v_t_1 lc_trk_g0_4 (14 2) routing wire_logic_cluster/lc_4/out lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 (14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_l_9 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 (14 3) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing top_op_4 lc_trk_g0_4 (14 4) routing bnr_op_0 lc_trk_g1_0 (14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_l_5 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 (14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 4) routing wire_logic_cluster/lc_0/out lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 (14 5) routing sp12_h_r_16 lc_trk_g1_0 (14 5) routing sp4_h_l_5 lc_trk_g1_0 (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing top_op_0 lc_trk_g1_0 (14 6) routing bnr_op_4 lc_trk_g1_4 (14 6) routing lft_op_4 lc_trk_g1_4 (14 6) routing sp12_h_l_3 lc_trk_g1_4 (14 6) routing sp4_h_l_1 lc_trk_g1_4 (14 6) routing sp4_h_l_9 lc_trk_g1_4 (14 6) routing sp4_v_b_4 lc_trk_g1_4 (14 6) routing sp4_v_t_1 lc_trk_g1_4 (14 6) routing wire_logic_cluster/lc_4/out lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_l_9 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing top_op_4 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 (14 8) routing rgt_op_0 lc_trk_g2_0 (14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_l_21 lc_trk_g2_0 (14 8) routing sp4_h_r_40 lc_trk_g2_0 (14 8) routing sp4_v_b_24 lc_trk_g2_0 (14 8) routing sp4_v_t_21 lc_trk_g2_0 (14 8) routing wire_logic_cluster/lc_0/out lc_trk_g2_0 (14 9) routing bnl_op_0 lc_trk_g2_0 (14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 (14 9) routing sp4_h_r_24 lc_trk_g2_0 (14 9) routing sp4_h_r_40 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_t_21 lc_trk_g2_0 (14 9) routing tnl_op_0 lc_trk_g2_0 (15 0) routing bot_op_1 lc_trk_g0_1 (15 0) routing lft_op_1 lc_trk_g0_1 (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_l_4 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_b_17 lc_trk_g0_1 (15 0) routing top_op_1 lc_trk_g0_1 (15 1) routing bot_op_0 lc_trk_g0_0 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_l_5 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 (15 1) routing sp4_v_t_5 lc_trk_g0_0 (15 1) routing top_op_0 lc_trk_g0_0 (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_t_2 lc_trk_g2_5 (15 10) routing sp4_h_l_16 lc_trk_g2_5 (15 10) routing sp4_h_l_24 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_t_32 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_t_3 lc_trk_g2_4 (15 11) routing sp4_h_l_17 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 (15 11) routing sp4_h_r_44 lc_trk_g2_4 (15 11) routing sp4_v_t_33 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 (15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_h_r_33 lc_trk_g3_1 (15 12) routing sp4_h_r_41 lc_trk_g3_1 (15 12) routing sp4_v_t_28 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 (15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 (15 13) routing sp4_h_l_21 lc_trk_g3_0 (15 13) routing sp4_h_r_24 lc_trk_g3_0 (15 13) routing sp4_h_r_40 lc_trk_g3_0 (15 13) routing sp4_v_t_29 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 (15 13) routing tnr_op_0 lc_trk_g3_0 (15 14) routing rgt_op_5 lc_trk_g3_5 (15 14) routing sp12_v_t_2 lc_trk_g3_5 (15 14) routing sp4_h_l_16 lc_trk_g3_5 (15 14) routing sp4_h_l_24 lc_trk_g3_5 (15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_t_32 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 (15 15) routing sp12_v_t_3 lc_trk_g3_4 (15 15) routing sp4_h_l_17 lc_trk_g3_4 (15 15) routing sp4_h_r_36 lc_trk_g3_4 (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_t_33 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 (15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing bot_op_5 lc_trk_g0_5 (15 2) routing lft_op_5 lc_trk_g0_5 (15 2) routing sp12_h_r_5 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_21 lc_trk_g0_5 (15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_b_21 lc_trk_g0_5 (15 2) routing top_op_5 lc_trk_g0_5 (15 3) routing bot_op_4 lc_trk_g0_4 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_l_1 lc_trk_g0_4 (15 3) routing sp4_h_l_9 lc_trk_g0_4 (15 3) routing sp4_h_r_4 lc_trk_g0_4 (15 3) routing sp4_v_t_9 lc_trk_g0_4 (15 3) routing top_op_4 lc_trk_g0_4 (15 4) routing bot_op_1 lc_trk_g1_1 (15 4) routing lft_op_1 lc_trk_g1_1 (15 4) routing sp12_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_l_4 lc_trk_g1_1 (15 4) routing sp4_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_b_17 lc_trk_g1_1 (15 4) routing top_op_1 lc_trk_g1_1 (15 5) routing bot_op_0 lc_trk_g1_0 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_l_5 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_t_5 lc_trk_g1_0 (15 5) routing top_op_0 lc_trk_g1_0 (15 6) routing bot_op_5 lc_trk_g1_5 (15 6) routing lft_op_5 lc_trk_g1_5 (15 6) routing sp12_h_r_5 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_21 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_b_21 lc_trk_g1_5 (15 6) routing top_op_5 lc_trk_g1_5 (15 7) routing bot_op_4 lc_trk_g1_4 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_l_1 lc_trk_g1_4 (15 7) routing sp4_h_l_9 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_t_9 lc_trk_g1_4 (15 7) routing top_op_4 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_h_r_33 lc_trk_g2_1 (15 8) routing sp4_h_r_41 lc_trk_g2_1 (15 8) routing sp4_v_t_28 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_l_21 lc_trk_g2_0 (15 9) routing sp4_h_r_24 lc_trk_g2_0 (15 9) routing sp4_h_r_40 lc_trk_g2_0 (15 9) routing sp4_v_t_29 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 (16 0) routing sp12_h_l_14 lc_trk_g0_1 (16 0) routing sp12_h_r_9 lc_trk_g0_1 (16 0) routing sp4_h_l_4 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_17 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 (16 1) routing sp12_h_r_16 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_l_5 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 (16 1) routing sp4_h_r_8 lc_trk_g0_0 (16 1) routing sp4_v_b_0 lc_trk_g0_0 (16 1) routing sp4_v_b_8 lc_trk_g0_0 (16 1) routing sp4_v_t_5 lc_trk_g0_0 (16 10) routing sp12_v_b_21 lc_trk_g2_5 (16 10) routing sp12_v_t_10 lc_trk_g2_5 (16 10) routing sp4_h_l_16 lc_trk_g2_5 (16 10) routing sp4_h_l_24 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_37 lc_trk_g2_5 (16 10) routing sp4_v_t_16 lc_trk_g2_5 (16 10) routing sp4_v_t_32 lc_trk_g2_5 (16 11) routing sp12_v_b_12 lc_trk_g2_4 (16 11) routing sp12_v_b_20 lc_trk_g2_4 (16 11) routing sp4_h_l_17 lc_trk_g2_4 (16 11) routing sp4_h_r_36 lc_trk_g2_4 (16 11) routing sp4_h_r_44 lc_trk_g2_4 (16 11) routing sp4_v_b_36 lc_trk_g2_4 (16 11) routing sp4_v_t_17 lc_trk_g2_4 (16 11) routing sp4_v_t_33 lc_trk_g2_4 (16 12) routing sp12_v_t_14 lc_trk_g3_1 (16 12) routing sp12_v_t_6 lc_trk_g3_1 (16 12) routing sp4_h_r_25 lc_trk_g3_1 (16 12) routing sp4_h_r_33 lc_trk_g3_1 (16 12) routing sp4_h_r_41 lc_trk_g3_1 (16 12) routing sp4_v_b_33 lc_trk_g3_1 (16 12) routing sp4_v_t_12 lc_trk_g3_1 (16 12) routing sp4_v_t_28 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_b_8 lc_trk_g3_0 (16 13) routing sp4_h_l_21 lc_trk_g3_0 (16 13) routing sp4_h_r_24 lc_trk_g3_0 (16 13) routing sp4_h_r_40 lc_trk_g3_0 (16 13) routing sp4_v_b_24 lc_trk_g3_0 (16 13) routing sp4_v_t_21 lc_trk_g3_0 (16 13) routing sp4_v_t_29 lc_trk_g3_0 (16 14) routing sp12_v_b_21 lc_trk_g3_5 (16 14) routing sp12_v_t_10 lc_trk_g3_5 (16 14) routing sp4_h_l_16 lc_trk_g3_5 (16 14) routing sp4_h_l_24 lc_trk_g3_5 (16 14) routing sp4_h_r_45 lc_trk_g3_5 (16 14) routing sp4_v_b_37 lc_trk_g3_5 (16 14) routing sp4_v_t_16 lc_trk_g3_5 (16 14) routing sp4_v_t_32 lc_trk_g3_5 (16 15) routing sp12_v_b_12 lc_trk_g3_4 (16 15) routing sp12_v_b_20 lc_trk_g3_4 (16 15) routing sp4_h_l_17 lc_trk_g3_4 (16 15) routing sp4_h_r_36 lc_trk_g3_4 (16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_36 lc_trk_g3_4 (16 15) routing sp4_v_t_17 lc_trk_g3_4 (16 15) routing sp4_v_t_33 lc_trk_g3_4 (16 2) routing sp12_h_l_18 lc_trk_g0_5 (16 2) routing sp12_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_5 lc_trk_g0_5 (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_21 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 3) routing sp12_h_r_12 lc_trk_g0_4 (16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_l_1 lc_trk_g0_4 (16 3) routing sp4_h_l_9 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 3) routing sp4_v_t_1 lc_trk_g0_4 (16 3) routing sp4_v_t_9 lc_trk_g0_4 (16 4) routing sp12_h_l_14 lc_trk_g1_1 (16 4) routing sp12_h_r_9 lc_trk_g1_1 (16 4) routing sp4_h_l_4 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_17 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 5) routing sp12_h_r_16 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_l_5 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_8 lc_trk_g1_0 (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 (16 5) routing sp4_v_t_5 lc_trk_g1_0 (16 6) routing sp12_h_l_18 lc_trk_g1_5 (16 6) routing sp12_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 (16 6) routing sp4_v_b_13 lc_trk_g1_5 (16 6) routing sp4_v_b_21 lc_trk_g1_5 (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 7) routing sp12_h_r_12 lc_trk_g1_4 (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_l_1 lc_trk_g1_4 (16 7) routing sp4_h_l_9 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 (16 7) routing sp4_v_t_1 lc_trk_g1_4 (16 7) routing sp4_v_t_9 lc_trk_g1_4 (16 8) routing sp12_v_t_14 lc_trk_g2_1 (16 8) routing sp12_v_t_6 lc_trk_g2_1 (16 8) routing sp4_h_r_25 lc_trk_g2_1 (16 8) routing sp4_h_r_33 lc_trk_g2_1 (16 8) routing sp4_h_r_41 lc_trk_g2_1 (16 8) routing sp4_v_b_33 lc_trk_g2_1 (16 8) routing sp4_v_t_12 lc_trk_g2_1 (16 8) routing sp4_v_t_28 lc_trk_g2_1 (16 9) routing sp12_v_b_16 lc_trk_g2_0 (16 9) routing sp12_v_b_8 lc_trk_g2_0 (16 9) routing sp4_h_l_21 lc_trk_g2_0 (16 9) routing sp4_h_r_24 lc_trk_g2_0 (16 9) routing sp4_h_r_40 lc_trk_g2_0 (16 9) routing sp4_v_b_24 lc_trk_g2_0 (16 9) routing sp4_v_t_21 lc_trk_g2_0 (16 9) routing sp4_v_t_29 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bot_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_l_4 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => top_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_t_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => top_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g0_0 (17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_2 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_24 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_16 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_32 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_17 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_6 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_12 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_8 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_24 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_2 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_24 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_32 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_17 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bot_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => top_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_9 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g0_4 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bot_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_l_4 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => top_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_t_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bot_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => top_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => wire_logic_cluster/lc_5/out lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_9 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => top_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => wire_logic_cluster/lc_4/out lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_6 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_12 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_28 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => wire_logic_cluster/lc_1/out lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_8 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_29 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => wire_logic_cluster/lc_0/out lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_l_4 lc_trk_g0_1 (18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 0) routing wire_logic_cluster/lc_1/out lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_l_14 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_l_4 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing top_op_1 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 (18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_t_2 lc_trk_g2_5 (18 10) routing sp4_h_l_24 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_37 lc_trk_g2_5 (18 10) routing sp4_v_t_16 lc_trk_g2_5 (18 10) routing wire_logic_cluster/lc_5/out lc_trk_g2_5 (18 11) routing bnl_op_5 lc_trk_g2_5 (18 11) routing sp12_v_b_21 lc_trk_g2_5 (18 11) routing sp12_v_t_2 lc_trk_g2_5 (18 11) routing sp4_h_l_16 lc_trk_g2_5 (18 11) routing sp4_h_r_45 lc_trk_g2_5 (18 11) routing sp4_r_v_b_37 lc_trk_g2_5 (18 11) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 (18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 (18 12) routing sp4_h_r_33 lc_trk_g3_1 (18 12) routing sp4_h_r_41 lc_trk_g3_1 (18 12) routing sp4_v_b_33 lc_trk_g3_1 (18 12) routing sp4_v_t_12 lc_trk_g3_1 (18 12) routing wire_logic_cluster/lc_1/out lc_trk_g3_1 (18 13) routing bnl_op_1 lc_trk_g3_1 (18 13) routing sp12_v_b_1 lc_trk_g3_1 (18 13) routing sp12_v_t_14 lc_trk_g3_1 (18 13) routing sp4_h_r_25 lc_trk_g3_1 (18 13) routing sp4_h_r_41 lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 lc_trk_g3_1 (18 13) routing sp4_v_b_33 lc_trk_g3_1 (18 13) routing tnl_op_1 lc_trk_g3_1 (18 14) routing bnl_op_5 lc_trk_g3_5 (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_t_2 lc_trk_g3_5 (18 14) routing sp4_h_l_24 lc_trk_g3_5 (18 14) routing sp4_h_r_45 lc_trk_g3_5 (18 14) routing sp4_v_b_37 lc_trk_g3_5 (18 14) routing sp4_v_t_16 lc_trk_g3_5 (18 14) routing wire_logic_cluster/lc_5/out lc_trk_g3_5 (18 15) routing bnl_op_5 lc_trk_g3_5 (18 15) routing sp12_v_b_21 lc_trk_g3_5 (18 15) routing sp12_v_t_2 lc_trk_g3_5 (18 15) routing sp4_h_l_16 lc_trk_g3_5 (18 15) routing sp4_h_r_45 lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 lc_trk_g3_5 (18 15) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing tnl_op_5 lc_trk_g3_5 (18 2) routing bnr_op_5 lc_trk_g0_5 (18 2) routing lft_op_5 lc_trk_g0_5 (18 2) routing sp12_h_r_5 lc_trk_g0_5 (18 2) routing sp4_h_r_13 lc_trk_g0_5 (18 2) routing sp4_h_r_21 lc_trk_g0_5 (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 2) routing wire_logic_cluster/lc_5/out lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 (18 3) routing sp12_h_l_18 lc_trk_g0_5 (18 3) routing sp12_h_r_5 lc_trk_g0_5 (18 3) routing sp4_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 (18 3) routing sp4_v_b_13 lc_trk_g0_5 (18 3) routing top_op_5 lc_trk_g0_5 (18 4) routing bnr_op_1 lc_trk_g1_1 (18 4) routing lft_op_1 lc_trk_g1_1 (18 4) routing sp12_h_r_1 lc_trk_g1_1 (18 4) routing sp4_h_l_4 lc_trk_g1_1 (18 4) routing sp4_h_r_9 lc_trk_g1_1 (18 4) routing sp4_v_b_1 lc_trk_g1_1 (18 4) routing sp4_v_b_9 lc_trk_g1_1 (18 4) routing wire_logic_cluster/lc_1/out lc_trk_g1_1 (18 5) routing bnr_op_1 lc_trk_g1_1 (18 5) routing sp12_h_l_14 lc_trk_g1_1 (18 5) routing sp12_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_l_4 lc_trk_g1_1 (18 5) routing sp4_h_r_1 lc_trk_g1_1 (18 5) routing sp4_r_v_b_25 lc_trk_g1_1 (18 5) routing sp4_v_b_9 lc_trk_g1_1 (18 5) routing top_op_1 lc_trk_g1_1 (18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 (18 6) routing sp12_h_r_5 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_h_r_21 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 6) routing wire_logic_cluster/lc_5/out lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 (18 7) routing sp12_h_l_18 lc_trk_g1_5 (18 7) routing sp12_h_r_5 lc_trk_g1_5 (18 7) routing sp4_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 7) routing top_op_5 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_r_33 lc_trk_g2_1 (18 8) routing sp4_h_r_41 lc_trk_g2_1 (18 8) routing sp4_v_b_33 lc_trk_g2_1 (18 8) routing sp4_v_t_12 lc_trk_g2_1 (18 8) routing wire_logic_cluster/lc_1/out lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 (18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_t_14 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 (18 9) routing sp4_h_r_41 lc_trk_g2_1 (18 9) routing sp4_r_v_b_33 lc_trk_g2_1 (18 9) routing sp4_v_b_33 lc_trk_g2_1 (18 9) routing tnl_op_1 lc_trk_g2_1 (19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13 (19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 (19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_b_23 (19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 (19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13 (19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1 (19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 (19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_r_14 (19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_b_15 (19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_t_2 sp4_v_t_3 (19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 (19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_t_6 sp4_v_t_5 (19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 (19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_b_18 (19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_b_21 (19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_t_9 (2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5 (2 1) Column buffer control bit: LH_colbuf_cntl_1 (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 (2 11) Column buffer control bit: LH_colbuf_cntl_5 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 (2 13) Column buffer control bit: LH_colbuf_cntl_6 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 (2 15) Column buffer control bit: LH_colbuf_cntl_7 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_logic_cluster/lc_7/clk (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_logic_cluster/lc_7/clk (2 3) routing lc_trk_g0_0 wire_logic_cluster/lc_7/clk (2 3) routing lc_trk_g1_1 wire_logic_cluster/lc_7/clk (2 3) routing lc_trk_g2_0 wire_logic_cluster/lc_7/clk (2 3) routing lc_trk_g3_1 wire_logic_cluster/lc_7/clk (2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7 (2 5) Column buffer control bit: LH_colbuf_cntl_2 (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_r_19 (2 7) Column buffer control bit: LH_colbuf_cntl_3 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_l_9 (2 9) Column buffer control bit: LH_colbuf_cntl_4 (21 0) routing bnr_op_3 lc_trk_g0_3 (21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_r_3 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_h_r_19 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 0) routing wire_logic_cluster/lc_3/out lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 (21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp12_h_r_3 lc_trk_g0_3 (21 1) routing sp4_h_r_19 lc_trk_g0_3 (21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 (21 1) routing sp4_v_b_11 lc_trk_g0_3 (21 1) routing top_op_3 lc_trk_g0_3 (21 10) routing bnl_op_7 lc_trk_g2_7 (21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_b_7 lc_trk_g2_7 (21 10) routing sp4_h_l_34 lc_trk_g2_7 (21 10) routing sp4_h_r_39 lc_trk_g2_7 (21 10) routing sp4_v_t_18 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 (21 10) routing wire_logic_cluster/lc_7/out lc_trk_g2_7 (21 11) routing bnl_op_7 lc_trk_g2_7 (21 11) routing sp12_v_b_23 lc_trk_g2_7 (21 11) routing sp12_v_b_7 lc_trk_g2_7 (21 11) routing sp4_h_l_34 lc_trk_g2_7 (21 11) routing sp4_h_r_31 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_t_0 lc_trk_g3_3 (21 12) routing sp4_h_r_35 lc_trk_g3_3 (21 12) routing sp4_h_r_43 lc_trk_g3_3 (21 12) routing sp4_v_t_14 lc_trk_g3_3 (21 12) routing sp4_v_t_22 lc_trk_g3_3 (21 12) routing wire_logic_cluster/lc_3/out lc_trk_g3_3 (21 13) routing bnl_op_3 lc_trk_g3_3 (21 13) routing sp12_v_b_19 lc_trk_g3_3 (21 13) routing sp12_v_t_0 lc_trk_g3_3 (21 13) routing sp4_h_r_27 lc_trk_g3_3 (21 13) routing sp4_h_r_43 lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 lc_trk_g3_3 (21 13) routing sp4_v_t_22 lc_trk_g3_3 (21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_b_7 lc_trk_g3_7 (21 14) routing sp4_h_l_34 lc_trk_g3_7 (21 14) routing sp4_h_r_39 lc_trk_g3_7 (21 14) routing sp4_v_t_18 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 14) routing wire_logic_cluster/lc_7/out lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_b_23 lc_trk_g3_7 (21 15) routing sp12_v_b_7 lc_trk_g3_7 (21 15) routing sp4_h_l_34 lc_trk_g3_7 (21 15) routing sp4_h_r_31 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 (21 2) routing sp12_h_l_4 lc_trk_g0_7 (21 2) routing sp4_h_l_10 lc_trk_g0_7 (21 2) routing sp4_h_l_2 lc_trk_g0_7 (21 2) routing sp4_v_b_15 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing wire_logic_cluster/lc_7/out lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_4 lc_trk_g0_7 (21 3) routing sp12_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_l_10 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 (21 3) routing sp4_v_b_15 lc_trk_g0_7 (21 3) routing top_op_7 lc_trk_g0_7 (21 4) routing bnr_op_3 lc_trk_g1_3 (21 4) routing lft_op_3 lc_trk_g1_3 (21 4) routing sp12_h_r_3 lc_trk_g1_3 (21 4) routing sp4_h_r_11 lc_trk_g1_3 (21 4) routing sp4_h_r_19 lc_trk_g1_3 (21 4) routing sp4_v_b_11 lc_trk_g1_3 (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 4) routing wire_logic_cluster/lc_3/out lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp12_h_r_3 lc_trk_g1_3 (21 5) routing sp4_h_r_19 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 (21 5) routing top_op_3 lc_trk_g1_3 (21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_l_4 lc_trk_g1_7 (21 6) routing sp4_h_l_10 lc_trk_g1_7 (21 6) routing sp4_h_l_2 lc_trk_g1_7 (21 6) routing sp4_v_b_15 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing wire_logic_cluster/lc_7/out lc_trk_g1_7 (21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_4 lc_trk_g1_7 (21 7) routing sp12_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_l_10 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_b_15 lc_trk_g1_7 (21 7) routing top_op_7 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_t_0 lc_trk_g2_3 (21 8) routing sp4_h_r_35 lc_trk_g2_3 (21 8) routing sp4_h_r_43 lc_trk_g2_3 (21 8) routing sp4_v_t_14 lc_trk_g2_3 (21 8) routing sp4_v_t_22 lc_trk_g2_3 (21 8) routing wire_logic_cluster/lc_3/out lc_trk_g2_3 (21 9) routing bnl_op_3 lc_trk_g2_3 (21 9) routing sp12_v_b_19 lc_trk_g2_3 (21 9) routing sp12_v_t_0 lc_trk_g2_3 (21 9) routing sp4_h_r_27 lc_trk_g2_3 (21 9) routing sp4_h_r_43 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bot_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => top_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_34 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g2_6 (22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_39 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_38 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g3_6 (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => bot_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => top_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bot_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => top_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g1_3 (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => bot_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bot_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_15 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => top_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => wire_logic_cluster/lc_7/out lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => wire_logic_cluster/lc_6/out lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => wire_logic_cluster/lc_3/out lc_trk_g2_3 (22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_42 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => wire_logic_cluster/lc_2/out lc_trk_g2_2 (23 0) routing sp12_h_l_16 lc_trk_g0_3 (23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_19 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_19 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 (23 1) routing sp12_h_l_17 lc_trk_g0_2 (23 1) routing sp12_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_l_7 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 (23 1) routing sp4_v_b_10 lc_trk_g0_2 (23 1) routing sp4_v_b_18 lc_trk_g0_2 (23 1) routing sp4_v_b_2 lc_trk_g0_2 (23 10) routing sp12_v_b_23 lc_trk_g2_7 (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp4_h_l_34 lc_trk_g2_7 (23 10) routing sp4_h_r_31 lc_trk_g2_7 (23 10) routing sp4_h_r_39 lc_trk_g2_7 (23 10) routing sp4_v_b_47 lc_trk_g2_7 (23 10) routing sp4_v_t_18 lc_trk_g2_7 (23 10) routing sp4_v_t_26 lc_trk_g2_7 (23 11) routing sp12_v_b_14 lc_trk_g2_6 (23 11) routing sp12_v_t_21 lc_trk_g2_6 (23 11) routing sp4_h_r_30 lc_trk_g2_6 (23 11) routing sp4_h_r_38 lc_trk_g2_6 (23 11) routing sp4_h_r_46 lc_trk_g2_6 (23 11) routing sp4_v_b_30 lc_trk_g2_6 (23 11) routing sp4_v_b_38 lc_trk_g2_6 (23 11) routing sp4_v_b_46 lc_trk_g2_6 (23 12) routing sp12_v_b_11 lc_trk_g3_3 (23 12) routing sp12_v_b_19 lc_trk_g3_3 (23 12) routing sp4_h_r_27 lc_trk_g3_3 (23 12) routing sp4_h_r_35 lc_trk_g3_3 (23 12) routing sp4_h_r_43 lc_trk_g3_3 (23 12) routing sp4_v_t_14 lc_trk_g3_3 (23 12) routing sp4_v_t_22 lc_trk_g3_3 (23 12) routing sp4_v_t_30 lc_trk_g3_3 (23 13) routing sp12_v_b_18 lc_trk_g3_2 (23 13) routing sp12_v_t_9 lc_trk_g3_2 (23 13) routing sp4_h_l_15 lc_trk_g3_2 (23 13) routing sp4_h_r_34 lc_trk_g3_2 (23 13) routing sp4_h_r_42 lc_trk_g3_2 (23 13) routing sp4_v_b_26 lc_trk_g3_2 (23 13) routing sp4_v_b_42 lc_trk_g3_2 (23 13) routing sp4_v_t_23 lc_trk_g3_2 (23 14) routing sp12_v_b_23 lc_trk_g3_7 (23 14) routing sp12_v_t_12 lc_trk_g3_7 (23 14) routing sp4_h_l_34 lc_trk_g3_7 (23 14) routing sp4_h_r_31 lc_trk_g3_7 (23 14) routing sp4_h_r_39 lc_trk_g3_7 (23 14) routing sp4_v_b_47 lc_trk_g3_7 (23 14) routing sp4_v_t_18 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 15) routing sp12_v_b_14 lc_trk_g3_6 (23 15) routing sp12_v_t_21 lc_trk_g3_6 (23 15) routing sp4_h_r_30 lc_trk_g3_6 (23 15) routing sp4_h_r_38 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_30 lc_trk_g3_6 (23 15) routing sp4_v_b_38 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 (23 2) routing sp12_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_l_10 lc_trk_g0_7 (23 2) routing sp4_h_l_2 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_15 lc_trk_g0_7 (23 2) routing sp4_v_b_23 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 3) routing sp12_h_l_21 lc_trk_g0_6 (23 3) routing sp12_h_r_14 lc_trk_g0_6 (23 3) routing sp4_h_l_11 lc_trk_g0_6 (23 3) routing sp4_h_r_14 lc_trk_g0_6 (23 3) routing sp4_h_r_6 lc_trk_g0_6 (23 3) routing sp4_v_b_22 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 (23 3) routing sp4_v_t_3 lc_trk_g0_6 (23 4) routing sp12_h_l_16 lc_trk_g1_3 (23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_19 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 (23 4) routing sp4_v_b_11 lc_trk_g1_3 (23 4) routing sp4_v_b_19 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 5) routing sp12_h_l_17 lc_trk_g1_2 (23 5) routing sp12_h_r_10 lc_trk_g1_2 (23 5) routing sp4_h_l_7 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 (23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_18 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 6) routing sp12_h_l_12 lc_trk_g1_7 (23 6) routing sp12_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_l_10 lc_trk_g1_7 (23 6) routing sp4_h_l_2 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 (23 6) routing sp4_v_b_15 lc_trk_g1_7 (23 6) routing sp4_v_b_23 lc_trk_g1_7 (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 7) routing sp12_h_l_21 lc_trk_g1_6 (23 7) routing sp12_h_r_14 lc_trk_g1_6 (23 7) routing sp4_h_l_11 lc_trk_g1_6 (23 7) routing sp4_h_r_14 lc_trk_g1_6 (23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_22 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 7) routing sp4_v_t_3 lc_trk_g1_6 (23 8) routing sp12_v_b_11 lc_trk_g2_3 (23 8) routing sp12_v_b_19 lc_trk_g2_3 (23 8) routing sp4_h_r_27 lc_trk_g2_3 (23 8) routing sp4_h_r_35 lc_trk_g2_3 (23 8) routing sp4_h_r_43 lc_trk_g2_3 (23 8) routing sp4_v_t_14 lc_trk_g2_3 (23 8) routing sp4_v_t_22 lc_trk_g2_3 (23 8) routing sp4_v_t_30 lc_trk_g2_3 (23 9) routing sp12_v_b_18 lc_trk_g2_2 (23 9) routing sp12_v_t_9 lc_trk_g2_2 (23 9) routing sp4_h_l_15 lc_trk_g2_2 (23 9) routing sp4_h_r_34 lc_trk_g2_2 (23 9) routing sp4_h_r_42 lc_trk_g2_2 (23 9) routing sp4_v_b_26 lc_trk_g2_2 (23 9) routing sp4_v_b_42 lc_trk_g2_2 (23 9) routing sp4_v_t_23 lc_trk_g2_2 (24 0) routing bot_op_3 lc_trk_g0_3 (24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_r_3 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_19 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_b_19 lc_trk_g0_3 (24 0) routing top_op_3 lc_trk_g0_3 (24 1) routing bot_op_2 lc_trk_g0_2 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_r_2 lc_trk_g0_2 (24 1) routing sp4_h_l_7 lc_trk_g0_2 (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_b_18 lc_trk_g0_2 (24 1) routing top_op_2 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_b_7 lc_trk_g2_7 (24 10) routing sp4_h_l_34 lc_trk_g2_7 (24 10) routing sp4_h_r_31 lc_trk_g2_7 (24 10) routing sp4_h_r_39 lc_trk_g2_7 (24 10) routing sp4_v_b_47 lc_trk_g2_7 (24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_b_6 lc_trk_g2_6 (24 11) routing sp4_h_r_30 lc_trk_g2_6 (24 11) routing sp4_h_r_38 lc_trk_g2_6 (24 11) routing sp4_h_r_46 lc_trk_g2_6 (24 11) routing sp4_v_b_46 lc_trk_g2_6 (24 11) routing tnl_op_6 lc_trk_g2_6 (24 11) routing tnr_op_6 lc_trk_g2_6 (24 12) routing rgt_op_3 lc_trk_g3_3 (24 12) routing sp12_v_t_0 lc_trk_g3_3 (24 12) routing sp4_h_r_27 lc_trk_g3_3 (24 12) routing sp4_h_r_35 lc_trk_g3_3 (24 12) routing sp4_h_r_43 lc_trk_g3_3 (24 12) routing sp4_v_t_30 lc_trk_g3_3 (24 12) routing tnl_op_3 lc_trk_g3_3 (24 12) routing tnr_op_3 lc_trk_g3_3 (24 13) routing rgt_op_2 lc_trk_g3_2 (24 13) routing sp12_v_t_1 lc_trk_g3_2 (24 13) routing sp4_h_l_15 lc_trk_g3_2 (24 13) routing sp4_h_r_34 lc_trk_g3_2 (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_b_42 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 (24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_b_7 lc_trk_g3_7 (24 14) routing sp4_h_l_34 lc_trk_g3_7 (24 14) routing sp4_h_r_31 lc_trk_g3_7 (24 14) routing sp4_h_r_39 lc_trk_g3_7 (24 14) routing sp4_v_b_47 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 (24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_b_6 lc_trk_g3_6 (24 15) routing sp4_h_r_30 lc_trk_g3_6 (24 15) routing sp4_h_r_38 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing bot_op_7 lc_trk_g0_7 (24 2) routing lft_op_7 lc_trk_g0_7 (24 2) routing sp12_h_l_4 lc_trk_g0_7 (24 2) routing sp4_h_l_10 lc_trk_g0_7 (24 2) routing sp4_h_l_2 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_b_23 lc_trk_g0_7 (24 2) routing top_op_7 lc_trk_g0_7 (24 3) routing bot_op_6 lc_trk_g0_6 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_11 lc_trk_g0_6 (24 3) routing sp4_h_r_14 lc_trk_g0_6 (24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_b_22 lc_trk_g0_6 (24 3) routing top_op_6 lc_trk_g0_6 (24 4) routing bot_op_3 lc_trk_g1_3 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_r_3 lc_trk_g1_3 (24 4) routing sp4_h_r_11 lc_trk_g1_3 (24 4) routing sp4_h_r_19 lc_trk_g1_3 (24 4) routing sp4_h_r_3 lc_trk_g1_3 (24 4) routing sp4_v_b_19 lc_trk_g1_3 (24 4) routing top_op_3 lc_trk_g1_3 (24 5) routing bot_op_2 lc_trk_g1_2 (24 5) routing lft_op_2 lc_trk_g1_2 (24 5) routing sp12_h_r_2 lc_trk_g1_2 (24 5) routing sp4_h_l_7 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 (24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_b_18 lc_trk_g1_2 (24 5) routing top_op_2 lc_trk_g1_2 (24 6) routing bot_op_7 lc_trk_g1_7 (24 6) routing lft_op_7 lc_trk_g1_7 (24 6) routing sp12_h_l_4 lc_trk_g1_7 (24 6) routing sp4_h_l_10 lc_trk_g1_7 (24 6) routing sp4_h_l_2 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 (24 6) routing sp4_v_b_23 lc_trk_g1_7 (24 6) routing top_op_7 lc_trk_g1_7 (24 7) routing bot_op_6 lc_trk_g1_6 (24 7) routing lft_op_6 lc_trk_g1_6 (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_11 lc_trk_g1_6 (24 7) routing sp4_h_r_14 lc_trk_g1_6 (24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_b_22 lc_trk_g1_6 (24 7) routing top_op_6 lc_trk_g1_6 (24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_t_0 lc_trk_g2_3 (24 8) routing sp4_h_r_27 lc_trk_g2_3 (24 8) routing sp4_h_r_35 lc_trk_g2_3 (24 8) routing sp4_h_r_43 lc_trk_g2_3 (24 8) routing sp4_v_t_30 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 (24 8) routing tnr_op_3 lc_trk_g2_3 (24 9) routing rgt_op_2 lc_trk_g2_2 (24 9) routing sp12_v_t_1 lc_trk_g2_2 (24 9) routing sp4_h_l_15 lc_trk_g2_2 (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_b_42 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_r_2 lc_trk_g0_2 (25 0) routing sp4_h_l_7 lc_trk_g0_2 (25 0) routing sp4_h_r_10 lc_trk_g0_2 (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 (25 0) routing wire_logic_cluster/lc_2/out lc_trk_g0_2 (25 1) routing bnr_op_2 lc_trk_g0_2 (25 1) routing sp12_h_l_17 lc_trk_g0_2 (25 1) routing sp12_h_r_2 lc_trk_g0_2 (25 1) routing sp4_h_l_7 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 (25 1) routing top_op_2 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_b_6 lc_trk_g2_6 (25 10) routing sp4_h_r_38 lc_trk_g2_6 (25 10) routing sp4_h_r_46 lc_trk_g2_6 (25 10) routing sp4_v_b_30 lc_trk_g2_6 (25 10) routing sp4_v_b_38 lc_trk_g2_6 (25 10) routing wire_logic_cluster/lc_6/out lc_trk_g2_6 (25 11) routing bnl_op_6 lc_trk_g2_6 (25 11) routing sp12_v_b_6 lc_trk_g2_6 (25 11) routing sp12_v_t_21 lc_trk_g2_6 (25 11) routing sp4_h_r_30 lc_trk_g2_6 (25 11) routing sp4_h_r_46 lc_trk_g2_6 (25 11) routing sp4_r_v_b_38 lc_trk_g2_6 (25 11) routing sp4_v_b_38 lc_trk_g2_6 (25 11) routing tnl_op_6 lc_trk_g2_6 (25 12) routing bnl_op_2 lc_trk_g3_2 (25 12) routing rgt_op_2 lc_trk_g3_2 (25 12) routing sp12_v_t_1 lc_trk_g3_2 (25 12) routing sp4_h_r_34 lc_trk_g3_2 (25 12) routing sp4_h_r_42 lc_trk_g3_2 (25 12) routing sp4_v_b_26 lc_trk_g3_2 (25 12) routing sp4_v_t_23 lc_trk_g3_2 (25 12) routing wire_logic_cluster/lc_2/out lc_trk_g3_2 (25 13) routing bnl_op_2 lc_trk_g3_2 (25 13) routing sp12_v_b_18 lc_trk_g3_2 (25 13) routing sp12_v_t_1 lc_trk_g3_2 (25 13) routing sp4_h_l_15 lc_trk_g3_2 (25 13) routing sp4_h_r_42 lc_trk_g3_2 (25 13) routing sp4_r_v_b_42 lc_trk_g3_2 (25 13) routing sp4_v_t_23 lc_trk_g3_2 (25 13) routing tnl_op_2 lc_trk_g3_2 (25 14) routing bnl_op_6 lc_trk_g3_6 (25 14) routing rgt_op_6 lc_trk_g3_6 (25 14) routing sp12_v_b_6 lc_trk_g3_6 (25 14) routing sp4_h_r_38 lc_trk_g3_6 (25 14) routing sp4_h_r_46 lc_trk_g3_6 (25 14) routing sp4_v_b_30 lc_trk_g3_6 (25 14) routing sp4_v_b_38 lc_trk_g3_6 (25 14) routing wire_logic_cluster/lc_6/out lc_trk_g3_6 (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_6 lc_trk_g3_6 (25 15) routing sp12_v_t_21 lc_trk_g3_6 (25 15) routing sp4_h_r_30 lc_trk_g3_6 (25 15) routing sp4_h_r_46 lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_b_38 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 (25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 (25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_11 lc_trk_g0_6 (25 2) routing sp4_h_r_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 2) routing sp4_v_t_3 lc_trk_g0_6 (25 2) routing wire_logic_cluster/lc_6/out lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_21 lc_trk_g0_6 (25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp4_h_l_11 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 (25 3) routing sp4_v_t_3 lc_trk_g0_6 (25 3) routing top_op_6 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_r_2 lc_trk_g1_2 (25 4) routing sp4_h_l_7 lc_trk_g1_2 (25 4) routing sp4_h_r_10 lc_trk_g1_2 (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 4) routing wire_logic_cluster/lc_2/out lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 (25 5) routing sp12_h_l_17 lc_trk_g1_2 (25 5) routing sp12_h_r_2 lc_trk_g1_2 (25 5) routing sp4_h_l_7 lc_trk_g1_2 (25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 (25 5) routing top_op_2 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 (25 6) routing sp4_h_l_11 lc_trk_g1_6 (25 6) routing sp4_h_r_14 lc_trk_g1_6 (25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 6) routing sp4_v_t_3 lc_trk_g1_6 (25 6) routing wire_logic_cluster/lc_6/out lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 (25 7) routing sp12_h_l_21 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp4_h_l_11 lc_trk_g1_6 (25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_t_3 lc_trk_g1_6 (25 7) routing top_op_6 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_t_1 lc_trk_g2_2 (25 8) routing sp4_h_r_34 lc_trk_g2_2 (25 8) routing sp4_h_r_42 lc_trk_g2_2 (25 8) routing sp4_v_b_26 lc_trk_g2_2 (25 8) routing sp4_v_t_23 lc_trk_g2_2 (25 8) routing wire_logic_cluster/lc_2/out lc_trk_g2_2 (25 9) routing bnl_op_2 lc_trk_g2_2 (25 9) routing sp12_v_b_18 lc_trk_g2_2 (25 9) routing sp12_v_t_1 lc_trk_g2_2 (25 9) routing sp4_h_l_15 lc_trk_g2_2 (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_t_23 lc_trk_g2_2 (25 9) routing tnl_op_2 lc_trk_g2_2 (26 0) routing lc_trk_g0_4 wire_logic_cluster/lc_0/in_0 (26 0) routing lc_trk_g0_6 wire_logic_cluster/lc_0/in_0 (26 0) routing lc_trk_g1_5 wire_logic_cluster/lc_0/in_0 (26 0) routing lc_trk_g1_7 wire_logic_cluster/lc_0/in_0 (26 0) routing lc_trk_g2_4 wire_logic_cluster/lc_0/in_0 (26 0) routing lc_trk_g2_6 wire_logic_cluster/lc_0/in_0 (26 0) routing lc_trk_g3_5 wire_logic_cluster/lc_0/in_0 (26 0) routing lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g0_2 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g0_6 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g1_3 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g1_7 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g2_2 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g2_6 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g3_3 wire_logic_cluster/lc_0/in_0 (26 1) routing lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 (26 10) routing lc_trk_g0_5 wire_logic_cluster/lc_5/in_0 (26 10) routing lc_trk_g0_7 wire_logic_cluster/lc_5/in_0 (26 10) routing lc_trk_g1_4 wire_logic_cluster/lc_5/in_0 (26 10) routing lc_trk_g1_6 wire_logic_cluster/lc_5/in_0 (26 10) routing lc_trk_g2_5 wire_logic_cluster/lc_5/in_0 (26 10) routing lc_trk_g2_7 wire_logic_cluster/lc_5/in_0 (26 10) routing lc_trk_g3_4 wire_logic_cluster/lc_5/in_0 (26 10) routing lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g0_3 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g0_7 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g1_2 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g1_6 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g2_3 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g2_7 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g3_2 wire_logic_cluster/lc_5/in_0 (26 11) routing lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 (26 12) routing lc_trk_g0_4 wire_logic_cluster/lc_6/in_0 (26 12) routing lc_trk_g0_6 wire_logic_cluster/lc_6/in_0 (26 12) routing lc_trk_g1_5 wire_logic_cluster/lc_6/in_0 (26 12) routing lc_trk_g1_7 wire_logic_cluster/lc_6/in_0 (26 12) routing lc_trk_g2_4 wire_logic_cluster/lc_6/in_0 (26 12) routing lc_trk_g2_6 wire_logic_cluster/lc_6/in_0 (26 12) routing lc_trk_g3_5 wire_logic_cluster/lc_6/in_0 (26 12) routing lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g0_2 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g0_6 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g1_3 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g1_7 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g2_2 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g2_6 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g3_3 wire_logic_cluster/lc_6/in_0 (26 13) routing lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 (26 14) routing lc_trk_g0_5 wire_logic_cluster/lc_7/in_0 (26 14) routing lc_trk_g0_7 wire_logic_cluster/lc_7/in_0 (26 14) routing lc_trk_g1_4 wire_logic_cluster/lc_7/in_0 (26 14) routing lc_trk_g1_6 wire_logic_cluster/lc_7/in_0 (26 14) routing lc_trk_g2_5 wire_logic_cluster/lc_7/in_0 (26 14) routing lc_trk_g2_7 wire_logic_cluster/lc_7/in_0 (26 14) routing lc_trk_g3_4 wire_logic_cluster/lc_7/in_0 (26 14) routing lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g0_3 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g0_7 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g1_2 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g1_6 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g2_3 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g2_7 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g3_2 wire_logic_cluster/lc_7/in_0 (26 15) routing lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 (26 2) routing lc_trk_g0_5 wire_logic_cluster/lc_1/in_0 (26 2) routing lc_trk_g0_7 wire_logic_cluster/lc_1/in_0 (26 2) routing lc_trk_g1_4 wire_logic_cluster/lc_1/in_0 (26 2) routing lc_trk_g1_6 wire_logic_cluster/lc_1/in_0 (26 2) routing lc_trk_g2_5 wire_logic_cluster/lc_1/in_0 (26 2) routing lc_trk_g2_7 wire_logic_cluster/lc_1/in_0 (26 2) routing lc_trk_g3_4 wire_logic_cluster/lc_1/in_0 (26 2) routing lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g0_3 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g0_7 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g1_2 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g1_6 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g2_3 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g2_7 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g3_2 wire_logic_cluster/lc_1/in_0 (26 3) routing lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 (26 4) routing lc_trk_g0_4 wire_logic_cluster/lc_2/in_0 (26 4) routing lc_trk_g0_6 wire_logic_cluster/lc_2/in_0 (26 4) routing lc_trk_g1_5 wire_logic_cluster/lc_2/in_0 (26 4) routing lc_trk_g1_7 wire_logic_cluster/lc_2/in_0 (26 4) routing lc_trk_g2_4 wire_logic_cluster/lc_2/in_0 (26 4) routing lc_trk_g2_6 wire_logic_cluster/lc_2/in_0 (26 4) routing lc_trk_g3_5 wire_logic_cluster/lc_2/in_0 (26 4) routing lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g0_2 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g0_6 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g1_3 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g1_7 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g2_2 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g2_6 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g3_3 wire_logic_cluster/lc_2/in_0 (26 5) routing lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 (26 6) routing lc_trk_g0_5 wire_logic_cluster/lc_3/in_0 (26 6) routing lc_trk_g0_7 wire_logic_cluster/lc_3/in_0 (26 6) routing lc_trk_g1_4 wire_logic_cluster/lc_3/in_0 (26 6) routing lc_trk_g1_6 wire_logic_cluster/lc_3/in_0 (26 6) routing lc_trk_g2_5 wire_logic_cluster/lc_3/in_0 (26 6) routing lc_trk_g2_7 wire_logic_cluster/lc_3/in_0 (26 6) routing lc_trk_g3_4 wire_logic_cluster/lc_3/in_0 (26 6) routing lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g0_3 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g0_7 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g1_2 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g1_6 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g2_3 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g2_7 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g3_2 wire_logic_cluster/lc_3/in_0 (26 7) routing lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 (26 8) routing lc_trk_g0_4 wire_logic_cluster/lc_4/in_0 (26 8) routing lc_trk_g0_6 wire_logic_cluster/lc_4/in_0 (26 8) routing lc_trk_g1_5 wire_logic_cluster/lc_4/in_0 (26 8) routing lc_trk_g1_7 wire_logic_cluster/lc_4/in_0 (26 8) routing lc_trk_g2_4 wire_logic_cluster/lc_4/in_0 (26 8) routing lc_trk_g2_6 wire_logic_cluster/lc_4/in_0 (26 8) routing lc_trk_g3_5 wire_logic_cluster/lc_4/in_0 (26 8) routing lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g0_2 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g0_6 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g1_3 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g1_7 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g2_2 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g2_6 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g3_3 wire_logic_cluster/lc_4/in_0 (26 9) routing lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 (27 0) routing lc_trk_g1_0 wire_logic_cluster/lc_0/in_1 (27 0) routing lc_trk_g1_2 wire_logic_cluster/lc_0/in_1 (27 0) routing lc_trk_g1_4 wire_logic_cluster/lc_0/in_1 (27 0) routing lc_trk_g1_6 wire_logic_cluster/lc_0/in_1 (27 0) routing lc_trk_g3_0 wire_logic_cluster/lc_0/in_1 (27 0) routing lc_trk_g3_2 wire_logic_cluster/lc_0/in_1 (27 0) routing lc_trk_g3_4 wire_logic_cluster/lc_0/in_1 (27 0) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 (27 1) routing lc_trk_g1_1 wire_logic_cluster/lc_0/in_0 (27 1) routing lc_trk_g1_3 wire_logic_cluster/lc_0/in_0 (27 1) routing lc_trk_g1_5 wire_logic_cluster/lc_0/in_0 (27 1) routing lc_trk_g1_7 wire_logic_cluster/lc_0/in_0 (27 1) routing lc_trk_g3_1 wire_logic_cluster/lc_0/in_0 (27 1) routing lc_trk_g3_3 wire_logic_cluster/lc_0/in_0 (27 1) routing lc_trk_g3_5 wire_logic_cluster/lc_0/in_0 (27 1) routing lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 (27 10) routing lc_trk_g1_1 wire_logic_cluster/lc_5/in_1 (27 10) routing lc_trk_g1_3 wire_logic_cluster/lc_5/in_1 (27 10) routing lc_trk_g1_5 wire_logic_cluster/lc_5/in_1 (27 10) routing lc_trk_g1_7 wire_logic_cluster/lc_5/in_1 (27 10) routing lc_trk_g3_1 wire_logic_cluster/lc_5/in_1 (27 10) routing lc_trk_g3_3 wire_logic_cluster/lc_5/in_1 (27 10) routing lc_trk_g3_5 wire_logic_cluster/lc_5/in_1 (27 10) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 (27 11) routing lc_trk_g1_0 wire_logic_cluster/lc_5/in_0 (27 11) routing lc_trk_g1_2 wire_logic_cluster/lc_5/in_0 (27 11) routing lc_trk_g1_4 wire_logic_cluster/lc_5/in_0 (27 11) routing lc_trk_g1_6 wire_logic_cluster/lc_5/in_0 (27 11) routing lc_trk_g3_0 wire_logic_cluster/lc_5/in_0 (27 11) routing lc_trk_g3_2 wire_logic_cluster/lc_5/in_0 (27 11) routing lc_trk_g3_4 wire_logic_cluster/lc_5/in_0 (27 11) routing lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 (27 12) routing lc_trk_g1_0 wire_logic_cluster/lc_6/in_1 (27 12) routing lc_trk_g1_2 wire_logic_cluster/lc_6/in_1 (27 12) routing lc_trk_g1_4 wire_logic_cluster/lc_6/in_1 (27 12) routing lc_trk_g1_6 wire_logic_cluster/lc_6/in_1 (27 12) routing lc_trk_g3_0 wire_logic_cluster/lc_6/in_1 (27 12) routing lc_trk_g3_2 wire_logic_cluster/lc_6/in_1 (27 12) routing lc_trk_g3_4 wire_logic_cluster/lc_6/in_1 (27 12) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 (27 13) routing lc_trk_g1_1 wire_logic_cluster/lc_6/in_0 (27 13) routing lc_trk_g1_3 wire_logic_cluster/lc_6/in_0 (27 13) routing lc_trk_g1_5 wire_logic_cluster/lc_6/in_0 (27 13) routing lc_trk_g1_7 wire_logic_cluster/lc_6/in_0 (27 13) routing lc_trk_g3_1 wire_logic_cluster/lc_6/in_0 (27 13) routing lc_trk_g3_3 wire_logic_cluster/lc_6/in_0 (27 13) routing lc_trk_g3_5 wire_logic_cluster/lc_6/in_0 (27 13) routing lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 (27 14) routing lc_trk_g1_1 wire_logic_cluster/lc_7/in_1 (27 14) routing lc_trk_g1_3 wire_logic_cluster/lc_7/in_1 (27 14) routing lc_trk_g1_5 wire_logic_cluster/lc_7/in_1 (27 14) routing lc_trk_g1_7 wire_logic_cluster/lc_7/in_1 (27 14) routing lc_trk_g3_1 wire_logic_cluster/lc_7/in_1 (27 14) routing lc_trk_g3_3 wire_logic_cluster/lc_7/in_1 (27 14) routing lc_trk_g3_5 wire_logic_cluster/lc_7/in_1 (27 14) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 (27 15) routing lc_trk_g1_0 wire_logic_cluster/lc_7/in_0 (27 15) routing lc_trk_g1_2 wire_logic_cluster/lc_7/in_0 (27 15) routing lc_trk_g1_4 wire_logic_cluster/lc_7/in_0 (27 15) routing lc_trk_g1_6 wire_logic_cluster/lc_7/in_0 (27 15) routing lc_trk_g3_0 wire_logic_cluster/lc_7/in_0 (27 15) routing lc_trk_g3_2 wire_logic_cluster/lc_7/in_0 (27 15) routing lc_trk_g3_4 wire_logic_cluster/lc_7/in_0 (27 15) routing lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 (27 2) routing lc_trk_g1_1 wire_logic_cluster/lc_1/in_1 (27 2) routing lc_trk_g1_3 wire_logic_cluster/lc_1/in_1 (27 2) routing lc_trk_g1_5 wire_logic_cluster/lc_1/in_1 (27 2) routing lc_trk_g1_7 wire_logic_cluster/lc_1/in_1 (27 2) routing lc_trk_g3_1 wire_logic_cluster/lc_1/in_1 (27 2) routing lc_trk_g3_3 wire_logic_cluster/lc_1/in_1 (27 2) routing lc_trk_g3_5 wire_logic_cluster/lc_1/in_1 (27 2) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 (27 3) routing lc_trk_g1_0 wire_logic_cluster/lc_1/in_0 (27 3) routing lc_trk_g1_2 wire_logic_cluster/lc_1/in_0 (27 3) routing lc_trk_g1_4 wire_logic_cluster/lc_1/in_0 (27 3) routing lc_trk_g1_6 wire_logic_cluster/lc_1/in_0 (27 3) routing lc_trk_g3_0 wire_logic_cluster/lc_1/in_0 (27 3) routing lc_trk_g3_2 wire_logic_cluster/lc_1/in_0 (27 3) routing lc_trk_g3_4 wire_logic_cluster/lc_1/in_0 (27 3) routing lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 (27 4) routing lc_trk_g1_0 wire_logic_cluster/lc_2/in_1 (27 4) routing lc_trk_g1_2 wire_logic_cluster/lc_2/in_1 (27 4) routing lc_trk_g1_4 wire_logic_cluster/lc_2/in_1 (27 4) routing lc_trk_g1_6 wire_logic_cluster/lc_2/in_1 (27 4) routing lc_trk_g3_0 wire_logic_cluster/lc_2/in_1 (27 4) routing lc_trk_g3_2 wire_logic_cluster/lc_2/in_1 (27 4) routing lc_trk_g3_4 wire_logic_cluster/lc_2/in_1 (27 4) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 (27 5) routing lc_trk_g1_1 wire_logic_cluster/lc_2/in_0 (27 5) routing lc_trk_g1_3 wire_logic_cluster/lc_2/in_0 (27 5) routing lc_trk_g1_5 wire_logic_cluster/lc_2/in_0 (27 5) routing lc_trk_g1_7 wire_logic_cluster/lc_2/in_0 (27 5) routing lc_trk_g3_1 wire_logic_cluster/lc_2/in_0 (27 5) routing lc_trk_g3_3 wire_logic_cluster/lc_2/in_0 (27 5) routing lc_trk_g3_5 wire_logic_cluster/lc_2/in_0 (27 5) routing lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 (27 6) routing lc_trk_g1_1 wire_logic_cluster/lc_3/in_1 (27 6) routing lc_trk_g1_3 wire_logic_cluster/lc_3/in_1 (27 6) routing lc_trk_g1_5 wire_logic_cluster/lc_3/in_1 (27 6) routing lc_trk_g1_7 wire_logic_cluster/lc_3/in_1 (27 6) routing lc_trk_g3_1 wire_logic_cluster/lc_3/in_1 (27 6) routing lc_trk_g3_3 wire_logic_cluster/lc_3/in_1 (27 6) routing lc_trk_g3_5 wire_logic_cluster/lc_3/in_1 (27 6) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 (27 7) routing lc_trk_g1_0 wire_logic_cluster/lc_3/in_0 (27 7) routing lc_trk_g1_2 wire_logic_cluster/lc_3/in_0 (27 7) routing lc_trk_g1_4 wire_logic_cluster/lc_3/in_0 (27 7) routing lc_trk_g1_6 wire_logic_cluster/lc_3/in_0 (27 7) routing lc_trk_g3_0 wire_logic_cluster/lc_3/in_0 (27 7) routing lc_trk_g3_2 wire_logic_cluster/lc_3/in_0 (27 7) routing lc_trk_g3_4 wire_logic_cluster/lc_3/in_0 (27 7) routing lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 (27 8) routing lc_trk_g1_0 wire_logic_cluster/lc_4/in_1 (27 8) routing lc_trk_g1_2 wire_logic_cluster/lc_4/in_1 (27 8) routing lc_trk_g1_4 wire_logic_cluster/lc_4/in_1 (27 8) routing lc_trk_g1_6 wire_logic_cluster/lc_4/in_1 (27 8) routing lc_trk_g3_0 wire_logic_cluster/lc_4/in_1 (27 8) routing lc_trk_g3_2 wire_logic_cluster/lc_4/in_1 (27 8) routing lc_trk_g3_4 wire_logic_cluster/lc_4/in_1 (27 8) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 (27 9) routing lc_trk_g1_1 wire_logic_cluster/lc_4/in_0 (27 9) routing lc_trk_g1_3 wire_logic_cluster/lc_4/in_0 (27 9) routing lc_trk_g1_5 wire_logic_cluster/lc_4/in_0 (27 9) routing lc_trk_g1_7 wire_logic_cluster/lc_4/in_0 (27 9) routing lc_trk_g3_1 wire_logic_cluster/lc_4/in_0 (27 9) routing lc_trk_g3_3 wire_logic_cluster/lc_4/in_0 (27 9) routing lc_trk_g3_5 wire_logic_cluster/lc_4/in_0 (27 9) routing lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 (28 0) routing lc_trk_g2_1 wire_logic_cluster/lc_0/in_1 (28 0) routing lc_trk_g2_3 wire_logic_cluster/lc_0/in_1 (28 0) routing lc_trk_g2_5 wire_logic_cluster/lc_0/in_1 (28 0) routing lc_trk_g2_7 wire_logic_cluster/lc_0/in_1 (28 0) routing lc_trk_g3_0 wire_logic_cluster/lc_0/in_1 (28 0) routing lc_trk_g3_2 wire_logic_cluster/lc_0/in_1 (28 0) routing lc_trk_g3_4 wire_logic_cluster/lc_0/in_1 (28 0) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 (28 1) routing lc_trk_g2_0 wire_logic_cluster/lc_0/in_0 (28 1) routing lc_trk_g2_2 wire_logic_cluster/lc_0/in_0 (28 1) routing lc_trk_g2_4 wire_logic_cluster/lc_0/in_0 (28 1) routing lc_trk_g2_6 wire_logic_cluster/lc_0/in_0 (28 1) routing lc_trk_g3_1 wire_logic_cluster/lc_0/in_0 (28 1) routing lc_trk_g3_3 wire_logic_cluster/lc_0/in_0 (28 1) routing lc_trk_g3_5 wire_logic_cluster/lc_0/in_0 (28 1) routing lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 (28 10) routing lc_trk_g2_0 wire_logic_cluster/lc_5/in_1 (28 10) routing lc_trk_g2_2 wire_logic_cluster/lc_5/in_1 (28 10) routing lc_trk_g2_4 wire_logic_cluster/lc_5/in_1 (28 10) routing lc_trk_g2_6 wire_logic_cluster/lc_5/in_1 (28 10) routing lc_trk_g3_1 wire_logic_cluster/lc_5/in_1 (28 10) routing lc_trk_g3_3 wire_logic_cluster/lc_5/in_1 (28 10) routing lc_trk_g3_5 wire_logic_cluster/lc_5/in_1 (28 10) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 (28 11) routing lc_trk_g2_1 wire_logic_cluster/lc_5/in_0 (28 11) routing lc_trk_g2_3 wire_logic_cluster/lc_5/in_0 (28 11) routing lc_trk_g2_5 wire_logic_cluster/lc_5/in_0 (28 11) routing lc_trk_g2_7 wire_logic_cluster/lc_5/in_0 (28 11) routing lc_trk_g3_0 wire_logic_cluster/lc_5/in_0 (28 11) routing lc_trk_g3_2 wire_logic_cluster/lc_5/in_0 (28 11) routing lc_trk_g3_4 wire_logic_cluster/lc_5/in_0 (28 11) routing lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 (28 12) routing lc_trk_g2_1 wire_logic_cluster/lc_6/in_1 (28 12) routing lc_trk_g2_3 wire_logic_cluster/lc_6/in_1 (28 12) routing lc_trk_g2_5 wire_logic_cluster/lc_6/in_1 (28 12) routing lc_trk_g2_7 wire_logic_cluster/lc_6/in_1 (28 12) routing lc_trk_g3_0 wire_logic_cluster/lc_6/in_1 (28 12) routing lc_trk_g3_2 wire_logic_cluster/lc_6/in_1 (28 12) routing lc_trk_g3_4 wire_logic_cluster/lc_6/in_1 (28 12) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 (28 13) routing lc_trk_g2_0 wire_logic_cluster/lc_6/in_0 (28 13) routing lc_trk_g2_2 wire_logic_cluster/lc_6/in_0 (28 13) routing lc_trk_g2_4 wire_logic_cluster/lc_6/in_0 (28 13) routing lc_trk_g2_6 wire_logic_cluster/lc_6/in_0 (28 13) routing lc_trk_g3_1 wire_logic_cluster/lc_6/in_0 (28 13) routing lc_trk_g3_3 wire_logic_cluster/lc_6/in_0 (28 13) routing lc_trk_g3_5 wire_logic_cluster/lc_6/in_0 (28 13) routing lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 (28 14) routing lc_trk_g2_0 wire_logic_cluster/lc_7/in_1 (28 14) routing lc_trk_g2_2 wire_logic_cluster/lc_7/in_1 (28 14) routing lc_trk_g2_4 wire_logic_cluster/lc_7/in_1 (28 14) routing lc_trk_g2_6 wire_logic_cluster/lc_7/in_1 (28 14) routing lc_trk_g3_1 wire_logic_cluster/lc_7/in_1 (28 14) routing lc_trk_g3_3 wire_logic_cluster/lc_7/in_1 (28 14) routing lc_trk_g3_5 wire_logic_cluster/lc_7/in_1 (28 14) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 (28 15) routing lc_trk_g2_1 wire_logic_cluster/lc_7/in_0 (28 15) routing lc_trk_g2_3 wire_logic_cluster/lc_7/in_0 (28 15) routing lc_trk_g2_5 wire_logic_cluster/lc_7/in_0 (28 15) routing lc_trk_g2_7 wire_logic_cluster/lc_7/in_0 (28 15) routing lc_trk_g3_0 wire_logic_cluster/lc_7/in_0 (28 15) routing lc_trk_g3_2 wire_logic_cluster/lc_7/in_0 (28 15) routing lc_trk_g3_4 wire_logic_cluster/lc_7/in_0 (28 15) routing lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 (28 2) routing lc_trk_g2_0 wire_logic_cluster/lc_1/in_1 (28 2) routing lc_trk_g2_2 wire_logic_cluster/lc_1/in_1 (28 2) routing lc_trk_g2_4 wire_logic_cluster/lc_1/in_1 (28 2) routing lc_trk_g2_6 wire_logic_cluster/lc_1/in_1 (28 2) routing lc_trk_g3_1 wire_logic_cluster/lc_1/in_1 (28 2) routing lc_trk_g3_3 wire_logic_cluster/lc_1/in_1 (28 2) routing lc_trk_g3_5 wire_logic_cluster/lc_1/in_1 (28 2) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 (28 3) routing lc_trk_g2_1 wire_logic_cluster/lc_1/in_0 (28 3) routing lc_trk_g2_3 wire_logic_cluster/lc_1/in_0 (28 3) routing lc_trk_g2_5 wire_logic_cluster/lc_1/in_0 (28 3) routing lc_trk_g2_7 wire_logic_cluster/lc_1/in_0 (28 3) routing lc_trk_g3_0 wire_logic_cluster/lc_1/in_0 (28 3) routing lc_trk_g3_2 wire_logic_cluster/lc_1/in_0 (28 3) routing lc_trk_g3_4 wire_logic_cluster/lc_1/in_0 (28 3) routing lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 (28 4) routing lc_trk_g2_1 wire_logic_cluster/lc_2/in_1 (28 4) routing lc_trk_g2_3 wire_logic_cluster/lc_2/in_1 (28 4) routing lc_trk_g2_5 wire_logic_cluster/lc_2/in_1 (28 4) routing lc_trk_g2_7 wire_logic_cluster/lc_2/in_1 (28 4) routing lc_trk_g3_0 wire_logic_cluster/lc_2/in_1 (28 4) routing lc_trk_g3_2 wire_logic_cluster/lc_2/in_1 (28 4) routing lc_trk_g3_4 wire_logic_cluster/lc_2/in_1 (28 4) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 (28 5) routing lc_trk_g2_0 wire_logic_cluster/lc_2/in_0 (28 5) routing lc_trk_g2_2 wire_logic_cluster/lc_2/in_0 (28 5) routing lc_trk_g2_4 wire_logic_cluster/lc_2/in_0 (28 5) routing lc_trk_g2_6 wire_logic_cluster/lc_2/in_0 (28 5) routing lc_trk_g3_1 wire_logic_cluster/lc_2/in_0 (28 5) routing lc_trk_g3_3 wire_logic_cluster/lc_2/in_0 (28 5) routing lc_trk_g3_5 wire_logic_cluster/lc_2/in_0 (28 5) routing lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 (28 6) routing lc_trk_g2_0 wire_logic_cluster/lc_3/in_1 (28 6) routing lc_trk_g2_2 wire_logic_cluster/lc_3/in_1 (28 6) routing lc_trk_g2_4 wire_logic_cluster/lc_3/in_1 (28 6) routing lc_trk_g2_6 wire_logic_cluster/lc_3/in_1 (28 6) routing lc_trk_g3_1 wire_logic_cluster/lc_3/in_1 (28 6) routing lc_trk_g3_3 wire_logic_cluster/lc_3/in_1 (28 6) routing lc_trk_g3_5 wire_logic_cluster/lc_3/in_1 (28 6) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 (28 7) routing lc_trk_g2_1 wire_logic_cluster/lc_3/in_0 (28 7) routing lc_trk_g2_3 wire_logic_cluster/lc_3/in_0 (28 7) routing lc_trk_g2_5 wire_logic_cluster/lc_3/in_0 (28 7) routing lc_trk_g2_7 wire_logic_cluster/lc_3/in_0 (28 7) routing lc_trk_g3_0 wire_logic_cluster/lc_3/in_0 (28 7) routing lc_trk_g3_2 wire_logic_cluster/lc_3/in_0 (28 7) routing lc_trk_g3_4 wire_logic_cluster/lc_3/in_0 (28 7) routing lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 (28 8) routing lc_trk_g2_1 wire_logic_cluster/lc_4/in_1 (28 8) routing lc_trk_g2_3 wire_logic_cluster/lc_4/in_1 (28 8) routing lc_trk_g2_5 wire_logic_cluster/lc_4/in_1 (28 8) routing lc_trk_g2_7 wire_logic_cluster/lc_4/in_1 (28 8) routing lc_trk_g3_0 wire_logic_cluster/lc_4/in_1 (28 8) routing lc_trk_g3_2 wire_logic_cluster/lc_4/in_1 (28 8) routing lc_trk_g3_4 wire_logic_cluster/lc_4/in_1 (28 8) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 (28 9) routing lc_trk_g2_0 wire_logic_cluster/lc_4/in_0 (28 9) routing lc_trk_g2_2 wire_logic_cluster/lc_4/in_0 (28 9) routing lc_trk_g2_4 wire_logic_cluster/lc_4/in_0 (28 9) routing lc_trk_g2_6 wire_logic_cluster/lc_4/in_0 (28 9) routing lc_trk_g3_1 wire_logic_cluster/lc_4/in_0 (28 9) routing lc_trk_g3_3 wire_logic_cluster/lc_4/in_0 (28 9) routing lc_trk_g3_5 wire_logic_cluster/lc_4/in_0 (28 9) routing lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_1 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_3 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_5 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g0_7 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_0 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_2 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_4 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g1_6 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_1 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_3 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_5 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g2_7 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_0 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_2 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_4 wire_logic_cluster/lc_0/in_1 (29 0) Enable bit of Mux _logic_cluster/lcb1_0 => lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_0 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_2 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_4 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g0_6 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_1 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_3 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_5 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g1_7 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_0 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_2 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_4 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g2_6 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_1 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_3 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_5 wire_logic_cluster/lc_0/in_0 (29 1) Enable bit of Mux _logic_cluster/lcb0_0 => lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_0 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_2 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_4 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g0_6 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_1 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_3 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_5 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g1_7 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_0 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_2 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_4 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g2_6 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_1 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_3 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_5 wire_logic_cluster/lc_5/in_1 (29 10) Enable bit of Mux _logic_cluster/lcb1_5 => lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_1 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_3 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_5 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g0_7 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_0 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_2 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_4 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g1_6 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_1 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_3 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_5 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g2_7 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_0 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_2 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_4 wire_logic_cluster/lc_5/in_0 (29 11) Enable bit of Mux _logic_cluster/lcb0_5 => lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_1 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_3 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_5 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g0_7 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_0 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_2 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_4 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g1_6 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_1 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_3 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_5 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g2_7 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_0 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_2 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_4 wire_logic_cluster/lc_6/in_1 (29 12) Enable bit of Mux _logic_cluster/lcb1_6 => lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_0 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_2 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_4 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g0_6 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_1 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_3 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_5 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g1_7 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_0 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_2 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_4 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g2_6 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_1 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_3 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_5 wire_logic_cluster/lc_6/in_0 (29 13) Enable bit of Mux _logic_cluster/lcb0_6 => lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_0 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_2 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_4 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g0_6 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_1 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_3 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_5 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g1_7 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_0 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_2 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_4 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g2_6 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_1 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_3 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_5 wire_logic_cluster/lc_7/in_1 (29 14) Enable bit of Mux _logic_cluster/lcb1_7 => lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_1 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_3 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_5 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g0_7 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_0 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_2 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_4 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g1_6 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_1 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_3 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_5 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g2_7 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_0 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_2 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_4 wire_logic_cluster/lc_7/in_0 (29 15) Enable bit of Mux _logic_cluster/lcb0_7 => lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_0 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_2 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_4 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g0_6 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_1 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_3 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_5 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g1_7 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_0 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_2 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_4 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g2_6 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_1 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_3 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_5 wire_logic_cluster/lc_1/in_1 (29 2) Enable bit of Mux _logic_cluster/lcb1_1 => lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_1 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_3 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_5 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g0_7 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_0 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_2 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_4 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g1_6 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_1 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_3 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_5 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g2_7 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_0 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_2 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_4 wire_logic_cluster/lc_1/in_0 (29 3) Enable bit of Mux _logic_cluster/lcb0_1 => lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_1 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_3 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_5 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g0_7 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_0 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_2 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_4 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g1_6 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_1 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_3 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_5 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g2_7 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_0 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_2 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_4 wire_logic_cluster/lc_2/in_1 (29 4) Enable bit of Mux _logic_cluster/lcb1_2 => lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_0 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_2 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_4 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g0_6 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_1 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_3 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_5 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g1_7 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_0 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_2 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_4 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g2_6 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_1 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_3 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_5 wire_logic_cluster/lc_2/in_0 (29 5) Enable bit of Mux _logic_cluster/lcb0_2 => lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_0 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_2 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_4 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g0_6 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_1 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_3 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_5 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g1_7 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_0 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_2 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_4 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g2_6 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_1 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_3 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_5 wire_logic_cluster/lc_3/in_1 (29 6) Enable bit of Mux _logic_cluster/lcb1_3 => lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_1 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_3 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_5 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g0_7 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_0 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_2 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_4 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g1_6 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_1 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_3 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_5 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g2_7 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_0 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_2 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_4 wire_logic_cluster/lc_3/in_0 (29 7) Enable bit of Mux _logic_cluster/lcb0_3 => lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_1 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_3 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_5 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g0_7 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_0 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_2 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_4 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g1_6 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_1 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_3 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_5 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g2_7 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_0 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_2 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_4 wire_logic_cluster/lc_4/in_1 (29 8) Enable bit of Mux _logic_cluster/lcb1_4 => lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_0 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_2 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_4 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g0_6 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_1 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_3 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_5 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g1_7 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_0 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_2 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_4 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g2_6 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_1 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_3 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_5 wire_logic_cluster/lc_4/in_0 (29 9) Enable bit of Mux _logic_cluster/lcb0_4 => lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 (3 0) routing sp12_h_r_0 sp12_v_b_0 (3 0) routing sp12_v_t_23 sp12_v_b_0 (3 1) routing sp12_h_l_23 sp12_v_b_0 (3 1) routing sp12_h_r_0 sp12_v_b_0 (3 10) routing sp12_h_r_1 sp12_h_l_22 (3 10) routing sp12_v_t_22 sp12_h_l_22 (3 11) routing sp12_h_r_1 sp12_h_l_22 (3 11) routing sp12_v_b_1 sp12_h_l_22 (3 12) routing sp12_v_b_1 sp12_h_r_1 (3 12) routing sp12_v_t_22 sp12_h_r_1 (3 13) routing sp12_h_l_22 sp12_h_r_1 (3 13) routing sp12_v_b_1 sp12_h_r_1 (3 14) routing sp12_h_r_1 sp12_v_t_22 (3 14) routing sp12_v_b_1 sp12_v_t_22 (3 15) routing sp12_h_l_22 sp12_v_t_22 (3 15) routing sp12_h_r_1 sp12_v_t_22 (3 2) routing sp12_h_r_0 sp12_h_l_23 (3 2) routing sp12_v_t_23 sp12_h_l_23 (3 3) routing sp12_h_r_0 sp12_h_l_23 (3 3) routing sp12_v_b_0 sp12_h_l_23 (3 4) routing sp12_v_b_0 sp12_h_r_0 (3 4) routing sp12_v_t_23 sp12_h_r_0 (3 5) routing sp12_h_l_23 sp12_h_r_0 (3 5) routing sp12_v_b_0 sp12_h_r_0 (3 6) routing sp12_h_r_0 sp12_v_t_23 (3 6) routing sp12_v_b_0 sp12_v_t_23 (3 7) routing sp12_h_l_23 sp12_v_t_23 (3 7) routing sp12_h_r_0 sp12_v_t_23 (3 8) routing sp12_h_r_1 sp12_v_b_1 (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 (30 0) routing lc_trk_g0_5 wire_logic_cluster/lc_0/in_1 (30 0) routing lc_trk_g0_7 wire_logic_cluster/lc_0/in_1 (30 0) routing lc_trk_g1_4 wire_logic_cluster/lc_0/in_1 (30 0) routing lc_trk_g1_6 wire_logic_cluster/lc_0/in_1 (30 0) routing lc_trk_g2_5 wire_logic_cluster/lc_0/in_1 (30 0) routing lc_trk_g2_7 wire_logic_cluster/lc_0/in_1 (30 0) routing lc_trk_g3_4 wire_logic_cluster/lc_0/in_1 (30 0) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g0_3 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g0_7 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g1_2 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g1_6 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g2_3 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g2_7 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g3_2 wire_logic_cluster/lc_0/in_1 (30 1) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 (30 10) routing lc_trk_g0_4 wire_logic_cluster/lc_5/in_1 (30 10) routing lc_trk_g0_6 wire_logic_cluster/lc_5/in_1 (30 10) routing lc_trk_g1_5 wire_logic_cluster/lc_5/in_1 (30 10) routing lc_trk_g1_7 wire_logic_cluster/lc_5/in_1 (30 10) routing lc_trk_g2_4 wire_logic_cluster/lc_5/in_1 (30 10) routing lc_trk_g2_6 wire_logic_cluster/lc_5/in_1 (30 10) routing lc_trk_g3_5 wire_logic_cluster/lc_5/in_1 (30 10) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g0_2 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g0_6 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g1_3 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g1_7 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g2_2 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g2_6 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g3_3 wire_logic_cluster/lc_5/in_1 (30 11) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 (30 12) routing lc_trk_g0_5 wire_logic_cluster/lc_6/in_1 (30 12) routing lc_trk_g0_7 wire_logic_cluster/lc_6/in_1 (30 12) routing lc_trk_g1_4 wire_logic_cluster/lc_6/in_1 (30 12) routing lc_trk_g1_6 wire_logic_cluster/lc_6/in_1 (30 12) routing lc_trk_g2_5 wire_logic_cluster/lc_6/in_1 (30 12) routing lc_trk_g2_7 wire_logic_cluster/lc_6/in_1 (30 12) routing lc_trk_g3_4 wire_logic_cluster/lc_6/in_1 (30 12) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g0_3 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g0_7 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g1_2 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g1_6 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g2_3 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g2_7 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g3_2 wire_logic_cluster/lc_6/in_1 (30 13) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 (30 14) routing lc_trk_g0_4 wire_logic_cluster/lc_7/in_1 (30 14) routing lc_trk_g0_6 wire_logic_cluster/lc_7/in_1 (30 14) routing lc_trk_g1_5 wire_logic_cluster/lc_7/in_1 (30 14) routing lc_trk_g1_7 wire_logic_cluster/lc_7/in_1 (30 14) routing lc_trk_g2_4 wire_logic_cluster/lc_7/in_1 (30 14) routing lc_trk_g2_6 wire_logic_cluster/lc_7/in_1 (30 14) routing lc_trk_g3_5 wire_logic_cluster/lc_7/in_1 (30 14) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g0_2 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g0_6 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g1_3 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g1_7 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g2_2 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g2_6 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g3_3 wire_logic_cluster/lc_7/in_1 (30 15) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 (30 2) routing lc_trk_g0_4 wire_logic_cluster/lc_1/in_1 (30 2) routing lc_trk_g0_6 wire_logic_cluster/lc_1/in_1 (30 2) routing lc_trk_g1_5 wire_logic_cluster/lc_1/in_1 (30 2) routing lc_trk_g1_7 wire_logic_cluster/lc_1/in_1 (30 2) routing lc_trk_g2_4 wire_logic_cluster/lc_1/in_1 (30 2) routing lc_trk_g2_6 wire_logic_cluster/lc_1/in_1 (30 2) routing lc_trk_g3_5 wire_logic_cluster/lc_1/in_1 (30 2) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g0_2 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g0_6 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g1_3 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g1_7 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g2_2 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g2_6 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g3_3 wire_logic_cluster/lc_1/in_1 (30 3) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 (30 4) routing lc_trk_g0_5 wire_logic_cluster/lc_2/in_1 (30 4) routing lc_trk_g0_7 wire_logic_cluster/lc_2/in_1 (30 4) routing lc_trk_g1_4 wire_logic_cluster/lc_2/in_1 (30 4) routing lc_trk_g1_6 wire_logic_cluster/lc_2/in_1 (30 4) routing lc_trk_g2_5 wire_logic_cluster/lc_2/in_1 (30 4) routing lc_trk_g2_7 wire_logic_cluster/lc_2/in_1 (30 4) routing lc_trk_g3_4 wire_logic_cluster/lc_2/in_1 (30 4) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g0_3 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g0_7 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g1_2 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g1_6 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g2_3 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g2_7 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g3_2 wire_logic_cluster/lc_2/in_1 (30 5) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 (30 6) routing lc_trk_g0_4 wire_logic_cluster/lc_3/in_1 (30 6) routing lc_trk_g0_6 wire_logic_cluster/lc_3/in_1 (30 6) routing lc_trk_g1_5 wire_logic_cluster/lc_3/in_1 (30 6) routing lc_trk_g1_7 wire_logic_cluster/lc_3/in_1 (30 6) routing lc_trk_g2_4 wire_logic_cluster/lc_3/in_1 (30 6) routing lc_trk_g2_6 wire_logic_cluster/lc_3/in_1 (30 6) routing lc_trk_g3_5 wire_logic_cluster/lc_3/in_1 (30 6) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g0_2 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g0_6 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g1_3 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g1_7 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g2_2 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g2_6 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g3_3 wire_logic_cluster/lc_3/in_1 (30 7) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 (30 8) routing lc_trk_g0_5 wire_logic_cluster/lc_4/in_1 (30 8) routing lc_trk_g0_7 wire_logic_cluster/lc_4/in_1 (30 8) routing lc_trk_g1_4 wire_logic_cluster/lc_4/in_1 (30 8) routing lc_trk_g1_6 wire_logic_cluster/lc_4/in_1 (30 8) routing lc_trk_g2_5 wire_logic_cluster/lc_4/in_1 (30 8) routing lc_trk_g2_7 wire_logic_cluster/lc_4/in_1 (30 8) routing lc_trk_g3_4 wire_logic_cluster/lc_4/in_1 (30 8) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g0_3 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g0_7 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g1_2 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g1_6 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g2_3 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g2_7 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g3_2 wire_logic_cluster/lc_4/in_1 (30 9) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 (31 0) routing lc_trk_g0_5 wire_logic_cluster/lc_0/in_3 (31 0) routing lc_trk_g0_7 wire_logic_cluster/lc_0/in_3 (31 0) routing lc_trk_g1_4 wire_logic_cluster/lc_0/in_3 (31 0) routing lc_trk_g1_6 wire_logic_cluster/lc_0/in_3 (31 0) routing lc_trk_g2_5 wire_logic_cluster/lc_0/in_3 (31 0) routing lc_trk_g2_7 wire_logic_cluster/lc_0/in_3 (31 0) routing lc_trk_g3_4 wire_logic_cluster/lc_0/in_3 (31 0) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g0_3 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g0_7 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g1_2 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g1_6 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g2_3 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g2_7 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g3_2 wire_logic_cluster/lc_0/in_3 (31 1) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 (31 10) routing lc_trk_g0_4 wire_logic_cluster/lc_5/in_3 (31 10) routing lc_trk_g0_6 wire_logic_cluster/lc_5/in_3 (31 10) routing lc_trk_g1_5 wire_logic_cluster/lc_5/in_3 (31 10) routing lc_trk_g1_7 wire_logic_cluster/lc_5/in_3 (31 10) routing lc_trk_g2_4 wire_logic_cluster/lc_5/in_3 (31 10) routing lc_trk_g2_6 wire_logic_cluster/lc_5/in_3 (31 10) routing lc_trk_g3_5 wire_logic_cluster/lc_5/in_3 (31 10) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g0_2 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g0_6 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g1_3 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g1_7 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g2_2 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g2_6 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g3_3 wire_logic_cluster/lc_5/in_3 (31 11) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 (31 12) routing lc_trk_g0_5 wire_logic_cluster/lc_6/in_3 (31 12) routing lc_trk_g0_7 wire_logic_cluster/lc_6/in_3 (31 12) routing lc_trk_g1_4 wire_logic_cluster/lc_6/in_3 (31 12) routing lc_trk_g1_6 wire_logic_cluster/lc_6/in_3 (31 12) routing lc_trk_g2_5 wire_logic_cluster/lc_6/in_3 (31 12) routing lc_trk_g2_7 wire_logic_cluster/lc_6/in_3 (31 12) routing lc_trk_g3_4 wire_logic_cluster/lc_6/in_3 (31 12) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g0_3 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g0_7 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g1_2 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g1_6 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g2_3 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g2_7 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g3_2 wire_logic_cluster/lc_6/in_3 (31 13) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 (31 14) routing lc_trk_g0_4 wire_logic_cluster/lc_7/in_3 (31 14) routing lc_trk_g0_6 wire_logic_cluster/lc_7/in_3 (31 14) routing lc_trk_g1_5 wire_logic_cluster/lc_7/in_3 (31 14) routing lc_trk_g1_7 wire_logic_cluster/lc_7/in_3 (31 14) routing lc_trk_g2_4 wire_logic_cluster/lc_7/in_3 (31 14) routing lc_trk_g2_6 wire_logic_cluster/lc_7/in_3 (31 14) routing lc_trk_g3_5 wire_logic_cluster/lc_7/in_3 (31 14) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g0_2 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g0_6 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g1_3 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g1_7 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g2_2 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g2_6 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g3_3 wire_logic_cluster/lc_7/in_3 (31 15) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 (31 2) routing lc_trk_g0_4 wire_logic_cluster/lc_1/in_3 (31 2) routing lc_trk_g0_6 wire_logic_cluster/lc_1/in_3 (31 2) routing lc_trk_g1_5 wire_logic_cluster/lc_1/in_3 (31 2) routing lc_trk_g1_7 wire_logic_cluster/lc_1/in_3 (31 2) routing lc_trk_g2_4 wire_logic_cluster/lc_1/in_3 (31 2) routing lc_trk_g2_6 wire_logic_cluster/lc_1/in_3 (31 2) routing lc_trk_g3_5 wire_logic_cluster/lc_1/in_3 (31 2) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g0_2 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g0_6 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g1_3 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g1_7 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g2_2 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g2_6 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g3_3 wire_logic_cluster/lc_1/in_3 (31 3) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 (31 4) routing lc_trk_g0_5 wire_logic_cluster/lc_2/in_3 (31 4) routing lc_trk_g0_7 wire_logic_cluster/lc_2/in_3 (31 4) routing lc_trk_g1_4 wire_logic_cluster/lc_2/in_3 (31 4) routing lc_trk_g1_6 wire_logic_cluster/lc_2/in_3 (31 4) routing lc_trk_g2_5 wire_logic_cluster/lc_2/in_3 (31 4) routing lc_trk_g2_7 wire_logic_cluster/lc_2/in_3 (31 4) routing lc_trk_g3_4 wire_logic_cluster/lc_2/in_3 (31 4) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g0_3 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g0_7 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g1_2 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g1_6 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g2_3 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g2_7 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g3_2 wire_logic_cluster/lc_2/in_3 (31 5) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 (31 6) routing lc_trk_g0_4 wire_logic_cluster/lc_3/in_3 (31 6) routing lc_trk_g0_6 wire_logic_cluster/lc_3/in_3 (31 6) routing lc_trk_g1_5 wire_logic_cluster/lc_3/in_3 (31 6) routing lc_trk_g1_7 wire_logic_cluster/lc_3/in_3 (31 6) routing lc_trk_g2_4 wire_logic_cluster/lc_3/in_3 (31 6) routing lc_trk_g2_6 wire_logic_cluster/lc_3/in_3 (31 6) routing lc_trk_g3_5 wire_logic_cluster/lc_3/in_3 (31 6) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g0_2 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g0_6 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g1_3 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g1_7 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g2_2 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g2_6 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g3_3 wire_logic_cluster/lc_3/in_3 (31 7) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 (31 8) routing lc_trk_g0_5 wire_logic_cluster/lc_4/in_3 (31 8) routing lc_trk_g0_7 wire_logic_cluster/lc_4/in_3 (31 8) routing lc_trk_g1_4 wire_logic_cluster/lc_4/in_3 (31 8) routing lc_trk_g1_6 wire_logic_cluster/lc_4/in_3 (31 8) routing lc_trk_g2_5 wire_logic_cluster/lc_4/in_3 (31 8) routing lc_trk_g2_7 wire_logic_cluster/lc_4/in_3 (31 8) routing lc_trk_g3_4 wire_logic_cluster/lc_4/in_3 (31 8) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g0_3 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g0_7 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g1_2 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g1_6 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g2_3 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g2_7 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g3_2 wire_logic_cluster/lc_4/in_3 (31 9) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g0_3 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g0_5 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g0_7 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_0 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_2 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_4 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g1_6 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_1 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_3 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_5 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g2_7 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_0 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_2 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_4 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 (32 0) Enable bit of Mux _logic_cluster/lcb3_0 => wire_logic_cluster/carry_in_mux/cout wire_logic_cluster/lc_0/in_3 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_0 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_2 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_4 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g0_6 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_1 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_3 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_5 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g1_7 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_0 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_2 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_4 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g2_6 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_1 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_3 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_5 input_2_0 (32 1) Enable bit of Mux _logic_cluster/lcb2_0 => lc_trk_g3_7 input_2_0 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g0_2 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g0_4 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g0_6 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_1 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_3 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_5 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g1_7 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_0 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_2 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_4 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g2_6 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_1 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_3 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_5 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 (32 10) Enable bit of Mux _logic_cluster/lcb3_5 => wire_logic_cluster/lc_4/cout wire_logic_cluster/lc_5/in_3 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_1 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_3 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_5 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g0_7 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_0 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_2 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_4 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g1_6 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_1 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_3 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_5 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g2_7 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_0 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_2 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_4 input_2_5 (32 11) Enable bit of Mux _logic_cluster/lcb2_5 => lc_trk_g3_6 input_2_5 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g0_3 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g0_5 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g0_7 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_0 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_2 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_4 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g1_6 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_1 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_3 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_5 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g2_7 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_0 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_2 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_4 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 (32 12) Enable bit of Mux _logic_cluster/lcb3_6 => wire_logic_cluster/lc_5/cout wire_logic_cluster/lc_6/in_3 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_0 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_2 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_4 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g0_6 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_1 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_3 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_5 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g1_7 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_0 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_2 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_4 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g2_6 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_1 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_3 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_5 input_2_6 (32 13) Enable bit of Mux _logic_cluster/lcb2_6 => lc_trk_g3_7 input_2_6 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g0_2 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g0_4 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g0_6 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_1 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_3 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_5 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g1_7 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_0 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_2 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_4 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g2_6 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_1 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_3 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_5 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 (32 14) Enable bit of Mux _logic_cluster/lcb3_7 => wire_logic_cluster/lc_6/cout wire_logic_cluster/lc_7/in_3 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_1 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_3 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_5 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g0_7 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_0 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_2 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_4 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g1_6 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_1 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_3 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_5 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g2_7 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_0 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_2 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_4 input_2_7 (32 15) Enable bit of Mux _logic_cluster/lcb2_7 => lc_trk_g3_6 input_2_7 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g0_2 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g0_4 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g0_6 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_1 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_3 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_5 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g1_7 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_0 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_2 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_4 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g2_6 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_1 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_3 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_5 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 (32 2) Enable bit of Mux _logic_cluster/lcb3_1 => wire_logic_cluster/lc_0/cout wire_logic_cluster/lc_1/in_3 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_1 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_3 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_5 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g0_7 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_0 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_2 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_4 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g1_6 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_1 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_3 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_5 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g2_7 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_0 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_2 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_4 input_2_1 (32 3) Enable bit of Mux _logic_cluster/lcb2_1 => lc_trk_g3_6 input_2_1 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g0_3 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g0_5 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g0_7 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_0 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_2 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_4 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g1_6 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_1 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_3 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_5 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g2_7 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_0 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_2 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_4 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 (32 4) Enable bit of Mux _logic_cluster/lcb3_2 => wire_logic_cluster/lc_1/cout wire_logic_cluster/lc_2/in_3 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_0 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_2 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_4 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g0_6 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_1 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_3 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_5 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g1_7 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_0 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_2 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_4 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g2_6 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_1 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_3 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_5 input_2_2 (32 5) Enable bit of Mux _logic_cluster/lcb2_2 => lc_trk_g3_7 input_2_2 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g0_2 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g0_4 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g0_6 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_1 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_3 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_5 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g1_7 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_0 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_2 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_4 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g2_6 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_1 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_3 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_5 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 (32 6) Enable bit of Mux _logic_cluster/lcb3_3 => wire_logic_cluster/lc_2/cout wire_logic_cluster/lc_3/in_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_1 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_3 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_5 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g0_7 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_0 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_2 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_4 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g1_6 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_1 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_3 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_5 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g2_7 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_0 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_2 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_4 input_2_3 (32 7) Enable bit of Mux _logic_cluster/lcb2_3 => lc_trk_g3_6 input_2_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g0_3 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g0_5 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g0_7 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_0 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_2 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_4 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g1_6 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_1 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_3 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_5 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g2_7 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_0 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_2 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_4 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 (32 8) Enable bit of Mux _logic_cluster/lcb3_4 => wire_logic_cluster/lc_3/cout wire_logic_cluster/lc_4/in_3 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_0 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_2 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_4 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g0_6 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_1 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_3 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_5 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g1_7 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_0 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_2 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_4 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g2_6 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_1 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_3 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_5 input_2_4 (32 9) Enable bit of Mux _logic_cluster/lcb2_4 => lc_trk_g3_7 input_2_4 (33 0) routing lc_trk_g2_1 wire_logic_cluster/lc_0/in_3 (33 0) routing lc_trk_g2_3 wire_logic_cluster/lc_0/in_3 (33 0) routing lc_trk_g2_5 wire_logic_cluster/lc_0/in_3 (33 0) routing lc_trk_g2_7 wire_logic_cluster/lc_0/in_3 (33 0) routing lc_trk_g3_0 wire_logic_cluster/lc_0/in_3 (33 0) routing lc_trk_g3_2 wire_logic_cluster/lc_0/in_3 (33 0) routing lc_trk_g3_4 wire_logic_cluster/lc_0/in_3 (33 0) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 (33 1) routing lc_trk_g2_0 input_2_0 (33 1) routing lc_trk_g2_2 input_2_0 (33 1) routing lc_trk_g2_4 input_2_0 (33 1) routing lc_trk_g2_6 input_2_0 (33 1) routing lc_trk_g3_1 input_2_0 (33 1) routing lc_trk_g3_3 input_2_0 (33 1) routing lc_trk_g3_5 input_2_0 (33 1) routing lc_trk_g3_7 input_2_0 (33 10) routing lc_trk_g2_0 wire_logic_cluster/lc_5/in_3 (33 10) routing lc_trk_g2_2 wire_logic_cluster/lc_5/in_3 (33 10) routing lc_trk_g2_4 wire_logic_cluster/lc_5/in_3 (33 10) routing lc_trk_g2_6 wire_logic_cluster/lc_5/in_3 (33 10) routing lc_trk_g3_1 wire_logic_cluster/lc_5/in_3 (33 10) routing lc_trk_g3_3 wire_logic_cluster/lc_5/in_3 (33 10) routing lc_trk_g3_5 wire_logic_cluster/lc_5/in_3 (33 10) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 (33 11) routing lc_trk_g2_1 input_2_5 (33 11) routing lc_trk_g2_3 input_2_5 (33 11) routing lc_trk_g2_5 input_2_5 (33 11) routing lc_trk_g2_7 input_2_5 (33 11) routing lc_trk_g3_0 input_2_5 (33 11) routing lc_trk_g3_2 input_2_5 (33 11) routing lc_trk_g3_4 input_2_5 (33 11) routing lc_trk_g3_6 input_2_5 (33 12) routing lc_trk_g2_1 wire_logic_cluster/lc_6/in_3 (33 12) routing lc_trk_g2_3 wire_logic_cluster/lc_6/in_3 (33 12) routing lc_trk_g2_5 wire_logic_cluster/lc_6/in_3 (33 12) routing lc_trk_g2_7 wire_logic_cluster/lc_6/in_3 (33 12) routing lc_trk_g3_0 wire_logic_cluster/lc_6/in_3 (33 12) routing lc_trk_g3_2 wire_logic_cluster/lc_6/in_3 (33 12) routing lc_trk_g3_4 wire_logic_cluster/lc_6/in_3 (33 12) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 (33 13) routing lc_trk_g2_0 input_2_6 (33 13) routing lc_trk_g2_2 input_2_6 (33 13) routing lc_trk_g2_4 input_2_6 (33 13) routing lc_trk_g2_6 input_2_6 (33 13) routing lc_trk_g3_1 input_2_6 (33 13) routing lc_trk_g3_3 input_2_6 (33 13) routing lc_trk_g3_5 input_2_6 (33 13) routing lc_trk_g3_7 input_2_6 (33 14) routing lc_trk_g2_0 wire_logic_cluster/lc_7/in_3 (33 14) routing lc_trk_g2_2 wire_logic_cluster/lc_7/in_3 (33 14) routing lc_trk_g2_4 wire_logic_cluster/lc_7/in_3 (33 14) routing lc_trk_g2_6 wire_logic_cluster/lc_7/in_3 (33 14) routing lc_trk_g3_1 wire_logic_cluster/lc_7/in_3 (33 14) routing lc_trk_g3_3 wire_logic_cluster/lc_7/in_3 (33 14) routing lc_trk_g3_5 wire_logic_cluster/lc_7/in_3 (33 14) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 (33 15) routing lc_trk_g2_1 input_2_7 (33 15) routing lc_trk_g2_3 input_2_7 (33 15) routing lc_trk_g2_5 input_2_7 (33 15) routing lc_trk_g2_7 input_2_7 (33 15) routing lc_trk_g3_0 input_2_7 (33 15) routing lc_trk_g3_2 input_2_7 (33 15) routing lc_trk_g3_4 input_2_7 (33 15) routing lc_trk_g3_6 input_2_7 (33 2) routing lc_trk_g2_0 wire_logic_cluster/lc_1/in_3 (33 2) routing lc_trk_g2_2 wire_logic_cluster/lc_1/in_3 (33 2) routing lc_trk_g2_4 wire_logic_cluster/lc_1/in_3 (33 2) routing lc_trk_g2_6 wire_logic_cluster/lc_1/in_3 (33 2) routing lc_trk_g3_1 wire_logic_cluster/lc_1/in_3 (33 2) routing lc_trk_g3_3 wire_logic_cluster/lc_1/in_3 (33 2) routing lc_trk_g3_5 wire_logic_cluster/lc_1/in_3 (33 2) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 (33 3) routing lc_trk_g2_1 input_2_1 (33 3) routing lc_trk_g2_3 input_2_1 (33 3) routing lc_trk_g2_5 input_2_1 (33 3) routing lc_trk_g2_7 input_2_1 (33 3) routing lc_trk_g3_0 input_2_1 (33 3) routing lc_trk_g3_2 input_2_1 (33 3) routing lc_trk_g3_4 input_2_1 (33 3) routing lc_trk_g3_6 input_2_1 (33 4) routing lc_trk_g2_1 wire_logic_cluster/lc_2/in_3 (33 4) routing lc_trk_g2_3 wire_logic_cluster/lc_2/in_3 (33 4) routing lc_trk_g2_5 wire_logic_cluster/lc_2/in_3 (33 4) routing lc_trk_g2_7 wire_logic_cluster/lc_2/in_3 (33 4) routing lc_trk_g3_0 wire_logic_cluster/lc_2/in_3 (33 4) routing lc_trk_g3_2 wire_logic_cluster/lc_2/in_3 (33 4) routing lc_trk_g3_4 wire_logic_cluster/lc_2/in_3 (33 4) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 (33 5) routing lc_trk_g2_0 input_2_2 (33 5) routing lc_trk_g2_2 input_2_2 (33 5) routing lc_trk_g2_4 input_2_2 (33 5) routing lc_trk_g2_6 input_2_2 (33 5) routing lc_trk_g3_1 input_2_2 (33 5) routing lc_trk_g3_3 input_2_2 (33 5) routing lc_trk_g3_5 input_2_2 (33 5) routing lc_trk_g3_7 input_2_2 (33 6) routing lc_trk_g2_0 wire_logic_cluster/lc_3/in_3 (33 6) routing lc_trk_g2_2 wire_logic_cluster/lc_3/in_3 (33 6) routing lc_trk_g2_4 wire_logic_cluster/lc_3/in_3 (33 6) routing lc_trk_g2_6 wire_logic_cluster/lc_3/in_3 (33 6) routing lc_trk_g3_1 wire_logic_cluster/lc_3/in_3 (33 6) routing lc_trk_g3_3 wire_logic_cluster/lc_3/in_3 (33 6) routing lc_trk_g3_5 wire_logic_cluster/lc_3/in_3 (33 6) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 (33 7) routing lc_trk_g2_1 input_2_3 (33 7) routing lc_trk_g2_3 input_2_3 (33 7) routing lc_trk_g2_5 input_2_3 (33 7) routing lc_trk_g2_7 input_2_3 (33 7) routing lc_trk_g3_0 input_2_3 (33 7) routing lc_trk_g3_2 input_2_3 (33 7) routing lc_trk_g3_4 input_2_3 (33 7) routing lc_trk_g3_6 input_2_3 (33 8) routing lc_trk_g2_1 wire_logic_cluster/lc_4/in_3 (33 8) routing lc_trk_g2_3 wire_logic_cluster/lc_4/in_3 (33 8) routing lc_trk_g2_5 wire_logic_cluster/lc_4/in_3 (33 8) routing lc_trk_g2_7 wire_logic_cluster/lc_4/in_3 (33 8) routing lc_trk_g3_0 wire_logic_cluster/lc_4/in_3 (33 8) routing lc_trk_g3_2 wire_logic_cluster/lc_4/in_3 (33 8) routing lc_trk_g3_4 wire_logic_cluster/lc_4/in_3 (33 8) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 (33 9) routing lc_trk_g2_0 input_2_4 (33 9) routing lc_trk_g2_2 input_2_4 (33 9) routing lc_trk_g2_4 input_2_4 (33 9) routing lc_trk_g2_6 input_2_4 (33 9) routing lc_trk_g3_1 input_2_4 (33 9) routing lc_trk_g3_3 input_2_4 (33 9) routing lc_trk_g3_5 input_2_4 (33 9) routing lc_trk_g3_7 input_2_4 (34 0) routing lc_trk_g1_0 wire_logic_cluster/lc_0/in_3 (34 0) routing lc_trk_g1_2 wire_logic_cluster/lc_0/in_3 (34 0) routing lc_trk_g1_4 wire_logic_cluster/lc_0/in_3 (34 0) routing lc_trk_g1_6 wire_logic_cluster/lc_0/in_3 (34 0) routing lc_trk_g3_0 wire_logic_cluster/lc_0/in_3 (34 0) routing lc_trk_g3_2 wire_logic_cluster/lc_0/in_3 (34 0) routing lc_trk_g3_4 wire_logic_cluster/lc_0/in_3 (34 0) routing lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 (34 1) routing lc_trk_g1_1 input_2_0 (34 1) routing lc_trk_g1_3 input_2_0 (34 1) routing lc_trk_g1_5 input_2_0 (34 1) routing lc_trk_g1_7 input_2_0 (34 1) routing lc_trk_g3_1 input_2_0 (34 1) routing lc_trk_g3_3 input_2_0 (34 1) routing lc_trk_g3_5 input_2_0 (34 1) routing lc_trk_g3_7 input_2_0 (34 10) routing lc_trk_g1_1 wire_logic_cluster/lc_5/in_3 (34 10) routing lc_trk_g1_3 wire_logic_cluster/lc_5/in_3 (34 10) routing lc_trk_g1_5 wire_logic_cluster/lc_5/in_3 (34 10) routing lc_trk_g1_7 wire_logic_cluster/lc_5/in_3 (34 10) routing lc_trk_g3_1 wire_logic_cluster/lc_5/in_3 (34 10) routing lc_trk_g3_3 wire_logic_cluster/lc_5/in_3 (34 10) routing lc_trk_g3_5 wire_logic_cluster/lc_5/in_3 (34 10) routing lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 (34 11) routing lc_trk_g1_0 input_2_5 (34 11) routing lc_trk_g1_2 input_2_5 (34 11) routing lc_trk_g1_4 input_2_5 (34 11) routing lc_trk_g1_6 input_2_5 (34 11) routing lc_trk_g3_0 input_2_5 (34 11) routing lc_trk_g3_2 input_2_5 (34 11) routing lc_trk_g3_4 input_2_5 (34 11) routing lc_trk_g3_6 input_2_5 (34 12) routing lc_trk_g1_0 wire_logic_cluster/lc_6/in_3 (34 12) routing lc_trk_g1_2 wire_logic_cluster/lc_6/in_3 (34 12) routing lc_trk_g1_4 wire_logic_cluster/lc_6/in_3 (34 12) routing lc_trk_g1_6 wire_logic_cluster/lc_6/in_3 (34 12) routing lc_trk_g3_0 wire_logic_cluster/lc_6/in_3 (34 12) routing lc_trk_g3_2 wire_logic_cluster/lc_6/in_3 (34 12) routing lc_trk_g3_4 wire_logic_cluster/lc_6/in_3 (34 12) routing lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 (34 13) routing lc_trk_g1_1 input_2_6 (34 13) routing lc_trk_g1_3 input_2_6 (34 13) routing lc_trk_g1_5 input_2_6 (34 13) routing lc_trk_g1_7 input_2_6 (34 13) routing lc_trk_g3_1 input_2_6 (34 13) routing lc_trk_g3_3 input_2_6 (34 13) routing lc_trk_g3_5 input_2_6 (34 13) routing lc_trk_g3_7 input_2_6 (34 14) routing lc_trk_g1_1 wire_logic_cluster/lc_7/in_3 (34 14) routing lc_trk_g1_3 wire_logic_cluster/lc_7/in_3 (34 14) routing lc_trk_g1_5 wire_logic_cluster/lc_7/in_3 (34 14) routing lc_trk_g1_7 wire_logic_cluster/lc_7/in_3 (34 14) routing lc_trk_g3_1 wire_logic_cluster/lc_7/in_3 (34 14) routing lc_trk_g3_3 wire_logic_cluster/lc_7/in_3 (34 14) routing lc_trk_g3_5 wire_logic_cluster/lc_7/in_3 (34 14) routing lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 (34 15) routing lc_trk_g1_0 input_2_7 (34 15) routing lc_trk_g1_2 input_2_7 (34 15) routing lc_trk_g1_4 input_2_7 (34 15) routing lc_trk_g1_6 input_2_7 (34 15) routing lc_trk_g3_0 input_2_7 (34 15) routing lc_trk_g3_2 input_2_7 (34 15) routing lc_trk_g3_4 input_2_7 (34 15) routing lc_trk_g3_6 input_2_7 (34 2) routing lc_trk_g1_1 wire_logic_cluster/lc_1/in_3 (34 2) routing lc_trk_g1_3 wire_logic_cluster/lc_1/in_3 (34 2) routing lc_trk_g1_5 wire_logic_cluster/lc_1/in_3 (34 2) routing lc_trk_g1_7 wire_logic_cluster/lc_1/in_3 (34 2) routing lc_trk_g3_1 wire_logic_cluster/lc_1/in_3 (34 2) routing lc_trk_g3_3 wire_logic_cluster/lc_1/in_3 (34 2) routing lc_trk_g3_5 wire_logic_cluster/lc_1/in_3 (34 2) routing lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 (34 3) routing lc_trk_g1_0 input_2_1 (34 3) routing lc_trk_g1_2 input_2_1 (34 3) routing lc_trk_g1_4 input_2_1 (34 3) routing lc_trk_g1_6 input_2_1 (34 3) routing lc_trk_g3_0 input_2_1 (34 3) routing lc_trk_g3_2 input_2_1 (34 3) routing lc_trk_g3_4 input_2_1 (34 3) routing lc_trk_g3_6 input_2_1 (34 4) routing lc_trk_g1_0 wire_logic_cluster/lc_2/in_3 (34 4) routing lc_trk_g1_2 wire_logic_cluster/lc_2/in_3 (34 4) routing lc_trk_g1_4 wire_logic_cluster/lc_2/in_3 (34 4) routing lc_trk_g1_6 wire_logic_cluster/lc_2/in_3 (34 4) routing lc_trk_g3_0 wire_logic_cluster/lc_2/in_3 (34 4) routing lc_trk_g3_2 wire_logic_cluster/lc_2/in_3 (34 4) routing lc_trk_g3_4 wire_logic_cluster/lc_2/in_3 (34 4) routing lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 (34 5) routing lc_trk_g1_1 input_2_2 (34 5) routing lc_trk_g1_3 input_2_2 (34 5) routing lc_trk_g1_5 input_2_2 (34 5) routing lc_trk_g1_7 input_2_2 (34 5) routing lc_trk_g3_1 input_2_2 (34 5) routing lc_trk_g3_3 input_2_2 (34 5) routing lc_trk_g3_5 input_2_2 (34 5) routing lc_trk_g3_7 input_2_2 (34 6) routing lc_trk_g1_1 wire_logic_cluster/lc_3/in_3 (34 6) routing lc_trk_g1_3 wire_logic_cluster/lc_3/in_3 (34 6) routing lc_trk_g1_5 wire_logic_cluster/lc_3/in_3 (34 6) routing lc_trk_g1_7 wire_logic_cluster/lc_3/in_3 (34 6) routing lc_trk_g3_1 wire_logic_cluster/lc_3/in_3 (34 6) routing lc_trk_g3_3 wire_logic_cluster/lc_3/in_3 (34 6) routing lc_trk_g3_5 wire_logic_cluster/lc_3/in_3 (34 6) routing lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 (34 7) routing lc_trk_g1_0 input_2_3 (34 7) routing lc_trk_g1_2 input_2_3 (34 7) routing lc_trk_g1_4 input_2_3 (34 7) routing lc_trk_g1_6 input_2_3 (34 7) routing lc_trk_g3_0 input_2_3 (34 7) routing lc_trk_g3_2 input_2_3 (34 7) routing lc_trk_g3_4 input_2_3 (34 7) routing lc_trk_g3_6 input_2_3 (34 8) routing lc_trk_g1_0 wire_logic_cluster/lc_4/in_3 (34 8) routing lc_trk_g1_2 wire_logic_cluster/lc_4/in_3 (34 8) routing lc_trk_g1_4 wire_logic_cluster/lc_4/in_3 (34 8) routing lc_trk_g1_6 wire_logic_cluster/lc_4/in_3 (34 8) routing lc_trk_g3_0 wire_logic_cluster/lc_4/in_3 (34 8) routing lc_trk_g3_2 wire_logic_cluster/lc_4/in_3 (34 8) routing lc_trk_g3_4 wire_logic_cluster/lc_4/in_3 (34 8) routing lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 (34 9) routing lc_trk_g1_1 input_2_4 (34 9) routing lc_trk_g1_3 input_2_4 (34 9) routing lc_trk_g1_5 input_2_4 (34 9) routing lc_trk_g1_7 input_2_4 (34 9) routing lc_trk_g3_1 input_2_4 (34 9) routing lc_trk_g3_3 input_2_4 (34 9) routing lc_trk_g3_5 input_2_4 (34 9) routing lc_trk_g3_7 input_2_4 (35 0) routing lc_trk_g0_4 input_2_0 (35 0) routing lc_trk_g0_6 input_2_0 (35 0) routing lc_trk_g1_5 input_2_0 (35 0) routing lc_trk_g1_7 input_2_0 (35 0) routing lc_trk_g2_4 input_2_0 (35 0) routing lc_trk_g2_6 input_2_0 (35 0) routing lc_trk_g3_5 input_2_0 (35 0) routing lc_trk_g3_7 input_2_0 (35 1) routing lc_trk_g0_2 input_2_0 (35 1) routing lc_trk_g0_6 input_2_0 (35 1) routing lc_trk_g1_3 input_2_0 (35 1) routing lc_trk_g1_7 input_2_0 (35 1) routing lc_trk_g2_2 input_2_0 (35 1) routing lc_trk_g2_6 input_2_0 (35 1) routing lc_trk_g3_3 input_2_0 (35 1) routing lc_trk_g3_7 input_2_0 (35 10) routing lc_trk_g0_5 input_2_5 (35 10) routing lc_trk_g0_7 input_2_5 (35 10) routing lc_trk_g1_4 input_2_5 (35 10) routing lc_trk_g1_6 input_2_5 (35 10) routing lc_trk_g2_5 input_2_5 (35 10) routing lc_trk_g2_7 input_2_5 (35 10) routing lc_trk_g3_4 input_2_5 (35 10) routing lc_trk_g3_6 input_2_5 (35 11) routing lc_trk_g0_3 input_2_5 (35 11) routing lc_trk_g0_7 input_2_5 (35 11) routing lc_trk_g1_2 input_2_5 (35 11) routing lc_trk_g1_6 input_2_5 (35 11) routing lc_trk_g2_3 input_2_5 (35 11) routing lc_trk_g2_7 input_2_5 (35 11) routing lc_trk_g3_2 input_2_5 (35 11) routing lc_trk_g3_6 input_2_5 (35 12) routing lc_trk_g0_4 input_2_6 (35 12) routing lc_trk_g0_6 input_2_6 (35 12) routing lc_trk_g1_5 input_2_6 (35 12) routing lc_trk_g1_7 input_2_6 (35 12) routing lc_trk_g2_4 input_2_6 (35 12) routing lc_trk_g2_6 input_2_6 (35 12) routing lc_trk_g3_5 input_2_6 (35 12) routing lc_trk_g3_7 input_2_6 (35 13) routing lc_trk_g0_2 input_2_6 (35 13) routing lc_trk_g0_6 input_2_6 (35 13) routing lc_trk_g1_3 input_2_6 (35 13) routing lc_trk_g1_7 input_2_6 (35 13) routing lc_trk_g2_2 input_2_6 (35 13) routing lc_trk_g2_6 input_2_6 (35 13) routing lc_trk_g3_3 input_2_6 (35 13) routing lc_trk_g3_7 input_2_6 (35 14) routing lc_trk_g0_5 input_2_7 (35 14) routing lc_trk_g0_7 input_2_7 (35 14) routing lc_trk_g1_4 input_2_7 (35 14) routing lc_trk_g1_6 input_2_7 (35 14) routing lc_trk_g2_5 input_2_7 (35 14) routing lc_trk_g2_7 input_2_7 (35 14) routing lc_trk_g3_4 input_2_7 (35 14) routing lc_trk_g3_6 input_2_7 (35 15) routing lc_trk_g0_3 input_2_7 (35 15) routing lc_trk_g0_7 input_2_7 (35 15) routing lc_trk_g1_2 input_2_7 (35 15) routing lc_trk_g1_6 input_2_7 (35 15) routing lc_trk_g2_3 input_2_7 (35 15) routing lc_trk_g2_7 input_2_7 (35 15) routing lc_trk_g3_2 input_2_7 (35 15) routing lc_trk_g3_6 input_2_7 (35 2) routing lc_trk_g0_5 input_2_1 (35 2) routing lc_trk_g0_7 input_2_1 (35 2) routing lc_trk_g1_4 input_2_1 (35 2) routing lc_trk_g1_6 input_2_1 (35 2) routing lc_trk_g2_5 input_2_1 (35 2) routing lc_trk_g2_7 input_2_1 (35 2) routing lc_trk_g3_4 input_2_1 (35 2) routing lc_trk_g3_6 input_2_1 (35 3) routing lc_trk_g0_3 input_2_1 (35 3) routing lc_trk_g0_7 input_2_1 (35 3) routing lc_trk_g1_2 input_2_1 (35 3) routing lc_trk_g1_6 input_2_1 (35 3) routing lc_trk_g2_3 input_2_1 (35 3) routing lc_trk_g2_7 input_2_1 (35 3) routing lc_trk_g3_2 input_2_1 (35 3) routing lc_trk_g3_6 input_2_1 (35 4) routing lc_trk_g0_4 input_2_2 (35 4) routing lc_trk_g0_6 input_2_2 (35 4) routing lc_trk_g1_5 input_2_2 (35 4) routing lc_trk_g1_7 input_2_2 (35 4) routing lc_trk_g2_4 input_2_2 (35 4) routing lc_trk_g2_6 input_2_2 (35 4) routing lc_trk_g3_5 input_2_2 (35 4) routing lc_trk_g3_7 input_2_2 (35 5) routing lc_trk_g0_2 input_2_2 (35 5) routing lc_trk_g0_6 input_2_2 (35 5) routing lc_trk_g1_3 input_2_2 (35 5) routing lc_trk_g1_7 input_2_2 (35 5) routing lc_trk_g2_2 input_2_2 (35 5) routing lc_trk_g2_6 input_2_2 (35 5) routing lc_trk_g3_3 input_2_2 (35 5) routing lc_trk_g3_7 input_2_2 (35 6) routing lc_trk_g0_5 input_2_3 (35 6) routing lc_trk_g0_7 input_2_3 (35 6) routing lc_trk_g1_4 input_2_3 (35 6) routing lc_trk_g1_6 input_2_3 (35 6) routing lc_trk_g2_5 input_2_3 (35 6) routing lc_trk_g2_7 input_2_3 (35 6) routing lc_trk_g3_4 input_2_3 (35 6) routing lc_trk_g3_6 input_2_3 (35 7) routing lc_trk_g0_3 input_2_3 (35 7) routing lc_trk_g0_7 input_2_3 (35 7) routing lc_trk_g1_2 input_2_3 (35 7) routing lc_trk_g1_6 input_2_3 (35 7) routing lc_trk_g2_3 input_2_3 (35 7) routing lc_trk_g2_7 input_2_3 (35 7) routing lc_trk_g3_2 input_2_3 (35 7) routing lc_trk_g3_6 input_2_3 (35 8) routing lc_trk_g0_4 input_2_4 (35 8) routing lc_trk_g0_6 input_2_4 (35 8) routing lc_trk_g1_5 input_2_4 (35 8) routing lc_trk_g1_7 input_2_4 (35 8) routing lc_trk_g2_4 input_2_4 (35 8) routing lc_trk_g2_6 input_2_4 (35 8) routing lc_trk_g3_5 input_2_4 (35 8) routing lc_trk_g3_7 input_2_4 (35 9) routing lc_trk_g0_2 input_2_4 (35 9) routing lc_trk_g0_6 input_2_4 (35 9) routing lc_trk_g1_3 input_2_4 (35 9) routing lc_trk_g1_7 input_2_4 (35 9) routing lc_trk_g2_2 input_2_4 (35 9) routing lc_trk_g2_6 input_2_4 (35 9) routing lc_trk_g3_3 input_2_4 (35 9) routing lc_trk_g3_7 input_2_4 (36 0) LC_0 Logic Functioning bit (36 1) LC_0 Logic Functioning bit (36 10) LC_5 Logic Functioning bit (36 11) LC_5 Logic Functioning bit (36 12) LC_6 Logic Functioning bit (36 13) LC_6 Logic Functioning bit (36 14) LC_7 Logic Functioning bit (36 15) LC_7 Logic Functioning bit (36 2) LC_1 Logic Functioning bit (36 3) LC_1 Logic Functioning bit (36 4) LC_2 Logic Functioning bit (36 5) LC_2 Logic Functioning bit (36 6) LC_3 Logic Functioning bit (36 7) LC_3 Logic Functioning bit (36 8) LC_4 Logic Functioning bit (36 9) LC_4 Logic Functioning bit (37 0) LC_0 Logic Functioning bit (37 1) LC_0 Logic Functioning bit (37 10) LC_5 Logic Functioning bit (37 11) LC_5 Logic Functioning bit (37 12) LC_6 Logic Functioning bit (37 13) LC_6 Logic Functioning bit (37 14) LC_7 Logic Functioning bit (37 15) LC_7 Logic Functioning bit (37 2) LC_1 Logic Functioning bit (37 3) LC_1 Logic Functioning bit (37 4) LC_2 Logic Functioning bit (37 5) LC_2 Logic Functioning bit (37 6) LC_3 Logic Functioning bit (37 7) LC_3 Logic Functioning bit (37 8) LC_4 Logic Functioning bit (37 9) LC_4 Logic Functioning bit (38 0) LC_0 Logic Functioning bit (38 1) LC_0 Logic Functioning bit (38 10) LC_5 Logic Functioning bit (38 11) LC_5 Logic Functioning bit (38 12) LC_6 Logic Functioning bit (38 13) LC_6 Logic Functioning bit (38 14) LC_7 Logic Functioning bit (38 15) LC_7 Logic Functioning bit (38 2) LC_1 Logic Functioning bit (38 3) LC_1 Logic Functioning bit (38 4) LC_2 Logic Functioning bit (38 5) LC_2 Logic Functioning bit (38 6) LC_3 Logic Functioning bit (38 7) LC_3 Logic Functioning bit (38 8) LC_4 Logic Functioning bit (38 9) LC_4 Logic Functioning bit (39 0) LC_0 Logic Functioning bit (39 1) LC_0 Logic Functioning bit (39 10) LC_5 Logic Functioning bit (39 11) LC_5 Logic Functioning bit (39 12) LC_6 Logic Functioning bit (39 13) LC_6 Logic Functioning bit (39 14) LC_7 Logic Functioning bit (39 15) LC_7 Logic Functioning bit (39 2) LC_1 Logic Functioning bit (39 3) LC_1 Logic Functioning bit (39 4) LC_2 Logic Functioning bit (39 5) LC_2 Logic Functioning bit (39 6) LC_3 Logic Functioning bit (39 7) LC_3 Logic Functioning bit (39 8) LC_4 Logic Functioning bit (39 9) LC_4 Logic Functioning bit (4 0) routing sp4_h_l_37 sp4_v_b_0 (4 0) routing sp4_h_l_43 sp4_v_b_0 (4 0) routing sp4_v_t_37 sp4_v_b_0 (4 0) routing sp4_v_t_41 sp4_v_b_0 (4 1) routing sp4_h_l_41 sp4_h_r_0 (4 1) routing sp4_h_l_44 sp4_h_r_0 (4 1) routing sp4_v_b_6 sp4_h_r_0 (4 1) routing sp4_v_t_42 sp4_h_r_0 (4 10) routing sp4_h_r_0 sp4_v_t_43 (4 10) routing sp4_h_r_6 sp4_v_t_43 (4 10) routing sp4_v_b_10 sp4_v_t_43 (4 10) routing sp4_v_b_6 sp4_v_t_43 (4 11) routing sp4_h_r_10 sp4_h_l_43 (4 11) routing sp4_h_r_3 sp4_h_l_43 (4 11) routing sp4_v_b_1 sp4_h_l_43 (4 11) routing sp4_v_t_37 sp4_h_l_43 (4 12) routing sp4_h_l_38 sp4_v_b_9 (4 12) routing sp4_h_l_44 sp4_v_b_9 (4 12) routing sp4_v_t_36 sp4_v_b_9 (4 12) routing sp4_v_t_44 sp4_v_b_9 (4 13) routing sp4_h_l_36 sp4_h_r_9 (4 13) routing sp4_h_l_43 sp4_h_r_9 (4 13) routing sp4_v_b_3 sp4_h_r_9 (4 13) routing sp4_v_t_41 sp4_h_r_9 (4 14) routing sp4_h_r_3 sp4_v_t_44 (4 14) routing sp4_h_r_9 sp4_v_t_44 (4 14) routing sp4_v_b_1 sp4_v_t_44 (4 14) routing sp4_v_b_9 sp4_v_t_44 (4 15) routing sp4_h_r_1 sp4_h_l_44 (4 15) routing sp4_h_r_6 sp4_h_l_44 (4 15) routing sp4_v_b_4 sp4_h_l_44 (4 15) routing sp4_v_t_38 sp4_h_l_44 (4 2) routing sp4_h_r_0 sp4_v_t_37 (4 2) routing sp4_h_r_6 sp4_v_t_37 (4 2) routing sp4_v_b_0 sp4_v_t_37 (4 2) routing sp4_v_b_4 sp4_v_t_37 (4 3) routing sp4_h_r_4 sp4_h_l_37 (4 3) routing sp4_h_r_9 sp4_h_l_37 (4 3) routing sp4_v_b_7 sp4_h_l_37 (4 3) routing sp4_v_t_43 sp4_h_l_37 (4 4) routing sp4_h_l_38 sp4_v_b_3 (4 4) routing sp4_h_l_44 sp4_v_b_3 (4 4) routing sp4_v_t_38 sp4_v_b_3 (4 4) routing sp4_v_t_42 sp4_v_b_3 (4 5) routing sp4_h_l_37 sp4_h_r_3 (4 5) routing sp4_h_l_42 sp4_h_r_3 (4 5) routing sp4_v_b_9 sp4_h_r_3 (4 5) routing sp4_v_t_47 sp4_h_r_3 (4 6) routing sp4_h_r_3 sp4_v_t_38 (4 6) routing sp4_h_r_9 sp4_v_t_38 (4 6) routing sp4_v_b_3 sp4_v_t_38 (4 6) routing sp4_v_b_7 sp4_v_t_38 (4 7) routing sp4_h_r_0 sp4_h_l_38 (4 7) routing sp4_h_r_7 sp4_h_l_38 (4 7) routing sp4_v_b_10 sp4_h_l_38 (4 7) routing sp4_v_t_44 sp4_h_l_38 (4 8) routing sp4_h_l_37 sp4_v_b_6 (4 8) routing sp4_h_l_43 sp4_v_b_6 (4 8) routing sp4_v_t_43 sp4_v_b_6 (4 8) routing sp4_v_t_47 sp4_v_b_6 (4 9) routing sp4_h_l_38 sp4_h_r_6 (4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) LC_0 Logic Functioning bit (40 1) LC_0 Logic Functioning bit (40 10) LC_5 Logic Functioning bit (40 11) LC_5 Logic Functioning bit (40 12) LC_6 Logic Functioning bit (40 13) LC_6 Logic Functioning bit (40 14) LC_7 Logic Functioning bit (40 15) LC_7 Logic Functioning bit (40 2) LC_1 Logic Functioning bit (40 3) LC_1 Logic Functioning bit (40 4) LC_2 Logic Functioning bit (40 5) LC_2 Logic Functioning bit (40 6) LC_3 Logic Functioning bit (40 7) LC_3 Logic Functioning bit (40 8) LC_4 Logic Functioning bit (40 9) LC_4 Logic Functioning bit (41 0) LC_0 Logic Functioning bit (41 1) LC_0 Logic Functioning bit (41 10) LC_5 Logic Functioning bit (41 11) LC_5 Logic Functioning bit (41 12) LC_6 Logic Functioning bit (41 13) LC_6 Logic Functioning bit (41 14) LC_7 Logic Functioning bit (41 15) LC_7 Logic Functioning bit (41 2) LC_1 Logic Functioning bit (41 3) LC_1 Logic Functioning bit (41 4) LC_2 Logic Functioning bit (41 5) LC_2 Logic Functioning bit (41 6) LC_3 Logic Functioning bit (41 7) LC_3 Logic Functioning bit (41 8) LC_4 Logic Functioning bit (41 9) LC_4 Logic Functioning bit (42 0) LC_0 Logic Functioning bit (42 1) LC_0 Logic Functioning bit (42 10) LC_5 Logic Functioning bit (42 11) LC_5 Logic Functioning bit (42 12) LC_6 Logic Functioning bit (42 13) LC_6 Logic Functioning bit (42 14) LC_7 Logic Functioning bit (42 15) LC_7 Logic Functioning bit (42 2) LC_1 Logic Functioning bit (42 3) LC_1 Logic Functioning bit (42 4) LC_2 Logic Functioning bit (42 5) LC_2 Logic Functioning bit (42 6) LC_3 Logic Functioning bit (42 7) LC_3 Logic Functioning bit (42 8) LC_4 Logic Functioning bit (42 9) LC_4 Logic Functioning bit (43 0) LC_0 Logic Functioning bit (43 1) LC_0 Logic Functioning bit (43 10) LC_5 Logic Functioning bit (43 11) LC_5 Logic Functioning bit (43 12) LC_6 Logic Functioning bit (43 13) LC_6 Logic Functioning bit (43 14) LC_7 Logic Functioning bit (43 15) LC_7 Logic Functioning bit (43 2) LC_1 Logic Functioning bit (43 3) LC_1 Logic Functioning bit (43 4) LC_2 Logic Functioning bit (43 5) LC_2 Logic Functioning bit (43 6) LC_3 Logic Functioning bit (43 7) LC_3 Logic Functioning bit (43 8) LC_4 Logic Functioning bit (43 9) LC_4 Logic Functioning bit (44 0) LC_0 Logic Functioning bit (44 1) LC_0 Logic Functioning bit (44 10) LC_5 Logic Functioning bit (44 11) LC_5 Logic Functioning bit (44 12) LC_6 Logic Functioning bit (44 13) LC_6 Logic Functioning bit (44 14) LC_7 Logic Functioning bit (44 15) LC_7 Logic Functioning bit (44 2) LC_1 Logic Functioning bit (44 3) LC_1 Logic Functioning bit (44 4) LC_2 Logic Functioning bit (44 5) LC_2 Logic Functioning bit (44 6) LC_3 Logic Functioning bit (44 7) LC_3 Logic Functioning bit (44 8) LC_4 Logic Functioning bit (44 9) LC_4 Logic Functioning bit (45 0) LC_0 Logic Functioning bit (45 1) LC_0 Logic Functioning bit (45 10) LC_5 Logic Functioning bit (45 11) LC_5 Logic Functioning bit (45 12) LC_6 Logic Functioning bit (45 13) LC_6 Logic Functioning bit (45 14) LC_7 Logic Functioning bit (45 15) LC_7 Logic Functioning bit (45 2) LC_1 Logic Functioning bit (45 3) LC_1 Logic Functioning bit (45 4) LC_2 Logic Functioning bit (45 5) LC_2 Logic Functioning bit (45 6) LC_3 Logic Functioning bit (45 7) LC_3 Logic Functioning bit (45 8) LC_4 Logic Functioning bit (45 9) LC_4 Logic Functioning bit (46 0) Enable bit of Mux _out_links/OutMux7_0 => wire_logic_cluster/lc_0/out sp4_h_l_5 (46 1) Enable bit of Mux _out_links/OutMux6_0 => wire_logic_cluster/lc_0/out sp4_h_r_0 (46 10) Enable bit of Mux _out_links/OutMux7_5 => wire_logic_cluster/lc_5/out sp4_h_l_15 (46 11) Enable bit of Mux _out_links/OutMux6_5 => wire_logic_cluster/lc_5/out sp4_h_r_10 (46 12) Enable bit of Mux _out_links/OutMux7_6 => wire_logic_cluster/lc_6/out sp4_h_l_17 (46 13) Enable bit of Mux _out_links/OutMux6_6 => wire_logic_cluster/lc_6/out sp4_h_l_1 (46 14) Enable bit of Mux _out_links/OutMux7_7 => wire_logic_cluster/lc_7/out sp4_h_r_30 (46 15) Enable bit of Mux _out_links/OutMux6_7 => wire_logic_cluster/lc_7/out sp4_h_r_14 (46 2) Enable bit of Mux _out_links/OutMux7_1 => wire_logic_cluster/lc_1/out sp4_h_l_7 (46 3) Enable bit of Mux _out_links/OutMux6_1 => wire_logic_cluster/lc_1/out sp4_h_r_2 (46 4) Enable bit of Mux _out_links/OutMux7_2 => wire_logic_cluster/lc_2/out sp4_h_l_9 (46 5) Enable bit of Mux _out_links/OutMux6_2 => wire_logic_cluster/lc_2/out sp4_h_r_4 (46 6) Enable bit of Mux _out_links/OutMux7_3 => wire_logic_cluster/lc_3/out sp4_h_l_11 (46 7) Enable bit of Mux _out_links/OutMux6_3 => wire_logic_cluster/lc_3/out sp4_h_r_6 (46 8) Enable bit of Mux _out_links/OutMux7_4 => wire_logic_cluster/lc_4/out sp4_h_r_24 (46 9) Enable bit of Mux _out_links/OutMux6_4 => wire_logic_cluster/lc_4/out sp4_h_r_8 (47 0) Enable bit of Mux _out_links/OutMux5_0 => wire_logic_cluster/lc_0/out sp12_h_r_8 (47 1) Enable bit of Mux _out_links/OutMux8_0 => wire_logic_cluster/lc_0/out sp4_h_l_21 (47 10) Enable bit of Mux _out_links/OutMux4_5 => wire_logic_cluster/lc_5/out sp12_h_r_2 (47 11) Enable bit of Mux _out_links/OutMux8_5 => wire_logic_cluster/lc_5/out sp4_h_r_42 (47 12) Enable bit of Mux _out_links/OutMux4_6 => wire_logic_cluster/lc_6/out sp12_h_l_3 (47 13) Enable bit of Mux _out_links/OutMux8_6 => wire_logic_cluster/lc_6/out sp4_h_r_44 (47 14) Enable bit of Mux _out_links/OutMux4_7 => wire_logic_cluster/lc_7/out sp12_h_l_5 (47 15) Enable bit of Mux _out_links/OutMux8_7 => wire_logic_cluster/lc_7/out sp4_h_r_46 (47 2) Enable bit of Mux _out_links/OutMux5_1 => wire_logic_cluster/lc_1/out sp12_h_r_10 (47 3) Enable bit of Mux _out_links/OutMux8_1 => wire_logic_cluster/lc_1/out sp4_h_r_34 (47 4) Enable bit of Mux _out_links/OutMux5_2 => wire_logic_cluster/lc_2/out sp12_h_r_12 (47 5) Enable bit of Mux _out_links/OutMux8_2 => wire_logic_cluster/lc_2/out sp4_h_r_36 (47 6) Enable bit of Mux _out_links/OutMux5_3 => wire_logic_cluster/lc_3/out sp12_h_r_14 (47 7) Enable bit of Mux _out_links/OutMux8_3 => wire_logic_cluster/lc_3/out sp4_h_r_38 (47 8) Enable bit of Mux _out_links/OutMux4_4 => wire_logic_cluster/lc_4/out sp12_h_r_0 (47 9) Enable bit of Mux _out_links/OutMux8_4 => wire_logic_cluster/lc_4/out sp4_h_r_40 (48 0) Enable bit of Mux _out_links/OutMux0_0 => wire_logic_cluster/lc_0/out sp4_v_b_0 (48 1) Enable bit of Mux _out_links/OutMux1_0 => wire_logic_cluster/lc_0/out sp4_v_t_5 (48 10) Enable bit of Mux _out_links/OutMux5_5 => wire_logic_cluster/lc_5/out sp12_h_l_17 (48 11) Enable bit of Mux _out_links/OutMux0_5 => wire_logic_cluster/lc_5/out sp4_v_b_10 (48 12) Enable bit of Mux _out_links/OutMux5_6 => wire_logic_cluster/lc_6/out sp12_h_r_20 (48 13) Enable bit of Mux _out_links/OutMux0_6 => wire_logic_cluster/lc_6/out sp4_v_t_1 (48 14) Enable bit of Mux _out_links/OutMux5_7 => wire_logic_cluster/lc_7/out sp12_h_l_21 (48 15) Enable bit of Mux _out_links/OutMux0_7 => wire_logic_cluster/lc_7/out sp4_v_t_3 (48 2) Enable bit of Mux _out_links/OutMux0_1 => wire_logic_cluster/lc_1/out sp4_v_b_2 (48 3) Enable bit of Mux _out_links/OutMux1_1 => wire_logic_cluster/lc_1/out sp4_v_b_18 (48 4) Enable bit of Mux _out_links/OutMux0_2 => wire_logic_cluster/lc_2/out sp4_v_b_4 (48 5) Enable bit of Mux _out_links/OutMux1_2 => wire_logic_cluster/lc_2/out sp4_v_t_9 (48 6) Enable bit of Mux _out_links/OutMux0_3 => wire_logic_cluster/lc_3/out sp4_v_b_6 (48 7) Enable bit of Mux _out_links/OutMux1_3 => wire_logic_cluster/lc_3/out sp4_v_b_22 (48 8) Enable bit of Mux _out_links/OutMux5_4 => wire_logic_cluster/lc_4/out sp12_h_r_16 (48 9) Enable bit of Mux _out_links/OutMux0_4 => wire_logic_cluster/lc_4/out sp4_v_b_8 (49 1) Carry_In_Mux bit (49 1) Carry_In_Mux bit (5 0) routing sp4_h_l_44 sp4_h_r_0 (5 0) routing sp4_v_b_0 sp4_h_r_0 (5 0) routing sp4_v_b_6 sp4_h_r_0 (5 0) routing sp4_v_t_37 sp4_h_r_0 (5 1) routing sp4_h_l_37 sp4_v_b_0 (5 1) routing sp4_h_l_43 sp4_v_b_0 (5 1) routing sp4_h_r_0 sp4_v_b_0 (5 1) routing sp4_v_t_44 sp4_v_b_0 (5 10) routing sp4_h_r_3 sp4_h_l_43 (5 10) routing sp4_v_b_6 sp4_h_l_43 (5 10) routing sp4_v_t_37 sp4_h_l_43 (5 10) routing sp4_v_t_43 sp4_h_l_43 (5 11) routing sp4_h_l_43 sp4_v_t_43 (5 11) routing sp4_h_r_0 sp4_v_t_43 (5 11) routing sp4_h_r_6 sp4_v_t_43 (5 11) routing sp4_v_b_3 sp4_v_t_43 (5 12) routing sp4_h_l_43 sp4_h_r_9 (5 12) routing sp4_v_b_3 sp4_h_r_9 (5 12) routing sp4_v_b_9 sp4_h_r_9 (5 12) routing sp4_v_t_44 sp4_h_r_9 (5 13) routing sp4_h_l_38 sp4_v_b_9 (5 13) routing sp4_h_l_44 sp4_v_b_9 (5 13) routing sp4_h_r_9 sp4_v_b_9 (5 13) routing sp4_v_t_43 sp4_v_b_9 (5 14) routing sp4_h_r_6 sp4_h_l_44 (5 14) routing sp4_v_b_9 sp4_h_l_44 (5 14) routing sp4_v_t_38 sp4_h_l_44 (5 14) routing sp4_v_t_44 sp4_h_l_44 (5 15) routing sp4_h_l_44 sp4_v_t_44 (5 15) routing sp4_h_r_3 sp4_v_t_44 (5 15) routing sp4_h_r_9 sp4_v_t_44 (5 15) routing sp4_v_b_6 sp4_v_t_44 (5 2) routing sp4_h_r_9 sp4_h_l_37 (5 2) routing sp4_v_b_0 sp4_h_l_37 (5 2) routing sp4_v_t_37 sp4_h_l_37 (5 2) routing sp4_v_t_43 sp4_h_l_37 (5 3) routing sp4_h_l_37 sp4_v_t_37 (5 3) routing sp4_h_r_0 sp4_v_t_37 (5 3) routing sp4_h_r_6 sp4_v_t_37 (5 3) routing sp4_v_b_9 sp4_v_t_37 (5 4) routing sp4_h_l_37 sp4_h_r_3 (5 4) routing sp4_v_b_3 sp4_h_r_3 (5 4) routing sp4_v_b_9 sp4_h_r_3 (5 4) routing sp4_v_t_38 sp4_h_r_3 (5 5) routing sp4_h_l_38 sp4_v_b_3 (5 5) routing sp4_h_l_44 sp4_v_b_3 (5 5) routing sp4_h_r_3 sp4_v_b_3 (5 5) routing sp4_v_t_37 sp4_v_b_3 (5 6) routing sp4_h_r_0 sp4_h_l_38 (5 6) routing sp4_v_b_3 sp4_h_l_38 (5 6) routing sp4_v_t_38 sp4_h_l_38 (5 6) routing sp4_v_t_44 sp4_h_l_38 (5 7) routing sp4_h_l_38 sp4_v_t_38 (5 7) routing sp4_h_r_3 sp4_v_t_38 (5 7) routing sp4_h_r_9 sp4_v_t_38 (5 7) routing sp4_v_b_0 sp4_v_t_38 (5 8) routing sp4_h_l_38 sp4_h_r_6 (5 8) routing sp4_v_b_0 sp4_h_r_6 (5 8) routing sp4_v_b_6 sp4_h_r_6 (5 8) routing sp4_v_t_43 sp4_h_r_6 (5 9) routing sp4_h_l_37 sp4_v_b_6 (5 9) routing sp4_h_l_43 sp4_v_b_6 (5 9) routing sp4_h_r_6 sp4_v_b_6 (5 9) routing sp4_v_t_38 sp4_v_b_6 (50 1) Carry_In_Mux bit (50 1) Carry_In_Mux bit (50 10) Cascade bit: LH_LC05_inmux02_5 (50 12) Cascade bit: LH_LC06_inmux02_5 (50 14) Cascade bit: LH_LC07_inmux02_5 (50 2) Cascade bit: LH_LC01_inmux02_5 (50 4) Cascade bit: LH_LC02_inmux02_5 (50 6) Cascade bit: LH_LC03_inmux02_5 (50 8) Cascade bit: LH_LC04_inmux02_5 (51 0) Enable bit of Mux _out_links/OutMux3_0 => wire_logic_cluster/lc_0/out sp12_v_b_0 (51 1) Enable bit of Mux _out_links/OutMux2_0 => wire_logic_cluster/lc_0/out sp4_v_t_21 (51 10) Enable bit of Mux _out_links/OutMux2_5 => wire_logic_cluster/lc_5/out sp4_v_b_42 (51 11) Enable bit of Mux _out_links/OutMux1_5 => wire_logic_cluster/lc_5/out sp4_v_b_26 (51 12) Enable bit of Mux _out_links/OutMux2_6 => wire_logic_cluster/lc_6/out sp4_v_t_33 (51 13) Enable bit of Mux _out_links/OutMux1_6 => wire_logic_cluster/lc_6/out sp4_v_t_17 (51 14) Enable bit of Mux _out_links/OutMux2_7 => wire_logic_cluster/lc_7/out sp4_v_b_46 (51 15) Enable bit of Mux _out_links/OutMux1_7 => wire_logic_cluster/lc_7/out sp4_v_b_30 (51 2) Enable bit of Mux _out_links/OutMux3_1 => wire_logic_cluster/lc_1/out sp12_v_t_1 (51 3) Enable bit of Mux _out_links/OutMux2_1 => wire_logic_cluster/lc_1/out sp4_v_t_23 (51 4) Enable bit of Mux _out_links/OutMux3_2 => wire_logic_cluster/lc_2/out sp12_v_t_3 (51 5) Enable bit of Mux _out_links/OutMux2_2 => wire_logic_cluster/lc_2/out sp4_v_b_36 (51 6) Enable bit of Mux _out_links/OutMux3_3 => wire_logic_cluster/lc_3/out sp12_v_b_6 (51 7) Enable bit of Mux _out_links/OutMux2_3 => wire_logic_cluster/lc_3/out sp4_v_b_38 (51 8) Enable bit of Mux _out_links/OutMux2_4 => wire_logic_cluster/lc_4/out sp4_v_t_29 (51 9) Enable bit of Mux _out_links/OutMux1_4 => wire_logic_cluster/lc_4/out sp4_v_b_24 (52 0) Enable bit of Mux _out_links/OutMux4_0 => wire_logic_cluster/lc_0/out sp12_v_b_16 (52 1) Enable bit of Mux _out_links/OutMux9_0 => wire_logic_cluster/lc_0/out sp4_r_v_b_1 (52 10) Enable bit of Mux _out_links/OutMux3_5 => wire_logic_cluster/lc_5/out sp12_v_t_9 (52 11) Enable bit of Mux _out_links/OutMux9_5 => wire_logic_cluster/lc_5/out sp4_r_v_b_11 (52 12) Enable bit of Mux _out_links/OutMux3_6 => wire_logic_cluster/lc_6/out sp12_v_b_12 (52 13) Enable bit of Mux _out_links/OutMux9_6 => wire_logic_cluster/lc_6/out sp4_r_v_b_13 (52 14) Enable bit of Mux _out_links/OutMux3_7 => wire_logic_cluster/lc_7/out sp12_v_b_14 (52 15) Enable bit of Mux _out_links/OutMux9_7 => wire_logic_cluster/lc_7/out sp4_r_v_b_15 (52 2) Enable bit of Mux _out_links/OutMux4_1 => wire_logic_cluster/lc_1/out sp12_v_b_18 (52 3) Enable bit of Mux _out_links/OutMux9_1 => wire_logic_cluster/lc_1/out sp4_r_v_b_3 (52 4) Enable bit of Mux _out_links/OutMux4_2 => wire_logic_cluster/lc_2/out sp12_v_b_20 (52 5) Enable bit of Mux _out_links/OutMux9_2 => wire_logic_cluster/lc_2/out sp4_r_v_b_5 (52 6) Enable bit of Mux _out_links/OutMux4_3 => wire_logic_cluster/lc_3/out sp12_v_t_21 (52 7) Enable bit of Mux _out_links/OutMux9_3 => wire_logic_cluster/lc_3/out sp4_r_v_b_7 (52 8) Enable bit of Mux _out_links/OutMux3_4 => wire_logic_cluster/lc_4/out sp12_v_b_8 (52 9) Enable bit of Mux _out_links/OutMux9_4 => wire_logic_cluster/lc_4/out sp4_r_v_b_9 (53 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_logic_cluster/lc_0/out sp4_r_v_b_17 (53 1) Enable bit of Mux _out_links/OutMuxb_0 => wire_logic_cluster/lc_0/out sp4_r_v_b_33 (53 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_logic_cluster/lc_5/out sp4_r_v_b_27 (53 11) Enable bit of Mux _out_links/OutMuxb_5 => wire_logic_cluster/lc_5/out sp4_r_v_b_43 (53 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_logic_cluster/lc_6/out sp4_r_v_b_29 (53 13) Enable bit of Mux _out_links/OutMuxb_6 => wire_logic_cluster/lc_6/out sp4_r_v_b_45 (53 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_logic_cluster/lc_7/out sp4_r_v_b_31 (53 15) Enable bit of Mux _out_links/OutMuxb_7 => wire_logic_cluster/lc_7/out sp4_r_v_b_47 (53 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_logic_cluster/lc_1/out sp4_r_v_b_19 (53 3) Enable bit of Mux _out_links/OutMuxb_1 => wire_logic_cluster/lc_1/out sp4_r_v_b_35 (53 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_logic_cluster/lc_2/out sp4_r_v_b_21 (53 5) Enable bit of Mux _out_links/OutMuxb_2 => wire_logic_cluster/lc_2/out sp4_r_v_b_37 (53 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_logic_cluster/lc_3/out sp4_r_v_b_23 (53 7) Enable bit of Mux _out_links/OutMuxb_3 => wire_logic_cluster/lc_3/out sp4_r_v_b_39 (53 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_logic_cluster/lc_4/out sp4_r_v_b_25 (53 9) Enable bit of Mux _out_links/OutMuxb_4 => wire_logic_cluster/lc_4/out sp4_r_v_b_41 (6 0) routing sp4_h_l_43 sp4_v_b_0 (6 0) routing sp4_h_r_7 sp4_v_b_0 (6 0) routing sp4_v_t_41 sp4_v_b_0 (6 0) routing sp4_v_t_44 sp4_v_b_0 (6 1) routing sp4_h_l_37 sp4_h_r_0 (6 1) routing sp4_h_l_41 sp4_h_r_0 (6 1) routing sp4_v_b_0 sp4_h_r_0 (6 1) routing sp4_v_b_6 sp4_h_r_0 (6 10) routing sp4_h_l_36 sp4_v_t_43 (6 10) routing sp4_h_r_0 sp4_v_t_43 (6 10) routing sp4_v_b_10 sp4_v_t_43 (6 10) routing sp4_v_b_3 sp4_v_t_43 (6 11) routing sp4_h_r_10 sp4_h_l_43 (6 11) routing sp4_h_r_6 sp4_h_l_43 (6 11) routing sp4_v_t_37 sp4_h_l_43 (6 11) routing sp4_v_t_43 sp4_h_l_43 (6 12) routing sp4_h_l_38 sp4_v_b_9 (6 12) routing sp4_h_r_4 sp4_v_b_9 (6 12) routing sp4_v_t_36 sp4_v_b_9 (6 12) routing sp4_v_t_43 sp4_v_b_9 (6 13) routing sp4_h_l_36 sp4_h_r_9 (6 13) routing sp4_h_l_44 sp4_h_r_9 (6 13) routing sp4_v_b_3 sp4_h_r_9 (6 13) routing sp4_v_b_9 sp4_h_r_9 (6 14) routing sp4_h_l_41 sp4_v_t_44 (6 14) routing sp4_h_r_3 sp4_v_t_44 (6 14) routing sp4_v_b_1 sp4_v_t_44 (6 14) routing sp4_v_b_6 sp4_v_t_44 (6 15) routing sp4_h_r_1 sp4_h_l_44 (6 15) routing sp4_h_r_9 sp4_h_l_44 (6 15) routing sp4_v_t_38 sp4_h_l_44 (6 15) routing sp4_v_t_44 sp4_h_l_44 (6 2) routing sp4_h_l_42 sp4_v_t_37 (6 2) routing sp4_h_r_6 sp4_v_t_37 (6 2) routing sp4_v_b_4 sp4_v_t_37 (6 2) routing sp4_v_b_9 sp4_v_t_37 (6 3) routing sp4_h_r_0 sp4_h_l_37 (6 3) routing sp4_h_r_4 sp4_h_l_37 (6 3) routing sp4_v_t_37 sp4_h_l_37 (6 3) routing sp4_v_t_43 sp4_h_l_37 (6 4) routing sp4_h_l_44 sp4_v_b_3 (6 4) routing sp4_h_r_10 sp4_v_b_3 (6 4) routing sp4_v_t_37 sp4_v_b_3 (6 4) routing sp4_v_t_42 sp4_v_b_3 (6 5) routing sp4_h_l_38 sp4_h_r_3 (6 5) routing sp4_h_l_42 sp4_h_r_3 (6 5) routing sp4_v_b_3 sp4_h_r_3 (6 5) routing sp4_v_b_9 sp4_h_r_3 (6 6) routing sp4_h_l_47 sp4_v_t_38 (6 6) routing sp4_h_r_9 sp4_v_t_38 (6 6) routing sp4_v_b_0 sp4_v_t_38 (6 6) routing sp4_v_b_7 sp4_v_t_38 (6 7) routing sp4_h_r_3 sp4_h_l_38 (6 7) routing sp4_h_r_7 sp4_h_l_38 (6 7) routing sp4_v_t_38 sp4_h_l_38 (6 7) routing sp4_v_t_44 sp4_h_l_38 (6 8) routing sp4_h_l_37 sp4_v_b_6 (6 8) routing sp4_h_r_1 sp4_v_b_6 (6 8) routing sp4_v_t_38 sp4_v_b_6 (6 8) routing sp4_v_t_47 sp4_v_b_6 (6 9) routing sp4_h_l_43 sp4_h_r_6 (6 9) routing sp4_h_l_47 sp4_h_r_6 (6 9) routing sp4_v_b_0 sp4_h_r_6 (6 9) routing sp4_v_b_6 sp4_h_r_6 (7 10) Column buffer control bit: LH_colbuf_cntl_3 (7 11) Column buffer control bit: LH_colbuf_cntl_2 (7 12) Column buffer control bit: LH_colbuf_cntl_5 (7 13) Column buffer control bit: LH_colbuf_cntl_4 (7 14) Column buffer control bit: LH_colbuf_cntl_7 (7 15) Column buffer control bit: LH_colbuf_cntl_6 (7 8) Column buffer control bit: LH_colbuf_cntl_1 (7 9) Column buffer control bit: LH_colbuf_cntl_0 (8 0) routing sp4_h_l_36 sp4_h_r_1 (8 0) routing sp4_h_l_40 sp4_h_r_1 (8 0) routing sp4_v_b_1 sp4_h_r_1 (8 0) routing sp4_v_b_7 sp4_h_r_1 (8 1) routing sp4_h_l_36 sp4_v_b_1 (8 1) routing sp4_h_l_42 sp4_v_b_1 (8 1) routing sp4_h_r_1 sp4_v_b_1 (8 1) routing sp4_v_t_47 sp4_v_b_1 (8 10) routing sp4_h_r_11 sp4_h_l_42 (8 10) routing sp4_h_r_7 sp4_h_l_42 (8 10) routing sp4_v_t_36 sp4_h_l_42 (8 10) routing sp4_v_t_42 sp4_h_l_42 (8 11) routing sp4_h_l_42 sp4_v_t_42 (8 11) routing sp4_h_r_1 sp4_v_t_42 (8 11) routing sp4_h_r_7 sp4_v_t_42 (8 11) routing sp4_v_b_4 sp4_v_t_42 (8 12) routing sp4_h_l_39 sp4_h_r_10 (8 12) routing sp4_h_l_47 sp4_h_r_10 (8 12) routing sp4_v_b_10 sp4_h_r_10 (8 12) routing sp4_v_b_4 sp4_h_r_10 (8 13) routing sp4_h_l_41 sp4_v_b_10 (8 13) routing sp4_h_l_47 sp4_v_b_10 (8 13) routing sp4_h_r_10 sp4_v_b_10 (8 13) routing sp4_v_t_42 sp4_v_b_10 (8 14) routing sp4_h_r_10 sp4_h_l_47 (8 14) routing sp4_h_r_2 sp4_h_l_47 (8 14) routing sp4_v_t_41 sp4_h_l_47 (8 14) routing sp4_v_t_47 sp4_h_l_47 (8 15) routing sp4_h_l_47 sp4_v_t_47 (8 15) routing sp4_h_r_10 sp4_v_t_47 (8 15) routing sp4_h_r_4 sp4_v_t_47 (8 15) routing sp4_v_b_7 sp4_v_t_47 (8 2) routing sp4_h_r_1 sp4_h_l_36 (8 2) routing sp4_h_r_5 sp4_h_l_36 (8 2) routing sp4_v_t_36 sp4_h_l_36 (8 2) routing sp4_v_t_42 sp4_h_l_36 (8 3) routing sp4_h_l_36 sp4_v_t_36 (8 3) routing sp4_h_r_1 sp4_v_t_36 (8 3) routing sp4_h_r_7 sp4_v_t_36 (8 3) routing sp4_v_b_10 sp4_v_t_36 (8 4) routing sp4_h_l_41 sp4_h_r_4 (8 4) routing sp4_h_l_45 sp4_h_r_4 (8 4) routing sp4_v_b_10 sp4_h_r_4 (8 4) routing sp4_v_b_4 sp4_h_r_4 (8 5) routing sp4_h_l_41 sp4_v_b_4 (8 5) routing sp4_h_l_47 sp4_v_b_4 (8 5) routing sp4_h_r_4 sp4_v_b_4 (8 5) routing sp4_v_t_36 sp4_v_b_4 (8 6) routing sp4_h_r_4 sp4_h_l_41 (8 6) routing sp4_h_r_8 sp4_h_l_41 (8 6) routing sp4_v_t_41 sp4_h_l_41 (8 6) routing sp4_v_t_47 sp4_h_l_41 (8 7) routing sp4_h_l_41 sp4_v_t_41 (8 7) routing sp4_h_r_10 sp4_v_t_41 (8 7) routing sp4_h_r_4 sp4_v_t_41 (8 7) routing sp4_v_b_1 sp4_v_t_41 (8 8) routing sp4_h_l_42 sp4_h_r_7 (8 8) routing sp4_h_l_46 sp4_h_r_7 (8 8) routing sp4_v_b_1 sp4_h_r_7 (8 8) routing sp4_v_b_7 sp4_h_r_7 (8 9) routing sp4_h_l_36 sp4_v_b_7 (8 9) routing sp4_h_l_42 sp4_v_b_7 (8 9) routing sp4_h_r_7 sp4_v_b_7 (8 9) routing sp4_v_t_41 sp4_v_b_7 (9 0) routing sp4_h_l_47 sp4_h_r_1 (9 0) routing sp4_v_b_1 sp4_h_r_1 (9 0) routing sp4_v_b_7 sp4_h_r_1 (9 0) routing sp4_v_t_36 sp4_h_r_1 (9 1) routing sp4_h_l_36 sp4_v_b_1 (9 1) routing sp4_h_l_42 sp4_v_b_1 (9 1) routing sp4_v_t_36 sp4_v_b_1 (9 1) routing sp4_v_t_40 sp4_v_b_1 (9 10) routing sp4_h_r_4 sp4_h_l_42 (9 10) routing sp4_v_b_7 sp4_h_l_42 (9 10) routing sp4_v_t_36 sp4_h_l_42 (9 10) routing sp4_v_t_42 sp4_h_l_42 (9 11) routing sp4_h_r_1 sp4_v_t_42 (9 11) routing sp4_h_r_7 sp4_v_t_42 (9 11) routing sp4_v_b_11 sp4_v_t_42 (9 11) routing sp4_v_b_7 sp4_v_t_42 (9 12) routing sp4_h_l_42 sp4_h_r_10 (9 12) routing sp4_v_b_10 sp4_h_r_10 (9 12) routing sp4_v_b_4 sp4_h_r_10 (9 12) routing sp4_v_t_47 sp4_h_r_10 (9 13) routing sp4_h_l_41 sp4_v_b_10 (9 13) routing sp4_h_l_47 sp4_v_b_10 (9 13) routing sp4_v_t_39 sp4_v_b_10 (9 13) routing sp4_v_t_47 sp4_v_b_10 (9 14) routing sp4_h_r_7 sp4_h_l_47 (9 14) routing sp4_v_b_10 sp4_h_l_47 (9 14) routing sp4_v_t_41 sp4_h_l_47 (9 14) routing sp4_v_t_47 sp4_h_l_47 (9 15) routing sp4_h_r_10 sp4_v_t_47 (9 15) routing sp4_h_r_4 sp4_v_t_47 (9 15) routing sp4_v_b_10 sp4_v_t_47 (9 15) routing sp4_v_b_2 sp4_v_t_47 (9 2) routing sp4_h_r_10 sp4_h_l_36 (9 2) routing sp4_v_b_1 sp4_h_l_36 (9 2) routing sp4_v_t_36 sp4_h_l_36 (9 2) routing sp4_v_t_42 sp4_h_l_36 (9 3) routing sp4_h_r_1 sp4_v_t_36 (9 3) routing sp4_h_r_7 sp4_v_t_36 (9 3) routing sp4_v_b_1 sp4_v_t_36 (9 3) routing sp4_v_b_5 sp4_v_t_36 (9 4) routing sp4_h_l_36 sp4_h_r_4 (9 4) routing sp4_v_b_10 sp4_h_r_4 (9 4) routing sp4_v_b_4 sp4_h_r_4 (9 4) routing sp4_v_t_41 sp4_h_r_4 (9 5) routing sp4_h_l_41 sp4_v_b_4 (9 5) routing sp4_h_l_47 sp4_v_b_4 (9 5) routing sp4_v_t_41 sp4_v_b_4 (9 5) routing sp4_v_t_45 sp4_v_b_4 (9 6) routing sp4_h_r_1 sp4_h_l_41 (9 6) routing sp4_v_b_4 sp4_h_l_41 (9 6) routing sp4_v_t_41 sp4_h_l_41 (9 6) routing sp4_v_t_47 sp4_h_l_41 (9 7) routing sp4_h_r_10 sp4_v_t_41 (9 7) routing sp4_h_r_4 sp4_v_t_41 (9 7) routing sp4_v_b_4 sp4_v_t_41 (9 7) routing sp4_v_b_8 sp4_v_t_41 (9 8) routing sp4_h_l_41 sp4_h_r_7 (9 8) routing sp4_v_b_1 sp4_h_r_7 (9 8) routing sp4_v_b_7 sp4_h_r_7 (9 8) routing sp4_v_t_42 sp4_h_r_7 (9 9) routing sp4_h_l_36 sp4_v_b_7 (9 9) routing sp4_h_l_42 sp4_v_b_7 (9 9) routing sp4_v_t_42 sp4_v_b_7 (9 9) routing sp4_v_t_46 sp4_v_b_7 fpga-icestorm-0~20160913git266e758/icefuzz/cached_ramb.txt000066400000000000000000005565651276746530600230500ustar00rootroot00000000000000(0 0) Negative Clock bit (0 10) routing glb_netwk_2 glb2local_2 (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 (0 10) routing glb_netwk_7 glb2local_2 (0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 (0 11) routing glb_netwk_7 glb2local_2 (0 12) routing glb_netwk_2 glb2local_3 (0 12) routing glb_netwk_3 glb2local_3 (0 12) routing glb_netwk_6 glb2local_3 (0 12) routing glb_netwk_7 glb2local_3 (0 13) routing glb_netwk_1 glb2local_3 (0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 (0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/WE (0 14) routing glb_netwk_6 wire_bram/ram/WE (0 14) routing lc_trk_g2_4 wire_bram/ram/WE (0 14) routing lc_trk_g3_5 wire_bram/ram/WE (0 15) routing glb_netwk_2 wire_bram/ram/WE (0 15) routing glb_netwk_6 wire_bram/ram/WE (0 15) routing lc_trk_g1_5 wire_bram/ram/WE (0 15) routing lc_trk_g3_5 wire_bram/ram/WE (0 2) routing glb_netwk_2 wire_bram/ram/WCLK (0 2) routing glb_netwk_3 wire_bram/ram/WCLK (0 2) routing glb_netwk_6 wire_bram/ram/WCLK (0 2) routing glb_netwk_7 wire_bram/ram/WCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/WCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/WCLK (0 3) routing glb_netwk_1 wire_bram/ram/WCLK (0 3) routing glb_netwk_3 wire_bram/ram/WCLK (0 3) routing glb_netwk_5 wire_bram/ram/WCLK (0 3) routing glb_netwk_7 wire_bram/ram/WCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/WCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/WCLK (0 4) routing glb_netwk_5 wire_bram/ram/WCLKE (0 4) routing glb_netwk_7 wire_bram/ram/WCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/WCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/WCLKE (0 5) routing glb_netwk_3 wire_bram/ram/WCLKE (0 5) routing glb_netwk_7 wire_bram/ram/WCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE (0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 (0 6) routing glb_netwk_6 glb2local_0 (0 6) routing glb_netwk_7 glb2local_0 (0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 (0 7) routing glb_netwk_7 glb2local_0 (0 8) routing glb_netwk_2 glb2local_1 (0 8) routing glb_netwk_3 glb2local_1 (0 8) routing glb_netwk_6 glb2local_1 (0 8) routing glb_netwk_7 glb2local_1 (0 9) routing glb_netwk_1 glb2local_1 (0 9) routing glb_netwk_3 glb2local_1 (0 9) routing glb_netwk_5 glb2local_1 (0 9) routing glb_netwk_7 glb2local_1 (1 0) Column buffer control bit: MEMB_colbuf_cntl_0 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 (1 11) routing glb_netwk_7 glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 (1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 (1 13) routing glb_netwk_6 glb2local_3 (1 13) routing glb_netwk_7 glb2local_3 (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/WE (1 15) routing lc_trk_g0_4 wire_bram/ram/WE (1 15) routing lc_trk_g1_5 wire_bram/ram/WE (1 15) routing lc_trk_g2_4 wire_bram/ram/WE (1 15) routing lc_trk_g3_5 wire_bram/ram/WE (1 2) routing glb_netwk_4 wire_bram/ram/WCLK (1 2) routing glb_netwk_5 wire_bram/ram/WCLK (1 2) routing glb_netwk_6 wire_bram/ram/WCLK (1 2) routing glb_netwk_7 wire_bram/ram/WCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/WCLKE (1 5) routing lc_trk_g0_2 wire_bram/ram/WCLKE (1 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/WCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 (1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 (1 7) routing glb_netwk_6 glb2local_0 (1 7) routing glb_netwk_7 glb2local_0 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 (1 9) routing glb_netwk_4 glb2local_1 (1 9) routing glb_netwk_5 glb2local_1 (1 9) routing glb_netwk_6 glb2local_1 (1 9) routing glb_netwk_7 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 (10 0) routing sp4_v_t_45 sp4_h_r_1 (10 1) routing sp4_h_l_42 sp4_v_b_1 (10 1) routing sp4_h_r_8 sp4_v_b_1 (10 1) routing sp4_v_t_40 sp4_v_b_1 (10 1) routing sp4_v_t_47 sp4_v_b_1 (10 10) routing sp4_h_r_11 sp4_h_l_42 (10 10) routing sp4_h_r_4 sp4_h_l_42 (10 10) routing sp4_v_b_2 sp4_h_l_42 (10 10) routing sp4_v_t_36 sp4_h_l_42 (10 11) routing sp4_h_l_39 sp4_v_t_42 (10 11) routing sp4_h_r_1 sp4_v_t_42 (10 11) routing sp4_v_b_11 sp4_v_t_42 (10 11) routing sp4_v_b_4 sp4_v_t_42 (10 12) routing sp4_h_l_39 sp4_h_r_10 (10 12) routing sp4_h_l_42 sp4_h_r_10 (10 12) routing sp4_v_b_4 sp4_h_r_10 (10 12) routing sp4_v_t_40 sp4_h_r_10 (10 13) routing sp4_h_l_41 sp4_v_b_10 (10 13) routing sp4_h_r_5 sp4_v_b_10 (10 13) routing sp4_v_t_39 sp4_v_b_10 (10 13) routing sp4_v_t_42 sp4_v_b_10 (10 14) routing sp4_h_r_2 sp4_h_l_47 (10 14) routing sp4_h_r_7 sp4_h_l_47 (10 14) routing sp4_v_b_5 sp4_h_l_47 (10 14) routing sp4_v_t_41 sp4_h_l_47 (10 15) routing sp4_h_l_40 sp4_v_t_47 (10 15) routing sp4_h_r_4 sp4_v_t_47 (10 15) routing sp4_v_b_2 sp4_v_t_47 (10 15) routing sp4_v_b_7 sp4_v_t_47 (10 2) routing sp4_h_r_10 sp4_h_l_36 (10 2) routing sp4_h_r_5 sp4_h_l_36 (10 2) routing sp4_v_b_8 sp4_h_l_36 (10 2) routing sp4_v_t_42 sp4_h_l_36 (10 3) routing sp4_h_l_45 sp4_v_t_36 (10 3) routing sp4_h_r_7 sp4_v_t_36 (10 3) routing sp4_v_b_10 sp4_v_t_36 (10 3) routing sp4_v_b_5 sp4_v_t_36 (10 4) routing sp4_h_l_36 sp4_h_r_4 (10 4) routing sp4_h_l_45 sp4_h_r_4 (10 4) routing sp4_v_b_10 sp4_h_r_4 (10 4) routing sp4_v_t_46 sp4_h_r_4 (10 5) routing sp4_h_l_47 sp4_v_b_4 (10 5) routing sp4_h_r_11 sp4_v_b_4 (10 5) routing sp4_v_t_36 sp4_v_b_4 (10 5) routing sp4_v_t_45 sp4_v_b_4 (10 6) routing sp4_h_r_1 sp4_h_l_41 (10 6) routing sp4_h_r_8 sp4_h_l_41 (10 6) routing sp4_v_b_11 sp4_h_l_41 (10 6) routing sp4_v_t_47 sp4_h_l_41 (10 7) routing sp4_h_l_46 sp4_v_t_41 (10 7) routing sp4_h_r_10 sp4_v_t_41 (10 7) routing sp4_v_b_1 sp4_v_t_41 (10 7) routing sp4_v_b_8 sp4_v_t_41 (10 8) routing sp4_h_l_41 sp4_h_r_7 (10 8) routing sp4_h_l_46 sp4_h_r_7 (10 8) routing sp4_v_b_1 sp4_h_r_7 (10 8) routing sp4_v_t_39 sp4_h_r_7 (10 9) routing sp4_h_l_36 sp4_v_b_7 (10 9) routing sp4_h_r_2 sp4_v_b_7 (10 9) routing sp4_v_t_41 sp4_v_b_7 (10 9) routing sp4_v_t_46 sp4_v_b_7 (11 0) routing sp4_h_l_45 sp4_v_b_2 (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 (11 1) routing sp4_h_l_39 sp4_h_r_2 (11 1) routing sp4_h_l_43 sp4_h_r_2 (11 1) routing sp4_v_b_2 sp4_h_r_2 (11 1) routing sp4_v_b_8 sp4_h_r_2 (11 10) routing sp4_h_l_38 sp4_v_t_45 (11 10) routing sp4_h_r_2 sp4_v_t_45 (11 10) routing sp4_v_b_0 sp4_v_t_45 (11 10) routing sp4_v_b_5 sp4_v_t_45 (11 11) routing sp4_h_r_0 sp4_h_l_45 (11 11) routing sp4_h_r_8 sp4_h_l_45 (11 11) routing sp4_v_t_39 sp4_h_l_45 (11 11) routing sp4_v_t_45 sp4_h_l_45 (11 12) routing sp4_h_l_40 sp4_v_b_11 (11 12) routing sp4_h_r_6 sp4_v_b_11 (11 12) routing sp4_v_t_38 sp4_v_b_11 (11 12) routing sp4_v_t_45 sp4_v_b_11 (11 13) routing sp4_h_l_38 sp4_h_r_11 (11 13) routing sp4_h_l_46 sp4_h_r_11 (11 13) routing sp4_v_b_11 sp4_h_r_11 (11 13) routing sp4_v_b_5 sp4_h_r_11 (11 14) routing sp4_h_l_43 sp4_v_t_46 (11 14) routing sp4_h_r_5 sp4_v_t_46 (11 14) routing sp4_v_b_3 sp4_v_t_46 (11 14) routing sp4_v_b_8 sp4_v_t_46 (11 15) routing sp4_h_r_11 sp4_h_l_46 (11 15) routing sp4_h_r_3 sp4_h_l_46 (11 15) routing sp4_v_t_40 sp4_h_l_46 (11 15) routing sp4_v_t_46 sp4_h_l_46 (11 2) routing sp4_h_l_44 sp4_v_t_39 (11 2) routing sp4_h_r_8 sp4_v_t_39 (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 (11 3) routing sp4_h_r_2 sp4_h_l_39 (11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 (11 4) routing sp4_h_r_0 sp4_v_b_5 (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 (11 5) routing sp4_h_l_40 sp4_h_r_5 (11 5) routing sp4_h_l_44 sp4_h_r_5 (11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 (11 6) routing sp4_h_r_11 sp4_v_t_40 (11 6) routing sp4_v_b_2 sp4_v_t_40 (11 6) routing sp4_v_b_9 sp4_v_t_40 (11 7) routing sp4_h_r_5 sp4_h_l_40 (11 7) routing sp4_h_r_9 sp4_h_l_40 (11 7) routing sp4_v_t_40 sp4_h_l_40 (11 7) routing sp4_v_t_46 sp4_h_l_40 (11 8) routing sp4_h_l_39 sp4_v_b_8 (11 8) routing sp4_h_r_3 sp4_v_b_8 (11 8) routing sp4_v_t_37 sp4_v_b_8 (11 8) routing sp4_v_t_40 sp4_v_b_8 (11 9) routing sp4_h_l_37 sp4_h_r_8 (11 9) routing sp4_h_l_45 sp4_h_r_8 (11 9) routing sp4_v_b_2 sp4_h_r_8 (11 9) routing sp4_v_b_8 sp4_h_r_8 (12 0) routing sp4_h_l_46 sp4_h_r_2 (12 0) routing sp4_v_b_2 sp4_h_r_2 (12 0) routing sp4_v_b_8 sp4_h_r_2 (12 0) routing sp4_v_t_39 sp4_h_r_2 (12 1) routing sp4_h_l_39 sp4_v_b_2 (12 1) routing sp4_h_l_45 sp4_v_b_2 (12 1) routing sp4_h_r_2 sp4_v_b_2 (12 1) routing sp4_v_t_46 sp4_v_b_2 (12 10) routing sp4_h_r_5 sp4_h_l_45 (12 10) routing sp4_v_b_8 sp4_h_l_45 (12 10) routing sp4_v_t_39 sp4_h_l_45 (12 10) routing sp4_v_t_45 sp4_h_l_45 (12 11) routing sp4_h_l_45 sp4_v_t_45 (12 11) routing sp4_h_r_2 sp4_v_t_45 (12 11) routing sp4_h_r_8 sp4_v_t_45 (12 11) routing sp4_v_b_5 sp4_v_t_45 (12 12) routing sp4_h_l_45 sp4_h_r_11 (12 12) routing sp4_v_b_11 sp4_h_r_11 (12 12) routing sp4_v_b_5 sp4_h_r_11 (12 12) routing sp4_v_t_46 sp4_h_r_11 (12 13) routing sp4_h_l_40 sp4_v_b_11 (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 (12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 (12 14) routing sp4_v_t_46 sp4_h_l_46 (12 15) routing sp4_h_l_46 sp4_v_t_46 (12 15) routing sp4_h_r_11 sp4_v_t_46 (12 15) routing sp4_h_r_5 sp4_v_t_46 (12 15) routing sp4_v_b_8 sp4_v_t_46 (12 2) routing sp4_h_r_11 sp4_h_l_39 (12 2) routing sp4_v_b_2 sp4_h_l_39 (12 2) routing sp4_v_t_39 sp4_h_l_39 (12 2) routing sp4_v_t_45 sp4_h_l_39 (12 3) routing sp4_h_l_39 sp4_v_t_39 (12 3) routing sp4_h_r_2 sp4_v_t_39 (12 3) routing sp4_h_r_8 sp4_v_t_39 (12 3) routing sp4_v_b_11 sp4_v_t_39 (12 4) routing sp4_h_l_39 sp4_h_r_5 (12 4) routing sp4_v_b_11 sp4_h_r_5 (12 4) routing sp4_v_b_5 sp4_h_r_5 (12 4) routing sp4_v_t_40 sp4_h_r_5 (12 5) routing sp4_h_l_40 sp4_v_b_5 (12 5) routing sp4_h_l_46 sp4_v_b_5 (12 5) routing sp4_h_r_5 sp4_v_b_5 (12 5) routing sp4_v_t_39 sp4_v_b_5 (12 6) routing sp4_h_r_2 sp4_h_l_40 (12 6) routing sp4_v_b_5 sp4_h_l_40 (12 6) routing sp4_v_t_40 sp4_h_l_40 (12 6) routing sp4_v_t_46 sp4_h_l_40 (12 7) routing sp4_h_l_40 sp4_v_t_40 (12 7) routing sp4_h_r_11 sp4_v_t_40 (12 7) routing sp4_h_r_5 sp4_v_t_40 (12 7) routing sp4_v_b_2 sp4_v_t_40 (12 8) routing sp4_h_l_40 sp4_h_r_8 (12 8) routing sp4_v_b_2 sp4_h_r_8 (12 8) routing sp4_v_b_8 sp4_h_r_8 (12 8) routing sp4_v_t_45 sp4_h_r_8 (12 9) routing sp4_h_l_39 sp4_v_b_8 (12 9) routing sp4_h_l_45 sp4_v_b_8 (12 9) routing sp4_h_r_8 sp4_v_b_8 (12 9) routing sp4_v_t_40 sp4_v_b_8 (13 0) routing sp4_h_l_39 sp4_v_b_2 (13 0) routing sp4_h_l_45 sp4_v_b_2 (13 0) routing sp4_v_t_39 sp4_v_b_2 (13 0) routing sp4_v_t_43 sp4_v_b_2 (13 1) routing sp4_h_l_43 sp4_h_r_2 (13 1) routing sp4_h_l_46 sp4_h_r_2 (13 1) routing sp4_v_b_8 sp4_h_r_2 (13 1) routing sp4_v_t_44 sp4_h_r_2 (13 10) routing sp4_h_r_2 sp4_v_t_45 (13 10) routing sp4_h_r_8 sp4_v_t_45 (13 10) routing sp4_v_b_0 sp4_v_t_45 (13 10) routing sp4_v_b_8 sp4_v_t_45 (13 11) routing sp4_h_r_0 sp4_h_l_45 (13 11) routing sp4_h_r_5 sp4_h_l_45 (13 11) routing sp4_v_b_3 sp4_h_l_45 (13 11) routing sp4_v_t_39 sp4_h_l_45 (13 12) routing sp4_h_l_40 sp4_v_b_11 (13 12) routing sp4_h_l_46 sp4_v_b_11 (13 12) routing sp4_v_t_38 sp4_v_b_11 (13 12) routing sp4_v_t_46 sp4_v_b_11 (13 13) routing sp4_h_l_38 sp4_h_r_11 (13 13) routing sp4_h_l_45 sp4_h_r_11 (13 13) routing sp4_v_b_5 sp4_h_r_11 (13 13) routing sp4_v_t_43 sp4_h_r_11 (13 14) routing sp4_h_r_11 sp4_v_t_46 (13 14) routing sp4_h_r_5 sp4_v_t_46 (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 (13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 (13 2) routing sp4_h_r_8 sp4_v_t_39 (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 (13 3) routing sp4_h_r_11 sp4_h_l_39 (13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 (13 4) routing sp4_h_l_46 sp4_v_b_5 (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 (13 5) routing sp4_h_l_39 sp4_h_r_5 (13 5) routing sp4_h_l_44 sp4_h_r_5 (13 5) routing sp4_v_b_11 sp4_h_r_5 (13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 (13 6) routing sp4_h_r_5 sp4_v_t_40 (13 6) routing sp4_v_b_5 sp4_v_t_40 (13 6) routing sp4_v_b_9 sp4_v_t_40 (13 7) routing sp4_h_r_2 sp4_h_l_40 (13 7) routing sp4_h_r_9 sp4_h_l_40 (13 7) routing sp4_v_b_0 sp4_h_l_40 (13 7) routing sp4_v_t_46 sp4_h_l_40 (13 8) routing sp4_h_l_39 sp4_v_b_8 (13 8) routing sp4_h_l_45 sp4_v_b_8 (13 8) routing sp4_v_t_37 sp4_v_b_8 (13 8) routing sp4_v_t_45 sp4_v_b_8 (13 9) routing sp4_h_l_37 sp4_h_r_8 (13 9) routing sp4_h_l_40 sp4_h_r_8 (13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 (14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_r_16 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 (14 1) routing sp12_h_l_15 lc_trk_g0_0 (14 1) routing sp12_h_r_0 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_h_r_16 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 (14 10) routing rgt_op_4 lc_trk_g2_4 (14 10) routing sp12_v_b_4 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 (14 10) routing sp4_v_b_28 lc_trk_g2_4 (14 10) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing bnl_op_4 lc_trk_g2_4 (14 11) routing sp12_v_b_20 lc_trk_g2_4 (14 11) routing sp12_v_b_4 lc_trk_g2_4 (14 11) routing sp4_h_r_28 lc_trk_g2_4 (14 11) routing sp4_h_r_44 lc_trk_g2_4 (14 11) routing sp4_r_v_b_36 lc_trk_g2_4 (14 11) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing tnl_op_4 lc_trk_g2_4 (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 (14 12) routing sp12_v_b_0 lc_trk_g3_0 (14 12) routing sp4_h_r_32 lc_trk_g3_0 (14 12) routing sp4_h_r_40 lc_trk_g3_0 (14 12) routing sp4_v_b_32 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 (14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 (14 13) routing sp4_h_r_24 lc_trk_g3_0 (14 13) routing sp4_h_r_40 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_b_32 lc_trk_g3_0 (14 13) routing tnl_op_0 lc_trk_g3_0 (14 14) routing bnl_op_4 lc_trk_g3_4 (14 14) routing rgt_op_4 lc_trk_g3_4 (14 14) routing sp12_v_b_4 lc_trk_g3_4 (14 14) routing sp4_h_r_36 lc_trk_g3_4 (14 14) routing sp4_h_r_44 lc_trk_g3_4 (14 14) routing sp4_v_b_28 lc_trk_g3_4 (14 14) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing bnl_op_4 lc_trk_g3_4 (14 15) routing sp12_v_b_20 lc_trk_g3_4 (14 15) routing sp12_v_b_4 lc_trk_g3_4 (14 15) routing sp4_h_r_28 lc_trk_g3_4 (14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing tnl_op_4 lc_trk_g3_4 (14 2) routing bnr_op_4 lc_trk_g0_4 (14 2) routing lft_op_4 lc_trk_g0_4 (14 2) routing sp12_h_l_3 lc_trk_g0_4 (14 2) routing sp4_h_l_1 lc_trk_g0_4 (14 2) routing sp4_h_l_9 lc_trk_g0_4 (14 2) routing sp4_v_b_12 lc_trk_g0_4 (14 2) routing sp4_v_b_4 lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 (14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_l_9 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 (14 3) routing sp4_v_b_12 lc_trk_g0_4 (14 4) routing bnr_op_0 lc_trk_g1_0 (14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_r_16 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 (14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_l_15 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_h_r_16 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 (14 6) routing bnr_op_4 lc_trk_g1_4 (14 6) routing lft_op_4 lc_trk_g1_4 (14 6) routing sp12_h_l_3 lc_trk_g1_4 (14 6) routing sp4_h_l_1 lc_trk_g1_4 (14 6) routing sp4_h_l_9 lc_trk_g1_4 (14 6) routing sp4_v_b_12 lc_trk_g1_4 (14 6) routing sp4_v_b_4 lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_l_9 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_b_12 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 (14 8) routing rgt_op_0 lc_trk_g2_0 (14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_r_32 lc_trk_g2_0 (14 8) routing sp4_h_r_40 lc_trk_g2_0 (14 8) routing sp4_v_b_32 lc_trk_g2_0 (14 8) routing sp4_v_t_13 lc_trk_g2_0 (14 9) routing bnl_op_0 lc_trk_g2_0 (14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 (14 9) routing sp4_h_r_24 lc_trk_g2_0 (14 9) routing sp4_h_r_40 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_b_32 lc_trk_g2_0 (14 9) routing tnl_op_0 lc_trk_g2_0 (15 0) routing lft_op_1 lc_trk_g0_1 (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_t_4 lc_trk_g0_1 (15 1) routing bot_op_0 lc_trk_g0_0 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_16 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 (15 1) routing sp4_v_b_16 lc_trk_g0_0 (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 (15 10) routing sp4_h_r_29 lc_trk_g2_5 (15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_b_4 lc_trk_g2_4 (15 11) routing sp4_h_r_28 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 (15 11) routing sp4_h_r_44 lc_trk_g2_4 (15 11) routing sp4_v_b_44 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 (15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_h_r_33 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 (15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 (15 13) routing sp4_h_r_24 lc_trk_g3_0 (15 13) routing sp4_h_r_32 lc_trk_g3_0 (15 13) routing sp4_h_r_40 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 (15 13) routing tnr_op_0 lc_trk_g3_0 (15 14) routing rgt_op_5 lc_trk_g3_5 (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_r_29 lc_trk_g3_5 (15 14) routing sp4_h_r_37 lc_trk_g3_5 (15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_b_45 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 (15 15) routing sp12_v_b_4 lc_trk_g3_4 (15 15) routing sp4_h_r_28 lc_trk_g3_4 (15 15) routing sp4_h_r_36 lc_trk_g3_4 (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_b_44 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 (15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing lft_op_5 lc_trk_g0_5 (15 2) routing sp12_h_l_2 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_21 lc_trk_g0_5 (15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 (15 3) routing bot_op_4 lc_trk_g0_4 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_l_1 lc_trk_g0_4 (15 3) routing sp4_h_l_9 lc_trk_g0_4 (15 3) routing sp4_h_r_4 lc_trk_g0_4 (15 3) routing sp4_v_b_20 lc_trk_g0_4 (15 4) routing lft_op_1 lc_trk_g1_1 (15 4) routing sp12_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_17 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_t_4 lc_trk_g1_1 (15 5) routing bot_op_0 lc_trk_g1_0 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_16 lc_trk_g1_0 (15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_b_16 lc_trk_g1_0 (15 6) routing lft_op_5 lc_trk_g1_5 (15 6) routing sp12_h_l_2 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_21 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 (15 7) routing bot_op_4 lc_trk_g1_4 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_l_1 lc_trk_g1_4 (15 7) routing sp4_h_l_9 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_h_r_33 lc_trk_g2_1 (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_r_24 lc_trk_g2_0 (15 9) routing sp4_h_r_32 lc_trk_g2_0 (15 9) routing sp4_h_r_40 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 (16 0) routing sp12_h_l_14 lc_trk_g0_1 (16 0) routing sp12_h_r_9 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 (16 0) routing sp4_v_t_4 lc_trk_g0_1 (16 1) routing sp12_h_l_15 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 (16 1) routing sp4_h_r_16 lc_trk_g0_0 (16 1) routing sp4_h_r_8 lc_trk_g0_0 (16 1) routing sp4_v_b_0 lc_trk_g0_0 (16 1) routing sp4_v_b_16 lc_trk_g0_0 (16 1) routing sp4_v_b_8 lc_trk_g0_0 (16 10) routing sp12_v_b_13 lc_trk_g2_5 (16 10) routing sp12_v_t_18 lc_trk_g2_5 (16 10) routing sp4_h_r_29 lc_trk_g2_5 (16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 (16 10) routing sp4_v_b_45 lc_trk_g2_5 (16 10) routing sp4_v_t_24 lc_trk_g2_5 (16 11) routing sp12_v_b_20 lc_trk_g2_4 (16 11) routing sp12_v_t_11 lc_trk_g2_4 (16 11) routing sp4_h_r_28 lc_trk_g2_4 (16 11) routing sp4_h_r_36 lc_trk_g2_4 (16 11) routing sp4_h_r_44 lc_trk_g2_4 (16 11) routing sp4_v_b_28 lc_trk_g2_4 (16 11) routing sp4_v_b_44 lc_trk_g2_4 (16 11) routing sp4_v_t_25 lc_trk_g2_4 (16 12) routing sp12_v_b_9 lc_trk_g3_1 (16 12) routing sp12_v_t_14 lc_trk_g3_1 (16 12) routing sp4_h_l_28 lc_trk_g3_1 (16 12) routing sp4_h_r_25 lc_trk_g3_1 (16 12) routing sp4_h_r_33 lc_trk_g3_1 (16 12) routing sp4_v_b_25 lc_trk_g3_1 (16 12) routing sp4_v_b_41 lc_trk_g3_1 (16 12) routing sp4_v_t_20 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 (16 13) routing sp4_h_r_24 lc_trk_g3_0 (16 13) routing sp4_h_r_32 lc_trk_g3_0 (16 13) routing sp4_h_r_40 lc_trk_g3_0 (16 13) routing sp4_v_b_32 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 (16 13) routing sp4_v_t_13 lc_trk_g3_0 (16 14) routing sp12_v_b_13 lc_trk_g3_5 (16 14) routing sp12_v_t_18 lc_trk_g3_5 (16 14) routing sp4_h_r_29 lc_trk_g3_5 (16 14) routing sp4_h_r_37 lc_trk_g3_5 (16 14) routing sp4_h_r_45 lc_trk_g3_5 (16 14) routing sp4_v_b_29 lc_trk_g3_5 (16 14) routing sp4_v_b_45 lc_trk_g3_5 (16 14) routing sp4_v_t_24 lc_trk_g3_5 (16 15) routing sp12_v_b_20 lc_trk_g3_4 (16 15) routing sp12_v_t_11 lc_trk_g3_4 (16 15) routing sp4_h_r_28 lc_trk_g3_4 (16 15) routing sp4_h_r_36 lc_trk_g3_4 (16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_b_44 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 2) routing sp12_h_l_10 lc_trk_g0_5 (16 2) routing sp12_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_5 lc_trk_g0_5 (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 (16 3) routing sp12_h_r_12 lc_trk_g0_4 (16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_l_1 lc_trk_g0_4 (16 3) routing sp4_h_l_9 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 (16 3) routing sp4_v_b_12 lc_trk_g0_4 (16 3) routing sp4_v_b_20 lc_trk_g0_4 (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 4) routing sp12_h_l_14 lc_trk_g1_1 (16 4) routing sp12_h_r_9 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 4) routing sp4_v_t_4 lc_trk_g1_1 (16 5) routing sp12_h_l_15 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_16 lc_trk_g1_0 (16 5) routing sp4_h_r_8 lc_trk_g1_0 (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 (16 6) routing sp12_h_l_10 lc_trk_g1_5 (16 6) routing sp12_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 (16 6) routing sp4_v_b_13 lc_trk_g1_5 (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 6) routing sp4_v_t_8 lc_trk_g1_5 (16 7) routing sp12_h_r_12 lc_trk_g1_4 (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_l_1 lc_trk_g1_4 (16 7) routing sp4_h_l_9 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_12 lc_trk_g1_4 (16 7) routing sp4_v_b_20 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 (16 8) routing sp12_v_b_9 lc_trk_g2_1 (16 8) routing sp12_v_t_14 lc_trk_g2_1 (16 8) routing sp4_h_l_28 lc_trk_g2_1 (16 8) routing sp4_h_r_25 lc_trk_g2_1 (16 8) routing sp4_h_r_33 lc_trk_g2_1 (16 8) routing sp4_v_b_25 lc_trk_g2_1 (16 8) routing sp4_v_b_41 lc_trk_g2_1 (16 8) routing sp4_v_t_20 lc_trk_g2_1 (16 9) routing sp12_v_b_16 lc_trk_g2_0 (16 9) routing sp12_v_t_7 lc_trk_g2_0 (16 9) routing sp4_h_r_24 lc_trk_g2_0 (16 9) routing sp4_h_r_32 lc_trk_g2_0 (16 9) routing sp4_h_r_40 lc_trk_g2_0 (16 9) routing sp4_v_b_32 lc_trk_g2_0 (16 9) routing sp4_v_b_40 lc_trk_g2_0 (16 9) routing sp4_v_t_13 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 (17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_r_17 lc_trk_g0_1 (18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_l_14 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 (18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_b_5 lc_trk_g2_5 (18 10) routing sp4_h_r_37 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_29 lc_trk_g2_5 (18 10) routing sp4_v_t_24 lc_trk_g2_5 (18 11) routing bnl_op_5 lc_trk_g2_5 (18 11) routing sp12_v_b_5 lc_trk_g2_5 (18 11) routing sp12_v_t_18 lc_trk_g2_5 (18 11) routing sp4_h_r_29 lc_trk_g2_5 (18 11) routing sp4_h_r_45 lc_trk_g2_5 (18 11) routing sp4_r_v_b_37 lc_trk_g2_5 (18 11) routing sp4_v_t_24 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 (18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 (18 12) routing sp4_h_l_28 lc_trk_g3_1 (18 12) routing sp4_h_r_33 lc_trk_g3_1 (18 12) routing sp4_v_b_25 lc_trk_g3_1 (18 12) routing sp4_v_t_20 lc_trk_g3_1 (18 13) routing bnl_op_1 lc_trk_g3_1 (18 13) routing sp12_v_b_1 lc_trk_g3_1 (18 13) routing sp12_v_t_14 lc_trk_g3_1 (18 13) routing sp4_h_l_28 lc_trk_g3_1 (18 13) routing sp4_h_r_25 lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 lc_trk_g3_1 (18 13) routing sp4_v_t_20 lc_trk_g3_1 (18 13) routing tnl_op_1 lc_trk_g3_1 (18 14) routing bnl_op_5 lc_trk_g3_5 (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 (18 14) routing sp4_h_r_37 lc_trk_g3_5 (18 14) routing sp4_h_r_45 lc_trk_g3_5 (18 14) routing sp4_v_b_29 lc_trk_g3_5 (18 14) routing sp4_v_t_24 lc_trk_g3_5 (18 15) routing bnl_op_5 lc_trk_g3_5 (18 15) routing sp12_v_b_5 lc_trk_g3_5 (18 15) routing sp12_v_t_18 lc_trk_g3_5 (18 15) routing sp4_h_r_29 lc_trk_g3_5 (18 15) routing sp4_h_r_45 lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 lc_trk_g3_5 (18 15) routing sp4_v_t_24 lc_trk_g3_5 (18 15) routing tnl_op_5 lc_trk_g3_5 (18 2) routing bnr_op_5 lc_trk_g0_5 (18 2) routing lft_op_5 lc_trk_g0_5 (18 2) routing sp12_h_l_2 lc_trk_g0_5 (18 2) routing sp4_h_r_13 lc_trk_g0_5 (18 2) routing sp4_h_r_21 lc_trk_g0_5 (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 (18 3) routing sp12_h_l_2 lc_trk_g0_5 (18 3) routing sp12_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 (18 3) routing sp4_v_b_13 lc_trk_g0_5 (18 4) routing bnr_op_1 lc_trk_g1_1 (18 4) routing lft_op_1 lc_trk_g1_1 (18 4) routing sp12_h_r_1 lc_trk_g1_1 (18 4) routing sp4_h_r_17 lc_trk_g1_1 (18 4) routing sp4_h_r_9 lc_trk_g1_1 (18 4) routing sp4_v_b_1 lc_trk_g1_1 (18 4) routing sp4_v_b_9 lc_trk_g1_1 (18 5) routing bnr_op_1 lc_trk_g1_1 (18 5) routing sp12_h_l_14 lc_trk_g1_1 (18 5) routing sp12_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_r_17 lc_trk_g1_1 (18 5) routing sp4_r_v_b_25 lc_trk_g1_1 (18 5) routing sp4_v_b_9 lc_trk_g1_1 (18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 (18 6) routing sp12_h_l_2 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_h_r_21 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 (18 7) routing sp12_h_l_2 lc_trk_g1_5 (18 7) routing sp12_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 (18 8) routing sp4_h_r_33 lc_trk_g2_1 (18 8) routing sp4_v_b_25 lc_trk_g2_1 (18 8) routing sp4_v_t_20 lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 (18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_t_14 lc_trk_g2_1 (18 9) routing sp4_h_l_28 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 (18 9) routing sp4_r_v_b_33 lc_trk_g2_1 (18 9) routing sp4_v_t_20 lc_trk_g2_1 (18 9) routing tnl_op_1 lc_trk_g2_1 (19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13 (19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 (19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_b_23 (19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11 (19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13 (19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1 (19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 (19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 (19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 (19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 (19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 (19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 (19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 (19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7 (19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 (19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 (2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 (2 1) Column buffer control bit: MEMB_colbuf_cntl_1 (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 (2 11) Column buffer control bit: MEMB_colbuf_cntl_5 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 (2 13) Column buffer control bit: MEMB_colbuf_cntl_6 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 (2 15) Column buffer control bit: MEMB_colbuf_cntl_7 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/WCLK (2 3) routing lc_trk_g0_0 wire_bram/ram/WCLK (2 3) routing lc_trk_g1_1 wire_bram/ram/WCLK (2 3) routing lc_trk_g2_0 wire_bram/ram/WCLK (2 3) routing lc_trk_g3_1 wire_bram/ram/WCLK (2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_r_18 (2 5) Column buffer control bit: MEMB_colbuf_cntl_2 (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6 (2 7) Column buffer control bit: MEMB_colbuf_cntl_3 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9 (2 9) Column buffer control bit: MEMB_colbuf_cntl_4 (21 0) routing bnr_op_3 lc_trk_g0_3 (21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_r_3 lc_trk_g0_3 (21 0) routing sp4_h_l_6 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 (21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp12_h_r_3 lc_trk_g0_3 (21 1) routing sp4_h_l_6 lc_trk_g0_3 (21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 (21 1) routing sp4_v_b_11 lc_trk_g0_3 (21 10) routing bnl_op_7 lc_trk_g2_7 (21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_t_4 lc_trk_g2_7 (21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_b_31 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing bnl_op_7 lc_trk_g2_7 (21 11) routing sp12_v_t_20 lc_trk_g2_7 (21 11) routing sp12_v_t_4 lc_trk_g2_7 (21 11) routing sp4_h_r_31 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_b_3 lc_trk_g3_3 (21 12) routing sp4_h_l_22 lc_trk_g3_3 (21 12) routing sp4_h_r_43 lc_trk_g3_3 (21 12) routing sp4_v_b_27 lc_trk_g3_3 (21 12) routing sp4_v_b_35 lc_trk_g3_3 (21 13) routing bnl_op_3 lc_trk_g3_3 (21 13) routing sp12_v_b_19 lc_trk_g3_3 (21 13) routing sp12_v_b_3 lc_trk_g3_3 (21 13) routing sp4_h_l_14 lc_trk_g3_3 (21 13) routing sp4_h_r_43 lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 lc_trk_g3_3 (21 13) routing sp4_v_b_35 lc_trk_g3_3 (21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_t_4 lc_trk_g3_7 (21 14) routing sp4_h_l_26 lc_trk_g3_7 (21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_b_31 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_t_20 lc_trk_g3_7 (21 15) routing sp12_v_t_4 lc_trk_g3_7 (21 15) routing sp4_h_r_31 lc_trk_g3_7 (21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 (21 2) routing sp12_h_r_7 lc_trk_g0_7 (21 2) routing sp4_h_r_15 lc_trk_g0_7 (21 2) routing sp4_h_r_23 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_20 lc_trk_g0_7 (21 3) routing sp12_h_r_7 lc_trk_g0_7 (21 3) routing sp4_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 (21 3) routing sp4_v_t_2 lc_trk_g0_7 (21 4) routing bnr_op_3 lc_trk_g1_3 (21 4) routing lft_op_3 lc_trk_g1_3 (21 4) routing sp12_h_r_3 lc_trk_g1_3 (21 4) routing sp4_h_l_6 lc_trk_g1_3 (21 4) routing sp4_h_r_11 lc_trk_g1_3 (21 4) routing sp4_v_b_11 lc_trk_g1_3 (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp12_h_r_3 lc_trk_g1_3 (21 5) routing sp4_h_l_6 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 (21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_r_7 lc_trk_g1_7 (21 6) routing sp4_h_r_15 lc_trk_g1_7 (21 6) routing sp4_h_r_23 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 (21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_20 lc_trk_g1_7 (21 7) routing sp12_h_r_7 lc_trk_g1_7 (21 7) routing sp4_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_b_3 lc_trk_g2_3 (21 8) routing sp4_h_l_22 lc_trk_g2_3 (21 8) routing sp4_h_r_43 lc_trk_g2_3 (21 8) routing sp4_v_b_27 lc_trk_g2_3 (21 8) routing sp4_v_b_35 lc_trk_g2_3 (21 9) routing bnl_op_3 lc_trk_g2_3 (21 9) routing sp12_v_b_19 lc_trk_g2_3 (21 9) routing sp12_v_b_3 lc_trk_g2_3 (21 9) routing sp4_h_l_14 lc_trk_g2_3 (21 9) routing sp4_h_r_43 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_b_35 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 (22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_34 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => bot_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 (22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 lc_trk_g0_3 (23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_l_6 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 (23 0) routing sp4_v_t_6 lc_trk_g0_3 (23 1) routing sp12_h_l_17 lc_trk_g0_2 (23 1) routing sp12_h_l_9 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 (23 1) routing sp4_v_b_10 lc_trk_g0_2 (23 1) routing sp4_v_b_2 lc_trk_g0_2 (23 1) routing sp4_v_t_7 lc_trk_g0_2 (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp12_v_t_20 lc_trk_g2_7 (23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_31 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_31 lc_trk_g2_7 (23 10) routing sp4_v_t_26 lc_trk_g2_7 (23 10) routing sp4_v_t_34 lc_trk_g2_7 (23 11) routing sp12_v_b_14 lc_trk_g2_6 (23 11) routing sp12_v_b_22 lc_trk_g2_6 (23 11) routing sp4_h_l_19 lc_trk_g2_6 (23 11) routing sp4_h_l_27 lc_trk_g2_6 (23 11) routing sp4_h_r_46 lc_trk_g2_6 (23 11) routing sp4_v_b_46 lc_trk_g2_6 (23 11) routing sp4_v_t_19 lc_trk_g2_6 (23 11) routing sp4_v_t_27 lc_trk_g2_6 (23 12) routing sp12_v_b_19 lc_trk_g3_3 (23 12) routing sp12_v_t_8 lc_trk_g3_3 (23 12) routing sp4_h_l_14 lc_trk_g3_3 (23 12) routing sp4_h_l_22 lc_trk_g3_3 (23 12) routing sp4_h_r_43 lc_trk_g3_3 (23 12) routing sp4_v_b_27 lc_trk_g3_3 (23 12) routing sp4_v_b_35 lc_trk_g3_3 (23 12) routing sp4_v_b_43 lc_trk_g3_3 (23 13) routing sp12_v_b_10 lc_trk_g3_2 (23 13) routing sp12_v_b_18 lc_trk_g3_2 (23 13) routing sp4_h_l_15 lc_trk_g3_2 (23 13) routing sp4_h_r_34 lc_trk_g3_2 (23 13) routing sp4_h_r_42 lc_trk_g3_2 (23 13) routing sp4_v_b_34 lc_trk_g3_2 (23 13) routing sp4_v_t_15 lc_trk_g3_2 (23 13) routing sp4_v_t_31 lc_trk_g3_2 (23 14) routing sp12_v_t_12 lc_trk_g3_7 (23 14) routing sp12_v_t_20 lc_trk_g3_7 (23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_31 lc_trk_g3_7 (23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_31 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 14) routing sp4_v_t_34 lc_trk_g3_7 (23 15) routing sp12_v_b_14 lc_trk_g3_6 (23 15) routing sp12_v_b_22 lc_trk_g3_6 (23 15) routing sp4_h_l_19 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 (23 15) routing sp4_v_t_19 lc_trk_g3_6 (23 15) routing sp4_v_t_27 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 (23 2) routing sp12_h_l_20 lc_trk_g0_7 (23 2) routing sp4_h_r_15 lc_trk_g0_7 (23 2) routing sp4_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_23 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 (23 3) routing sp12_h_r_14 lc_trk_g0_6 (23 3) routing sp12_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_l_11 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 (23 3) routing sp4_h_r_6 lc_trk_g0_6 (23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 (23 3) routing sp4_v_t_11 lc_trk_g0_6 (23 4) routing sp12_h_l_16 lc_trk_g1_3 (23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_l_6 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 (23 4) routing sp4_v_b_11 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 4) routing sp4_v_t_6 lc_trk_g1_3 (23 5) routing sp12_h_l_17 lc_trk_g1_2 (23 5) routing sp12_h_l_9 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 (23 5) routing sp4_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 (23 6) routing sp12_h_l_12 lc_trk_g1_7 (23 6) routing sp12_h_l_20 lc_trk_g1_7 (23 6) routing sp4_h_r_15 lc_trk_g1_7 (23 6) routing sp4_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 (23 6) routing sp4_v_b_23 lc_trk_g1_7 (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 (23 7) routing sp12_h_r_14 lc_trk_g1_6 (23 7) routing sp12_h_r_22 lc_trk_g1_6 (23 7) routing sp4_h_l_11 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_14 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 7) routing sp4_v_t_11 lc_trk_g1_6 (23 8) routing sp12_v_b_19 lc_trk_g2_3 (23 8) routing sp12_v_t_8 lc_trk_g2_3 (23 8) routing sp4_h_l_14 lc_trk_g2_3 (23 8) routing sp4_h_l_22 lc_trk_g2_3 (23 8) routing sp4_h_r_43 lc_trk_g2_3 (23 8) routing sp4_v_b_27 lc_trk_g2_3 (23 8) routing sp4_v_b_35 lc_trk_g2_3 (23 8) routing sp4_v_b_43 lc_trk_g2_3 (23 9) routing sp12_v_b_10 lc_trk_g2_2 (23 9) routing sp12_v_b_18 lc_trk_g2_2 (23 9) routing sp4_h_l_15 lc_trk_g2_2 (23 9) routing sp4_h_r_34 lc_trk_g2_2 (23 9) routing sp4_h_r_42 lc_trk_g2_2 (23 9) routing sp4_v_b_34 lc_trk_g2_2 (23 9) routing sp4_v_t_15 lc_trk_g2_2 (23 9) routing sp4_v_t_31 lc_trk_g2_2 (24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_r_3 lc_trk_g0_3 (24 0) routing sp4_h_l_6 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_t_6 lc_trk_g0_3 (24 1) routing bot_op_2 lc_trk_g0_2 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_l_1 lc_trk_g0_2 (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_18 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_t_7 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_t_4 lc_trk_g2_7 (24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_31 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_t_34 lc_trk_g2_7 (24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_t_5 lc_trk_g2_6 (24 11) routing sp4_h_l_19 lc_trk_g2_6 (24 11) routing sp4_h_l_27 lc_trk_g2_6 (24 11) routing sp4_h_r_46 lc_trk_g2_6 (24 11) routing sp4_v_b_46 lc_trk_g2_6 (24 11) routing tnl_op_6 lc_trk_g2_6 (24 11) routing tnr_op_6 lc_trk_g2_6 (24 12) routing rgt_op_3 lc_trk_g3_3 (24 12) routing sp12_v_b_3 lc_trk_g3_3 (24 12) routing sp4_h_l_14 lc_trk_g3_3 (24 12) routing sp4_h_l_22 lc_trk_g3_3 (24 12) routing sp4_h_r_43 lc_trk_g3_3 (24 12) routing sp4_v_b_43 lc_trk_g3_3 (24 12) routing tnl_op_3 lc_trk_g3_3 (24 12) routing tnr_op_3 lc_trk_g3_3 (24 13) routing rgt_op_2 lc_trk_g3_2 (24 13) routing sp12_v_t_1 lc_trk_g3_2 (24 13) routing sp4_h_l_15 lc_trk_g3_2 (24 13) routing sp4_h_r_34 lc_trk_g3_2 (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 (24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_t_4 lc_trk_g3_7 (24 14) routing sp4_h_l_26 lc_trk_g3_7 (24 14) routing sp4_h_r_31 lc_trk_g3_7 (24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_t_34 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 (24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_t_5 lc_trk_g3_6 (24 15) routing sp4_h_l_19 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 (24 2) routing sp12_h_r_7 lc_trk_g0_7 (24 2) routing sp4_h_r_15 lc_trk_g0_7 (24 2) routing sp4_h_r_23 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_b_23 lc_trk_g0_7 (24 3) routing bot_op_6 lc_trk_g0_6 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_11 lc_trk_g0_6 (24 3) routing sp4_h_l_3 lc_trk_g0_6 (24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_t_11 lc_trk_g0_6 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_r_3 lc_trk_g1_3 (24 4) routing sp4_h_l_6 lc_trk_g1_3 (24 4) routing sp4_h_r_11 lc_trk_g1_3 (24 4) routing sp4_h_r_3 lc_trk_g1_3 (24 4) routing sp4_v_t_6 lc_trk_g1_3 (24 5) routing bot_op_2 lc_trk_g1_2 (24 5) routing lft_op_2 lc_trk_g1_2 (24 5) routing sp12_h_l_1 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 (24 5) routing sp4_h_r_18 lc_trk_g1_2 (24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_t_7 lc_trk_g1_2 (24 6) routing lft_op_7 lc_trk_g1_7 (24 6) routing sp12_h_r_7 lc_trk_g1_7 (24 6) routing sp4_h_r_15 lc_trk_g1_7 (24 6) routing sp4_h_r_23 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 (24 6) routing sp4_v_b_23 lc_trk_g1_7 (24 7) routing bot_op_6 lc_trk_g1_6 (24 7) routing lft_op_6 lc_trk_g1_6 (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_11 lc_trk_g1_6 (24 7) routing sp4_h_l_3 lc_trk_g1_6 (24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_t_11 lc_trk_g1_6 (24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_b_3 lc_trk_g2_3 (24 8) routing sp4_h_l_14 lc_trk_g2_3 (24 8) routing sp4_h_l_22 lc_trk_g2_3 (24 8) routing sp4_h_r_43 lc_trk_g2_3 (24 8) routing sp4_v_b_43 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 (24 8) routing tnr_op_3 lc_trk_g2_3 (24 9) routing rgt_op_2 lc_trk_g2_2 (24 9) routing sp12_v_t_1 lc_trk_g2_2 (24 9) routing sp4_h_l_15 lc_trk_g2_2 (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_l_1 lc_trk_g0_2 (25 0) routing sp4_h_r_10 lc_trk_g0_2 (25 0) routing sp4_h_r_18 lc_trk_g0_2 (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 (25 1) routing bnr_op_2 lc_trk_g0_2 (25 1) routing sp12_h_l_1 lc_trk_g0_2 (25 1) routing sp12_h_l_17 lc_trk_g0_2 (25 1) routing sp4_h_r_18 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_t_5 lc_trk_g2_6 (25 10) routing sp4_h_l_27 lc_trk_g2_6 (25 10) routing sp4_h_r_46 lc_trk_g2_6 (25 10) routing sp4_v_t_19 lc_trk_g2_6 (25 10) routing sp4_v_t_27 lc_trk_g2_6 (25 11) routing bnl_op_6 lc_trk_g2_6 (25 11) routing sp12_v_b_22 lc_trk_g2_6 (25 11) routing sp12_v_t_5 lc_trk_g2_6 (25 11) routing sp4_h_l_19 lc_trk_g2_6 (25 11) routing sp4_h_r_46 lc_trk_g2_6 (25 11) routing sp4_r_v_b_38 lc_trk_g2_6 (25 11) routing sp4_v_t_27 lc_trk_g2_6 (25 11) routing tnl_op_6 lc_trk_g2_6 (25 12) routing bnl_op_2 lc_trk_g3_2 (25 12) routing rgt_op_2 lc_trk_g3_2 (25 12) routing sp12_v_t_1 lc_trk_g3_2 (25 12) routing sp4_h_r_34 lc_trk_g3_2 (25 12) routing sp4_h_r_42 lc_trk_g3_2 (25 12) routing sp4_v_b_34 lc_trk_g3_2 (25 12) routing sp4_v_t_15 lc_trk_g3_2 (25 13) routing bnl_op_2 lc_trk_g3_2 (25 13) routing sp12_v_b_18 lc_trk_g3_2 (25 13) routing sp12_v_t_1 lc_trk_g3_2 (25 13) routing sp4_h_l_15 lc_trk_g3_2 (25 13) routing sp4_h_r_42 lc_trk_g3_2 (25 13) routing sp4_r_v_b_42 lc_trk_g3_2 (25 13) routing sp4_v_b_34 lc_trk_g3_2 (25 13) routing tnl_op_2 lc_trk_g3_2 (25 14) routing bnl_op_6 lc_trk_g3_6 (25 14) routing rgt_op_6 lc_trk_g3_6 (25 14) routing sp12_v_t_5 lc_trk_g3_6 (25 14) routing sp4_h_l_27 lc_trk_g3_6 (25 14) routing sp4_h_r_46 lc_trk_g3_6 (25 14) routing sp4_v_t_19 lc_trk_g3_6 (25 14) routing sp4_v_t_27 lc_trk_g3_6 (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_22 lc_trk_g3_6 (25 15) routing sp12_v_t_5 lc_trk_g3_6 (25 15) routing sp4_h_l_19 lc_trk_g3_6 (25 15) routing sp4_h_r_46 lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_t_27 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 (25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 (25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_11 lc_trk_g0_6 (25 2) routing sp4_h_l_3 lc_trk_g0_6 (25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp12_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_l_11 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 (25 3) routing sp4_v_b_14 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_l_1 lc_trk_g1_2 (25 4) routing sp4_h_r_10 lc_trk_g1_2 (25 4) routing sp4_h_r_18 lc_trk_g1_2 (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 (25 5) routing sp12_h_l_1 lc_trk_g1_2 (25 5) routing sp12_h_l_17 lc_trk_g1_2 (25 5) routing sp4_h_r_18 lc_trk_g1_2 (25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 (25 6) routing sp4_h_l_11 lc_trk_g1_6 (25 6) routing sp4_h_l_3 lc_trk_g1_6 (25 6) routing sp4_v_b_14 lc_trk_g1_6 (25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp12_h_r_22 lc_trk_g1_6 (25 7) routing sp4_h_l_11 lc_trk_g1_6 (25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_b_14 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_t_1 lc_trk_g2_2 (25 8) routing sp4_h_r_34 lc_trk_g2_2 (25 8) routing sp4_h_r_42 lc_trk_g2_2 (25 8) routing sp4_v_b_34 lc_trk_g2_2 (25 8) routing sp4_v_t_15 lc_trk_g2_2 (25 9) routing bnl_op_2 lc_trk_g2_2 (25 9) routing sp12_v_b_18 lc_trk_g2_2 (25 9) routing sp12_v_t_1 lc_trk_g2_2 (25 9) routing sp4_h_l_15 lc_trk_g2_2 (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_b_34 lc_trk_g2_2 (25 9) routing tnl_op_2 lc_trk_g2_2 (26 0) routing lc_trk_g0_4 input0_0 (26 0) routing lc_trk_g0_6 input0_0 (26 0) routing lc_trk_g1_5 input0_0 (26 0) routing lc_trk_g1_7 input0_0 (26 0) routing lc_trk_g2_4 input0_0 (26 0) routing lc_trk_g2_6 input0_0 (26 0) routing lc_trk_g3_5 input0_0 (26 0) routing lc_trk_g3_7 input0_0 (26 1) routing lc_trk_g0_2 input0_0 (26 1) routing lc_trk_g0_6 input0_0 (26 1) routing lc_trk_g1_3 input0_0 (26 1) routing lc_trk_g1_7 input0_0 (26 1) routing lc_trk_g2_2 input0_0 (26 1) routing lc_trk_g2_6 input0_0 (26 1) routing lc_trk_g3_3 input0_0 (26 1) routing lc_trk_g3_7 input0_0 (26 10) routing lc_trk_g0_5 input0_5 (26 10) routing lc_trk_g0_7 input0_5 (26 10) routing lc_trk_g1_4 input0_5 (26 10) routing lc_trk_g1_6 input0_5 (26 10) routing lc_trk_g2_5 input0_5 (26 10) routing lc_trk_g2_7 input0_5 (26 10) routing lc_trk_g3_4 input0_5 (26 10) routing lc_trk_g3_6 input0_5 (26 11) routing lc_trk_g0_3 input0_5 (26 11) routing lc_trk_g0_7 input0_5 (26 11) routing lc_trk_g1_2 input0_5 (26 11) routing lc_trk_g1_6 input0_5 (26 11) routing lc_trk_g2_3 input0_5 (26 11) routing lc_trk_g2_7 input0_5 (26 11) routing lc_trk_g3_2 input0_5 (26 11) routing lc_trk_g3_6 input0_5 (26 12) routing lc_trk_g0_4 input0_6 (26 12) routing lc_trk_g0_6 input0_6 (26 12) routing lc_trk_g1_5 input0_6 (26 12) routing lc_trk_g1_7 input0_6 (26 12) routing lc_trk_g2_4 input0_6 (26 12) routing lc_trk_g2_6 input0_6 (26 12) routing lc_trk_g3_5 input0_6 (26 12) routing lc_trk_g3_7 input0_6 (26 13) routing lc_trk_g0_2 input0_6 (26 13) routing lc_trk_g0_6 input0_6 (26 13) routing lc_trk_g1_3 input0_6 (26 13) routing lc_trk_g1_7 input0_6 (26 13) routing lc_trk_g2_2 input0_6 (26 13) routing lc_trk_g2_6 input0_6 (26 13) routing lc_trk_g3_3 input0_6 (26 13) routing lc_trk_g3_7 input0_6 (26 14) routing lc_trk_g0_5 input0_7 (26 14) routing lc_trk_g0_7 input0_7 (26 14) routing lc_trk_g1_4 input0_7 (26 14) routing lc_trk_g1_6 input0_7 (26 14) routing lc_trk_g2_5 input0_7 (26 14) routing lc_trk_g2_7 input0_7 (26 14) routing lc_trk_g3_4 input0_7 (26 14) routing lc_trk_g3_6 input0_7 (26 15) routing lc_trk_g0_3 input0_7 (26 15) routing lc_trk_g0_7 input0_7 (26 15) routing lc_trk_g1_2 input0_7 (26 15) routing lc_trk_g1_6 input0_7 (26 15) routing lc_trk_g2_3 input0_7 (26 15) routing lc_trk_g2_7 input0_7 (26 15) routing lc_trk_g3_2 input0_7 (26 15) routing lc_trk_g3_6 input0_7 (26 2) routing lc_trk_g0_5 input0_1 (26 2) routing lc_trk_g0_7 input0_1 (26 2) routing lc_trk_g1_4 input0_1 (26 2) routing lc_trk_g1_6 input0_1 (26 2) routing lc_trk_g2_5 input0_1 (26 2) routing lc_trk_g2_7 input0_1 (26 2) routing lc_trk_g3_4 input0_1 (26 2) routing lc_trk_g3_6 input0_1 (26 3) routing lc_trk_g0_3 input0_1 (26 3) routing lc_trk_g0_7 input0_1 (26 3) routing lc_trk_g1_2 input0_1 (26 3) routing lc_trk_g1_6 input0_1 (26 3) routing lc_trk_g2_3 input0_1 (26 3) routing lc_trk_g2_7 input0_1 (26 3) routing lc_trk_g3_2 input0_1 (26 3) routing lc_trk_g3_6 input0_1 (26 4) routing lc_trk_g0_4 input0_2 (26 4) routing lc_trk_g0_6 input0_2 (26 4) routing lc_trk_g1_5 input0_2 (26 4) routing lc_trk_g1_7 input0_2 (26 4) routing lc_trk_g2_4 input0_2 (26 4) routing lc_trk_g2_6 input0_2 (26 4) routing lc_trk_g3_5 input0_2 (26 4) routing lc_trk_g3_7 input0_2 (26 5) routing lc_trk_g0_2 input0_2 (26 5) routing lc_trk_g0_6 input0_2 (26 5) routing lc_trk_g1_3 input0_2 (26 5) routing lc_trk_g1_7 input0_2 (26 5) routing lc_trk_g2_2 input0_2 (26 5) routing lc_trk_g2_6 input0_2 (26 5) routing lc_trk_g3_3 input0_2 (26 5) routing lc_trk_g3_7 input0_2 (26 6) routing lc_trk_g0_5 input0_3 (26 6) routing lc_trk_g0_7 input0_3 (26 6) routing lc_trk_g1_4 input0_3 (26 6) routing lc_trk_g1_6 input0_3 (26 6) routing lc_trk_g2_5 input0_3 (26 6) routing lc_trk_g2_7 input0_3 (26 6) routing lc_trk_g3_4 input0_3 (26 6) routing lc_trk_g3_6 input0_3 (26 7) routing lc_trk_g0_3 input0_3 (26 7) routing lc_trk_g0_7 input0_3 (26 7) routing lc_trk_g1_2 input0_3 (26 7) routing lc_trk_g1_6 input0_3 (26 7) routing lc_trk_g2_3 input0_3 (26 7) routing lc_trk_g2_7 input0_3 (26 7) routing lc_trk_g3_2 input0_3 (26 7) routing lc_trk_g3_6 input0_3 (26 8) routing lc_trk_g0_4 input0_4 (26 8) routing lc_trk_g0_6 input0_4 (26 8) routing lc_trk_g1_5 input0_4 (26 8) routing lc_trk_g1_7 input0_4 (26 8) routing lc_trk_g2_4 input0_4 (26 8) routing lc_trk_g2_6 input0_4 (26 8) routing lc_trk_g3_5 input0_4 (26 8) routing lc_trk_g3_7 input0_4 (26 9) routing lc_trk_g0_2 input0_4 (26 9) routing lc_trk_g0_6 input0_4 (26 9) routing lc_trk_g1_3 input0_4 (26 9) routing lc_trk_g1_7 input0_4 (26 9) routing lc_trk_g2_2 input0_4 (26 9) routing lc_trk_g2_6 input0_4 (26 9) routing lc_trk_g3_3 input0_4 (26 9) routing lc_trk_g3_7 input0_4 (27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_0 (27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_0 (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_0 (27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_0 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_0 (27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_0 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_0 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_0 (27 1) routing lc_trk_g1_1 input0_0 (27 1) routing lc_trk_g1_3 input0_0 (27 1) routing lc_trk_g1_5 input0_0 (27 1) routing lc_trk_g1_7 input0_0 (27 1) routing lc_trk_g3_1 input0_0 (27 1) routing lc_trk_g3_3 input0_0 (27 1) routing lc_trk_g3_5 input0_0 (27 1) routing lc_trk_g3_7 input0_0 (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_5 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_5 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_5 (27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_5 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_5 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_5 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_5 (27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_5 (27 11) routing lc_trk_g1_0 input0_5 (27 11) routing lc_trk_g1_2 input0_5 (27 11) routing lc_trk_g1_4 input0_5 (27 11) routing lc_trk_g1_6 input0_5 (27 11) routing lc_trk_g3_0 input0_5 (27 11) routing lc_trk_g3_2 input0_5 (27 11) routing lc_trk_g3_4 input0_5 (27 11) routing lc_trk_g3_6 input0_5 (27 12) routing lc_trk_g1_0 wire_bram/ram/WDATA_6 (27 12) routing lc_trk_g1_2 wire_bram/ram/WDATA_6 (27 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_6 (27 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_6 (27 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_6 (27 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_6 (27 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_6 (27 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_6 (27 13) routing lc_trk_g1_1 input0_6 (27 13) routing lc_trk_g1_3 input0_6 (27 13) routing lc_trk_g1_5 input0_6 (27 13) routing lc_trk_g1_7 input0_6 (27 13) routing lc_trk_g3_1 input0_6 (27 13) routing lc_trk_g3_3 input0_6 (27 13) routing lc_trk_g3_5 input0_6 (27 13) routing lc_trk_g3_7 input0_6 (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_7 (27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_7 (27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_7 (27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_7 (27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_7 (27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_7 (27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_7 (27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_7 (27 15) routing lc_trk_g1_0 input0_7 (27 15) routing lc_trk_g1_2 input0_7 (27 15) routing lc_trk_g1_4 input0_7 (27 15) routing lc_trk_g1_6 input0_7 (27 15) routing lc_trk_g3_0 input0_7 (27 15) routing lc_trk_g3_2 input0_7 (27 15) routing lc_trk_g3_4 input0_7 (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_1 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_1 (27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_1 (27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_1 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_1 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_1 (27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_1 (27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_1 (27 3) routing lc_trk_g1_0 input0_1 (27 3) routing lc_trk_g1_2 input0_1 (27 3) routing lc_trk_g1_4 input0_1 (27 3) routing lc_trk_g1_6 input0_1 (27 3) routing lc_trk_g3_0 input0_1 (27 3) routing lc_trk_g3_2 input0_1 (27 3) routing lc_trk_g3_4 input0_1 (27 3) routing lc_trk_g3_6 input0_1 (27 4) routing lc_trk_g1_0 wire_bram/ram/WDATA_2 (27 4) routing lc_trk_g1_2 wire_bram/ram/WDATA_2 (27 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_2 (27 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_2 (27 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_2 (27 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_2 (27 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_2 (27 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_2 (27 5) routing lc_trk_g1_1 input0_2 (27 5) routing lc_trk_g1_3 input0_2 (27 5) routing lc_trk_g1_5 input0_2 (27 5) routing lc_trk_g1_7 input0_2 (27 5) routing lc_trk_g3_1 input0_2 (27 5) routing lc_trk_g3_3 input0_2 (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 (27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_3 (27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_3 (27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_3 (27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_3 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_3 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_3 (27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_3 (27 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_3 (27 7) routing lc_trk_g1_0 input0_3 (27 7) routing lc_trk_g1_2 input0_3 (27 7) routing lc_trk_g1_4 input0_3 (27 7) routing lc_trk_g1_6 input0_3 (27 7) routing lc_trk_g3_0 input0_3 (27 7) routing lc_trk_g3_2 input0_3 (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_4 (27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_4 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_4 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_4 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_4 (27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_4 (27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_4 (27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_4 (27 9) routing lc_trk_g1_1 input0_4 (27 9) routing lc_trk_g1_3 input0_4 (27 9) routing lc_trk_g1_5 input0_4 (27 9) routing lc_trk_g1_7 input0_4 (27 9) routing lc_trk_g3_1 input0_4 (27 9) routing lc_trk_g3_3 input0_4 (27 9) routing lc_trk_g3_5 input0_4 (27 9) routing lc_trk_g3_7 input0_4 (28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_0 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_0 (28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_0 (28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_0 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_0 (28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_0 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_0 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_0 (28 1) routing lc_trk_g2_0 input0_0 (28 1) routing lc_trk_g2_2 input0_0 (28 1) routing lc_trk_g2_4 input0_0 (28 1) routing lc_trk_g2_6 input0_0 (28 1) routing lc_trk_g3_1 input0_0 (28 1) routing lc_trk_g3_3 input0_0 (28 1) routing lc_trk_g3_5 input0_0 (28 1) routing lc_trk_g3_7 input0_0 (28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_5 (28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_5 (28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_5 (28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_5 (28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_5 (28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_5 (28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_5 (28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_5 (28 11) routing lc_trk_g2_1 input0_5 (28 11) routing lc_trk_g2_3 input0_5 (28 11) routing lc_trk_g2_5 input0_5 (28 11) routing lc_trk_g2_7 input0_5 (28 11) routing lc_trk_g3_0 input0_5 (28 11) routing lc_trk_g3_2 input0_5 (28 11) routing lc_trk_g3_4 input0_5 (28 11) routing lc_trk_g3_6 input0_5 (28 12) routing lc_trk_g2_1 wire_bram/ram/WDATA_6 (28 12) routing lc_trk_g2_3 wire_bram/ram/WDATA_6 (28 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_6 (28 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_6 (28 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_6 (28 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_6 (28 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_6 (28 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_6 (28 13) routing lc_trk_g2_0 input0_6 (28 13) routing lc_trk_g2_2 input0_6 (28 13) routing lc_trk_g2_4 input0_6 (28 13) routing lc_trk_g2_6 input0_6 (28 13) routing lc_trk_g3_1 input0_6 (28 13) routing lc_trk_g3_3 input0_6 (28 13) routing lc_trk_g3_5 input0_6 (28 13) routing lc_trk_g3_7 input0_6 (28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_7 (28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_7 (28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_7 (28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_7 (28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_7 (28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_7 (28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_7 (28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_7 (28 15) routing lc_trk_g2_1 input0_7 (28 15) routing lc_trk_g2_3 input0_7 (28 15) routing lc_trk_g2_5 input0_7 (28 15) routing lc_trk_g2_7 input0_7 (28 15) routing lc_trk_g3_0 input0_7 (28 15) routing lc_trk_g3_2 input0_7 (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 (28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_1 (28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_1 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_1 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_1 (28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_1 (28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_1 (28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_1 (28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_1 (28 3) routing lc_trk_g2_1 input0_1 (28 3) routing lc_trk_g2_3 input0_1 (28 3) routing lc_trk_g2_5 input0_1 (28 3) routing lc_trk_g2_7 input0_1 (28 3) routing lc_trk_g3_0 input0_1 (28 3) routing lc_trk_g3_2 input0_1 (28 3) routing lc_trk_g3_4 input0_1 (28 3) routing lc_trk_g3_6 input0_1 (28 4) routing lc_trk_g2_1 wire_bram/ram/WDATA_2 (28 4) routing lc_trk_g2_3 wire_bram/ram/WDATA_2 (28 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_2 (28 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_2 (28 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_2 (28 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_2 (28 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_2 (28 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_2 (28 5) routing lc_trk_g2_0 input0_2 (28 5) routing lc_trk_g2_2 input0_2 (28 5) routing lc_trk_g2_4 input0_2 (28 5) routing lc_trk_g2_6 input0_2 (28 5) routing lc_trk_g3_1 input0_2 (28 5) routing lc_trk_g3_3 input0_2 (28 5) routing lc_trk_g3_5 input0_2 (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_3 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_3 (28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_3 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_3 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_3 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_3 (28 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_3 (28 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_3 (28 7) routing lc_trk_g2_1 input0_3 (28 7) routing lc_trk_g2_3 input0_3 (28 7) routing lc_trk_g2_5 input0_3 (28 7) routing lc_trk_g2_7 input0_3 (28 7) routing lc_trk_g3_0 input0_3 (28 7) routing lc_trk_g3_2 input0_3 (28 7) routing lc_trk_g3_4 input0_3 (28 7) routing lc_trk_g3_6 input0_3 (28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_4 (28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_4 (28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_4 (28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_4 (28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_4 (28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_4 (28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_4 (28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_4 (28 9) routing lc_trk_g2_0 input0_4 (28 9) routing lc_trk_g2_2 input0_4 (28 9) routing lc_trk_g2_4 input0_4 (28 9) routing lc_trk_g2_6 input0_4 (28 9) routing lc_trk_g3_1 input0_4 (28 9) routing lc_trk_g3_3 input0_4 (28 9) routing lc_trk_g3_5 input0_4 (28 9) routing lc_trk_g3_7 input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_0 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_5 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_6 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_7 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_1 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_2 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_3 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_4 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 (3 0) routing sp12_h_r_0 sp12_v_b_0 (3 0) routing sp12_v_t_23 sp12_v_b_0 (3 1) routing sp12_h_l_23 sp12_v_b_0 (3 1) routing sp12_h_r_0 sp12_v_b_0 (3 10) routing sp12_h_r_1 sp12_h_l_22 (3 10) routing sp12_v_t_22 sp12_h_l_22 (3 11) routing sp12_h_r_1 sp12_h_l_22 (3 11) routing sp12_v_b_1 sp12_h_l_22 (3 12) routing sp12_v_b_1 sp12_h_r_1 (3 12) routing sp12_v_t_22 sp12_h_r_1 (3 13) routing sp12_h_l_22 sp12_h_r_1 (3 13) routing sp12_v_b_1 sp12_h_r_1 (3 14) routing sp12_h_r_1 sp12_v_t_22 (3 14) routing sp12_v_b_1 sp12_v_t_22 (3 15) routing sp12_h_l_22 sp12_v_t_22 (3 15) routing sp12_h_r_1 sp12_v_t_22 (3 2) routing sp12_h_r_0 sp12_h_l_23 (3 2) routing sp12_v_t_23 sp12_h_l_23 (3 3) routing sp12_h_r_0 sp12_h_l_23 (3 3) routing sp12_v_b_0 sp12_h_l_23 (3 4) routing sp12_v_b_0 sp12_h_r_0 (3 4) routing sp12_v_t_23 sp12_h_r_0 (3 5) routing sp12_h_l_23 sp12_h_r_0 (3 5) routing sp12_v_b_0 sp12_h_r_0 (3 6) routing sp12_h_r_0 sp12_v_t_23 (3 6) routing sp12_v_b_0 sp12_v_t_23 (3 7) routing sp12_h_l_23 sp12_v_t_23 (3 7) routing sp12_h_r_0 sp12_v_t_23 (3 8) routing sp12_h_r_1 sp12_v_b_1 (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 (30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_0 (30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_0 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_0 (30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_0 (30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_0 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_0 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_0 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_0 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_0 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_5 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_5 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_5 (30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_5 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_5 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_5 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_5 (30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_5 (30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_5 (30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_6 (30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_6 (30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_6 (30 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_6 (30 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_6 (30 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_6 (30 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_6 (30 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g0_3 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g0_7 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g1_2 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g1_6 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g2_3 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g2_7 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g3_2 wire_bram/ram/WDATA_6 (30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_6 (30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_7 (30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_7 (30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_7 (30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_7 (30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_7 (30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_7 (30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_7 (30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_7 (30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_7 (30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_1 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_1 (30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_1 (30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_1 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_1 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_1 (30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_1 (30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_1 (30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_1 (30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_2 (30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_2 (30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_2 (30 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_2 (30 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_2 (30 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_2 (30 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_2 (30 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g0_3 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g0_7 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g1_2 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g1_6 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g2_3 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_2 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_2 (30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_3 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_3 (30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_3 (30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_3 (30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_3 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_3 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_3 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_3 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_4 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_4 (31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_0 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_0 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_0 (31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_0 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_0 (31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_0 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_0 (31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_0 (31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_0 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_5 (31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_5 (31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_5 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_5 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_5 (31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_5 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_5 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_5 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_5 (31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_6 (31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_6 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_6 (31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_6 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_6 (31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_6 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_6 (31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_6 (31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_6 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_7 (31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_7 (31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_7 (31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_7 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_7 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_7 (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_7 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_7 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_7 (31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_1 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_1 (31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_1 (31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_1 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_1 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_1 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_1 (31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_1 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_1 (31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_2 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_2 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_2 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_2 (31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_2 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_2 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_2 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_2 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_2 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_3 (31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_3 (31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_3 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_3 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_3 (31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_3 (31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_3 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_3 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_4 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_4 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_0 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_0 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_2 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_4 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_6 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_1 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_3 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_5 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_7 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_0 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_2 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_4 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_6 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_1 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_3 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_5 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_7 input2_0 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_5 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_6 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_6 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_7 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_7 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_1 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_1 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_3 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_5 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_7 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_0 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_2 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_4 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_6 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_1 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_3 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_5 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_7 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_0 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_2 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_4 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_6 input2_1 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_2 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_0 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_2 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_4 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_6 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_1 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_3 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_5 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_7 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_0 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_2 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_4 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_6 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_1 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_3 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_5 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_7 input2_2 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_3 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_4 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_0 (33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_0 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_0 (33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_0 (33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_0 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_0 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_0 (33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_0 (33 1) routing lc_trk_g2_0 input2_0 (33 1) routing lc_trk_g2_2 input2_0 (33 1) routing lc_trk_g2_4 input2_0 (33 1) routing lc_trk_g2_6 input2_0 (33 1) routing lc_trk_g3_1 input2_0 (33 1) routing lc_trk_g3_3 input2_0 (33 1) routing lc_trk_g3_5 input2_0 (33 1) routing lc_trk_g3_7 input2_0 (33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_5 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_5 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_5 (33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_5 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_5 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_5 (33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_5 (33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_5 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_6 (33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_6 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_6 (33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_6 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_6 (33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_6 (33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_6 (33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_6 (33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_7 (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_7 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_7 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_7 (33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_7 (33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_7 (33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_7 (33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_7 (33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_1 (33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_1 (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_1 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_1 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_1 (33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_1 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_1 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_1 (33 3) routing lc_trk_g2_1 input2_1 (33 3) routing lc_trk_g2_3 input2_1 (33 3) routing lc_trk_g2_5 input2_1 (33 3) routing lc_trk_g2_7 input2_1 (33 3) routing lc_trk_g3_0 input2_1 (33 3) routing lc_trk_g3_2 input2_1 (33 3) routing lc_trk_g3_4 input2_1 (33 3) routing lc_trk_g3_6 input2_1 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_2 (33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_2 (33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_2 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_2 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_2 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_2 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_2 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_2 (33 5) routing lc_trk_g2_0 input2_2 (33 5) routing lc_trk_g2_2 input2_2 (33 5) routing lc_trk_g2_4 input2_2 (33 5) routing lc_trk_g2_6 input2_2 (33 5) routing lc_trk_g3_1 input2_2 (33 5) routing lc_trk_g3_3 input2_2 (33 5) routing lc_trk_g3_5 input2_2 (33 5) routing lc_trk_g3_7 input2_2 (33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_3 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_3 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_3 (33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_3 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_3 (33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_3 (33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_3 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_4 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_0 (34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_0 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_0 (34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_0 (34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_0 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_0 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_0 (34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_0 (34 1) routing lc_trk_g1_1 input2_0 (34 1) routing lc_trk_g1_3 input2_0 (34 1) routing lc_trk_g1_5 input2_0 (34 1) routing lc_trk_g1_7 input2_0 (34 1) routing lc_trk_g3_1 input2_0 (34 1) routing lc_trk_g3_3 input2_0 (34 1) routing lc_trk_g3_5 input2_0 (34 1) routing lc_trk_g3_7 input2_0 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_5 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_5 (34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_5 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_5 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_5 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_5 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_5 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_5 (34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_6 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_6 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_6 (34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_6 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_6 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_6 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_6 (34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_7 (34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_7 (34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_7 (34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_7 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_7 (34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_7 (34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_7 (34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_7 (34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_1 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_1 (34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_1 (34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_1 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_1 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_1 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_1 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_1 (34 3) routing lc_trk_g1_0 input2_1 (34 3) routing lc_trk_g1_2 input2_1 (34 3) routing lc_trk_g1_4 input2_1 (34 3) routing lc_trk_g1_6 input2_1 (34 3) routing lc_trk_g3_0 input2_1 (34 3) routing lc_trk_g3_2 input2_1 (34 3) routing lc_trk_g3_4 input2_1 (34 3) routing lc_trk_g3_6 input2_1 (34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_2 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_2 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_2 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_2 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_2 (34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_2 (34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_2 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_2 (34 5) routing lc_trk_g1_1 input2_2 (34 5) routing lc_trk_g1_3 input2_2 (34 5) routing lc_trk_g1_5 input2_2 (34 5) routing lc_trk_g1_7 input2_2 (34 5) routing lc_trk_g3_1 input2_2 (34 5) routing lc_trk_g3_3 input2_2 (34 5) routing lc_trk_g3_5 input2_2 (34 5) routing lc_trk_g3_7 input2_2 (34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_3 (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_3 (34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_3 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_3 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_3 (34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_3 (34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_3 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_4 (35 0) routing lc_trk_g0_4 input2_0 (35 0) routing lc_trk_g0_6 input2_0 (35 0) routing lc_trk_g1_5 input2_0 (35 0) routing lc_trk_g1_7 input2_0 (35 0) routing lc_trk_g2_4 input2_0 (35 0) routing lc_trk_g2_6 input2_0 (35 0) routing lc_trk_g3_5 input2_0 (35 0) routing lc_trk_g3_7 input2_0 (35 1) routing lc_trk_g0_2 input2_0 (35 1) routing lc_trk_g0_6 input2_0 (35 1) routing lc_trk_g1_3 input2_0 (35 1) routing lc_trk_g1_7 input2_0 (35 1) routing lc_trk_g2_2 input2_0 (35 1) routing lc_trk_g2_6 input2_0 (35 1) routing lc_trk_g3_3 input2_0 (35 1) routing lc_trk_g3_7 input2_0 (35 2) routing lc_trk_g0_5 input2_1 (35 2) routing lc_trk_g0_7 input2_1 (35 2) routing lc_trk_g1_4 input2_1 (35 2) routing lc_trk_g1_6 input2_1 (35 2) routing lc_trk_g2_5 input2_1 (35 2) routing lc_trk_g2_7 input2_1 (35 2) routing lc_trk_g3_4 input2_1 (35 2) routing lc_trk_g3_6 input2_1 (35 3) routing lc_trk_g0_3 input2_1 (35 3) routing lc_trk_g0_7 input2_1 (35 3) routing lc_trk_g1_2 input2_1 (35 3) routing lc_trk_g1_6 input2_1 (35 3) routing lc_trk_g2_3 input2_1 (35 3) routing lc_trk_g2_7 input2_1 (35 3) routing lc_trk_g3_2 input2_1 (35 3) routing lc_trk_g3_6 input2_1 (35 4) routing lc_trk_g0_4 input2_2 (35 4) routing lc_trk_g0_6 input2_2 (35 4) routing lc_trk_g1_5 input2_2 (35 4) routing lc_trk_g1_7 input2_2 (35 4) routing lc_trk_g2_4 input2_2 (35 4) routing lc_trk_g2_6 input2_2 (35 4) routing lc_trk_g3_5 input2_2 (35 4) routing lc_trk_g3_7 input2_2 (35 5) routing lc_trk_g0_2 input2_2 (35 5) routing lc_trk_g0_6 input2_2 (35 5) routing lc_trk_g1_3 input2_2 (35 5) routing lc_trk_g1_7 input2_2 (35 5) routing lc_trk_g2_2 input2_2 (35 5) routing lc_trk_g2_6 input2_2 (35 5) routing lc_trk_g3_3 input2_2 (35 5) routing lc_trk_g3_7 input2_2 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_0 sp4_h_r_32 (36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_0 sp4_h_r_0 (36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_5 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_5 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_6 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_6 sp4_h_l_1 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_7 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_7 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_1 sp4_h_r_34 (36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_1 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_2 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_2 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_3 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_3 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_4 sp4_h_r_40 (36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_4 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_0 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_0 sp4_h_r_16 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_5 sp12_h_l_1 (37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_5 sp4_h_l_15 (37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_6 sp12_h_l_3 (37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_6 sp4_h_r_28 (37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_7 sp12_h_l_5 (37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_7 sp4_h_l_19 (37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_1 sp12_h_l_9 (37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_1 sp4_h_r_18 (37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_2 sp12_h_r_12 (37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_2 sp4_h_l_9 (37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_3 sp12_h_r_14 (37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_3 sp4_h_l_11 (37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_4 sp12_h_r_0 (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_4 sp4_h_r_24 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_0 sp4_v_b_32 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_0 sp4_v_b_0 (38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_5 sp4_v_t_15 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_5 sp12_h_l_17 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_6 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_6 sp12_h_r_20 (38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_7 sp4_v_t_19 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_7 sp12_h_r_22 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_1 sp4_v_b_34 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_1 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_2 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_2 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_3 sp4_v_t_27 (38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_3 sp4_v_b_6 (38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_4 sp4_v_t_13 (38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_4 sp12_h_l_15 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_0 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_0 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_5 sp4_v_t_31 (39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_5 sp4_v_b_10 (39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_6 sp4_v_b_44 (39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_6 sp4_v_b_12 (39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_7 sp4_v_b_46 (39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_7 sp4_v_b_14 (39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_1 sp12_v_t_1 (39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_1 sp4_v_t_7 (39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_2 sp12_v_b_4 (39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_2 sp4_v_b_20 (39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_3 sp12_v_t_5 (39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_3 sp4_v_t_11 (39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_4 sp4_v_b_40 (39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_4 sp4_v_b_8 (4 0) routing sp4_h_l_37 sp4_v_b_0 (4 0) routing sp4_h_l_43 sp4_v_b_0 (4 0) routing sp4_v_t_37 sp4_v_b_0 (4 0) routing sp4_v_t_41 sp4_v_b_0 (4 1) routing sp4_h_l_41 sp4_h_r_0 (4 1) routing sp4_h_l_44 sp4_h_r_0 (4 1) routing sp4_v_b_6 sp4_h_r_0 (4 1) routing sp4_v_t_42 sp4_h_r_0 (4 10) routing sp4_h_r_0 sp4_v_t_43 (4 10) routing sp4_h_r_6 sp4_v_t_43 (4 10) routing sp4_v_b_10 sp4_v_t_43 (4 10) routing sp4_v_b_6 sp4_v_t_43 (4 11) routing sp4_h_r_10 sp4_h_l_43 (4 11) routing sp4_h_r_3 sp4_h_l_43 (4 11) routing sp4_v_b_1 sp4_h_l_43 (4 11) routing sp4_v_t_37 sp4_h_l_43 (4 12) routing sp4_h_l_38 sp4_v_b_9 (4 12) routing sp4_h_l_44 sp4_v_b_9 (4 12) routing sp4_v_t_36 sp4_v_b_9 (4 12) routing sp4_v_t_44 sp4_v_b_9 (4 13) routing sp4_h_l_36 sp4_h_r_9 (4 13) routing sp4_h_l_43 sp4_h_r_9 (4 13) routing sp4_v_b_3 sp4_h_r_9 (4 13) routing sp4_v_t_41 sp4_h_r_9 (4 14) routing sp4_h_r_3 sp4_v_t_44 (4 14) routing sp4_h_r_9 sp4_v_t_44 (4 14) routing sp4_v_b_1 sp4_v_t_44 (4 14) routing sp4_v_b_9 sp4_v_t_44 (4 15) routing sp4_h_r_1 sp4_h_l_44 (4 15) routing sp4_h_r_6 sp4_h_l_44 (4 15) routing sp4_v_b_4 sp4_h_l_44 (4 15) routing sp4_v_t_38 sp4_h_l_44 (4 2) routing sp4_h_r_0 sp4_v_t_37 (4 2) routing sp4_h_r_6 sp4_v_t_37 (4 2) routing sp4_v_b_0 sp4_v_t_37 (4 2) routing sp4_v_b_4 sp4_v_t_37 (4 3) routing sp4_h_r_4 sp4_h_l_37 (4 3) routing sp4_h_r_9 sp4_h_l_37 (4 3) routing sp4_v_b_7 sp4_h_l_37 (4 3) routing sp4_v_t_43 sp4_h_l_37 (4 4) routing sp4_h_l_38 sp4_v_b_3 (4 4) routing sp4_h_l_44 sp4_v_b_3 (4 4) routing sp4_v_t_38 sp4_v_b_3 (4 4) routing sp4_v_t_42 sp4_v_b_3 (4 5) routing sp4_h_l_37 sp4_h_r_3 (4 5) routing sp4_h_l_42 sp4_h_r_3 (4 5) routing sp4_v_b_9 sp4_h_r_3 (4 5) routing sp4_v_t_47 sp4_h_r_3 (4 6) routing sp4_h_r_3 sp4_v_t_38 (4 6) routing sp4_h_r_9 sp4_v_t_38 (4 6) routing sp4_v_b_3 sp4_v_t_38 (4 6) routing sp4_v_b_7 sp4_v_t_38 (4 7) routing sp4_h_r_0 sp4_h_l_38 (4 7) routing sp4_h_r_7 sp4_h_l_38 (4 7) routing sp4_v_b_10 sp4_h_l_38 (4 7) routing sp4_v_t_44 sp4_h_l_38 (4 8) routing sp4_h_l_37 sp4_v_b_6 (4 8) routing sp4_h_l_43 sp4_v_b_6 (4 8) routing sp4_v_t_43 sp4_v_b_6 (4 8) routing sp4_v_t_47 sp4_v_b_6 (4 9) routing sp4_h_l_38 sp4_h_r_6 (4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_0 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_0 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_5 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_5 sp12_v_b_10 (40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_6 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_6 sp12_v_t_11 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_7 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_7 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_1 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_1 sp12_v_b_18 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_2 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_2 sp12_v_b_20 (40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_3 sp4_r_v_b_23 (40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_3 sp12_v_b_22 (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_4 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_4 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_0 sp4_r_v_b_33 (41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_0 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_5 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_5 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_6 sp4_r_v_b_45 (41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_6 sp4_r_v_b_13 (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_7 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_7 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_1 sp4_r_v_b_35 (41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_1 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_2 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_2 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_3 sp4_r_v_b_39 (41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_3 sp4_r_v_b_7 (41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_4 sp4_r_v_b_41 (41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_4 sp4_r_v_b_9 (5 0) routing sp4_h_l_44 sp4_h_r_0 (5 0) routing sp4_v_b_0 sp4_h_r_0 (5 0) routing sp4_v_b_6 sp4_h_r_0 (5 0) routing sp4_v_t_37 sp4_h_r_0 (5 1) routing sp4_h_l_37 sp4_v_b_0 (5 1) routing sp4_h_l_43 sp4_v_b_0 (5 1) routing sp4_h_r_0 sp4_v_b_0 (5 1) routing sp4_v_t_44 sp4_v_b_0 (5 10) routing sp4_h_r_3 sp4_h_l_43 (5 10) routing sp4_v_b_6 sp4_h_l_43 (5 10) routing sp4_v_t_37 sp4_h_l_43 (5 10) routing sp4_v_t_43 sp4_h_l_43 (5 11) routing sp4_h_l_43 sp4_v_t_43 (5 11) routing sp4_h_r_0 sp4_v_t_43 (5 11) routing sp4_h_r_6 sp4_v_t_43 (5 11) routing sp4_v_b_3 sp4_v_t_43 (5 12) routing sp4_h_l_43 sp4_h_r_9 (5 12) routing sp4_v_b_3 sp4_h_r_9 (5 12) routing sp4_v_b_9 sp4_h_r_9 (5 12) routing sp4_v_t_44 sp4_h_r_9 (5 13) routing sp4_h_l_38 sp4_v_b_9 (5 13) routing sp4_h_l_44 sp4_v_b_9 (5 13) routing sp4_h_r_9 sp4_v_b_9 (5 13) routing sp4_v_t_43 sp4_v_b_9 (5 14) routing sp4_h_r_6 sp4_h_l_44 (5 14) routing sp4_v_b_9 sp4_h_l_44 (5 14) routing sp4_v_t_38 sp4_h_l_44 (5 14) routing sp4_v_t_44 sp4_h_l_44 (5 15) routing sp4_h_l_44 sp4_v_t_44 (5 15) routing sp4_h_r_3 sp4_v_t_44 (5 15) routing sp4_h_r_9 sp4_v_t_44 (5 15) routing sp4_v_b_6 sp4_v_t_44 (5 2) routing sp4_h_r_9 sp4_h_l_37 (5 2) routing sp4_v_b_0 sp4_h_l_37 (5 2) routing sp4_v_t_37 sp4_h_l_37 (5 2) routing sp4_v_t_43 sp4_h_l_37 (5 3) routing sp4_h_l_37 sp4_v_t_37 (5 3) routing sp4_h_r_0 sp4_v_t_37 (5 3) routing sp4_h_r_6 sp4_v_t_37 (5 3) routing sp4_v_b_9 sp4_v_t_37 (5 4) routing sp4_h_l_37 sp4_h_r_3 (5 4) routing sp4_v_b_3 sp4_h_r_3 (5 4) routing sp4_v_b_9 sp4_h_r_3 (5 4) routing sp4_v_t_38 sp4_h_r_3 (5 5) routing sp4_h_l_38 sp4_v_b_3 (5 5) routing sp4_h_l_44 sp4_v_b_3 (5 5) routing sp4_h_r_3 sp4_v_b_3 (5 5) routing sp4_v_t_37 sp4_v_b_3 (5 6) routing sp4_h_r_0 sp4_h_l_38 (5 6) routing sp4_v_b_3 sp4_h_l_38 (5 6) routing sp4_v_t_38 sp4_h_l_38 (5 6) routing sp4_v_t_44 sp4_h_l_38 (5 7) routing sp4_h_l_38 sp4_v_t_38 (5 7) routing sp4_h_r_3 sp4_v_t_38 (5 7) routing sp4_h_r_9 sp4_v_t_38 (5 7) routing sp4_v_b_0 sp4_v_t_38 (5 8) routing sp4_h_l_38 sp4_h_r_6 (5 8) routing sp4_v_b_0 sp4_h_r_6 (5 8) routing sp4_v_b_6 sp4_h_r_6 (5 8) routing sp4_v_t_43 sp4_h_r_6 (5 9) routing sp4_h_l_37 sp4_v_b_6 (5 9) routing sp4_h_l_43 sp4_v_b_6 (5 9) routing sp4_h_r_6 sp4_v_b_6 (5 9) routing sp4_v_t_38 sp4_v_b_6 (6 0) routing sp4_h_l_43 sp4_v_b_0 (6 0) routing sp4_h_r_7 sp4_v_b_0 (6 0) routing sp4_v_t_41 sp4_v_b_0 (6 0) routing sp4_v_t_44 sp4_v_b_0 (6 1) routing sp4_h_l_37 sp4_h_r_0 (6 1) routing sp4_h_l_41 sp4_h_r_0 (6 1) routing sp4_v_b_0 sp4_h_r_0 (6 1) routing sp4_v_b_6 sp4_h_r_0 (6 10) routing sp4_h_l_36 sp4_v_t_43 (6 10) routing sp4_h_r_0 sp4_v_t_43 (6 10) routing sp4_v_b_10 sp4_v_t_43 (6 10) routing sp4_v_b_3 sp4_v_t_43 (6 11) routing sp4_h_r_10 sp4_h_l_43 (6 11) routing sp4_h_r_6 sp4_h_l_43 (6 11) routing sp4_v_t_37 sp4_h_l_43 (6 11) routing sp4_v_t_43 sp4_h_l_43 (6 12) routing sp4_h_l_38 sp4_v_b_9 (6 12) routing sp4_h_r_4 sp4_v_b_9 (6 12) routing sp4_v_t_36 sp4_v_b_9 (6 12) routing sp4_v_t_43 sp4_v_b_9 (6 13) routing sp4_h_l_36 sp4_h_r_9 (6 13) routing sp4_h_l_44 sp4_h_r_9 (6 13) routing sp4_v_b_3 sp4_h_r_9 (6 13) routing sp4_v_b_9 sp4_h_r_9 (6 14) routing sp4_h_l_41 sp4_v_t_44 (6 14) routing sp4_h_r_3 sp4_v_t_44 (6 14) routing sp4_v_b_1 sp4_v_t_44 (6 14) routing sp4_v_b_6 sp4_v_t_44 (6 15) routing sp4_h_r_1 sp4_h_l_44 (6 15) routing sp4_h_r_9 sp4_h_l_44 (6 15) routing sp4_v_t_38 sp4_h_l_44 (6 15) routing sp4_v_t_44 sp4_h_l_44 (6 2) routing sp4_h_l_42 sp4_v_t_37 (6 2) routing sp4_h_r_6 sp4_v_t_37 (6 2) routing sp4_v_b_4 sp4_v_t_37 (6 2) routing sp4_v_b_9 sp4_v_t_37 (6 3) routing sp4_h_r_0 sp4_h_l_37 (6 3) routing sp4_h_r_4 sp4_h_l_37 (6 3) routing sp4_v_t_37 sp4_h_l_37 (6 3) routing sp4_v_t_43 sp4_h_l_37 (6 4) routing sp4_h_l_44 sp4_v_b_3 (6 4) routing sp4_h_r_10 sp4_v_b_3 (6 4) routing sp4_v_t_37 sp4_v_b_3 (6 4) routing sp4_v_t_42 sp4_v_b_3 (6 5) routing sp4_h_l_38 sp4_h_r_3 (6 5) routing sp4_h_l_42 sp4_h_r_3 (6 5) routing sp4_v_b_3 sp4_h_r_3 (6 5) routing sp4_v_b_9 sp4_h_r_3 (6 6) routing sp4_h_l_47 sp4_v_t_38 (6 6) routing sp4_h_r_9 sp4_v_t_38 (6 6) routing sp4_v_b_0 sp4_v_t_38 (6 6) routing sp4_v_b_7 sp4_v_t_38 (6 7) routing sp4_h_r_3 sp4_h_l_38 (6 7) routing sp4_h_r_7 sp4_h_l_38 (6 7) routing sp4_v_t_38 sp4_h_l_38 (6 7) routing sp4_v_t_44 sp4_h_l_38 (6 8) routing sp4_h_l_37 sp4_v_b_6 (6 8) routing sp4_h_r_1 sp4_v_b_6 (6 8) routing sp4_v_t_38 sp4_v_b_6 (6 8) routing sp4_v_t_47 sp4_v_b_6 (6 9) routing sp4_h_l_43 sp4_h_r_6 (6 9) routing sp4_h_l_47 sp4_h_r_6 (6 9) routing sp4_v_b_0 sp4_h_r_6 (6 9) routing sp4_v_b_6 sp4_h_r_6 (7 1) Ram config bit: MEMB_Power_Up_Control (8 0) routing sp4_h_l_36 sp4_h_r_1 (8 0) routing sp4_h_l_40 sp4_h_r_1 (8 0) routing sp4_v_b_1 sp4_h_r_1 (8 0) routing sp4_v_b_7 sp4_h_r_1 (8 1) routing sp4_h_l_36 sp4_v_b_1 (8 1) routing sp4_h_l_42 sp4_v_b_1 (8 1) routing sp4_h_r_1 sp4_v_b_1 (8 1) routing sp4_v_t_47 sp4_v_b_1 (8 10) routing sp4_h_r_11 sp4_h_l_42 (8 10) routing sp4_h_r_7 sp4_h_l_42 (8 10) routing sp4_v_t_36 sp4_h_l_42 (8 10) routing sp4_v_t_42 sp4_h_l_42 (8 11) routing sp4_h_l_42 sp4_v_t_42 (8 11) routing sp4_h_r_1 sp4_v_t_42 (8 11) routing sp4_h_r_7 sp4_v_t_42 (8 11) routing sp4_v_b_4 sp4_v_t_42 (8 12) routing sp4_h_l_39 sp4_h_r_10 (8 12) routing sp4_h_l_47 sp4_h_r_10 (8 12) routing sp4_v_b_10 sp4_h_r_10 (8 12) routing sp4_v_b_4 sp4_h_r_10 (8 13) routing sp4_h_l_41 sp4_v_b_10 (8 13) routing sp4_h_l_47 sp4_v_b_10 (8 13) routing sp4_h_r_10 sp4_v_b_10 (8 13) routing sp4_v_t_42 sp4_v_b_10 (8 14) routing sp4_h_r_10 sp4_h_l_47 (8 14) routing sp4_h_r_2 sp4_h_l_47 (8 14) routing sp4_v_t_41 sp4_h_l_47 (8 14) routing sp4_v_t_47 sp4_h_l_47 (8 15) routing sp4_h_l_47 sp4_v_t_47 (8 15) routing sp4_h_r_10 sp4_v_t_47 (8 15) routing sp4_h_r_4 sp4_v_t_47 (8 15) routing sp4_v_b_7 sp4_v_t_47 (8 2) routing sp4_h_r_1 sp4_h_l_36 (8 2) routing sp4_h_r_5 sp4_h_l_36 (8 2) routing sp4_v_t_36 sp4_h_l_36 (8 2) routing sp4_v_t_42 sp4_h_l_36 (8 3) routing sp4_h_l_36 sp4_v_t_36 (8 3) routing sp4_h_r_1 sp4_v_t_36 (8 3) routing sp4_h_r_7 sp4_v_t_36 (8 3) routing sp4_v_b_10 sp4_v_t_36 (8 4) routing sp4_h_l_41 sp4_h_r_4 (8 4) routing sp4_h_l_45 sp4_h_r_4 (8 4) routing sp4_v_b_10 sp4_h_r_4 (8 4) routing sp4_v_b_4 sp4_h_r_4 (8 5) routing sp4_h_l_41 sp4_v_b_4 (8 5) routing sp4_h_l_47 sp4_v_b_4 (8 5) routing sp4_h_r_4 sp4_v_b_4 (8 5) routing sp4_v_t_36 sp4_v_b_4 (8 6) routing sp4_h_r_4 sp4_h_l_41 (8 6) routing sp4_h_r_8 sp4_h_l_41 (8 6) routing sp4_v_t_41 sp4_h_l_41 (8 6) routing sp4_v_t_47 sp4_h_l_41 (8 7) routing sp4_h_l_41 sp4_v_t_41 (8 7) routing sp4_h_r_10 sp4_v_t_41 (8 7) routing sp4_h_r_4 sp4_v_t_41 (8 7) routing sp4_v_b_1 sp4_v_t_41 (8 8) routing sp4_h_l_42 sp4_h_r_7 (8 8) routing sp4_h_l_46 sp4_h_r_7 (8 8) routing sp4_v_b_1 sp4_h_r_7 (8 8) routing sp4_v_b_7 sp4_h_r_7 (8 9) routing sp4_h_l_36 sp4_v_b_7 (8 9) routing sp4_h_l_42 sp4_v_b_7 (8 9) routing sp4_h_r_7 sp4_v_b_7 (8 9) routing sp4_v_t_41 sp4_v_b_7 (9 0) routing sp4_h_l_47 sp4_h_r_1 (9 0) routing sp4_v_b_1 sp4_h_r_1 (9 0) routing sp4_v_b_7 sp4_h_r_1 (9 0) routing sp4_v_t_36 sp4_h_r_1 (9 1) routing sp4_h_l_36 sp4_v_b_1 (9 1) routing sp4_h_l_42 sp4_v_b_1 (9 1) routing sp4_v_t_36 sp4_v_b_1 (9 1) routing sp4_v_t_40 sp4_v_b_1 (9 10) routing sp4_h_r_4 sp4_h_l_42 (9 10) routing sp4_v_b_7 sp4_h_l_42 (9 10) routing sp4_v_t_36 sp4_h_l_42 (9 10) routing sp4_v_t_42 sp4_h_l_42 (9 11) routing sp4_h_r_1 sp4_v_t_42 (9 11) routing sp4_h_r_7 sp4_v_t_42 (9 11) routing sp4_v_b_11 sp4_v_t_42 (9 11) routing sp4_v_b_7 sp4_v_t_42 (9 12) routing sp4_h_l_42 sp4_h_r_10 (9 12) routing sp4_v_b_10 sp4_h_r_10 (9 12) routing sp4_v_b_4 sp4_h_r_10 (9 12) routing sp4_v_t_47 sp4_h_r_10 (9 13) routing sp4_h_l_41 sp4_v_b_10 (9 13) routing sp4_h_l_47 sp4_v_b_10 (9 13) routing sp4_v_t_39 sp4_v_b_10 (9 13) routing sp4_v_t_47 sp4_v_b_10 (9 14) routing sp4_h_r_7 sp4_h_l_47 (9 14) routing sp4_v_b_10 sp4_h_l_47 (9 14) routing sp4_v_t_41 sp4_h_l_47 (9 14) routing sp4_v_t_47 sp4_h_l_47 (9 15) routing sp4_h_r_10 sp4_v_t_47 (9 15) routing sp4_h_r_4 sp4_v_t_47 (9 15) routing sp4_v_b_10 sp4_v_t_47 (9 15) routing sp4_v_b_2 sp4_v_t_47 (9 2) routing sp4_h_r_10 sp4_h_l_36 (9 2) routing sp4_v_b_1 sp4_h_l_36 (9 2) routing sp4_v_t_36 sp4_h_l_36 (9 2) routing sp4_v_t_42 sp4_h_l_36 (9 3) routing sp4_h_r_1 sp4_v_t_36 (9 3) routing sp4_h_r_7 sp4_v_t_36 (9 3) routing sp4_v_b_1 sp4_v_t_36 (9 3) routing sp4_v_b_5 sp4_v_t_36 (9 4) routing sp4_h_l_36 sp4_h_r_4 (9 4) routing sp4_v_b_10 sp4_h_r_4 (9 4) routing sp4_v_b_4 sp4_h_r_4 (9 4) routing sp4_v_t_41 sp4_h_r_4 (9 5) routing sp4_h_l_41 sp4_v_b_4 (9 5) routing sp4_h_l_47 sp4_v_b_4 (9 5) routing sp4_v_t_41 sp4_v_b_4 (9 5) routing sp4_v_t_45 sp4_v_b_4 (9 6) routing sp4_h_r_1 sp4_h_l_41 (9 6) routing sp4_v_b_4 sp4_h_l_41 (9 6) routing sp4_v_t_41 sp4_h_l_41 (9 6) routing sp4_v_t_47 sp4_h_l_41 (9 7) routing sp4_h_r_10 sp4_v_t_41 (9 7) routing sp4_h_r_4 sp4_v_t_41 (9 7) routing sp4_v_b_4 sp4_v_t_41 (9 7) routing sp4_v_b_8 sp4_v_t_41 (9 8) routing sp4_h_l_41 sp4_h_r_7 (9 8) routing sp4_v_b_1 sp4_h_r_7 (9 8) routing sp4_v_b_7 sp4_h_r_7 (9 8) routing sp4_v_t_42 sp4_h_r_7 (9 9) routing sp4_h_l_36 sp4_v_b_7 (9 9) routing sp4_h_l_42 sp4_v_b_7 (9 9) routing sp4_v_t_42 sp4_v_b_7 (9 9) routing sp4_v_t_46 sp4_v_b_7 fpga-icestorm-0~20160913git266e758/icefuzz/cached_ramb_8k.txt000066400000000000000000005573161276746530600234450ustar00rootroot00000000000000(0 0) Negative Clock bit (0 10) routing glb_netwk_2 glb2local_2 (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 (0 10) routing glb_netwk_7 glb2local_2 (0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 (0 11) routing glb_netwk_7 glb2local_2 (0 12) routing glb_netwk_2 glb2local_3 (0 12) routing glb_netwk_3 glb2local_3 (0 12) routing glb_netwk_6 glb2local_3 (0 12) routing glb_netwk_7 glb2local_3 (0 13) routing glb_netwk_1 glb2local_3 (0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 (0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/RE (0 14) routing glb_netwk_6 wire_bram/ram/RE (0 14) routing lc_trk_g2_4 wire_bram/ram/RE (0 14) routing lc_trk_g3_5 wire_bram/ram/RE (0 15) routing glb_netwk_2 wire_bram/ram/RE (0 15) routing glb_netwk_6 wire_bram/ram/RE (0 15) routing lc_trk_g1_5 wire_bram/ram/RE (0 15) routing lc_trk_g3_5 wire_bram/ram/RE (0 2) routing glb_netwk_2 wire_bram/ram/RCLK (0 2) routing glb_netwk_3 wire_bram/ram/RCLK (0 2) routing glb_netwk_6 wire_bram/ram/RCLK (0 2) routing glb_netwk_7 wire_bram/ram/RCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/RCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/RCLK (0 3) routing glb_netwk_1 wire_bram/ram/RCLK (0 3) routing glb_netwk_3 wire_bram/ram/RCLK (0 3) routing glb_netwk_5 wire_bram/ram/RCLK (0 3) routing glb_netwk_7 wire_bram/ram/RCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/RCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/RCLK (0 4) routing glb_netwk_5 wire_bram/ram/RCLKE (0 4) routing glb_netwk_7 wire_bram/ram/RCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/RCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/RCLKE (0 5) routing glb_netwk_3 wire_bram/ram/RCLKE (0 5) routing glb_netwk_7 wire_bram/ram/RCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE (0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 (0 6) routing glb_netwk_6 glb2local_0 (0 6) routing glb_netwk_7 glb2local_0 (0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 (0 7) routing glb_netwk_7 glb2local_0 (0 8) routing glb_netwk_2 glb2local_1 (0 8) routing glb_netwk_3 glb2local_1 (0 8) routing glb_netwk_6 glb2local_1 (0 8) routing glb_netwk_7 glb2local_1 (0 9) routing glb_netwk_1 glb2local_1 (0 9) routing glb_netwk_3 glb2local_1 (0 9) routing glb_netwk_5 glb2local_1 (0 9) routing glb_netwk_7 glb2local_1 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 (1 11) routing glb_netwk_7 glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 (1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 (1 13) routing glb_netwk_6 glb2local_3 (1 13) routing glb_netwk_7 glb2local_3 (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE (1 15) routing lc_trk_g0_4 wire_bram/ram/RE (1 15) routing lc_trk_g1_5 wire_bram/ram/RE (1 15) routing lc_trk_g2_4 wire_bram/ram/RE (1 15) routing lc_trk_g3_5 wire_bram/ram/RE (1 2) routing glb_netwk_4 wire_bram/ram/RCLK (1 2) routing glb_netwk_5 wire_bram/ram/RCLK (1 2) routing glb_netwk_6 wire_bram/ram/RCLK (1 2) routing glb_netwk_7 wire_bram/ram/RCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/RCLKE (1 5) routing lc_trk_g0_2 wire_bram/ram/RCLKE (1 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/RCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 (1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 (1 7) routing glb_netwk_6 glb2local_0 (1 7) routing glb_netwk_7 glb2local_0 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 (1 9) routing glb_netwk_4 glb2local_1 (1 9) routing glb_netwk_5 glb2local_1 (1 9) routing glb_netwk_6 glb2local_1 (1 9) routing glb_netwk_7 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 (10 0) routing sp4_v_t_45 sp4_h_r_1 (10 1) routing sp4_h_l_42 sp4_v_b_1 (10 1) routing sp4_h_r_8 sp4_v_b_1 (10 1) routing sp4_v_t_40 sp4_v_b_1 (10 1) routing sp4_v_t_47 sp4_v_b_1 (10 10) routing sp4_h_r_11 sp4_h_l_42 (10 10) routing sp4_h_r_4 sp4_h_l_42 (10 10) routing sp4_v_b_2 sp4_h_l_42 (10 10) routing sp4_v_t_36 sp4_h_l_42 (10 11) routing sp4_h_l_39 sp4_v_t_42 (10 11) routing sp4_h_r_1 sp4_v_t_42 (10 11) routing sp4_v_b_11 sp4_v_t_42 (10 11) routing sp4_v_b_4 sp4_v_t_42 (10 12) routing sp4_h_l_39 sp4_h_r_10 (10 12) routing sp4_h_l_42 sp4_h_r_10 (10 12) routing sp4_v_b_4 sp4_h_r_10 (10 12) routing sp4_v_t_40 sp4_h_r_10 (10 13) routing sp4_h_l_41 sp4_v_b_10 (10 13) routing sp4_h_r_5 sp4_v_b_10 (10 13) routing sp4_v_t_39 sp4_v_b_10 (10 13) routing sp4_v_t_42 sp4_v_b_10 (10 14) routing sp4_h_r_2 sp4_h_l_47 (10 14) routing sp4_h_r_7 sp4_h_l_47 (10 14) routing sp4_v_b_5 sp4_h_l_47 (10 14) routing sp4_v_t_41 sp4_h_l_47 (10 15) routing sp4_h_l_40 sp4_v_t_47 (10 15) routing sp4_h_r_4 sp4_v_t_47 (10 15) routing sp4_v_b_2 sp4_v_t_47 (10 15) routing sp4_v_b_7 sp4_v_t_47 (10 2) routing sp4_h_r_10 sp4_h_l_36 (10 2) routing sp4_h_r_5 sp4_h_l_36 (10 2) routing sp4_v_b_8 sp4_h_l_36 (10 2) routing sp4_v_t_42 sp4_h_l_36 (10 3) routing sp4_h_l_45 sp4_v_t_36 (10 3) routing sp4_h_r_7 sp4_v_t_36 (10 3) routing sp4_v_b_10 sp4_v_t_36 (10 3) routing sp4_v_b_5 sp4_v_t_36 (10 4) routing sp4_h_l_36 sp4_h_r_4 (10 4) routing sp4_h_l_45 sp4_h_r_4 (10 4) routing sp4_v_b_10 sp4_h_r_4 (10 4) routing sp4_v_t_46 sp4_h_r_4 (10 5) routing sp4_h_l_47 sp4_v_b_4 (10 5) routing sp4_h_r_11 sp4_v_b_4 (10 5) routing sp4_v_t_36 sp4_v_b_4 (10 5) routing sp4_v_t_45 sp4_v_b_4 (10 6) routing sp4_h_r_1 sp4_h_l_41 (10 6) routing sp4_h_r_8 sp4_h_l_41 (10 6) routing sp4_v_b_11 sp4_h_l_41 (10 6) routing sp4_v_t_47 sp4_h_l_41 (10 7) routing sp4_h_l_46 sp4_v_t_41 (10 7) routing sp4_h_r_10 sp4_v_t_41 (10 7) routing sp4_v_b_1 sp4_v_t_41 (10 7) routing sp4_v_b_8 sp4_v_t_41 (10 8) routing sp4_h_l_41 sp4_h_r_7 (10 8) routing sp4_h_l_46 sp4_h_r_7 (10 8) routing sp4_v_b_1 sp4_h_r_7 (10 8) routing sp4_v_t_39 sp4_h_r_7 (10 9) routing sp4_h_l_36 sp4_v_b_7 (10 9) routing sp4_h_r_2 sp4_v_b_7 (10 9) routing sp4_v_t_41 sp4_v_b_7 (10 9) routing sp4_v_t_46 sp4_v_b_7 (11 0) routing sp4_h_l_45 sp4_v_b_2 (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 (11 1) routing sp4_h_l_39 sp4_h_r_2 (11 1) routing sp4_h_l_43 sp4_h_r_2 (11 1) routing sp4_v_b_2 sp4_h_r_2 (11 1) routing sp4_v_b_8 sp4_h_r_2 (11 10) routing sp4_h_l_38 sp4_v_t_45 (11 10) routing sp4_h_r_2 sp4_v_t_45 (11 10) routing sp4_v_b_0 sp4_v_t_45 (11 10) routing sp4_v_b_5 sp4_v_t_45 (11 11) routing sp4_h_r_0 sp4_h_l_45 (11 11) routing sp4_h_r_8 sp4_h_l_45 (11 11) routing sp4_v_t_39 sp4_h_l_45 (11 11) routing sp4_v_t_45 sp4_h_l_45 (11 12) routing sp4_h_l_40 sp4_v_b_11 (11 12) routing sp4_h_r_6 sp4_v_b_11 (11 12) routing sp4_v_t_38 sp4_v_b_11 (11 12) routing sp4_v_t_45 sp4_v_b_11 (11 13) routing sp4_h_l_38 sp4_h_r_11 (11 13) routing sp4_h_l_46 sp4_h_r_11 (11 13) routing sp4_v_b_11 sp4_h_r_11 (11 13) routing sp4_v_b_5 sp4_h_r_11 (11 14) routing sp4_h_l_43 sp4_v_t_46 (11 14) routing sp4_h_r_5 sp4_v_t_46 (11 14) routing sp4_v_b_3 sp4_v_t_46 (11 14) routing sp4_v_b_8 sp4_v_t_46 (11 15) routing sp4_h_r_11 sp4_h_l_46 (11 15) routing sp4_h_r_3 sp4_h_l_46 (11 15) routing sp4_v_t_40 sp4_h_l_46 (11 15) routing sp4_v_t_46 sp4_h_l_46 (11 2) routing sp4_h_l_44 sp4_v_t_39 (11 2) routing sp4_h_r_8 sp4_v_t_39 (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 (11 3) routing sp4_h_r_2 sp4_h_l_39 (11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 (11 4) routing sp4_h_r_0 sp4_v_b_5 (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 (11 5) routing sp4_h_l_40 sp4_h_r_5 (11 5) routing sp4_h_l_44 sp4_h_r_5 (11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 (11 6) routing sp4_h_r_11 sp4_v_t_40 (11 6) routing sp4_v_b_2 sp4_v_t_40 (11 6) routing sp4_v_b_9 sp4_v_t_40 (11 7) routing sp4_h_r_5 sp4_h_l_40 (11 7) routing sp4_h_r_9 sp4_h_l_40 (11 7) routing sp4_v_t_40 sp4_h_l_40 (11 7) routing sp4_v_t_46 sp4_h_l_40 (11 8) routing sp4_h_l_39 sp4_v_b_8 (11 8) routing sp4_h_r_3 sp4_v_b_8 (11 8) routing sp4_v_t_37 sp4_v_b_8 (11 8) routing sp4_v_t_40 sp4_v_b_8 (11 9) routing sp4_h_l_37 sp4_h_r_8 (11 9) routing sp4_h_l_45 sp4_h_r_8 (11 9) routing sp4_v_b_2 sp4_h_r_8 (11 9) routing sp4_v_b_8 sp4_h_r_8 (12 0) routing sp4_h_l_46 sp4_h_r_2 (12 0) routing sp4_v_b_2 sp4_h_r_2 (12 0) routing sp4_v_b_8 sp4_h_r_2 (12 0) routing sp4_v_t_39 sp4_h_r_2 (12 1) routing sp4_h_l_39 sp4_v_b_2 (12 1) routing sp4_h_l_45 sp4_v_b_2 (12 1) routing sp4_h_r_2 sp4_v_b_2 (12 1) routing sp4_v_t_46 sp4_v_b_2 (12 10) routing sp4_h_r_5 sp4_h_l_45 (12 10) routing sp4_v_b_8 sp4_h_l_45 (12 10) routing sp4_v_t_39 sp4_h_l_45 (12 10) routing sp4_v_t_45 sp4_h_l_45 (12 11) routing sp4_h_l_45 sp4_v_t_45 (12 11) routing sp4_h_r_2 sp4_v_t_45 (12 11) routing sp4_h_r_8 sp4_v_t_45 (12 11) routing sp4_v_b_5 sp4_v_t_45 (12 12) routing sp4_h_l_45 sp4_h_r_11 (12 12) routing sp4_v_b_11 sp4_h_r_11 (12 12) routing sp4_v_b_5 sp4_h_r_11 (12 12) routing sp4_v_t_46 sp4_h_r_11 (12 13) routing sp4_h_l_40 sp4_v_b_11 (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 (12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 (12 14) routing sp4_v_t_46 sp4_h_l_46 (12 15) routing sp4_h_l_46 sp4_v_t_46 (12 15) routing sp4_h_r_11 sp4_v_t_46 (12 15) routing sp4_h_r_5 sp4_v_t_46 (12 15) routing sp4_v_b_8 sp4_v_t_46 (12 2) routing sp4_h_r_11 sp4_h_l_39 (12 2) routing sp4_v_b_2 sp4_h_l_39 (12 2) routing sp4_v_t_39 sp4_h_l_39 (12 2) routing sp4_v_t_45 sp4_h_l_39 (12 3) routing sp4_h_l_39 sp4_v_t_39 (12 3) routing sp4_h_r_2 sp4_v_t_39 (12 3) routing sp4_h_r_8 sp4_v_t_39 (12 3) routing sp4_v_b_11 sp4_v_t_39 (12 4) routing sp4_h_l_39 sp4_h_r_5 (12 4) routing sp4_v_b_11 sp4_h_r_5 (12 4) routing sp4_v_b_5 sp4_h_r_5 (12 4) routing sp4_v_t_40 sp4_h_r_5 (12 5) routing sp4_h_l_40 sp4_v_b_5 (12 5) routing sp4_h_l_46 sp4_v_b_5 (12 5) routing sp4_h_r_5 sp4_v_b_5 (12 5) routing sp4_v_t_39 sp4_v_b_5 (12 6) routing sp4_h_r_2 sp4_h_l_40 (12 6) routing sp4_v_b_5 sp4_h_l_40 (12 6) routing sp4_v_t_40 sp4_h_l_40 (12 6) routing sp4_v_t_46 sp4_h_l_40 (12 7) routing sp4_h_l_40 sp4_v_t_40 (12 7) routing sp4_h_r_11 sp4_v_t_40 (12 7) routing sp4_h_r_5 sp4_v_t_40 (12 7) routing sp4_v_b_2 sp4_v_t_40 (12 8) routing sp4_h_l_40 sp4_h_r_8 (12 8) routing sp4_v_b_2 sp4_h_r_8 (12 8) routing sp4_v_b_8 sp4_h_r_8 (12 8) routing sp4_v_t_45 sp4_h_r_8 (12 9) routing sp4_h_l_39 sp4_v_b_8 (12 9) routing sp4_h_l_45 sp4_v_b_8 (12 9) routing sp4_h_r_8 sp4_v_b_8 (12 9) routing sp4_v_t_40 sp4_v_b_8 (13 0) routing sp4_h_l_39 sp4_v_b_2 (13 0) routing sp4_h_l_45 sp4_v_b_2 (13 0) routing sp4_v_t_39 sp4_v_b_2 (13 0) routing sp4_v_t_43 sp4_v_b_2 (13 1) routing sp4_h_l_43 sp4_h_r_2 (13 1) routing sp4_h_l_46 sp4_h_r_2 (13 1) routing sp4_v_b_8 sp4_h_r_2 (13 1) routing sp4_v_t_44 sp4_h_r_2 (13 10) routing sp4_h_r_2 sp4_v_t_45 (13 10) routing sp4_h_r_8 sp4_v_t_45 (13 10) routing sp4_v_b_0 sp4_v_t_45 (13 10) routing sp4_v_b_8 sp4_v_t_45 (13 11) routing sp4_h_r_0 sp4_h_l_45 (13 11) routing sp4_h_r_5 sp4_h_l_45 (13 11) routing sp4_v_b_3 sp4_h_l_45 (13 11) routing sp4_v_t_39 sp4_h_l_45 (13 12) routing sp4_h_l_40 sp4_v_b_11 (13 12) routing sp4_h_l_46 sp4_v_b_11 (13 12) routing sp4_v_t_38 sp4_v_b_11 (13 12) routing sp4_v_t_46 sp4_v_b_11 (13 13) routing sp4_h_l_38 sp4_h_r_11 (13 13) routing sp4_h_l_45 sp4_h_r_11 (13 13) routing sp4_v_b_5 sp4_h_r_11 (13 13) routing sp4_v_t_43 sp4_h_r_11 (13 14) routing sp4_h_r_11 sp4_v_t_46 (13 14) routing sp4_h_r_5 sp4_v_t_46 (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 (13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 (13 2) routing sp4_h_r_8 sp4_v_t_39 (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 (13 3) routing sp4_h_r_11 sp4_h_l_39 (13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 (13 4) routing sp4_h_l_46 sp4_v_b_5 (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 (13 5) routing sp4_h_l_39 sp4_h_r_5 (13 5) routing sp4_h_l_44 sp4_h_r_5 (13 5) routing sp4_v_b_11 sp4_h_r_5 (13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 (13 6) routing sp4_h_r_5 sp4_v_t_40 (13 6) routing sp4_v_b_5 sp4_v_t_40 (13 6) routing sp4_v_b_9 sp4_v_t_40 (13 7) routing sp4_h_r_2 sp4_h_l_40 (13 7) routing sp4_h_r_9 sp4_h_l_40 (13 7) routing sp4_v_b_0 sp4_h_l_40 (13 7) routing sp4_v_t_46 sp4_h_l_40 (13 8) routing sp4_h_l_39 sp4_v_b_8 (13 8) routing sp4_h_l_45 sp4_v_b_8 (13 8) routing sp4_v_t_37 sp4_v_b_8 (13 8) routing sp4_v_t_45 sp4_v_b_8 (13 9) routing sp4_h_l_37 sp4_h_r_8 (13 9) routing sp4_h_l_40 sp4_h_r_8 (13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 (14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_r_16 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 (14 1) routing sp12_h_l_15 lc_trk_g0_0 (14 1) routing sp12_h_r_0 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_h_r_16 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 (14 10) routing rgt_op_4 lc_trk_g2_4 (14 10) routing sp12_v_b_4 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 (14 10) routing sp4_v_b_28 lc_trk_g2_4 (14 10) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing bnl_op_4 lc_trk_g2_4 (14 11) routing sp12_v_b_20 lc_trk_g2_4 (14 11) routing sp12_v_b_4 lc_trk_g2_4 (14 11) routing sp4_h_r_28 lc_trk_g2_4 (14 11) routing sp4_h_r_44 lc_trk_g2_4 (14 11) routing sp4_r_v_b_36 lc_trk_g2_4 (14 11) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing tnl_op_4 lc_trk_g2_4 (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 (14 12) routing sp12_v_b_0 lc_trk_g3_0 (14 12) routing sp4_h_r_32 lc_trk_g3_0 (14 12) routing sp4_h_r_40 lc_trk_g3_0 (14 12) routing sp4_v_b_32 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 (14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 (14 13) routing sp4_h_r_24 lc_trk_g3_0 (14 13) routing sp4_h_r_40 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_b_32 lc_trk_g3_0 (14 13) routing tnl_op_0 lc_trk_g3_0 (14 14) routing bnl_op_4 lc_trk_g3_4 (14 14) routing rgt_op_4 lc_trk_g3_4 (14 14) routing sp12_v_b_4 lc_trk_g3_4 (14 14) routing sp4_h_r_36 lc_trk_g3_4 (14 14) routing sp4_h_r_44 lc_trk_g3_4 (14 14) routing sp4_v_b_28 lc_trk_g3_4 (14 14) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing bnl_op_4 lc_trk_g3_4 (14 15) routing sp12_v_b_20 lc_trk_g3_4 (14 15) routing sp12_v_b_4 lc_trk_g3_4 (14 15) routing sp4_h_r_28 lc_trk_g3_4 (14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing tnl_op_4 lc_trk_g3_4 (14 2) routing bnr_op_4 lc_trk_g0_4 (14 2) routing lft_op_4 lc_trk_g0_4 (14 2) routing sp12_h_l_3 lc_trk_g0_4 (14 2) routing sp4_h_l_1 lc_trk_g0_4 (14 2) routing sp4_h_l_9 lc_trk_g0_4 (14 2) routing sp4_v_b_12 lc_trk_g0_4 (14 2) routing sp4_v_b_4 lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 (14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_l_9 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 (14 3) routing sp4_v_b_12 lc_trk_g0_4 (14 4) routing bnr_op_0 lc_trk_g1_0 (14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_r_16 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 (14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_l_15 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_h_r_16 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 (14 6) routing bnr_op_4 lc_trk_g1_4 (14 6) routing lft_op_4 lc_trk_g1_4 (14 6) routing sp12_h_l_3 lc_trk_g1_4 (14 6) routing sp4_h_l_1 lc_trk_g1_4 (14 6) routing sp4_h_l_9 lc_trk_g1_4 (14 6) routing sp4_v_b_12 lc_trk_g1_4 (14 6) routing sp4_v_b_4 lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_l_9 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_b_12 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 (14 8) routing rgt_op_0 lc_trk_g2_0 (14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_r_32 lc_trk_g2_0 (14 8) routing sp4_h_r_40 lc_trk_g2_0 (14 8) routing sp4_v_b_32 lc_trk_g2_0 (14 8) routing sp4_v_t_13 lc_trk_g2_0 (14 9) routing bnl_op_0 lc_trk_g2_0 (14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 (14 9) routing sp4_h_r_24 lc_trk_g2_0 (14 9) routing sp4_h_r_40 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_b_32 lc_trk_g2_0 (14 9) routing tnl_op_0 lc_trk_g2_0 (15 0) routing lft_op_1 lc_trk_g0_1 (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_t_4 lc_trk_g0_1 (15 1) routing bot_op_0 lc_trk_g0_0 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_16 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 (15 1) routing sp4_v_b_16 lc_trk_g0_0 (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 (15 10) routing sp4_h_r_29 lc_trk_g2_5 (15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_b_4 lc_trk_g2_4 (15 11) routing sp4_h_r_28 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 (15 11) routing sp4_h_r_44 lc_trk_g2_4 (15 11) routing sp4_v_b_44 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 (15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_h_r_33 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 (15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 (15 13) routing sp4_h_r_24 lc_trk_g3_0 (15 13) routing sp4_h_r_32 lc_trk_g3_0 (15 13) routing sp4_h_r_40 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 (15 13) routing tnr_op_0 lc_trk_g3_0 (15 14) routing rgt_op_5 lc_trk_g3_5 (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_r_29 lc_trk_g3_5 (15 14) routing sp4_h_r_37 lc_trk_g3_5 (15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_b_45 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 (15 15) routing sp12_v_b_4 lc_trk_g3_4 (15 15) routing sp4_h_r_28 lc_trk_g3_4 (15 15) routing sp4_h_r_36 lc_trk_g3_4 (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_b_44 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 (15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing lft_op_5 lc_trk_g0_5 (15 2) routing sp12_h_l_2 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_21 lc_trk_g0_5 (15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 (15 3) routing bot_op_4 lc_trk_g0_4 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_l_1 lc_trk_g0_4 (15 3) routing sp4_h_l_9 lc_trk_g0_4 (15 3) routing sp4_h_r_4 lc_trk_g0_4 (15 3) routing sp4_v_b_20 lc_trk_g0_4 (15 4) routing lft_op_1 lc_trk_g1_1 (15 4) routing sp12_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_17 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_t_4 lc_trk_g1_1 (15 5) routing bot_op_0 lc_trk_g1_0 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_16 lc_trk_g1_0 (15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_b_16 lc_trk_g1_0 (15 6) routing lft_op_5 lc_trk_g1_5 (15 6) routing sp12_h_l_2 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_21 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 (15 7) routing bot_op_4 lc_trk_g1_4 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_l_1 lc_trk_g1_4 (15 7) routing sp4_h_l_9 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_h_r_33 lc_trk_g2_1 (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_r_24 lc_trk_g2_0 (15 9) routing sp4_h_r_32 lc_trk_g2_0 (15 9) routing sp4_h_r_40 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 (16 0) routing sp12_h_l_14 lc_trk_g0_1 (16 0) routing sp12_h_r_9 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 (16 0) routing sp4_v_t_4 lc_trk_g0_1 (16 1) routing sp12_h_l_15 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 (16 1) routing sp4_h_r_16 lc_trk_g0_0 (16 1) routing sp4_h_r_8 lc_trk_g0_0 (16 1) routing sp4_v_b_0 lc_trk_g0_0 (16 1) routing sp4_v_b_16 lc_trk_g0_0 (16 1) routing sp4_v_b_8 lc_trk_g0_0 (16 10) routing sp12_v_b_13 lc_trk_g2_5 (16 10) routing sp12_v_t_18 lc_trk_g2_5 (16 10) routing sp4_h_r_29 lc_trk_g2_5 (16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 (16 10) routing sp4_v_b_45 lc_trk_g2_5 (16 10) routing sp4_v_t_24 lc_trk_g2_5 (16 11) routing sp12_v_b_20 lc_trk_g2_4 (16 11) routing sp12_v_t_11 lc_trk_g2_4 (16 11) routing sp4_h_r_28 lc_trk_g2_4 (16 11) routing sp4_h_r_36 lc_trk_g2_4 (16 11) routing sp4_h_r_44 lc_trk_g2_4 (16 11) routing sp4_v_b_28 lc_trk_g2_4 (16 11) routing sp4_v_b_44 lc_trk_g2_4 (16 11) routing sp4_v_t_25 lc_trk_g2_4 (16 12) routing sp12_v_b_9 lc_trk_g3_1 (16 12) routing sp12_v_t_14 lc_trk_g3_1 (16 12) routing sp4_h_l_28 lc_trk_g3_1 (16 12) routing sp4_h_r_25 lc_trk_g3_1 (16 12) routing sp4_h_r_33 lc_trk_g3_1 (16 12) routing sp4_v_b_25 lc_trk_g3_1 (16 12) routing sp4_v_b_41 lc_trk_g3_1 (16 12) routing sp4_v_t_20 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 (16 13) routing sp4_h_r_24 lc_trk_g3_0 (16 13) routing sp4_h_r_32 lc_trk_g3_0 (16 13) routing sp4_h_r_40 lc_trk_g3_0 (16 13) routing sp4_v_b_32 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 (16 13) routing sp4_v_t_13 lc_trk_g3_0 (16 14) routing sp12_v_b_13 lc_trk_g3_5 (16 14) routing sp12_v_t_18 lc_trk_g3_5 (16 14) routing sp4_h_r_29 lc_trk_g3_5 (16 14) routing sp4_h_r_37 lc_trk_g3_5 (16 14) routing sp4_h_r_45 lc_trk_g3_5 (16 14) routing sp4_v_b_29 lc_trk_g3_5 (16 14) routing sp4_v_b_45 lc_trk_g3_5 (16 14) routing sp4_v_t_24 lc_trk_g3_5 (16 15) routing sp12_v_b_20 lc_trk_g3_4 (16 15) routing sp12_v_t_11 lc_trk_g3_4 (16 15) routing sp4_h_r_28 lc_trk_g3_4 (16 15) routing sp4_h_r_36 lc_trk_g3_4 (16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_b_44 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 2) routing sp12_h_l_10 lc_trk_g0_5 (16 2) routing sp12_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_5 lc_trk_g0_5 (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 (16 3) routing sp12_h_r_12 lc_trk_g0_4 (16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_l_1 lc_trk_g0_4 (16 3) routing sp4_h_l_9 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 (16 3) routing sp4_v_b_12 lc_trk_g0_4 (16 3) routing sp4_v_b_20 lc_trk_g0_4 (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 4) routing sp12_h_l_14 lc_trk_g1_1 (16 4) routing sp12_h_r_9 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 4) routing sp4_v_t_4 lc_trk_g1_1 (16 5) routing sp12_h_l_15 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_16 lc_trk_g1_0 (16 5) routing sp4_h_r_8 lc_trk_g1_0 (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 (16 6) routing sp12_h_l_10 lc_trk_g1_5 (16 6) routing sp12_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 (16 6) routing sp4_v_b_13 lc_trk_g1_5 (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 6) routing sp4_v_t_8 lc_trk_g1_5 (16 7) routing sp12_h_r_12 lc_trk_g1_4 (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_l_1 lc_trk_g1_4 (16 7) routing sp4_h_l_9 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_12 lc_trk_g1_4 (16 7) routing sp4_v_b_20 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 (16 8) routing sp12_v_b_9 lc_trk_g2_1 (16 8) routing sp12_v_t_14 lc_trk_g2_1 (16 8) routing sp4_h_l_28 lc_trk_g2_1 (16 8) routing sp4_h_r_25 lc_trk_g2_1 (16 8) routing sp4_h_r_33 lc_trk_g2_1 (16 8) routing sp4_v_b_25 lc_trk_g2_1 (16 8) routing sp4_v_b_41 lc_trk_g2_1 (16 8) routing sp4_v_t_20 lc_trk_g2_1 (16 9) routing sp12_v_b_16 lc_trk_g2_0 (16 9) routing sp12_v_t_7 lc_trk_g2_0 (16 9) routing sp4_h_r_24 lc_trk_g2_0 (16 9) routing sp4_h_r_32 lc_trk_g2_0 (16 9) routing sp4_h_r_40 lc_trk_g2_0 (16 9) routing sp4_v_b_32 lc_trk_g2_0 (16 9) routing sp4_v_b_40 lc_trk_g2_0 (16 9) routing sp4_v_t_13 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 (17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_r_17 lc_trk_g0_1 (18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_l_14 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 (18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_b_5 lc_trk_g2_5 (18 10) routing sp4_h_r_37 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_29 lc_trk_g2_5 (18 10) routing sp4_v_t_24 lc_trk_g2_5 (18 11) routing bnl_op_5 lc_trk_g2_5 (18 11) routing sp12_v_b_5 lc_trk_g2_5 (18 11) routing sp12_v_t_18 lc_trk_g2_5 (18 11) routing sp4_h_r_29 lc_trk_g2_5 (18 11) routing sp4_h_r_45 lc_trk_g2_5 (18 11) routing sp4_r_v_b_37 lc_trk_g2_5 (18 11) routing sp4_v_t_24 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 (18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 (18 12) routing sp4_h_l_28 lc_trk_g3_1 (18 12) routing sp4_h_r_33 lc_trk_g3_1 (18 12) routing sp4_v_b_25 lc_trk_g3_1 (18 12) routing sp4_v_t_20 lc_trk_g3_1 (18 13) routing bnl_op_1 lc_trk_g3_1 (18 13) routing sp12_v_b_1 lc_trk_g3_1 (18 13) routing sp12_v_t_14 lc_trk_g3_1 (18 13) routing sp4_h_l_28 lc_trk_g3_1 (18 13) routing sp4_h_r_25 lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 lc_trk_g3_1 (18 13) routing sp4_v_t_20 lc_trk_g3_1 (18 13) routing tnl_op_1 lc_trk_g3_1 (18 14) routing bnl_op_5 lc_trk_g3_5 (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 (18 14) routing sp4_h_r_37 lc_trk_g3_5 (18 14) routing sp4_h_r_45 lc_trk_g3_5 (18 14) routing sp4_v_b_29 lc_trk_g3_5 (18 14) routing sp4_v_t_24 lc_trk_g3_5 (18 15) routing bnl_op_5 lc_trk_g3_5 (18 15) routing sp12_v_b_5 lc_trk_g3_5 (18 15) routing sp12_v_t_18 lc_trk_g3_5 (18 15) routing sp4_h_r_29 lc_trk_g3_5 (18 15) routing sp4_h_r_45 lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 lc_trk_g3_5 (18 15) routing sp4_v_t_24 lc_trk_g3_5 (18 15) routing tnl_op_5 lc_trk_g3_5 (18 2) routing bnr_op_5 lc_trk_g0_5 (18 2) routing lft_op_5 lc_trk_g0_5 (18 2) routing sp12_h_l_2 lc_trk_g0_5 (18 2) routing sp4_h_r_13 lc_trk_g0_5 (18 2) routing sp4_h_r_21 lc_trk_g0_5 (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 (18 3) routing sp12_h_l_2 lc_trk_g0_5 (18 3) routing sp12_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 (18 3) routing sp4_v_b_13 lc_trk_g0_5 (18 4) routing bnr_op_1 lc_trk_g1_1 (18 4) routing lft_op_1 lc_trk_g1_1 (18 4) routing sp12_h_r_1 lc_trk_g1_1 (18 4) routing sp4_h_r_17 lc_trk_g1_1 (18 4) routing sp4_h_r_9 lc_trk_g1_1 (18 4) routing sp4_v_b_1 lc_trk_g1_1 (18 4) routing sp4_v_b_9 lc_trk_g1_1 (18 5) routing bnr_op_1 lc_trk_g1_1 (18 5) routing sp12_h_l_14 lc_trk_g1_1 (18 5) routing sp12_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_r_17 lc_trk_g1_1 (18 5) routing sp4_r_v_b_25 lc_trk_g1_1 (18 5) routing sp4_v_b_9 lc_trk_g1_1 (18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 (18 6) routing sp12_h_l_2 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_h_r_21 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 (18 7) routing sp12_h_l_2 lc_trk_g1_5 (18 7) routing sp12_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 (18 8) routing sp4_h_r_33 lc_trk_g2_1 (18 8) routing sp4_v_b_25 lc_trk_g2_1 (18 8) routing sp4_v_t_20 lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 (18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_t_14 lc_trk_g2_1 (18 9) routing sp4_h_l_28 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 (18 9) routing sp4_r_v_b_33 lc_trk_g2_1 (18 9) routing sp4_v_t_20 lc_trk_g2_1 (18 9) routing tnl_op_1 lc_trk_g2_1 (19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13 (19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 (19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_b_23 (19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11 (19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13 (19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1 (19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 (19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 (19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 (19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 (19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 (19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 (19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 (19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7 (19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 (19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 (2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/RCLK (2 3) routing lc_trk_g0_0 wire_bram/ram/RCLK (2 3) routing lc_trk_g1_1 wire_bram/ram/RCLK (2 3) routing lc_trk_g2_0 wire_bram/ram/RCLK (2 3) routing lc_trk_g3_1 wire_bram/ram/RCLK (2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_r_18 (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9 (21 0) routing bnr_op_3 lc_trk_g0_3 (21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_r_3 lc_trk_g0_3 (21 0) routing sp4_h_l_6 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 (21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp12_h_r_3 lc_trk_g0_3 (21 1) routing sp4_h_l_6 lc_trk_g0_3 (21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 (21 1) routing sp4_v_b_11 lc_trk_g0_3 (21 10) routing bnl_op_7 lc_trk_g2_7 (21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_t_4 lc_trk_g2_7 (21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_b_31 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing bnl_op_7 lc_trk_g2_7 (21 11) routing sp12_v_t_20 lc_trk_g2_7 (21 11) routing sp12_v_t_4 lc_trk_g2_7 (21 11) routing sp4_h_r_31 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_b_3 lc_trk_g3_3 (21 12) routing sp4_h_l_22 lc_trk_g3_3 (21 12) routing sp4_h_r_43 lc_trk_g3_3 (21 12) routing sp4_v_b_27 lc_trk_g3_3 (21 12) routing sp4_v_b_35 lc_trk_g3_3 (21 13) routing bnl_op_3 lc_trk_g3_3 (21 13) routing sp12_v_b_19 lc_trk_g3_3 (21 13) routing sp12_v_b_3 lc_trk_g3_3 (21 13) routing sp4_h_l_14 lc_trk_g3_3 (21 13) routing sp4_h_r_43 lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 lc_trk_g3_3 (21 13) routing sp4_v_b_35 lc_trk_g3_3 (21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_t_4 lc_trk_g3_7 (21 14) routing sp4_h_l_26 lc_trk_g3_7 (21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_b_31 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_t_20 lc_trk_g3_7 (21 15) routing sp12_v_t_4 lc_trk_g3_7 (21 15) routing sp4_h_r_31 lc_trk_g3_7 (21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 (21 2) routing sp12_h_r_7 lc_trk_g0_7 (21 2) routing sp4_h_r_15 lc_trk_g0_7 (21 2) routing sp4_h_r_23 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_20 lc_trk_g0_7 (21 3) routing sp12_h_r_7 lc_trk_g0_7 (21 3) routing sp4_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 (21 3) routing sp4_v_t_2 lc_trk_g0_7 (21 4) routing bnr_op_3 lc_trk_g1_3 (21 4) routing lft_op_3 lc_trk_g1_3 (21 4) routing sp12_h_r_3 lc_trk_g1_3 (21 4) routing sp4_h_l_6 lc_trk_g1_3 (21 4) routing sp4_h_r_11 lc_trk_g1_3 (21 4) routing sp4_v_b_11 lc_trk_g1_3 (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp12_h_r_3 lc_trk_g1_3 (21 5) routing sp4_h_l_6 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 (21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_r_7 lc_trk_g1_7 (21 6) routing sp4_h_r_15 lc_trk_g1_7 (21 6) routing sp4_h_r_23 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 (21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_20 lc_trk_g1_7 (21 7) routing sp12_h_r_7 lc_trk_g1_7 (21 7) routing sp4_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_b_3 lc_trk_g2_3 (21 8) routing sp4_h_l_22 lc_trk_g2_3 (21 8) routing sp4_h_r_43 lc_trk_g2_3 (21 8) routing sp4_v_b_27 lc_trk_g2_3 (21 8) routing sp4_v_b_35 lc_trk_g2_3 (21 9) routing bnl_op_3 lc_trk_g2_3 (21 9) routing sp12_v_b_19 lc_trk_g2_3 (21 9) routing sp12_v_b_3 lc_trk_g2_3 (21 9) routing sp4_h_l_14 lc_trk_g2_3 (21 9) routing sp4_h_r_43 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_b_35 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 (22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_34 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 (22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 lc_trk_g0_3 (23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_l_6 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 (23 0) routing sp4_v_t_6 lc_trk_g0_3 (23 1) routing sp12_h_l_17 lc_trk_g0_2 (23 1) routing sp12_h_l_9 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 (23 1) routing sp4_v_b_10 lc_trk_g0_2 (23 1) routing sp4_v_b_2 lc_trk_g0_2 (23 1) routing sp4_v_t_7 lc_trk_g0_2 (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp12_v_t_20 lc_trk_g2_7 (23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_31 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_31 lc_trk_g2_7 (23 10) routing sp4_v_t_26 lc_trk_g2_7 (23 10) routing sp4_v_t_34 lc_trk_g2_7 (23 11) routing sp12_v_b_14 lc_trk_g2_6 (23 11) routing sp12_v_b_22 lc_trk_g2_6 (23 11) routing sp4_h_l_19 lc_trk_g2_6 (23 11) routing sp4_h_l_27 lc_trk_g2_6 (23 11) routing sp4_h_r_46 lc_trk_g2_6 (23 11) routing sp4_v_b_46 lc_trk_g2_6 (23 11) routing sp4_v_t_19 lc_trk_g2_6 (23 11) routing sp4_v_t_27 lc_trk_g2_6 (23 12) routing sp12_v_b_19 lc_trk_g3_3 (23 12) routing sp12_v_t_8 lc_trk_g3_3 (23 12) routing sp4_h_l_14 lc_trk_g3_3 (23 12) routing sp4_h_l_22 lc_trk_g3_3 (23 12) routing sp4_h_r_43 lc_trk_g3_3 (23 12) routing sp4_v_b_27 lc_trk_g3_3 (23 12) routing sp4_v_b_35 lc_trk_g3_3 (23 12) routing sp4_v_b_43 lc_trk_g3_3 (23 13) routing sp12_v_b_10 lc_trk_g3_2 (23 13) routing sp12_v_b_18 lc_trk_g3_2 (23 13) routing sp4_h_l_15 lc_trk_g3_2 (23 13) routing sp4_h_r_34 lc_trk_g3_2 (23 13) routing sp4_h_r_42 lc_trk_g3_2 (23 13) routing sp4_v_b_34 lc_trk_g3_2 (23 13) routing sp4_v_t_15 lc_trk_g3_2 (23 13) routing sp4_v_t_31 lc_trk_g3_2 (23 14) routing sp12_v_t_12 lc_trk_g3_7 (23 14) routing sp12_v_t_20 lc_trk_g3_7 (23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_31 lc_trk_g3_7 (23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_31 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 14) routing sp4_v_t_34 lc_trk_g3_7 (23 15) routing sp12_v_b_14 lc_trk_g3_6 (23 15) routing sp12_v_b_22 lc_trk_g3_6 (23 15) routing sp4_h_l_19 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 (23 15) routing sp4_v_t_19 lc_trk_g3_6 (23 15) routing sp4_v_t_27 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 (23 2) routing sp12_h_l_20 lc_trk_g0_7 (23 2) routing sp4_h_r_15 lc_trk_g0_7 (23 2) routing sp4_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_23 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 (23 3) routing sp12_h_r_14 lc_trk_g0_6 (23 3) routing sp12_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_l_11 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 (23 3) routing sp4_h_r_6 lc_trk_g0_6 (23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 (23 3) routing sp4_v_t_11 lc_trk_g0_6 (23 4) routing sp12_h_l_16 lc_trk_g1_3 (23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_l_6 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 (23 4) routing sp4_v_b_11 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 4) routing sp4_v_t_6 lc_trk_g1_3 (23 5) routing sp12_h_l_17 lc_trk_g1_2 (23 5) routing sp12_h_l_9 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 (23 5) routing sp4_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 (23 6) routing sp12_h_l_12 lc_trk_g1_7 (23 6) routing sp12_h_l_20 lc_trk_g1_7 (23 6) routing sp4_h_r_15 lc_trk_g1_7 (23 6) routing sp4_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 (23 6) routing sp4_v_b_23 lc_trk_g1_7 (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 (23 7) routing sp12_h_r_14 lc_trk_g1_6 (23 7) routing sp12_h_r_22 lc_trk_g1_6 (23 7) routing sp4_h_l_11 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_14 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 7) routing sp4_v_t_11 lc_trk_g1_6 (23 8) routing sp12_v_b_19 lc_trk_g2_3 (23 8) routing sp12_v_t_8 lc_trk_g2_3 (23 8) routing sp4_h_l_14 lc_trk_g2_3 (23 8) routing sp4_h_l_22 lc_trk_g2_3 (23 8) routing sp4_h_r_43 lc_trk_g2_3 (23 8) routing sp4_v_b_27 lc_trk_g2_3 (23 8) routing sp4_v_b_35 lc_trk_g2_3 (23 8) routing sp4_v_b_43 lc_trk_g2_3 (23 9) routing sp12_v_b_10 lc_trk_g2_2 (23 9) routing sp12_v_b_18 lc_trk_g2_2 (23 9) routing sp4_h_l_15 lc_trk_g2_2 (23 9) routing sp4_h_r_34 lc_trk_g2_2 (23 9) routing sp4_h_r_42 lc_trk_g2_2 (23 9) routing sp4_v_b_34 lc_trk_g2_2 (23 9) routing sp4_v_t_15 lc_trk_g2_2 (23 9) routing sp4_v_t_31 lc_trk_g2_2 (24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_r_3 lc_trk_g0_3 (24 0) routing sp4_h_l_6 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_t_6 lc_trk_g0_3 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_l_1 lc_trk_g0_2 (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_18 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_t_7 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_t_4 lc_trk_g2_7 (24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_31 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_t_34 lc_trk_g2_7 (24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_t_5 lc_trk_g2_6 (24 11) routing sp4_h_l_19 lc_trk_g2_6 (24 11) routing sp4_h_l_27 lc_trk_g2_6 (24 11) routing sp4_h_r_46 lc_trk_g2_6 (24 11) routing sp4_v_b_46 lc_trk_g2_6 (24 11) routing tnl_op_6 lc_trk_g2_6 (24 11) routing tnr_op_6 lc_trk_g2_6 (24 12) routing rgt_op_3 lc_trk_g3_3 (24 12) routing sp12_v_b_3 lc_trk_g3_3 (24 12) routing sp4_h_l_14 lc_trk_g3_3 (24 12) routing sp4_h_l_22 lc_trk_g3_3 (24 12) routing sp4_h_r_43 lc_trk_g3_3 (24 12) routing sp4_v_b_43 lc_trk_g3_3 (24 12) routing tnl_op_3 lc_trk_g3_3 (24 12) routing tnr_op_3 lc_trk_g3_3 (24 13) routing rgt_op_2 lc_trk_g3_2 (24 13) routing sp12_v_t_1 lc_trk_g3_2 (24 13) routing sp4_h_l_15 lc_trk_g3_2 (24 13) routing sp4_h_r_34 lc_trk_g3_2 (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 (24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_t_4 lc_trk_g3_7 (24 14) routing sp4_h_l_26 lc_trk_g3_7 (24 14) routing sp4_h_r_31 lc_trk_g3_7 (24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_t_34 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 (24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_t_5 lc_trk_g3_6 (24 15) routing sp4_h_l_19 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 (24 2) routing sp12_h_r_7 lc_trk_g0_7 (24 2) routing sp4_h_r_15 lc_trk_g0_7 (24 2) routing sp4_h_r_23 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_b_23 lc_trk_g0_7 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_11 lc_trk_g0_6 (24 3) routing sp4_h_l_3 lc_trk_g0_6 (24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_t_11 lc_trk_g0_6 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_r_3 lc_trk_g1_3 (24 4) routing sp4_h_l_6 lc_trk_g1_3 (24 4) routing sp4_h_r_11 lc_trk_g1_3 (24 4) routing sp4_h_r_3 lc_trk_g1_3 (24 4) routing sp4_v_t_6 lc_trk_g1_3 (24 5) routing lft_op_2 lc_trk_g1_2 (24 5) routing sp12_h_l_1 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 (24 5) routing sp4_h_r_18 lc_trk_g1_2 (24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_t_7 lc_trk_g1_2 (24 6) routing lft_op_7 lc_trk_g1_7 (24 6) routing sp12_h_r_7 lc_trk_g1_7 (24 6) routing sp4_h_r_15 lc_trk_g1_7 (24 6) routing sp4_h_r_23 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 (24 6) routing sp4_v_b_23 lc_trk_g1_7 (24 7) routing lft_op_6 lc_trk_g1_6 (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_11 lc_trk_g1_6 (24 7) routing sp4_h_l_3 lc_trk_g1_6 (24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_t_11 lc_trk_g1_6 (24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_b_3 lc_trk_g2_3 (24 8) routing sp4_h_l_14 lc_trk_g2_3 (24 8) routing sp4_h_l_22 lc_trk_g2_3 (24 8) routing sp4_h_r_43 lc_trk_g2_3 (24 8) routing sp4_v_b_43 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 (24 8) routing tnr_op_3 lc_trk_g2_3 (24 9) routing rgt_op_2 lc_trk_g2_2 (24 9) routing sp12_v_t_1 lc_trk_g2_2 (24 9) routing sp4_h_l_15 lc_trk_g2_2 (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_l_1 lc_trk_g0_2 (25 0) routing sp4_h_r_10 lc_trk_g0_2 (25 0) routing sp4_h_r_18 lc_trk_g0_2 (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 (25 1) routing bnr_op_2 lc_trk_g0_2 (25 1) routing sp12_h_l_1 lc_trk_g0_2 (25 1) routing sp12_h_l_17 lc_trk_g0_2 (25 1) routing sp4_h_r_18 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_t_5 lc_trk_g2_6 (25 10) routing sp4_h_l_27 lc_trk_g2_6 (25 10) routing sp4_h_r_46 lc_trk_g2_6 (25 10) routing sp4_v_t_19 lc_trk_g2_6 (25 10) routing sp4_v_t_27 lc_trk_g2_6 (25 11) routing bnl_op_6 lc_trk_g2_6 (25 11) routing sp12_v_b_22 lc_trk_g2_6 (25 11) routing sp12_v_t_5 lc_trk_g2_6 (25 11) routing sp4_h_l_19 lc_trk_g2_6 (25 11) routing sp4_h_r_46 lc_trk_g2_6 (25 11) routing sp4_r_v_b_38 lc_trk_g2_6 (25 11) routing sp4_v_t_27 lc_trk_g2_6 (25 11) routing tnl_op_6 lc_trk_g2_6 (25 12) routing bnl_op_2 lc_trk_g3_2 (25 12) routing rgt_op_2 lc_trk_g3_2 (25 12) routing sp12_v_t_1 lc_trk_g3_2 (25 12) routing sp4_h_r_34 lc_trk_g3_2 (25 12) routing sp4_h_r_42 lc_trk_g3_2 (25 12) routing sp4_v_b_34 lc_trk_g3_2 (25 12) routing sp4_v_t_15 lc_trk_g3_2 (25 13) routing bnl_op_2 lc_trk_g3_2 (25 13) routing sp12_v_b_18 lc_trk_g3_2 (25 13) routing sp12_v_t_1 lc_trk_g3_2 (25 13) routing sp4_h_l_15 lc_trk_g3_2 (25 13) routing sp4_h_r_42 lc_trk_g3_2 (25 13) routing sp4_r_v_b_42 lc_trk_g3_2 (25 13) routing sp4_v_b_34 lc_trk_g3_2 (25 13) routing tnl_op_2 lc_trk_g3_2 (25 14) routing bnl_op_6 lc_trk_g3_6 (25 14) routing rgt_op_6 lc_trk_g3_6 (25 14) routing sp12_v_t_5 lc_trk_g3_6 (25 14) routing sp4_h_l_27 lc_trk_g3_6 (25 14) routing sp4_h_r_46 lc_trk_g3_6 (25 14) routing sp4_v_t_19 lc_trk_g3_6 (25 14) routing sp4_v_t_27 lc_trk_g3_6 (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_22 lc_trk_g3_6 (25 15) routing sp12_v_t_5 lc_trk_g3_6 (25 15) routing sp4_h_l_19 lc_trk_g3_6 (25 15) routing sp4_h_r_46 lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_t_27 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 (25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 (25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_11 lc_trk_g0_6 (25 2) routing sp4_h_l_3 lc_trk_g0_6 (25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp12_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_l_11 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 (25 3) routing sp4_v_b_14 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_l_1 lc_trk_g1_2 (25 4) routing sp4_h_r_10 lc_trk_g1_2 (25 4) routing sp4_h_r_18 lc_trk_g1_2 (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 (25 5) routing sp12_h_l_1 lc_trk_g1_2 (25 5) routing sp12_h_l_17 lc_trk_g1_2 (25 5) routing sp4_h_r_18 lc_trk_g1_2 (25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 (25 6) routing sp4_h_l_11 lc_trk_g1_6 (25 6) routing sp4_h_l_3 lc_trk_g1_6 (25 6) routing sp4_v_b_14 lc_trk_g1_6 (25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp12_h_r_22 lc_trk_g1_6 (25 7) routing sp4_h_l_11 lc_trk_g1_6 (25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_b_14 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_t_1 lc_trk_g2_2 (25 8) routing sp4_h_r_34 lc_trk_g2_2 (25 8) routing sp4_h_r_42 lc_trk_g2_2 (25 8) routing sp4_v_b_34 lc_trk_g2_2 (25 8) routing sp4_v_t_15 lc_trk_g2_2 (25 9) routing bnl_op_2 lc_trk_g2_2 (25 9) routing sp12_v_b_18 lc_trk_g2_2 (25 9) routing sp12_v_t_1 lc_trk_g2_2 (25 9) routing sp4_h_l_15 lc_trk_g2_2 (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_b_34 lc_trk_g2_2 (25 9) routing tnl_op_2 lc_trk_g2_2 (26 0) routing lc_trk_g0_4 input0_0 (26 0) routing lc_trk_g0_6 input0_0 (26 0) routing lc_trk_g1_5 input0_0 (26 0) routing lc_trk_g1_7 input0_0 (26 0) routing lc_trk_g2_4 input0_0 (26 0) routing lc_trk_g2_6 input0_0 (26 0) routing lc_trk_g3_5 input0_0 (26 0) routing lc_trk_g3_7 input0_0 (26 1) routing lc_trk_g0_2 input0_0 (26 1) routing lc_trk_g0_6 input0_0 (26 1) routing lc_trk_g1_3 input0_0 (26 1) routing lc_trk_g1_7 input0_0 (26 1) routing lc_trk_g2_2 input0_0 (26 1) routing lc_trk_g2_6 input0_0 (26 1) routing lc_trk_g3_3 input0_0 (26 1) routing lc_trk_g3_7 input0_0 (26 10) routing lc_trk_g0_5 input0_5 (26 10) routing lc_trk_g0_7 input0_5 (26 10) routing lc_trk_g1_4 input0_5 (26 10) routing lc_trk_g1_6 input0_5 (26 10) routing lc_trk_g2_5 input0_5 (26 10) routing lc_trk_g2_7 input0_5 (26 10) routing lc_trk_g3_4 input0_5 (26 10) routing lc_trk_g3_6 input0_5 (26 11) routing lc_trk_g0_3 input0_5 (26 11) routing lc_trk_g0_7 input0_5 (26 11) routing lc_trk_g1_2 input0_5 (26 11) routing lc_trk_g1_6 input0_5 (26 11) routing lc_trk_g2_3 input0_5 (26 11) routing lc_trk_g2_7 input0_5 (26 11) routing lc_trk_g3_2 input0_5 (26 11) routing lc_trk_g3_6 input0_5 (26 12) routing lc_trk_g0_4 input0_6 (26 12) routing lc_trk_g0_6 input0_6 (26 12) routing lc_trk_g1_5 input0_6 (26 12) routing lc_trk_g1_7 input0_6 (26 12) routing lc_trk_g2_4 input0_6 (26 12) routing lc_trk_g2_6 input0_6 (26 12) routing lc_trk_g3_5 input0_6 (26 12) routing lc_trk_g3_7 input0_6 (26 13) routing lc_trk_g0_2 input0_6 (26 13) routing lc_trk_g0_6 input0_6 (26 13) routing lc_trk_g1_3 input0_6 (26 13) routing lc_trk_g1_7 input0_6 (26 13) routing lc_trk_g2_2 input0_6 (26 13) routing lc_trk_g2_6 input0_6 (26 13) routing lc_trk_g3_3 input0_6 (26 13) routing lc_trk_g3_7 input0_6 (26 14) routing lc_trk_g0_5 input0_7 (26 14) routing lc_trk_g0_7 input0_7 (26 14) routing lc_trk_g1_4 input0_7 (26 14) routing lc_trk_g1_6 input0_7 (26 14) routing lc_trk_g2_5 input0_7 (26 14) routing lc_trk_g2_7 input0_7 (26 14) routing lc_trk_g3_4 input0_7 (26 14) routing lc_trk_g3_6 input0_7 (26 15) routing lc_trk_g0_3 input0_7 (26 15) routing lc_trk_g0_7 input0_7 (26 15) routing lc_trk_g1_2 input0_7 (26 15) routing lc_trk_g1_6 input0_7 (26 15) routing lc_trk_g2_3 input0_7 (26 15) routing lc_trk_g2_7 input0_7 (26 15) routing lc_trk_g3_2 input0_7 (26 15) routing lc_trk_g3_6 input0_7 (26 2) routing lc_trk_g0_5 input0_1 (26 2) routing lc_trk_g0_7 input0_1 (26 2) routing lc_trk_g1_4 input0_1 (26 2) routing lc_trk_g1_6 input0_1 (26 2) routing lc_trk_g2_5 input0_1 (26 2) routing lc_trk_g2_7 input0_1 (26 2) routing lc_trk_g3_4 input0_1 (26 2) routing lc_trk_g3_6 input0_1 (26 3) routing lc_trk_g0_3 input0_1 (26 3) routing lc_trk_g0_7 input0_1 (26 3) routing lc_trk_g1_2 input0_1 (26 3) routing lc_trk_g1_6 input0_1 (26 3) routing lc_trk_g2_3 input0_1 (26 3) routing lc_trk_g2_7 input0_1 (26 3) routing lc_trk_g3_2 input0_1 (26 3) routing lc_trk_g3_6 input0_1 (26 4) routing lc_trk_g0_4 input0_2 (26 4) routing lc_trk_g0_6 input0_2 (26 4) routing lc_trk_g1_5 input0_2 (26 4) routing lc_trk_g1_7 input0_2 (26 4) routing lc_trk_g2_4 input0_2 (26 4) routing lc_trk_g2_6 input0_2 (26 4) routing lc_trk_g3_5 input0_2 (26 4) routing lc_trk_g3_7 input0_2 (26 5) routing lc_trk_g0_2 input0_2 (26 5) routing lc_trk_g0_6 input0_2 (26 5) routing lc_trk_g1_3 input0_2 (26 5) routing lc_trk_g1_7 input0_2 (26 5) routing lc_trk_g2_2 input0_2 (26 5) routing lc_trk_g2_6 input0_2 (26 5) routing lc_trk_g3_3 input0_2 (26 5) routing lc_trk_g3_7 input0_2 (26 6) routing lc_trk_g0_5 input0_3 (26 6) routing lc_trk_g0_7 input0_3 (26 6) routing lc_trk_g1_4 input0_3 (26 6) routing lc_trk_g1_6 input0_3 (26 6) routing lc_trk_g2_5 input0_3 (26 6) routing lc_trk_g2_7 input0_3 (26 6) routing lc_trk_g3_4 input0_3 (26 6) routing lc_trk_g3_6 input0_3 (26 7) routing lc_trk_g0_3 input0_3 (26 7) routing lc_trk_g0_7 input0_3 (26 7) routing lc_trk_g1_2 input0_3 (26 7) routing lc_trk_g1_6 input0_3 (26 7) routing lc_trk_g2_3 input0_3 (26 7) routing lc_trk_g2_7 input0_3 (26 7) routing lc_trk_g3_2 input0_3 (26 7) routing lc_trk_g3_6 input0_3 (26 8) routing lc_trk_g0_4 input0_4 (26 8) routing lc_trk_g0_6 input0_4 (26 8) routing lc_trk_g1_5 input0_4 (26 8) routing lc_trk_g1_7 input0_4 (26 8) routing lc_trk_g2_4 input0_4 (26 8) routing lc_trk_g2_6 input0_4 (26 8) routing lc_trk_g3_5 input0_4 (26 8) routing lc_trk_g3_7 input0_4 (26 9) routing lc_trk_g0_2 input0_4 (26 9) routing lc_trk_g0_6 input0_4 (26 9) routing lc_trk_g1_3 input0_4 (26 9) routing lc_trk_g1_7 input0_4 (26 9) routing lc_trk_g2_2 input0_4 (26 9) routing lc_trk_g2_6 input0_4 (26 9) routing lc_trk_g3_3 input0_4 (26 9) routing lc_trk_g3_7 input0_4 (27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (27 1) routing lc_trk_g1_1 input0_0 (27 1) routing lc_trk_g1_3 input0_0 (27 1) routing lc_trk_g1_5 input0_0 (27 1) routing lc_trk_g1_7 input0_0 (27 1) routing lc_trk_g3_1 input0_0 (27 1) routing lc_trk_g3_3 input0_0 (27 1) routing lc_trk_g3_5 input0_0 (27 1) routing lc_trk_g3_7 input0_0 (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (27 11) routing lc_trk_g1_0 input0_5 (27 11) routing lc_trk_g1_2 input0_5 (27 11) routing lc_trk_g1_4 input0_5 (27 11) routing lc_trk_g1_6 input0_5 (27 11) routing lc_trk_g3_0 input0_5 (27 11) routing lc_trk_g3_2 input0_5 (27 11) routing lc_trk_g3_4 input0_5 (27 11) routing lc_trk_g3_6 input0_5 (27 12) routing lc_trk_g1_0 wire_bram/ram/WDATA_9 (27 12) routing lc_trk_g1_2 wire_bram/ram/WDATA_9 (27 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_9 (27 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 (27 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_9 (27 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_9 (27 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_9 (27 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 (27 13) routing lc_trk_g1_1 input0_6 (27 13) routing lc_trk_g1_3 input0_6 (27 13) routing lc_trk_g1_5 input0_6 (27 13) routing lc_trk_g1_7 input0_6 (27 13) routing lc_trk_g3_1 input0_6 (27 13) routing lc_trk_g3_3 input0_6 (27 13) routing lc_trk_g3_5 input0_6 (27 13) routing lc_trk_g3_7 input0_6 (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (27 15) routing lc_trk_g1_0 input0_7 (27 15) routing lc_trk_g1_2 input0_7 (27 15) routing lc_trk_g1_4 input0_7 (27 15) routing lc_trk_g1_6 input0_7 (27 15) routing lc_trk_g3_0 input0_7 (27 15) routing lc_trk_g3_2 input0_7 (27 15) routing lc_trk_g3_4 input0_7 (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (27 3) routing lc_trk_g1_0 input0_1 (27 3) routing lc_trk_g1_2 input0_1 (27 3) routing lc_trk_g1_4 input0_1 (27 3) routing lc_trk_g1_6 input0_1 (27 3) routing lc_trk_g3_0 input0_1 (27 3) routing lc_trk_g3_2 input0_1 (27 3) routing lc_trk_g3_4 input0_1 (27 3) routing lc_trk_g3_6 input0_1 (27 4) routing lc_trk_g1_0 wire_bram/ram/WDATA_13 (27 4) routing lc_trk_g1_2 wire_bram/ram/WDATA_13 (27 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_13 (27 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_13 (27 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_13 (27 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 (27 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_13 (27 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 (27 5) routing lc_trk_g1_1 input0_2 (27 5) routing lc_trk_g1_3 input0_2 (27 5) routing lc_trk_g1_5 input0_2 (27 5) routing lc_trk_g1_7 input0_2 (27 5) routing lc_trk_g3_1 input0_2 (27 5) routing lc_trk_g3_3 input0_2 (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 (27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (27 7) routing lc_trk_g1_0 input0_3 (27 7) routing lc_trk_g1_2 input0_3 (27 7) routing lc_trk_g1_4 input0_3 (27 7) routing lc_trk_g1_6 input0_3 (27 7) routing lc_trk_g3_0 input0_3 (27 7) routing lc_trk_g3_2 input0_3 (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (27 9) routing lc_trk_g1_1 input0_4 (27 9) routing lc_trk_g1_3 input0_4 (27 9) routing lc_trk_g1_5 input0_4 (27 9) routing lc_trk_g1_7 input0_4 (27 9) routing lc_trk_g3_1 input0_4 (27 9) routing lc_trk_g3_3 input0_4 (27 9) routing lc_trk_g3_5 input0_4 (27 9) routing lc_trk_g3_7 input0_4 (28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (28 1) routing lc_trk_g2_0 input0_0 (28 1) routing lc_trk_g2_2 input0_0 (28 1) routing lc_trk_g2_4 input0_0 (28 1) routing lc_trk_g2_6 input0_0 (28 1) routing lc_trk_g3_1 input0_0 (28 1) routing lc_trk_g3_3 input0_0 (28 1) routing lc_trk_g3_5 input0_0 (28 1) routing lc_trk_g3_7 input0_0 (28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (28 11) routing lc_trk_g2_1 input0_5 (28 11) routing lc_trk_g2_3 input0_5 (28 11) routing lc_trk_g2_5 input0_5 (28 11) routing lc_trk_g2_7 input0_5 (28 11) routing lc_trk_g3_0 input0_5 (28 11) routing lc_trk_g3_2 input0_5 (28 11) routing lc_trk_g3_4 input0_5 (28 11) routing lc_trk_g3_6 input0_5 (28 12) routing lc_trk_g2_1 wire_bram/ram/WDATA_9 (28 12) routing lc_trk_g2_3 wire_bram/ram/WDATA_9 (28 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_9 (28 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_9 (28 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_9 (28 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_9 (28 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_9 (28 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 (28 13) routing lc_trk_g2_0 input0_6 (28 13) routing lc_trk_g2_2 input0_6 (28 13) routing lc_trk_g2_4 input0_6 (28 13) routing lc_trk_g2_6 input0_6 (28 13) routing lc_trk_g3_1 input0_6 (28 13) routing lc_trk_g3_3 input0_6 (28 13) routing lc_trk_g3_5 input0_6 (28 13) routing lc_trk_g3_7 input0_6 (28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (28 15) routing lc_trk_g2_1 input0_7 (28 15) routing lc_trk_g2_3 input0_7 (28 15) routing lc_trk_g2_5 input0_7 (28 15) routing lc_trk_g2_7 input0_7 (28 15) routing lc_trk_g3_0 input0_7 (28 15) routing lc_trk_g3_2 input0_7 (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 (28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (28 3) routing lc_trk_g2_1 input0_1 (28 3) routing lc_trk_g2_3 input0_1 (28 3) routing lc_trk_g2_5 input0_1 (28 3) routing lc_trk_g2_7 input0_1 (28 3) routing lc_trk_g3_0 input0_1 (28 3) routing lc_trk_g3_2 input0_1 (28 3) routing lc_trk_g3_4 input0_1 (28 3) routing lc_trk_g3_6 input0_1 (28 4) routing lc_trk_g2_1 wire_bram/ram/WDATA_13 (28 4) routing lc_trk_g2_3 wire_bram/ram/WDATA_13 (28 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_13 (28 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 (28 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_13 (28 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 (28 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_13 (28 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 (28 5) routing lc_trk_g2_0 input0_2 (28 5) routing lc_trk_g2_2 input0_2 (28 5) routing lc_trk_g2_4 input0_2 (28 5) routing lc_trk_g2_6 input0_2 (28 5) routing lc_trk_g3_1 input0_2 (28 5) routing lc_trk_g3_3 input0_2 (28 5) routing lc_trk_g3_5 input0_2 (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (28 7) routing lc_trk_g2_1 input0_3 (28 7) routing lc_trk_g2_3 input0_3 (28 7) routing lc_trk_g2_5 input0_3 (28 7) routing lc_trk_g2_7 input0_3 (28 7) routing lc_trk_g3_0 input0_3 (28 7) routing lc_trk_g3_2 input0_3 (28 7) routing lc_trk_g3_4 input0_3 (28 7) routing lc_trk_g3_6 input0_3 (28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (28 9) routing lc_trk_g2_0 input0_4 (28 9) routing lc_trk_g2_2 input0_4 (28 9) routing lc_trk_g2_4 input0_4 (28 9) routing lc_trk_g2_6 input0_4 (28 9) routing lc_trk_g3_1 input0_4 (28 9) routing lc_trk_g3_3 input0_4 (28 9) routing lc_trk_g3_5 input0_4 (28 9) routing lc_trk_g3_7 input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_9 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_13 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_13 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_12 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 (3 0) routing sp12_h_r_0 sp12_v_b_0 (3 0) routing sp12_v_t_23 sp12_v_b_0 (3 1) routing sp12_h_l_23 sp12_v_b_0 (3 1) routing sp12_h_r_0 sp12_v_b_0 (3 10) routing sp12_h_r_1 sp12_h_l_22 (3 10) routing sp12_v_t_22 sp12_h_l_22 (3 11) routing sp12_h_r_1 sp12_h_l_22 (3 11) routing sp12_v_b_1 sp12_h_l_22 (3 12) routing sp12_v_b_1 sp12_h_r_1 (3 12) routing sp12_v_t_22 sp12_h_r_1 (3 13) routing sp12_h_l_22 sp12_h_r_1 (3 13) routing sp12_v_b_1 sp12_h_r_1 (3 14) routing sp12_h_r_1 sp12_v_t_22 (3 14) routing sp12_v_b_1 sp12_v_t_22 (3 15) routing sp12_h_l_22 sp12_v_t_22 (3 15) routing sp12_h_r_1 sp12_v_t_22 (3 2) routing sp12_h_r_0 sp12_h_l_23 (3 2) routing sp12_v_t_23 sp12_h_l_23 (3 3) routing sp12_h_r_0 sp12_h_l_23 (3 3) routing sp12_v_b_0 sp12_h_l_23 (3 4) routing sp12_v_b_0 sp12_h_r_0 (3 4) routing sp12_v_t_23 sp12_h_r_0 (3 5) routing sp12_h_l_23 sp12_h_r_0 (3 5) routing sp12_v_b_0 sp12_h_r_0 (3 6) routing sp12_h_r_0 sp12_v_t_23 (3 6) routing sp12_v_b_0 sp12_v_t_23 (3 7) routing sp12_h_l_23 sp12_v_t_23 (3 7) routing sp12_h_r_0 sp12_v_t_23 (3 8) routing sp12_h_r_1 sp12_v_b_1 (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 (30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g0_3 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g1_2 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g2_3 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g2_7 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g3_2 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 (30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g0_3 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g0_7 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g1_2 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g1_6 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g2_3 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 (30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_14 (31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (33 11) routing lc_trk_g2_1 input2_5 (33 11) routing lc_trk_g2_3 input2_5 (33 11) routing lc_trk_g2_5 input2_5 (33 11) routing lc_trk_g2_7 input2_5 (33 11) routing lc_trk_g3_0 input2_5 (33 11) routing lc_trk_g3_2 input2_5 (33 11) routing lc_trk_g3_4 input2_5 (33 11) routing lc_trk_g3_6 input2_5 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (33 13) routing lc_trk_g2_0 input2_6 (33 13) routing lc_trk_g2_2 input2_6 (33 13) routing lc_trk_g2_4 input2_6 (33 13) routing lc_trk_g2_6 input2_6 (33 13) routing lc_trk_g3_1 input2_6 (33 13) routing lc_trk_g3_3 input2_6 (33 13) routing lc_trk_g3_5 input2_6 (33 13) routing lc_trk_g3_7 input2_6 (33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (33 15) routing lc_trk_g2_1 input2_7 (33 15) routing lc_trk_g2_3 input2_7 (33 15) routing lc_trk_g2_5 input2_7 (33 15) routing lc_trk_g2_7 input2_7 (33 15) routing lc_trk_g3_0 input2_7 (33 15) routing lc_trk_g3_2 input2_7 (33 15) routing lc_trk_g3_4 input2_7 (33 15) routing lc_trk_g3_6 input2_7 (33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (34 11) routing lc_trk_g1_0 input2_5 (34 11) routing lc_trk_g1_2 input2_5 (34 11) routing lc_trk_g1_4 input2_5 (34 11) routing lc_trk_g1_6 input2_5 (34 11) routing lc_trk_g3_0 input2_5 (34 11) routing lc_trk_g3_2 input2_5 (34 11) routing lc_trk_g3_4 input2_5 (34 11) routing lc_trk_g3_6 input2_5 (34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (34 13) routing lc_trk_g1_1 input2_6 (34 13) routing lc_trk_g1_3 input2_6 (34 13) routing lc_trk_g1_5 input2_6 (34 13) routing lc_trk_g1_7 input2_6 (34 13) routing lc_trk_g3_1 input2_6 (34 13) routing lc_trk_g3_3 input2_6 (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (34 15) routing lc_trk_g1_0 input2_7 (34 15) routing lc_trk_g1_2 input2_7 (34 15) routing lc_trk_g1_4 input2_7 (34 15) routing lc_trk_g1_6 input2_7 (34 15) routing lc_trk_g3_0 input2_7 (34 15) routing lc_trk_g3_2 input2_7 (34 15) routing lc_trk_g3_4 input2_7 (34 15) routing lc_trk_g3_6 input2_7 (34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 (34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (35 10) routing lc_trk_g0_5 input2_5 (35 10) routing lc_trk_g0_7 input2_5 (35 10) routing lc_trk_g1_4 input2_5 (35 10) routing lc_trk_g1_6 input2_5 (35 10) routing lc_trk_g2_5 input2_5 (35 10) routing lc_trk_g2_7 input2_5 (35 10) routing lc_trk_g3_4 input2_5 (35 10) routing lc_trk_g3_6 input2_5 (35 11) routing lc_trk_g0_3 input2_5 (35 11) routing lc_trk_g0_7 input2_5 (35 11) routing lc_trk_g1_2 input2_5 (35 11) routing lc_trk_g1_6 input2_5 (35 11) routing lc_trk_g2_3 input2_5 (35 11) routing lc_trk_g2_7 input2_5 (35 11) routing lc_trk_g3_2 input2_5 (35 11) routing lc_trk_g3_6 input2_5 (35 12) routing lc_trk_g0_4 input2_6 (35 12) routing lc_trk_g0_6 input2_6 (35 12) routing lc_trk_g1_5 input2_6 (35 12) routing lc_trk_g1_7 input2_6 (35 12) routing lc_trk_g2_4 input2_6 (35 12) routing lc_trk_g2_6 input2_6 (35 12) routing lc_trk_g3_5 input2_6 (35 12) routing lc_trk_g3_7 input2_6 (35 13) routing lc_trk_g0_2 input2_6 (35 13) routing lc_trk_g0_6 input2_6 (35 13) routing lc_trk_g1_3 input2_6 (35 13) routing lc_trk_g1_7 input2_6 (35 13) routing lc_trk_g2_2 input2_6 (35 13) routing lc_trk_g2_6 input2_6 (35 13) routing lc_trk_g3_3 input2_6 (35 13) routing lc_trk_g3_7 input2_6 (35 14) routing lc_trk_g0_5 input2_7 (35 14) routing lc_trk_g0_7 input2_7 (35 14) routing lc_trk_g1_4 input2_7 (35 14) routing lc_trk_g1_6 input2_7 (35 14) routing lc_trk_g2_5 input2_7 (35 14) routing lc_trk_g2_7 input2_7 (35 14) routing lc_trk_g3_4 input2_7 (35 14) routing lc_trk_g3_6 input2_7 (35 15) routing lc_trk_g0_3 input2_7 (35 15) routing lc_trk_g0_7 input2_7 (35 15) routing lc_trk_g1_2 input2_7 (35 15) routing lc_trk_g1_6 input2_7 (35 15) routing lc_trk_g2_3 input2_7 (35 15) routing lc_trk_g2_7 input2_7 (35 15) routing lc_trk_g3_2 input2_7 (35 15) routing lc_trk_g3_6 input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 (36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 (36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 (36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40 (36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1 (37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_10 sp4_h_l_15 (37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_9 sp12_h_l_3 (37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_9 sp4_h_r_28 (37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_8 sp12_h_l_5 (37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_8 sp4_h_l_19 (37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_14 sp12_h_l_9 (37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_14 sp4_h_r_18 (37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_13 sp12_h_r_12 (37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_13 sp4_h_l_9 (37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_12 sp12_h_r_14 (37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_12 sp4_h_l_11 (37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_11 sp12_h_r_0 (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0 (38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 (38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 (38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 (38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 (38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 (39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_10 sp4_v_b_10 (39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_9 sp4_v_b_44 (39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_9 sp4_v_b_12 (39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_8 sp4_v_b_46 (39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_8 sp4_v_b_14 (39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_14 sp12_v_t_1 (39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_14 sp4_v_t_7 (39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_13 sp12_v_b_4 (39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_13 sp4_v_b_20 (39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_12 sp12_v_t_5 (39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_12 sp4_v_t_11 (39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_11 sp4_v_b_40 (39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_11 sp4_v_b_8 (4 0) routing sp4_h_l_37 sp4_v_b_0 (4 0) routing sp4_h_l_43 sp4_v_b_0 (4 0) routing sp4_v_t_37 sp4_v_b_0 (4 0) routing sp4_v_t_41 sp4_v_b_0 (4 1) routing sp4_h_l_41 sp4_h_r_0 (4 1) routing sp4_h_l_44 sp4_h_r_0 (4 1) routing sp4_v_b_6 sp4_h_r_0 (4 1) routing sp4_v_t_42 sp4_h_r_0 (4 10) routing sp4_h_r_0 sp4_v_t_43 (4 10) routing sp4_h_r_6 sp4_v_t_43 (4 10) routing sp4_v_b_10 sp4_v_t_43 (4 10) routing sp4_v_b_6 sp4_v_t_43 (4 11) routing sp4_h_r_10 sp4_h_l_43 (4 11) routing sp4_h_r_3 sp4_h_l_43 (4 11) routing sp4_v_b_1 sp4_h_l_43 (4 11) routing sp4_v_t_37 sp4_h_l_43 (4 12) routing sp4_h_l_38 sp4_v_b_9 (4 12) routing sp4_h_l_44 sp4_v_b_9 (4 12) routing sp4_v_t_36 sp4_v_b_9 (4 12) routing sp4_v_t_44 sp4_v_b_9 (4 13) routing sp4_h_l_36 sp4_h_r_9 (4 13) routing sp4_h_l_43 sp4_h_r_9 (4 13) routing sp4_v_b_3 sp4_h_r_9 (4 13) routing sp4_v_t_41 sp4_h_r_9 (4 14) routing sp4_h_r_3 sp4_v_t_44 (4 14) routing sp4_h_r_9 sp4_v_t_44 (4 14) routing sp4_v_b_1 sp4_v_t_44 (4 14) routing sp4_v_b_9 sp4_v_t_44 (4 15) routing sp4_h_r_1 sp4_h_l_44 (4 15) routing sp4_h_r_6 sp4_h_l_44 (4 15) routing sp4_v_b_4 sp4_h_l_44 (4 15) routing sp4_v_t_38 sp4_h_l_44 (4 2) routing sp4_h_r_0 sp4_v_t_37 (4 2) routing sp4_h_r_6 sp4_v_t_37 (4 2) routing sp4_v_b_0 sp4_v_t_37 (4 2) routing sp4_v_b_4 sp4_v_t_37 (4 3) routing sp4_h_r_4 sp4_h_l_37 (4 3) routing sp4_h_r_9 sp4_h_l_37 (4 3) routing sp4_v_b_7 sp4_h_l_37 (4 3) routing sp4_v_t_43 sp4_h_l_37 (4 4) routing sp4_h_l_38 sp4_v_b_3 (4 4) routing sp4_h_l_44 sp4_v_b_3 (4 4) routing sp4_v_t_38 sp4_v_b_3 (4 4) routing sp4_v_t_42 sp4_v_b_3 (4 5) routing sp4_h_l_37 sp4_h_r_3 (4 5) routing sp4_h_l_42 sp4_h_r_3 (4 5) routing sp4_v_b_9 sp4_h_r_3 (4 5) routing sp4_v_t_47 sp4_h_r_3 (4 6) routing sp4_h_r_3 sp4_v_t_38 (4 6) routing sp4_h_r_9 sp4_v_t_38 (4 6) routing sp4_v_b_3 sp4_v_t_38 (4 6) routing sp4_v_b_7 sp4_v_t_38 (4 7) routing sp4_h_r_0 sp4_h_l_38 (4 7) routing sp4_h_r_7 sp4_h_l_38 (4 7) routing sp4_v_b_10 sp4_h_l_38 (4 7) routing sp4_v_t_44 sp4_h_l_38 (4 8) routing sp4_h_l_37 sp4_v_b_6 (4 8) routing sp4_h_l_43 sp4_v_b_6 (4 8) routing sp4_v_t_43 sp4_v_b_6 (4 8) routing sp4_v_t_47 sp4_v_b_6 (4 9) routing sp4_h_l_38 sp4_h_r_6 (4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 (40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_13 sp12_v_b_20 (40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_23 (40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_12 sp12_v_b_22 (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_11 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_33 (41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_45 (41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_13 (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 (41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 (41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_7 (41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_41 (41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_9 (5 0) routing sp4_h_l_44 sp4_h_r_0 (5 0) routing sp4_v_b_0 sp4_h_r_0 (5 0) routing sp4_v_b_6 sp4_h_r_0 (5 0) routing sp4_v_t_37 sp4_h_r_0 (5 1) routing sp4_h_l_37 sp4_v_b_0 (5 1) routing sp4_h_l_43 sp4_v_b_0 (5 1) routing sp4_h_r_0 sp4_v_b_0 (5 1) routing sp4_v_t_44 sp4_v_b_0 (5 10) routing sp4_h_r_3 sp4_h_l_43 (5 10) routing sp4_v_b_6 sp4_h_l_43 (5 10) routing sp4_v_t_37 sp4_h_l_43 (5 10) routing sp4_v_t_43 sp4_h_l_43 (5 11) routing sp4_h_l_43 sp4_v_t_43 (5 11) routing sp4_h_r_0 sp4_v_t_43 (5 11) routing sp4_h_r_6 sp4_v_t_43 (5 11) routing sp4_v_b_3 sp4_v_t_43 (5 12) routing sp4_h_l_43 sp4_h_r_9 (5 12) routing sp4_v_b_3 sp4_h_r_9 (5 12) routing sp4_v_b_9 sp4_h_r_9 (5 12) routing sp4_v_t_44 sp4_h_r_9 (5 13) routing sp4_h_l_38 sp4_v_b_9 (5 13) routing sp4_h_l_44 sp4_v_b_9 (5 13) routing sp4_h_r_9 sp4_v_b_9 (5 13) routing sp4_v_t_43 sp4_v_b_9 (5 14) routing sp4_h_r_6 sp4_h_l_44 (5 14) routing sp4_v_b_9 sp4_h_l_44 (5 14) routing sp4_v_t_38 sp4_h_l_44 (5 14) routing sp4_v_t_44 sp4_h_l_44 (5 15) routing sp4_h_l_44 sp4_v_t_44 (5 15) routing sp4_h_r_3 sp4_v_t_44 (5 15) routing sp4_h_r_9 sp4_v_t_44 (5 15) routing sp4_v_b_6 sp4_v_t_44 (5 2) routing sp4_h_r_9 sp4_h_l_37 (5 2) routing sp4_v_b_0 sp4_h_l_37 (5 2) routing sp4_v_t_37 sp4_h_l_37 (5 2) routing sp4_v_t_43 sp4_h_l_37 (5 3) routing sp4_h_l_37 sp4_v_t_37 (5 3) routing sp4_h_r_0 sp4_v_t_37 (5 3) routing sp4_h_r_6 sp4_v_t_37 (5 3) routing sp4_v_b_9 sp4_v_t_37 (5 4) routing sp4_h_l_37 sp4_h_r_3 (5 4) routing sp4_v_b_3 sp4_h_r_3 (5 4) routing sp4_v_b_9 sp4_h_r_3 (5 4) routing sp4_v_t_38 sp4_h_r_3 (5 5) routing sp4_h_l_38 sp4_v_b_3 (5 5) routing sp4_h_l_44 sp4_v_b_3 (5 5) routing sp4_h_r_3 sp4_v_b_3 (5 5) routing sp4_v_t_37 sp4_v_b_3 (5 6) routing sp4_h_r_0 sp4_h_l_38 (5 6) routing sp4_v_b_3 sp4_h_l_38 (5 6) routing sp4_v_t_38 sp4_h_l_38 (5 6) routing sp4_v_t_44 sp4_h_l_38 (5 7) routing sp4_h_l_38 sp4_v_t_38 (5 7) routing sp4_h_r_3 sp4_v_t_38 (5 7) routing sp4_h_r_9 sp4_v_t_38 (5 7) routing sp4_v_b_0 sp4_v_t_38 (5 8) routing sp4_h_l_38 sp4_h_r_6 (5 8) routing sp4_v_b_0 sp4_h_r_6 (5 8) routing sp4_v_b_6 sp4_h_r_6 (5 8) routing sp4_v_t_43 sp4_h_r_6 (5 9) routing sp4_h_l_37 sp4_v_b_6 (5 9) routing sp4_h_l_43 sp4_v_b_6 (5 9) routing sp4_h_r_6 sp4_v_b_6 (5 9) routing sp4_v_t_38 sp4_v_b_6 (6 0) routing sp4_h_l_43 sp4_v_b_0 (6 0) routing sp4_h_r_7 sp4_v_b_0 (6 0) routing sp4_v_t_41 sp4_v_b_0 (6 0) routing sp4_v_t_44 sp4_v_b_0 (6 1) routing sp4_h_l_37 sp4_h_r_0 (6 1) routing sp4_h_l_41 sp4_h_r_0 (6 1) routing sp4_v_b_0 sp4_h_r_0 (6 1) routing sp4_v_b_6 sp4_h_r_0 (6 10) routing sp4_h_l_36 sp4_v_t_43 (6 10) routing sp4_h_r_0 sp4_v_t_43 (6 10) routing sp4_v_b_10 sp4_v_t_43 (6 10) routing sp4_v_b_3 sp4_v_t_43 (6 11) routing sp4_h_r_10 sp4_h_l_43 (6 11) routing sp4_h_r_6 sp4_h_l_43 (6 11) routing sp4_v_t_37 sp4_h_l_43 (6 11) routing sp4_v_t_43 sp4_h_l_43 (6 12) routing sp4_h_l_38 sp4_v_b_9 (6 12) routing sp4_h_r_4 sp4_v_b_9 (6 12) routing sp4_v_t_36 sp4_v_b_9 (6 12) routing sp4_v_t_43 sp4_v_b_9 (6 13) routing sp4_h_l_36 sp4_h_r_9 (6 13) routing sp4_h_l_44 sp4_h_r_9 (6 13) routing sp4_v_b_3 sp4_h_r_9 (6 13) routing sp4_v_b_9 sp4_h_r_9 (6 14) routing sp4_h_l_41 sp4_v_t_44 (6 14) routing sp4_h_r_3 sp4_v_t_44 (6 14) routing sp4_v_b_1 sp4_v_t_44 (6 14) routing sp4_v_b_6 sp4_v_t_44 (6 15) routing sp4_h_r_1 sp4_h_l_44 (6 15) routing sp4_h_r_9 sp4_h_l_44 (6 15) routing sp4_v_t_38 sp4_h_l_44 (6 15) routing sp4_v_t_44 sp4_h_l_44 (6 2) routing sp4_h_l_42 sp4_v_t_37 (6 2) routing sp4_h_r_6 sp4_v_t_37 (6 2) routing sp4_v_b_4 sp4_v_t_37 (6 2) routing sp4_v_b_9 sp4_v_t_37 (6 3) routing sp4_h_r_0 sp4_h_l_37 (6 3) routing sp4_h_r_4 sp4_h_l_37 (6 3) routing sp4_v_t_37 sp4_h_l_37 (6 3) routing sp4_v_t_43 sp4_h_l_37 (6 4) routing sp4_h_l_44 sp4_v_b_3 (6 4) routing sp4_h_r_10 sp4_v_b_3 (6 4) routing sp4_v_t_37 sp4_v_b_3 (6 4) routing sp4_v_t_42 sp4_v_b_3 (6 5) routing sp4_h_l_38 sp4_h_r_3 (6 5) routing sp4_h_l_42 sp4_h_r_3 (6 5) routing sp4_v_b_3 sp4_h_r_3 (6 5) routing sp4_v_b_9 sp4_h_r_3 (6 6) routing sp4_h_l_47 sp4_v_t_38 (6 6) routing sp4_h_r_9 sp4_v_t_38 (6 6) routing sp4_v_b_0 sp4_v_t_38 (6 6) routing sp4_v_b_7 sp4_v_t_38 (6 7) routing sp4_h_r_3 sp4_h_l_38 (6 7) routing sp4_h_r_7 sp4_h_l_38 (6 7) routing sp4_v_t_38 sp4_h_l_38 (6 7) routing sp4_v_t_44 sp4_h_l_38 (6 8) routing sp4_h_l_37 sp4_v_b_6 (6 8) routing sp4_h_r_1 sp4_v_b_6 (6 8) routing sp4_v_t_38 sp4_v_b_6 (6 8) routing sp4_v_t_47 sp4_v_b_6 (6 9) routing sp4_h_l_43 sp4_h_r_6 (6 9) routing sp4_h_l_47 sp4_h_r_6 (6 9) routing sp4_v_b_0 sp4_h_r_6 (6 9) routing sp4_v_b_6 sp4_h_r_6 (7 1) Ram config bit: MEMB_Power_Up_Control (7 10) Column buffer control bit: MEMB_colbuf_cntl_3 (7 11) Column buffer control bit: MEMB_colbuf_cntl_2 (7 12) Column buffer control bit: MEMB_colbuf_cntl_5 (7 13) Column buffer control bit: MEMB_colbuf_cntl_4 (7 14) Column buffer control bit: MEMB_colbuf_cntl_7 (7 15) Column buffer control bit: MEMB_colbuf_cntl_6 (7 8) Column buffer control bit: MEMB_colbuf_cntl_1 (7 9) Column buffer control bit: MEMB_colbuf_cntl_0 (8 0) routing sp4_h_l_36 sp4_h_r_1 (8 0) routing sp4_h_l_40 sp4_h_r_1 (8 0) routing sp4_v_b_1 sp4_h_r_1 (8 0) routing sp4_v_b_7 sp4_h_r_1 (8 1) routing sp4_h_l_36 sp4_v_b_1 (8 1) routing sp4_h_l_42 sp4_v_b_1 (8 1) routing sp4_h_r_1 sp4_v_b_1 (8 1) routing sp4_v_t_47 sp4_v_b_1 (8 10) routing sp4_h_r_11 sp4_h_l_42 (8 10) routing sp4_h_r_7 sp4_h_l_42 (8 10) routing sp4_v_t_36 sp4_h_l_42 (8 10) routing sp4_v_t_42 sp4_h_l_42 (8 11) routing sp4_h_l_42 sp4_v_t_42 (8 11) routing sp4_h_r_1 sp4_v_t_42 (8 11) routing sp4_h_r_7 sp4_v_t_42 (8 11) routing sp4_v_b_4 sp4_v_t_42 (8 12) routing sp4_h_l_39 sp4_h_r_10 (8 12) routing sp4_h_l_47 sp4_h_r_10 (8 12) routing sp4_v_b_10 sp4_h_r_10 (8 12) routing sp4_v_b_4 sp4_h_r_10 (8 13) routing sp4_h_l_41 sp4_v_b_10 (8 13) routing sp4_h_l_47 sp4_v_b_10 (8 13) routing sp4_h_r_10 sp4_v_b_10 (8 13) routing sp4_v_t_42 sp4_v_b_10 (8 14) routing sp4_h_r_10 sp4_h_l_47 (8 14) routing sp4_h_r_2 sp4_h_l_47 (8 14) routing sp4_v_t_41 sp4_h_l_47 (8 14) routing sp4_v_t_47 sp4_h_l_47 (8 15) routing sp4_h_l_47 sp4_v_t_47 (8 15) routing sp4_h_r_10 sp4_v_t_47 (8 15) routing sp4_h_r_4 sp4_v_t_47 (8 15) routing sp4_v_b_7 sp4_v_t_47 (8 2) routing sp4_h_r_1 sp4_h_l_36 (8 2) routing sp4_h_r_5 sp4_h_l_36 (8 2) routing sp4_v_t_36 sp4_h_l_36 (8 2) routing sp4_v_t_42 sp4_h_l_36 (8 3) routing sp4_h_l_36 sp4_v_t_36 (8 3) routing sp4_h_r_1 sp4_v_t_36 (8 3) routing sp4_h_r_7 sp4_v_t_36 (8 3) routing sp4_v_b_10 sp4_v_t_36 (8 4) routing sp4_h_l_41 sp4_h_r_4 (8 4) routing sp4_h_l_45 sp4_h_r_4 (8 4) routing sp4_v_b_10 sp4_h_r_4 (8 4) routing sp4_v_b_4 sp4_h_r_4 (8 5) routing sp4_h_l_41 sp4_v_b_4 (8 5) routing sp4_h_l_47 sp4_v_b_4 (8 5) routing sp4_h_r_4 sp4_v_b_4 (8 5) routing sp4_v_t_36 sp4_v_b_4 (8 6) routing sp4_h_r_4 sp4_h_l_41 (8 6) routing sp4_h_r_8 sp4_h_l_41 (8 6) routing sp4_v_t_41 sp4_h_l_41 (8 6) routing sp4_v_t_47 sp4_h_l_41 (8 7) routing sp4_h_l_41 sp4_v_t_41 (8 7) routing sp4_h_r_10 sp4_v_t_41 (8 7) routing sp4_h_r_4 sp4_v_t_41 (8 7) routing sp4_v_b_1 sp4_v_t_41 (8 8) routing sp4_h_l_42 sp4_h_r_7 (8 8) routing sp4_h_l_46 sp4_h_r_7 (8 8) routing sp4_v_b_1 sp4_h_r_7 (8 8) routing sp4_v_b_7 sp4_h_r_7 (8 9) routing sp4_h_l_36 sp4_v_b_7 (8 9) routing sp4_h_l_42 sp4_v_b_7 (8 9) routing sp4_h_r_7 sp4_v_b_7 (8 9) routing sp4_v_t_41 sp4_v_b_7 (9 0) routing sp4_h_l_47 sp4_h_r_1 (9 0) routing sp4_v_b_1 sp4_h_r_1 (9 0) routing sp4_v_b_7 sp4_h_r_1 (9 0) routing sp4_v_t_36 sp4_h_r_1 (9 1) routing sp4_h_l_36 sp4_v_b_1 (9 1) routing sp4_h_l_42 sp4_v_b_1 (9 1) routing sp4_v_t_36 sp4_v_b_1 (9 1) routing sp4_v_t_40 sp4_v_b_1 (9 10) routing sp4_h_r_4 sp4_h_l_42 (9 10) routing sp4_v_b_7 sp4_h_l_42 (9 10) routing sp4_v_t_36 sp4_h_l_42 (9 10) routing sp4_v_t_42 sp4_h_l_42 (9 11) routing sp4_h_r_1 sp4_v_t_42 (9 11) routing sp4_h_r_7 sp4_v_t_42 (9 11) routing sp4_v_b_11 sp4_v_t_42 (9 11) routing sp4_v_b_7 sp4_v_t_42 (9 12) routing sp4_h_l_42 sp4_h_r_10 (9 12) routing sp4_v_b_10 sp4_h_r_10 (9 12) routing sp4_v_b_4 sp4_h_r_10 (9 12) routing sp4_v_t_47 sp4_h_r_10 (9 13) routing sp4_h_l_41 sp4_v_b_10 (9 13) routing sp4_h_l_47 sp4_v_b_10 (9 13) routing sp4_v_t_39 sp4_v_b_10 (9 13) routing sp4_v_t_47 sp4_v_b_10 (9 14) routing sp4_h_r_7 sp4_h_l_47 (9 14) routing sp4_v_b_10 sp4_h_l_47 (9 14) routing sp4_v_t_41 sp4_h_l_47 (9 14) routing sp4_v_t_47 sp4_h_l_47 (9 15) routing sp4_h_r_10 sp4_v_t_47 (9 15) routing sp4_h_r_4 sp4_v_t_47 (9 15) routing sp4_v_b_10 sp4_v_t_47 (9 15) routing sp4_v_b_2 sp4_v_t_47 (9 2) routing sp4_h_r_10 sp4_h_l_36 (9 2) routing sp4_v_b_1 sp4_h_l_36 (9 2) routing sp4_v_t_36 sp4_h_l_36 (9 2) routing sp4_v_t_42 sp4_h_l_36 (9 3) routing sp4_h_r_1 sp4_v_t_36 (9 3) routing sp4_h_r_7 sp4_v_t_36 (9 3) routing sp4_v_b_1 sp4_v_t_36 (9 3) routing sp4_v_b_5 sp4_v_t_36 (9 4) routing sp4_h_l_36 sp4_h_r_4 (9 4) routing sp4_v_b_10 sp4_h_r_4 (9 4) routing sp4_v_b_4 sp4_h_r_4 (9 4) routing sp4_v_t_41 sp4_h_r_4 (9 5) routing sp4_h_l_41 sp4_v_b_4 (9 5) routing sp4_h_l_47 sp4_v_b_4 (9 5) routing sp4_v_t_41 sp4_v_b_4 (9 5) routing sp4_v_t_45 sp4_v_b_4 (9 6) routing sp4_h_r_1 sp4_h_l_41 (9 6) routing sp4_v_b_4 sp4_h_l_41 (9 6) routing sp4_v_t_41 sp4_h_l_41 (9 6) routing sp4_v_t_47 sp4_h_l_41 (9 7) routing sp4_h_r_10 sp4_v_t_41 (9 7) routing sp4_h_r_4 sp4_v_t_41 (9 7) routing sp4_v_b_4 sp4_v_t_41 (9 7) routing sp4_v_b_8 sp4_v_t_41 (9 8) routing sp4_h_l_41 sp4_h_r_7 (9 8) routing sp4_v_b_1 sp4_h_r_7 (9 8) routing sp4_v_b_7 sp4_h_r_7 (9 8) routing sp4_v_t_42 sp4_h_r_7 (9 9) routing sp4_h_l_36 sp4_v_b_7 (9 9) routing sp4_h_l_42 sp4_v_b_7 (9 9) routing sp4_v_t_42 sp4_v_b_7 (9 9) routing sp4_v_t_46 sp4_v_b_7 fpga-icestorm-0~20160913git266e758/icefuzz/cached_ramt.txt000066400000000000000000005643031276746530600230570ustar00rootroot00000000000000(0 0) Negative Clock bit (0 10) routing glb_netwk_2 glb2local_2 (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 (0 10) routing glb_netwk_7 glb2local_2 (0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 (0 11) routing glb_netwk_7 glb2local_2 (0 12) routing glb_netwk_2 glb2local_3 (0 12) routing glb_netwk_3 glb2local_3 (0 12) routing glb_netwk_6 glb2local_3 (0 12) routing glb_netwk_7 glb2local_3 (0 13) routing glb_netwk_1 glb2local_3 (0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 (0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/RE (0 14) routing glb_netwk_6 wire_bram/ram/RE (0 14) routing lc_trk_g2_4 wire_bram/ram/RE (0 14) routing lc_trk_g3_5 wire_bram/ram/RE (0 15) routing glb_netwk_2 wire_bram/ram/RE (0 15) routing glb_netwk_6 wire_bram/ram/RE (0 15) routing lc_trk_g1_5 wire_bram/ram/RE (0 15) routing lc_trk_g3_5 wire_bram/ram/RE (0 2) routing glb_netwk_2 wire_bram/ram/RCLK (0 2) routing glb_netwk_3 wire_bram/ram/RCLK (0 2) routing glb_netwk_6 wire_bram/ram/RCLK (0 2) routing glb_netwk_7 wire_bram/ram/RCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/RCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/RCLK (0 3) routing glb_netwk_1 wire_bram/ram/RCLK (0 3) routing glb_netwk_3 wire_bram/ram/RCLK (0 3) routing glb_netwk_5 wire_bram/ram/RCLK (0 3) routing glb_netwk_7 wire_bram/ram/RCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/RCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/RCLK (0 4) routing glb_netwk_5 wire_bram/ram/RCLKE (0 4) routing glb_netwk_7 wire_bram/ram/RCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/RCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/RCLKE (0 5) routing glb_netwk_3 wire_bram/ram/RCLKE (0 5) routing glb_netwk_7 wire_bram/ram/RCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE (0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 (0 6) routing glb_netwk_6 glb2local_0 (0 6) routing glb_netwk_7 glb2local_0 (0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 (0 7) routing glb_netwk_7 glb2local_0 (0 8) routing glb_netwk_2 glb2local_1 (0 8) routing glb_netwk_3 glb2local_1 (0 8) routing glb_netwk_6 glb2local_1 (0 8) routing glb_netwk_7 glb2local_1 (0 9) routing glb_netwk_1 glb2local_1 (0 9) routing glb_netwk_3 glb2local_1 (0 9) routing glb_netwk_5 glb2local_1 (0 9) routing glb_netwk_7 glb2local_1 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 (1 11) routing glb_netwk_7 glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 (1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 (1 13) routing glb_netwk_6 glb2local_3 (1 13) routing glb_netwk_7 glb2local_3 (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE (1 15) routing lc_trk_g0_4 wire_bram/ram/RE (1 15) routing lc_trk_g1_5 wire_bram/ram/RE (1 15) routing lc_trk_g2_4 wire_bram/ram/RE (1 15) routing lc_trk_g3_5 wire_bram/ram/RE (1 2) routing glb_netwk_4 wire_bram/ram/RCLK (1 2) routing glb_netwk_5 wire_bram/ram/RCLK (1 2) routing glb_netwk_6 wire_bram/ram/RCLK (1 2) routing glb_netwk_7 wire_bram/ram/RCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/RCLKE (1 5) routing lc_trk_g0_2 wire_bram/ram/RCLKE (1 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/RCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 (1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 (1 7) routing glb_netwk_6 glb2local_0 (1 7) routing glb_netwk_7 glb2local_0 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 (1 9) routing glb_netwk_4 glb2local_1 (1 9) routing glb_netwk_5 glb2local_1 (1 9) routing glb_netwk_6 glb2local_1 (1 9) routing glb_netwk_7 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 (10 0) routing sp4_v_t_45 sp4_h_r_1 (10 1) routing sp4_h_l_42 sp4_v_b_1 (10 1) routing sp4_h_r_8 sp4_v_b_1 (10 1) routing sp4_v_t_40 sp4_v_b_1 (10 1) routing sp4_v_t_47 sp4_v_b_1 (10 10) routing sp4_h_r_11 sp4_h_l_42 (10 10) routing sp4_h_r_4 sp4_h_l_42 (10 10) routing sp4_v_b_2 sp4_h_l_42 (10 10) routing sp4_v_t_36 sp4_h_l_42 (10 11) routing sp4_h_l_39 sp4_v_t_42 (10 11) routing sp4_h_r_1 sp4_v_t_42 (10 11) routing sp4_v_b_11 sp4_v_t_42 (10 11) routing sp4_v_b_4 sp4_v_t_42 (10 12) routing sp4_h_l_39 sp4_h_r_10 (10 12) routing sp4_h_l_42 sp4_h_r_10 (10 12) routing sp4_v_b_4 sp4_h_r_10 (10 12) routing sp4_v_t_40 sp4_h_r_10 (10 13) routing sp4_h_l_41 sp4_v_b_10 (10 13) routing sp4_h_r_5 sp4_v_b_10 (10 13) routing sp4_v_t_39 sp4_v_b_10 (10 13) routing sp4_v_t_42 sp4_v_b_10 (10 14) routing sp4_h_r_2 sp4_h_l_47 (10 14) routing sp4_h_r_7 sp4_h_l_47 (10 14) routing sp4_v_b_5 sp4_h_l_47 (10 14) routing sp4_v_t_41 sp4_h_l_47 (10 15) routing sp4_h_l_40 sp4_v_t_47 (10 15) routing sp4_h_r_4 sp4_v_t_47 (10 15) routing sp4_v_b_2 sp4_v_t_47 (10 15) routing sp4_v_b_7 sp4_v_t_47 (10 2) routing sp4_h_r_10 sp4_h_l_36 (10 2) routing sp4_h_r_5 sp4_h_l_36 (10 2) routing sp4_v_b_8 sp4_h_l_36 (10 2) routing sp4_v_t_42 sp4_h_l_36 (10 3) routing sp4_h_l_45 sp4_v_t_36 (10 3) routing sp4_h_r_7 sp4_v_t_36 (10 3) routing sp4_v_b_10 sp4_v_t_36 (10 3) routing sp4_v_b_5 sp4_v_t_36 (10 4) routing sp4_h_l_36 sp4_h_r_4 (10 4) routing sp4_h_l_45 sp4_h_r_4 (10 4) routing sp4_v_b_10 sp4_h_r_4 (10 4) routing sp4_v_t_46 sp4_h_r_4 (10 5) routing sp4_h_l_47 sp4_v_b_4 (10 5) routing sp4_h_r_11 sp4_v_b_4 (10 5) routing sp4_v_t_36 sp4_v_b_4 (10 5) routing sp4_v_t_45 sp4_v_b_4 (10 6) routing sp4_h_r_1 sp4_h_l_41 (10 6) routing sp4_h_r_8 sp4_h_l_41 (10 6) routing sp4_v_b_11 sp4_h_l_41 (10 6) routing sp4_v_t_47 sp4_h_l_41 (10 7) routing sp4_h_l_46 sp4_v_t_41 (10 7) routing sp4_h_r_10 sp4_v_t_41 (10 7) routing sp4_v_b_1 sp4_v_t_41 (10 7) routing sp4_v_b_8 sp4_v_t_41 (10 8) routing sp4_h_l_41 sp4_h_r_7 (10 8) routing sp4_h_l_46 sp4_h_r_7 (10 8) routing sp4_v_b_1 sp4_h_r_7 (10 8) routing sp4_v_t_39 sp4_h_r_7 (10 9) routing sp4_h_l_36 sp4_v_b_7 (10 9) routing sp4_h_r_2 sp4_v_b_7 (10 9) routing sp4_v_t_41 sp4_v_b_7 (10 9) routing sp4_v_t_46 sp4_v_b_7 (11 0) routing sp4_h_l_45 sp4_v_b_2 (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 (11 1) routing sp4_h_l_39 sp4_h_r_2 (11 1) routing sp4_h_l_43 sp4_h_r_2 (11 1) routing sp4_v_b_2 sp4_h_r_2 (11 1) routing sp4_v_b_8 sp4_h_r_2 (11 10) routing sp4_h_l_38 sp4_v_t_45 (11 10) routing sp4_h_r_2 sp4_v_t_45 (11 10) routing sp4_v_b_0 sp4_v_t_45 (11 10) routing sp4_v_b_5 sp4_v_t_45 (11 11) routing sp4_h_r_0 sp4_h_l_45 (11 11) routing sp4_h_r_8 sp4_h_l_45 (11 11) routing sp4_v_t_39 sp4_h_l_45 (11 11) routing sp4_v_t_45 sp4_h_l_45 (11 12) routing sp4_h_l_40 sp4_v_b_11 (11 12) routing sp4_h_r_6 sp4_v_b_11 (11 12) routing sp4_v_t_38 sp4_v_b_11 (11 12) routing sp4_v_t_45 sp4_v_b_11 (11 13) routing sp4_h_l_38 sp4_h_r_11 (11 13) routing sp4_h_l_46 sp4_h_r_11 (11 13) routing sp4_v_b_11 sp4_h_r_11 (11 13) routing sp4_v_b_5 sp4_h_r_11 (11 14) routing sp4_h_l_43 sp4_v_t_46 (11 14) routing sp4_h_r_5 sp4_v_t_46 (11 14) routing sp4_v_b_3 sp4_v_t_46 (11 14) routing sp4_v_b_8 sp4_v_t_46 (11 15) routing sp4_h_r_11 sp4_h_l_46 (11 15) routing sp4_h_r_3 sp4_h_l_46 (11 15) routing sp4_v_t_40 sp4_h_l_46 (11 15) routing sp4_v_t_46 sp4_h_l_46 (11 2) routing sp4_h_l_44 sp4_v_t_39 (11 2) routing sp4_h_r_8 sp4_v_t_39 (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 (11 3) routing sp4_h_r_2 sp4_h_l_39 (11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 (11 4) routing sp4_h_r_0 sp4_v_b_5 (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 (11 5) routing sp4_h_l_40 sp4_h_r_5 (11 5) routing sp4_h_l_44 sp4_h_r_5 (11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 (11 6) routing sp4_h_r_11 sp4_v_t_40 (11 6) routing sp4_v_b_2 sp4_v_t_40 (11 6) routing sp4_v_b_9 sp4_v_t_40 (11 7) routing sp4_h_r_5 sp4_h_l_40 (11 7) routing sp4_h_r_9 sp4_h_l_40 (11 7) routing sp4_v_t_40 sp4_h_l_40 (11 7) routing sp4_v_t_46 sp4_h_l_40 (11 8) routing sp4_h_l_39 sp4_v_b_8 (11 8) routing sp4_h_r_3 sp4_v_b_8 (11 8) routing sp4_v_t_37 sp4_v_b_8 (11 8) routing sp4_v_t_40 sp4_v_b_8 (11 9) routing sp4_h_l_37 sp4_h_r_8 (11 9) routing sp4_h_l_45 sp4_h_r_8 (11 9) routing sp4_v_b_2 sp4_h_r_8 (11 9) routing sp4_v_b_8 sp4_h_r_8 (12 0) routing sp4_h_l_46 sp4_h_r_2 (12 0) routing sp4_v_b_2 sp4_h_r_2 (12 0) routing sp4_v_b_8 sp4_h_r_2 (12 0) routing sp4_v_t_39 sp4_h_r_2 (12 1) routing sp4_h_l_39 sp4_v_b_2 (12 1) routing sp4_h_l_45 sp4_v_b_2 (12 1) routing sp4_h_r_2 sp4_v_b_2 (12 1) routing sp4_v_t_46 sp4_v_b_2 (12 10) routing sp4_h_r_5 sp4_h_l_45 (12 10) routing sp4_v_b_8 sp4_h_l_45 (12 10) routing sp4_v_t_39 sp4_h_l_45 (12 10) routing sp4_v_t_45 sp4_h_l_45 (12 11) routing sp4_h_l_45 sp4_v_t_45 (12 11) routing sp4_h_r_2 sp4_v_t_45 (12 11) routing sp4_h_r_8 sp4_v_t_45 (12 11) routing sp4_v_b_5 sp4_v_t_45 (12 12) routing sp4_h_l_45 sp4_h_r_11 (12 12) routing sp4_v_b_11 sp4_h_r_11 (12 12) routing sp4_v_b_5 sp4_h_r_11 (12 12) routing sp4_v_t_46 sp4_h_r_11 (12 13) routing sp4_h_l_40 sp4_v_b_11 (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 (12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 (12 14) routing sp4_v_t_46 sp4_h_l_46 (12 15) routing sp4_h_l_46 sp4_v_t_46 (12 15) routing sp4_h_r_11 sp4_v_t_46 (12 15) routing sp4_h_r_5 sp4_v_t_46 (12 15) routing sp4_v_b_8 sp4_v_t_46 (12 2) routing sp4_h_r_11 sp4_h_l_39 (12 2) routing sp4_v_b_2 sp4_h_l_39 (12 2) routing sp4_v_t_39 sp4_h_l_39 (12 2) routing sp4_v_t_45 sp4_h_l_39 (12 3) routing sp4_h_l_39 sp4_v_t_39 (12 3) routing sp4_h_r_2 sp4_v_t_39 (12 3) routing sp4_h_r_8 sp4_v_t_39 (12 3) routing sp4_v_b_11 sp4_v_t_39 (12 4) routing sp4_h_l_39 sp4_h_r_5 (12 4) routing sp4_v_b_11 sp4_h_r_5 (12 4) routing sp4_v_b_5 sp4_h_r_5 (12 4) routing sp4_v_t_40 sp4_h_r_5 (12 5) routing sp4_h_l_40 sp4_v_b_5 (12 5) routing sp4_h_l_46 sp4_v_b_5 (12 5) routing sp4_h_r_5 sp4_v_b_5 (12 5) routing sp4_v_t_39 sp4_v_b_5 (12 6) routing sp4_h_r_2 sp4_h_l_40 (12 6) routing sp4_v_b_5 sp4_h_l_40 (12 6) routing sp4_v_t_40 sp4_h_l_40 (12 6) routing sp4_v_t_46 sp4_h_l_40 (12 7) routing sp4_h_l_40 sp4_v_t_40 (12 7) routing sp4_h_r_11 sp4_v_t_40 (12 7) routing sp4_h_r_5 sp4_v_t_40 (12 7) routing sp4_v_b_2 sp4_v_t_40 (12 8) routing sp4_h_l_40 sp4_h_r_8 (12 8) routing sp4_v_b_2 sp4_h_r_8 (12 8) routing sp4_v_b_8 sp4_h_r_8 (12 8) routing sp4_v_t_45 sp4_h_r_8 (12 9) routing sp4_h_l_39 sp4_v_b_8 (12 9) routing sp4_h_l_45 sp4_v_b_8 (12 9) routing sp4_h_r_8 sp4_v_b_8 (12 9) routing sp4_v_t_40 sp4_v_b_8 (13 0) routing sp4_h_l_39 sp4_v_b_2 (13 0) routing sp4_h_l_45 sp4_v_b_2 (13 0) routing sp4_v_t_39 sp4_v_b_2 (13 0) routing sp4_v_t_43 sp4_v_b_2 (13 1) routing sp4_h_l_43 sp4_h_r_2 (13 1) routing sp4_h_l_46 sp4_h_r_2 (13 1) routing sp4_v_b_8 sp4_h_r_2 (13 1) routing sp4_v_t_44 sp4_h_r_2 (13 10) routing sp4_h_r_2 sp4_v_t_45 (13 10) routing sp4_h_r_8 sp4_v_t_45 (13 10) routing sp4_v_b_0 sp4_v_t_45 (13 10) routing sp4_v_b_8 sp4_v_t_45 (13 11) routing sp4_h_r_0 sp4_h_l_45 (13 11) routing sp4_h_r_5 sp4_h_l_45 (13 11) routing sp4_v_b_3 sp4_h_l_45 (13 11) routing sp4_v_t_39 sp4_h_l_45 (13 12) routing sp4_h_l_40 sp4_v_b_11 (13 12) routing sp4_h_l_46 sp4_v_b_11 (13 12) routing sp4_v_t_38 sp4_v_b_11 (13 12) routing sp4_v_t_46 sp4_v_b_11 (13 13) routing sp4_h_l_38 sp4_h_r_11 (13 13) routing sp4_h_l_45 sp4_h_r_11 (13 13) routing sp4_v_b_5 sp4_h_r_11 (13 13) routing sp4_v_t_43 sp4_h_r_11 (13 14) routing sp4_h_r_11 sp4_v_t_46 (13 14) routing sp4_h_r_5 sp4_v_t_46 (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 (13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 (13 2) routing sp4_h_r_8 sp4_v_t_39 (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 (13 3) routing sp4_h_r_11 sp4_h_l_39 (13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 (13 4) routing sp4_h_l_46 sp4_v_b_5 (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 (13 5) routing sp4_h_l_39 sp4_h_r_5 (13 5) routing sp4_h_l_44 sp4_h_r_5 (13 5) routing sp4_v_b_11 sp4_h_r_5 (13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 (13 6) routing sp4_h_r_5 sp4_v_t_40 (13 6) routing sp4_v_b_5 sp4_v_t_40 (13 6) routing sp4_v_b_9 sp4_v_t_40 (13 7) routing sp4_h_r_2 sp4_h_l_40 (13 7) routing sp4_h_r_9 sp4_h_l_40 (13 7) routing sp4_v_b_0 sp4_h_l_40 (13 7) routing sp4_v_t_46 sp4_h_l_40 (13 8) routing sp4_h_l_39 sp4_v_b_8 (13 8) routing sp4_h_l_45 sp4_v_b_8 (13 8) routing sp4_v_t_37 sp4_v_b_8 (13 8) routing sp4_v_t_45 sp4_v_b_8 (13 9) routing sp4_h_l_37 sp4_h_r_8 (13 9) routing sp4_h_l_40 sp4_h_r_8 (13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 (14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_l_5 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 (14 1) routing sp12_h_r_0 lc_trk_g0_0 (14 1) routing sp12_h_r_16 lc_trk_g0_0 (14 1) routing sp4_h_l_5 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing top_op_0 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 (14 10) routing rgt_op_4 lc_trk_g2_4 (14 10) routing sp12_v_t_3 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 (14 10) routing sp4_v_b_28 lc_trk_g2_4 (14 10) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing bnl_op_4 lc_trk_g2_4 (14 11) routing sp12_v_t_19 lc_trk_g2_4 (14 11) routing sp12_v_t_3 lc_trk_g2_4 (14 11) routing sp4_h_l_17 lc_trk_g2_4 (14 11) routing sp4_h_r_44 lc_trk_g2_4 (14 11) routing sp4_r_v_b_36 lc_trk_g2_4 (14 11) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing tnl_op_4 lc_trk_g2_4 (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 (14 12) routing sp12_v_b_0 lc_trk_g3_0 (14 12) routing sp4_h_l_21 lc_trk_g3_0 (14 12) routing sp4_h_l_29 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 12) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 (14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 (14 13) routing sp4_h_l_13 lc_trk_g3_0 (14 13) routing sp4_h_l_29 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing tnl_op_0 lc_trk_g3_0 (14 14) routing bnl_op_4 lc_trk_g3_4 (14 14) routing rgt_op_4 lc_trk_g3_4 (14 14) routing sp12_v_t_3 lc_trk_g3_4 (14 14) routing sp4_h_r_36 lc_trk_g3_4 (14 14) routing sp4_h_r_44 lc_trk_g3_4 (14 14) routing sp4_v_b_28 lc_trk_g3_4 (14 14) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing bnl_op_4 lc_trk_g3_4 (14 15) routing sp12_v_t_19 lc_trk_g3_4 (14 15) routing sp12_v_t_3 lc_trk_g3_4 (14 15) routing sp4_h_l_17 lc_trk_g3_4 (14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing tnl_op_4 lc_trk_g3_4 (14 2) routing bnr_op_4 lc_trk_g0_4 (14 2) routing lft_op_4 lc_trk_g0_4 (14 2) routing sp12_h_l_3 lc_trk_g0_4 (14 2) routing sp4_h_r_12 lc_trk_g0_4 (14 2) routing sp4_h_r_20 lc_trk_g0_4 (14 2) routing sp4_v_b_4 lc_trk_g0_4 (14 2) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 (14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 (14 3) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing top_op_4 lc_trk_g0_4 (14 4) routing bnr_op_0 lc_trk_g1_0 (14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_l_5 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 (14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 (14 5) routing sp12_h_r_16 lc_trk_g1_0 (14 5) routing sp4_h_l_5 lc_trk_g1_0 (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing top_op_0 lc_trk_g1_0 (14 6) routing bnr_op_4 lc_trk_g1_4 (14 6) routing lft_op_4 lc_trk_g1_4 (14 6) routing sp12_h_l_3 lc_trk_g1_4 (14 6) routing sp4_h_r_12 lc_trk_g1_4 (14 6) routing sp4_h_r_20 lc_trk_g1_4 (14 6) routing sp4_v_b_4 lc_trk_g1_4 (14 6) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing top_op_4 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 (14 8) routing rgt_op_0 lc_trk_g2_0 (14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_l_21 lc_trk_g2_0 (14 8) routing sp4_h_l_29 lc_trk_g2_0 (14 8) routing sp4_v_t_13 lc_trk_g2_0 (14 8) routing sp4_v_t_21 lc_trk_g2_0 (14 9) routing bnl_op_0 lc_trk_g2_0 (14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 (14 9) routing sp4_h_l_13 lc_trk_g2_0 (14 9) routing sp4_h_l_29 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_t_21 lc_trk_g2_0 (14 9) routing tnl_op_0 lc_trk_g2_0 (15 0) routing lft_op_1 lc_trk_g0_1 (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_b_17 lc_trk_g0_1 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_l_5 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 (15 1) routing sp4_v_b_16 lc_trk_g0_0 (15 1) routing top_op_0 lc_trk_g0_0 (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 (15 10) routing sp4_h_l_16 lc_trk_g2_5 (15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_t_3 lc_trk_g2_4 (15 11) routing sp4_h_l_17 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 (15 11) routing sp4_h_r_44 lc_trk_g2_4 (15 11) routing sp4_v_t_33 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 (15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 (15 12) routing sp4_h_l_20 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 (15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 (15 13) routing sp4_h_l_13 lc_trk_g3_0 (15 13) routing sp4_h_l_21 lc_trk_g3_0 (15 13) routing sp4_h_l_29 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 (15 13) routing tnr_op_0 lc_trk_g3_0 (15 14) routing rgt_op_5 lc_trk_g3_5 (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_l_16 lc_trk_g3_5 (15 14) routing sp4_h_r_37 lc_trk_g3_5 (15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_b_45 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 (15 15) routing sp12_v_t_3 lc_trk_g3_4 (15 15) routing sp4_h_l_17 lc_trk_g3_4 (15 15) routing sp4_h_r_36 lc_trk_g3_4 (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_t_33 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 (15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing lft_op_5 lc_trk_g0_5 (15 2) routing sp12_h_r_5 lc_trk_g0_5 (15 2) routing sp4_h_l_8 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_r_12 lc_trk_g0_4 (15 3) routing sp4_h_r_20 lc_trk_g0_4 (15 3) routing sp4_h_r_4 lc_trk_g0_4 (15 3) routing sp4_v_b_20 lc_trk_g0_4 (15 3) routing top_op_4 lc_trk_g0_4 (15 4) routing lft_op_1 lc_trk_g1_1 (15 4) routing sp12_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_17 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_b_17 lc_trk_g1_1 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_l_5 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_b_16 lc_trk_g1_0 (15 5) routing top_op_0 lc_trk_g1_0 (15 6) routing lft_op_5 lc_trk_g1_5 (15 6) routing sp12_h_r_5 lc_trk_g1_5 (15 6) routing sp4_h_l_8 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_r_12 lc_trk_g1_4 (15 7) routing sp4_h_r_20 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 (15 7) routing top_op_4 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_20 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_l_13 lc_trk_g2_0 (15 9) routing sp4_h_l_21 lc_trk_g2_0 (15 9) routing sp4_h_l_29 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 (16 0) routing sp12_h_l_6 lc_trk_g0_1 (16 0) routing sp12_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_17 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 (16 1) routing sp12_h_r_16 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_l_5 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 (16 1) routing sp4_h_r_8 lc_trk_g0_0 (16 1) routing sp4_v_b_0 lc_trk_g0_0 (16 1) routing sp4_v_b_16 lc_trk_g0_0 (16 1) routing sp4_v_b_8 lc_trk_g0_0 (16 10) routing sp12_v_b_21 lc_trk_g2_5 (16 10) routing sp12_v_t_10 lc_trk_g2_5 (16 10) routing sp4_h_l_16 lc_trk_g2_5 (16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 (16 10) routing sp4_v_b_37 lc_trk_g2_5 (16 10) routing sp4_v_b_45 lc_trk_g2_5 (16 11) routing sp12_v_b_12 lc_trk_g2_4 (16 11) routing sp12_v_t_19 lc_trk_g2_4 (16 11) routing sp4_h_l_17 lc_trk_g2_4 (16 11) routing sp4_h_r_36 lc_trk_g2_4 (16 11) routing sp4_h_r_44 lc_trk_g2_4 (16 11) routing sp4_v_b_28 lc_trk_g2_4 (16 11) routing sp4_v_t_25 lc_trk_g2_4 (16 11) routing sp4_v_t_33 lc_trk_g2_4 (16 12) routing sp12_v_b_17 lc_trk_g3_1 (16 12) routing sp12_v_b_9 lc_trk_g3_1 (16 12) routing sp4_h_l_20 lc_trk_g3_1 (16 12) routing sp4_h_l_28 lc_trk_g3_1 (16 12) routing sp4_h_r_25 lc_trk_g3_1 (16 12) routing sp4_v_b_25 lc_trk_g3_1 (16 12) routing sp4_v_b_33 lc_trk_g3_1 (16 12) routing sp4_v_b_41 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 (16 13) routing sp4_h_l_13 lc_trk_g3_0 (16 13) routing sp4_h_l_21 lc_trk_g3_0 (16 13) routing sp4_h_l_29 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 (16 13) routing sp4_v_t_13 lc_trk_g3_0 (16 13) routing sp4_v_t_21 lc_trk_g3_0 (16 14) routing sp12_v_b_21 lc_trk_g3_5 (16 14) routing sp12_v_t_10 lc_trk_g3_5 (16 14) routing sp4_h_l_16 lc_trk_g3_5 (16 14) routing sp4_h_r_37 lc_trk_g3_5 (16 14) routing sp4_h_r_45 lc_trk_g3_5 (16 14) routing sp4_v_b_29 lc_trk_g3_5 (16 14) routing sp4_v_b_37 lc_trk_g3_5 (16 14) routing sp4_v_b_45 lc_trk_g3_5 (16 15) routing sp12_v_b_12 lc_trk_g3_4 (16 15) routing sp12_v_t_19 lc_trk_g3_4 (16 15) routing sp4_h_l_17 lc_trk_g3_4 (16 15) routing sp4_h_r_36 lc_trk_g3_4 (16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 15) routing sp4_v_t_33 lc_trk_g3_4 (16 2) routing sp12_h_l_18 lc_trk_g0_5 (16 2) routing sp12_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_l_8 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_5 lc_trk_g0_5 (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 (16 3) routing sp12_h_r_12 lc_trk_g0_4 (16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_12 lc_trk_g0_4 (16 3) routing sp4_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 (16 3) routing sp4_v_b_20 lc_trk_g0_4 (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 3) routing sp4_v_t_1 lc_trk_g0_4 (16 4) routing sp12_h_l_6 lc_trk_g1_1 (16 4) routing sp12_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_17 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 5) routing sp12_h_r_16 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_l_5 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_8 lc_trk_g1_0 (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 (16 6) routing sp12_h_l_18 lc_trk_g1_5 (16 6) routing sp12_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_l_8 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 (16 6) routing sp4_v_b_13 lc_trk_g1_5 (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 6) routing sp4_v_t_8 lc_trk_g1_5 (16 7) routing sp12_h_r_12 lc_trk_g1_4 (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_12 lc_trk_g1_4 (16 7) routing sp4_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_20 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 (16 7) routing sp4_v_t_1 lc_trk_g1_4 (16 8) routing sp12_v_b_17 lc_trk_g2_1 (16 8) routing sp12_v_b_9 lc_trk_g2_1 (16 8) routing sp4_h_l_20 lc_trk_g2_1 (16 8) routing sp4_h_l_28 lc_trk_g2_1 (16 8) routing sp4_h_r_25 lc_trk_g2_1 (16 8) routing sp4_v_b_25 lc_trk_g2_1 (16 8) routing sp4_v_b_33 lc_trk_g2_1 (16 8) routing sp4_v_b_41 lc_trk_g2_1 (16 9) routing sp12_v_b_16 lc_trk_g2_0 (16 9) routing sp12_v_t_7 lc_trk_g2_0 (16 9) routing sp4_h_l_13 lc_trk_g2_0 (16 9) routing sp4_h_l_21 lc_trk_g2_0 (16 9) routing sp4_h_l_29 lc_trk_g2_0 (16 9) routing sp4_v_b_40 lc_trk_g2_0 (16 9) routing sp4_v_t_13 lc_trk_g2_0 (16 9) routing sp4_v_t_21 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => top_op_0 lc_trk_g0_0 (17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => top_op_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_r_17 lc_trk_g0_1 (18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp12_h_r_17 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 (18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_b_5 lc_trk_g2_5 (18 10) routing sp4_h_r_37 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_29 lc_trk_g2_5 (18 10) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing bnl_op_5 lc_trk_g2_5 (18 11) routing sp12_v_b_21 lc_trk_g2_5 (18 11) routing sp12_v_b_5 lc_trk_g2_5 (18 11) routing sp4_h_l_16 lc_trk_g2_5 (18 11) routing sp4_h_r_45 lc_trk_g2_5 (18 11) routing sp4_r_v_b_37 lc_trk_g2_5 (18 11) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 (18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 (18 12) routing sp4_h_l_20 lc_trk_g3_1 (18 12) routing sp4_h_l_28 lc_trk_g3_1 (18 12) routing sp4_v_b_25 lc_trk_g3_1 (18 12) routing sp4_v_b_33 lc_trk_g3_1 (18 13) routing bnl_op_1 lc_trk_g3_1 (18 13) routing sp12_v_b_1 lc_trk_g3_1 (18 13) routing sp12_v_b_17 lc_trk_g3_1 (18 13) routing sp4_h_l_28 lc_trk_g3_1 (18 13) routing sp4_h_r_25 lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 lc_trk_g3_1 (18 13) routing sp4_v_b_33 lc_trk_g3_1 (18 13) routing tnl_op_1 lc_trk_g3_1 (18 14) routing bnl_op_5 lc_trk_g3_5 (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 (18 14) routing sp4_h_r_37 lc_trk_g3_5 (18 14) routing sp4_h_r_45 lc_trk_g3_5 (18 14) routing sp4_v_b_29 lc_trk_g3_5 (18 14) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing bnl_op_5 lc_trk_g3_5 (18 15) routing sp12_v_b_21 lc_trk_g3_5 (18 15) routing sp12_v_b_5 lc_trk_g3_5 (18 15) routing sp4_h_l_16 lc_trk_g3_5 (18 15) routing sp4_h_r_45 lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 lc_trk_g3_5 (18 15) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing tnl_op_5 lc_trk_g3_5 (18 2) routing bnr_op_5 lc_trk_g0_5 (18 2) routing lft_op_5 lc_trk_g0_5 (18 2) routing sp12_h_r_5 lc_trk_g0_5 (18 2) routing sp4_h_l_8 lc_trk_g0_5 (18 2) routing sp4_h_r_13 lc_trk_g0_5 (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 (18 3) routing sp12_h_l_18 lc_trk_g0_5 (18 3) routing sp12_h_r_5 lc_trk_g0_5 (18 3) routing sp4_h_l_8 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 (18 3) routing sp4_v_b_13 lc_trk_g0_5 (18 4) routing bnr_op_1 lc_trk_g1_1 (18 4) routing lft_op_1 lc_trk_g1_1 (18 4) routing sp12_h_r_1 lc_trk_g1_1 (18 4) routing sp4_h_r_17 lc_trk_g1_1 (18 4) routing sp4_h_r_9 lc_trk_g1_1 (18 4) routing sp4_v_b_1 lc_trk_g1_1 (18 4) routing sp4_v_b_9 lc_trk_g1_1 (18 5) routing bnr_op_1 lc_trk_g1_1 (18 5) routing sp12_h_r_1 lc_trk_g1_1 (18 5) routing sp12_h_r_17 lc_trk_g1_1 (18 5) routing sp4_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_r_17 lc_trk_g1_1 (18 5) routing sp4_r_v_b_25 lc_trk_g1_1 (18 5) routing sp4_v_b_9 lc_trk_g1_1 (18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 (18 6) routing sp12_h_r_5 lc_trk_g1_5 (18 6) routing sp4_h_l_8 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 (18 7) routing sp12_h_l_18 lc_trk_g1_5 (18 7) routing sp12_h_r_5 lc_trk_g1_5 (18 7) routing sp4_h_l_8 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_20 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 (18 8) routing sp4_v_b_25 lc_trk_g2_1 (18 8) routing sp4_v_b_33 lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 (18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_b_17 lc_trk_g2_1 (18 9) routing sp4_h_l_28 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 (18 9) routing sp4_r_v_b_33 lc_trk_g2_1 (18 9) routing sp4_v_b_33 lc_trk_g2_1 (18 9) routing tnl_op_1 lc_trk_g2_1 (19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13 (19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 (19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 (19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 (19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13 (19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 (19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 (19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 (19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2 (19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 (19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 (19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 (19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 (19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7 (19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 (19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_b_17 sp4_v_b_20 (2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5 (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/RCLK (2 3) routing lc_trk_g0_0 wire_bram/ram/RCLK (2 3) routing lc_trk_g1_1 wire_bram/ram/RCLK (2 3) routing lc_trk_g2_0 wire_bram/ram/RCLK (2 3) routing lc_trk_g3_1 wire_bram/ram/RCLK (2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7 (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 (21 0) routing bnr_op_3 lc_trk_g0_3 (21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_l_0 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_h_r_19 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 (21 1) routing sp12_h_l_0 lc_trk_g0_3 (21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp4_h_r_19 lc_trk_g0_3 (21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 (21 1) routing sp4_v_b_11 lc_trk_g0_3 (21 10) routing bnl_op_7 lc_trk_g2_7 (21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_b_7 lc_trk_g2_7 (21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_t_18 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing bnl_op_7 lc_trk_g2_7 (21 11) routing sp12_v_b_23 lc_trk_g2_7 (21 11) routing sp12_v_b_7 lc_trk_g2_7 (21 11) routing sp4_h_l_18 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_t_0 lc_trk_g3_3 (21 12) routing sp4_h_l_30 lc_trk_g3_3 (21 12) routing sp4_h_r_35 lc_trk_g3_3 (21 12) routing sp4_v_t_14 lc_trk_g3_3 (21 12) routing sp4_v_t_22 lc_trk_g3_3 (21 13) routing bnl_op_3 lc_trk_g3_3 (21 13) routing sp12_v_t_0 lc_trk_g3_3 (21 13) routing sp12_v_t_16 lc_trk_g3_3 (21 13) routing sp4_h_l_30 lc_trk_g3_3 (21 13) routing sp4_h_r_27 lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 lc_trk_g3_3 (21 13) routing sp4_v_t_22 lc_trk_g3_3 (21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_b_7 lc_trk_g3_7 (21 14) routing sp4_h_l_26 lc_trk_g3_7 (21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_t_18 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_b_23 lc_trk_g3_7 (21 15) routing sp12_v_b_7 lc_trk_g3_7 (21 15) routing sp4_h_l_18 lc_trk_g3_7 (21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 (21 2) routing sp12_h_l_4 lc_trk_g0_7 (21 2) routing sp4_h_l_10 lc_trk_g0_7 (21 2) routing sp4_h_l_2 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_4 lc_trk_g0_7 (21 3) routing sp12_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_l_10 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 (21 3) routing sp4_v_t_2 lc_trk_g0_7 (21 4) routing bnr_op_3 lc_trk_g1_3 (21 4) routing lft_op_3 lc_trk_g1_3 (21 4) routing sp12_h_l_0 lc_trk_g1_3 (21 4) routing sp4_h_r_11 lc_trk_g1_3 (21 4) routing sp4_h_r_19 lc_trk_g1_3 (21 4) routing sp4_v_b_11 lc_trk_g1_3 (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_0 lc_trk_g1_3 (21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp4_h_r_19 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 (21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_l_4 lc_trk_g1_7 (21 6) routing sp4_h_l_10 lc_trk_g1_7 (21 6) routing sp4_h_l_2 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 (21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_4 lc_trk_g1_7 (21 7) routing sp12_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_l_10 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_t_0 lc_trk_g2_3 (21 8) routing sp4_h_l_30 lc_trk_g2_3 (21 8) routing sp4_h_r_35 lc_trk_g2_3 (21 8) routing sp4_v_t_14 lc_trk_g2_3 (21 8) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing bnl_op_3 lc_trk_g2_3 (21 9) routing sp12_v_t_0 lc_trk_g2_3 (21 9) routing sp12_v_t_16 lc_trk_g2_3 (21 9) routing sp4_h_l_30 lc_trk_g2_3 (21 9) routing sp4_h_r_27 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 (22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 (22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 lc_trk_g0_3 (23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_19 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_19 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 (23 1) routing sp12_h_r_10 lc_trk_g0_2 (23 1) routing sp12_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_l_7 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 (23 1) routing sp4_v_b_10 lc_trk_g0_2 (23 1) routing sp4_v_b_2 lc_trk_g0_2 (23 1) routing sp4_v_t_7 lc_trk_g0_2 (23 10) routing sp12_v_b_23 lc_trk_g2_7 (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp4_h_l_18 lc_trk_g2_7 (23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_47 lc_trk_g2_7 (23 10) routing sp4_v_t_18 lc_trk_g2_7 (23 10) routing sp4_v_t_26 lc_trk_g2_7 (23 11) routing sp12_v_b_14 lc_trk_g2_6 (23 11) routing sp12_v_t_21 lc_trk_g2_6 (23 11) routing sp4_h_l_27 lc_trk_g2_6 (23 11) routing sp4_h_r_30 lc_trk_g2_6 (23 11) routing sp4_h_r_46 lc_trk_g2_6 (23 11) routing sp4_v_b_30 lc_trk_g2_6 (23 11) routing sp4_v_b_38 lc_trk_g2_6 (23 11) routing sp4_v_b_46 lc_trk_g2_6 (23 12) routing sp12_v_b_11 lc_trk_g3_3 (23 12) routing sp12_v_t_16 lc_trk_g3_3 (23 12) routing sp4_h_l_30 lc_trk_g3_3 (23 12) routing sp4_h_r_27 lc_trk_g3_3 (23 12) routing sp4_h_r_35 lc_trk_g3_3 (23 12) routing sp4_v_t_14 lc_trk_g3_3 (23 12) routing sp4_v_t_22 lc_trk_g3_3 (23 12) routing sp4_v_t_30 lc_trk_g3_3 (23 13) routing sp12_v_t_17 lc_trk_g3_2 (23 13) routing sp12_v_t_9 lc_trk_g3_2 (23 13) routing sp4_h_l_15 lc_trk_g3_2 (23 13) routing sp4_h_r_34 lc_trk_g3_2 (23 13) routing sp4_h_r_42 lc_trk_g3_2 (23 13) routing sp4_v_b_26 lc_trk_g3_2 (23 13) routing sp4_v_t_23 lc_trk_g3_2 (23 13) routing sp4_v_t_31 lc_trk_g3_2 (23 14) routing sp12_v_b_23 lc_trk_g3_7 (23 14) routing sp12_v_t_12 lc_trk_g3_7 (23 14) routing sp4_h_l_18 lc_trk_g3_7 (23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_47 lc_trk_g3_7 (23 14) routing sp4_v_t_18 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 15) routing sp12_v_b_14 lc_trk_g3_6 (23 15) routing sp12_v_t_21 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 (23 15) routing sp4_h_r_30 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_30 lc_trk_g3_6 (23 15) routing sp4_v_b_38 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 (23 2) routing sp12_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_l_10 lc_trk_g0_7 (23 2) routing sp4_h_l_2 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_10 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 (23 3) routing sp12_h_l_13 lc_trk_g0_6 (23 3) routing sp12_h_l_21 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 (23 3) routing sp4_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_r_6 lc_trk_g0_6 (23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_22 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 (23 4) routing sp12_h_l_16 lc_trk_g1_3 (23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_19 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 (23 4) routing sp4_v_b_11 lc_trk_g1_3 (23 4) routing sp4_v_b_19 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 5) routing sp12_h_r_10 lc_trk_g1_2 (23 5) routing sp12_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_l_7 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 (23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 (23 6) routing sp12_h_l_12 lc_trk_g1_7 (23 6) routing sp12_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_l_10 lc_trk_g1_7 (23 6) routing sp4_h_l_2 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_10 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 (23 7) routing sp12_h_l_13 lc_trk_g1_6 (23 7) routing sp12_h_l_21 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_22 lc_trk_g1_6 (23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_14 lc_trk_g1_6 (23 7) routing sp4_v_b_22 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 8) routing sp12_v_b_11 lc_trk_g2_3 (23 8) routing sp12_v_t_16 lc_trk_g2_3 (23 8) routing sp4_h_l_30 lc_trk_g2_3 (23 8) routing sp4_h_r_27 lc_trk_g2_3 (23 8) routing sp4_h_r_35 lc_trk_g2_3 (23 8) routing sp4_v_t_14 lc_trk_g2_3 (23 8) routing sp4_v_t_22 lc_trk_g2_3 (23 8) routing sp4_v_t_30 lc_trk_g2_3 (23 9) routing sp12_v_t_17 lc_trk_g2_2 (23 9) routing sp12_v_t_9 lc_trk_g2_2 (23 9) routing sp4_h_l_15 lc_trk_g2_2 (23 9) routing sp4_h_r_34 lc_trk_g2_2 (23 9) routing sp4_h_r_42 lc_trk_g2_2 (23 9) routing sp4_v_b_26 lc_trk_g2_2 (23 9) routing sp4_v_t_23 lc_trk_g2_2 (23 9) routing sp4_v_t_31 lc_trk_g2_2 (24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_l_0 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_19 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_b_19 lc_trk_g0_3 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_r_2 lc_trk_g0_2 (24 1) routing sp4_h_l_7 lc_trk_g0_2 (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_t_7 lc_trk_g0_2 (24 1) routing top_op_2 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_b_7 lc_trk_g2_7 (24 10) routing sp4_h_l_18 lc_trk_g2_7 (24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_b_47 lc_trk_g2_7 (24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_b_6 lc_trk_g2_6 (24 11) routing sp4_h_l_27 lc_trk_g2_6 (24 11) routing sp4_h_r_30 lc_trk_g2_6 (24 11) routing sp4_h_r_46 lc_trk_g2_6 (24 11) routing sp4_v_b_46 lc_trk_g2_6 (24 11) routing tnl_op_6 lc_trk_g2_6 (24 11) routing tnr_op_6 lc_trk_g2_6 (24 12) routing rgt_op_3 lc_trk_g3_3 (24 12) routing sp12_v_t_0 lc_trk_g3_3 (24 12) routing sp4_h_l_30 lc_trk_g3_3 (24 12) routing sp4_h_r_27 lc_trk_g3_3 (24 12) routing sp4_h_r_35 lc_trk_g3_3 (24 12) routing sp4_v_t_30 lc_trk_g3_3 (24 12) routing tnl_op_3 lc_trk_g3_3 (24 12) routing tnr_op_3 lc_trk_g3_3 (24 13) routing rgt_op_2 lc_trk_g3_2 (24 13) routing sp12_v_b_2 lc_trk_g3_2 (24 13) routing sp4_h_l_15 lc_trk_g3_2 (24 13) routing sp4_h_r_34 lc_trk_g3_2 (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 (24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_b_7 lc_trk_g3_7 (24 14) routing sp4_h_l_18 lc_trk_g3_7 (24 14) routing sp4_h_l_26 lc_trk_g3_7 (24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_b_47 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 (24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_b_6 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 (24 15) routing sp4_h_r_30 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 (24 2) routing sp12_h_l_4 lc_trk_g0_7 (24 2) routing sp4_h_l_10 lc_trk_g0_7 (24 2) routing sp4_h_l_2 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_t_10 lc_trk_g0_7 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_3 lc_trk_g0_6 (24 3) routing sp4_h_r_22 lc_trk_g0_6 (24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_b_22 lc_trk_g0_6 (24 3) routing top_op_6 lc_trk_g0_6 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_l_0 lc_trk_g1_3 (24 4) routing sp4_h_r_11 lc_trk_g1_3 (24 4) routing sp4_h_r_19 lc_trk_g1_3 (24 4) routing sp4_h_r_3 lc_trk_g1_3 (24 4) routing sp4_v_b_19 lc_trk_g1_3 (24 5) routing lft_op_2 lc_trk_g1_2 (24 5) routing sp12_h_r_2 lc_trk_g1_2 (24 5) routing sp4_h_l_7 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 (24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_t_7 lc_trk_g1_2 (24 5) routing top_op_2 lc_trk_g1_2 (24 6) routing lft_op_7 lc_trk_g1_7 (24 6) routing sp12_h_l_4 lc_trk_g1_7 (24 6) routing sp4_h_l_10 lc_trk_g1_7 (24 6) routing sp4_h_l_2 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 (24 6) routing sp4_v_t_10 lc_trk_g1_7 (24 7) routing lft_op_6 lc_trk_g1_6 (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_3 lc_trk_g1_6 (24 7) routing sp4_h_r_22 lc_trk_g1_6 (24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_b_22 lc_trk_g1_6 (24 7) routing top_op_6 lc_trk_g1_6 (24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_t_0 lc_trk_g2_3 (24 8) routing sp4_h_l_30 lc_trk_g2_3 (24 8) routing sp4_h_r_27 lc_trk_g2_3 (24 8) routing sp4_h_r_35 lc_trk_g2_3 (24 8) routing sp4_v_t_30 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 (24 8) routing tnr_op_3 lc_trk_g2_3 (24 9) routing rgt_op_2 lc_trk_g2_2 (24 9) routing sp12_v_b_2 lc_trk_g2_2 (24 9) routing sp4_h_l_15 lc_trk_g2_2 (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_r_2 lc_trk_g0_2 (25 0) routing sp4_h_l_7 lc_trk_g0_2 (25 0) routing sp4_h_r_10 lc_trk_g0_2 (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 (25 1) routing bnr_op_2 lc_trk_g0_2 (25 1) routing sp12_h_r_18 lc_trk_g0_2 (25 1) routing sp12_h_r_2 lc_trk_g0_2 (25 1) routing sp4_h_l_7 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 (25 1) routing top_op_2 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_b_6 lc_trk_g2_6 (25 10) routing sp4_h_l_27 lc_trk_g2_6 (25 10) routing sp4_h_r_46 lc_trk_g2_6 (25 10) routing sp4_v_b_30 lc_trk_g2_6 (25 10) routing sp4_v_b_38 lc_trk_g2_6 (25 11) routing bnl_op_6 lc_trk_g2_6 (25 11) routing sp12_v_b_6 lc_trk_g2_6 (25 11) routing sp12_v_t_21 lc_trk_g2_6 (25 11) routing sp4_h_r_30 lc_trk_g2_6 (25 11) routing sp4_h_r_46 lc_trk_g2_6 (25 11) routing sp4_r_v_b_38 lc_trk_g2_6 (25 11) routing sp4_v_b_38 lc_trk_g2_6 (25 11) routing tnl_op_6 lc_trk_g2_6 (25 12) routing bnl_op_2 lc_trk_g3_2 (25 12) routing rgt_op_2 lc_trk_g3_2 (25 12) routing sp12_v_b_2 lc_trk_g3_2 (25 12) routing sp4_h_r_34 lc_trk_g3_2 (25 12) routing sp4_h_r_42 lc_trk_g3_2 (25 12) routing sp4_v_b_26 lc_trk_g3_2 (25 12) routing sp4_v_t_23 lc_trk_g3_2 (25 13) routing bnl_op_2 lc_trk_g3_2 (25 13) routing sp12_v_b_2 lc_trk_g3_2 (25 13) routing sp12_v_t_17 lc_trk_g3_2 (25 13) routing sp4_h_l_15 lc_trk_g3_2 (25 13) routing sp4_h_r_42 lc_trk_g3_2 (25 13) routing sp4_r_v_b_42 lc_trk_g3_2 (25 13) routing sp4_v_t_23 lc_trk_g3_2 (25 13) routing tnl_op_2 lc_trk_g3_2 (25 14) routing bnl_op_6 lc_trk_g3_6 (25 14) routing rgt_op_6 lc_trk_g3_6 (25 14) routing sp12_v_b_6 lc_trk_g3_6 (25 14) routing sp4_h_l_27 lc_trk_g3_6 (25 14) routing sp4_h_r_46 lc_trk_g3_6 (25 14) routing sp4_v_b_30 lc_trk_g3_6 (25 14) routing sp4_v_b_38 lc_trk_g3_6 (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_6 lc_trk_g3_6 (25 15) routing sp12_v_t_21 lc_trk_g3_6 (25 15) routing sp4_h_r_30 lc_trk_g3_6 (25 15) routing sp4_h_r_46 lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_b_38 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 (25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 (25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_3 lc_trk_g0_6 (25 2) routing sp4_h_r_22 lc_trk_g0_6 (25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_21 lc_trk_g0_6 (25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp4_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 (25 3) routing sp4_v_b_14 lc_trk_g0_6 (25 3) routing top_op_6 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_r_2 lc_trk_g1_2 (25 4) routing sp4_h_l_7 lc_trk_g1_2 (25 4) routing sp4_h_r_10 lc_trk_g1_2 (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 (25 5) routing sp12_h_r_18 lc_trk_g1_2 (25 5) routing sp12_h_r_2 lc_trk_g1_2 (25 5) routing sp4_h_l_7 lc_trk_g1_2 (25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 (25 5) routing top_op_2 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 (25 6) routing sp4_h_l_3 lc_trk_g1_6 (25 6) routing sp4_h_r_22 lc_trk_g1_6 (25 6) routing sp4_v_b_14 lc_trk_g1_6 (25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 (25 7) routing sp12_h_l_21 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp4_h_r_22 lc_trk_g1_6 (25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_b_14 lc_trk_g1_6 (25 7) routing top_op_6 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_b_2 lc_trk_g2_2 (25 8) routing sp4_h_r_34 lc_trk_g2_2 (25 8) routing sp4_h_r_42 lc_trk_g2_2 (25 8) routing sp4_v_b_26 lc_trk_g2_2 (25 8) routing sp4_v_t_23 lc_trk_g2_2 (25 9) routing bnl_op_2 lc_trk_g2_2 (25 9) routing sp12_v_b_2 lc_trk_g2_2 (25 9) routing sp12_v_t_17 lc_trk_g2_2 (25 9) routing sp4_h_l_15 lc_trk_g2_2 (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_t_23 lc_trk_g2_2 (25 9) routing tnl_op_2 lc_trk_g2_2 (26 0) routing lc_trk_g0_4 input0_0 (26 0) routing lc_trk_g0_6 input0_0 (26 0) routing lc_trk_g1_5 input0_0 (26 0) routing lc_trk_g1_7 input0_0 (26 0) routing lc_trk_g2_4 input0_0 (26 0) routing lc_trk_g2_6 input0_0 (26 0) routing lc_trk_g3_5 input0_0 (26 0) routing lc_trk_g3_7 input0_0 (26 1) routing lc_trk_g0_2 input0_0 (26 1) routing lc_trk_g0_6 input0_0 (26 1) routing lc_trk_g1_3 input0_0 (26 1) routing lc_trk_g1_7 input0_0 (26 1) routing lc_trk_g2_2 input0_0 (26 1) routing lc_trk_g2_6 input0_0 (26 1) routing lc_trk_g3_3 input0_0 (26 1) routing lc_trk_g3_7 input0_0 (26 10) routing lc_trk_g0_5 input0_5 (26 10) routing lc_trk_g0_7 input0_5 (26 10) routing lc_trk_g1_4 input0_5 (26 10) routing lc_trk_g1_6 input0_5 (26 10) routing lc_trk_g2_5 input0_5 (26 10) routing lc_trk_g2_7 input0_5 (26 10) routing lc_trk_g3_4 input0_5 (26 10) routing lc_trk_g3_6 input0_5 (26 11) routing lc_trk_g0_3 input0_5 (26 11) routing lc_trk_g0_7 input0_5 (26 11) routing lc_trk_g1_2 input0_5 (26 11) routing lc_trk_g1_6 input0_5 (26 11) routing lc_trk_g2_3 input0_5 (26 11) routing lc_trk_g2_7 input0_5 (26 11) routing lc_trk_g3_2 input0_5 (26 11) routing lc_trk_g3_6 input0_5 (26 12) routing lc_trk_g0_4 input0_6 (26 12) routing lc_trk_g0_6 input0_6 (26 12) routing lc_trk_g1_5 input0_6 (26 12) routing lc_trk_g1_7 input0_6 (26 12) routing lc_trk_g2_4 input0_6 (26 12) routing lc_trk_g2_6 input0_6 (26 12) routing lc_trk_g3_5 input0_6 (26 12) routing lc_trk_g3_7 input0_6 (26 13) routing lc_trk_g0_2 input0_6 (26 13) routing lc_trk_g0_6 input0_6 (26 13) routing lc_trk_g1_3 input0_6 (26 13) routing lc_trk_g1_7 input0_6 (26 13) routing lc_trk_g2_2 input0_6 (26 13) routing lc_trk_g2_6 input0_6 (26 13) routing lc_trk_g3_3 input0_6 (26 13) routing lc_trk_g3_7 input0_6 (26 14) routing lc_trk_g0_5 input0_7 (26 14) routing lc_trk_g0_7 input0_7 (26 14) routing lc_trk_g1_4 input0_7 (26 14) routing lc_trk_g1_6 input0_7 (26 14) routing lc_trk_g2_5 input0_7 (26 14) routing lc_trk_g2_7 input0_7 (26 14) routing lc_trk_g3_4 input0_7 (26 14) routing lc_trk_g3_6 input0_7 (26 15) routing lc_trk_g0_3 input0_7 (26 15) routing lc_trk_g0_7 input0_7 (26 15) routing lc_trk_g1_2 input0_7 (26 15) routing lc_trk_g1_6 input0_7 (26 15) routing lc_trk_g2_3 input0_7 (26 15) routing lc_trk_g2_7 input0_7 (26 15) routing lc_trk_g3_2 input0_7 (26 15) routing lc_trk_g3_6 input0_7 (26 2) routing lc_trk_g0_5 input0_1 (26 2) routing lc_trk_g0_7 input0_1 (26 2) routing lc_trk_g1_4 input0_1 (26 2) routing lc_trk_g1_6 input0_1 (26 2) routing lc_trk_g2_5 input0_1 (26 2) routing lc_trk_g2_7 input0_1 (26 2) routing lc_trk_g3_4 input0_1 (26 2) routing lc_trk_g3_6 input0_1 (26 3) routing lc_trk_g0_3 input0_1 (26 3) routing lc_trk_g0_7 input0_1 (26 3) routing lc_trk_g1_2 input0_1 (26 3) routing lc_trk_g1_6 input0_1 (26 3) routing lc_trk_g2_3 input0_1 (26 3) routing lc_trk_g2_7 input0_1 (26 3) routing lc_trk_g3_2 input0_1 (26 3) routing lc_trk_g3_6 input0_1 (26 4) routing lc_trk_g0_4 input0_2 (26 4) routing lc_trk_g0_6 input0_2 (26 4) routing lc_trk_g1_5 input0_2 (26 4) routing lc_trk_g1_7 input0_2 (26 4) routing lc_trk_g2_4 input0_2 (26 4) routing lc_trk_g2_6 input0_2 (26 4) routing lc_trk_g3_5 input0_2 (26 4) routing lc_trk_g3_7 input0_2 (26 5) routing lc_trk_g0_2 input0_2 (26 5) routing lc_trk_g0_6 input0_2 (26 5) routing lc_trk_g1_3 input0_2 (26 5) routing lc_trk_g1_7 input0_2 (26 5) routing lc_trk_g2_2 input0_2 (26 5) routing lc_trk_g2_6 input0_2 (26 5) routing lc_trk_g3_3 input0_2 (26 5) routing lc_trk_g3_7 input0_2 (26 6) routing lc_trk_g0_5 input0_3 (26 6) routing lc_trk_g0_7 input0_3 (26 6) routing lc_trk_g1_4 input0_3 (26 6) routing lc_trk_g1_6 input0_3 (26 6) routing lc_trk_g2_5 input0_3 (26 6) routing lc_trk_g2_7 input0_3 (26 6) routing lc_trk_g3_4 input0_3 (26 6) routing lc_trk_g3_6 input0_3 (26 7) routing lc_trk_g0_3 input0_3 (26 7) routing lc_trk_g0_7 input0_3 (26 7) routing lc_trk_g1_2 input0_3 (26 7) routing lc_trk_g1_6 input0_3 (26 7) routing lc_trk_g2_3 input0_3 (26 7) routing lc_trk_g2_7 input0_3 (26 7) routing lc_trk_g3_2 input0_3 (26 7) routing lc_trk_g3_6 input0_3 (26 8) routing lc_trk_g0_4 input0_4 (26 8) routing lc_trk_g0_6 input0_4 (26 8) routing lc_trk_g1_5 input0_4 (26 8) routing lc_trk_g1_7 input0_4 (26 8) routing lc_trk_g2_4 input0_4 (26 8) routing lc_trk_g2_6 input0_4 (26 8) routing lc_trk_g3_5 input0_4 (26 8) routing lc_trk_g3_7 input0_4 (26 9) routing lc_trk_g0_2 input0_4 (26 9) routing lc_trk_g0_6 input0_4 (26 9) routing lc_trk_g1_3 input0_4 (26 9) routing lc_trk_g1_7 input0_4 (26 9) routing lc_trk_g2_2 input0_4 (26 9) routing lc_trk_g2_6 input0_4 (26 9) routing lc_trk_g3_3 input0_4 (26 9) routing lc_trk_g3_7 input0_4 (27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_8 (27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_8 (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_8 (27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_8 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_8 (27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_8 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_8 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_8 (27 1) routing lc_trk_g1_1 input0_0 (27 1) routing lc_trk_g1_3 input0_0 (27 1) routing lc_trk_g1_5 input0_0 (27 1) routing lc_trk_g1_7 input0_0 (27 1) routing lc_trk_g3_1 input0_0 (27 1) routing lc_trk_g3_3 input0_0 (27 1) routing lc_trk_g3_5 input0_0 (27 1) routing lc_trk_g3_7 input0_0 (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_13 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_13 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_13 (27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_13 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_13 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_13 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_13 (27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_13 (27 11) routing lc_trk_g1_0 input0_5 (27 11) routing lc_trk_g1_2 input0_5 (27 11) routing lc_trk_g1_4 input0_5 (27 11) routing lc_trk_g1_6 input0_5 (27 11) routing lc_trk_g3_0 input0_5 (27 11) routing lc_trk_g3_2 input0_5 (27 11) routing lc_trk_g3_4 input0_5 (27 11) routing lc_trk_g3_6 input0_5 (27 12) routing lc_trk_g1_0 wire_bram/ram/WDATA_14 (27 12) routing lc_trk_g1_2 wire_bram/ram/WDATA_14 (27 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_14 (27 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_14 (27 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_14 (27 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_14 (27 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_14 (27 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_14 (27 13) routing lc_trk_g1_1 input0_6 (27 13) routing lc_trk_g1_3 input0_6 (27 13) routing lc_trk_g1_5 input0_6 (27 13) routing lc_trk_g1_7 input0_6 (27 13) routing lc_trk_g3_1 input0_6 (27 13) routing lc_trk_g3_3 input0_6 (27 13) routing lc_trk_g3_5 input0_6 (27 13) routing lc_trk_g3_7 input0_6 (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_15 (27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_15 (27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_15 (27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_15 (27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_15 (27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_15 (27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_15 (27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_15 (27 15) routing lc_trk_g1_0 input0_7 (27 15) routing lc_trk_g1_2 input0_7 (27 15) routing lc_trk_g1_4 input0_7 (27 15) routing lc_trk_g1_6 input0_7 (27 15) routing lc_trk_g3_0 input0_7 (27 15) routing lc_trk_g3_2 input0_7 (27 15) routing lc_trk_g3_4 input0_7 (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_9 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_9 (27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_9 (27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_9 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_9 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_9 (27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_9 (27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_9 (27 3) routing lc_trk_g1_0 input0_1 (27 3) routing lc_trk_g1_2 input0_1 (27 3) routing lc_trk_g1_4 input0_1 (27 3) routing lc_trk_g1_6 input0_1 (27 3) routing lc_trk_g3_0 input0_1 (27 3) routing lc_trk_g3_2 input0_1 (27 3) routing lc_trk_g3_4 input0_1 (27 3) routing lc_trk_g3_6 input0_1 (27 4) routing lc_trk_g1_0 wire_bram/ram/WDATA_10 (27 4) routing lc_trk_g1_2 wire_bram/ram/WDATA_10 (27 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_10 (27 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_10 (27 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_10 (27 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_10 (27 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_10 (27 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_10 (27 5) routing lc_trk_g1_1 input0_2 (27 5) routing lc_trk_g1_3 input0_2 (27 5) routing lc_trk_g1_5 input0_2 (27 5) routing lc_trk_g1_7 input0_2 (27 5) routing lc_trk_g3_1 input0_2 (27 5) routing lc_trk_g3_3 input0_2 (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 (27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_11 (27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_11 (27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_11 (27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_11 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_11 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_11 (27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_11 (27 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_11 (27 7) routing lc_trk_g1_0 input0_3 (27 7) routing lc_trk_g1_2 input0_3 (27 7) routing lc_trk_g1_4 input0_3 (27 7) routing lc_trk_g1_6 input0_3 (27 7) routing lc_trk_g3_0 input0_3 (27 7) routing lc_trk_g3_2 input0_3 (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_12 (27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_12 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_12 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_12 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_12 (27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_12 (27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_12 (27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_12 (27 9) routing lc_trk_g1_1 input0_4 (27 9) routing lc_trk_g1_3 input0_4 (27 9) routing lc_trk_g1_5 input0_4 (27 9) routing lc_trk_g1_7 input0_4 (27 9) routing lc_trk_g3_1 input0_4 (27 9) routing lc_trk_g3_3 input0_4 (27 9) routing lc_trk_g3_5 input0_4 (27 9) routing lc_trk_g3_7 input0_4 (28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_8 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_8 (28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_8 (28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_8 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_8 (28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_8 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_8 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_8 (28 1) routing lc_trk_g2_0 input0_0 (28 1) routing lc_trk_g2_2 input0_0 (28 1) routing lc_trk_g2_4 input0_0 (28 1) routing lc_trk_g2_6 input0_0 (28 1) routing lc_trk_g3_1 input0_0 (28 1) routing lc_trk_g3_3 input0_0 (28 1) routing lc_trk_g3_5 input0_0 (28 1) routing lc_trk_g3_7 input0_0 (28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_13 (28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_13 (28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_13 (28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_13 (28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_13 (28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_13 (28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_13 (28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_13 (28 11) routing lc_trk_g2_1 input0_5 (28 11) routing lc_trk_g2_3 input0_5 (28 11) routing lc_trk_g2_5 input0_5 (28 11) routing lc_trk_g2_7 input0_5 (28 11) routing lc_trk_g3_0 input0_5 (28 11) routing lc_trk_g3_2 input0_5 (28 11) routing lc_trk_g3_4 input0_5 (28 11) routing lc_trk_g3_6 input0_5 (28 12) routing lc_trk_g2_1 wire_bram/ram/WDATA_14 (28 12) routing lc_trk_g2_3 wire_bram/ram/WDATA_14 (28 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_14 (28 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_14 (28 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_14 (28 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_14 (28 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_14 (28 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_14 (28 13) routing lc_trk_g2_0 input0_6 (28 13) routing lc_trk_g2_2 input0_6 (28 13) routing lc_trk_g2_4 input0_6 (28 13) routing lc_trk_g2_6 input0_6 (28 13) routing lc_trk_g3_1 input0_6 (28 13) routing lc_trk_g3_3 input0_6 (28 13) routing lc_trk_g3_5 input0_6 (28 13) routing lc_trk_g3_7 input0_6 (28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_15 (28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_15 (28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_15 (28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_15 (28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_15 (28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_15 (28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_15 (28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_15 (28 15) routing lc_trk_g2_1 input0_7 (28 15) routing lc_trk_g2_3 input0_7 (28 15) routing lc_trk_g2_5 input0_7 (28 15) routing lc_trk_g2_7 input0_7 (28 15) routing lc_trk_g3_0 input0_7 (28 15) routing lc_trk_g3_2 input0_7 (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 (28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_9 (28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_9 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_9 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_9 (28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_9 (28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_9 (28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_9 (28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_9 (28 3) routing lc_trk_g2_1 input0_1 (28 3) routing lc_trk_g2_3 input0_1 (28 3) routing lc_trk_g2_5 input0_1 (28 3) routing lc_trk_g2_7 input0_1 (28 3) routing lc_trk_g3_0 input0_1 (28 3) routing lc_trk_g3_2 input0_1 (28 3) routing lc_trk_g3_4 input0_1 (28 3) routing lc_trk_g3_6 input0_1 (28 4) routing lc_trk_g2_1 wire_bram/ram/WDATA_10 (28 4) routing lc_trk_g2_3 wire_bram/ram/WDATA_10 (28 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_10 (28 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_10 (28 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_10 (28 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_10 (28 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_10 (28 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_10 (28 5) routing lc_trk_g2_0 input0_2 (28 5) routing lc_trk_g2_2 input0_2 (28 5) routing lc_trk_g2_4 input0_2 (28 5) routing lc_trk_g2_6 input0_2 (28 5) routing lc_trk_g3_1 input0_2 (28 5) routing lc_trk_g3_3 input0_2 (28 5) routing lc_trk_g3_5 input0_2 (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_11 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_11 (28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_11 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_11 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_11 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_11 (28 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_11 (28 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_11 (28 7) routing lc_trk_g2_1 input0_3 (28 7) routing lc_trk_g2_3 input0_3 (28 7) routing lc_trk_g2_5 input0_3 (28 7) routing lc_trk_g2_7 input0_3 (28 7) routing lc_trk_g3_0 input0_3 (28 7) routing lc_trk_g3_2 input0_3 (28 7) routing lc_trk_g3_4 input0_3 (28 7) routing lc_trk_g3_6 input0_3 (28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_12 (28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_12 (28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_12 (28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_12 (28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_12 (28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_12 (28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_12 (28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_12 (28 9) routing lc_trk_g2_0 input0_4 (28 9) routing lc_trk_g2_2 input0_4 (28 9) routing lc_trk_g2_4 input0_4 (28 9) routing lc_trk_g2_6 input0_4 (28 9) routing lc_trk_g3_1 input0_4 (28 9) routing lc_trk_g3_3 input0_4 (28 9) routing lc_trk_g3_5 input0_4 (28 9) routing lc_trk_g3_7 input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_8 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_8 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_13 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_13 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_14 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_14 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_15 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_15 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_9 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_9 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_10 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_10 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_11 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_11 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_12 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_12 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 (3 0) routing sp12_h_r_0 sp12_v_b_0 (3 0) routing sp12_v_t_23 sp12_v_b_0 (3 1) routing sp12_h_l_23 sp12_v_b_0 (3 1) routing sp12_h_r_0 sp12_v_b_0 (3 10) routing sp12_h_r_1 sp12_h_l_22 (3 10) routing sp12_v_t_22 sp12_h_l_22 (3 11) routing sp12_h_r_1 sp12_h_l_22 (3 11) routing sp12_v_b_1 sp12_h_l_22 (3 12) routing sp12_v_b_1 sp12_h_r_1 (3 12) routing sp12_v_t_22 sp12_h_r_1 (3 13) routing sp12_h_l_22 sp12_h_r_1 (3 13) routing sp12_v_b_1 sp12_h_r_1 (3 14) routing sp12_h_r_1 sp12_v_t_22 (3 14) routing sp12_v_b_1 sp12_v_t_22 (3 15) routing sp12_h_l_22 sp12_v_t_22 (3 15) routing sp12_h_r_1 sp12_v_t_22 (3 2) routing sp12_h_r_0 sp12_h_l_23 (3 2) routing sp12_v_t_23 sp12_h_l_23 (3 3) routing sp12_h_r_0 sp12_h_l_23 (3 3) routing sp12_v_b_0 sp12_h_l_23 (3 4) routing sp12_v_b_0 sp12_h_r_0 (3 4) routing sp12_v_t_23 sp12_h_r_0 (3 5) routing sp12_h_l_23 sp12_h_r_0 (3 5) routing sp12_v_b_0 sp12_h_r_0 (3 6) routing sp12_h_r_0 sp12_v_t_23 (3 6) routing sp12_v_b_0 sp12_v_t_23 (3 7) routing sp12_h_l_23 sp12_v_t_23 (3 7) routing sp12_h_r_0 sp12_v_t_23 (3 8) routing sp12_h_r_1 sp12_v_b_1 (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 (30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_8 (30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_8 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_8 (30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_8 (30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_8 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_8 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_8 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_8 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_8 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_13 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_13 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_13 (30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_13 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_13 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_13 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_13 (30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_13 (30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_13 (30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_14 (30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_14 (30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_14 (30 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_14 (30 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_14 (30 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_14 (30 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_14 (30 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g0_3 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g0_7 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g1_2 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g1_6 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g2_3 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g2_7 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g3_2 wire_bram/ram/WDATA_14 (30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_14 (30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_15 (30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_15 (30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_15 (30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_15 (30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_15 (30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_15 (30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_15 (30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_15 (30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_15 (30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_9 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_9 (30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_9 (30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_9 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_9 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_9 (30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_9 (30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_9 (30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_9 (30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_10 (30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_10 (30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_10 (30 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_10 (30 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_10 (30 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_10 (30 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_10 (30 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g0_3 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g0_7 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g1_2 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g1_6 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g2_3 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_10 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_10 (30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_11 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_11 (30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_11 (30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_11 (30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_11 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_11 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_11 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_11 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_12 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_12 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_12 (31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_8 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_8 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_8 (31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_8 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_8 (31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_8 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_8 (31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_8 (31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_8 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_13 (31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_13 (31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_13 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_13 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_13 (31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_13 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_13 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_13 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_13 (31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_14 (31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_14 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_14 (31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_14 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_14 (31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_14 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_14 (31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_14 (31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_14 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_15 (31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_15 (31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_15 (31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_15 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_15 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_15 (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_15 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_15 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_15 (31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_9 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_9 (31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_9 (31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_9 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_9 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_9 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_9 (31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_9 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_9 (31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_10 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_10 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_10 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_10 (31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_10 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_10 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_10 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_10 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_10 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_11 (31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_11 (31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_11 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_11 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_11 (31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_11 (31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_11 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_11 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_12 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_12 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_8 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_8 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_0 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_2 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_4 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_6 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_1 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_3 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_5 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g1_7 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_0 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_2 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_4 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_6 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_1 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_3 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_5 input2_0 (32 1) Enable bit of Mux _bram/lcb2_0 => lc_trk_g3_7 input2_0 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_13 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_13 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_14 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_14 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_15 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_15 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_9 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_9 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_1 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_3 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_5 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g0_7 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_0 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_2 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_4 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g1_6 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_1 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_3 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_5 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_7 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_0 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_2 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_4 input2_1 (32 3) Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_6 input2_1 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_10 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_10 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_0 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_2 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_4 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_6 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_1 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_3 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_5 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_7 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_0 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_2 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_4 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g2_6 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_1 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_3 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_5 input2_2 (32 5) Enable bit of Mux _bram/lcb2_2 => lc_trk_g3_7 input2_2 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_11 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_12 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_8 (33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_8 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_8 (33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_8 (33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_8 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_8 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_8 (33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_8 (33 1) routing lc_trk_g2_0 input2_0 (33 1) routing lc_trk_g2_2 input2_0 (33 1) routing lc_trk_g2_4 input2_0 (33 1) routing lc_trk_g2_6 input2_0 (33 1) routing lc_trk_g3_1 input2_0 (33 1) routing lc_trk_g3_3 input2_0 (33 1) routing lc_trk_g3_5 input2_0 (33 1) routing lc_trk_g3_7 input2_0 (33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_13 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_13 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_13 (33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_13 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_13 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_13 (33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_13 (33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_13 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_14 (33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_14 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_14 (33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_14 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_14 (33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_14 (33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_14 (33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_14 (33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_15 (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_15 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_15 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_15 (33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_15 (33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_15 (33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_15 (33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_15 (33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_9 (33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_9 (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_9 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_9 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_9 (33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_9 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_9 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_9 (33 3) routing lc_trk_g2_1 input2_1 (33 3) routing lc_trk_g2_3 input2_1 (33 3) routing lc_trk_g2_5 input2_1 (33 3) routing lc_trk_g2_7 input2_1 (33 3) routing lc_trk_g3_0 input2_1 (33 3) routing lc_trk_g3_2 input2_1 (33 3) routing lc_trk_g3_4 input2_1 (33 3) routing lc_trk_g3_6 input2_1 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_10 (33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_10 (33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_10 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_10 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_10 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_10 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_10 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_10 (33 5) routing lc_trk_g2_0 input2_2 (33 5) routing lc_trk_g2_2 input2_2 (33 5) routing lc_trk_g2_4 input2_2 (33 5) routing lc_trk_g2_6 input2_2 (33 5) routing lc_trk_g3_1 input2_2 (33 5) routing lc_trk_g3_3 input2_2 (33 5) routing lc_trk_g3_5 input2_2 (33 5) routing lc_trk_g3_7 input2_2 (33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_11 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_11 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_11 (33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_11 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_11 (33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_11 (33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_11 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_12 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_12 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_8 (34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_8 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_8 (34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_8 (34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_8 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_8 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_8 (34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_8 (34 1) routing lc_trk_g1_1 input2_0 (34 1) routing lc_trk_g1_3 input2_0 (34 1) routing lc_trk_g1_5 input2_0 (34 1) routing lc_trk_g1_7 input2_0 (34 1) routing lc_trk_g3_1 input2_0 (34 1) routing lc_trk_g3_3 input2_0 (34 1) routing lc_trk_g3_5 input2_0 (34 1) routing lc_trk_g3_7 input2_0 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_13 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_13 (34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_13 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_13 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_13 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_13 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_13 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_13 (34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_14 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_14 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_14 (34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_14 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_14 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_14 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_14 (34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_14 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_15 (34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_15 (34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_15 (34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_15 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_15 (34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_15 (34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_15 (34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_15 (34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_9 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_9 (34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_9 (34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_9 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_9 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_9 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_9 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_9 (34 3) routing lc_trk_g1_0 input2_1 (34 3) routing lc_trk_g1_2 input2_1 (34 3) routing lc_trk_g1_4 input2_1 (34 3) routing lc_trk_g1_6 input2_1 (34 3) routing lc_trk_g3_0 input2_1 (34 3) routing lc_trk_g3_2 input2_1 (34 3) routing lc_trk_g3_4 input2_1 (34 3) routing lc_trk_g3_6 input2_1 (34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_10 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_10 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_10 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_10 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_10 (34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_10 (34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_10 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_10 (34 5) routing lc_trk_g1_1 input2_2 (34 5) routing lc_trk_g1_3 input2_2 (34 5) routing lc_trk_g1_5 input2_2 (34 5) routing lc_trk_g1_7 input2_2 (34 5) routing lc_trk_g3_1 input2_2 (34 5) routing lc_trk_g3_3 input2_2 (34 5) routing lc_trk_g3_5 input2_2 (34 5) routing lc_trk_g3_7 input2_2 (34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_11 (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_11 (34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_11 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_11 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_11 (34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_11 (34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_11 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_12 (35 0) routing lc_trk_g0_4 input2_0 (35 0) routing lc_trk_g0_6 input2_0 (35 0) routing lc_trk_g1_5 input2_0 (35 0) routing lc_trk_g1_7 input2_0 (35 0) routing lc_trk_g2_4 input2_0 (35 0) routing lc_trk_g2_6 input2_0 (35 0) routing lc_trk_g3_5 input2_0 (35 0) routing lc_trk_g3_7 input2_0 (35 1) routing lc_trk_g0_2 input2_0 (35 1) routing lc_trk_g0_6 input2_0 (35 1) routing lc_trk_g1_3 input2_0 (35 1) routing lc_trk_g1_7 input2_0 (35 1) routing lc_trk_g2_2 input2_0 (35 1) routing lc_trk_g2_6 input2_0 (35 1) routing lc_trk_g3_3 input2_0 (35 1) routing lc_trk_g3_7 input2_0 (35 2) routing lc_trk_g0_5 input2_1 (35 2) routing lc_trk_g0_7 input2_1 (35 2) routing lc_trk_g1_4 input2_1 (35 2) routing lc_trk_g1_6 input2_1 (35 2) routing lc_trk_g2_5 input2_1 (35 2) routing lc_trk_g2_7 input2_1 (35 2) routing lc_trk_g3_4 input2_1 (35 2) routing lc_trk_g3_6 input2_1 (35 3) routing lc_trk_g0_3 input2_1 (35 3) routing lc_trk_g0_7 input2_1 (35 3) routing lc_trk_g1_2 input2_1 (35 3) routing lc_trk_g1_6 input2_1 (35 3) routing lc_trk_g2_3 input2_1 (35 3) routing lc_trk_g2_7 input2_1 (35 3) routing lc_trk_g3_2 input2_1 (35 3) routing lc_trk_g3_6 input2_1 (35 4) routing lc_trk_g0_4 input2_2 (35 4) routing lc_trk_g0_6 input2_2 (35 4) routing lc_trk_g1_5 input2_2 (35 4) routing lc_trk_g1_7 input2_2 (35 4) routing lc_trk_g2_4 input2_2 (35 4) routing lc_trk_g2_6 input2_2 (35 4) routing lc_trk_g3_5 input2_2 (35 4) routing lc_trk_g3_7 input2_2 (35 5) routing lc_trk_g0_2 input2_2 (35 5) routing lc_trk_g0_6 input2_2 (35 5) routing lc_trk_g1_3 input2_2 (35 5) routing lc_trk_g1_7 input2_2 (35 5) routing lc_trk_g2_2 input2_2 (35 5) routing lc_trk_g2_6 input2_2 (35 5) routing lc_trk_g3_3 input2_2 (35 5) routing lc_trk_g3_7 input2_2 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_8 sp4_h_l_21 (36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_8 sp4_h_r_0 (36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_13 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_13 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_14 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_14 sp4_h_r_12 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_15 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_15 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_9 sp4_h_r_34 (36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_9 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_10 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_10 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_11 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_11 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_12 sp4_h_l_29 (36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_12 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_8 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_8 sp4_h_l_5 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_13 sp12_h_r_2 (37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_13 sp4_h_l_15 (37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_14 sp12_h_l_3 (37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_14 sp4_h_l_17 (37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_15 sp12_h_l_5 (37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_15 sp4_h_r_30 (37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_9 sp12_h_r_10 (37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_9 sp4_h_l_7 (37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_10 sp12_h_r_12 (37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_10 sp4_h_r_20 (37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_11 sp12_h_l_13 (37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_11 sp4_h_r_22 (37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_12 sp12_h_r_0 (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_12 sp4_h_l_13 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_8 sp4_v_t_21 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_8 sp4_v_b_0 (38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_13 sp4_v_b_26 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_13 sp12_h_r_18 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_14 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_14 sp12_h_r_20 (38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_15 sp4_v_b_30 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_15 sp12_h_l_21 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_9 sp4_v_t_23 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_9 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_10 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_10 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_11 sp4_v_b_38 (38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_11 sp4_v_b_6 (38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_12 sp4_v_t_13 (38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_12 sp12_h_r_16 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_8 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_8 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_13 sp4_v_t_31 (39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_13 sp4_v_b_10 (39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_14 sp4_v_t_33 (39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_14 sp4_v_t_1 (39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_15 sp4_v_b_46 (39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_15 sp4_v_b_14 (39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_9 sp12_v_b_2 (39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_9 sp4_v_t_7 (39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_10 sp12_v_t_3 (39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_10 sp4_v_b_20 (39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_11 sp12_v_b_6 (39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_11 sp4_v_b_22 (39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_12 sp4_v_b_40 (39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_12 sp4_v_b_8 (4 0) routing sp4_h_l_37 sp4_v_b_0 (4 0) routing sp4_h_l_43 sp4_v_b_0 (4 0) routing sp4_v_t_37 sp4_v_b_0 (4 0) routing sp4_v_t_41 sp4_v_b_0 (4 1) routing sp4_h_l_41 sp4_h_r_0 (4 1) routing sp4_h_l_44 sp4_h_r_0 (4 1) routing sp4_v_b_6 sp4_h_r_0 (4 1) routing sp4_v_t_42 sp4_h_r_0 (4 10) routing sp4_h_r_0 sp4_v_t_43 (4 10) routing sp4_h_r_6 sp4_v_t_43 (4 10) routing sp4_v_b_10 sp4_v_t_43 (4 10) routing sp4_v_b_6 sp4_v_t_43 (4 11) routing sp4_h_r_10 sp4_h_l_43 (4 11) routing sp4_h_r_3 sp4_h_l_43 (4 11) routing sp4_v_b_1 sp4_h_l_43 (4 11) routing sp4_v_t_37 sp4_h_l_43 (4 12) routing sp4_h_l_38 sp4_v_b_9 (4 12) routing sp4_h_l_44 sp4_v_b_9 (4 12) routing sp4_v_t_36 sp4_v_b_9 (4 12) routing sp4_v_t_44 sp4_v_b_9 (4 13) routing sp4_h_l_36 sp4_h_r_9 (4 13) routing sp4_h_l_43 sp4_h_r_9 (4 13) routing sp4_v_b_3 sp4_h_r_9 (4 13) routing sp4_v_t_41 sp4_h_r_9 (4 14) routing sp4_h_r_3 sp4_v_t_44 (4 14) routing sp4_h_r_9 sp4_v_t_44 (4 14) routing sp4_v_b_1 sp4_v_t_44 (4 14) routing sp4_v_b_9 sp4_v_t_44 (4 15) routing sp4_h_r_1 sp4_h_l_44 (4 15) routing sp4_h_r_6 sp4_h_l_44 (4 15) routing sp4_v_b_4 sp4_h_l_44 (4 15) routing sp4_v_t_38 sp4_h_l_44 (4 2) routing sp4_h_r_0 sp4_v_t_37 (4 2) routing sp4_h_r_6 sp4_v_t_37 (4 2) routing sp4_v_b_0 sp4_v_t_37 (4 2) routing sp4_v_b_4 sp4_v_t_37 (4 3) routing sp4_h_r_4 sp4_h_l_37 (4 3) routing sp4_h_r_9 sp4_h_l_37 (4 3) routing sp4_v_b_7 sp4_h_l_37 (4 3) routing sp4_v_t_43 sp4_h_l_37 (4 4) routing sp4_h_l_38 sp4_v_b_3 (4 4) routing sp4_h_l_44 sp4_v_b_3 (4 4) routing sp4_v_t_38 sp4_v_b_3 (4 4) routing sp4_v_t_42 sp4_v_b_3 (4 5) routing sp4_h_l_37 sp4_h_r_3 (4 5) routing sp4_h_l_42 sp4_h_r_3 (4 5) routing sp4_v_b_9 sp4_h_r_3 (4 5) routing sp4_v_t_47 sp4_h_r_3 (4 6) routing sp4_h_r_3 sp4_v_t_38 (4 6) routing sp4_h_r_9 sp4_v_t_38 (4 6) routing sp4_v_b_3 sp4_v_t_38 (4 6) routing sp4_v_b_7 sp4_v_t_38 (4 7) routing sp4_h_r_0 sp4_h_l_38 (4 7) routing sp4_h_r_7 sp4_h_l_38 (4 7) routing sp4_v_b_10 sp4_h_l_38 (4 7) routing sp4_v_t_44 sp4_h_l_38 (4 8) routing sp4_h_l_37 sp4_v_b_6 (4 8) routing sp4_h_l_43 sp4_v_b_6 (4 8) routing sp4_v_t_43 sp4_v_b_6 (4 8) routing sp4_v_t_47 sp4_v_b_6 (4 9) routing sp4_h_l_38 sp4_h_r_6 (4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_8 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_8 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_13 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_13 sp12_v_t_9 (40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_14 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_14 sp12_v_b_12 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_15 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_15 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_9 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_9 sp12_v_t_17 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_10 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_10 sp12_v_t_19 (40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_11 sp4_r_v_b_23 (40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_11 sp12_v_t_21 (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_12 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_12 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_8 sp4_r_v_b_33 (41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_8 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_13 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_13 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_14 sp4_r_v_b_45 (41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_14 sp4_r_v_b_13 (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_15 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_15 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_9 sp4_r_v_b_35 (41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_9 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_10 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_10 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_11 sp4_r_v_b_39 (41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_11 sp4_r_v_b_7 (41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_12 sp4_r_v_b_41 (41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_12 sp4_r_v_b_9 (5 0) routing sp4_h_l_44 sp4_h_r_0 (5 0) routing sp4_v_b_0 sp4_h_r_0 (5 0) routing sp4_v_b_6 sp4_h_r_0 (5 0) routing sp4_v_t_37 sp4_h_r_0 (5 1) routing sp4_h_l_37 sp4_v_b_0 (5 1) routing sp4_h_l_43 sp4_v_b_0 (5 1) routing sp4_h_r_0 sp4_v_b_0 (5 1) routing sp4_v_t_44 sp4_v_b_0 (5 10) routing sp4_h_r_3 sp4_h_l_43 (5 10) routing sp4_v_b_6 sp4_h_l_43 (5 10) routing sp4_v_t_37 sp4_h_l_43 (5 10) routing sp4_v_t_43 sp4_h_l_43 (5 11) routing sp4_h_l_43 sp4_v_t_43 (5 11) routing sp4_h_r_0 sp4_v_t_43 (5 11) routing sp4_h_r_6 sp4_v_t_43 (5 11) routing sp4_v_b_3 sp4_v_t_43 (5 12) routing sp4_h_l_43 sp4_h_r_9 (5 12) routing sp4_v_b_3 sp4_h_r_9 (5 12) routing sp4_v_b_9 sp4_h_r_9 (5 12) routing sp4_v_t_44 sp4_h_r_9 (5 13) routing sp4_h_l_38 sp4_v_b_9 (5 13) routing sp4_h_l_44 sp4_v_b_9 (5 13) routing sp4_h_r_9 sp4_v_b_9 (5 13) routing sp4_v_t_43 sp4_v_b_9 (5 14) routing sp4_h_r_6 sp4_h_l_44 (5 14) routing sp4_v_b_9 sp4_h_l_44 (5 14) routing sp4_v_t_38 sp4_h_l_44 (5 14) routing sp4_v_t_44 sp4_h_l_44 (5 15) routing sp4_h_l_44 sp4_v_t_44 (5 15) routing sp4_h_r_3 sp4_v_t_44 (5 15) routing sp4_h_r_9 sp4_v_t_44 (5 15) routing sp4_v_b_6 sp4_v_t_44 (5 2) routing sp4_h_r_9 sp4_h_l_37 (5 2) routing sp4_v_b_0 sp4_h_l_37 (5 2) routing sp4_v_t_37 sp4_h_l_37 (5 2) routing sp4_v_t_43 sp4_h_l_37 (5 3) routing sp4_h_l_37 sp4_v_t_37 (5 3) routing sp4_h_r_0 sp4_v_t_37 (5 3) routing sp4_h_r_6 sp4_v_t_37 (5 3) routing sp4_v_b_9 sp4_v_t_37 (5 4) routing sp4_h_l_37 sp4_h_r_3 (5 4) routing sp4_v_b_3 sp4_h_r_3 (5 4) routing sp4_v_b_9 sp4_h_r_3 (5 4) routing sp4_v_t_38 sp4_h_r_3 (5 5) routing sp4_h_l_38 sp4_v_b_3 (5 5) routing sp4_h_l_44 sp4_v_b_3 (5 5) routing sp4_h_r_3 sp4_v_b_3 (5 5) routing sp4_v_t_37 sp4_v_b_3 (5 6) routing sp4_h_r_0 sp4_h_l_38 (5 6) routing sp4_v_b_3 sp4_h_l_38 (5 6) routing sp4_v_t_38 sp4_h_l_38 (5 6) routing sp4_v_t_44 sp4_h_l_38 (5 7) routing sp4_h_l_38 sp4_v_t_38 (5 7) routing sp4_h_r_3 sp4_v_t_38 (5 7) routing sp4_h_r_9 sp4_v_t_38 (5 7) routing sp4_v_b_0 sp4_v_t_38 (5 8) routing sp4_h_l_38 sp4_h_r_6 (5 8) routing sp4_v_b_0 sp4_h_r_6 (5 8) routing sp4_v_b_6 sp4_h_r_6 (5 8) routing sp4_v_t_43 sp4_h_r_6 (5 9) routing sp4_h_l_37 sp4_v_b_6 (5 9) routing sp4_h_l_43 sp4_v_b_6 (5 9) routing sp4_h_r_6 sp4_v_b_6 (5 9) routing sp4_v_t_38 sp4_v_b_6 (6 0) routing sp4_h_l_43 sp4_v_b_0 (6 0) routing sp4_h_r_7 sp4_v_b_0 (6 0) routing sp4_v_t_41 sp4_v_b_0 (6 0) routing sp4_v_t_44 sp4_v_b_0 (6 1) routing sp4_h_l_37 sp4_h_r_0 (6 1) routing sp4_h_l_41 sp4_h_r_0 (6 1) routing sp4_v_b_0 sp4_h_r_0 (6 1) routing sp4_v_b_6 sp4_h_r_0 (6 10) routing sp4_h_l_36 sp4_v_t_43 (6 10) routing sp4_h_r_0 sp4_v_t_43 (6 10) routing sp4_v_b_10 sp4_v_t_43 (6 10) routing sp4_v_b_3 sp4_v_t_43 (6 11) routing sp4_h_r_10 sp4_h_l_43 (6 11) routing sp4_h_r_6 sp4_h_l_43 (6 11) routing sp4_v_t_37 sp4_h_l_43 (6 11) routing sp4_v_t_43 sp4_h_l_43 (6 12) routing sp4_h_l_38 sp4_v_b_9 (6 12) routing sp4_h_r_4 sp4_v_b_9 (6 12) routing sp4_v_t_36 sp4_v_b_9 (6 12) routing sp4_v_t_43 sp4_v_b_9 (6 13) routing sp4_h_l_36 sp4_h_r_9 (6 13) routing sp4_h_l_44 sp4_h_r_9 (6 13) routing sp4_v_b_3 sp4_h_r_9 (6 13) routing sp4_v_b_9 sp4_h_r_9 (6 14) routing sp4_h_l_41 sp4_v_t_44 (6 14) routing sp4_h_r_3 sp4_v_t_44 (6 14) routing sp4_v_b_1 sp4_v_t_44 (6 14) routing sp4_v_b_6 sp4_v_t_44 (6 15) routing sp4_h_r_1 sp4_h_l_44 (6 15) routing sp4_h_r_9 sp4_h_l_44 (6 15) routing sp4_v_t_38 sp4_h_l_44 (6 15) routing sp4_v_t_44 sp4_h_l_44 (6 2) routing sp4_h_l_42 sp4_v_t_37 (6 2) routing sp4_h_r_6 sp4_v_t_37 (6 2) routing sp4_v_b_4 sp4_v_t_37 (6 2) routing sp4_v_b_9 sp4_v_t_37 (6 3) routing sp4_h_r_0 sp4_h_l_37 (6 3) routing sp4_h_r_4 sp4_h_l_37 (6 3) routing sp4_v_t_37 sp4_h_l_37 (6 3) routing sp4_v_t_43 sp4_h_l_37 (6 4) routing sp4_h_l_44 sp4_v_b_3 (6 4) routing sp4_h_r_10 sp4_v_b_3 (6 4) routing sp4_v_t_37 sp4_v_b_3 (6 4) routing sp4_v_t_42 sp4_v_b_3 (6 5) routing sp4_h_l_38 sp4_h_r_3 (6 5) routing sp4_h_l_42 sp4_h_r_3 (6 5) routing sp4_v_b_3 sp4_h_r_3 (6 5) routing sp4_v_b_9 sp4_h_r_3 (6 6) routing sp4_h_l_47 sp4_v_t_38 (6 6) routing sp4_h_r_9 sp4_v_t_38 (6 6) routing sp4_v_b_0 sp4_v_t_38 (6 6) routing sp4_v_b_7 sp4_v_t_38 (6 7) routing sp4_h_r_3 sp4_h_l_38 (6 7) routing sp4_h_r_7 sp4_h_l_38 (6 7) routing sp4_v_t_38 sp4_h_l_38 (6 7) routing sp4_v_t_44 sp4_h_l_38 (6 8) routing sp4_h_l_37 sp4_v_b_6 (6 8) routing sp4_h_r_1 sp4_v_b_6 (6 8) routing sp4_v_t_38 sp4_v_b_6 (6 8) routing sp4_v_t_47 sp4_v_b_6 (6 9) routing sp4_h_l_43 sp4_h_r_6 (6 9) routing sp4_h_l_47 sp4_h_r_6 (6 9) routing sp4_v_b_0 sp4_h_r_6 (6 9) routing sp4_v_b_6 sp4_h_r_6 (7 0) Ram config bit: MEMT_bram_cbit_1 (7 1) Ram config bit: MEMT_bram_cbit_0 (7 2) Ram config bit: MEMT_bram_cbit_3 (7 3) Ram config bit: MEMT_bram_cbit_2 (7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC00_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC01_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 (7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC00_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC01_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC03_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 (7 6) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC00_inmux02_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC01_inmux02_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_7 (7 7) Cascade bit: MEMT_LC00_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC00_inmux02_bram_cbit_6 (7 7) Cascade bit: MEMT_LC01_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC01_inmux02_bram_cbit_6 (7 7) Cascade bit: MEMT_LC02_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC03_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC04_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC05_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC06_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC07_inmux00_bram_cbit_6 (8 0) routing sp4_h_l_36 sp4_h_r_1 (8 0) routing sp4_h_l_40 sp4_h_r_1 (8 0) routing sp4_v_b_1 sp4_h_r_1 (8 0) routing sp4_v_b_7 sp4_h_r_1 (8 1) routing sp4_h_l_36 sp4_v_b_1 (8 1) routing sp4_h_l_42 sp4_v_b_1 (8 1) routing sp4_h_r_1 sp4_v_b_1 (8 1) routing sp4_v_t_47 sp4_v_b_1 (8 10) routing sp4_h_r_11 sp4_h_l_42 (8 10) routing sp4_h_r_7 sp4_h_l_42 (8 10) routing sp4_v_t_36 sp4_h_l_42 (8 10) routing sp4_v_t_42 sp4_h_l_42 (8 11) routing sp4_h_l_42 sp4_v_t_42 (8 11) routing sp4_h_r_1 sp4_v_t_42 (8 11) routing sp4_h_r_7 sp4_v_t_42 (8 11) routing sp4_v_b_4 sp4_v_t_42 (8 12) routing sp4_h_l_39 sp4_h_r_10 (8 12) routing sp4_h_l_47 sp4_h_r_10 (8 12) routing sp4_v_b_10 sp4_h_r_10 (8 12) routing sp4_v_b_4 sp4_h_r_10 (8 13) routing sp4_h_l_41 sp4_v_b_10 (8 13) routing sp4_h_l_47 sp4_v_b_10 (8 13) routing sp4_h_r_10 sp4_v_b_10 (8 13) routing sp4_v_t_42 sp4_v_b_10 (8 14) routing sp4_h_r_10 sp4_h_l_47 (8 14) routing sp4_h_r_2 sp4_h_l_47 (8 14) routing sp4_v_t_41 sp4_h_l_47 (8 14) routing sp4_v_t_47 sp4_h_l_47 (8 15) routing sp4_h_l_47 sp4_v_t_47 (8 15) routing sp4_h_r_10 sp4_v_t_47 (8 15) routing sp4_h_r_4 sp4_v_t_47 (8 15) routing sp4_v_b_7 sp4_v_t_47 (8 2) routing sp4_h_r_1 sp4_h_l_36 (8 2) routing sp4_h_r_5 sp4_h_l_36 (8 2) routing sp4_v_t_36 sp4_h_l_36 (8 2) routing sp4_v_t_42 sp4_h_l_36 (8 3) routing sp4_h_l_36 sp4_v_t_36 (8 3) routing sp4_h_r_1 sp4_v_t_36 (8 3) routing sp4_h_r_7 sp4_v_t_36 (8 3) routing sp4_v_b_10 sp4_v_t_36 (8 4) routing sp4_h_l_41 sp4_h_r_4 (8 4) routing sp4_h_l_45 sp4_h_r_4 (8 4) routing sp4_v_b_10 sp4_h_r_4 (8 4) routing sp4_v_b_4 sp4_h_r_4 (8 5) routing sp4_h_l_41 sp4_v_b_4 (8 5) routing sp4_h_l_47 sp4_v_b_4 (8 5) routing sp4_h_r_4 sp4_v_b_4 (8 5) routing sp4_v_t_36 sp4_v_b_4 (8 6) routing sp4_h_r_4 sp4_h_l_41 (8 6) routing sp4_h_r_8 sp4_h_l_41 (8 6) routing sp4_v_t_41 sp4_h_l_41 (8 6) routing sp4_v_t_47 sp4_h_l_41 (8 7) routing sp4_h_l_41 sp4_v_t_41 (8 7) routing sp4_h_r_10 sp4_v_t_41 (8 7) routing sp4_h_r_4 sp4_v_t_41 (8 7) routing sp4_v_b_1 sp4_v_t_41 (8 8) routing sp4_h_l_42 sp4_h_r_7 (8 8) routing sp4_h_l_46 sp4_h_r_7 (8 8) routing sp4_v_b_1 sp4_h_r_7 (8 8) routing sp4_v_b_7 sp4_h_r_7 (8 9) routing sp4_h_l_36 sp4_v_b_7 (8 9) routing sp4_h_l_42 sp4_v_b_7 (8 9) routing sp4_h_r_7 sp4_v_b_7 (8 9) routing sp4_v_t_41 sp4_v_b_7 (9 0) routing sp4_h_l_47 sp4_h_r_1 (9 0) routing sp4_v_b_1 sp4_h_r_1 (9 0) routing sp4_v_b_7 sp4_h_r_1 (9 0) routing sp4_v_t_36 sp4_h_r_1 (9 1) routing sp4_h_l_36 sp4_v_b_1 (9 1) routing sp4_h_l_42 sp4_v_b_1 (9 1) routing sp4_v_t_36 sp4_v_b_1 (9 1) routing sp4_v_t_40 sp4_v_b_1 (9 10) routing sp4_h_r_4 sp4_h_l_42 (9 10) routing sp4_v_b_7 sp4_h_l_42 (9 10) routing sp4_v_t_36 sp4_h_l_42 (9 10) routing sp4_v_t_42 sp4_h_l_42 (9 11) routing sp4_h_r_1 sp4_v_t_42 (9 11) routing sp4_h_r_7 sp4_v_t_42 (9 11) routing sp4_v_b_11 sp4_v_t_42 (9 11) routing sp4_v_b_7 sp4_v_t_42 (9 12) routing sp4_h_l_42 sp4_h_r_10 (9 12) routing sp4_v_b_10 sp4_h_r_10 (9 12) routing sp4_v_b_4 sp4_h_r_10 (9 12) routing sp4_v_t_47 sp4_h_r_10 (9 13) routing sp4_h_l_41 sp4_v_b_10 (9 13) routing sp4_h_l_47 sp4_v_b_10 (9 13) routing sp4_v_t_39 sp4_v_b_10 (9 13) routing sp4_v_t_47 sp4_v_b_10 (9 14) routing sp4_h_r_7 sp4_h_l_47 (9 14) routing sp4_v_b_10 sp4_h_l_47 (9 14) routing sp4_v_t_41 sp4_h_l_47 (9 14) routing sp4_v_t_47 sp4_h_l_47 (9 15) routing sp4_h_r_10 sp4_v_t_47 (9 15) routing sp4_h_r_4 sp4_v_t_47 (9 15) routing sp4_v_b_10 sp4_v_t_47 (9 15) routing sp4_v_b_2 sp4_v_t_47 (9 2) routing sp4_h_r_10 sp4_h_l_36 (9 2) routing sp4_v_b_1 sp4_h_l_36 (9 2) routing sp4_v_t_36 sp4_h_l_36 (9 2) routing sp4_v_t_42 sp4_h_l_36 (9 3) routing sp4_h_r_1 sp4_v_t_36 (9 3) routing sp4_h_r_7 sp4_v_t_36 (9 3) routing sp4_v_b_1 sp4_v_t_36 (9 3) routing sp4_v_b_5 sp4_v_t_36 (9 4) routing sp4_h_l_36 sp4_h_r_4 (9 4) routing sp4_v_b_10 sp4_h_r_4 (9 4) routing sp4_v_b_4 sp4_h_r_4 (9 4) routing sp4_v_t_41 sp4_h_r_4 (9 5) routing sp4_h_l_41 sp4_v_b_4 (9 5) routing sp4_h_l_47 sp4_v_b_4 (9 5) routing sp4_v_t_41 sp4_v_b_4 (9 5) routing sp4_v_t_45 sp4_v_b_4 (9 6) routing sp4_h_r_1 sp4_h_l_41 (9 6) routing sp4_v_b_4 sp4_h_l_41 (9 6) routing sp4_v_t_41 sp4_h_l_41 (9 6) routing sp4_v_t_47 sp4_h_l_41 (9 7) routing sp4_h_r_10 sp4_v_t_41 (9 7) routing sp4_h_r_4 sp4_v_t_41 (9 7) routing sp4_v_b_4 sp4_v_t_41 (9 7) routing sp4_v_b_8 sp4_v_t_41 (9 8) routing sp4_h_l_41 sp4_h_r_7 (9 8) routing sp4_v_b_1 sp4_h_r_7 (9 8) routing sp4_v_b_7 sp4_h_r_7 (9 8) routing sp4_v_t_42 sp4_h_r_7 (9 9) routing sp4_h_l_36 sp4_v_b_7 (9 9) routing sp4_h_l_42 sp4_v_b_7 (9 9) routing sp4_v_t_42 sp4_v_b_7 (9 9) routing sp4_v_t_46 sp4_v_b_7 fpga-icestorm-0~20160913git266e758/icefuzz/cached_ramt_8k.txt000066400000000000000000005641671276746530600234710ustar00rootroot00000000000000(0 0) Negative Clock bit (0 10) routing glb_netwk_2 glb2local_2 (0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 (0 10) routing glb_netwk_7 glb2local_2 (0 11) routing glb_netwk_1 glb2local_2 (0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 (0 11) routing glb_netwk_7 glb2local_2 (0 12) routing glb_netwk_2 glb2local_3 (0 12) routing glb_netwk_3 glb2local_3 (0 12) routing glb_netwk_6 glb2local_3 (0 12) routing glb_netwk_7 glb2local_3 (0 13) routing glb_netwk_1 glb2local_3 (0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 (0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/WE (0 14) routing glb_netwk_6 wire_bram/ram/WE (0 14) routing lc_trk_g2_4 wire_bram/ram/WE (0 14) routing lc_trk_g3_5 wire_bram/ram/WE (0 15) routing glb_netwk_2 wire_bram/ram/WE (0 15) routing glb_netwk_6 wire_bram/ram/WE (0 15) routing lc_trk_g1_5 wire_bram/ram/WE (0 15) routing lc_trk_g3_5 wire_bram/ram/WE (0 2) routing glb_netwk_2 wire_bram/ram/WCLK (0 2) routing glb_netwk_3 wire_bram/ram/WCLK (0 2) routing glb_netwk_6 wire_bram/ram/WCLK (0 2) routing glb_netwk_7 wire_bram/ram/WCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/WCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/WCLK (0 3) routing glb_netwk_1 wire_bram/ram/WCLK (0 3) routing glb_netwk_3 wire_bram/ram/WCLK (0 3) routing glb_netwk_5 wire_bram/ram/WCLK (0 3) routing glb_netwk_7 wire_bram/ram/WCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/WCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/WCLK (0 4) routing glb_netwk_5 wire_bram/ram/WCLKE (0 4) routing glb_netwk_7 wire_bram/ram/WCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/WCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/WCLKE (0 5) routing glb_netwk_3 wire_bram/ram/WCLKE (0 5) routing glb_netwk_7 wire_bram/ram/WCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE (0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 (0 6) routing glb_netwk_6 glb2local_0 (0 6) routing glb_netwk_7 glb2local_0 (0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 (0 7) routing glb_netwk_7 glb2local_0 (0 8) routing glb_netwk_2 glb2local_1 (0 8) routing glb_netwk_3 glb2local_1 (0 8) routing glb_netwk_6 glb2local_1 (0 8) routing glb_netwk_7 glb2local_1 (0 9) routing glb_netwk_1 glb2local_1 (0 9) routing glb_netwk_3 glb2local_1 (0 9) routing glb_netwk_5 glb2local_1 (0 9) routing glb_netwk_7 glb2local_1 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 (1 11) routing glb_netwk_7 glb2local_2 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 (1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 (1 13) routing glb_netwk_6 glb2local_3 (1 13) routing glb_netwk_7 glb2local_3 (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/WE (1 15) routing lc_trk_g0_4 wire_bram/ram/WE (1 15) routing lc_trk_g1_5 wire_bram/ram/WE (1 15) routing lc_trk_g2_4 wire_bram/ram/WE (1 15) routing lc_trk_g3_5 wire_bram/ram/WE (1 2) routing glb_netwk_4 wire_bram/ram/WCLK (1 2) routing glb_netwk_5 wire_bram/ram/WCLK (1 2) routing glb_netwk_6 wire_bram/ram/WCLK (1 2) routing glb_netwk_7 wire_bram/ram/WCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/WCLKE (1 5) routing lc_trk_g0_2 wire_bram/ram/WCLKE (1 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/WCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 (1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 (1 7) routing glb_netwk_6 glb2local_0 (1 7) routing glb_netwk_7 glb2local_0 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 (1 9) routing glb_netwk_4 glb2local_1 (1 9) routing glb_netwk_5 glb2local_1 (1 9) routing glb_netwk_6 glb2local_1 (1 9) routing glb_netwk_7 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 (10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 (10 0) routing sp4_v_t_45 sp4_h_r_1 (10 1) routing sp4_h_l_42 sp4_v_b_1 (10 1) routing sp4_h_r_8 sp4_v_b_1 (10 1) routing sp4_v_t_40 sp4_v_b_1 (10 1) routing sp4_v_t_47 sp4_v_b_1 (10 10) routing sp4_h_r_11 sp4_h_l_42 (10 10) routing sp4_h_r_4 sp4_h_l_42 (10 10) routing sp4_v_b_2 sp4_h_l_42 (10 10) routing sp4_v_t_36 sp4_h_l_42 (10 11) routing sp4_h_l_39 sp4_v_t_42 (10 11) routing sp4_h_r_1 sp4_v_t_42 (10 11) routing sp4_v_b_11 sp4_v_t_42 (10 11) routing sp4_v_b_4 sp4_v_t_42 (10 12) routing sp4_h_l_39 sp4_h_r_10 (10 12) routing sp4_h_l_42 sp4_h_r_10 (10 12) routing sp4_v_b_4 sp4_h_r_10 (10 12) routing sp4_v_t_40 sp4_h_r_10 (10 13) routing sp4_h_l_41 sp4_v_b_10 (10 13) routing sp4_h_r_5 sp4_v_b_10 (10 13) routing sp4_v_t_39 sp4_v_b_10 (10 13) routing sp4_v_t_42 sp4_v_b_10 (10 14) routing sp4_h_r_2 sp4_h_l_47 (10 14) routing sp4_h_r_7 sp4_h_l_47 (10 14) routing sp4_v_b_5 sp4_h_l_47 (10 14) routing sp4_v_t_41 sp4_h_l_47 (10 15) routing sp4_h_l_40 sp4_v_t_47 (10 15) routing sp4_h_r_4 sp4_v_t_47 (10 15) routing sp4_v_b_2 sp4_v_t_47 (10 15) routing sp4_v_b_7 sp4_v_t_47 (10 2) routing sp4_h_r_10 sp4_h_l_36 (10 2) routing sp4_h_r_5 sp4_h_l_36 (10 2) routing sp4_v_b_8 sp4_h_l_36 (10 2) routing sp4_v_t_42 sp4_h_l_36 (10 3) routing sp4_h_l_45 sp4_v_t_36 (10 3) routing sp4_h_r_7 sp4_v_t_36 (10 3) routing sp4_v_b_10 sp4_v_t_36 (10 3) routing sp4_v_b_5 sp4_v_t_36 (10 4) routing sp4_h_l_36 sp4_h_r_4 (10 4) routing sp4_h_l_45 sp4_h_r_4 (10 4) routing sp4_v_b_10 sp4_h_r_4 (10 4) routing sp4_v_t_46 sp4_h_r_4 (10 5) routing sp4_h_l_47 sp4_v_b_4 (10 5) routing sp4_h_r_11 sp4_v_b_4 (10 5) routing sp4_v_t_36 sp4_v_b_4 (10 5) routing sp4_v_t_45 sp4_v_b_4 (10 6) routing sp4_h_r_1 sp4_h_l_41 (10 6) routing sp4_h_r_8 sp4_h_l_41 (10 6) routing sp4_v_b_11 sp4_h_l_41 (10 6) routing sp4_v_t_47 sp4_h_l_41 (10 7) routing sp4_h_l_46 sp4_v_t_41 (10 7) routing sp4_h_r_10 sp4_v_t_41 (10 7) routing sp4_v_b_1 sp4_v_t_41 (10 7) routing sp4_v_b_8 sp4_v_t_41 (10 8) routing sp4_h_l_41 sp4_h_r_7 (10 8) routing sp4_h_l_46 sp4_h_r_7 (10 8) routing sp4_v_b_1 sp4_h_r_7 (10 8) routing sp4_v_t_39 sp4_h_r_7 (10 9) routing sp4_h_l_36 sp4_v_b_7 (10 9) routing sp4_h_r_2 sp4_v_b_7 (10 9) routing sp4_v_t_41 sp4_v_b_7 (10 9) routing sp4_v_t_46 sp4_v_b_7 (11 0) routing sp4_h_l_45 sp4_v_b_2 (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 (11 1) routing sp4_h_l_39 sp4_h_r_2 (11 1) routing sp4_h_l_43 sp4_h_r_2 (11 1) routing sp4_v_b_2 sp4_h_r_2 (11 1) routing sp4_v_b_8 sp4_h_r_2 (11 10) routing sp4_h_l_38 sp4_v_t_45 (11 10) routing sp4_h_r_2 sp4_v_t_45 (11 10) routing sp4_v_b_0 sp4_v_t_45 (11 10) routing sp4_v_b_5 sp4_v_t_45 (11 11) routing sp4_h_r_0 sp4_h_l_45 (11 11) routing sp4_h_r_8 sp4_h_l_45 (11 11) routing sp4_v_t_39 sp4_h_l_45 (11 11) routing sp4_v_t_45 sp4_h_l_45 (11 12) routing sp4_h_l_40 sp4_v_b_11 (11 12) routing sp4_h_r_6 sp4_v_b_11 (11 12) routing sp4_v_t_38 sp4_v_b_11 (11 12) routing sp4_v_t_45 sp4_v_b_11 (11 13) routing sp4_h_l_38 sp4_h_r_11 (11 13) routing sp4_h_l_46 sp4_h_r_11 (11 13) routing sp4_v_b_11 sp4_h_r_11 (11 13) routing sp4_v_b_5 sp4_h_r_11 (11 14) routing sp4_h_l_43 sp4_v_t_46 (11 14) routing sp4_h_r_5 sp4_v_t_46 (11 14) routing sp4_v_b_3 sp4_v_t_46 (11 14) routing sp4_v_b_8 sp4_v_t_46 (11 15) routing sp4_h_r_11 sp4_h_l_46 (11 15) routing sp4_h_r_3 sp4_h_l_46 (11 15) routing sp4_v_t_40 sp4_h_l_46 (11 15) routing sp4_v_t_46 sp4_h_l_46 (11 2) routing sp4_h_l_44 sp4_v_t_39 (11 2) routing sp4_h_r_8 sp4_v_t_39 (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 (11 3) routing sp4_h_r_2 sp4_h_l_39 (11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 (11 4) routing sp4_h_r_0 sp4_v_b_5 (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 (11 5) routing sp4_h_l_40 sp4_h_r_5 (11 5) routing sp4_h_l_44 sp4_h_r_5 (11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 (11 6) routing sp4_h_r_11 sp4_v_t_40 (11 6) routing sp4_v_b_2 sp4_v_t_40 (11 6) routing sp4_v_b_9 sp4_v_t_40 (11 7) routing sp4_h_r_5 sp4_h_l_40 (11 7) routing sp4_h_r_9 sp4_h_l_40 (11 7) routing sp4_v_t_40 sp4_h_l_40 (11 7) routing sp4_v_t_46 sp4_h_l_40 (11 8) routing sp4_h_l_39 sp4_v_b_8 (11 8) routing sp4_h_r_3 sp4_v_b_8 (11 8) routing sp4_v_t_37 sp4_v_b_8 (11 8) routing sp4_v_t_40 sp4_v_b_8 (11 9) routing sp4_h_l_37 sp4_h_r_8 (11 9) routing sp4_h_l_45 sp4_h_r_8 (11 9) routing sp4_v_b_2 sp4_h_r_8 (11 9) routing sp4_v_b_8 sp4_h_r_8 (12 0) routing sp4_h_l_46 sp4_h_r_2 (12 0) routing sp4_v_b_2 sp4_h_r_2 (12 0) routing sp4_v_b_8 sp4_h_r_2 (12 0) routing sp4_v_t_39 sp4_h_r_2 (12 1) routing sp4_h_l_39 sp4_v_b_2 (12 1) routing sp4_h_l_45 sp4_v_b_2 (12 1) routing sp4_h_r_2 sp4_v_b_2 (12 1) routing sp4_v_t_46 sp4_v_b_2 (12 10) routing sp4_h_r_5 sp4_h_l_45 (12 10) routing sp4_v_b_8 sp4_h_l_45 (12 10) routing sp4_v_t_39 sp4_h_l_45 (12 10) routing sp4_v_t_45 sp4_h_l_45 (12 11) routing sp4_h_l_45 sp4_v_t_45 (12 11) routing sp4_h_r_2 sp4_v_t_45 (12 11) routing sp4_h_r_8 sp4_v_t_45 (12 11) routing sp4_v_b_5 sp4_v_t_45 (12 12) routing sp4_h_l_45 sp4_h_r_11 (12 12) routing sp4_v_b_11 sp4_h_r_11 (12 12) routing sp4_v_b_5 sp4_h_r_11 (12 12) routing sp4_v_t_46 sp4_h_r_11 (12 13) routing sp4_h_l_40 sp4_v_b_11 (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 (12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 (12 14) routing sp4_v_t_46 sp4_h_l_46 (12 15) routing sp4_h_l_46 sp4_v_t_46 (12 15) routing sp4_h_r_11 sp4_v_t_46 (12 15) routing sp4_h_r_5 sp4_v_t_46 (12 15) routing sp4_v_b_8 sp4_v_t_46 (12 2) routing sp4_h_r_11 sp4_h_l_39 (12 2) routing sp4_v_b_2 sp4_h_l_39 (12 2) routing sp4_v_t_39 sp4_h_l_39 (12 2) routing sp4_v_t_45 sp4_h_l_39 (12 3) routing sp4_h_l_39 sp4_v_t_39 (12 3) routing sp4_h_r_2 sp4_v_t_39 (12 3) routing sp4_h_r_8 sp4_v_t_39 (12 3) routing sp4_v_b_11 sp4_v_t_39 (12 4) routing sp4_h_l_39 sp4_h_r_5 (12 4) routing sp4_v_b_11 sp4_h_r_5 (12 4) routing sp4_v_b_5 sp4_h_r_5 (12 4) routing sp4_v_t_40 sp4_h_r_5 (12 5) routing sp4_h_l_40 sp4_v_b_5 (12 5) routing sp4_h_l_46 sp4_v_b_5 (12 5) routing sp4_h_r_5 sp4_v_b_5 (12 5) routing sp4_v_t_39 sp4_v_b_5 (12 6) routing sp4_h_r_2 sp4_h_l_40 (12 6) routing sp4_v_b_5 sp4_h_l_40 (12 6) routing sp4_v_t_40 sp4_h_l_40 (12 6) routing sp4_v_t_46 sp4_h_l_40 (12 7) routing sp4_h_l_40 sp4_v_t_40 (12 7) routing sp4_h_r_11 sp4_v_t_40 (12 7) routing sp4_h_r_5 sp4_v_t_40 (12 7) routing sp4_v_b_2 sp4_v_t_40 (12 8) routing sp4_h_l_40 sp4_h_r_8 (12 8) routing sp4_v_b_2 sp4_h_r_8 (12 8) routing sp4_v_b_8 sp4_h_r_8 (12 8) routing sp4_v_t_45 sp4_h_r_8 (12 9) routing sp4_h_l_39 sp4_v_b_8 (12 9) routing sp4_h_l_45 sp4_v_b_8 (12 9) routing sp4_h_r_8 sp4_v_b_8 (12 9) routing sp4_v_t_40 sp4_v_b_8 (13 0) routing sp4_h_l_39 sp4_v_b_2 (13 0) routing sp4_h_l_45 sp4_v_b_2 (13 0) routing sp4_v_t_39 sp4_v_b_2 (13 0) routing sp4_v_t_43 sp4_v_b_2 (13 1) routing sp4_h_l_43 sp4_h_r_2 (13 1) routing sp4_h_l_46 sp4_h_r_2 (13 1) routing sp4_v_b_8 sp4_h_r_2 (13 1) routing sp4_v_t_44 sp4_h_r_2 (13 10) routing sp4_h_r_2 sp4_v_t_45 (13 10) routing sp4_h_r_8 sp4_v_t_45 (13 10) routing sp4_v_b_0 sp4_v_t_45 (13 10) routing sp4_v_b_8 sp4_v_t_45 (13 11) routing sp4_h_r_0 sp4_h_l_45 (13 11) routing sp4_h_r_5 sp4_h_l_45 (13 11) routing sp4_v_b_3 sp4_h_l_45 (13 11) routing sp4_v_t_39 sp4_h_l_45 (13 12) routing sp4_h_l_40 sp4_v_b_11 (13 12) routing sp4_h_l_46 sp4_v_b_11 (13 12) routing sp4_v_t_38 sp4_v_b_11 (13 12) routing sp4_v_t_46 sp4_v_b_11 (13 13) routing sp4_h_l_38 sp4_h_r_11 (13 13) routing sp4_h_l_45 sp4_h_r_11 (13 13) routing sp4_v_b_5 sp4_h_r_11 (13 13) routing sp4_v_t_43 sp4_h_r_11 (13 14) routing sp4_h_r_11 sp4_v_t_46 (13 14) routing sp4_h_r_5 sp4_v_t_46 (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 (13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 (13 2) routing sp4_h_r_8 sp4_v_t_39 (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 (13 3) routing sp4_h_r_11 sp4_h_l_39 (13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 (13 4) routing sp4_h_l_46 sp4_v_b_5 (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 (13 5) routing sp4_h_l_39 sp4_h_r_5 (13 5) routing sp4_h_l_44 sp4_h_r_5 (13 5) routing sp4_v_b_11 sp4_h_r_5 (13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 (13 6) routing sp4_h_r_5 sp4_v_t_40 (13 6) routing sp4_v_b_5 sp4_v_t_40 (13 6) routing sp4_v_b_9 sp4_v_t_40 (13 7) routing sp4_h_r_2 sp4_h_l_40 (13 7) routing sp4_h_r_9 sp4_h_l_40 (13 7) routing sp4_v_b_0 sp4_h_l_40 (13 7) routing sp4_v_t_46 sp4_h_l_40 (13 8) routing sp4_h_l_39 sp4_v_b_8 (13 8) routing sp4_h_l_45 sp4_v_b_8 (13 8) routing sp4_v_t_37 sp4_v_b_8 (13 8) routing sp4_v_t_45 sp4_v_b_8 (13 9) routing sp4_h_l_37 sp4_h_r_8 (13 9) routing sp4_h_l_40 sp4_h_r_8 (13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 (14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_l_5 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 (14 1) routing sp12_h_r_0 lc_trk_g0_0 (14 1) routing sp12_h_r_16 lc_trk_g0_0 (14 1) routing sp4_h_l_5 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing top_op_0 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 (14 10) routing rgt_op_4 lc_trk_g2_4 (14 10) routing sp12_v_t_3 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 (14 10) routing sp4_v_b_28 lc_trk_g2_4 (14 10) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing bnl_op_4 lc_trk_g2_4 (14 11) routing sp12_v_t_19 lc_trk_g2_4 (14 11) routing sp12_v_t_3 lc_trk_g2_4 (14 11) routing sp4_h_l_17 lc_trk_g2_4 (14 11) routing sp4_h_r_44 lc_trk_g2_4 (14 11) routing sp4_r_v_b_36 lc_trk_g2_4 (14 11) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing tnl_op_4 lc_trk_g2_4 (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 (14 12) routing sp12_v_b_0 lc_trk_g3_0 (14 12) routing sp4_h_l_21 lc_trk_g3_0 (14 12) routing sp4_h_l_29 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 12) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 (14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 (14 13) routing sp4_h_l_13 lc_trk_g3_0 (14 13) routing sp4_h_l_29 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing tnl_op_0 lc_trk_g3_0 (14 14) routing bnl_op_4 lc_trk_g3_4 (14 14) routing rgt_op_4 lc_trk_g3_4 (14 14) routing sp12_v_t_3 lc_trk_g3_4 (14 14) routing sp4_h_r_36 lc_trk_g3_4 (14 14) routing sp4_h_r_44 lc_trk_g3_4 (14 14) routing sp4_v_b_28 lc_trk_g3_4 (14 14) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing bnl_op_4 lc_trk_g3_4 (14 15) routing sp12_v_t_19 lc_trk_g3_4 (14 15) routing sp12_v_t_3 lc_trk_g3_4 (14 15) routing sp4_h_l_17 lc_trk_g3_4 (14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 (14 15) routing tnl_op_4 lc_trk_g3_4 (14 2) routing bnr_op_4 lc_trk_g0_4 (14 2) routing lft_op_4 lc_trk_g0_4 (14 2) routing sp12_h_l_3 lc_trk_g0_4 (14 2) routing sp4_h_r_12 lc_trk_g0_4 (14 2) routing sp4_h_r_20 lc_trk_g0_4 (14 2) routing sp4_v_b_4 lc_trk_g0_4 (14 2) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 (14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 (14 3) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing top_op_4 lc_trk_g0_4 (14 4) routing bnr_op_0 lc_trk_g1_0 (14 4) routing lft_op_0 lc_trk_g1_0 (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_l_5 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 (14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_r_0 lc_trk_g1_0 (14 5) routing sp12_h_r_16 lc_trk_g1_0 (14 5) routing sp4_h_l_5 lc_trk_g1_0 (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing top_op_0 lc_trk_g1_0 (14 6) routing bnr_op_4 lc_trk_g1_4 (14 6) routing lft_op_4 lc_trk_g1_4 (14 6) routing sp12_h_l_3 lc_trk_g1_4 (14 6) routing sp4_h_r_12 lc_trk_g1_4 (14 6) routing sp4_h_r_20 lc_trk_g1_4 (14 6) routing sp4_v_b_4 lc_trk_g1_4 (14 6) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing top_op_4 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 (14 8) routing rgt_op_0 lc_trk_g2_0 (14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_l_21 lc_trk_g2_0 (14 8) routing sp4_h_l_29 lc_trk_g2_0 (14 8) routing sp4_v_t_13 lc_trk_g2_0 (14 8) routing sp4_v_t_21 lc_trk_g2_0 (14 9) routing bnl_op_0 lc_trk_g2_0 (14 9) routing sp12_v_b_0 lc_trk_g2_0 (14 9) routing sp12_v_b_16 lc_trk_g2_0 (14 9) routing sp4_h_l_13 lc_trk_g2_0 (14 9) routing sp4_h_l_29 lc_trk_g2_0 (14 9) routing sp4_r_v_b_32 lc_trk_g2_0 (14 9) routing sp4_v_t_21 lc_trk_g2_0 (14 9) routing tnl_op_0 lc_trk_g2_0 (15 0) routing lft_op_1 lc_trk_g0_1 (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_b_17 lc_trk_g0_1 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_l_5 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 (15 1) routing sp4_v_b_16 lc_trk_g0_0 (15 1) routing top_op_0 lc_trk_g0_0 (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 (15 10) routing sp4_h_l_16 lc_trk_g2_5 (15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 (15 11) routing sp12_v_t_3 lc_trk_g2_4 (15 11) routing sp4_h_l_17 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 (15 11) routing sp4_h_r_44 lc_trk_g2_4 (15 11) routing sp4_v_t_33 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 (15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 (15 12) routing sp4_h_l_20 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 (15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 (15 13) routing sp4_h_l_13 lc_trk_g3_0 (15 13) routing sp4_h_l_21 lc_trk_g3_0 (15 13) routing sp4_h_l_29 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 (15 13) routing tnr_op_0 lc_trk_g3_0 (15 14) routing rgt_op_5 lc_trk_g3_5 (15 14) routing sp12_v_b_5 lc_trk_g3_5 (15 14) routing sp4_h_l_16 lc_trk_g3_5 (15 14) routing sp4_h_r_37 lc_trk_g3_5 (15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_b_45 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 (15 15) routing sp12_v_t_3 lc_trk_g3_4 (15 15) routing sp4_h_l_17 lc_trk_g3_4 (15 15) routing sp4_h_r_36 lc_trk_g3_4 (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_t_33 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 (15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing lft_op_5 lc_trk_g0_5 (15 2) routing sp12_h_r_5 lc_trk_g0_5 (15 2) routing sp4_h_l_8 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_r_12 lc_trk_g0_4 (15 3) routing sp4_h_r_20 lc_trk_g0_4 (15 3) routing sp4_h_r_4 lc_trk_g0_4 (15 3) routing sp4_v_b_20 lc_trk_g0_4 (15 3) routing top_op_4 lc_trk_g0_4 (15 4) routing lft_op_1 lc_trk_g1_1 (15 4) routing sp12_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_1 lc_trk_g1_1 (15 4) routing sp4_h_r_17 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_b_17 lc_trk_g1_1 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_l_5 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_b_16 lc_trk_g1_0 (15 5) routing top_op_0 lc_trk_g1_0 (15 6) routing lft_op_5 lc_trk_g1_5 (15 6) routing sp12_h_r_5 lc_trk_g1_5 (15 6) routing sp4_h_l_8 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_r_12 lc_trk_g1_4 (15 7) routing sp4_h_r_20 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 (15 7) routing top_op_4 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_20 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_l_13 lc_trk_g2_0 (15 9) routing sp4_h_l_21 lc_trk_g2_0 (15 9) routing sp4_h_l_29 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 (16 0) routing sp12_h_l_6 lc_trk_g0_1 (16 0) routing sp12_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_17 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 (16 1) routing sp12_h_r_16 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_l_5 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 (16 1) routing sp4_h_r_8 lc_trk_g0_0 (16 1) routing sp4_v_b_0 lc_trk_g0_0 (16 1) routing sp4_v_b_16 lc_trk_g0_0 (16 1) routing sp4_v_b_8 lc_trk_g0_0 (16 10) routing sp12_v_b_21 lc_trk_g2_5 (16 10) routing sp12_v_t_10 lc_trk_g2_5 (16 10) routing sp4_h_l_16 lc_trk_g2_5 (16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 (16 10) routing sp4_v_b_37 lc_trk_g2_5 (16 10) routing sp4_v_b_45 lc_trk_g2_5 (16 11) routing sp12_v_b_12 lc_trk_g2_4 (16 11) routing sp12_v_t_19 lc_trk_g2_4 (16 11) routing sp4_h_l_17 lc_trk_g2_4 (16 11) routing sp4_h_r_36 lc_trk_g2_4 (16 11) routing sp4_h_r_44 lc_trk_g2_4 (16 11) routing sp4_v_b_28 lc_trk_g2_4 (16 11) routing sp4_v_t_25 lc_trk_g2_4 (16 11) routing sp4_v_t_33 lc_trk_g2_4 (16 12) routing sp12_v_b_17 lc_trk_g3_1 (16 12) routing sp12_v_b_9 lc_trk_g3_1 (16 12) routing sp4_h_l_20 lc_trk_g3_1 (16 12) routing sp4_h_l_28 lc_trk_g3_1 (16 12) routing sp4_h_r_25 lc_trk_g3_1 (16 12) routing sp4_v_b_25 lc_trk_g3_1 (16 12) routing sp4_v_b_33 lc_trk_g3_1 (16 12) routing sp4_v_b_41 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 (16 13) routing sp4_h_l_13 lc_trk_g3_0 (16 13) routing sp4_h_l_21 lc_trk_g3_0 (16 13) routing sp4_h_l_29 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 (16 13) routing sp4_v_t_13 lc_trk_g3_0 (16 13) routing sp4_v_t_21 lc_trk_g3_0 (16 14) routing sp12_v_b_21 lc_trk_g3_5 (16 14) routing sp12_v_t_10 lc_trk_g3_5 (16 14) routing sp4_h_l_16 lc_trk_g3_5 (16 14) routing sp4_h_r_37 lc_trk_g3_5 (16 14) routing sp4_h_r_45 lc_trk_g3_5 (16 14) routing sp4_v_b_29 lc_trk_g3_5 (16 14) routing sp4_v_b_37 lc_trk_g3_5 (16 14) routing sp4_v_b_45 lc_trk_g3_5 (16 15) routing sp12_v_b_12 lc_trk_g3_4 (16 15) routing sp12_v_t_19 lc_trk_g3_4 (16 15) routing sp4_h_l_17 lc_trk_g3_4 (16 15) routing sp4_h_r_36 lc_trk_g3_4 (16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 15) routing sp4_v_t_33 lc_trk_g3_4 (16 2) routing sp12_h_l_18 lc_trk_g0_5 (16 2) routing sp12_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_l_8 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_5 lc_trk_g0_5 (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 (16 3) routing sp12_h_r_12 lc_trk_g0_4 (16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_12 lc_trk_g0_4 (16 3) routing sp4_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 (16 3) routing sp4_v_b_20 lc_trk_g0_4 (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 3) routing sp4_v_t_1 lc_trk_g0_4 (16 4) routing sp12_h_l_6 lc_trk_g1_1 (16 4) routing sp12_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 (16 4) routing sp4_v_b_1 lc_trk_g1_1 (16 4) routing sp4_v_b_17 lc_trk_g1_1 (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 5) routing sp12_h_r_16 lc_trk_g1_0 (16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_l_5 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_8 lc_trk_g1_0 (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 (16 6) routing sp12_h_l_18 lc_trk_g1_5 (16 6) routing sp12_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_l_8 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 (16 6) routing sp4_v_b_13 lc_trk_g1_5 (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 6) routing sp4_v_t_8 lc_trk_g1_5 (16 7) routing sp12_h_r_12 lc_trk_g1_4 (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_12 lc_trk_g1_4 (16 7) routing sp4_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_20 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 (16 7) routing sp4_v_t_1 lc_trk_g1_4 (16 8) routing sp12_v_b_17 lc_trk_g2_1 (16 8) routing sp12_v_b_9 lc_trk_g2_1 (16 8) routing sp4_h_l_20 lc_trk_g2_1 (16 8) routing sp4_h_l_28 lc_trk_g2_1 (16 8) routing sp4_h_r_25 lc_trk_g2_1 (16 8) routing sp4_v_b_25 lc_trk_g2_1 (16 8) routing sp4_v_b_33 lc_trk_g2_1 (16 8) routing sp4_v_b_41 lc_trk_g2_1 (16 9) routing sp12_v_b_16 lc_trk_g2_0 (16 9) routing sp12_v_t_7 lc_trk_g2_0 (16 9) routing sp4_h_l_13 lc_trk_g2_0 (16 9) routing sp4_h_l_21 lc_trk_g2_0 (16 9) routing sp4_h_l_29 lc_trk_g2_0 (16 9) routing sp4_v_b_40 lc_trk_g2_0 (16 9) routing sp4_v_t_13 lc_trk_g2_0 (16 9) routing sp4_v_t_21 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => top_op_0 lc_trk_g0_0 (17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 (17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 (17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => top_op_4 lc_trk_g0_4 (17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => top_op_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_r_17 lc_trk_g0_1 (18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp12_h_r_17 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 (18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_b_5 lc_trk_g2_5 (18 10) routing sp4_h_r_37 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_29 lc_trk_g2_5 (18 10) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing bnl_op_5 lc_trk_g2_5 (18 11) routing sp12_v_b_21 lc_trk_g2_5 (18 11) routing sp12_v_b_5 lc_trk_g2_5 (18 11) routing sp4_h_l_16 lc_trk_g2_5 (18 11) routing sp4_h_r_45 lc_trk_g2_5 (18 11) routing sp4_r_v_b_37 lc_trk_g2_5 (18 11) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 (18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 (18 12) routing sp4_h_l_20 lc_trk_g3_1 (18 12) routing sp4_h_l_28 lc_trk_g3_1 (18 12) routing sp4_v_b_25 lc_trk_g3_1 (18 12) routing sp4_v_b_33 lc_trk_g3_1 (18 13) routing bnl_op_1 lc_trk_g3_1 (18 13) routing sp12_v_b_1 lc_trk_g3_1 (18 13) routing sp12_v_b_17 lc_trk_g3_1 (18 13) routing sp4_h_l_28 lc_trk_g3_1 (18 13) routing sp4_h_r_25 lc_trk_g3_1 (18 13) routing sp4_r_v_b_41 lc_trk_g3_1 (18 13) routing sp4_v_b_33 lc_trk_g3_1 (18 13) routing tnl_op_1 lc_trk_g3_1 (18 14) routing bnl_op_5 lc_trk_g3_5 (18 14) routing rgt_op_5 lc_trk_g3_5 (18 14) routing sp12_v_b_5 lc_trk_g3_5 (18 14) routing sp4_h_r_37 lc_trk_g3_5 (18 14) routing sp4_h_r_45 lc_trk_g3_5 (18 14) routing sp4_v_b_29 lc_trk_g3_5 (18 14) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing bnl_op_5 lc_trk_g3_5 (18 15) routing sp12_v_b_21 lc_trk_g3_5 (18 15) routing sp12_v_b_5 lc_trk_g3_5 (18 15) routing sp4_h_l_16 lc_trk_g3_5 (18 15) routing sp4_h_r_45 lc_trk_g3_5 (18 15) routing sp4_r_v_b_45 lc_trk_g3_5 (18 15) routing sp4_v_b_37 lc_trk_g3_5 (18 15) routing tnl_op_5 lc_trk_g3_5 (18 2) routing bnr_op_5 lc_trk_g0_5 (18 2) routing lft_op_5 lc_trk_g0_5 (18 2) routing sp12_h_r_5 lc_trk_g0_5 (18 2) routing sp4_h_l_8 lc_trk_g0_5 (18 2) routing sp4_h_r_13 lc_trk_g0_5 (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 (18 3) routing sp12_h_l_18 lc_trk_g0_5 (18 3) routing sp12_h_r_5 lc_trk_g0_5 (18 3) routing sp4_h_l_8 lc_trk_g0_5 (18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 (18 3) routing sp4_v_b_13 lc_trk_g0_5 (18 4) routing bnr_op_1 lc_trk_g1_1 (18 4) routing lft_op_1 lc_trk_g1_1 (18 4) routing sp12_h_r_1 lc_trk_g1_1 (18 4) routing sp4_h_r_17 lc_trk_g1_1 (18 4) routing sp4_h_r_9 lc_trk_g1_1 (18 4) routing sp4_v_b_1 lc_trk_g1_1 (18 4) routing sp4_v_b_9 lc_trk_g1_1 (18 5) routing bnr_op_1 lc_trk_g1_1 (18 5) routing sp12_h_r_1 lc_trk_g1_1 (18 5) routing sp12_h_r_17 lc_trk_g1_1 (18 5) routing sp4_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_r_17 lc_trk_g1_1 (18 5) routing sp4_r_v_b_25 lc_trk_g1_1 (18 5) routing sp4_v_b_9 lc_trk_g1_1 (18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 (18 6) routing sp12_h_r_5 lc_trk_g1_5 (18 6) routing sp4_h_l_8 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 (18 7) routing sp12_h_l_18 lc_trk_g1_5 (18 7) routing sp12_h_r_5 lc_trk_g1_5 (18 7) routing sp4_h_l_8 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_20 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 (18 8) routing sp4_v_b_25 lc_trk_g2_1 (18 8) routing sp4_v_b_33 lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 (18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_b_17 lc_trk_g2_1 (18 9) routing sp4_h_l_28 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 (18 9) routing sp4_r_v_b_33 lc_trk_g2_1 (18 9) routing sp4_v_b_33 lc_trk_g2_1 (18 9) routing tnl_op_1 lc_trk_g2_1 (19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13 (19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 (19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 (19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 (19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13 (19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 (19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 (19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 (19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2 (19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 (19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 (19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 (19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 (19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7 (19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 (19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_b_17 sp4_v_b_20 (2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5 (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/WCLK (2 3) routing lc_trk_g0_0 wire_bram/ram/WCLK (2 3) routing lc_trk_g1_1 wire_bram/ram/WCLK (2 3) routing lc_trk_g2_0 wire_bram/ram/WCLK (2 3) routing lc_trk_g3_1 wire_bram/ram/WCLK (2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7 (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 (2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 (21 0) routing bnr_op_3 lc_trk_g0_3 (21 0) routing lft_op_3 lc_trk_g0_3 (21 0) routing sp12_h_l_0 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_h_r_19 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 (21 1) routing sp12_h_l_0 lc_trk_g0_3 (21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp4_h_r_19 lc_trk_g0_3 (21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 (21 1) routing sp4_v_b_11 lc_trk_g0_3 (21 10) routing bnl_op_7 lc_trk_g2_7 (21 10) routing rgt_op_7 lc_trk_g2_7 (21 10) routing sp12_v_b_7 lc_trk_g2_7 (21 10) routing sp4_h_l_26 lc_trk_g2_7 (21 10) routing sp4_h_r_47 lc_trk_g2_7 (21 10) routing sp4_v_t_18 lc_trk_g2_7 (21 10) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing bnl_op_7 lc_trk_g2_7 (21 11) routing sp12_v_b_23 lc_trk_g2_7 (21 11) routing sp12_v_b_7 lc_trk_g2_7 (21 11) routing sp4_h_l_18 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 (21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_t_0 lc_trk_g3_3 (21 12) routing sp4_h_l_30 lc_trk_g3_3 (21 12) routing sp4_h_r_35 lc_trk_g3_3 (21 12) routing sp4_v_t_14 lc_trk_g3_3 (21 12) routing sp4_v_t_22 lc_trk_g3_3 (21 13) routing bnl_op_3 lc_trk_g3_3 (21 13) routing sp12_v_t_0 lc_trk_g3_3 (21 13) routing sp12_v_t_16 lc_trk_g3_3 (21 13) routing sp4_h_l_30 lc_trk_g3_3 (21 13) routing sp4_h_r_27 lc_trk_g3_3 (21 13) routing sp4_r_v_b_43 lc_trk_g3_3 (21 13) routing sp4_v_t_22 lc_trk_g3_3 (21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 (21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_b_7 lc_trk_g3_7 (21 14) routing sp4_h_l_26 lc_trk_g3_7 (21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_t_18 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_b_23 lc_trk_g3_7 (21 15) routing sp12_v_b_7 lc_trk_g3_7 (21 15) routing sp4_h_l_18 lc_trk_g3_7 (21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 (21 2) routing sp12_h_l_4 lc_trk_g0_7 (21 2) routing sp4_h_l_10 lc_trk_g0_7 (21 2) routing sp4_h_l_2 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_4 lc_trk_g0_7 (21 3) routing sp12_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_l_10 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 (21 3) routing sp4_v_t_2 lc_trk_g0_7 (21 4) routing bnr_op_3 lc_trk_g1_3 (21 4) routing lft_op_3 lc_trk_g1_3 (21 4) routing sp12_h_l_0 lc_trk_g1_3 (21 4) routing sp4_h_r_11 lc_trk_g1_3 (21 4) routing sp4_h_r_19 lc_trk_g1_3 (21 4) routing sp4_v_b_11 lc_trk_g1_3 (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_0 lc_trk_g1_3 (21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp4_h_r_19 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 (21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_l_4 lc_trk_g1_7 (21 6) routing sp4_h_l_10 lc_trk_g1_7 (21 6) routing sp4_h_l_2 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 (21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_4 lc_trk_g1_7 (21 7) routing sp12_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_l_10 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_t_0 lc_trk_g2_3 (21 8) routing sp4_h_l_30 lc_trk_g2_3 (21 8) routing sp4_h_r_35 lc_trk_g2_3 (21 8) routing sp4_v_t_14 lc_trk_g2_3 (21 8) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing bnl_op_3 lc_trk_g2_3 (21 9) routing sp12_v_t_0 lc_trk_g2_3 (21 9) routing sp12_v_t_16 lc_trk_g2_3 (21 9) routing sp4_h_l_30 lc_trk_g2_3 (21 9) routing sp4_h_r_27 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 (22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 (22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 (22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 (22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 (22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 (22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 (22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 (23 0) routing sp12_h_l_16 lc_trk_g0_3 (23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_19 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 (23 0) routing sp4_v_b_11 lc_trk_g0_3 (23 0) routing sp4_v_b_19 lc_trk_g0_3 (23 0) routing sp4_v_b_3 lc_trk_g0_3 (23 1) routing sp12_h_r_10 lc_trk_g0_2 (23 1) routing sp12_h_r_18 lc_trk_g0_2 (23 1) routing sp4_h_l_7 lc_trk_g0_2 (23 1) routing sp4_h_r_10 lc_trk_g0_2 (23 1) routing sp4_h_r_2 lc_trk_g0_2 (23 1) routing sp4_v_b_10 lc_trk_g0_2 (23 1) routing sp4_v_b_2 lc_trk_g0_2 (23 1) routing sp4_v_t_7 lc_trk_g0_2 (23 10) routing sp12_v_b_23 lc_trk_g2_7 (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp4_h_l_18 lc_trk_g2_7 (23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_47 lc_trk_g2_7 (23 10) routing sp4_v_t_18 lc_trk_g2_7 (23 10) routing sp4_v_t_26 lc_trk_g2_7 (23 11) routing sp12_v_b_14 lc_trk_g2_6 (23 11) routing sp12_v_t_21 lc_trk_g2_6 (23 11) routing sp4_h_l_27 lc_trk_g2_6 (23 11) routing sp4_h_r_30 lc_trk_g2_6 (23 11) routing sp4_h_r_46 lc_trk_g2_6 (23 11) routing sp4_v_b_30 lc_trk_g2_6 (23 11) routing sp4_v_b_38 lc_trk_g2_6 (23 11) routing sp4_v_b_46 lc_trk_g2_6 (23 12) routing sp12_v_b_11 lc_trk_g3_3 (23 12) routing sp12_v_t_16 lc_trk_g3_3 (23 12) routing sp4_h_l_30 lc_trk_g3_3 (23 12) routing sp4_h_r_27 lc_trk_g3_3 (23 12) routing sp4_h_r_35 lc_trk_g3_3 (23 12) routing sp4_v_t_14 lc_trk_g3_3 (23 12) routing sp4_v_t_22 lc_trk_g3_3 (23 12) routing sp4_v_t_30 lc_trk_g3_3 (23 13) routing sp12_v_t_17 lc_trk_g3_2 (23 13) routing sp12_v_t_9 lc_trk_g3_2 (23 13) routing sp4_h_l_15 lc_trk_g3_2 (23 13) routing sp4_h_r_34 lc_trk_g3_2 (23 13) routing sp4_h_r_42 lc_trk_g3_2 (23 13) routing sp4_v_b_26 lc_trk_g3_2 (23 13) routing sp4_v_t_23 lc_trk_g3_2 (23 13) routing sp4_v_t_31 lc_trk_g3_2 (23 14) routing sp12_v_b_23 lc_trk_g3_7 (23 14) routing sp12_v_t_12 lc_trk_g3_7 (23 14) routing sp4_h_l_18 lc_trk_g3_7 (23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_47 lc_trk_g3_7 (23 14) routing sp4_v_t_18 lc_trk_g3_7 (23 14) routing sp4_v_t_26 lc_trk_g3_7 (23 15) routing sp12_v_b_14 lc_trk_g3_6 (23 15) routing sp12_v_t_21 lc_trk_g3_6 (23 15) routing sp4_h_l_27 lc_trk_g3_6 (23 15) routing sp4_h_r_30 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_30 lc_trk_g3_6 (23 15) routing sp4_v_b_38 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 (23 2) routing sp12_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_l_10 lc_trk_g0_7 (23 2) routing sp4_h_l_2 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_10 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 (23 3) routing sp12_h_l_13 lc_trk_g0_6 (23 3) routing sp12_h_l_21 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 (23 3) routing sp4_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_r_6 lc_trk_g0_6 (23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_22 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 (23 4) routing sp12_h_l_16 lc_trk_g1_3 (23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_19 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 (23 4) routing sp4_v_b_11 lc_trk_g1_3 (23 4) routing sp4_v_b_19 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 5) routing sp12_h_r_10 lc_trk_g1_2 (23 5) routing sp12_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_l_7 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 (23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 (23 6) routing sp12_h_l_12 lc_trk_g1_7 (23 6) routing sp12_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_l_10 lc_trk_g1_7 (23 6) routing sp4_h_l_2 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 (23 6) routing sp4_v_b_7 lc_trk_g1_7 (23 6) routing sp4_v_t_10 lc_trk_g1_7 (23 6) routing sp4_v_t_2 lc_trk_g1_7 (23 7) routing sp12_h_l_13 lc_trk_g1_6 (23 7) routing sp12_h_l_21 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_22 lc_trk_g1_6 (23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_14 lc_trk_g1_6 (23 7) routing sp4_v_b_22 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 8) routing sp12_v_b_11 lc_trk_g2_3 (23 8) routing sp12_v_t_16 lc_trk_g2_3 (23 8) routing sp4_h_l_30 lc_trk_g2_3 (23 8) routing sp4_h_r_27 lc_trk_g2_3 (23 8) routing sp4_h_r_35 lc_trk_g2_3 (23 8) routing sp4_v_t_14 lc_trk_g2_3 (23 8) routing sp4_v_t_22 lc_trk_g2_3 (23 8) routing sp4_v_t_30 lc_trk_g2_3 (23 9) routing sp12_v_t_17 lc_trk_g2_2 (23 9) routing sp12_v_t_9 lc_trk_g2_2 (23 9) routing sp4_h_l_15 lc_trk_g2_2 (23 9) routing sp4_h_r_34 lc_trk_g2_2 (23 9) routing sp4_h_r_42 lc_trk_g2_2 (23 9) routing sp4_v_b_26 lc_trk_g2_2 (23 9) routing sp4_v_t_23 lc_trk_g2_2 (23 9) routing sp4_v_t_31 lc_trk_g2_2 (24 0) routing lft_op_3 lc_trk_g0_3 (24 0) routing sp12_h_l_0 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_19 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 (24 0) routing sp4_v_b_19 lc_trk_g0_3 (24 1) routing lft_op_2 lc_trk_g0_2 (24 1) routing sp12_h_r_2 lc_trk_g0_2 (24 1) routing sp4_h_l_7 lc_trk_g0_2 (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_t_7 lc_trk_g0_2 (24 1) routing top_op_2 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_b_7 lc_trk_g2_7 (24 10) routing sp4_h_l_18 lc_trk_g2_7 (24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_b_47 lc_trk_g2_7 (24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_b_6 lc_trk_g2_6 (24 11) routing sp4_h_l_27 lc_trk_g2_6 (24 11) routing sp4_h_r_30 lc_trk_g2_6 (24 11) routing sp4_h_r_46 lc_trk_g2_6 (24 11) routing sp4_v_b_46 lc_trk_g2_6 (24 11) routing tnl_op_6 lc_trk_g2_6 (24 11) routing tnr_op_6 lc_trk_g2_6 (24 12) routing rgt_op_3 lc_trk_g3_3 (24 12) routing sp12_v_t_0 lc_trk_g3_3 (24 12) routing sp4_h_l_30 lc_trk_g3_3 (24 12) routing sp4_h_r_27 lc_trk_g3_3 (24 12) routing sp4_h_r_35 lc_trk_g3_3 (24 12) routing sp4_v_t_30 lc_trk_g3_3 (24 12) routing tnl_op_3 lc_trk_g3_3 (24 12) routing tnr_op_3 lc_trk_g3_3 (24 13) routing rgt_op_2 lc_trk_g3_2 (24 13) routing sp12_v_b_2 lc_trk_g3_2 (24 13) routing sp4_h_l_15 lc_trk_g3_2 (24 13) routing sp4_h_r_34 lc_trk_g3_2 (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 (24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_b_7 lc_trk_g3_7 (24 14) routing sp4_h_l_18 lc_trk_g3_7 (24 14) routing sp4_h_l_26 lc_trk_g3_7 (24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_b_47 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 (24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_b_6 lc_trk_g3_6 (24 15) routing sp4_h_l_27 lc_trk_g3_6 (24 15) routing sp4_h_r_30 lc_trk_g3_6 (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 (24 2) routing sp12_h_l_4 lc_trk_g0_7 (24 2) routing sp4_h_l_10 lc_trk_g0_7 (24 2) routing sp4_h_l_2 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_t_10 lc_trk_g0_7 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_3 lc_trk_g0_6 (24 3) routing sp4_h_r_22 lc_trk_g0_6 (24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_b_22 lc_trk_g0_6 (24 3) routing top_op_6 lc_trk_g0_6 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_l_0 lc_trk_g1_3 (24 4) routing sp4_h_r_11 lc_trk_g1_3 (24 4) routing sp4_h_r_19 lc_trk_g1_3 (24 4) routing sp4_h_r_3 lc_trk_g1_3 (24 4) routing sp4_v_b_19 lc_trk_g1_3 (24 5) routing lft_op_2 lc_trk_g1_2 (24 5) routing sp12_h_r_2 lc_trk_g1_2 (24 5) routing sp4_h_l_7 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 (24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_t_7 lc_trk_g1_2 (24 5) routing top_op_2 lc_trk_g1_2 (24 6) routing lft_op_7 lc_trk_g1_7 (24 6) routing sp12_h_l_4 lc_trk_g1_7 (24 6) routing sp4_h_l_10 lc_trk_g1_7 (24 6) routing sp4_h_l_2 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 (24 6) routing sp4_v_t_10 lc_trk_g1_7 (24 7) routing lft_op_6 lc_trk_g1_6 (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_3 lc_trk_g1_6 (24 7) routing sp4_h_r_22 lc_trk_g1_6 (24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_b_22 lc_trk_g1_6 (24 7) routing top_op_6 lc_trk_g1_6 (24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_t_0 lc_trk_g2_3 (24 8) routing sp4_h_l_30 lc_trk_g2_3 (24 8) routing sp4_h_r_27 lc_trk_g2_3 (24 8) routing sp4_h_r_35 lc_trk_g2_3 (24 8) routing sp4_v_t_30 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 (24 8) routing tnr_op_3 lc_trk_g2_3 (24 9) routing rgt_op_2 lc_trk_g2_2 (24 9) routing sp12_v_b_2 lc_trk_g2_2 (24 9) routing sp4_h_l_15 lc_trk_g2_2 (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 (25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_r_2 lc_trk_g0_2 (25 0) routing sp4_h_l_7 lc_trk_g0_2 (25 0) routing sp4_h_r_10 lc_trk_g0_2 (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 (25 1) routing bnr_op_2 lc_trk_g0_2 (25 1) routing sp12_h_r_18 lc_trk_g0_2 (25 1) routing sp12_h_r_2 lc_trk_g0_2 (25 1) routing sp4_h_l_7 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 (25 1) routing top_op_2 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_b_6 lc_trk_g2_6 (25 10) routing sp4_h_l_27 lc_trk_g2_6 (25 10) routing sp4_h_r_46 lc_trk_g2_6 (25 10) routing sp4_v_b_30 lc_trk_g2_6 (25 10) routing sp4_v_b_38 lc_trk_g2_6 (25 11) routing bnl_op_6 lc_trk_g2_6 (25 11) routing sp12_v_b_6 lc_trk_g2_6 (25 11) routing sp12_v_t_21 lc_trk_g2_6 (25 11) routing sp4_h_r_30 lc_trk_g2_6 (25 11) routing sp4_h_r_46 lc_trk_g2_6 (25 11) routing sp4_r_v_b_38 lc_trk_g2_6 (25 11) routing sp4_v_b_38 lc_trk_g2_6 (25 11) routing tnl_op_6 lc_trk_g2_6 (25 12) routing bnl_op_2 lc_trk_g3_2 (25 12) routing rgt_op_2 lc_trk_g3_2 (25 12) routing sp12_v_b_2 lc_trk_g3_2 (25 12) routing sp4_h_r_34 lc_trk_g3_2 (25 12) routing sp4_h_r_42 lc_trk_g3_2 (25 12) routing sp4_v_b_26 lc_trk_g3_2 (25 12) routing sp4_v_t_23 lc_trk_g3_2 (25 13) routing bnl_op_2 lc_trk_g3_2 (25 13) routing sp12_v_b_2 lc_trk_g3_2 (25 13) routing sp12_v_t_17 lc_trk_g3_2 (25 13) routing sp4_h_l_15 lc_trk_g3_2 (25 13) routing sp4_h_r_42 lc_trk_g3_2 (25 13) routing sp4_r_v_b_42 lc_trk_g3_2 (25 13) routing sp4_v_t_23 lc_trk_g3_2 (25 13) routing tnl_op_2 lc_trk_g3_2 (25 14) routing bnl_op_6 lc_trk_g3_6 (25 14) routing rgt_op_6 lc_trk_g3_6 (25 14) routing sp12_v_b_6 lc_trk_g3_6 (25 14) routing sp4_h_l_27 lc_trk_g3_6 (25 14) routing sp4_h_r_46 lc_trk_g3_6 (25 14) routing sp4_v_b_30 lc_trk_g3_6 (25 14) routing sp4_v_b_38 lc_trk_g3_6 (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_6 lc_trk_g3_6 (25 15) routing sp12_v_t_21 lc_trk_g3_6 (25 15) routing sp4_h_r_30 lc_trk_g3_6 (25 15) routing sp4_h_r_46 lc_trk_g3_6 (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_b_38 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 (25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 (25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_3 lc_trk_g0_6 (25 2) routing sp4_h_r_22 lc_trk_g0_6 (25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_21 lc_trk_g0_6 (25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp4_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 (25 3) routing sp4_v_b_14 lc_trk_g0_6 (25 3) routing top_op_6 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_r_2 lc_trk_g1_2 (25 4) routing sp4_h_l_7 lc_trk_g1_2 (25 4) routing sp4_h_r_10 lc_trk_g1_2 (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 (25 5) routing sp12_h_r_18 lc_trk_g1_2 (25 5) routing sp12_h_r_2 lc_trk_g1_2 (25 5) routing sp4_h_l_7 lc_trk_g1_2 (25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 (25 5) routing top_op_2 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 (25 6) routing sp4_h_l_3 lc_trk_g1_6 (25 6) routing sp4_h_r_22 lc_trk_g1_6 (25 6) routing sp4_v_b_14 lc_trk_g1_6 (25 6) routing sp4_v_b_6 lc_trk_g1_6 (25 7) routing bnr_op_6 lc_trk_g1_6 (25 7) routing sp12_h_l_21 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp4_h_r_22 lc_trk_g1_6 (25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_b_14 lc_trk_g1_6 (25 7) routing top_op_6 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_b_2 lc_trk_g2_2 (25 8) routing sp4_h_r_34 lc_trk_g2_2 (25 8) routing sp4_h_r_42 lc_trk_g2_2 (25 8) routing sp4_v_b_26 lc_trk_g2_2 (25 8) routing sp4_v_t_23 lc_trk_g2_2 (25 9) routing bnl_op_2 lc_trk_g2_2 (25 9) routing sp12_v_b_2 lc_trk_g2_2 (25 9) routing sp12_v_t_17 lc_trk_g2_2 (25 9) routing sp4_h_l_15 lc_trk_g2_2 (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_t_23 lc_trk_g2_2 (25 9) routing tnl_op_2 lc_trk_g2_2 (26 0) routing lc_trk_g0_4 input0_0 (26 0) routing lc_trk_g0_6 input0_0 (26 0) routing lc_trk_g1_5 input0_0 (26 0) routing lc_trk_g1_7 input0_0 (26 0) routing lc_trk_g2_4 input0_0 (26 0) routing lc_trk_g2_6 input0_0 (26 0) routing lc_trk_g3_5 input0_0 (26 0) routing lc_trk_g3_7 input0_0 (26 1) routing lc_trk_g0_2 input0_0 (26 1) routing lc_trk_g0_6 input0_0 (26 1) routing lc_trk_g1_3 input0_0 (26 1) routing lc_trk_g1_7 input0_0 (26 1) routing lc_trk_g2_2 input0_0 (26 1) routing lc_trk_g2_6 input0_0 (26 1) routing lc_trk_g3_3 input0_0 (26 1) routing lc_trk_g3_7 input0_0 (26 10) routing lc_trk_g0_5 input0_5 (26 10) routing lc_trk_g0_7 input0_5 (26 10) routing lc_trk_g1_4 input0_5 (26 10) routing lc_trk_g1_6 input0_5 (26 10) routing lc_trk_g2_5 input0_5 (26 10) routing lc_trk_g2_7 input0_5 (26 10) routing lc_trk_g3_4 input0_5 (26 10) routing lc_trk_g3_6 input0_5 (26 11) routing lc_trk_g0_3 input0_5 (26 11) routing lc_trk_g0_7 input0_5 (26 11) routing lc_trk_g1_2 input0_5 (26 11) routing lc_trk_g1_6 input0_5 (26 11) routing lc_trk_g2_3 input0_5 (26 11) routing lc_trk_g2_7 input0_5 (26 11) routing lc_trk_g3_2 input0_5 (26 11) routing lc_trk_g3_6 input0_5 (26 12) routing lc_trk_g0_4 input0_6 (26 12) routing lc_trk_g0_6 input0_6 (26 12) routing lc_trk_g1_5 input0_6 (26 12) routing lc_trk_g1_7 input0_6 (26 12) routing lc_trk_g2_4 input0_6 (26 12) routing lc_trk_g2_6 input0_6 (26 12) routing lc_trk_g3_5 input0_6 (26 12) routing lc_trk_g3_7 input0_6 (26 13) routing lc_trk_g0_2 input0_6 (26 13) routing lc_trk_g0_6 input0_6 (26 13) routing lc_trk_g1_3 input0_6 (26 13) routing lc_trk_g1_7 input0_6 (26 13) routing lc_trk_g2_2 input0_6 (26 13) routing lc_trk_g2_6 input0_6 (26 13) routing lc_trk_g3_3 input0_6 (26 13) routing lc_trk_g3_7 input0_6 (26 14) routing lc_trk_g0_5 input0_7 (26 14) routing lc_trk_g0_7 input0_7 (26 14) routing lc_trk_g1_4 input0_7 (26 14) routing lc_trk_g1_6 input0_7 (26 14) routing lc_trk_g2_5 input0_7 (26 14) routing lc_trk_g2_7 input0_7 (26 14) routing lc_trk_g3_4 input0_7 (26 14) routing lc_trk_g3_6 input0_7 (26 15) routing lc_trk_g0_3 input0_7 (26 15) routing lc_trk_g0_7 input0_7 (26 15) routing lc_trk_g1_2 input0_7 (26 15) routing lc_trk_g1_6 input0_7 (26 15) routing lc_trk_g2_3 input0_7 (26 15) routing lc_trk_g2_7 input0_7 (26 15) routing lc_trk_g3_2 input0_7 (26 15) routing lc_trk_g3_6 input0_7 (26 2) routing lc_trk_g0_5 input0_1 (26 2) routing lc_trk_g0_7 input0_1 (26 2) routing lc_trk_g1_4 input0_1 (26 2) routing lc_trk_g1_6 input0_1 (26 2) routing lc_trk_g2_5 input0_1 (26 2) routing lc_trk_g2_7 input0_1 (26 2) routing lc_trk_g3_4 input0_1 (26 2) routing lc_trk_g3_6 input0_1 (26 3) routing lc_trk_g0_3 input0_1 (26 3) routing lc_trk_g0_7 input0_1 (26 3) routing lc_trk_g1_2 input0_1 (26 3) routing lc_trk_g1_6 input0_1 (26 3) routing lc_trk_g2_3 input0_1 (26 3) routing lc_trk_g2_7 input0_1 (26 3) routing lc_trk_g3_2 input0_1 (26 3) routing lc_trk_g3_6 input0_1 (26 4) routing lc_trk_g0_4 input0_2 (26 4) routing lc_trk_g0_6 input0_2 (26 4) routing lc_trk_g1_5 input0_2 (26 4) routing lc_trk_g1_7 input0_2 (26 4) routing lc_trk_g2_4 input0_2 (26 4) routing lc_trk_g2_6 input0_2 (26 4) routing lc_trk_g3_5 input0_2 (26 4) routing lc_trk_g3_7 input0_2 (26 5) routing lc_trk_g0_2 input0_2 (26 5) routing lc_trk_g0_6 input0_2 (26 5) routing lc_trk_g1_3 input0_2 (26 5) routing lc_trk_g1_7 input0_2 (26 5) routing lc_trk_g2_2 input0_2 (26 5) routing lc_trk_g2_6 input0_2 (26 5) routing lc_trk_g3_3 input0_2 (26 5) routing lc_trk_g3_7 input0_2 (26 6) routing lc_trk_g0_5 input0_3 (26 6) routing lc_trk_g0_7 input0_3 (26 6) routing lc_trk_g1_4 input0_3 (26 6) routing lc_trk_g1_6 input0_3 (26 6) routing lc_trk_g2_5 input0_3 (26 6) routing lc_trk_g2_7 input0_3 (26 6) routing lc_trk_g3_4 input0_3 (26 6) routing lc_trk_g3_6 input0_3 (26 7) routing lc_trk_g0_3 input0_3 (26 7) routing lc_trk_g0_7 input0_3 (26 7) routing lc_trk_g1_2 input0_3 (26 7) routing lc_trk_g1_6 input0_3 (26 7) routing lc_trk_g2_3 input0_3 (26 7) routing lc_trk_g2_7 input0_3 (26 7) routing lc_trk_g3_2 input0_3 (26 7) routing lc_trk_g3_6 input0_3 (26 8) routing lc_trk_g0_4 input0_4 (26 8) routing lc_trk_g0_6 input0_4 (26 8) routing lc_trk_g1_5 input0_4 (26 8) routing lc_trk_g1_7 input0_4 (26 8) routing lc_trk_g2_4 input0_4 (26 8) routing lc_trk_g2_6 input0_4 (26 8) routing lc_trk_g3_5 input0_4 (26 8) routing lc_trk_g3_7 input0_4 (26 9) routing lc_trk_g0_2 input0_4 (26 9) routing lc_trk_g0_6 input0_4 (26 9) routing lc_trk_g1_3 input0_4 (26 9) routing lc_trk_g1_7 input0_4 (26 9) routing lc_trk_g2_2 input0_4 (26 9) routing lc_trk_g2_6 input0_4 (26 9) routing lc_trk_g3_3 input0_4 (26 9) routing lc_trk_g3_7 input0_4 (27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (27 1) routing lc_trk_g1_1 input0_0 (27 1) routing lc_trk_g1_3 input0_0 (27 1) routing lc_trk_g1_5 input0_0 (27 1) routing lc_trk_g1_7 input0_0 (27 1) routing lc_trk_g3_1 input0_0 (27 1) routing lc_trk_g3_3 input0_0 (27 1) routing lc_trk_g3_5 input0_0 (27 1) routing lc_trk_g3_7 input0_0 (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 (27 11) routing lc_trk_g1_0 input0_5 (27 11) routing lc_trk_g1_2 input0_5 (27 11) routing lc_trk_g1_4 input0_5 (27 11) routing lc_trk_g1_6 input0_5 (27 11) routing lc_trk_g3_0 input0_5 (27 11) routing lc_trk_g3_2 input0_5 (27 11) routing lc_trk_g3_4 input0_5 (27 11) routing lc_trk_g3_6 input0_5 (27 12) routing lc_trk_g1_0 wire_bram/ram/WDATA_1 (27 12) routing lc_trk_g1_2 wire_bram/ram/WDATA_1 (27 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_1 (27 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_1 (27 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_1 (27 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_1 (27 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_1 (27 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 (27 13) routing lc_trk_g1_1 input0_6 (27 13) routing lc_trk_g1_3 input0_6 (27 13) routing lc_trk_g1_5 input0_6 (27 13) routing lc_trk_g1_7 input0_6 (27 13) routing lc_trk_g3_1 input0_6 (27 13) routing lc_trk_g3_3 input0_6 (27 13) routing lc_trk_g3_5 input0_6 (27 13) routing lc_trk_g3_7 input0_6 (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 (27 15) routing lc_trk_g1_0 input0_7 (27 15) routing lc_trk_g1_2 input0_7 (27 15) routing lc_trk_g1_4 input0_7 (27 15) routing lc_trk_g1_6 input0_7 (27 15) routing lc_trk_g3_0 input0_7 (27 15) routing lc_trk_g3_2 input0_7 (27 15) routing lc_trk_g3_4 input0_7 (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 (27 3) routing lc_trk_g1_0 input0_1 (27 3) routing lc_trk_g1_2 input0_1 (27 3) routing lc_trk_g1_4 input0_1 (27 3) routing lc_trk_g1_6 input0_1 (27 3) routing lc_trk_g3_0 input0_1 (27 3) routing lc_trk_g3_2 input0_1 (27 3) routing lc_trk_g3_4 input0_1 (27 3) routing lc_trk_g3_6 input0_1 (27 4) routing lc_trk_g1_0 wire_bram/ram/WDATA_5 (27 4) routing lc_trk_g1_2 wire_bram/ram/WDATA_5 (27 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_5 (27 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_5 (27 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_5 (27 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 (27 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_5 (27 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 (27 5) routing lc_trk_g1_1 input0_2 (27 5) routing lc_trk_g1_3 input0_2 (27 5) routing lc_trk_g1_5 input0_2 (27 5) routing lc_trk_g1_7 input0_2 (27 5) routing lc_trk_g3_1 input0_2 (27 5) routing lc_trk_g3_3 input0_2 (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 (27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 (27 7) routing lc_trk_g1_0 input0_3 (27 7) routing lc_trk_g1_2 input0_3 (27 7) routing lc_trk_g1_4 input0_3 (27 7) routing lc_trk_g1_6 input0_3 (27 7) routing lc_trk_g3_0 input0_3 (27 7) routing lc_trk_g3_2 input0_3 (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 (27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 (27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 (27 9) routing lc_trk_g1_1 input0_4 (27 9) routing lc_trk_g1_3 input0_4 (27 9) routing lc_trk_g1_5 input0_4 (27 9) routing lc_trk_g1_7 input0_4 (27 9) routing lc_trk_g3_1 input0_4 (27 9) routing lc_trk_g3_3 input0_4 (27 9) routing lc_trk_g3_5 input0_4 (27 9) routing lc_trk_g3_7 input0_4 (28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (28 1) routing lc_trk_g2_0 input0_0 (28 1) routing lc_trk_g2_2 input0_0 (28 1) routing lc_trk_g2_4 input0_0 (28 1) routing lc_trk_g2_6 input0_0 (28 1) routing lc_trk_g3_1 input0_0 (28 1) routing lc_trk_g3_3 input0_0 (28 1) routing lc_trk_g3_5 input0_0 (28 1) routing lc_trk_g3_7 input0_0 (28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_2 (28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_2 (28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_2 (28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 (28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_2 (28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 (28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 (28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 (28 11) routing lc_trk_g2_1 input0_5 (28 11) routing lc_trk_g2_3 input0_5 (28 11) routing lc_trk_g2_5 input0_5 (28 11) routing lc_trk_g2_7 input0_5 (28 11) routing lc_trk_g3_0 input0_5 (28 11) routing lc_trk_g3_2 input0_5 (28 11) routing lc_trk_g3_4 input0_5 (28 11) routing lc_trk_g3_6 input0_5 (28 12) routing lc_trk_g2_1 wire_bram/ram/WDATA_1 (28 12) routing lc_trk_g2_3 wire_bram/ram/WDATA_1 (28 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_1 (28 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_1 (28 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_1 (28 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_1 (28 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_1 (28 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 (28 13) routing lc_trk_g2_0 input0_6 (28 13) routing lc_trk_g2_2 input0_6 (28 13) routing lc_trk_g2_4 input0_6 (28 13) routing lc_trk_g2_6 input0_6 (28 13) routing lc_trk_g3_1 input0_6 (28 13) routing lc_trk_g3_3 input0_6 (28 13) routing lc_trk_g3_5 input0_6 (28 13) routing lc_trk_g3_7 input0_6 (28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_0 (28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_0 (28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_0 (28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 (28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_0 (28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 (28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_0 (28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 (28 15) routing lc_trk_g2_1 input0_7 (28 15) routing lc_trk_g2_3 input0_7 (28 15) routing lc_trk_g2_5 input0_7 (28 15) routing lc_trk_g2_7 input0_7 (28 15) routing lc_trk_g3_0 input0_7 (28 15) routing lc_trk_g3_2 input0_7 (28 15) routing lc_trk_g3_4 input0_7 (28 15) routing lc_trk_g3_6 input0_7 (28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 (28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 (28 3) routing lc_trk_g2_1 input0_1 (28 3) routing lc_trk_g2_3 input0_1 (28 3) routing lc_trk_g2_5 input0_1 (28 3) routing lc_trk_g2_7 input0_1 (28 3) routing lc_trk_g3_0 input0_1 (28 3) routing lc_trk_g3_2 input0_1 (28 3) routing lc_trk_g3_4 input0_1 (28 3) routing lc_trk_g3_6 input0_1 (28 4) routing lc_trk_g2_1 wire_bram/ram/WDATA_5 (28 4) routing lc_trk_g2_3 wire_bram/ram/WDATA_5 (28 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_5 (28 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 (28 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_5 (28 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 (28 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_5 (28 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 (28 5) routing lc_trk_g2_0 input0_2 (28 5) routing lc_trk_g2_2 input0_2 (28 5) routing lc_trk_g2_4 input0_2 (28 5) routing lc_trk_g2_6 input0_2 (28 5) routing lc_trk_g3_1 input0_2 (28 5) routing lc_trk_g3_3 input0_2 (28 5) routing lc_trk_g3_5 input0_2 (28 5) routing lc_trk_g3_7 input0_2 (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 (28 7) routing lc_trk_g2_1 input0_3 (28 7) routing lc_trk_g2_3 input0_3 (28 7) routing lc_trk_g2_5 input0_3 (28 7) routing lc_trk_g2_7 input0_3 (28 7) routing lc_trk_g3_0 input0_3 (28 7) routing lc_trk_g3_2 input0_3 (28 7) routing lc_trk_g3_4 input0_3 (28 7) routing lc_trk_g3_6 input0_3 (28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_3 (28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_3 (28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_3 (28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 (28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_3 (28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 (28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 (28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 (28 9) routing lc_trk_g2_0 input0_4 (28 9) routing lc_trk_g2_2 input0_4 (28 9) routing lc_trk_g2_4 input0_4 (28 9) routing lc_trk_g2_6 input0_4 (28 9) routing lc_trk_g3_1 input0_4 (28 9) routing lc_trk_g3_3 input0_4 (28 9) routing lc_trk_g3_5 input0_4 (28 9) routing lc_trk_g3_7 input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_2 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_1 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_1 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_0 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_6 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_5 (29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_5 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 (29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_4 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_3 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 (29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 (3 0) routing sp12_h_r_0 sp12_v_b_0 (3 0) routing sp12_v_t_23 sp12_v_b_0 (3 1) routing sp12_h_l_23 sp12_v_b_0 (3 1) routing sp12_h_r_0 sp12_v_b_0 (3 10) routing sp12_h_r_1 sp12_h_l_22 (3 10) routing sp12_v_t_22 sp12_h_l_22 (3 11) routing sp12_h_r_1 sp12_h_l_22 (3 11) routing sp12_v_b_1 sp12_h_l_22 (3 12) routing sp12_v_b_1 sp12_h_r_1 (3 12) routing sp12_v_t_22 sp12_h_r_1 (3 13) routing sp12_h_l_22 sp12_h_r_1 (3 13) routing sp12_v_b_1 sp12_h_r_1 (3 14) routing sp12_h_r_1 sp12_v_t_22 (3 14) routing sp12_v_b_1 sp12_v_t_22 (3 15) routing sp12_h_l_22 sp12_v_t_22 (3 15) routing sp12_h_r_1 sp12_v_t_22 (3 2) routing sp12_h_r_0 sp12_h_l_23 (3 2) routing sp12_v_t_23 sp12_h_l_23 (3 3) routing sp12_h_r_0 sp12_h_l_23 (3 3) routing sp12_v_b_0 sp12_h_l_23 (3 4) routing sp12_v_b_0 sp12_h_r_0 (3 4) routing sp12_v_t_23 sp12_h_r_0 (3 5) routing sp12_h_l_23 sp12_h_r_0 (3 5) routing sp12_v_b_0 sp12_h_r_0 (3 6) routing sp12_h_r_0 sp12_v_t_23 (3 6) routing sp12_v_b_0 sp12_v_t_23 (3 7) routing sp12_h_l_23 sp12_v_t_23 (3 7) routing sp12_h_r_0 sp12_v_t_23 (3 8) routing sp12_h_r_1 sp12_v_b_1 (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 (30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 (30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 (30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_1 (30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_1 (30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_1 (30 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_1 (30 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_1 (30 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_1 (30 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_1 (30 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g0_3 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g0_7 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g1_2 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g1_6 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g2_3 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g2_7 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g3_2 wire_bram/ram/WDATA_1 (30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 (30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_0 (30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_0 (30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_0 (30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 (30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_0 (30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 (30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_0 (30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 (30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 (30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 (30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 (30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_5 (30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_5 (30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_5 (30 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_5 (30 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_5 (30 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 (30 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_5 (30 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g0_3 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g0_7 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g1_2 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g1_6 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g2_3 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 (30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 (30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 (31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_2 (31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_0 (31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_0 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_6 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 (33 11) routing lc_trk_g2_1 input2_5 (33 11) routing lc_trk_g2_3 input2_5 (33 11) routing lc_trk_g2_5 input2_5 (33 11) routing lc_trk_g2_7 input2_5 (33 11) routing lc_trk_g3_0 input2_5 (33 11) routing lc_trk_g3_2 input2_5 (33 11) routing lc_trk_g3_4 input2_5 (33 11) routing lc_trk_g3_6 input2_5 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (33 13) routing lc_trk_g2_0 input2_6 (33 13) routing lc_trk_g2_2 input2_6 (33 13) routing lc_trk_g2_4 input2_6 (33 13) routing lc_trk_g2_6 input2_6 (33 13) routing lc_trk_g3_1 input2_6 (33 13) routing lc_trk_g3_3 input2_6 (33 13) routing lc_trk_g3_5 input2_6 (33 13) routing lc_trk_g3_7 input2_6 (33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 (33 15) routing lc_trk_g2_1 input2_7 (33 15) routing lc_trk_g2_3 input2_7 (33 15) routing lc_trk_g2_5 input2_7 (33 15) routing lc_trk_g2_7 input2_7 (33 15) routing lc_trk_g3_0 input2_7 (33 15) routing lc_trk_g3_2 input2_7 (33 15) routing lc_trk_g3_4 input2_7 (33 15) routing lc_trk_g3_6 input2_7 (33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 (34 11) routing lc_trk_g1_0 input2_5 (34 11) routing lc_trk_g1_2 input2_5 (34 11) routing lc_trk_g1_4 input2_5 (34 11) routing lc_trk_g1_6 input2_5 (34 11) routing lc_trk_g3_0 input2_5 (34 11) routing lc_trk_g3_2 input2_5 (34 11) routing lc_trk_g3_4 input2_5 (34 11) routing lc_trk_g3_6 input2_5 (34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 (34 13) routing lc_trk_g1_1 input2_6 (34 13) routing lc_trk_g1_3 input2_6 (34 13) routing lc_trk_g1_5 input2_6 (34 13) routing lc_trk_g1_7 input2_6 (34 13) routing lc_trk_g3_1 input2_6 (34 13) routing lc_trk_g3_3 input2_6 (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 (34 15) routing lc_trk_g1_0 input2_7 (34 15) routing lc_trk_g1_2 input2_7 (34 15) routing lc_trk_g1_4 input2_7 (34 15) routing lc_trk_g1_6 input2_7 (34 15) routing lc_trk_g3_0 input2_7 (34 15) routing lc_trk_g3_2 input2_7 (34 15) routing lc_trk_g3_4 input2_7 (34 15) routing lc_trk_g3_6 input2_7 (34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (35 10) routing lc_trk_g0_5 input2_5 (35 10) routing lc_trk_g0_7 input2_5 (35 10) routing lc_trk_g1_4 input2_5 (35 10) routing lc_trk_g1_6 input2_5 (35 10) routing lc_trk_g2_5 input2_5 (35 10) routing lc_trk_g2_7 input2_5 (35 10) routing lc_trk_g3_4 input2_5 (35 10) routing lc_trk_g3_6 input2_5 (35 11) routing lc_trk_g0_3 input2_5 (35 11) routing lc_trk_g0_7 input2_5 (35 11) routing lc_trk_g1_2 input2_5 (35 11) routing lc_trk_g1_6 input2_5 (35 11) routing lc_trk_g2_3 input2_5 (35 11) routing lc_trk_g2_7 input2_5 (35 11) routing lc_trk_g3_2 input2_5 (35 11) routing lc_trk_g3_6 input2_5 (35 12) routing lc_trk_g0_4 input2_6 (35 12) routing lc_trk_g0_6 input2_6 (35 12) routing lc_trk_g1_5 input2_6 (35 12) routing lc_trk_g1_7 input2_6 (35 12) routing lc_trk_g2_4 input2_6 (35 12) routing lc_trk_g2_6 input2_6 (35 12) routing lc_trk_g3_5 input2_6 (35 12) routing lc_trk_g3_7 input2_6 (35 13) routing lc_trk_g0_2 input2_6 (35 13) routing lc_trk_g0_6 input2_6 (35 13) routing lc_trk_g1_3 input2_6 (35 13) routing lc_trk_g1_7 input2_6 (35 13) routing lc_trk_g2_2 input2_6 (35 13) routing lc_trk_g2_6 input2_6 (35 13) routing lc_trk_g3_3 input2_6 (35 13) routing lc_trk_g3_7 input2_6 (35 14) routing lc_trk_g0_5 input2_7 (35 14) routing lc_trk_g0_7 input2_7 (35 14) routing lc_trk_g1_4 input2_7 (35 14) routing lc_trk_g1_6 input2_7 (35 14) routing lc_trk_g2_5 input2_7 (35 14) routing lc_trk_g2_7 input2_7 (35 14) routing lc_trk_g3_4 input2_7 (35 14) routing lc_trk_g3_6 input2_7 (35 15) routing lc_trk_g0_3 input2_7 (35 15) routing lc_trk_g0_7 input2_7 (35 15) routing lc_trk_g1_2 input2_7 (35 15) routing lc_trk_g1_6 input2_7 (35 15) routing lc_trk_g2_3 input2_7 (35 15) routing lc_trk_g2_7 input2_7 (35 15) routing lc_trk_g3_2 input2_7 (35 15) routing lc_trk_g3_6 input2_7 (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21 (36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0 (36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42 (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 (36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 (36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 (36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 (36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29 (36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 (37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_2 sp4_h_l_15 (37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_1 sp12_h_l_3 (37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_1 sp4_h_l_17 (37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_0 sp12_h_l_5 (37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_0 sp4_h_r_30 (37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_6 sp12_h_r_10 (37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_6 sp4_h_l_7 (37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_5 sp12_h_r_12 (37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_5 sp4_h_r_20 (37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_4 sp12_h_l_13 (37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_4 sp4_h_r_22 (37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_3 sp12_h_r_0 (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21 (38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0 (38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26 (38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20 (38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_0 sp4_v_b_30 (38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_0 sp12_h_l_21 (38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_6 sp4_v_t_23 (38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_6 sp4_v_b_2 (38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_5 sp4_v_t_25 (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_5 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_4 sp4_v_b_38 (38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_4 sp4_v_b_6 (38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_3 sp4_v_t_13 (38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_3 sp12_h_r_16 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_7 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_7 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_2 sp4_v_t_31 (39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_2 sp4_v_b_10 (39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_1 sp4_v_t_33 (39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_1 sp4_v_t_1 (39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_0 sp4_v_b_46 (39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_0 sp4_v_b_14 (39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_6 sp12_v_b_2 (39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_6 sp4_v_t_7 (39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_5 sp12_v_t_3 (39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_5 sp4_v_b_20 (39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_4 sp12_v_b_6 (39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_4 sp4_v_b_22 (39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_3 sp4_v_b_40 (39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_3 sp4_v_b_8 (4 0) routing sp4_h_l_37 sp4_v_b_0 (4 0) routing sp4_h_l_43 sp4_v_b_0 (4 0) routing sp4_v_t_37 sp4_v_b_0 (4 0) routing sp4_v_t_41 sp4_v_b_0 (4 1) routing sp4_h_l_41 sp4_h_r_0 (4 1) routing sp4_h_l_44 sp4_h_r_0 (4 1) routing sp4_v_b_6 sp4_h_r_0 (4 1) routing sp4_v_t_42 sp4_h_r_0 (4 10) routing sp4_h_r_0 sp4_v_t_43 (4 10) routing sp4_h_r_6 sp4_v_t_43 (4 10) routing sp4_v_b_10 sp4_v_t_43 (4 10) routing sp4_v_b_6 sp4_v_t_43 (4 11) routing sp4_h_r_10 sp4_h_l_43 (4 11) routing sp4_h_r_3 sp4_h_l_43 (4 11) routing sp4_v_b_1 sp4_h_l_43 (4 11) routing sp4_v_t_37 sp4_h_l_43 (4 12) routing sp4_h_l_38 sp4_v_b_9 (4 12) routing sp4_h_l_44 sp4_v_b_9 (4 12) routing sp4_v_t_36 sp4_v_b_9 (4 12) routing sp4_v_t_44 sp4_v_b_9 (4 13) routing sp4_h_l_36 sp4_h_r_9 (4 13) routing sp4_h_l_43 sp4_h_r_9 (4 13) routing sp4_v_b_3 sp4_h_r_9 (4 13) routing sp4_v_t_41 sp4_h_r_9 (4 14) routing sp4_h_r_3 sp4_v_t_44 (4 14) routing sp4_h_r_9 sp4_v_t_44 (4 14) routing sp4_v_b_1 sp4_v_t_44 (4 14) routing sp4_v_b_9 sp4_v_t_44 (4 15) routing sp4_h_r_1 sp4_h_l_44 (4 15) routing sp4_h_r_6 sp4_h_l_44 (4 15) routing sp4_v_b_4 sp4_h_l_44 (4 15) routing sp4_v_t_38 sp4_h_l_44 (4 2) routing sp4_h_r_0 sp4_v_t_37 (4 2) routing sp4_h_r_6 sp4_v_t_37 (4 2) routing sp4_v_b_0 sp4_v_t_37 (4 2) routing sp4_v_b_4 sp4_v_t_37 (4 3) routing sp4_h_r_4 sp4_h_l_37 (4 3) routing sp4_h_r_9 sp4_h_l_37 (4 3) routing sp4_v_b_7 sp4_h_l_37 (4 3) routing sp4_v_t_43 sp4_h_l_37 (4 4) routing sp4_h_l_38 sp4_v_b_3 (4 4) routing sp4_h_l_44 sp4_v_b_3 (4 4) routing sp4_v_t_38 sp4_v_b_3 (4 4) routing sp4_v_t_42 sp4_v_b_3 (4 5) routing sp4_h_l_37 sp4_h_r_3 (4 5) routing sp4_h_l_42 sp4_h_r_3 (4 5) routing sp4_v_b_9 sp4_h_r_3 (4 5) routing sp4_v_t_47 sp4_h_r_3 (4 6) routing sp4_h_r_3 sp4_v_t_38 (4 6) routing sp4_h_r_9 sp4_v_t_38 (4 6) routing sp4_v_b_3 sp4_v_t_38 (4 6) routing sp4_v_b_7 sp4_v_t_38 (4 7) routing sp4_h_r_0 sp4_h_l_38 (4 7) routing sp4_h_r_7 sp4_h_l_38 (4 7) routing sp4_v_b_10 sp4_h_l_38 (4 7) routing sp4_v_t_44 sp4_h_l_38 (4 8) routing sp4_h_l_37 sp4_v_b_6 (4 8) routing sp4_h_l_43 sp4_v_b_6 (4 8) routing sp4_v_t_43 sp4_v_b_6 (4 8) routing sp4_v_t_47 sp4_v_b_6 (4 9) routing sp4_h_l_38 sp4_h_r_6 (4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9 (40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12 (40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19 (40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_23 (40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_4 sp12_v_t_21 (40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33 (41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1 (41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45 (41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_13 (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_35 (41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_39 (41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_7 (41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_41 (41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_9 (5 0) routing sp4_h_l_44 sp4_h_r_0 (5 0) routing sp4_v_b_0 sp4_h_r_0 (5 0) routing sp4_v_b_6 sp4_h_r_0 (5 0) routing sp4_v_t_37 sp4_h_r_0 (5 1) routing sp4_h_l_37 sp4_v_b_0 (5 1) routing sp4_h_l_43 sp4_v_b_0 (5 1) routing sp4_h_r_0 sp4_v_b_0 (5 1) routing sp4_v_t_44 sp4_v_b_0 (5 10) routing sp4_h_r_3 sp4_h_l_43 (5 10) routing sp4_v_b_6 sp4_h_l_43 (5 10) routing sp4_v_t_37 sp4_h_l_43 (5 10) routing sp4_v_t_43 sp4_h_l_43 (5 11) routing sp4_h_l_43 sp4_v_t_43 (5 11) routing sp4_h_r_0 sp4_v_t_43 (5 11) routing sp4_h_r_6 sp4_v_t_43 (5 11) routing sp4_v_b_3 sp4_v_t_43 (5 12) routing sp4_h_l_43 sp4_h_r_9 (5 12) routing sp4_v_b_3 sp4_h_r_9 (5 12) routing sp4_v_b_9 sp4_h_r_9 (5 12) routing sp4_v_t_44 sp4_h_r_9 (5 13) routing sp4_h_l_38 sp4_v_b_9 (5 13) routing sp4_h_l_44 sp4_v_b_9 (5 13) routing sp4_h_r_9 sp4_v_b_9 (5 13) routing sp4_v_t_43 sp4_v_b_9 (5 14) routing sp4_h_r_6 sp4_h_l_44 (5 14) routing sp4_v_b_9 sp4_h_l_44 (5 14) routing sp4_v_t_38 sp4_h_l_44 (5 14) routing sp4_v_t_44 sp4_h_l_44 (5 15) routing sp4_h_l_44 sp4_v_t_44 (5 15) routing sp4_h_r_3 sp4_v_t_44 (5 15) routing sp4_h_r_9 sp4_v_t_44 (5 15) routing sp4_v_b_6 sp4_v_t_44 (5 2) routing sp4_h_r_9 sp4_h_l_37 (5 2) routing sp4_v_b_0 sp4_h_l_37 (5 2) routing sp4_v_t_37 sp4_h_l_37 (5 2) routing sp4_v_t_43 sp4_h_l_37 (5 3) routing sp4_h_l_37 sp4_v_t_37 (5 3) routing sp4_h_r_0 sp4_v_t_37 (5 3) routing sp4_h_r_6 sp4_v_t_37 (5 3) routing sp4_v_b_9 sp4_v_t_37 (5 4) routing sp4_h_l_37 sp4_h_r_3 (5 4) routing sp4_v_b_3 sp4_h_r_3 (5 4) routing sp4_v_b_9 sp4_h_r_3 (5 4) routing sp4_v_t_38 sp4_h_r_3 (5 5) routing sp4_h_l_38 sp4_v_b_3 (5 5) routing sp4_h_l_44 sp4_v_b_3 (5 5) routing sp4_h_r_3 sp4_v_b_3 (5 5) routing sp4_v_t_37 sp4_v_b_3 (5 6) routing sp4_h_r_0 sp4_h_l_38 (5 6) routing sp4_v_b_3 sp4_h_l_38 (5 6) routing sp4_v_t_38 sp4_h_l_38 (5 6) routing sp4_v_t_44 sp4_h_l_38 (5 7) routing sp4_h_l_38 sp4_v_t_38 (5 7) routing sp4_h_r_3 sp4_v_t_38 (5 7) routing sp4_h_r_9 sp4_v_t_38 (5 7) routing sp4_v_b_0 sp4_v_t_38 (5 8) routing sp4_h_l_38 sp4_h_r_6 (5 8) routing sp4_v_b_0 sp4_h_r_6 (5 8) routing sp4_v_b_6 sp4_h_r_6 (5 8) routing sp4_v_t_43 sp4_h_r_6 (5 9) routing sp4_h_l_37 sp4_v_b_6 (5 9) routing sp4_h_l_43 sp4_v_b_6 (5 9) routing sp4_h_r_6 sp4_v_b_6 (5 9) routing sp4_v_t_38 sp4_v_b_6 (6 0) routing sp4_h_l_43 sp4_v_b_0 (6 0) routing sp4_h_r_7 sp4_v_b_0 (6 0) routing sp4_v_t_41 sp4_v_b_0 (6 0) routing sp4_v_t_44 sp4_v_b_0 (6 1) routing sp4_h_l_37 sp4_h_r_0 (6 1) routing sp4_h_l_41 sp4_h_r_0 (6 1) routing sp4_v_b_0 sp4_h_r_0 (6 1) routing sp4_v_b_6 sp4_h_r_0 (6 10) routing sp4_h_l_36 sp4_v_t_43 (6 10) routing sp4_h_r_0 sp4_v_t_43 (6 10) routing sp4_v_b_10 sp4_v_t_43 (6 10) routing sp4_v_b_3 sp4_v_t_43 (6 11) routing sp4_h_r_10 sp4_h_l_43 (6 11) routing sp4_h_r_6 sp4_h_l_43 (6 11) routing sp4_v_t_37 sp4_h_l_43 (6 11) routing sp4_v_t_43 sp4_h_l_43 (6 12) routing sp4_h_l_38 sp4_v_b_9 (6 12) routing sp4_h_r_4 sp4_v_b_9 (6 12) routing sp4_v_t_36 sp4_v_b_9 (6 12) routing sp4_v_t_43 sp4_v_b_9 (6 13) routing sp4_h_l_36 sp4_h_r_9 (6 13) routing sp4_h_l_44 sp4_h_r_9 (6 13) routing sp4_v_b_3 sp4_h_r_9 (6 13) routing sp4_v_b_9 sp4_h_r_9 (6 14) routing sp4_h_l_41 sp4_v_t_44 (6 14) routing sp4_h_r_3 sp4_v_t_44 (6 14) routing sp4_v_b_1 sp4_v_t_44 (6 14) routing sp4_v_b_6 sp4_v_t_44 (6 15) routing sp4_h_r_1 sp4_h_l_44 (6 15) routing sp4_h_r_9 sp4_h_l_44 (6 15) routing sp4_v_t_38 sp4_h_l_44 (6 15) routing sp4_v_t_44 sp4_h_l_44 (6 2) routing sp4_h_l_42 sp4_v_t_37 (6 2) routing sp4_h_r_6 sp4_v_t_37 (6 2) routing sp4_v_b_4 sp4_v_t_37 (6 2) routing sp4_v_b_9 sp4_v_t_37 (6 3) routing sp4_h_r_0 sp4_h_l_37 (6 3) routing sp4_h_r_4 sp4_h_l_37 (6 3) routing sp4_v_t_37 sp4_h_l_37 (6 3) routing sp4_v_t_43 sp4_h_l_37 (6 4) routing sp4_h_l_44 sp4_v_b_3 (6 4) routing sp4_h_r_10 sp4_v_b_3 (6 4) routing sp4_v_t_37 sp4_v_b_3 (6 4) routing sp4_v_t_42 sp4_v_b_3 (6 5) routing sp4_h_l_38 sp4_h_r_3 (6 5) routing sp4_h_l_42 sp4_h_r_3 (6 5) routing sp4_v_b_3 sp4_h_r_3 (6 5) routing sp4_v_b_9 sp4_h_r_3 (6 6) routing sp4_h_l_47 sp4_v_t_38 (6 6) routing sp4_h_r_9 sp4_v_t_38 (6 6) routing sp4_v_b_0 sp4_v_t_38 (6 6) routing sp4_v_b_7 sp4_v_t_38 (6 7) routing sp4_h_r_3 sp4_h_l_38 (6 7) routing sp4_h_r_7 sp4_h_l_38 (6 7) routing sp4_v_t_38 sp4_h_l_38 (6 7) routing sp4_v_t_44 sp4_h_l_38 (6 8) routing sp4_h_l_37 sp4_v_b_6 (6 8) routing sp4_h_r_1 sp4_v_b_6 (6 8) routing sp4_v_t_38 sp4_v_b_6 (6 8) routing sp4_v_t_47 sp4_v_b_6 (6 9) routing sp4_h_l_43 sp4_h_r_6 (6 9) routing sp4_h_l_47 sp4_h_r_6 (6 9) routing sp4_v_b_0 sp4_h_r_6 (6 9) routing sp4_v_b_6 sp4_h_r_6 (7 0) Ram config bit: MEMT_bram_cbit_1 (7 1) Ram config bit: MEMT_bram_cbit_0 (7 10) Column buffer control bit: MEMT_colbuf_cntl_3 (7 11) Column buffer control bit: MEMT_colbuf_cntl_2 (7 12) Column buffer control bit: MEMT_colbuf_cntl_5 (7 13) Column buffer control bit: MEMT_colbuf_cntl_4 (7 14) Column buffer control bit: MEMT_colbuf_cntl_7 (7 15) Column buffer control bit: MEMT_colbuf_cntl_6 (7 2) Ram config bit: MEMT_bram_cbit_3 (7 3) Ram config bit: MEMT_bram_cbit_2 (7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 (7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC03_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 (7 6) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_7 (7 6) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_7 (7 7) Cascade bit: MEMT_LC00_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC01_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC02_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC03_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC04_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC05_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC06_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC06_inmux02_bram_cbit_6 (7 7) Cascade bit: MEMT_LC07_inmux00_bram_cbit_6 (7 7) Cascade bit: MEMT_LC07_inmux02_bram_cbit_6 (7 8) Column buffer control bit: MEMT_colbuf_cntl_1 (7 9) Column buffer control bit: MEMT_colbuf_cntl_0 (8 0) routing sp4_h_l_36 sp4_h_r_1 (8 0) routing sp4_h_l_40 sp4_h_r_1 (8 0) routing sp4_v_b_1 sp4_h_r_1 (8 0) routing sp4_v_b_7 sp4_h_r_1 (8 1) routing sp4_h_l_36 sp4_v_b_1 (8 1) routing sp4_h_l_42 sp4_v_b_1 (8 1) routing sp4_h_r_1 sp4_v_b_1 (8 1) routing sp4_v_t_47 sp4_v_b_1 (8 10) routing sp4_h_r_11 sp4_h_l_42 (8 10) routing sp4_h_r_7 sp4_h_l_42 (8 10) routing sp4_v_t_36 sp4_h_l_42 (8 10) routing sp4_v_t_42 sp4_h_l_42 (8 11) routing sp4_h_l_42 sp4_v_t_42 (8 11) routing sp4_h_r_1 sp4_v_t_42 (8 11) routing sp4_h_r_7 sp4_v_t_42 (8 11) routing sp4_v_b_4 sp4_v_t_42 (8 12) routing sp4_h_l_39 sp4_h_r_10 (8 12) routing sp4_h_l_47 sp4_h_r_10 (8 12) routing sp4_v_b_10 sp4_h_r_10 (8 12) routing sp4_v_b_4 sp4_h_r_10 (8 13) routing sp4_h_l_41 sp4_v_b_10 (8 13) routing sp4_h_l_47 sp4_v_b_10 (8 13) routing sp4_h_r_10 sp4_v_b_10 (8 13) routing sp4_v_t_42 sp4_v_b_10 (8 14) routing sp4_h_r_10 sp4_h_l_47 (8 14) routing sp4_h_r_2 sp4_h_l_47 (8 14) routing sp4_v_t_41 sp4_h_l_47 (8 14) routing sp4_v_t_47 sp4_h_l_47 (8 15) routing sp4_h_l_47 sp4_v_t_47 (8 15) routing sp4_h_r_10 sp4_v_t_47 (8 15) routing sp4_h_r_4 sp4_v_t_47 (8 15) routing sp4_v_b_7 sp4_v_t_47 (8 2) routing sp4_h_r_1 sp4_h_l_36 (8 2) routing sp4_h_r_5 sp4_h_l_36 (8 2) routing sp4_v_t_36 sp4_h_l_36 (8 2) routing sp4_v_t_42 sp4_h_l_36 (8 3) routing sp4_h_l_36 sp4_v_t_36 (8 3) routing sp4_h_r_1 sp4_v_t_36 (8 3) routing sp4_h_r_7 sp4_v_t_36 (8 3) routing sp4_v_b_10 sp4_v_t_36 (8 4) routing sp4_h_l_41 sp4_h_r_4 (8 4) routing sp4_h_l_45 sp4_h_r_4 (8 4) routing sp4_v_b_10 sp4_h_r_4 (8 4) routing sp4_v_b_4 sp4_h_r_4 (8 5) routing sp4_h_l_41 sp4_v_b_4 (8 5) routing sp4_h_l_47 sp4_v_b_4 (8 5) routing sp4_h_r_4 sp4_v_b_4 (8 5) routing sp4_v_t_36 sp4_v_b_4 (8 6) routing sp4_h_r_4 sp4_h_l_41 (8 6) routing sp4_h_r_8 sp4_h_l_41 (8 6) routing sp4_v_t_41 sp4_h_l_41 (8 6) routing sp4_v_t_47 sp4_h_l_41 (8 7) routing sp4_h_l_41 sp4_v_t_41 (8 7) routing sp4_h_r_10 sp4_v_t_41 (8 7) routing sp4_h_r_4 sp4_v_t_41 (8 7) routing sp4_v_b_1 sp4_v_t_41 (8 8) routing sp4_h_l_42 sp4_h_r_7 (8 8) routing sp4_h_l_46 sp4_h_r_7 (8 8) routing sp4_v_b_1 sp4_h_r_7 (8 8) routing sp4_v_b_7 sp4_h_r_7 (8 9) routing sp4_h_l_36 sp4_v_b_7 (8 9) routing sp4_h_l_42 sp4_v_b_7 (8 9) routing sp4_h_r_7 sp4_v_b_7 (8 9) routing sp4_v_t_41 sp4_v_b_7 (9 0) routing sp4_h_l_47 sp4_h_r_1 (9 0) routing sp4_v_b_1 sp4_h_r_1 (9 0) routing sp4_v_b_7 sp4_h_r_1 (9 0) routing sp4_v_t_36 sp4_h_r_1 (9 1) routing sp4_h_l_36 sp4_v_b_1 (9 1) routing sp4_h_l_42 sp4_v_b_1 (9 1) routing sp4_v_t_36 sp4_v_b_1 (9 1) routing sp4_v_t_40 sp4_v_b_1 (9 10) routing sp4_h_r_4 sp4_h_l_42 (9 10) routing sp4_v_b_7 sp4_h_l_42 (9 10) routing sp4_v_t_36 sp4_h_l_42 (9 10) routing sp4_v_t_42 sp4_h_l_42 (9 11) routing sp4_h_r_1 sp4_v_t_42 (9 11) routing sp4_h_r_7 sp4_v_t_42 (9 11) routing sp4_v_b_11 sp4_v_t_42 (9 11) routing sp4_v_b_7 sp4_v_t_42 (9 12) routing sp4_h_l_42 sp4_h_r_10 (9 12) routing sp4_v_b_10 sp4_h_r_10 (9 12) routing sp4_v_b_4 sp4_h_r_10 (9 12) routing sp4_v_t_47 sp4_h_r_10 (9 13) routing sp4_h_l_41 sp4_v_b_10 (9 13) routing sp4_h_l_47 sp4_v_b_10 (9 13) routing sp4_v_t_39 sp4_v_b_10 (9 13) routing sp4_v_t_47 sp4_v_b_10 (9 14) routing sp4_h_r_7 sp4_h_l_47 (9 14) routing sp4_v_b_10 sp4_h_l_47 (9 14) routing sp4_v_t_41 sp4_h_l_47 (9 14) routing sp4_v_t_47 sp4_h_l_47 (9 15) routing sp4_h_r_10 sp4_v_t_47 (9 15) routing sp4_h_r_4 sp4_v_t_47 (9 15) routing sp4_v_b_10 sp4_v_t_47 (9 15) routing sp4_v_b_2 sp4_v_t_47 (9 2) routing sp4_h_r_10 sp4_h_l_36 (9 2) routing sp4_v_b_1 sp4_h_l_36 (9 2) routing sp4_v_t_36 sp4_h_l_36 (9 2) routing sp4_v_t_42 sp4_h_l_36 (9 3) routing sp4_h_r_1 sp4_v_t_36 (9 3) routing sp4_h_r_7 sp4_v_t_36 (9 3) routing sp4_v_b_1 sp4_v_t_36 (9 3) routing sp4_v_b_5 sp4_v_t_36 (9 4) routing sp4_h_l_36 sp4_h_r_4 (9 4) routing sp4_v_b_10 sp4_h_r_4 (9 4) routing sp4_v_b_4 sp4_h_r_4 (9 4) routing sp4_v_t_41 sp4_h_r_4 (9 5) routing sp4_h_l_41 sp4_v_b_4 (9 5) routing sp4_h_l_47 sp4_v_b_4 (9 5) routing sp4_v_t_41 sp4_v_b_4 (9 5) routing sp4_v_t_45 sp4_v_b_4 (9 6) routing sp4_h_r_1 sp4_h_l_41 (9 6) routing sp4_v_b_4 sp4_h_l_41 (9 6) routing sp4_v_t_41 sp4_h_l_41 (9 6) routing sp4_v_t_47 sp4_h_l_41 (9 7) routing sp4_h_r_10 sp4_v_t_41 (9 7) routing sp4_h_r_4 sp4_v_t_41 (9 7) routing sp4_v_b_4 sp4_v_t_41 (9 7) routing sp4_v_b_8 sp4_v_t_41 (9 8) routing sp4_h_l_41 sp4_h_r_7 (9 8) routing sp4_v_b_1 sp4_h_r_7 (9 8) routing sp4_v_b_7 sp4_h_r_7 (9 8) routing sp4_v_t_42 sp4_h_r_7 (9 9) routing sp4_h_l_36 sp4_v_b_7 (9 9) routing sp4_h_l_42 sp4_v_b_7 (9 9) routing sp4_v_t_42 sp4_v_b_7 (9 9) routing sp4_v_t_46 sp4_v_b_7 fpga-icestorm-0~20160913git266e758/icefuzz/check.sh000066400000000000000000000017421276746530600214660ustar00rootroot00000000000000#!/bin/bash set -ex for id; do id=${id%.bin} icebox_vlog_opts="-Sa" if test -f $id.pcf; then icebox_vlog_opts="$icebox_vlog_opts -p $id.pcf"; fi if test -f $id.psb; then icebox_vlog_opts="$icebox_vlog_opts -P $id.psb"; fi ../icepack/iceunpack $id.bin $id.asc ../icebox/icebox_vlog.py $icebox_vlog_opts $id.asc > $id.ve yosys -p " read_verilog $id.v read_verilog $id.ve read_verilog -lib +/ice40/cells_sim.v rename top gold rename chip gate proc splitnets -ports clean -purge ## Variant 1 ## # miter -equiv -flatten gold gate equiv # tee -q synth -top equiv # sat -verify -prove trigger 0 -show-ports equiv ## Variant 2 ## # miter -equiv -flatten -ignore_gold_x -make_outcmp -make_outputs gold gate equiv # hierarchy -top equiv # sat -max_undef -prove trigger 0 -show-ports equiv ## Variant 3 ## equiv_make gold gate equiv hierarchy -top equiv opt -share_all equiv_simple equiv_induct equiv_status -assert " touch $id.ok done fpga-icestorm-0~20160913git266e758/icefuzz/database.py000066400000000000000000000141251276746530600221720ustar00rootroot00000000000000#!/usr/bin/env python3 import re, sys, os def sort_bits_key(a): if a[0] == "!": a = a[1:] return re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a) def read_database(filename, tile_type): raw_db = list() route_to_buffer = set() add_mux_bits = dict() with open(filename, "r") as f: for line in f: line = line.strip() m = re.match(r"\s*\((\d+)\s+(\d+)\)\s+(.*)", line) assert m bit = "B%d[%d]" % (int(m.group(2)), int(m.group(1))) line = m.group(3) line = re.sub(r"^Enable bit of Mux", "MuxEn", line) line = re.sub(r"^IO control bit:", "IoCtrl", line) line = re.sub(r"^Column buffer control bit:", "ColBufCtrl", line) line = re.sub(r"^Negative Clock bit", "NegClk", line) line = re.sub(r"^Cascade (buffer Enable )?bit:", "Cascade", line) line = re.sub(r"^Ram config bit:", "RamConfig", line) line = re.sub(r"^PLL config bit:", "PLL", line) line = re.sub(r"^Icegate Enable bit:", "Icegate", line) line = line.split() if line[0] == "routing": if line[3] == "wire_gbuf/in": line[3] = "fabout" raw_db.append((bit, (line[0], line[1], line[3]))) elif line[0] == "IoCtrl": raw_db.append((bit, (line[0], re.sub(r"^.*?_", "", line[1]).replace("_en", "")))) elif line[0] in ("IOB_0", "IOB_1"): if line[1] != "IO": raw_db.append((bit, (line[0], line[1]))) elif line[0] == "PLL": line[1] = re.sub(r"CLOCK_T_\d+_\d+_IO(LEFT|RIGHT|UP|DOWN)_", "pll_", line[1]) line[1] = re.sub(r"pll_cf_bit_", "PLLCONFIG_", line[1]) raw_db.append((bit, (line[0], line[1]))) elif line[0] == "ColBufCtrl": line[1] = re.sub(r"B?IO(LEFT|RIGHT)_", "IO_", line[1]) line[1] = re.sub(r"IO_half_column_clock_enable_", "glb_netwk_", line[1]) line[1] = re.sub(r"(LH|MEM[BT])_colbuf_cntl_", "glb_netwk_", line[1]) if m.group(1) == "7": line[1] = re.sub(r"glb_netwk_", "8k_glb_netwk_", line[1]) elif m.group(1) in ["1", "2"]: line[1] = re.sub(r"glb_netwk_", "1k_glb_netwk_", line[1]) raw_db.append((bit, (line[0], line[1]))) elif line[0] == "Cascade": match = re.match("LH_LC0(\d)_inmux02_5", line[1]) if match: raw_db.append((bit, ("buffer", "wire_logic_cluster/lc_%d/lout" % (int(match.group(1))-1), "input_2_%s" % match.group(1)))) else: match = re.match("MEMT_LC\d+_inmux\d+_bram_cbit_(\d+)", line[1]) if match: raw_db.append((bit, ("RamCascade", "CBIT_%d" % int(match.group(1))))) else: raw_db.append((bit, (line[0], line[1]))) elif line[0] == "RamConfig": if line[1] == "MEMB_Power_Up_Control": line[1] = "PowerUp" line[1] = re.sub(r"MEMT_bram_cbit_", "CBIT_", line[1]) raw_db.append((bit, (line[0], line[1]))) elif line[0] == "MuxEn": if line[4] == "wire_gbuf/in": line[4] = "fabout" if line[3].startswith("logic_op_"): for prefix in ["IO_L.", "IO_R.", "IO_T.", "IO_B."]: route_to_buffer.add((prefix + line[3], line[4])) add_mux_bits.setdefault(prefix + line[3], set()).add((bit, ("buffer", prefix + line[3], line[4]))) else: raw_db.append((bit, ("buffer", line[3], line[4]))) route_to_buffer.add((line[3], line[4])) elif line[0] == "NegClk" or line[0] == "Icegate" or re.match(r"LC_\d+", line[0]): raw_db.append((bit, (line[0],))) elif line[0] == "Carry_In_Mux": continue else: print("unsupported statement: %s: %s" % (bit, line)) assert False for i in range(len(raw_db)): if raw_db[i][1][0] == "routing" and (raw_db[i][1][1], raw_db[i][1][2]) in route_to_buffer: if raw_db[i][1][1] in add_mux_bits: for entry in add_mux_bits[raw_db[i][1][1]]: raw_db.append(entry) raw_db[i] = (raw_db[i][0], ("buffer", raw_db[i][1][1], raw_db[i][1][2])) func_to_bits = dict() for entry in raw_db: func_to_bits.setdefault(entry[1], set()).add(entry[0]) bit_groups = dict() for func, bits in list(func_to_bits.items()): for bit in bits: bit_groups[bit] = bit_groups.setdefault(bit, set()).union(bits) for func in func_to_bits: new_bits = set() for bit2 in func_to_bits[func]: for bit in bit_groups[bit2]: if bit in func_to_bits[func]: new_bits.add(bit) else: new_bits.add("!" + bit) func_to_bits[func] = new_bits database = list() for func in sorted(func_to_bits): bits = func_to_bits[func] entry = (",".join(sorted(bits, key=sort_bits_key)),) + func database.append(entry) return database with open("database_io.txt", "w") as f: for entry in read_database("bitdata_io.txt", "io"): print("\t".join(entry), file=f) with open("database_logic.txt", "w") as f: for entry in read_database("bitdata_logic.txt", "logic"): print("\t".join(entry), file=f) with open("database_ramb.txt", "w") as f: for entry in read_database("bitdata_ramb.txt", "ramb"): print("\t".join(entry), file=f) with open("database_ramt.txt", "w") as f: for entry in read_database("bitdata_ramt.txt", "ramt"): print("\t".join(entry), file=f) with open("database_ramb_8k.txt", "w") as f: for entry in read_database("bitdata_ramb_8k.txt", "ramb_8k"): print("\t".join(entry), file=f) with open("database_ramt_8k.txt", "w") as f: for entry in read_database("bitdata_ramt_8k.txt", "ramt_8k"): print("\t".join(entry), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/export.py000066400000000000000000000005761276746530600217540ustar00rootroot00000000000000#!/usr/bin/env python3 with open("../icebox/iceboxdb.py", "w") as f: for i in [ "database_io", "database_logic", "database_ramb", "database_ramt", "database_ramb_8k", "database_ramt_8k" ]: print('%s_txt = """' % i, file=f) with open("%s.txt" % i, "r") as fi: for line in fi: print(line, end="", file=f) print('"""', file=f) fpga-icestorm-0~20160913git266e758/icefuzz/extract.py000066400000000000000000000036261276746530600221040ustar00rootroot00000000000000#!/usr/bin/env python3 import sys, re db = set() text_db = dict() mode_8k = False cur_text_db = None max_x, max_y = 0, 0 if sys.argv[1] == '-8': sys.argv = sys.argv[1:] mode_8k = True for filename in sys.argv[1:]: with open(filename, "r") as f: for line in f: if line == "\n": pass elif line.startswith("GlobalNetwork"): cur_text_db = set() elif line.startswith("IO"): match = re.match("IO_Tile_(\d+)_(\d+)", line) assert match max_x = max(max_x, int(match.group(1))) max_y = max(max_y, int(match.group(2))) cur_text_db = text_db.setdefault("io", set()) elif line.startswith("Logic"): cur_text_db = text_db.setdefault("logic", set()) elif line.startswith("RAM"): match = re.match(r"RAM_Tile_\d+_(\d+)", line) if int(match.group(1)) % 2 == 1: cur_text_db = text_db.setdefault("ramb_8k" if mode_8k else "ramb", set()) else: cur_text_db = text_db.setdefault("ramt_8k" if mode_8k else "ramt", set()) else: assert line.startswith(" ") cur_text_db.add(line) def logic_op_prefix(match): x = int(match.group(1)) y = int(match.group(2)) if x == 0: return " IO_L.logic_op_" if y == 0: return " IO_B.logic_op_" if x == max_x: return " IO_R.logic_op_" if y == max_y: return " IO_T.logic_op_" assert False for tile_type in text_db: for line in text_db[tile_type]: line = re.sub(" T_(\d+)_(\d+)\.logic_op_", logic_op_prefix, line) line = re.sub(" T_\d+_\d+\.", " ", line) m = re.match(" *(\([\d ]+\)) +\([\d ]+\) +\([\d ]+\) +(.*\S)", line) if m: db.add("%s %s %s" % (tile_type, m.group(1), m.group(2))) for line in sorted(db): print(line) fpga-icestorm-0~20160913git266e758/icefuzz/fuzzconfig.py000066400000000000000000000032421276746530600226100ustar00rootroot00000000000000import os num = 20 if os.getenv('ICE8KPINS'): num_ramb40 = 32 pins=""" A1 A2 A5 A6 A7 A9 A10 A11 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 D16 E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 E16 F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 H16 J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 J15 J16 K1 K3 K4 K5 K9 K11 K12 K13 K14 K15 K16 L1 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 L14 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M14 M15 M16 N2 N3 N4 N5 N6 N7 N9 N10 N12 N16 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 R16 T1 T2 T3 T5 T6 T7 T8 T9 T10 T11 T13 T14 T15 T16 """.split() gpins = "C8 F7 G1 H11 H16 I3 K9 R9".split() else: num_ramb40 = 16 pins = """ 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34 37 38 41 42 43 44 45 47 48 52 56 58 60 61 62 63 64 73 74 75 76 78 79 80 81 87 88 90 91 95 96 97 98 101 102 104 105 106 107 112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144 """.split() gpins = "20 21 49 50 93 94 128 129".split() fpga-icestorm-0~20160913git266e758/icefuzz/glbcheck.py000066400000000000000000000033271276746530600221720ustar00rootroot00000000000000#!/usr/bin/env python3 from sys import argv, exit asc_bits = set() glb_bits = set() # parsing .asc file with open(argv[1]) as f: current_tile = None current_line = None for line in f: if line.startswith("."): if line.find("_tile ") >= 0: f = line.split() current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) current_line = 0 else: current_tile = None current_line = None continue if current_tile is not None: for i in range(len(line)): if line[i] == '1': asc_bits.add("%s.%02d.%02d" % (current_tile, current_line, i)) current_line += 1 # parsing .glb file with open(argv[2]) as f: current_tile = None for line in f: if line.find("Tile_") >= 0: f = line.replace("IO_", "").replace("RAM_", "").split("_") assert len(f) == 3 current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) continue if line.find("GlobalNetwork") >= 0: current_tile = None continue if current_tile is not None: f = line.replace("(", "").replace(")", "").split() if len(f) >= 2: glb_bits.add("%s.%02d.%02d" % (current_tile, int(f[1]), int(f[0]))) # compare and report if asc_bits == glb_bits: print("ASC and GLB files match.") exit(0) only_in_asc = asc_bits - glb_bits only_in_glb = glb_bits - asc_bits assert len(only_in_asc) != 0 or len(only_in_glb) != 0 if len(only_in_asc) != 0: print("Only in ASC: %s" % sorted(only_in_asc)) if len(only_in_glb) != 0: print("Only in GLB: %s" % sorted(only_in_glb)) exit(1) fpga-icestorm-0~20160913git266e758/icefuzz/glbmapbits.py000066400000000000000000000014631276746530600225530ustar00rootroot00000000000000#!/usr/bin/env python3 import re import fileinput tiletype = "" x, y = 0, 0 for line in fileinput.input(): if line.startswith("LogicTile"): fields = line.split("_") tiletype = "Logic" x, y = int(fields[1]), int(fields[2]) continue if line.startswith("RAM_Tile") or line.startswith("IO_Tile"): fields = line.split("_") tiletype = fields[0] x, y = int(fields[2]), int(fields[3]) continue if line.startswith("GlobalNetwork"): tiletype = "" continue if tiletype != "": fields = re.split('[ ()]*', line.strip()) if len(fields) <= 1: continue fields = [int(fields[i+1]) for i in range(4)] print("%-5s %2d %2d %2d %2d %3d %3d" % (tiletype, x, y, fields[0], fields[1], fields[2], fields[3])) fpga-icestorm-0~20160913git266e758/icefuzz/icecube.sh000066400000000000000000000256411276746530600220140ustar00rootroot00000000000000#!/bin/bash # # Installing iCEcube2: # - Install iCEcube2.2015.08 in /opt/lscc/iCEcube2.2015.08 # - Install License in /opt/lscc/iCEcube2.2015.08/license.dat # # Creating a project: # - .v ## HDL sources (use "top" as name for the top module) # - .sdc ## timing constraint file # - .pcf ## physical constraint file # # Running iCEcube2: # - bash icecube.sh [-1k|-8k] ## creates .bin # # # # Additional notes for installing iCEcube2 on 64 Bit Ubuntu: # # sudo apt-get install ibc6-i386 zlib1g:i386 libxext6:i386 libpng12-0:i386 libsm6:i386 # sudo apt-get install libxi6:i386 libxrender1:i386 libxrandr2:i386 libxfixes3:i386 # sudo apt-get install libxcursor1:i386 libXinerama.so.1:i386 libXinerama1:i386 libfreetype6:i386 # sudo apt-get install libfontconfig1:i386 libglib2.0-0:i386 libstdc++6:i386 libelf1:i386 # # icecubedir="/opt/lscc/iCEcube2.2015.08" # sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/synplify_pro # sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/c_hdl # sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/syn_nfilter # sudo sed -ri "1 s,/bin/sh,/bin/bash,;" $icecubedir/synpbase/bin/m_generic # scriptdir=${BASH_SOURCE%/*} if [ -z "$scriptdir" ]; then scriptdir="."; fi if [ "$1" == "-1k" ]; then ICEDEV=hx1k-tq144 shift fi if [ "$1" == "-8k" ]; then ICEDEV=hx8k-ct256 shift fi if [ "$1" == "-ul1k" ]; then ICEDEV=ul1k-cm36a shift fi set -ex set -- ${1%.v} icecubedir="${ICECUBEDIR:-/opt/lscc/iCEcube2.2015.08}" export FOUNDRY="$icecubedir/LSE" export SBT_DIR="$icecubedir/sbt_backend" export SYNPLIFY_PATH="$icecubedir/synpbase" export LM_LICENSE_FILE="$icecubedir/license.dat" export TCL_LIBRARY="$icecubedir/sbt_backend/bin/linux/lib/tcl8.4" export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt" export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt/synpwrap" export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/lib/linux/opt" export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/LSE/bin/lin" case "${ICEDEV:-hx1k-tq144}" in hx1k-cb132) iCEPACKAGE="CB132" iCE40DEV="iCE40HX1K" ;; hx1k-vq100) iCEPACKAGE="VQ100" iCE40DEV="iCE40HX1K" ;; hx1k-tq144) iCEPACKAGE="TQ144" iCE40DEV="iCE40HX1K" ;; hx4k-cb132) iCEPACKAGE="CB132" iCE40DEV="iCE40HX4K" ;; hx4k-tq144) iCEPACKAGE="TQ144" iCE40DEV="iCE40HX4K" ;; hx8k-cm225) iCEPACKAGE="CM225" iCE40DEV="iCE40HX8K" ;; hx8k-ct256) iCEPACKAGE="CT256" iCE40DEV="iCE40HX8K" ;; hx8k-cb132) iCEPACKAGE="CB132" iCE40DEV="iCE40HX8K" ;; lp1k-swg16tr) iCEPACKAGE="SWG16TR" iCE40DEV="iCE40LP1K" ;; lp1k-cm36) iCEPACKAGE="CM36" iCE40DEV="iCE40LP1K" ;; lp1k-cm49) iCEPACKAGE="CM49" iCE40DEV="iCE40LP1K" ;; lp1k-cm81) iCEPACKAGE="CM81" iCE40DEV="iCE40LP1K" ;; lp1k-cm121) iCEPACKAGE="CM121" iCE40DEV="iCE40LP1K" ;; lp1k-qn84) iCEPACKAGE="QN84" iCE40DEV="iCE40LP1K" ;; lp1k-cb81) iCEPACKAGE="CB81" iCE40DEV="iCE40LP1K" ;; lp1k-cb121) iCEPACKAGE="CB121" iCE40DEV="iCE40LP1K" ;; lp4k-cm81) iCEPACKAGE="CM81" iCE40DEV="iCE40LP4K" ;; lp4k-cm121) iCEPACKAGE="CM121" iCE40DEV="iCE40LP4K" ;; lp4k-cm225) iCEPACKAGE="CM225" iCE40DEV="iCE40LP4K" ;; lp8k-cm81) iCEPACKAGE="CM81" iCE40DEV="iCE40LP8K" ;; lp8k-cm121) iCEPACKAGE="CM121" iCE40DEV="iCE40LP8K" ;; lp8k-cm225) iCEPACKAGE="CM225" iCE40DEV="iCE40LP8K" ;; ul1k-cm36a) iCEPACKAGE="CM36A" iCE40DEV="iCE40UL1K" ;; ul1k-swg16) iCEPACKAGE="CM36A" iCE40DEV="iCE40UL1K" ;; *) echo "ERROR: Invalid \$ICEDEV device config '$ICEDEV'." exit 1 esac case "$iCE40DEV" in iCE40HX1K) icetech="SBTiCE40" libfile="ice40HX1K.lib" devfile="ICE40P01.dev" ;; iCE40HX4K) icetech="SBTiCE40" libfile="ice40HX8K.lib" devfile="ICE40P04.dev" ;; iCE40HX8K) icetech="SBTiCE40" libfile="ice40HX8K.lib" devfile="ICE40P08.dev" ;; iCE40LP1K) icetech="SBTiCE40" libfile="ice40LP1K.lib" devfile="ICE40P01.dev" ;; iCE40LP4K) icetech="SBTiCE40" libfile="ice40LP8K.lib" devfile="ICE40P04.dev" ;; iCE40LP8K) icetech="SBTiCE40" libfile="ice40LP8K.lib" devfile="ICE40P08.dev" ;; iCE40UL1K) icetech="SBTiCE40UL" libfile="ice40BT1K.lib" devfile="ICE40T01.dev" ;; esac ( rm -rf "$1.tmp" mkdir -p "$1.tmp" cp "$1.v" "$1.tmp/input.v" if test -f "$1.sdc"; then cp "$1.sdc" "$1.tmp/input.sdc"; fi if test -f "$1.pcf"; then cp "$1.pcf" "$1.tmp/input.pcf"; fi cd "$1.tmp" touch input.sdc touch input.pcf mkdir -p outputs/packer mkdir -p outputs/placer mkdir -p outputs/router mkdir -p outputs/bitmap mkdir -p outputs/netlist mkdir -p netlist/Log/bitmap cat > impl_syn.prj << EOT add_file -verilog -lib work input.v impl -add impl -type fpga # implementation attributes set_option -vlog_std v2001 set_option -project_relative_includes 1 # device options set_option -technology $icetech set_option -part $iCE40DEV set_option -package $iCEPACKAGE set_option -speed_grade set_option -part_companion "" # mapper_options set_option -frequency auto set_option -write_verilog 0 set_option -write_vhdl 0 # Silicon Blue iCE40 set_option -maxfan 10000 set_option -disable_io_insertion 0 set_option -pipe 1 set_option -retiming 0 set_option -update_models_cp 0 set_option -fixgatedclocks 2 set_option -fixgeneratedclocks 0 # NFilter set_option -popfeed 0 set_option -constprop 0 set_option -createhierarchy 0 # sequential_optimization_options set_option -symbolic_fsm_compiler 1 # Compiler Options set_option -compiler_compatible 0 set_option -resource_sharing 1 # automatic place and route (vendor) options set_option -write_apr_constraint 1 # set result format/file last project -result_format edif project -result_file impl.edf impl -active impl project -run synthesis -clean EOT cat > impl_lse.prj << EOT #device -a $icetech -d $iCE40DEV -t $iCEPACKAGE #constraint file #options -optimization_goal Area -twr_paths 3 -bram_utilization 100.00 -ramstyle Auto -romstyle Auto -use_carry_chain 1 -carry_chain_length 0 -resource_sharing 1 -propagate_constants 1 -remove_duplicate_regs 1 -max_fanout 10000 -fsm_encoding_style Auto -use_io_insertion 1 -use_io_reg auto -resolve_mixed_drivers 0 -RWCheckOnRam 0 -fix_gated_clocks 1 -loop_limit 1950 -ver "input.v" -p "$PWD" #set result format/file last -output_edif impl/impl.edf #set log file -logfile "impl_lse.log" EOT # synthesis (Synplify Pro) if false; then "$icecubedir"/sbt_backend/bin/linux/opt/synpwrap/synpwrap -prj impl_syn.prj -log impl.srr fi # synthesis (Lattice LSE) if true; then "$icecubedir"/LSE/bin/lin/synthesis -f "impl_lse.prj" fi # convert netlist "$icecubedir"/sbt_backend/bin/linux/opt/edifparser "$icecubedir"/sbt_backend/devices/$devfile "$PWD"/impl/impl.edf "$PWD"/netlist -p$iCEPACKAGE -yinput.pcf -sinput.sdc -c --devicename $iCE40DEV # run placer "$icecubedir"/sbt_backend/bin/linux/opt/sbtplacer --des-lib "$PWD"/netlist/oadb-top --outdir "$PWD"/outputs/placer --device-file "$icecubedir"/sbt_backend/devices/$devfile --package $iCEPACKAGE --deviceMarketName $iCE40DEV --sdc-file "$PWD"/Temp/sbt_temp.sdc --lib-file "$icecubedir"/sbt_backend/devices/$libfile --effort_level std --out-sdc-file "$PWD"/outputs/placer/top_pl.sdc # run packer "$icecubedir"/sbt_backend/bin/linux/opt/packer "$icecubedir"/sbt_backend/devices/$devfile "$PWD"/netlist/oadb-top --package $iCEPACKAGE --outdir "$PWD"/outputs/packer --translator "$icecubedir"/sbt_backend/bin/sdc_translator.tcl --src_sdc_file "$PWD"/outputs/placer/top_pl.sdc --dst_sdc_file "$PWD"/outputs/packer/top_pk.sdc --devicename $iCE40DEV # run router "$icecubedir"/sbt_backend/bin/linux/opt/sbrouter "$icecubedir"/sbt_backend/devices/$devfile "$PWD"/netlist/oadb-top "$icecubedir"/sbt_backend/devices/$libfile "$PWD"/outputs/packer/top_pk.sdc --outdir "$PWD"/outputs/router --sdf_file "$PWD"/outputs/netlist/top_sbt.sdf --pin_permutation # run netlister "$icecubedir"/sbt_backend/bin/linux/opt/netlister --verilog "$PWD"/outputs/netlist/top_sbt.v --vhdl "$PWD"/outputs/netlist/top_sbt.vhd --lib "$PWD"/netlist/oadb-top --view rt --device "$icecubedir"/sbt_backend/devices/$devfile --splitio --in-sdc-file "$PWD"/outputs/packer/top_pk.sdc --out-sdc-file "$PWD"/outputs/netlist/top_sbt.sdc if [ -n "$ICE_SBTIMER_LP" ]; then "$icecubedir"/sbt_backend/bin/linux/opt/sbtimer --des-lib "$PWD"/netlist/oadb-top --lib-file "$icecubedir"/sbt_backend/devices/$libfile --sdc-file "$PWD"/outputs/netlist/top_sbt.sdc --sdf-file "$PWD"/outputs/netlist/top_sbt_lp.sdf --report-file "$PWD"/outputs/netlist/top_timing_lp.rpt --device-file "$icecubedir"/sbt_backend/devices/$devfile --timing-summary fi # hacks for sbtimer so it knows what device we are dealing with ln -fs . sbt ln -fs . foobar_Implmnt cat > foobar_sbt.project << EOT [Project] Implementations=foobar_Implmnt [foobar_Implmnt] DeviceFamily=$( echo $iCE40DEV | sed -re 's,(HX).*,,'; ) Device=$( echo $iCE40DEV | sed -re 's,iCE40,,'; ) DevicePackage=$iCEPACKAGE Devicevoltage=1.14 DevicevoltagePerformance=+/-5%(datasheet default) DeviceTemperature=85 TimingAnalysisBasedOn=Worst OperationRange=Commercial IOBankVoltages=topBank,2.5 bottomBank,2.5 leftBank,2.5 rightBank,2.5 derValue=0.701346 EOT # run timer "$icecubedir"/sbt_backend/bin/linux/opt/sbtimer --des-lib "$PWD"/foobar_Implmnt/sbt/netlist/oadb-top --lib-file "$icecubedir"/sbt_backend/devices/$libfile --sdc-file "$PWD"/outputs/netlist/top_sbt.sdc --sdf-file "$PWD"/outputs/netlist/top_sbt.sdf --report-file "$PWD"/outputs/netlist/top_timing.rpt --device-file "$icecubedir"/sbt_backend/devices/$devfile --timing-summary # make bitmap "$icecubedir"/sbt_backend/bin/linux/opt/bitmap "$icecubedir"/sbt_backend/devices/$devfile --design "$PWD"/netlist/oadb-top --device_name $iCE40DEV --package $iCEPACKAGE --outdir "$PWD"/outputs/bitmap --debug --low_power on --init_ram on --init_ram_bank 1111 --frequency low --warm_boot on ) ( set +x echo "export FOUNDRY=\"$FOUNDRY\"" echo "export SBT_DIR=\"$SBT_DIR\"" echo "export TCL_LIBRARY=\"$TCL_LIBRARY\"" echo "export LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\"" ) cp "$1.tmp"/outputs/bitmap/top_bitmap.bin "$1.bin" cp "$1.tmp"/outputs/bitmap/top_bitmap_glb.txt "$1.glb" cp "$1.tmp"/outputs/placer/top_sbt.pcf "$1.psb" cp "$1.tmp"/outputs/netlist/top_sbt.v "$1.vsb" cp "$1.tmp"/outputs/netlist/top_sbt.sdf "$1.sdf" cp "$1.tmp"/outputs/netlist/top_timing.rpt "$1.rpt" if [ -n "$ICE_SBTIMER_LP" ]; then cp "$1.tmp"/outputs/netlist/top_sbt_lp.sdf "$1.slp" cp "$1.tmp"/outputs/netlist/top_timing_lp.rpt "$1.rlp" fi $scriptdir/../icepack/iceunpack "$1.bin" "$1.asc" fpga-icestorm-0~20160913git266e758/icefuzz/make_aig.py000066400000000000000000000034621276746530600221650ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_aig") os.mkdir("work_aig") for idx in range(num): with open("work_aig/aig_%02d.v" % idx, "w") as f: print("module top(input [31:0] a, output [31:0] y);", file=f) sigs = ["a[%d]" % i for i in range(32)] netidx = 0 for i in range(100 if num_ramb40 < 20 else 1000): netidx += 1 newnet = "n_%d" % netidx print(" wire %s = %s%s && %s%s;" % (newnet, np.random.choice(["", "!"]), np.random.choice(sigs), np.random.choice(["", "!"]), np.random.choice(sigs)), file=f) sigs.append(newnet) while len(sigs) > 32: netidx += 1 newnet = "n_%d" % netidx a = np.random.choice(sigs) sigs.remove(a) b = np.random.choice(sigs) sigs.remove(b) print(" wire %s = %s%s && %s%s;" % (newnet, np.random.choice(["", "!"]), a, np.random.choice(["", "!"]), b), file=f) sigs.append(newnet) for i in range(32): print(" assign y[%d] = %s;" % (i, sigs[i]), file=f) print("endmodule", file=f) with open("work_aig/aig_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(32): print("set_io a[%d] %s" % (i, p[i]), file=f) print("set_io y[%d] %s" % (i, p[i+32]), file=f) with open("work_aig/Makefile", "w") as f: print("all: %s" % " ".join(["aig_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("aig_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh aig_%02d > aig_%02d.log 2>&1 && rm -rf aig_%02d.tmp || tail aig_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_binop.py000066400000000000000000000017421276746530600225330ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_binop") os.mkdir("work_binop") for idx in range(num): with open("work_binop/binop_%02d.v" % idx, "w") as f: print("module top(input a, b, output y);", file=f) print(" assign y = a%sb;" % np.random.choice([" ^ ", " ^ ~", " & ", " & ~", " | ", " | ~"]), file=f) print("endmodule", file=f) with open("work_binop/binop_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) print("set_io a %s" % p[0], file=f) print("set_io b %s" % p[1], file=f) print("set_io y %s" % p[2], file=f) with open("work_binop/Makefile", "w") as f: print("all: %s" % " ".join(["binop_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("binop_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh binop_%02d > binop_%02d.log 2>&1 && rm -rf binop_%02d.tmp || tail binop_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_cluster.py000066400000000000000000000021021276746530600230740ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_cluster") os.mkdir("work_cluster") for idx in range(num): with open("work_cluster/cluster_%02d.v" % idx, "w") as f: print("module top(input [3:0] a, output [3:0] y);", file=f) print(" assign y = {|a, &a, ^a, a[3:2] == a[1:0]};", file=f) print("endmodule", file=f) with open("work_cluster/cluster_%02d.pcf" % idx, "w") as f: i = np.random.randint(len(pins)) netnames = np.random.permutation(["a[%d]" % i for i in range(4)] + ["y[%d]" % i for i in range(4)]) for net in netnames: print("set_io %s %s" % (net, pins[i]), file=f) i = (i + 1) % len(pins) with open("work_cluster/Makefile", "w") as f: print("all: %s" % " ".join(["cluster_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("cluster_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh cluster_%02d > cluster_%02d.log 2>&1 && rm -rf cluster_%02d.tmp || tail cluster_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_fanout.py000066400000000000000000000017531276746530600227220ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_fanout") os.mkdir("work_fanout") for idx in range(num): with open("work_fanout/fanout_%02d.v" % idx, "w") as f: print("module top(input [1:0] a, output [63:0] y);", file=f) print(" assign y = {32{a}};", file=f) print("endmodule", file=f) with open("work_fanout/fanout_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(64): print("set_io y[%d] %s" % (i, p[i]), file=f) print("set_io a[0] %s" % p[64], file=f) print("set_io a[1] %s" % p[65], file=f) with open("work_fanout/Makefile", "w") as f: print("all: %s" % " ".join(["fanout_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("fanout_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh fanout_%02d > fanout_%02d.log 2>&1 && rm -rf fanout_%02d.tmp || tail fanout_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_fflogic.py000066400000000000000000000043401276746530600230320ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_fflogic") os.mkdir("work_fflogic") def random_op(): return np.random.choice(["+", "-", "*", "^", "&", "|"]) def print_seq_op(dst, src1, src2, op, f): mode = np.random.choice(list("abc")) negreset = np.random.choice(["!", ""]) enable = np.random.choice(["if (en) ", ""]) if mode == "a": print(" always @(%sedge clk) begin" % np.random.choice(["pos", "neg"]), file=f) print(" %s%s <= %s %s %s;" % (enable, dst, src1, op, src2), file=f) print(" end", file=f) elif mode == "b": print(" always @(%sedge clk) begin" % np.random.choice(["pos", "neg"]), file=f) print(" if (%srst)" % negreset, file=f) print(" %s <= %d;" % (dst, np.random.randint(2**16)), file=f) print(" else", file=f) print(" %s%s <= %s %s %s;" % (enable, dst, src1, op, src2), file=f) print(" end", file=f) elif mode == "c": print(" always @(%sedge clk, %sedge rst) begin" % (np.random.choice(["pos", "neg"]), "neg" if negreset == "!" else "pos"), file=f) print(" if (%srst)" % negreset, file=f) print(" %s <= %d;" % (dst, np.random.randint(2**16)), file=f) print(" else", file=f) print(" %s%s <= %s %s %s;" % (enable, dst, src1, op, src2), file=f) print(" end", file=f) else: assert False for idx in range(num): with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f: print("module top(input clk, rst, en, input [15:0] a, b, c, d, output [15:0] y, output z);", file=f) print(" reg [15:0] p, q;", file=f) print_seq_op("p", "a", "b", random_op(), f) print_seq_op("q", "c", "d", random_op(), f) print(" assign y = p %s q, z = clk ^ rst ^ en;" % random_op(), file=f) print("endmodule", file=f) with open("work_fflogic/Makefile", "w") as f: print("all: %s" % " ".join(["fflogic_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("fflogic_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh fflogic_%02d > fflogic_%02d.log 2>&1 && rm -rf fflogic_%02d.tmp || tail fflogic_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_gbio.py000066400000000000000000000067211276746530600223460ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_gbio") os.mkdir("work_gbio") for p in gpins: if p in pins: pins.remove(p) for idx in range(num): with open("work_gbio/gbio_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) print(""" module top ( inout [7:0] pin, input latch_in, input clk_en, input clk_in, input clk_out, input oen, input dout_0, input dout_1, output [7:0] din_0, output [7:0] din_1, output [7:0] globals, output reg q ); SB_GB_IO #( .PIN_TYPE(6'b 1100_00), .PULLUP(1'b0), .NEG_TRIGGER(1'b0), .IO_STANDARD("SB_LVCMOS") ) PINS [7:0] ( .PACKAGE_PIN(pin), .LATCH_INPUT_VALUE(%s), .CLOCK_ENABLE(%s), .INPUT_CLK(%s), .OUTPUT_CLK(%s), .OUTPUT_ENABLE(%s), .D_OUT_0(%s), .D_OUT_1(%s), .D_IN_0(%s), .D_IN_1(%s), .GLOBAL_BUFFER_OUTPUT(%s) ); always @(posedge globals[%d], posedge globals[%d]) if (globals[%d]) q <= 0; else if (globals[%d]) q <= globals[%d]; endmodule """ % ( np.random.choice(["latch_in", "globals", "din_0+din_1", "din_0^din_1"]), np.random.choice(["clk_en", "globals", "din_0+din_1", "din_0^din_1"]), np.random.choice(["clk_in", "globals", "din_0+din_1", "din_0^din_1"]), np.random.choice(["clk_out", "globals", "din_0+din_1", "din_0^din_1"]), np.random.choice(["oen", "globals", "din_0+din_1", "din_0^din_1"]), np.random.choice(["dout_1", "globals", "globals^dout_0", "din_0+din_1", "~din_0"]), np.random.choice(["dout_0", "globals", "globals^dout_1", "din_0+din_1", "~din_1"]), np.random.choice(["din_0", "{din_0[3:0], din_0[7:4]}"]), np.random.choice(["din_1", "{din_1[1:0], din_1[7:2]}"]), np.random.choice(["globals", "{globals[0], globals[7:1]}"]), glbs[0], glbs[1], glbs[1], glbs[2], glbs[3] ), file=f) with open("work_gbio/gbio_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) g = np.random.permutation(gpins) for i in range(8): print("set_io pin[%d] %s" % (i, g[i]), file=f) print("set_io din_0[%d] %s" % (i, p[8+i]), file=f) print("set_io din_1[%d] %s" % (i, p[2*8+i]), file=f) print("set_io globals[%d] %s" % (i, p[3*8+i]), file=f) for i, n in enumerate("latch_in clk_en clk_in clk_out oen dout_0 dout_1".split()): print("set_io %s %s" % (n, p[4*8+i]), file=f) print("set_io q %s" % (p[-1]), file=f) with open("work_gbio/Makefile", "w") as f: print("all: %s" % " ".join(["gbio_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("gbio_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh gbio_%02d > gbio_%02d.log 2>&1 && rm -rf gbio_%02d.tmp || tail gbio_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_gbio2.py000066400000000000000000000060511276746530600224240ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_gbio2") os.mkdir("work_gbio2") for p in gpins: if p in pins: pins.remove(p) for idx in range(num): with open("work_gbio2/gbio2_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) print(""" module top ( inout [7:0] pin, input latch_in, input clk_en, input clk_in, input clk_out, input oen, input dout_0, input dout_1, output [7:0] din_0, output [7:0] din_1, output [7:0] globals, output reg q ); """, file=f); for k in range(8): print(""" SB_GB_IO #( .PIN_TYPE(6'b %s), .PULLUP(1'b %s), .NEG_TRIGGER(1'b %s), .IO_STANDARD("SB_LVCMOS") ) \pin[%d]_gb_io ( .PACKAGE_PIN(pin[%d]), .LATCH_INPUT_VALUE(latch_in), .CLOCK_ENABLE(clk_en), .INPUT_CLK(clk_in), .OUTPUT_CLK(clk_out), .OUTPUT_ENABLE(oen), .D_OUT_0(dout_0), .D_OUT_1(dout_1), .D_IN_0(din_0[%d]), .D_IN_1(din_1[%d]), .GLOBAL_BUFFER_OUTPUT(globals[%d]) ); """ % ( np.random.choice(["1100_00", "1010_10", "1010_00", "0000_11", "1111_00"]), np.random.choice(["0", "1"]), np.random.choice(["0", "1"]), k, k, k, k, k ), file=f) print(""" always @(posedge globals[%d], posedge globals[%d]) if (globals[%d]) q <= 0; else if (globals[%d]) q <= globals[%d]; endmodule """ % ( glbs[0], glbs[1], glbs[1], glbs[2], glbs[3] ), file=f) with open("work_gbio2/gbio2_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) g = np.random.permutation(gpins) for i in range(8): print("set_io pin[%d] %s" % (i, g[i]), file=f) print("set_io din_0[%d] %s" % (i, p[8+i]), file=f) print("set_io din_1[%d] %s" % (i, p[2*8+i]), file=f) print("set_io globals[%d] %s" % (i, p[3*8+i]), file=f) for i, n in enumerate("latch_in clk_en clk_in clk_out oen dout_0 dout_1".split()): print("set_io %s %s" % (n, p[4*8+i]), file=f) print("set_io q %s" % (p[-1]), file=f) with open("work_gbio2/Makefile", "w") as f: print("all: %s" % " ".join(["gbio2_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("gbio2_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh gbio2_%02d > gbio2_%02d.log 2>&1 && rm -rf gbio2_%02d.tmp || tail gbio2_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_io.py000066400000000000000000000043111276746530600220260ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_io") os.mkdir("work_io") for idx in range(num): with open("work_io/io_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) print(""" module top ( inout [3:0] pin, input [3:0] latch_in, input [3:0] clk_en, input [3:0] clk_in, input [3:0] clk_out, input [3:0] oen, input [3:0] dout_0, input [3:0] dout_1, output [3:0] din_0, output [3:0] din_1 ); SB_IO #( .PIN_TYPE(6'b %s_%s), .PULLUP(1'b %s), .NEG_TRIGGER(1'b %s), .IO_STANDARD("SB_LVCMOS") ) PINS [3:0] ( .PACKAGE_PIN(pin), .LATCH_INPUT_VALUE(latch_in), .CLOCK_ENABLE(clk_en), .INPUT_CLK(clk_in), .OUTPUT_CLK(clk_out), .OUTPUT_ENABLE(oen), .D_OUT_0(dout_0), .D_OUT_1(dout_1), .D_IN_0(din_0), .D_IN_1(din_1) ); endmodule """ % ( np.random.choice(["0000", "0110", "1010", "1110", "0101", "1001", "1101", "0100", "1000", "1100", "0111", "1111"]), np.random.choice(["00", "01", "10", "11"]), np.random.choice(["0", "1"]), np.random.choice(["0", "1"]) ), file=f) with open("work_io/io_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for k in ["pin", "latch_in", "clk_en", "clk_in", "clk_out", "oen", "dout_0", "dout_1", "din_0", "din_1"]: for i in range(4): print("set_io %s[%d] %s" % (k, i, p.pop()), file=f) with open("work_io/Makefile", "w") as f: print("all: %s" % " ".join(["io_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("io_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh io_%02d > io_%02d.log 2>&1 && rm -rf io_%02d.tmp || tail io_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_iopack.py000066400000000000000000000044011276746530600226650ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os from numpy.random import randint, choice, permutation num_xor = 8 num_luts = 8 num_outputs_range = (5, 20) os.system("rm -rf work_iopack") os.mkdir("work_iopack") def get_pin_directions(): pindirs = ["i" for i in range(len(pins))] for i in range(randint(num_outputs_range[0], num_outputs_range[1])): pindirs[randint(len(pins))] = "o" return pindirs def get_nearby_inputs(p, n, r): while True: ipins = list() for i in range(-r, +r): ip = (p + i + len(pins)) % len(pins) if pindirs[ip] == "i": ipins.append(ip) if len(ipins) >= n: break r += 4 return [choice(ipins) for i in range(n)] for idx in range(num): with open("work_iopack/iopack_%02d.v" % idx, "w") as f: pindirs = get_pin_directions() print("module top(%s);" % ", ".join(["%sput p%d" % ("in" if pindirs[i] == "i" else "out", i) for i in range(len(pins))]), file=f) for outp in range(len(pins)): if pindirs[outp] == "o": xor_nets = set(["%sp%d" % (choice(["~", ""]), p) for p in get_nearby_inputs(outp, num_xor, 2 + randint(10))]) for i in range(num_luts): print(" localparam [15:0] p%d_lut%d = 16'd %d;" % (outp, i, randint(2**16)), file=f) print(" wire p%d_in%d = p%d_lut%d >> {%s};" % (outp, i, outp, i, ", ".join(["p%d" % p for p in get_nearby_inputs(outp + randint(-10, +11), 4, 4)])), file=f) xor_nets.add("%sp%d_in%d" % (choice(["~", ""]), outp, i)) print(" assign p%d = ^{%s};" % (outp, ", ".join(sorted(xor_nets))), file=f) print("endmodule", file=f) with open("work_iopack/iopack_%02d.pcf" % idx, "w") as f: for i in range(len(pins)): print("set_io p%d %s" % (i, pins[i]), file=f) with open("work_iopack/Makefile", "w") as f: print("all: %s" % " ".join(["iopack_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("iopack_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh iopack_%02d > iopack_%02d.log 2>&1 && rm -rf iopack_%02d.tmp || tail iopack_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_logic.py000066400000000000000000000024041276746530600225150ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_logic") os.mkdir("work_logic") def random_op(): return np.random.choice(["+", "-", "^", "&", "|", "&~", "|~"]) for idx in range(num): with open("work_logic/logic_%02d.v" % idx, "w") as f: print("module top(input [15:0] a, b, c, d, output [15:0] y);", file=f) print(" assign y = (a %s b) %s (c %s d);" % (random_op(), random_op(), random_op()), file=f) print("endmodule", file=f) with open("work_logic/logic_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(16): print("set_io a[%d] %s" % (i, p[i]), file=f) print("set_io b[%d] %s" % (i, p[i+16]), file=f) print("set_io c[%d] %s" % (i, p[i+32]), file=f) print("set_io d[%d] %s" % (i, p[i+48]), file=f) print("set_io y[%d] %s" % (i, p[i+64]), file=f) with open("work_logic/Makefile", "w") as f: print("all: %s" % " ".join(["logic_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("logic_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh logic_%02d > logic_%02d.log 2>&1 && rm -rf logic_%02d.tmp || tail logic_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_mem.py000066400000000000000000000027151276746530600222030ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_mem") os.mkdir("work_mem") for idx in range(num): with open("work_mem/mem_%02d.v" % idx, "w") as f: print(""" module top(input clk, i0, i1, i2, i3, output reg o0, o1, o2, o3, o4); reg [9:0] raddr, waddr, rdata, wdata; reg [9:0] memory [0:1023]; always @(posedge clk) begin case ({i0, i1, i2}) 0: raddr <= {raddr, i3}; 1: waddr <= {waddr, i3}; 2: wdata <= {wdata, i3}; 3: rdata <= memory[raddr]; 4: memory[waddr] <= wdata; 5: rdata <= memory[waddr]; 6: {o0, o1, o2, o3, o4} <= rdata[4:0]; 7: {o0, o1, o2, o3, o4} <= rdata[9:5]; endcase end endmodule """, file=f) with open("work_mem/mem_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for port in [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3", "o4" ]: print("set_io %s %s" % (port, p.pop()), file=f) with open("work_mem/Makefile", "w") as f: print("all: %s" % " ".join(["mem_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("mem_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh mem_%02d > mem_%02d.log 2>&1 && rm -rf mem_%02d.tmp || tail mem_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_mesh.py000066400000000000000000000017041276746530600223560ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_mesh") os.mkdir("work_mesh") for idx in range(num): with open("work_mesh/mesh_%02d.v" % idx, "w") as f: print("module top(input [39:0] a, output [39:0] y);", file=f) print(" assign y = a;", file=f) print("endmodule", file=f) with open("work_mesh/mesh_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(40): print("set_io a[%d] %s" % (i, p[i]), file=f) for i in range(40): print("set_io y[%d] %s" % (i, p[40+i]), file=f) with open("work_mesh/Makefile", "w") as f: print("all: %s" % " ".join(["mesh_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("mesh_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh mesh_%02d > mesh_%02d.log 2>&1 && rm -rf mesh_%02d.tmp || tail mesh_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_pin2pin.py000066400000000000000000000016101276746530600227750ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_pin2pin") os.mkdir("work_pin2pin") for idx in range(num): with open("work_pin2pin/pin2pin_%02d.v" % idx, "w") as f: print("module top(input a, output y);", file=f) print(" assign y = a;", file=f) print("endmodule", file=f) with open("work_pin2pin/pin2pin_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) print("set_io a %s" % p[0], file=f) print("set_io y %s" % p[1], file=f) with open("work_pin2pin/Makefile", "w") as f: print("all: %s" % " ".join(["pin2pin_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("pin2pin_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh pin2pin_%02d > pin2pin_%02d.log 2>&1 && rm -rf pin2pin_%02d.tmp || tail pin2pin_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_pll.py000066400000000000000000000131531276746530600222120ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os from numpy.random import randint, choice, permutation def randbin(n): return "".join([choice(["0", "1"]) for i in range(n)]) for p in gpins: if p in pins: pins.remove(p) os.system("rm -rf work_pll") os.mkdir("work_pll") for idx in range(num): pin_names = list() vlog_body = list() pll_inst = list() pll_type = choice(["SB_PLL40_CORE", "SB_PLL40_2F_CORE", "SB_PLL40_PAD", "SB_PLL40_2_PAD", "SB_PLL40_2F_PAD"]) pll_inst.append("%s uut (" % pll_type) if pll_type.endswith("_PAD"): pin_names.append("packagepin") vlog_body.append("input packagepin;") pll_inst.append(" .PACKAGEPIN(packagepin),") else: pin_names.append("referenceclk") vlog_body.append("input referenceclk;") pll_inst.append(" .REFERENCECLK(referenceclk),") for pin in ["a", "b"]: pin_names.append(pin) vlog_body.append("input %s;" % pin) for pin in ["w", "x", "y", "z"]: pin_names.append(pin) vlog_body.append("output %s%s;" % ("reg " if pin in ["y", "z"] else "", pin)) for pin in ["EXTFEEDBACK", "BYPASS", "RESETB", "LOCK", "LATCHINPUTVALUE", "SDI", "SDO", "SCLK"]: pin_names.append(pin.lower()) vlog_body.append("%sput %s;" % ("out" if pin in ["LOCK", "SDO"] else "in", pin.lower())) pll_inst.append(" .%s(%s)," % (pin, pin.lower())) if pll_type.find("_2_") < 0 and pll_type.find("_2F_") < 0: for pin in ["PLLOUTCORE", "PLLOUTGLOBAL"]: vlog_body.append("wire %s;" % pin.lower()) pll_inst.append(" .%s(%s)," % (pin, pin.lower())) vlog_body.append("assign w = plloutcore ^ a;") vlog_body.append("assign x = plloutcore ^ b;") vlog_body.append("always @(posedge plloutglobal) y <= a;") vlog_body.append("always @(posedge plloutglobal) z <= b;") else: for pin in ["PLLOUTCOREA", "PLLOUTCOREB", "PLLOUTGLOBALA", "PLLOUTGLOBALB"]: vlog_body.append("wire %s;" % pin.lower()) pll_inst.append(" .%s(%s)," % (pin, pin.lower())) vlog_body.append("assign w = plloutcorea ^ a;") vlog_body.append("assign x = plloutcoreb ^ b;") vlog_body.append("always @(posedge plloutglobala) y <= a;") vlog_body.append("always @(posedge plloutglobalb) z <= b;") for i in range(8): pin_names.append("dynamicdelay_%d" % i) vlog_body.append("input dynamicdelay_%d;" % i) pll_inst.append(" .DYNAMICDELAY({%s})" % ", ".join(["dynamicdelay_%d" % i for i in range(7, -1, -1)])) pll_inst.append(");") divq = randbin(3) if divq == "000": divq = "001" if divq == "111": divq = "110" pll_inst.append("defparam uut.DIVR = 4'b%s;" % randbin(4)) pll_inst.append("defparam uut.DIVF = 7'b%s;" % randbin(7)) pll_inst.append("defparam uut.DIVQ = 3'b%s;" % divq) pll_inst.append("defparam uut.FILTER_RANGE = 3'b%s;" % randbin(3)) pll_inst.append("defparam uut.FEEDBACK_PATH = \"%s\";" % choice(["DELAY", "SIMPLE", "PHASE_AND_DELAY", "EXTERNAL"])) if choice([True, False]): pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_FEEDBACK = \"FIXED\";") pll_inst.append("defparam uut.FDA_FEEDBACK = 4'b%s;" % randbin(4)) else: pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_FEEDBACK = \"DYNAMIC\";") pll_inst.append("defparam uut.FDA_FEEDBACK = 4'b1111;") if choice([True, False]): pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_RELATIVE = \"FIXED\";") pll_inst.append("defparam uut.FDA_RELATIVE = 4'b%s;" % randbin(4)) else: pll_inst.append("defparam uut.DELAY_ADJUSTMENT_MODE_RELATIVE = \"DYNAMIC\";") pll_inst.append("defparam uut.FDA_RELATIVE = 4'b1111;") pll_inst.append("defparam uut.SHIFTREG_DIV_MODE = 1'b%s;" % randbin(1)) if pll_type.find("_2_") < 0 and pll_type.find("_2F_") < 0: pll_inst.append("defparam uut.PLLOUT_SELECT = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"])) elif pll_type.find("_2F_") < 0: pll_inst.append("defparam uut.PLLOUT_SELECT_PORTB = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"])) else: pll_inst.append("defparam uut.PLLOUT_SELECT_PORTA = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"])) pll_inst.append("defparam uut.PLLOUT_SELECT_PORTB = \"%s\";" % choice(["GENCLK", "GENCLK_HALF", "SHIFTREG_90deg", "SHIFTREG_0deg"])) if pll_type.find("_2_") < 0 and pll_type.find("_2F_") < 0: pll_inst.append("defparam uut.ENABLE_ICEGATE = 1'b0;") else: pll_inst.append("defparam uut.ENABLE_ICEGATE_PORTA = 1'b0;") pll_inst.append("defparam uut.ENABLE_ICEGATE_PORTB = 1'b0;") pll_inst.append("defparam uut.TEST_MODE = 1'b0;") with open("work_pll/pll_%02d.v" % idx, "w") as f: print("module top(%s);" % ", ".join(pin_names), file=f) print("\n".join(vlog_body), file=f) print("\n".join(pll_inst), file=f) print("endmodule", file=f) with open("work_pll/pll_%02d.pcf" % idx, "w") as f: for pll_pin, package_pin in zip(pin_names, list(permutation(pins))[0:len(pin_names)]): if pll_pin == "packagepin": package_pin = "49" print("set_io %s %s" % (pll_pin, package_pin), file=f) with open("work_pll/Makefile", "w") as f: print("all: %s" % " ".join(["pll_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("pll_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh pll_%02d > pll_%02d.log 2>&1 && rm -rf pll_%02d.tmp || tail pll_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_prim.py000066400000000000000000000044561276746530600224000ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_prim") os.mkdir("work_prim") for idx in range(num): with open("work_prim/prim_%02d.v" % idx, "w") as f: clkedge = np.random.choice(["pos", "neg"]) print("module top(input clk, input [23:0] a, b, output reg x, output reg [23:0] y);", file=f) print(" reg [23:0] aa, bb;", file=f) print(" always @(%sedge clk) aa <= a;" % clkedge, file=f) print(" always @(%sedge clk) bb <= b;" % clkedge, file=f) if np.random.choice([True, False]): print(" always @(%sedge clk) x <= %s%s;" % (clkedge, np.random.choice(["^", "&", "|", "!"]), np.random.choice(["a", "b", "y"])), file=f) else: print(" always @(%sedge clk) x <= a%sb;" % (clkedge, np.random.choice(["&&", "||"])), file=f) if np.random.choice([True, False]): print(" always @(%sedge clk) y <= a%sb;" % (clkedge, np.random.choice(["+", "-", "&", "|"])), file=f) else: print(" always @(%sedge clk) y <= %s%s;" % (clkedge, np.random.choice(["~", "-", ""]), np.random.choice(["a", "b"])), file=f) print("endmodule", file=f) with open("work_prim/prim_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) if np.random.choice([True, False]): for i in range(24): print("set_io a[%d] %s" % (i, p[i]), file=f) if np.random.choice([True, False]): for i in range(24): print("set_io b[%d] %s" % (i, p[24+i]), file=f) if np.random.choice([True, False]): for i in range(24): print("set_io y[%d] %s" % (i, p[2*24+i]), file=f) if np.random.choice([True, False]): print("set_io x %s" % p[3*24], file=f) if np.random.choice([True, False]): print("set_io y %s" % p[3*24+1], file=f) if np.random.choice([True, False]): print("set_io clk %s" % p[3*24+2], file=f) with open("work_prim/Makefile", "w") as f: print("all: %s" % " ".join(["prim_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("prim_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh prim_%02d > prim_%02d.log 2>&1 && rm -rf prim_%02d.tmp || tail prim_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/make_ram40.py000066400000000000000000000113111276746530600223400ustar00rootroot00000000000000#!/usr/bin/env python3 from fuzzconfig import * import numpy as np import os os.system("rm -rf work_ram40") os.mkdir("work_ram40") for idx in range(num): with open("work_ram40/ram40_%02d.v" % idx, "w") as f: glbs = ["glb[%d]" % i for i in range(np.random.randint(9))] glbs_choice = ["wa", "ra", "msk", "wd", "we", "wce", "wc", "re", "rce", "rc"] print(""" module top ( input [%d:0] glb_pins, input [59:0] in_pins, output [15:0] out_pins ); wire [%d:0] glb, glb_pins; SB_GB gbufs [%d:0] ( .USER_SIGNAL_TO_GLOBAL_BUFFER(glb_pins), .GLOBAL_BUFFER_OUTPUT(glb) ); """ % (len(glbs)-1, len(glbs)-1, len(glbs)-1), file=f) bits = ["in_pins[%d]" % i for i in range(60)] bits = list(np.random.permutation(bits)) for i in range(num_ramb40): tmp = list(np.random.permutation(bits)) rmode = np.random.randint(4) if rmode == 3: wmode = np.random.randint(1, 4) else: wmode = np.random.randint(4) raddr_bits = (8, 9, 10, 11)[rmode] waddr_bits = (8, 9, 10, 11)[wmode] rdata_bits = (16, 8, 4, 2)[rmode] wdata_bits = (16, 8, 4, 2)[wmode] bits_waddr = [tmp.pop() for k in range(waddr_bits)] bits_raddr = [tmp.pop() for k in range(raddr_bits)] bits_mask = [tmp.pop() for k in range(16)] bits_wdata = [tmp.pop() for k in range(wdata_bits)] bit_we = tmp.pop() bit_wclke = tmp.pop() bit_wclk = tmp.pop() bit_re = tmp.pop() bit_rclke = tmp.pop() bit_rclk = tmp.pop() if len(glbs) != 0: s = np.random.choice(glbs_choice) glbs_choice.remove(s) if s == "wa": bits_waddr[np.random.randint(len(bits_waddr))] = glbs.pop() if s == "ra": bits_raddr[np.random.randint(len(bits_raddr))] = glbs.pop() if s == "msk": bits_mask [np.random.randint(len(bits_mask ))] = glbs.pop() if s == "wd": bits_wdata[np.random.randint(len(bits_wdata))] = glbs.pop() if s == "we": bit_we = glbs.pop() if s == "wce": bit_wclke = glbs.pop() if s == "wc": bit_wclk = glbs.pop() if s == "re": bit_re = glbs.pop() if s == "rce": bit_rclke = glbs.pop() if s == "rc": bit_rclk = glbs.pop() bits_waddr = "{%s}" % ", ".join(bits_waddr) bits_raddr = "{%s}" % ", ".join(bits_raddr) bits_mask = "{%s}" % ", ".join(bits_mask) bits_wdata = "{%s}" % ", ".join(bits_wdata) if wmode != 0: bits_mask = "" memtype = np.random.choice(["", "NR", "NW", "NRNW"]) wclksuffix = "N" if memtype in ["NW", "NRNW"] else "" rclksuffix = "N" if memtype in ["NR", "NRNW"] else "" print(""" wire [%d:0] rdata_%d; SB_RAM40_4K%s #( .READ_MODE(%d), .WRITE_MODE(%d) ) ram_%d ( .WADDR(%s), .RADDR(%s), .MASK(%s), .WDATA(%s), .RDATA(rdata_%d), .WE(%s), .WCLKE(%s), .WCLK%s(%s), .RE(%s), .RCLKE(%s), .RCLK%s(%s) ); """ % ( rdata_bits-1, i, memtype, rmode, wmode, i, bits_waddr, bits_raddr, bits_mask, bits_wdata, i, bit_we, bit_wclke, wclksuffix, bit_wclk, bit_re, bit_rclke, rclksuffix, bit_rclk ), file=f) bits = list(np.random.permutation(bits)) for k in range(rdata_bits): bits[k] = "rdata_%d[%d] ^ %s" % (i, k, bits[k]) print("assign out_pins = rdata_%d;" % i, file=f) print("endmodule", file=f) with open("work_ram40/ram40_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for i in range(60): print("set_io in_pins[%d] %s" % (i, p.pop()), file=f) for i in range(16): print("set_io out_pins[%d] %s" % (i, p.pop()), file=f) with open("work_ram40/Makefile", "w") as f: print("all: %s" % " ".join(["ram40_%02d.bin" % i for i in range(num)]), file=f) for i in range(num): print("ram40_%02d.bin:" % i, file=f) print("\t-bash ../icecube.sh ram40_%02d > ram40_%02d.log 2>&1 && rm -rf ram40_%02d.tmp || tail ram40_%02d.log" % (i, i, i, i), file=f) fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/000077500000000000000000000000001276746530600213355ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/.gitignore000066400000000000000000000001511276746530600233220ustar00rootroot00000000000000pinloc-*.mk pinloc-*.exp pinloc-*.exp.new pinloc-*.log pinloc-*.pcf pinloc-*.rpt pinloc-*.txt pinloc-*.v fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-cb121.sh000066400000000000000000000022061276746530600242740ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-cb121 cd pinloc-1k-cb121 pins=" A2 A3 A4 A5 A6 A8 A10 A11 B1 B3 B4 B5 B8 B9 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E2 E3 E4 E5 E6 E7 E8 E9 E11 F2 F3 F4 F7 F8 F9 F10 G1 G3 G4 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J8 J9 J11 K3 K4 K8 K9 K11 L2 L3 L4 L5 L8 L9 L10 L11 " if [ $(echo $pins | wc -w) -ne 92 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-cb121_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-cb121_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-cb121 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-cb121.mk set -ex make -f pinloc-1k-cb121.mk -j4 python3 ../pinlocdb.py pinloc-1k-cb121_*.exp > ../pinloc-1k-cb121.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-cb132.sh000066400000000000000000000022431276746530600242770ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-cb132 cd pinloc-1k-cb132 pins=" A1 A2 A4 A5 A6 A7 A10 A12 B1 B14 C1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C14 D1 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D14 E1 E4 E11 E12 E14 F3 F4 F11 F12 F14 G1 G3 G4 G11 G12 G14 H1 H3 H4 H11 H12 J1 J3 J11 J12 K3 K4 K11 K12 K14 L1 L4 L5 L6 L7 L8 L9 L12 L14 M1 M3 M4 M6 M7 M8 M9 M11 M12 N14 P2 P3 P4 P5 P7 P8 P9 P10 P11 P12 P13 P14 " if [ $(echo $pins | wc -w) -ne 95 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-cb132_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-cb132_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx1k-cb132 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-cb132.mk set -ex make -f pinloc-1k-cb132.mk -j4 python3 ../pinlocdb.py pinloc-1k-cb132_*.exp > ../pinloc-1k-cb132.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-cb81.sh000066400000000000000000000020221276746530600242150ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-cb81 cd pinloc-1k-cb81 pins=" A2 A3 A4 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 E1 E2 E3 E6 E7 E8 E9 F2 F3 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H2 H3 H4 H5 H7 H8 J2 J3 J7 J8 " if [ $(echo $pins | wc -w) -ne 62 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-cb81_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-cb81_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-cb81 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-cb81.mk set -ex make -f pinloc-1k-cb81.mk -j4 python3 ../pinlocdb.py pinloc-1k-cb81_*.exp > ../pinloc-1k-cb81.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-cm121.sh000066400000000000000000000022231276746530600243060ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-cm121 cd pinloc-1k-cm121 pins=" A1 A2 A3 A5 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D10 D11 E2 E3 E4 E6 E7 E8 E9 E10 F2 F3 F4 F5 F6 F8 F9 F11 G2 G4 G8 G9 G11 H1 H2 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J5 J6 J8 J10 J11 K1 K2 K3 K4 K5 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L7 L9 L10 L11 " if [ $(echo $pins | wc -w) -ne 95 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-cm121_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-cm121_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-cm121 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-cm121.mk set -ex make -f pinloc-1k-cm121.mk -j4 python3 ../pinlocdb.py pinloc-1k-cm121_*.exp > ../pinloc-1k-cm121.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-cm36.sh000066400000000000000000000016401276746530600242350ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-cm36 cd pinloc-1k-cm36 pins=" A1 A2 A3 B1 B3 B4 B5 B6 C1 C2 C3 C5 C6 D1 D5 D6 E1 E2 E3 E4 E5 E6 F2 F3 F5 " if [ $(echo $pins | wc -w) -ne 25 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-cm36_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-cm36_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-cm36 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-cm36.mk set -ex make -f pinloc-1k-cm36.mk -j4 python3 ../pinlocdb.py pinloc-1k-cm36_*.exp > ../pinloc-1k-cm36.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-cm49.sh000066400000000000000000000016771276746530600242530ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-cm49 cd pinloc-1k-cm49 pins=" A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 C1 C2 C4 C5 C6 C7 D1 D2 D3 D4 D6 D7 E2 E6 E7 F2 F3 F4 F5 F6 F7 G3 G4 G6 " if [ $(echo $pins | wc -w) -ne 35 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-cm49_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-cm49_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-cm49 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-cm49.mk set -ex make -f pinloc-1k-cm49.mk -j4 python3 ../pinlocdb.py pinloc-1k-cm49_*.exp > ../pinloc-1k-cm49.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-cm81.sh000066400000000000000000000020251276746530600242330ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-cm81 cd pinloc-1k-cm81 pins=" A1 A2 A3 A4 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C9 D1 D2 D3 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E7 E8 F1 F3 F7 F8 G1 G3 G4 G5 G6 G7 G8 G9 H1 H4 H5 H7 H9 J1 J2 J3 J4 J6 J7 J8 J9 " if [ $(echo $pins | wc -w) -ne 63 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-cm81_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-cm81_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-cm81 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-cm81.mk set -ex make -f pinloc-1k-cm81.mk -j4 python3 ../pinlocdb.py pinloc-1k-cm81_*.exp > ../pinloc-1k-cm81.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-qn84.sh000066400000000000000000000021431276746530600242560ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-qn84 cd pinloc-1k-qn84 pins=" A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A8 A9 B7 A10 B8 A11 B9 A12 A13 B10 B11 A14 B12 A16 B13 B14 A19 B15 A20 B17 A22 A23 B18 B19 A25 A26 B20 B21 A27 A29 B22 B23 A31 B24 A32 A33 A34 B26 A35 B27 A38 B29 A39 B30 A40 B31 A41 A43 B32 A44 A45 B34 A46 B35 A47 B36 A48 " if [ $(echo $pins | wc -w) -ne 67 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-qn84_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-qn84_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-qn84 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-qn84.mk set -ex make -f pinloc-1k-qn84.mk -j4 python3 ../pinlocdb.py pinloc-1k-qn84_*.exp > ../pinloc-1k-qn84.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-swg16tr.sh000066400000000000000000000016111276746530600250000ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-swg16tr cd pinloc-1k-swg16tr pins=" A2 A4 B1 B2 B3 C1 C2 C3 D1 D3 " if [ $(echo $pins | wc -w) -ne 10 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-swg16tr_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-swg16tr_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp1k-swg16tr bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-swg16tr.mk set -ex make -f pinloc-1k-swg16tr.mk -j4 python3 ../pinlocdb.py pinloc-1k-swg16tr_*.exp > ../pinloc-1k-swg16tr.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-tq144.sh000066400000000000000000000022221276746530600243370ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-tq144 cd pinloc-1k-tq144 pins=" 1 2 3 4 7 8 9 10 11 12 19 20 21 22 23 24 25 26 28 29 31 32 33 34 37 38 39 41 42 43 44 45 47 48 49 50 52 56 58 60 61 62 63 64 67 68 70 71 73 74 75 76 78 79 80 81 87 88 90 91 93 94 95 96 97 98 99 101 102 104 105 106 107 112 113 114 115 116 117 118 119 120 121 122 128 129 134 135 136 137 138 139 141 142 143 144 " if [ $(echo $pins | wc -w) -ne 96 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-tq144_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-tq144_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx1k-tq144 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-tq144.mk set -ex make -f pinloc-1k-tq144.mk -j4 python3 ../pinlocdb.py pinloc-1k-tq144_*.exp > ../pinloc-1k-tq144.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-1k-vq100.sh000066400000000000000000000020561276746530600243360ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-1k-vq100 cd pinloc-1k-vq100 pins=" 1 2 3 4 7 8 9 10 12 13 15 16 18 19 20 21 24 25 26 27 28 29 30 33 34 36 37 40 41 42 45 46 48 49 51 52 53 54 56 57 59 60 62 63 64 65 66 68 69 71 72 73 74 78 79 80 81 82 83 85 86 87 89 90 91 93 94 95 96 97 99 100 " if [ $(echo $pins | wc -w) -ne 72 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-1k-vq100_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-1k-vq100_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx1k-vq100 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-1k-vq100.mk set -ex make -f pinloc-1k-vq100.mk -j4 python3 ../pinlocdb.py pinloc-1k-vq100_*.exp > ../pinloc-1k-vq100.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-4k-cb132.sh000066400000000000000000000022441276746530600243030ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-4k-cb132 cd pinloc-4k-cb132 pins=" A1 A2 A3 A4 A5 A6 A7 A10 A11 A12 B1 B14 C1 C3 C4 C5 C6 C7 C9 C10 C11 C12 C14 D1 D3 D4 D5 D6 D7 D9 D10 D11 D12 D14 E1 E4 E11 E12 E14 F3 F4 F11 F12 F14 G1 G3 G4 G11 G12 G14 H1 H3 H4 H11 H12 J1 J3 J11 J12 K3 K4 K11 K12 K14 L1 L4 L5 L6 L8 L9 L12 L14 M1 M3 M4 M6 M7 M9 M11 M12 N1 N14 P1 P2 P3 P4 P5 P7 P8 P9 P10 P11 P12 P13 P14 " if [ $(echo $pins | wc -w) -ne 95 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-4k-cb132_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-4k-cb132_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx4k-cb132 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-4k-cb132.mk set -ex make -f pinloc-4k-cb132.mk -j4 python3 ../pinlocdb.py pinloc-4k-cb132_*.exp > ../pinloc-4k-cb132.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-4k-cm121.sh000066400000000000000000000022151276746530600243120ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-4k-cm121 cd pinloc-4k-cm121 pins=" A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B11 C1 C2 C3 C4 C7 C8 C9 C11 D1 D2 D3 D5 D7 D9 D10 D11 E1 E2 E3 E8 E9 E10 E11 F1 F2 F3 F4 F9 F10 F11 G1 G2 G3 G8 G9 G10 G11 H1 H2 H3 H7 H9 H10 H11 J1 J2 J3 J4 J5 J7 J8 J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K9 K10 K11 L1 L2 L3 L4 L5 L7 L8 L10 " if [ $(echo $pins | wc -w) -ne 93 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-4k-cm121_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-4k-cm121_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp4k-cm121 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-4k-cm121.mk set -ex make -f pinloc-4k-cm121.mk -j4 python3 ../pinlocdb.py pinloc-4k-cm121_*.exp > ../pinloc-4k-cm121.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-4k-cm225.sh000066400000000000000000000026401276746530600243210ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-4k-cm225 cd pinloc-4k-cm225 pins=" A1 A2 A5 A6 A7 A8 A9 A11 A15 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 G2 G4 G5 G10 G11 G12 G13 G14 G15 H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 J1 J2 J3 J4 J5 J10 J11 J12 J14 J15 K1 K4 K5 K9 K11 K12 K13 K15 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M15 N2 N3 N4 N5 N6 N7 N9 N10 N12 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 " if [ $(echo $pins | wc -w) -ne 167 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-4k-cm225_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-4k-cm225_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp4k-cm225 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-4k-cm225.mk set -ex make -f pinloc-4k-cm225.mk -j4 python3 ../pinlocdb.py pinloc-4k-cm225_*.exp > ../pinloc-4k-cm225.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-4k-cm81.sh000066400000000000000000000020251276746530600242360ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-4k-cm81 cd pinloc-4k-cm81 pins=" A1 A2 A3 A4 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C9 D1 D2 D3 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E7 E8 F1 F3 F7 F8 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H4 H5 H7 H9 J1 J2 J3 J4 J8 J9 " if [ $(echo $pins | wc -w) -ne 63 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-4k-cm81_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-4k-cm81_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp4k-cm81 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-4k-cm81.mk set -ex make -f pinloc-4k-cm81.mk -j4 python3 ../pinlocdb.py pinloc-4k-cm81_*.exp > ../pinloc-4k-cm81.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-4k-tq144.sh000066400000000000000000000022701276746530600243450ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-4k-tq144 cd pinloc-4k-tq144 pins=" 1 2 3 4 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 26 28 29 31 32 33 34 37 38 39 41 42 43 44 45 47 48 49 52 55 56 60 61 62 63 64 67 68 70 71 73 74 75 76 78 79 80 81 82 83 84 85 87 88 90 91 93 94 95 96 97 98 99 101 102 104 105 106 107 110 112 113 114 115 116 117 118 119 120 121 122 124 125 128 129 130 134 135 136 137 138 139 141 142 143 144 " if [ $(echo $pins | wc -w) -ne 107 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-4k-tq144_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-4k-tq144_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx4k-tq144 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-4k-tq144.mk set -ex make -f pinloc-4k-tq144.mk -j4 python3 ../pinlocdb.py pinloc-4k-tq144_*.exp > ../pinloc-4k-tq144.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-8k-cb132.sh000066400000000000000000000022441276746530600243070ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-8k-cb132 cd pinloc-8k-cb132 pins=" A1 A2 A3 A4 A5 A6 A7 A10 A11 A12 B1 B14 C1 C3 C4 C5 C6 C7 C9 C10 C11 C12 C14 D1 D3 D4 D5 D6 D7 D9 D10 D11 D12 D14 E1 E4 E11 E12 E14 F3 F4 F11 F12 F14 G1 G3 G4 G11 G12 G14 H1 H3 H4 H11 H12 J1 J3 J11 J12 K3 K4 K11 K12 K14 L1 L4 L5 L6 L8 L9 L12 L14 M1 M3 M4 M6 M7 M9 M11 M12 N1 N14 P1 P2 P3 P4 P5 P7 P8 P9 P10 P11 P12 P13 P14 " if [ $(echo $pins | wc -w) -ne 95 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-8k-cb132_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-8k-cb132_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx8k-cb132 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-8k-cb132.mk set -ex make -f pinloc-8k-cb132.mk -j4 python3 ../pinlocdb.py pinloc-8k-cb132_*.exp > ../pinloc-8k-cb132.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-8k-cm121.sh000066400000000000000000000022151276746530600243160ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-8k-cm121 cd pinloc-8k-cm121 pins=" A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B11 C1 C2 C3 C4 C7 C8 C9 C11 D1 D2 D3 D5 D7 D9 D10 D11 E1 E2 E3 E8 E9 E10 E11 F1 F2 F3 F4 F9 F10 F11 G1 G2 G3 G8 G9 G10 G11 H1 H2 H3 H7 H9 H10 H11 J1 J2 J3 J4 J5 J7 J8 J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K9 K10 K11 L1 L2 L3 L4 L5 L7 L8 L10 " if [ $(echo $pins | wc -w) -ne 93 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-8k-cm121_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-8k-cm121_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp8k-cm121 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-8k-cm121.mk set -ex make -f pinloc-8k-cm121.mk -j4 python3 ../pinlocdb.py pinloc-8k-cm121_*.exp > ../pinloc-8k-cm121.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-8k-cm225.sh000066400000000000000000000030111276746530600243160ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-8k-cm225 cd pinloc-8k-cm225 # Note: pin locations for hx8k-cm225 and lp8k-cm225 are identical pins=" A1 A2 A5 A6 A7 A8 A9 A10 A11 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 G15 H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 J15 K1 K3 K4 K5 K9 K11 K12 K13 K14 K15 L1 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M14 M15 N2 N3 N4 N5 N6 N7 N9 N10 N12 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 " if [ $(echo $pins | wc -w) -ne 178 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-8k-cm225_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-8k-cm225_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx8k-cm225 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-8k-cm225.mk set -ex make -f pinloc-8k-cm225.mk -j4 python3 ../pinlocdb.py pinloc-8k-cm225_*.exp > ../pinloc-8k-cm225.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-8k-cm81.sh000066400000000000000000000020251276746530600242420ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-8k-cm81 cd pinloc-8k-cm81 pins=" A1 A2 A3 A4 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C9 D1 D2 D3 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E7 E8 F1 F3 F7 F8 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H4 H5 H7 H9 J1 J2 J3 J4 J8 J9 " if [ $(echo $pins | wc -w) -ne 63 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-8k-cm81_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-8k-cm81_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=lp8k-cm81 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-8k-cm81.mk set -ex make -f pinloc-8k-cm81.mk -j4 python3 ../pinlocdb.py pinloc-8k-cm81_*.exp > ../pinloc-8k-cm81.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinloc-8k-ct256.sh000066400000000000000000000035511276746530600243420ustar00rootroot00000000000000#!/bin/bash mkdir -p pinloc-8k-ct256 cd pinloc-8k-ct256 pins=" A1 A2 A5 A6 A7 A9 A10 A11 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 D16 E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 E16 F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 H16 J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 J15 J16 K1 K3 K4 K5 K9 K11 K12 K13 K14 K15 K16 L1 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 L14 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M14 M15 M16 N2 N3 N4 N5 N6 N7 N9 N10 N12 N16 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 R16 T1 T2 T3 T5 T6 T7 T8 T9 T10 T11 T13 T14 T15 T16 " if [ $(echo $pins | wc -w) -ne 206 ]; then echo "Incorrect number of pins:" $(echo $pins | wc -w) exit 1 fi { echo -n "all:" for pin in $pins; do id="pinloc-8k-ct256_${pin}" echo -n " ${id}.exp" done echo for pin in $pins; do id="pinloc-8k-ct256_${pin}" echo "module top(output y); assign y = 0; endmodule" > ${id}.v echo "set_io y ${pin}" >> ${id}.pcf echo; echo "${id}.exp:" echo " ICEDEV=hx8k-ct256 bash ../../icecube.sh ${id} > ${id}.log 2>&1" echo " ../../../icebox/icebox_explain.py ${id}.asc > ${id}.exp.new" echo " ! grep '^Warning: pin' ${id}.log" echo " rm -rf ${id}.tmp" echo " mv ${id}.exp.new ${id}.exp" done } > pinloc-8k-ct256.mk set -ex make -f pinloc-8k-ct256.mk -j4 python3 ../pinlocdb.py pinloc-8k-ct256_*.exp > ../pinloc-8k-ct256.txt fpga-icestorm-0~20160913git266e758/icefuzz/pinloc/pinlocdb.py000066400000000000000000000021261276746530600235020ustar00rootroot00000000000000#!/usr/bin/env python3 import re from sys import argv ieren_db = [ ] pinloc_db = [ ] for arg in argv[1:]: pin = re.search(r"_([^.]*)", arg).group(1) with open(arg, "r") as f: tile = [0, 0] iob = [0, 0, 0] ioctrl = [0, 0, 0] for line in f: match = re.match(r"^\.io_tile (\d+) (\d+)", line) if match: tile = [int(match.group(1)), int(match.group(2))] match = re.match(r"^IOB_(\d+)", line) if match: iob = tile + [int(match.group(1))] match = re.match(r"^IoCtrl REN_(\d+)", line) if match: ioctrl = tile + [int(match.group(1))] ieren_db.append(tuple(iob + ioctrl)) pinloc_db.append(tuple(['"' + pin + '"'] + iob)) print() print("# ieren_db") for entry in sorted(ieren_db): print(" (%2d, %2d, %d, %2d, %2d, %d)," % entry) print() print("# pinloc_db") for entry in sorted(pinloc_db, key=lambda n: re.sub(r"[0-9]+", lambda d: "%03d" % int(d.group(0)), n[0])): print(" (%5s, %2d, %2d, %d)," % entry) print() fpga-icestorm-0~20160913git266e758/icefuzz/runloop.sh000066400000000000000000000011171276746530600221030ustar00rootroot00000000000000#!/bin/bash i=0 while true; do echo; git diff cached_*.txt | diffstat echo; echo -n "[$(date '+%H:%M:%S')] Iteration $(( ++i )) " { echo; echo; echo; echo; echo; echo; echo "Iteration $i"; date; } >> runloop.log if make clean > >( gawk '{ print >> "runloop.log"; printf("x"); fflush(""); }'; ) 2>&1 && make -j6 > >( gawk '{ print >> "runloop.log"; printf("m"); fflush(""); }'; ) 2>&1 && make -j6 check > >( gawk '{ print >> "runloop.log"; if (NR % 100 == 0) printf("c"); fflush(""); }'; ) 2>&1 then echo -n " OK" else echo " ERROR"; echo tail runloop.log exit 1 fi done fpga-icestorm-0~20160913git266e758/icefuzz/tests/000077500000000000000000000000001276746530600212135ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icefuzz/tests/all_luts_ffff.bin000066400000000000000000000770531276746530600245270ustar00rootroot00000000000000LatticeiCEcube2 2014.08.26723Part: iCE40HX1K-TQ144Date: Mar 5 2015 17:24:04~~Q bKr@@@@s ??@@C4  ??  ??  ?(?@  ? ?  ??  ??4  ??  ??@@ 4  ??<  ??  ?(?  ? ?  ??  ??  ??  ??@@@C4  ??  ??  ?h?@  ? ?  ??  ?? (??s  ??@@ 4  ??  ??  ?h?@  ? ?  ??  ??  ?? ?@@C4  ??  ??  ?h?  ? ?  ??  ??  ??s ??@C4  ??  ??  ?(?  ? ?  ??  ?? @ ??4  ??@@@ 4  ??  ??  ?(?  ? ?  ??  ??  ?? s ??@   ??  ??  ??  ? ?  ?(?  ??  ??@@@@?? ?? ?? ?? ? ?h( ?? ?? 44?@? ?? ?? ?? ?? ?@ ?(( ?? ?? 44?@?s ?? ?? ?@? ?? ?0?( ?? ?? C4?? ?? ?? ?@? ?? ?@ ?h ?@? ??$4???? ??  ??  ?? ? ? ?? ?? ?@?s ?? ?? ?? ?? ? ?(( ?? ?? 44?@? ?? ?? ?? ?? ? ?(( ?? ?? 44?@?s ?? ?? ?? ?? ? ?(( ?? ?? 44?@?     @??@  ,???@?L??@?`??@P???@ ???@???@?`??@???@  ,???@???@?@??@ ???@ ???@X???@???@???@  ,???@???@?@??@P???@ ???@???@???@p???8  ???@???@?@??@???@ ???@X???@???@???@  ,???@???@?@??@P???@ ???@???@??????@  ,???@???@???@P ???@ ?`??@???@???@???@  $???@???@?@??@X???@ ???@???@???@???8  ???@???@?`??@???@ ???@X???@???@?    ??@???@???@???@??? @`???@???@?,?? @???@???@???@X???@? ?? @X@???@???@?,?? @???@???@???@???@??? @PX@???@???p@?,?? @??? @P???@???@X`???@? ?? @???@???@?,?? @???@0???@???@`???@???@PP???@???@?,?? @???@???@???@X???@? ?? @X`???@???@?,??@???@???@???@? ??@??? @PX@? ??@???@?,??@???@???@???@`???@? ?? @???@x???@?,?? @?b?r"fpga-icestorm-0~20160913git266e758/icefuzz/tests/bitop.pcf000066400000000000000000000000461276746530600230220ustar00rootroot00000000000000set_io a 1 set_io b 10 set_io y 11 fpga-icestorm-0~20160913git266e758/icefuzz/tests/bitop.v000066400000000000000000000001011276746530600225070ustar00rootroot00000000000000module top (input a, b, output y); assign y = a & b; endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/bram.pcf000066400000000000000000000000251276746530600226230ustar00rootroot00000000000000set_location ram 3 1 fpga-icestorm-0~20160913git266e758/icefuzz/tests/bram.v000066400000000000000000000034521276746530600223270ustar00rootroot00000000000000module top ( input clk, input [15:0] wdata, output [15:0] rdata, input [7:0] addr ); SB_RAM40_4K #( .WRITE_MODE(0), .READ_MODE(0) ) ram ( .RDATA(rdata), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(1'b1), .MASK(16'b0) ); defparam ram.INIT_0 = 256'h123456789abcdef00000dddd0000eeee00000012483569ac0111044400000001; defparam ram.INIT_1 = 256'h56789abcdef123400000dddd0000eeee00000012483569ac0111044401000002; defparam ram.INIT_2 = 256'habcdef12345678900000dddd0000eeee00000012483569ac0111044402000004; defparam ram.INIT_3 = 256'h00000000000000000000dddd0000eeee00000012483569ac0111044403000008; defparam ram.INIT_4 = 256'hffff000022220000444400006666000088880012483569ac0111044404000010; defparam ram.INIT_5 = 256'hffff000022220000444400006666000088880012483569ac0111044405000020; defparam ram.INIT_6 = 256'hffff000022220000444400006666000088880012483569ac0111044406000040; defparam ram.INIT_7 = 256'hffff000022220000444400006666000088880012483569ac0111044407000080; defparam ram.INIT_8 = 256'h0000111100003333000055550000777700000012483569ac0111044408000100; defparam ram.INIT_9 = 256'h0000111100003333000055550000777700000012483569ac0111044409000200; defparam ram.INIT_A = 256'h0000111100003333000055550000777700000012483569ac011104440a000400; defparam ram.INIT_B = 256'h0000111100003333000055550000777700000012483569ac011104440b000800; defparam ram.INIT_C = 256'h0123000099990000aaaa0000bbbb0000cccc0012483569ac011104440c001000; defparam ram.INIT_D = 256'h4567000099990000aaaa0000bbbb0000cccc0012483569ac011104440d002000; defparam ram.INIT_E = 256'h89ab000099990000aaaa0000bbbb0000cccc0012483569ac011104440e004000; defparam ram.INIT_F = 256'hcdef000099990000aaaa0000bbbb0000cccc0012483569ac011104440f008000; endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/carry.v000066400000000000000000000001661276746530600225250ustar00rootroot00000000000000module top (input a, b, ci, output co); SB_CARRY carry_cell ( .I0(a), .I1(b), .CI(ci), .CO(co) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf.py000066400000000000000000000012001276746530600230300ustar00rootroot00000000000000#!/usr/bin/env python3 import fileinput colbuf_tile = None glbnet_tile = None for line in fileinput.input(): line = line.split() if len(line) == 0: continue if line[0] in [".io_tile", ".logic_tile", ".ramb_tile", ".ramt_tile"]: current_tile = (int(line[1]), int(line[2])) if line[0] == "ColBufCtrl": assert colbuf_tile is None colbuf_tile = current_tile if line[0] == "buffer" and line[1].startswith("glb_netwk_"): assert glbnet_tile is None glbnet_tile = current_tile print("(%2d, %2d, %2d, %2d)," % (colbuf_tile[0], colbuf_tile[1], glbnet_tile[0], glbnet_tile[1])) fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf.sh000066400000000000000000000027221276746530600230240ustar00rootroot00000000000000#!/bin/bash # for f in colbuf_io.work/*.exp colbuf_logic.work/*.exp colbuf_ram.work/*.exp; do # python3 colbuf.py $f # done | sort -u > colbuf.txt get_colbuf_data() { # tr -d '(,)' < colbuf.txt for x in {0..2} {4..9} {11..13}; do echo $x 4 $x 0 echo $x 5 $x 8 echo $x 12 $x 9 echo $x 13 $x 17 done for x in 3 10; do echo $x 3 $x 0 echo $x 3 $x 4 echo $x 5 $x 8 echo $x 11 $x 9 echo $x 11 $x 12 echo $x 13 $x 17 done } { echo "" for x in {1..13}; do echo "" done for y in {1..17}; do echo "" done for x in {0..13}; do echo "$x" done for y in {0..17}; do echo "$y" done while read x1 y1 x2 y2; do echo "" done < <( get_colbuf_data; ) while read x1 y1 x2 y2; do echo "" done < <( get_colbuf_data; ) echo "" } > colbuf.svg fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf_8k.sh000066400000000000000000000032401276746530600234220ustar00rootroot00000000000000#!/bin/bash for f in colbuf_io_8k.work/*.exp colbuf_logic_8k.work/*.exp colbuf_ram_8k.work/*.exp; do echo $f >&2 python3 colbuf.py $f done | sort -u > colbuf_8k.txt get_colbuf_data() { tr -d '(,)' < colbuf_8k.txt # for x in {0..2} {4..9} {11..13}; do # echo $x 4 $x 0 # echo $x 5 $x 8 # echo $x 12 $x 9 # echo $x 13 $x 17 # done # for x in 3 10; do # echo $x 3 $x 0 # echo $x 3 $x 4 # echo $x 5 $x 8 # echo $x 11 $x 9 # echo $x 11 $x 12 # echo $x 13 $x 17 # done } { echo "" for x in {1..33}; do echo "" done for y in {1..33}; do echo "" done for x in {0..33}; do echo "$x" done for y in {0..33}; do echo "$y" done while read x1 y1 x2 y2; do echo "" done < <( get_colbuf_data; ) while read x1 y1 x2 y2; do echo "" done < <( get_colbuf_data; ) while read x1 y1 x2 y2; do echo "" done < <( get_colbuf_data; ) echo "" } > colbuf_8k.svg fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf_io.sh000066400000000000000000000016511276746530600235130ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p colbuf_io.work cd colbuf_io.work glb_pins="93 21 128 50 20 94 49 129" pins=" 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34 37 38 41 42 43 44 45 47 48 52 56 58 60 61 62 63 64 73 74 75 76 78 79 80 81 87 88 90 91 95 96 97 98 101 102 104 105 106 107 112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144 " pins="$( echo $pins )" for pin in $pins; do pf="colbuf_io_$pin" gpin=$( echo $glb_pins | tr ' ' '\n' | grep -v $pin | sort -R | head -n1; ) cat > ${pf}.v <<- EOT module top (input clk, data, output pin); SB_IO #( .PIN_TYPE(6'b 0101_00) ) pin_obuf ( .PACKAGE_PIN(pin), .OUTPUT_CLK(clk), .D_OUT_0(data) ); endmodule EOT echo "set_io pin $pin" > ${pf}.pcf echo "set_io clk $gpin" >> ${pf}.pcf bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 ../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp rm -rf ${pf}.tmp done fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf_io_8k.sh000066400000000000000000000033061276746530600241140ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p colbuf_io_8k.work cd colbuf_io_8k.work glb_pins="C8 F7 G1 H11 H16 J3 K9 R9" pins=" A1 A2 A5 A6 A7 A9 A10 A11 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 D16 E2 E3 E4 E5 E6 E9 E10 E11 E13 E14 E16 F1 F2 F3 F4 F5 F7 F9 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H11 H12 H13 H14 H16 J1 J2 J3 J4 J5 J10 J11 J12 J13 J14 J15 J16 K1 K3 K4 K5 K9 K11 K12 K13 K14 K15 K16 L1 L3 L4 L5 L6 L7 L9 L10 L11 L12 L13 L14 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M11 M12 M13 M14 M15 M16 N2 N3 N4 N5 N6 N7 N9 N10 N12 N16 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R9 R10 R11 R12 R14 R15 R16 T1 T2 T3 T5 T6 T7 T8 T9 T10 T11 T13 T14 T15 T16 " pins="$( echo $pins )" for pin in $pins; do pf="colbuf_io_8k_$pin" gpin=$( echo $glb_pins | tr ' ' '\n' | grep -v $pin | sort -R | head -n1; ) cat > ${pf}.v <<- EOT module top (input clk, data, output pin); SB_IO #( .PIN_TYPE(6'b 0101_00) ) pin_obuf ( .PACKAGE_PIN(pin), .OUTPUT_CLK(clk), .D_OUT_0(data) ); endmodule EOT echo "set_io pin $pin" > ${pf}.pcf echo "set_io clk $gpin" >> ${pf}.pcf ICEDEV=hx8k-ct256 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 ../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp rm -rf ${pf}.tmp done fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf_logic.sh000066400000000000000000000011261276746530600241760ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p colbuf_logic.work cd colbuf_logic.work glb_pins="93 21 128 50 20 94 49 129" for x in 1 2 {4..9} 11 12; do for y in {1..16}; do pf="colbuf_logic_${x}_${y}" gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; ) cat > ${pf}.v <<- EOT module top (input c, d, output q); SB_DFF dff ( .C(c), .D(d), .Q(q) ); endmodule EOT echo "set_location dff $x $y 0" > ${pf}.pcf echo "set_io c $gpin" >> ${pf}.pcf bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 ../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp rm -rf ${pf}.tmp done; done fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf_logic_8k.sh000066400000000000000000000011701276746530600245770ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p colbuf_logic_8k.work cd colbuf_logic_8k.work glb_pins="C8 F7 G1 H11 H16 J3 K9 R9" for x in {1..7} {9..24} {26..32}; do for y in {1..32}; do pf="colbuf_logic_8k_${x}_${y}" gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; ) cat > ${pf}.v <<- EOT module top (input c, d, output q); SB_DFF dff ( .C(c), .D(d), .Q(q) ); endmodule EOT echo "set_location dff $x $y 0" > ${pf}.pcf echo "set_io c $gpin" >> ${pf}.pcf ICEDEV=hx8k-ct256 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 ../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp rm -rf ${pf}.tmp done; done fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf_ram.sh000066400000000000000000000022201276746530600236540ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p colbuf_ram.work cd colbuf_ram.work glb_pins="93 21 128 50 20 94 49 129" for x in 3 10; do for y in {1..16}; do pf="colbuf_ram_${x}_${y}" gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; ) if [ $((y % 2)) == 1 ]; then clkport="WCLK" other_clkport="RCLK" else clkport="RCLK" other_clkport="WCLK" fi cat > ${pf}.v <<- EOT module top (input c, oc, input [1:0] d, output [1:0] q); wire gc; SB_GB_IO #( .PIN_TYPE(6'b 0000_00), .PULLUP(1'b0), .NEG_TRIGGER(1'b0), .IO_STANDARD("SB_LVCMOS") ) gbuf ( .PACKAGE_PIN(c), .GLOBAL_BUFFER_OUTPUT(gc) ); SB_RAM40_4K #( .READ_MODE(3), .WRITE_MODE(3) ) ram40 ( .WADDR(11'b0), .RADDR(11'b0), .$clkport(gc), .$other_clkport(oc), .RDATA(q), .WDATA(d), .WE(1'b1), .WCLKE(1'b1), .RE(1'b1), .RCLKE(1'b1) ); endmodule EOT echo "set_location ram40 $x $((y - (1 - y%2))) 0" > ${pf}.pcf echo "set_io oc 1" >> ${pf}.pcf echo "set_io c $gpin" >> ${pf}.pcf bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 ../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp rm -rf ${pf}.tmp done; done fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbuf_ram_8k.sh000066400000000000000000000022531276746530600242640ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p colbuf_ram_8k.work cd colbuf_ram_8k.work glb_pins="C8 F7 G1 H11 H16 J3 K9 R9" for x in 8 25; do for y in {1..32}; do pf="colbuf_ram_8k_${x}_${y}" gpin=$( echo $glb_pins | tr ' ' '\n' | sort -R | head -n1; ) if [ $((y % 2)) == 1 ]; then clkport="WCLK" other_clkport="RCLK" else clkport="RCLK" other_clkport="WCLK" fi cat > ${pf}.v <<- EOT module top (input c, oc, input [1:0] d, output [1:0] q); wire gc; SB_GB_IO #( .PIN_TYPE(6'b 0000_00), .PULLUP(1'b0), .NEG_TRIGGER(1'b0), .IO_STANDARD("SB_LVCMOS") ) gbuf ( .PACKAGE_PIN(c), .GLOBAL_BUFFER_OUTPUT(gc) ); SB_RAM40_4K #( .READ_MODE(3), .WRITE_MODE(3) ) ram40 ( .WADDR(11'b0), .RADDR(11'b0), .$clkport(gc), .$other_clkport(oc), .RDATA(q), .WDATA(d), .WE(1'b1), .WCLKE(1'b1), .RE(1'b1), .RCLKE(1'b1) ); endmodule EOT echo "set_location ram40 $x $((y - (1 - y%2))) 0" > ${pf}.pcf echo "set_io oc 1" >> ${pf}.pcf echo "set_io c $gpin" >> ${pf}.pcf ICEDEV=hx8k-ct256 bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 ../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp rm -rf ${pf}.tmp done; done fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbufs.pcf000066400000000000000000000004071276746530600233430ustar00rootroot00000000000000# set_io clk[0] J3 # set_io clk[1] G1 # set_io clk[2] R9 # set_io clk[3] F7 # set_io clk[4] K9 # set_io clk[5] C8 # set_io clk[6] H11 # set_io clk[7] H16 set_io clk[0] H16 set_location bitslice[0].ram40_upper 8 11 0 set_location bitslice[0].ram40_lower 25 5 0 fpga-icestorm-0~20160913git266e758/icefuzz/tests/colbufs.v000066400000000000000000000016541276746530600230450ustar00rootroot00000000000000module top #( parameter NUM_BITS = 1 ) ( input [NUM_BITS-1:0] clk, output [NUM_BITS-1:0] y ); wire [NUM_BITS-1:0] t1, t2, t3; genvar i; generate for (i = 0; i < NUM_BITS; i = i+1) begin:bitslice SB_RAM40_4K #( .READ_MODE(0), .WRITE_MODE(0) ) ram40_upper ( .WADDR(8'b0), .RADDR(8'b0), .MASK(~16'b0), .WDATA(8'b0), .RDATA(t1[i]), .WE(1'b1), .WCLKE(1'b1), .WCLK(clk[i]), .RE(1'b1), .RCLKE(1'b1), .RCLK(clk[i]) ); SB_RAM40_4K #( .READ_MODE(0), .WRITE_MODE(0) ) ram40_lower ( .WADDR(8'b0), .RADDR(8'b0), .MASK(~16'b0), .WDATA(8'b0), .RDATA(t2[i]), .WE(1'b1), .WCLKE(1'b1), .WCLK(clk[i]), .RE(1'b1), .RCLKE(1'b1), .RCLK(clk[i]) ); SB_DFF dff ( .C(clk[i]), .D(t1[i] ^ t2[i]), .Q(t3[i]) ); SB_IO #( .PIN_TYPE(6'b 0101_01) ) out ( .PACKAGE_PIN(y[i]), .OUTPUT_CLK(clk[i]), .D_OUT_0(t3[i]) ); end endgenerate endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/cross_0.pcf000066400000000000000000000003441276746530600232560ustar00rootroot00000000000000 # row 14, block 0 set_io in_left 2 set_io out_right 104 # row 4, block 0 set_io out_left 29 set_io in_right 79 # col 4, block 0 set_io in_bottom 44 set_io out_top 137 # col 8, block 0 set_io out_bottom 58 set_io in_top 121 fpga-icestorm-0~20160913git266e758/icefuzz/tests/cross_0.v000066400000000000000000000003541276746530600227540ustar00rootroot00000000000000module top ( input in_left, in_right, in_top, in_bottom, output out_left, out_right, out_top, out_bottom ); assign out_left = in_right; assign out_right = in_left; assign out_top = in_bottom; assign out_bottom = in_top; endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_hx8kboard.pcf000066400000000000000000000002171276746530600253120ustar00rootroot00000000000000set_io LED0 B5 set_io LED1 B4 set_io LED2 A2 set_io LED3 A1 set_io LED4 C5 set_io LED5 C4 set_io LED6 B3 set_io LED7 C3 set_io clk J3 fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_hx8kboard.sdc000066400000000000000000000000751276746530600253150ustar00rootroot00000000000000create_clock -period 10.00 -name {top|clk} [get_ports {clk}] fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_hx8kboard.sh000066400000000000000000000001051276746530600251500ustar00rootroot00000000000000#!/bin/bash ICEDEV=hx8k-ct256 bash ../icecube.sh example_hx8kboard.v fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_hx8kboard.v000066400000000000000000000037201276746530600250110ustar00rootroot00000000000000module top ( input clk, output LED0, output LED1, output LED2, output LED3, output LED4, output LED5, output LED6, output LED7 ); reg [31:0] counter = 0; wire [7:0] raddr = counter >> 22; always @(posedge clk) counter <= counter + 1; // Python 3 code for memory initialization: // // queue = list() // for i in range(256): // queue.append("%04x" % (i ^ (i >> 1))) // if i % 16 == 15: // print("256'h%s" % "".join(reversed(queue))) // queue = list() SB_RAM40_4K #( .READ_MODE(0), .WRITE_MODE(0), .INIT_0(256'h00080009000b000a000e000f000d000c00040005000700060002000300010000), .INIT_1(256'h00100011001300120016001700150014001c001d001f001e001a001b00190018), .INIT_2(256'h00380039003b003a003e003f003d003c00340035003700360032003300310030), .INIT_3(256'h00200021002300220026002700250024002c002d002f002e002a002b00290028), .INIT_4(256'h00680069006b006a006e006f006d006c00640065006700660062006300610060), .INIT_5(256'h00700071007300720076007700750074007c007d007f007e007a007b00790078), .INIT_6(256'h00580059005b005a005e005f005d005c00540055005700560052005300510050), .INIT_7(256'h00400041004300420046004700450044004c004d004f004e004a004b00490048), .INIT_8(256'h00c800c900cb00ca00ce00cf00cd00cc00c400c500c700c600c200c300c100c0), .INIT_9(256'h00d000d100d300d200d600d700d500d400dc00dd00df00de00da00db00d900d8), .INIT_A(256'h00f800f900fb00fa00fe00ff00fd00fc00f400f500f700f600f200f300f100f0), .INIT_B(256'h00e000e100e300e200e600e700e500e400ec00ed00ef00ee00ea00eb00e900e8), .INIT_C(256'h00a800a900ab00aa00ae00af00ad00ac00a400a500a700a600a200a300a100a0), .INIT_D(256'h00b000b100b300b200b600b700b500b400bc00bd00bf00be00ba00bb00b900b8), .INIT_E(256'h00980099009b009a009e009f009d009c00940095009700960092009300910090), .INIT_F(256'h00800081008300820086008700850084008c008d008f008e008a008b00890088) ) ram ( .RADDR(raddr), .RDATA({LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7}), .RE(1'b1), .RCLKE(1'b1), .RCLK(clk) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_icestick.pcf000066400000000000000000000001371276746530600252170ustar00rootroot00000000000000set_io LED1 99 set_io LED2 98 set_io LED3 97 set_io LED4 96 set_io LED5 95 set_io clk 21 fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_icestick.sdc000066400000000000000000000000751276746530600252210ustar00rootroot00000000000000create_clock -period 10.00 -name {top|clk} [get_ports {clk}] fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_icestick.sh000066400000000000000000000000621276746530600250560ustar00rootroot00000000000000#!/bin/bash bash ../icecube.sh example_icestick.v fpga-icestorm-0~20160913git266e758/icefuzz/tests/example_icestick.v000066400000000000000000000010001276746530600247020ustar00rootroot00000000000000module top ( input clk, output LED1, output LED2, output LED3, output LED4, output LED5 ); localparam BITS = 5; localparam LOG2DELAY = 22; function [BITS-1:0] bin2gray(input [BITS-1:0] in); integer i; reg [BITS:0] temp; begin temp = in; for (i=0; i> LOG2DELAY); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/icegate.pcf000066400000000000000000000001141276746530600233020ustar00rootroot00000000000000set_io din_0 33 set_io global 97 set_io latch_in 112 set_io pin_gb_io 0 9 0 fpga-icestorm-0~20160913git266e758/icefuzz/tests/icegate.v000066400000000000000000000006021276746530600230010ustar00rootroot00000000000000module top ( inout pin, input latch_in, output din_0, output global ); SB_GB_IO #( .PIN_TYPE(6'b 0000_11), .PULLUP(1'b 0), .NEG_TRIGGER(1'b 0), .IO_STANDARD("SB_LVCMOS") ) \pin_gb_io ( .PACKAGE_PIN(pin), .LATCH_INPUT_VALUE(latch_in), .D_IN_0(din_0), .GLOBAL_BUFFER_OUTPUT(globals) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/io_glb_netwk.pcf000066400000000000000000000004011276746530600243430ustar00rootroot00000000000000set_io in 1 set_io out 2 set_io pin[0] 20 # padin_4 set_io pin[1] 21 # padin_1 set_io pin[2] 49 # padin_6 set_io pin[3] 50 # padin_3 set_io pin[4] 93 # padin_0 set_io pin[5] 94 # padin_5 set_io pin[6] 128 # padin_2 set_io pin[7] 129 # padin_7 fpga-icestorm-0~20160913git266e758/icefuzz/tests/io_glb_netwk.v000066400000000000000000000016011276746530600240430ustar00rootroot00000000000000module top ( inout [7:0] pin, input in, output out ); wire [7:0] glbl, clk; reg [7:0] q; SB_GB_IO #( .PIN_TYPE(6'b 0000_11), .PULLUP(1'b0), .NEG_TRIGGER(1'b0), .IO_STANDARD("SB_LVCMOS") ) PIO[7:0] ( .PACKAGE_PIN(pin), .LATCH_INPUT_VALUE(1'b1), .CLOCK_ENABLE(), .INPUT_CLK(), .OUTPUT_CLK(), .OUTPUT_ENABLE(), .D_OUT_0(), .D_OUT_1(), .D_IN_0(), .D_IN_1(), .GLOBAL_BUFFER_OUTPUT(glbl) ); assign clk[0] = glbl[0]; // glb_netwk_4 assign clk[1] = glbl[1]; // glb_netwk_1 assign clk[2] = glbl[2]; // glb_netwk_6 assign clk[3] = glbl[3]; // glb_netwk_3 assign clk[4] = glbl[4]; // glb_netwk_0 assign clk[5] = glbl[5]; // glb_netwk_5 assign clk[6] = glbl[6]; // glb_netwk_2 assign clk[7] = glbl[7]; // glb_netwk_7 genvar i; generate for (i = 0; i < 8; i=i+1) begin always @(posedge clk[i]) q[i] <= in; end endgenerate assign out = ^{q, in}; endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/io_latched.sh000066400000000000000000000013461276746530600236460ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p io_latched.work cd io_latched.work pins=" 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34 37 38 41 42 43 44 45 47 48 52 56 58 60 61 62 63 64 73 74 75 76 78 79 80 81 87 88 90 91 95 96 97 98 101 102 104 105 106 107 112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144 " pins="$( echo $pins )" for pin in $pins; do pf="io_latched_$pin" cp ../io_latched.v ${pf}.v read pin_latch pin_data < <( echo $pins | tr ' ' '\n' | grep -v $pin | sort -R; ) { echo "set_io pin $pin" echo "set_io latch_in $pin_latch" echo "set_io data_out $pin_data" } > ${pf}.pcf bash ../../icecube.sh ${pf}.v ../../../icebox/icebox_vlog.py -SP ${pf}.psb ${pf}.asc > ${pf}.ve done fpga-icestorm-0~20160913git266e758/icefuzz/tests/io_latched.v000066400000000000000000000005721276746530600235010ustar00rootroot00000000000000module top ( inout pin, input latch_in, output data_out ); SB_IO #( .PIN_TYPE(6'b0000_11), .PULLUP(1'b0), .NEG_TRIGGER(1'b0), .IO_STANDARD("SB_LVCMOS") ) pin_ibuf ( .PACKAGE_PIN(pin), .LATCH_INPUT_VALUE(latch_in), .CLOCK_ENABLE(), .INPUT_CLK(), .OUTPUT_CLK(), .OUTPUT_ENABLE(), .D_OUT_0(), .D_OUT_1(), .D_IN_0(data_out), .D_IN_1() ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/ioctrl.py000066400000000000000000000012451276746530600230630ustar00rootroot00000000000000#!/usr/bin/env python3 import fileinput for line in fileinput.input(): line = line.split() if len(line) == 0: continue if line[0] == ".io_tile": current_tile = (int(line[1]), int(line[2])) if line[0] == "IoCtrl" and line[1] == "REN_0": ren = (current_tile[0], current_tile[1], 0) if line[0] == "IoCtrl" and line[1] == "REN_1": ren = (current_tile[0], current_tile[1], 1) if line[0] == "IOB_0": iob = (current_tile[0], current_tile[1], 0) if line[0] == "IOB_1": iob = (current_tile[0], current_tile[1], 1) print("(%2d, %2d, %2d, %2d, %2d, %2d)," % (iob[0], iob[1], iob[2], ren[0], ren[1], ren[2])) fpga-icestorm-0~20160913git266e758/icefuzz/tests/ioctrl.sh000066400000000000000000000014231276746530600230430ustar00rootroot00000000000000#!/bin/bash set -ex mkdir -p ioctrl.work cd ioctrl.work pins=" 1 2 3 4 7 8 9 10 11 12 19 20 21 22 23 24 25 26 28 29 31 32 33 34 37 38 39 41 42 43 44 45 47 48 49 50 52 56 58 60 61 62 63 64 67 68 70 71 73 74 75 76 78 79 80 81 87 88 90 91 93 94 95 96 97 98 99 101 102 104 105 106 107 112 113 114 115 116 117 118 119 120 121 122 128 129 134 135 136 137 138 139 141 142 143 144 " pins="$( echo $pins )" for pin in $pins; do pf="ioctrl_$pin" echo "module top (output pin); assign pin = 1; endmodule" > ${pf}.v echo "set_io pin $pin" > ${pf}.pcf bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 ../../../icebox/icebox_explain.py ${pf}.asc > ${pf}.exp done set +x echo "--snip--" for pin in $pins; do python3 ../ioctrl.py ioctrl_${pin}.exp done | tee ioctrl_db.txt echo "--snap--" fpga-icestorm-0~20160913git266e758/icefuzz/tests/lut_cascade.pcf000066400000000000000000000001761276746530600241600ustar00rootroot00000000000000set_location dst_lut 6 8 2 # SB_LUT4 (LogicCell: dst_lut_LC_0) set_location src_lut 6 8 1 # SB_LUT4 (LogicCell: src_lut_LC_1) fpga-icestorm-0~20160913git266e758/icefuzz/tests/lut_cascade.v000066400000000000000000000004771276746530600236610ustar00rootroot00000000000000module top (input a, b, c, d, e, f, g, output y); wire cascade; SB_LUT4 #( .LUT_INIT(16'b 1100_1100_1100_1010) ) src_lut ( .O(cascade), .I0(a), .I1(b), .I2(c), .I3(d) ); SB_LUT4 #( .LUT_INIT(16'b 1000_0100_0010_0001) ) dst_lut ( .O(y), .I0(e), .I1(f), .I2(cascade), .I3(g) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/raminits.pcf000066400000000000000000000006561276746530600235420ustar00rootroot00000000000000set_location ram_0301 3 1 set_location ram_0303 3 3 set_location ram_0305 3 5 set_location ram_0307 3 7 set_location ram_0309 3 9 set_location ram_0311 3 11 set_location ram_0313 3 13 set_location ram_0315 3 15 set_location ram_1001 10 1 set_location ram_1003 10 3 set_location ram_1005 10 5 set_location ram_1007 10 7 set_location ram_1009 10 9 set_location ram_1011 10 11 set_location ram_1013 10 13 set_location ram_1015 10 15 fpga-icestorm-0~20160913git266e758/icefuzz/tests/raminits.v000066400000000000000000000720341276746530600232360ustar00rootroot00000000000000// tmpfiles/ex_00.v module top ( input clk, input [7:0] sel, input [15:0] wdata, output [15:0] rdata, input [7:0] addr ); wire [15:0] rdata_0301; SB_RAM256x16 ram_0301 ( .RDATA(rdata_0301), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 0), .MASK(16'b0) ); defparam ram_0301.INIT_0 = 256'heee7d4195b1ee583e83766c47c4279255c36fac37ffa2db1c7978834c0a7b756; defparam ram_0301.INIT_1 = 256'haf36df1852690a6f4bd5a70c8cdc7ace32570591bdc9da916fdfebbf250ee920; defparam ram_0301.INIT_2 = 256'h062ec86b566ae81511bdb1c797b09358fd7b8b55a4033809181a8590636ebc4a; defparam ram_0301.INIT_3 = 256'he5647bccd28fcd7e1175dd08c07eee22b5f7a76ce80b814acc913a8bf6272489; defparam ram_0301.INIT_4 = 256'h847367636b8515d939efbb8e215509b3639c2d42650023fde29a300331ea02dd; defparam ram_0301.INIT_5 = 256'h1bfed331fc20e7d3855f6f57b704e77098ad9921daa03a251a0d4750cfdb8c5c; defparam ram_0301.INIT_6 = 256'h5796d45e174c10a14c1c6296d8e71d33a2601b790ac8ace68483a4095b8b2f2c; defparam ram_0301.INIT_7 = 256'h5c02f2a5a09d26529a93bdc1c3b2dad1edbdba8729e3ba1447b96a823b5e6ddb; defparam ram_0301.INIT_8 = 256'he6c0da7b269cb3b8213608a7c38a5eb224f7d37981f337e1b1f4e4aa13a330bc; defparam ram_0301.INIT_9 = 256'hd8aab74a136340b43c44e69b99233b7657c1faf8795e6e6513e399eccf835d64; defparam ram_0301.INIT_A = 256'h76da9bfa7def43d27b289046765ebad19bd9853133aa79e7a4c53b489266b78b; defparam ram_0301.INIT_B = 256'hd0be66fe7f334ca37b5cfa6fcfb84f2b5d7b556e3b179da25cb20a4bcf285dbc; defparam ram_0301.INIT_C = 256'he36823bd57f798408173ee4e1a138496a319039e28f783015ad938818b1ffeef; defparam ram_0301.INIT_D = 256'h19ad3217524d84a9eed19f6a88a3e6f6f3e27c256534dcefe6721a2eaf27e104; defparam ram_0301.INIT_E = 256'hbb5e5ef9246e61ee24121f2169dc1d755429486f030b7ae134f83c35915a2f44; defparam ram_0301.INIT_F = 256'hf0b5e781fb75db80882e0641026b6c4df0e61dd31d84c2f44bbe7073ccad1d01; wire [15:0] rdata_0303; SB_RAM256x16 ram_0303 ( .RDATA(rdata_0303), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 1), .MASK(16'b0) ); defparam ram_0303.INIT_0 = 256'h2b668f5787aef8f5025f79512dcefc91d4bebc46513598e42c93d37c931d8923; defparam ram_0303.INIT_1 = 256'h7b9a84f2d5f65df84d4157495ab21e01e152dd7a886c33cb614e382e7fed9eab; defparam ram_0303.INIT_2 = 256'h878bdd512303597de1345a1cc680af906dabb3a7ad0ff50221288bce8af64881; defparam ram_0303.INIT_3 = 256'he36b5511c45aec1bba20d1791c3ccfa39cf93bde842f184cc1a93d70520529d6; defparam ram_0303.INIT_4 = 256'haf4b39a9fdfb42ccae9f2eea59845f5a8c2fb07035d64d71722f4d656b703c69; defparam ram_0303.INIT_5 = 256'h4c0cacce82085c0931587d9e7f4e6d074746cca6744b4a3b0ab1b54ec03fc84e; defparam ram_0303.INIT_6 = 256'he937cdb315288fbfdcaf1d77b698da022e5f6cf1b4fa3249d0d50eaf876466ae; defparam ram_0303.INIT_7 = 256'h1bd6d490c00964563d3f8438a32966a8f5de9447eae7b0e63dbf930d2dad4faa; defparam ram_0303.INIT_8 = 256'h55f0e909449d025ca05f81ffe6a71641b98694281522061a7d60fc84447395af; defparam ram_0303.INIT_9 = 256'h03cbdbbb3afb93d1360dc27ee9bc65b9dd407010717a2e5d5a2e6d7195875aef; defparam ram_0303.INIT_A = 256'hc8f9ceb334e4c22b1bfbd0321ab6762af2d10f9e67282aa4b3c0b4784c061708; defparam ram_0303.INIT_B = 256'h4a49021a4cf723dca9d9dba93f8ae9f3d5be64f54d61b5b40646bc8f11418390; defparam ram_0303.INIT_C = 256'hd579caee533c14990f0ef6e2307cbfd1252414b9384802fa7b434e40cc8b1f21; defparam ram_0303.INIT_D = 256'h17ff7be7f32b4e90a04b999795a68ecf923fd605ae58d82f9ddf78adfff85572; defparam ram_0303.INIT_E = 256'h41f8121524de634c0801dc5f8c04c8dec086b1f63d3e3a769c9cd63fd8132a72; defparam ram_0303.INIT_F = 256'h32d4549b468eba9a49fb496ff2d11b8e43d138b24a800e49853a6aba5bb5c5a2; wire [15:0] rdata_0305; SB_RAM256x16 ram_0305 ( .RDATA(rdata_0305), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 2), .MASK(16'b0) ); defparam ram_0305.INIT_0 = 256'h172521cfcd66a4e54fdd281bea4e877d13357371970a607c4f1ec21bb92550c1; defparam ram_0305.INIT_1 = 256'h570a6f1ceb613a885a738b85084a55cf2e1d619a5392390c972d53e0b3c11f5d; defparam ram_0305.INIT_2 = 256'hb630e33faca35036486f0b8f94f0a4b21f804a2d82799ab121141b3ab1ba8df4; defparam ram_0305.INIT_3 = 256'haf7d9e3eb70911e8af4f2a1aad6cbfaa69248b89b36c222f7b1a5c32aa3844a4; defparam ram_0305.INIT_4 = 256'h273c5c3dcea0d9942168d6181aaaa30efbc3efd5fff73c7f30de4bdacd018779; defparam ram_0305.INIT_5 = 256'h559c7a4af1d4c9204d935d10817727b1ca5c554580e8b28dfc9e2fd6f2c71e77; defparam ram_0305.INIT_6 = 256'h418602bdff1e69af57af6a198e57a59c68443f3934fdd09ee68e630304166940; defparam ram_0305.INIT_7 = 256'h54aac47c7be964002b6c71aec829d69dc6ef2ee6f3640279b8c7f7947b4a2e61; defparam ram_0305.INIT_8 = 256'h32b50c21a7bdbdfac5909853b9d0fa8915dadc18f087070e30fba834d6eab209; defparam ram_0305.INIT_9 = 256'h02742ea4a2b626738ce04c7f6b4472739f981a7dd37413214228c9446ab320cb; defparam ram_0305.INIT_A = 256'h5c70fe89a21724eb2d36ded6fd01f47da78a97db0666e038cc5284ffaf5e66e1; defparam ram_0305.INIT_B = 256'h7ffdc072c4f7abc5888f3d30aa097195aa54f18635ad8308e08d3cda939db459; defparam ram_0305.INIT_C = 256'h159a2eaace991c51eb3c61abe9fe74af235d51f04ebabf0b2c0f0dfe6e3bb4e6; defparam ram_0305.INIT_D = 256'h460ded1b0a7f120b23cd292508e5a575fa8fd66f3033b69ab189e110fae0d668; defparam ram_0305.INIT_E = 256'hc72b4562d113f6f9c58ba44a7edf53b39b664357e12296fc389bd05d098311ee; defparam ram_0305.INIT_F = 256'h69bb7c5e08c96718f7ad092ba30a40c3b4347572251976ab0d1cae6bbac50333; wire [15:0] rdata_0307; SB_RAM256x16 ram_0307 ( .RDATA(rdata_0307), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 3), .MASK(16'b0) ); defparam ram_0307.INIT_0 = 256'hf59c43dc52bc3d2b7bd85cd8c56aabb48969aae3721d16db0ff0524dabde709b; defparam ram_0307.INIT_1 = 256'heff0fb7181e53b6512b080104e27b8e18c62780045a8106caf69951ca6173db4; defparam ram_0307.INIT_2 = 256'hbfcb9c012c6c74f22b40ebe0369f994c9e409a65cd018bacb6dc6c3da36a6652; defparam ram_0307.INIT_3 = 256'h7ea21da12871042efd405fe9998f635050a02f99e9b802cfec48d38fe984f30a; defparam ram_0307.INIT_4 = 256'h5b659e0511fe236eb30e9fe92c5d69a637a10ab807a98eb567c2e914431a96fe; defparam ram_0307.INIT_5 = 256'h6a7816f542396924307d31d55501a35849b2531f4ca596a29e84cb3c650b4062; defparam ram_0307.INIT_6 = 256'he278bbc6ce05e58f6d15b005337aa2abdc6866ce8fc74cda53e9393909662f49; defparam ram_0307.INIT_7 = 256'h353257b35760e5d107ec73be367dbcef8e9d6f4c227f436758f569bc325ac59f; defparam ram_0307.INIT_8 = 256'h83609202f72286d35700331a86c68f0b1f20d8c0dd39bf0e7652cda584bec453; defparam ram_0307.INIT_9 = 256'hf24f9f1dca3539dcc73bd15a1c3b12e4f27d864325c1eb2f5f7c5e9ab0c6ec68; defparam ram_0307.INIT_A = 256'h2f41690287a95877a8637624974e1d779aa82daa7f1439733a7bcd7ee6a7d6df; defparam ram_0307.INIT_B = 256'h4d3e73056bebe5184c7fbacd65b2862c66c425d3b82ac573ab4b325035a9cff1; defparam ram_0307.INIT_C = 256'hf2dd4cf5279f86c413dc082dfc3b8e1dd913b59118dac6c99cde6e4a487316a2; defparam ram_0307.INIT_D = 256'haa901c2b6d47194f2157465b276bc2cb30c8af04f6372384f969e26235a1fc6b; defparam ram_0307.INIT_E = 256'h7cacd0b5a31ca17fdf94837ffa560342e9aa8ec69626dfd0b33b4df263d1fb88; defparam ram_0307.INIT_F = 256'h0da63678ff1980428f183ce9f9317dd0f2e0ad40f9c55b89342db6e18b832977; wire [15:0] rdata_0309; SB_RAM256x16 ram_0309 ( .RDATA(rdata_0309), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 4), .MASK(16'b0) ); defparam ram_0309.INIT_0 = 256'h07a51489176ecf26b26ba3d3f4acb14b927e4f80c1a3333e79f52b87d0052eba; defparam ram_0309.INIT_1 = 256'he542c4ed986aef41e2c1f1f1e0eff957f5f7fe3c1a956f1b7e73f6c12c3e7b35; defparam ram_0309.INIT_2 = 256'h08e0d0315d86c998bfce1650d75c4cba11db471ff568d0ad39078ee3ad2dd5ae; defparam ram_0309.INIT_3 = 256'h0624c556f3b27168ca874071a2c037eba979cb6738a8983c26017669cd44f3f9; defparam ram_0309.INIT_4 = 256'h8f3727f57d00cdfdb0766c85a68bb59c52691d4b154bc2017cb2f0cf9deac2de; defparam ram_0309.INIT_5 = 256'he2d9ad2f0193ddb2ca738bed9d69fff0c4e181c5f6534a986fcb65d1756b0f5d; defparam ram_0309.INIT_6 = 256'hd28fc8443c5006206c35efd0fb2e0504f8d08f788e276b9f642d6837897906bc; defparam ram_0309.INIT_7 = 256'h9d25639c0a8e04cdb1fd5e02583734811a349e6ebfb3913e775e5fc09dbd8536; defparam ram_0309.INIT_8 = 256'h845c59e1f7c470abce8fa54120e38a9ff002c46c0eb2b651d3120627df47fa65; defparam ram_0309.INIT_9 = 256'h709ef0f92579008ec26a7bb4aa70870557693cc59c4e16347e23574429b1acaa; defparam ram_0309.INIT_A = 256'hd3553eac767b972d7cbec91901fdf203768c337577e599929a02788bab131ba2; defparam ram_0309.INIT_B = 256'hbcb398877ab4e802f93de666ee53147b4104a883e8fc58f704764bb0377457aa; defparam ram_0309.INIT_C = 256'hcb6bcd60cbeec7d69627cb56da8e829171c72a8f9ae075ca73146cb3bb33895f; defparam ram_0309.INIT_D = 256'hec0a7b61ca77b184a5da828074adee07b0bdaf9d3a75f0b4e496228906882c96; defparam ram_0309.INIT_E = 256'h4fcaff83f49c993e1344167d32660a6693a730fa2f29d5d4cab9063853bd7bbe; defparam ram_0309.INIT_F = 256'h0238e69d220727869654edd6fa05d2e9f17b82827fdf7e151d0078147fe5bdff; wire [15:0] rdata_0311; SB_RAM256x16 ram_0311 ( .RDATA(rdata_0311), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 5), .MASK(16'b0) ); defparam ram_0311.INIT_0 = 256'h1e29fa340abb28a034d044905ef2b7aa08b76a1dafc7e743bdfc4fe88d77bb02; defparam ram_0311.INIT_1 = 256'h2fed2793ab9de32ba8d11df985a68371bdfb9564ccb8c12c63aa9c968b95b348; defparam ram_0311.INIT_2 = 256'hc3603ba144d8f2e8273b7762172a862f179e043fc755912fe840c60eb0aafc5f; defparam ram_0311.INIT_3 = 256'hbe3c00c259e270eec9ab5ca99a40653662bdc9ba0b0742eddc9da27441c29907; defparam ram_0311.INIT_4 = 256'h2effdb8a2a1ad09741d463bafe42d24e684e5c271cb64911f33651abb2554217; defparam ram_0311.INIT_5 = 256'h3d12ab8b32a2f8e90e616ba6136747522f6ef4b3ef3231750a6a6da587c46544; defparam ram_0311.INIT_6 = 256'hb9b1d4f05a71ca7bc92e7ef599655af7ca4abdc9a6bdb0ca6c9a1b2de1b67e6f; defparam ram_0311.INIT_7 = 256'ha2601f9d00bcab3ca1ec26151124156e6cf0f2c45f4761bdfb4f3ea6d0b9789c; defparam ram_0311.INIT_8 = 256'h16012927b00b193efde7ca215c88573280cea742d31623de3e0ed88b5a08e23c; defparam ram_0311.INIT_9 = 256'h5b1657e14902f7c08b6c154f96e04192d52439983d0a5c8810d0462f45d1c091; defparam ram_0311.INIT_A = 256'hdc67eaa704ff2aa09386be4dc9448074c427139cbb5118273a954a53838ffecf; defparam ram_0311.INIT_B = 256'h347c2253402c45890e871a1dbe53cd91e98b3cb4c1884c349e9536fcc1e5b53f; defparam ram_0311.INIT_C = 256'hc22e14b25ffdfb89a0556700e8171d0dfc84eb865898e6280cdbf0dbf51ec78c; defparam ram_0311.INIT_D = 256'h9fc88e0a32800fcb117c996b5dc252ec0256ccf1cecfccb0f2bfd5870219878c; defparam ram_0311.INIT_E = 256'h69df52b9aa92b8f75eb961cb77e1753ce5da5400f412bd36bc5c274a58fe17c2; defparam ram_0311.INIT_F = 256'h96dda78bb769a16e24ad1d9c34604b35c450c79d6fd2e51b28320a1bdd2408b0; wire [15:0] rdata_0313; SB_RAM256x16 ram_0313 ( .RDATA(rdata_0313), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 6), .MASK(16'b0) ); defparam ram_0313.INIT_0 = 256'hd9559cc61e3f4571d58b14ea4740e577d14c30ebdf4f73b8c782f46f3b6c08d1; defparam ram_0313.INIT_1 = 256'h6f4efcd9b858d443ac63f0fd9225592fdba22f66c1eccb3714aa800ed71412ba; defparam ram_0313.INIT_2 = 256'h0ab1107b6d650fdf66add2cc2a7e488108161e3e651486f00ad50b3c070e68c3; defparam ram_0313.INIT_3 = 256'h37ffb1dc247db3f4b69ca946e62587246b0806f819735c9261c4cbfd46769b71; defparam ram_0313.INIT_4 = 256'hb436465a2f3a75b373c8a2013106750d96cd433c935988591a46c2cf947a4fc0; defparam ram_0313.INIT_5 = 256'h97752e46f2a5658b7a242904bbe1e26748ba95bf6f7e9a6ff72373e9a3f5dcc0; defparam ram_0313.INIT_6 = 256'h2f25d930c7bea790540df0b90418e26c86c58cba0f3cfd2e20c1adfafc8b58b9; defparam ram_0313.INIT_7 = 256'hf67a98264a755ad033da5a3f4f7bb0563a24c65f9e379e7ea24398ff770a1569; defparam ram_0313.INIT_8 = 256'h1a9d43cfcd1ae2142b2f35e8eb1f961e20f3488685a817ea0f7147abefe92821; defparam ram_0313.INIT_9 = 256'hb3c30dcac4dccdad0c7e14a9fa41edd57fb93a1560cfad9fffe812b476a66bcf; defparam ram_0313.INIT_A = 256'hda6c916c9a250420b9470d5bb5f4895bc65f83f3418d7872734951b3c89f8157; defparam ram_0313.INIT_B = 256'ha09ff972ebcbd082333bc97a4687b5b5f7b3a7939d7f4a6d3728cfa5a6599e93; defparam ram_0313.INIT_C = 256'h38eb42c565b9f9ebe0596a1fa9f9fc33836fca4058e1e20f60069ecbde0a1a05; defparam ram_0313.INIT_D = 256'h4beeab82252f2569fb56ffad4478db381e6b0d96b7f6d712c7073d8a118a5892; defparam ram_0313.INIT_E = 256'h0b48f12af2ff6febee038a01ae79d93cac9f09ac76501e43bb4817d39f1d043d; defparam ram_0313.INIT_F = 256'hdfbaa596a11d2248f849620d20cf3a6f856302c5bcc74dd6bfb3a756f59446c3; wire [15:0] rdata_0315; SB_RAM256x16 ram_0315 ( .RDATA(rdata_0315), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 7), .MASK(16'b0) ); defparam ram_0315.INIT_0 = 256'h2af31f7e9493844389075cf4a347ad1ded317b44870c068432d89047eeca2b37; defparam ram_0315.INIT_1 = 256'hf51a6444eba4fb0b4baef416aa19593cf6ab473fe46255e53550cc8523ccb1fc; defparam ram_0315.INIT_2 = 256'h09f3a52d859af19ba525a62fccf0b64d03a86be72316ce8f38acb5959db215f5; defparam ram_0315.INIT_3 = 256'hfe309f2ae03cb8f724c01818371d5456ff5c9ef029f4806597554044d23fca5c; defparam ram_0315.INIT_4 = 256'h13bbbf3bb5e83b3200dde2fa4ef0566f4fcb2bee140ab81acf351cfad0a9d1cb; defparam ram_0315.INIT_5 = 256'h73b9f5bff710c59328c47ff675d8b68cdd2cfc07aa71d66b29ff98500b70e063; defparam ram_0315.INIT_6 = 256'h24d0607d548133d0f4e50d79b643fc604de016ca3d849c9e1fa5d70357f443c7; defparam ram_0315.INIT_7 = 256'hab53d6af5f0b3c6d7710bb402e21438013f3ac830c6405e219b3f114ad5b4db2; defparam ram_0315.INIT_8 = 256'h268b8fc89f948592c8e2fb38912dbd2bc88e67e820d03f5b4cf494491ac36816; defparam ram_0315.INIT_9 = 256'h846a486f199955e0852705305a805d5cece1647e839d3cd811a7a9d197f84815; defparam ram_0315.INIT_A = 256'h09007c4a495b836c16a082cd2418b2962059924230aa7729d1bb2be706283998; defparam ram_0315.INIT_B = 256'h336ee10a1530f40a98d338e2dceb777d8f6b456431c2267dcfda449bf5d28ed4; defparam ram_0315.INIT_C = 256'h1b16770684b88454ab9db7e40b07802b36d741eeacebc9d1648723b857f2ba4b; defparam ram_0315.INIT_D = 256'h9ccb7b57c9d5f4ac9eb293df84b6a124d1dde80bc7f262e38af79177e6520243; defparam ram_0315.INIT_E = 256'hab117e08b2b8ddcd7f68311478c2e018799685480835f1dc30b9159377ff2d69; defparam ram_0315.INIT_F = 256'hb05b0092e8d80ea1ff04a52f94d9b7f147f5651e8b624c1d800ce228e9db35e4; wire [15:0] rdata_1001; SB_RAM256x16 ram_1001 ( .RDATA(rdata_1001), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 8), .MASK(16'b0) ); defparam ram_1001.INIT_0 = 256'h9c7c41b50768a605cf8152a411317da39cf38541b53e6cab1f59fd2ff79f1b29; defparam ram_1001.INIT_1 = 256'h2cb583fde53060648977748557fe9480afb7e331806f1955e4cb348795a15d4a; defparam ram_1001.INIT_2 = 256'hfc57e12bed42aa24b833f3f2e8a254f8d17dbaefde4ef4fa78f14f96bb248b1d; defparam ram_1001.INIT_3 = 256'h6fa44ad672bb75f06d5e00fe4d735e528400897f0eaec902ec089786e9e0968d; defparam ram_1001.INIT_4 = 256'h1ce5e5112b8ab585513bcb8ef393e593ddd5d0e76af31aaa4e815e680eea7d1d; defparam ram_1001.INIT_5 = 256'hc338e533ee20665b272c18f0b85424e41745d7649fad5736f68677b92feaba2c; defparam ram_1001.INIT_6 = 256'hf1ba42579571926ee12e8abbd287acf12d22a10caecce7b310dd7e75dde1bb7d; defparam ram_1001.INIT_7 = 256'hf4b97664ff2e90cb650c33d660c8e03898a7c0f608c58667867bb9f0c4042b77; defparam ram_1001.INIT_8 = 256'h03c5c843009d4ce9457a900cc6c45ca871bcf29e8c206b85bc1f7637e5afddd2; defparam ram_1001.INIT_9 = 256'hae78d5d9491ce25d1c833158e72dc0b440f91d1acce4bc33cddcf8a63885b8a6; defparam ram_1001.INIT_A = 256'hff813a16814de988dd1d99c902ccba4c070623d63935bc59ca9a54f8811d97b8; defparam ram_1001.INIT_B = 256'h0644e9960a194d65fed04e16f0f45d6ddf1aa911f13da01696dce1e5fdff6a9a; defparam ram_1001.INIT_C = 256'h93aa1fbc2c2f92dbec99d4e59741569b7a5fef853715af2e069b19fb50a1b934; defparam ram_1001.INIT_D = 256'hbdfc5a6a699eb6c6a6857c6b2ff4ef867084d4db40cdc5babd878ec8a5b9f0ea; defparam ram_1001.INIT_E = 256'h0d3751acaa17328f1e52fd4443755392bc4d20b626185b200c87677191df6259; defparam ram_1001.INIT_F = 256'h7772f629fcb9aff2a3318a98b9e4e58f44fd902bf544239968d748796577ca6a; wire [15:0] rdata_1003; SB_RAM256x16 ram_1003 ( .RDATA(rdata_1003), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 9), .MASK(16'b0) ); defparam ram_1003.INIT_0 = 256'h52f7a59fb8d848aad51bd38121e11d5175b3239b971a8bcbd270d276e4f21f90; defparam ram_1003.INIT_1 = 256'h19a6611c09a950d1045425ecee7977d0f3bd3b70cce0ade0aa10f5fe3f15b1d3; defparam ram_1003.INIT_2 = 256'hff16259d190b5d0dd4453df81d9375dc1768e22673be4905fcc51f0f975e2cd1; defparam ram_1003.INIT_3 = 256'ha32a34f06674fd42bc1c9533c378d01b65cbce95a7200b64f9dde478cbb754b7; defparam ram_1003.INIT_4 = 256'hf6d4f68fd768de9aa637f5755cc3f64248d0f9866c5fcb00bd79be9d247243f8; defparam ram_1003.INIT_5 = 256'hb2411f4b8b21802fbce0082920a96856c9902897538f7068c10ebe6dca1ff7d6; defparam ram_1003.INIT_6 = 256'h2b3b94e10d954bc10b97e227f5b2c1c629e62166ed06c2347bfb2fa4a44010ea; defparam ram_1003.INIT_7 = 256'hff82fa877fbf9802434a2f8f8eff7a18e6b9ad444f736c1592db47627146289e; defparam ram_1003.INIT_8 = 256'hfced2cd513690efbd52ded9fe01bb809a8d2b048326d0e7559d8c181cf6d075f; defparam ram_1003.INIT_9 = 256'hba7672c199d70b9d2b3d5c980aad280086feeacbe16077b94941ac9ebe9c7aa4; defparam ram_1003.INIT_A = 256'heb9d91de7a2ffabce82eead39a8ee44eb1b65a7274ead34013422c9f7cb0bcd7; defparam ram_1003.INIT_B = 256'h2fbc5beec9c515ca4d0186e649eb7475e5170e7ea4b6e0e3de09f96b98a4216c; defparam ram_1003.INIT_C = 256'hd146f604f32aea162557efc77e070a9edbbad0d276024acf16d1a5dd4629d48d; defparam ram_1003.INIT_D = 256'h445080680263cbe9b1dec849f5dba0449c1a105981a3ad167e346303742edf2f; defparam ram_1003.INIT_E = 256'h0527a9fbf0a68e910b8589e3bb1efa281615e6857d5cdb78ece71aeb9f69de3d; defparam ram_1003.INIT_F = 256'h9282f9309931634a765f52b8eec225c309549d9a1045a9b700831ab3468223de; wire [15:0] rdata_1005; SB_RAM256x16 ram_1005 ( .RDATA(rdata_1005), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 10), .MASK(16'b0) ); defparam ram_1005.INIT_0 = 256'h0776006ec4d03f7a5c73c6057f7bbb99f7edd3d8a12be2e3861cd69aa1bc525c; defparam ram_1005.INIT_1 = 256'hf24b4a0303bece261707dd7962cd9ab47513d64b793224f15562b4c4d72ec72c; defparam ram_1005.INIT_2 = 256'hd30dbc4325341cdd5dcfb3d5f9410e1519c20e4b16d74676e855324ccd67af40; defparam ram_1005.INIT_3 = 256'h4a60c84b1172429d7d8a0b7bbefc3e626e25187906cd7e14e1c316ac7e9ed288; defparam ram_1005.INIT_4 = 256'h9d1c20f207820f24ba23a74a0da804ec13f8a1b7ed61e5a644c79e5932782489; defparam ram_1005.INIT_5 = 256'ha2f4c117c4d10358b1b04ab329706816dce90617ee78102870d29889a7660488; defparam ram_1005.INIT_6 = 256'h22b667287f6fed4bfee9b16292dc9c8123a2ab5dcfa8fefdfcedfe2cb1869519; defparam ram_1005.INIT_7 = 256'hddfb1d4815eaa10a75bde6c4799ef3e1d4c0812fa1d808083bc054d21b3655f0; defparam ram_1005.INIT_8 = 256'h6bebae5c4efe1bdf465dda9e4ca89a3a78d985462f017150b8f9d36783fc27d3; defparam ram_1005.INIT_9 = 256'hde7dd3ae6e92319591c5d8647f2e51d38d1b0cad7683fd870d63f55fca8a1524; defparam ram_1005.INIT_A = 256'hd27e172a81e83608bbc9ea610f3801d47a54d14a5309a4847f14abceda8fecb9; defparam ram_1005.INIT_B = 256'ha151d1f63317c4515c9f5773a7e5812a3906738b26b9a9447ec9aceb93fe5636; defparam ram_1005.INIT_C = 256'ha43c9e64daef57c028270e426fa141aa96209263021ae9d0c78fd98f9c148954; defparam ram_1005.INIT_D = 256'h40d7f09924ea37080c9b7243c18c25243eeef757b2ddf45cd90f1552f2dc67f4; defparam ram_1005.INIT_E = 256'hf09c320f602b1fa8d8321d0554a8a6613a67f43747362b7f5e2881a27d943bec; defparam ram_1005.INIT_F = 256'h86a034c22751bb658bb02c3d653e7f3af4f1d23807a5d0850342092825c678d7; wire [15:0] rdata_1007; SB_RAM256x16 ram_1007 ( .RDATA(rdata_1007), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 11), .MASK(16'b0) ); defparam ram_1007.INIT_0 = 256'h4e39bcdedc4225f725553e52a5ac856ffce7ec677b03371f5cfcbdc088d25d3e; defparam ram_1007.INIT_1 = 256'h3ae63a363e292263c3767b69693f590967b4a51b7545ef66197a9e81340625f4; defparam ram_1007.INIT_2 = 256'hd143d96571dcf7c28197a18318537b93c8fcf207cbc9c28b02e6891faa1d2060; defparam ram_1007.INIT_3 = 256'hd4cccc72f0bc14361256a0860cf83c4036056951417bd9e9c36bb443da137a45; defparam ram_1007.INIT_4 = 256'h19fdfb40c38ba5c327ec0e928aa904b3c82003e48245d6665ea30e6de59d95b5; defparam ram_1007.INIT_5 = 256'h1955f4d9c2eb2e65e772a58e15b472caa748bcdfe36ff847d6b40e3144fbeec3; defparam ram_1007.INIT_6 = 256'h1731ac85d13545f4d691a4c6b53833936ba7bf84be95a37682d3d7e8f46105ae; defparam ram_1007.INIT_7 = 256'hff2e1b21202bc8d4e6d0924ec4f3d650c383ddecef63c838ec35fdcdbfff217a; defparam ram_1007.INIT_8 = 256'h6cba3ae658a500c33b92d92896b897b356daf59a114db811c6386201d9933a04; defparam ram_1007.INIT_9 = 256'hfc3a2543ec498d95e4d91a702c848c7ac8bbd9a2e427f73c9103bf231eed364f; defparam ram_1007.INIT_A = 256'h93e1884aeb0366366c841e1f542598c2bd8b2cf31f73055007bc12d74164191b; defparam ram_1007.INIT_B = 256'hec77a7c083657e4af9e587b26a41f9951cbc47a4998066a06fbef31e4c703a84; defparam ram_1007.INIT_C = 256'h2fe468d39c8459102279bb9b4ee58b644a36bf6473591f8ef3cbba2a994869ba; defparam ram_1007.INIT_D = 256'h83776c239ddd7de3a1578433608dc6a4469bf2d56f488f12b726d8ce919ea9d2; defparam ram_1007.INIT_E = 256'h3fdc7c39c3d78e24f206100c593ae13f3504e3fdb51d0c1e0ee8deb94c2e56f8; defparam ram_1007.INIT_F = 256'h0cf5c0b04f44cb998f2666e53fb0821fce4cd86a56cf0d9294c63badae74ea58; wire [15:0] rdata_1009; SB_RAM256x16 ram_1009 ( .RDATA(rdata_1009), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 12), .MASK(16'b0) ); defparam ram_1009.INIT_0 = 256'h00dd22ab72977ee266ff25412fb075db016baeca9f13968d4616a585eee3090a; defparam ram_1009.INIT_1 = 256'h13e38c740dfa42a0dd7630edf82bec6afc3e4444a24e308b45899e5c2179aa53; defparam ram_1009.INIT_2 = 256'h46074c8da907cd884cf6a0d6c8f42c68d5aaeade7159ac472a3846993f283607; defparam ram_1009.INIT_3 = 256'h6e9a5cdcc076f56aea6b66f2423f485b78289ed5c6192a7b88de6b149a0bcc77; defparam ram_1009.INIT_4 = 256'hba3d1385e32eab4b82370495b8d90f5751a6dc1da47d33e82fef50b08904afa8; defparam ram_1009.INIT_5 = 256'h070b3ab69f1e5ff13022fd403e3197f363bcf4b926a12265e8e7143b9ce57bff; defparam ram_1009.INIT_6 = 256'h54e43106537fc4a6ee059ca2e4608f1ddf4c225a60c46b4b8c5aad9c0140e6e3; defparam ram_1009.INIT_7 = 256'hf54a84ac1112cce38092c8ab9dc372da803fb1043313a44bc09e0ae9870882de; defparam ram_1009.INIT_8 = 256'h7bea9c49dfce264c2887a4d75f8401384d3ecd8f4126ba767b0f559e9bc27589; defparam ram_1009.INIT_9 = 256'hd83372f53ac2c6174a64540ebc7c0a604d6d739f6f7ec5c7c217b0f42ff28ce4; defparam ram_1009.INIT_A = 256'h225c6c8d155ddc900609375ff62e940face07ecd4700b9a58e31f79ad4177031; defparam ram_1009.INIT_B = 256'h6f3934aeb7cb9b817f7a1e742cd2b64c077f7b394ac65fcc5d67f2b13ef402ef; defparam ram_1009.INIT_C = 256'h4634285a3fe505d87689ddd607abe8942354d1ff1ab96bbda0e3992cc51827f2; defparam ram_1009.INIT_D = 256'h8f5ba84568337a4c48dd650d26e7774062012636b6be06c3d084e9e69505669d; defparam ram_1009.INIT_E = 256'h9c8362ebbd6cdb77941d8dcc2cd9975ecf45bdab9cd5c6c6d96cd12439ba3416; defparam ram_1009.INIT_F = 256'h6ac567c655b53b93d3dd0718c2bed6419eff6bb310b4865c1115d7d6a18dbe39; wire [15:0] rdata_1011; SB_RAM256x16 ram_1011 ( .RDATA(rdata_1011), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 13), .MASK(16'b0) ); defparam ram_1011.INIT_0 = 256'h362c2d793cc2cbefa8f0856599ae3092fc9d1899af1176c56cf4af5204ceff43; defparam ram_1011.INIT_1 = 256'h24a47c459b500efbdbade11495dc1563d0eb10d855e616d158903f42c85f9d7f; defparam ram_1011.INIT_2 = 256'h22dcae4b4ea436cfcfab001745d46d018985b37ca8967cfa1acd8092b04b8f54; defparam ram_1011.INIT_3 = 256'hafc84dc99ccba1a754e8891edcd82ef3bb3b2c3ae1cb1ec0a14f572c60d12f08; defparam ram_1011.INIT_4 = 256'h904aa0e37fa6c8da80ef6a8494b730ce7e422c4cf13aa527573671d153cf7ce1; defparam ram_1011.INIT_5 = 256'h03f03529f73ed23835562295897065dee7cf99f593ccef4c545193d867ac7e08; defparam ram_1011.INIT_6 = 256'h5d2fd0e50390eccf5322efa530c77ef20d5807ae44138ca9d55c7eb221c4a3ed; defparam ram_1011.INIT_7 = 256'h5ecf2c470973a0d8a192a9aebb1fc0634a2bc4ad471a81a56dbef77148acc224; defparam ram_1011.INIT_8 = 256'hb729ece2b3ebf4a36f769a6fa20a6e78f448a15ae707f593097b6d2aecaa6948; defparam ram_1011.INIT_9 = 256'h0af41c521d3c94c64b76a424110a8d95fba2b51dbf72b0b34806cb2a1088fd7e; defparam ram_1011.INIT_A = 256'h65f51a767a25bcf8c8b922d2291a81cb43d8fd14c4f28e3f6211e685cf6bf659; defparam ram_1011.INIT_B = 256'h525643b65c204fbc4784701c8d27bc7272d622ce3b95f6cfc3dd99df69cb3b8e; defparam ram_1011.INIT_C = 256'ha60853f8e9d0e538e106184173fdc70b496cc3048e65f3378e0b740b76bf594f; defparam ram_1011.INIT_D = 256'h8359c3bc1e7be748e9e74c42b2ac4ff44fa6e1a5cd485e18bf2f1674d76fc7ad; defparam ram_1011.INIT_E = 256'h19868c5139623b8823c1f62d69ba80469415a6766cb8c4e5827ada6e7b2c107c; defparam ram_1011.INIT_F = 256'h1c7f1dd62f29a97250327ce5d9909876004e17f1532a2d218a67980a03ded845; wire [15:0] rdata_1013; SB_RAM256x16 ram_1013 ( .RDATA(rdata_1013), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 14), .MASK(16'b0) ); defparam ram_1013.INIT_0 = 256'h1c9b05f5062cf4c25ddeeac8024576874c7989e717a11770dca3747f29ae514a; defparam ram_1013.INIT_1 = 256'h13cfb7cc84ef05f07fc8f83085878e6aab399c88815116dc4ad2f7c4cea680e2; defparam ram_1013.INIT_2 = 256'h50b45abe6c1f167f5bccf97db6d7251da4321990172d4897804947f434e79b1c; defparam ram_1013.INIT_3 = 256'hb2a152c418006c4a0e7bcc961cacaf37eedbb38830633b7fe3a124f7795f58e6; defparam ram_1013.INIT_4 = 256'hc8b596be79c27aa527c94de1cee75f50e13465f1031d4f6e88866f2adb61806f; defparam ram_1013.INIT_5 = 256'hcb2b6636db3b635aadfd796a226f128ff3d2005b501abee63f9caa1116367044; defparam ram_1013.INIT_6 = 256'hfd2255e9d120bfd3df10e0dd1f3488243e58bf85058a960d9767ae3176090494; defparam ram_1013.INIT_7 = 256'hdc0aec0de8936cc5843863a55f7d60326be11898381a27151ee3ba699a4e8d6d; defparam ram_1013.INIT_8 = 256'h5219e84d5be7ff41723580327bf1d2931ebff70ac32a3219066af7ebe5b6d1d2; defparam ram_1013.INIT_9 = 256'hcb5029f958e66f0e3d1b1b9df273b9131bc1d10abe226c03de9b15ff5ff9e282; defparam ram_1013.INIT_A = 256'h02637bb03a384463fee3a500ca6b4614e19db03d8eec5214540767a13f4218d1; defparam ram_1013.INIT_B = 256'h1d83eee108d925f34f15f03269d685d1132a5aa102f8a49ba0d216d4a2de5858; defparam ram_1013.INIT_C = 256'h5b354f004e9a7d40dd6f4b38b9d258c6718a6db339eb23d591e96b31b4ffed14; defparam ram_1013.INIT_D = 256'hc1c1c526ea60690e3bbf2bce2989a12e3deb4dcafc2818b37a591a15bc6fe402; defparam ram_1013.INIT_E = 256'hc08c14e42ac9e3175d2c2ae617d71f3aac4c18ab51f4827f491bd8c7109c3db0; defparam ram_1013.INIT_F = 256'h50929c51c7d605a973c3f518850e9ecc133cffd13a9942a69317b566dba8e78e; wire [15:0] rdata_1015; SB_RAM256x16 ram_1015 ( .RDATA(rdata_1015), .RADDR(addr), .RCLK(clk), .RCLKE(1'b1), .RE(1'b1), .WADDR(addr), .WCLK(clk), .WCLKE(1'b1), .WDATA(wdata), .WE(sel == 15), .MASK(16'b0) ); defparam ram_1015.INIT_0 = 256'h12be2212ed14b2640338f81dff4108d4ac3bf1e6a03d7a29cac03cfe50e1bff8; defparam ram_1015.INIT_1 = 256'hf485c1d5ad53c47a71709a5fb8cfcbc329f0e18b7178c13872b52c7c6a285ce4; defparam ram_1015.INIT_2 = 256'h0f7b97d175c184936b7626f2402e106ec7a53b31b97f05b87b224270da05e334; defparam ram_1015.INIT_3 = 256'heb2844df6eb99634216dfe81c6287f7c55d047b08034e4c32b1d824d10c64fe0; defparam ram_1015.INIT_4 = 256'ha28fff103cf00d3a51939c8eb633d49ed059a79bb70253ef6a145fa0fba30636; defparam ram_1015.INIT_5 = 256'he8ac62e181b16da21e581e88f0a9faf89d14e1e2e1013d7522705f7dd64d2de4; defparam ram_1015.INIT_6 = 256'h7b90b08c103dd63a3c5423a7ee83d6a144fbf40c6fb04befa7e116b1b8a5d6b6; defparam ram_1015.INIT_7 = 256'h6d5eae0464fff912dcde27536baa0ce0831c559a90f63df5d7dc9c2ac9cd82a2; defparam ram_1015.INIT_8 = 256'hff802d46b492cf02aff2dc259541586414f67b86fc8c4114969f39702d29830e; defparam ram_1015.INIT_9 = 256'h7078b25fbb5914cd4dfc3c391beb54a2c47baabae73f3ee4da1b64cf7767be72; defparam ram_1015.INIT_A = 256'hfc517c45f85fb461e326f7a886cebeb6c977d0b285b42d1ca35042cafadee9e3; defparam ram_1015.INIT_B = 256'h5519034f258fa5c885ea5cf8d67b379a55859ae6b38f12236e559c4b19972731; defparam ram_1015.INIT_C = 256'hcf4251d73f1054d3986f2ac746ac44d4e0e9a0b4f179126262ffef39f4ba1756; defparam ram_1015.INIT_D = 256'h3cd68370c54a6b68802813bb1a3181ad13166a324cf1c3eba85f8651664dde8a; defparam ram_1015.INIT_E = 256'h8a0896ac480c525a1c702b9856da6163328b36a3ec5c2e13bc07656b71bd1575; defparam ram_1015.INIT_F = 256'hdbccace4967a5bbacc70d66dd227a1fbd11062e04cc1cb91d6d0dcd9750fd1b7; assign rdata = sel == 0 ? rdata_0301 : sel == 1 ? rdata_0303 : sel == 2 ? rdata_0305 : sel == 3 ? rdata_0307 : sel == 4 ? rdata_0309 : sel == 5 ? rdata_0311 : sel == 6 ? rdata_0313 : sel == 7 ? rdata_0315 : sel == 8 ? rdata_1001 : sel == 9 ? rdata_1003 : sel == 10 ? rdata_1005 : sel == 11 ? rdata_1007 : sel == 12 ? rdata_1009 : sel == 13 ? rdata_1011 : sel == 14 ? rdata_1013 : sel == 15 ? rdata_1015 : 0; endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dff.v000066400000000000000000000001171276746530600226240ustar00rootroot00000000000000module top (input C, D, output Q); SB_DFF ff (.C(C), .D(D), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffe.v000066400000000000000000000001321276746530600227660ustar00rootroot00000000000000module top (input C, D, E, output Q); SB_DFFE ff (.C(C), .D(D), .E(E), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffer.v000066400000000000000000000001451276746530600231540ustar00rootroot00000000000000module top (input C, D, E, R, output Q); SB_DFFER ff (.C(C), .D(D), .E(E), .R(R), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffes.v000066400000000000000000000001451276746530600231550ustar00rootroot00000000000000module top (input C, D, E, S, output Q); SB_DFFES ff (.C(C), .D(D), .E(E), .S(S), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffesr.v000066400000000000000000000001461276746530600233400ustar00rootroot00000000000000module top (input C, D, E, R, output Q); SB_DFFESR ff (.C(C), .D(D), .E(E), .R(R), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffess.v000066400000000000000000000001461276746530600233410ustar00rootroot00000000000000module top (input C, D, E, S, output Q); SB_DFFESS ff (.C(C), .D(D), .E(E), .S(S), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffr.v000066400000000000000000000001321276746530600230030ustar00rootroot00000000000000module top (input C, D, R, output Q); SB_DFFR ff (.C(C), .D(D), .R(R), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffs.v000066400000000000000000000001321276746530600230040ustar00rootroot00000000000000module top (input C, D, S, output Q); SB_DFFS ff (.C(C), .D(D), .S(S), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffsr.v000066400000000000000000000001331276746530600231670ustar00rootroot00000000000000module top (input C, D, R, output Q); SB_DFFSR ff (.C(C), .D(D), .R(R), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_dffss.v000066400000000000000000000001331276746530600231700ustar00rootroot00000000000000module top (input C, D, S, output Q); SB_DFFSS ff (.C(C), .D(D), .S(S), .Q(Q)); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_gb.v000066400000000000000000000002221276746530600224520ustar00rootroot00000000000000module top ( input [7:0] a, output [7:0] y ); SB_GB gbufs [7:0] ( .USER_SIGNAL_TO_GLOBAL_BUFFER(a), .GLOBAL_BUFFER_OUTPUT(y) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_gb_io.v000066400000000000000000000011231276746530600231420ustar00rootroot00000000000000module top ( inout [7:0] pin, input latch_in, input clk_en, input clk_in, input clk_out, input oen, input dout_0, input dout_1, output [7:0] din_0, output [7:0] din_1, output [7:0] globals ); SB_GB_IO #( .PIN_TYPE(6'b 1100_00), .PULLUP(1'b0), .NEG_TRIGGER(1'b0), .IO_STANDARD("SB_LVCMOS") ) PINS [7:0] ( .PACKAGE_PIN(pin), .LATCH_INPUT_VALUE(latch_in), .CLOCK_ENABLE(clk_en), .INPUT_CLK(clk_in), .OUTPUT_CLK(clk_out), .OUTPUT_ENABLE(oen), .D_OUT_0(dout_0), .D_OUT_1(dout_1), .D_IN_0(din_0), .D_IN_1(din_1), .GLOBAL_BUFFER_OUTPUT(globals) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_io.pcf000066400000000000000000000002501276746530600227750ustar00rootroot00000000000000# set_io pin 1 set_io pin 2 # set_io pin # set_io latch_in # set_io clk_in # set_io clk_out # set_io oen # set_io dout_0 # set_io dout_1 # set_io din_0 # set_io din_1 fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_io.v000066400000000000000000000025711276746530600225020ustar00rootroot00000000000000`define CONN_INTERNAL_BITS `define PINTYPE 6'b010000 // `define IOSTANDARD "SB_LVCMOS" `define IOSTANDARD "SB_LVDS_INPUT" // The following IO standards are just aliases for SB_LVCMOS // `define IOSTANDARD "SB_LVCMOS25_16" // `define IOSTANDARD "SB_LVCMOS25_12" // `define IOSTANDARD "SB_LVCMOS25_8" // `define IOSTANDARD "SB_LVCMOS25_4" // `define IOSTANDARD "SB_LVCMOS18_10" // `define IOSTANDARD "SB_LVCMOS18_8" // `define IOSTANDARD "SB_LVCMOS18_4" // `define IOSTANDARD "SB_LVCMOS18_2" // `define IOSTANDARD "SB_LVCMOS15_4" // `define IOSTANDARD "SB_LVCMOS15_2" // `define IOSTANDARD "SB_MDDR10" // `define IOSTANDARD "SB_MDDR8" // `define IOSTANDARD "SB_MDDR4" // `define IOSTANDARD "SB_MDDR2" `ifdef CONN_INTERNAL_BITS module top ( inout pin, input latch_in, input clk_in, input clk_out, input oen, input dout_0, input dout_1, output din_0, output din_1 ); `else module top(pin); inout pin; wire latch_in = 0; wire clk_in = 0; wire clk_out = 0; wire oen = 0; wire dout_0 = 0; wire dout_1 = 0; wire din_0; wire din_1; `endif SB_IO #( .PIN_TYPE(`PINTYPE), .PULLUP(1'b0), .NEG_TRIGGER(1'b0), .IO_STANDARD(`IOSTANDARD) ) IO_PIN_I ( .PACKAGE_PIN(pin), .LATCH_INPUT_VALUE(latch_in), .CLOCK_ENABLE(clk_en), .INPUT_CLK(clk_in), .OUTPUT_CLK(clk_out), .OUTPUT_ENABLE(oen), .D_OUT_0(dout_0), .D_OUT_1(dout_1), .D_IN_0(din_0), .D_IN_1(din_1) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_io_negclk.pcf000066400000000000000000000000341276746530600243200ustar00rootroot00000000000000set_io pin1 1 set_io pin2 2 fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_io_negclk.v000066400000000000000000000012461276746530600240230ustar00rootroot00000000000000module top(input clk, inout pin1, inout pin2); wire w; SB_IO #( .PIN_TYPE(6'b 0101_00), .PULLUP(1'b0), .NEG_TRIGGER(1'b1), .IO_STANDARD("SB_LVCMOS") ) IO_PIN_1 ( .PACKAGE_PIN(pin1), .LATCH_INPUT_VALUE(), .CLOCK_ENABLE(), .INPUT_CLK(clk), .OUTPUT_CLK(clk), .OUTPUT_ENABLE(), .D_OUT_0(1'b0), .D_OUT_1(1'b0), .D_IN_0(w), .D_IN_1() ); SB_IO #( .PIN_TYPE(6'b 0101_00), .PULLUP(1'b0), .NEG_TRIGGER(1'b1), .IO_STANDARD("SB_LVCMOS") ) IO_PIN_2 ( .PACKAGE_PIN(pin2), .LATCH_INPUT_VALUE(), .CLOCK_ENABLE(), .INPUT_CLK(clk), .OUTPUT_CLK(clk), .OUTPUT_ENABLE(), .D_OUT_0(w), .D_OUT_1(1'b0), .D_IN_0(), .D_IN_1() ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_pll40_2_pad.v000066400000000000000000000030311276746530600240630ustar00rootroot00000000000000module top( input PACKAGEPIN, output [1:0] PLLOUTCORE, output [1:0] PLLOUTGLOBAL, input EXTFEEDBACK, input [7:0] DYNAMICDELAY, output LOCK, input BYPASS, input RESETB, input LATCHINPUTVALUE, //Test Pins output SDO, input SDI, input SCLK ); SB_PLL40_2_PAD #( .FEEDBACK_PATH("DELAY"), // .FEEDBACK_PATH("SIMPLE"), // .FEEDBACK_PATH("PHASE_AND_DELAY"), // .FEEDBACK_PATH("EXTERNAL"), .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), .PLLOUT_SELECT_PORTB("GENCLK"), // .PLLOUT_SELECT_PORTB("GENCLK_HALF"), // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"), // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"), .SHIFTREG_DIV_MODE(1'b0), .FDA_FEEDBACK(4'b1111), .FDA_RELATIVE(4'b1111), .DIVR(4'b0000), .DIVF(7'b0000000), .DIVQ(3'b001), .FILTER_RANGE(3'b000), .ENABLE_ICEGATE_PORTA(1'b0), .ENABLE_ICEGATE_PORTB(1'b0), .TEST_MODE(1'b0) ) uut ( .PACKAGEPIN (PACKAGEPIN ), .PLLOUTCOREA (PLLOUTCORE [0]), .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), .PLLOUTCOREB (PLLOUTCORE [1]), .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), .EXTFEEDBACK (EXTFEEDBACK ), .DYNAMICDELAY (DYNAMICDELAY ), .LOCK (LOCK ), .BYPASS (BYPASS ), .RESETB (RESETB ), .LATCHINPUTVALUE(LATCHINPUTVALUE), .SDO (SDO ), .SDI (SDI ), .SCLK (SCLK ) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_pll40_2f_core.v000066400000000000000000000033031276746530600244170ustar00rootroot00000000000000module top( input REFERENCECLK, output [1:0] PLLOUTCORE, output [1:0] PLLOUTGLOBAL, input EXTFEEDBACK, input [7:0] DYNAMICDELAY, output LOCK, input BYPASS, input RESETB, input LATCHINPUTVALUE, //Test Pins output SDO, input SDI, input SCLK ); SB_PLL40_2F_CORE #( .FEEDBACK_PATH("DELAY"), // .FEEDBACK_PATH("SIMPLE"), // .FEEDBACK_PATH("PHASE_AND_DELAY"), // .FEEDBACK_PATH("EXTERNAL"), .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), .PLLOUT_SELECT_PORTA("GENCLK"), // .PLLOUT_SELECT_PORTA("GENCLK_HALF"), // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"), // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"), .PLLOUT_SELECT_PORTB("GENCLK"), // .PLLOUT_SELECT_PORTB("GENCLK_HALF"), // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"), // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"), .SHIFTREG_DIV_MODE(1'b0), .FDA_FEEDBACK(4'b1111), .FDA_RELATIVE(4'b1111), .DIVR(4'b0000), .DIVF(7'b0000000), .DIVQ(3'b001), .FILTER_RANGE(3'b000), .ENABLE_ICEGATE_PORTA(1'b0), .ENABLE_ICEGATE_PORTB(1'b0), .TEST_MODE(1'b0) ) uut ( .REFERENCECLK (REFERENCECLK ), .PLLOUTCOREA (PLLOUTCORE [0]), .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), .PLLOUTCOREB (PLLOUTCORE [1]), .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), .EXTFEEDBACK (EXTFEEDBACK ), .DYNAMICDELAY (DYNAMICDELAY ), .LOCK (LOCK ), .BYPASS (BYPASS ), .RESETB (RESETB ), .LATCHINPUTVALUE(LATCHINPUTVALUE), .SDO (SDO ), .SDI (SDI ), .SCLK (SCLK ) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_pll40_2f_pad.v000066400000000000000000000033001276746530600242300ustar00rootroot00000000000000module top( input PACKAGEPIN, output [1:0] PLLOUTCORE, output [1:0] PLLOUTGLOBAL, input EXTFEEDBACK, input [7:0] DYNAMICDELAY, output LOCK, input BYPASS, input RESETB, input LATCHINPUTVALUE, //Test Pins output SDO, input SDI, input SCLK ); SB_PLL40_2F_PAD #( .FEEDBACK_PATH("DELAY"), // .FEEDBACK_PATH("SIMPLE"), // .FEEDBACK_PATH("PHASE_AND_DELAY"), // .FEEDBACK_PATH("EXTERNAL"), .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), .PLLOUT_SELECT_PORTA("GENCLK"), // .PLLOUT_SELECT_PORTA("GENCLK_HALF"), // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"), // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"), .PLLOUT_SELECT_PORTB("GENCLK"), // .PLLOUT_SELECT_PORTB("GENCLK_HALF"), // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"), // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"), .SHIFTREG_DIV_MODE(1'b0), .FDA_FEEDBACK(4'b1111), .FDA_RELATIVE(4'b1111), .DIVR(4'b0000), .DIVF(7'b0000000), .DIVQ(3'b001), .FILTER_RANGE(3'b000), .ENABLE_ICEGATE_PORTA(1'b0), .ENABLE_ICEGATE_PORTB(1'b0), .TEST_MODE(1'b0) ) uut ( .PACKAGEPIN (PACKAGEPIN ), .PLLOUTCOREA (PLLOUTCORE [0]), .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), .PLLOUTCOREB (PLLOUTCORE [1]), .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), .EXTFEEDBACK (EXTFEEDBACK ), .DYNAMICDELAY (DYNAMICDELAY ), .LOCK (LOCK ), .BYPASS (BYPASS ), .RESETB (RESETB ), .LATCHINPUTVALUE(LATCHINPUTVALUE), .SDO (SDO ), .SDI (SDI ), .SCLK (SCLK ) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_pll40_core.v000066400000000000000000000026071276746530600240360ustar00rootroot00000000000000module top( input REFERENCECLK, output PLLOUTCORE, output PLLOUTGLOBAL, input EXTFEEDBACK, input [7:0] DYNAMICDELAY, output LOCK, input BYPASS, input RESETB, input LATCHINPUTVALUE, //Test Pins output SDO, input SDI, input SCLK ); SB_PLL40_CORE #( .FEEDBACK_PATH("DELAY"), // .FEEDBACK_PATH("SIMPLE"), // .FEEDBACK_PATH("PHASE_AND_DELAY"), // .FEEDBACK_PATH("EXTERNAL"), .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), .PLLOUT_SELECT("GENCLK"), // .PLLOUT_SELECT("GENCLK_HALF"), // .PLLOUT_SELECT("SHIFTREG_90deg"), // .PLLOUT_SELECT("SHIFTREG_0deg"), .SHIFTREG_DIV_MODE(1'b0), .FDA_FEEDBACK(4'b1111), .FDA_RELATIVE(4'b1111), .DIVR(4'b0000), .DIVF(7'b0000000), .DIVQ(3'b001), .FILTER_RANGE(3'b000), .ENABLE_ICEGATE(1'b0), .TEST_MODE(1'b0) ) uut ( .REFERENCECLK (REFERENCECLK ), .PLLOUTCORE (PLLOUTCORE ), .PLLOUTGLOBAL (PLLOUTGLOBAL ), .EXTFEEDBACK (EXTFEEDBACK ), .DYNAMICDELAY (DYNAMICDELAY ), .LOCK (LOCK ), .BYPASS (BYPASS ), .RESETB (RESETB ), .LATCHINPUTVALUE(LATCHINPUTVALUE), .SDO (SDO ), .SDI (SDI ), .SCLK (SCLK ) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_pll40_pad.v000066400000000000000000000026051276746530600236500ustar00rootroot00000000000000module top( input PACKAGEPIN, output PLLOUTCORE, output PLLOUTGLOBAL, input EXTFEEDBACK, input [7:0] DYNAMICDELAY, output LOCK, input BYPASS, input RESETB, input LATCHINPUTVALUE, //Test Pins output SDO, input SDI, input SCLK ); SB_PLL40_PAD #( .FEEDBACK_PATH("DELAY"), // .FEEDBACK_PATH("SIMPLE"), // .FEEDBACK_PATH("PHASE_AND_DELAY"), // .FEEDBACK_PATH("EXTERNAL"), .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), .PLLOUT_SELECT("GENCLK"), // .PLLOUT_SELECT("GENCLK_HALF"), // .PLLOUT_SELECT("SHIFTREG_90deg"), // .PLLOUT_SELECT("SHIFTREG_0deg"), .SHIFTREG_DIV_MODE(1'b0), .FDA_FEEDBACK(4'b1111), .FDA_RELATIVE(4'b1111), .DIVR(4'b0000), .DIVF(7'b0000000), .DIVQ(3'b001), .FILTER_RANGE(3'b000), .ENABLE_ICEGATE(1'b0), .TEST_MODE(1'b0) ) uut ( .PACKAGEPIN (PACKAGEPIN ), .PLLOUTCORE (PLLOUTCORE ), .PLLOUTGLOBAL (PLLOUTGLOBAL ), .EXTFEEDBACK (EXTFEEDBACK ), .DYNAMICDELAY (DYNAMICDELAY ), .LOCK (LOCK ), .BYPASS (BYPASS ), .RESETB (RESETB ), .LATCHINPUTVALUE(LATCHINPUTVALUE), .SDO (SDO ), .SDI (SDI ), .SCLK (SCLK ) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_ram40.pcf000066400000000000000000000001641276746530600233150ustar00rootroot00000000000000set_location lut 7 21 0 set_location ram40_00 8 21 0 set_location ram40_12 8 19 0 set_location ram40_33 8 17 0 fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_ram40.v000066400000000000000000000027441276746530600230200ustar00rootroot00000000000000// ICEDEV=hx8k-ct256 bash ../icecube.sh sb_ram40.v // ../../icebox/icebox_vlog.py -P sb_ram40.psb sb_ram40.txt // ../../icebox/icebox_explain.py -t '7 21' sb_ram40.txt module top ( input [10:0] WADDR, input [10:0] RADDR, input [15:0] MASK, input [15:0] WDATA, output [15:0] RDATA_0, output [ 7:0] RDATA_1, output [ 1:0] RDATA_3, input WE, WCLKE, WCLK, input RE, RCLKE, RCLK, output X ); // Write Mode 0: 8 Bit ADDR, 16 Bit DATA, MASK // Write Mode 1: 9 Bit ADDR, 8 Bit DATA, NO MASK // Write Mode 2: 10 Bit ADDR, 4 Bit DATA, NO MASK // Write Mode 3: 11 Bit ADDR, 2 Bit DATA, NO MASK SB_RAM40_4K #( .READ_MODE(0), .WRITE_MODE(0) ) ram40_00 ( .WADDR(WADDR[7:0]), .RADDR(RADDR[7:0]), .MASK(MASK), .WDATA(WDATA), .RDATA(RDATA_0), .WE(WE), .WCLKE(WCLKE), .WCLK(WCLK), .RE(RE), .RCLKE(RCLKE), .RCLK(RCLK) ); SB_RAM40_4K #( .READ_MODE(1), .WRITE_MODE(2) ) ram40_12 ( .WADDR(WADDR[9:0]), .RADDR(RADDR[8:0]), .WDATA(WDATA[3:0]), .RDATA(RDATA_1), .WE(WE), .WCLKE(WCLKE), .WCLK(WCLK), .RE(RE), .RCLKE(RCLKE), .RCLK(RCLK) ); SB_RAM40_4K #( .READ_MODE(3), .WRITE_MODE(3) ) ram40_33 ( .WADDR(WADDR), .RADDR(RADDR), .WDATA(WDATA[1:0]), .RDATA(RDATA_3), .WE(WE), .WCLKE(WCLKE), .WCLK(WCLK), .RE(RE), .RCLKE(RCLKE), .RCLK(RCLK) ); SB_LUT4 #( .LUT_INIT(16'b 1000_0000_0000_0000) ) lut ( .O(X), .I0(RDATA_0[0]), .I1(RDATA_0[6]), .I2(RDATA_0[8]), .I3(RDATA_0[14]) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/sb_warmboot.v000066400000000000000000000001521276746530600237160ustar00rootroot00000000000000module top(input boot, s0, s1); SB_WARMBOOT warmboot ( .BOOT(boot), .S0(s0), .S1(s1) ); endmodule fpga-icestorm-0~20160913git266e758/icefuzz/tests/test_pio.sh000066400000000000000000000027621276746530600234040ustar00rootroot00000000000000#!/bin/bash set -e lattice_simlib="/opt/lscc/iCEcube2.2014.12/verilog/sb_ice_syn.v" mkdir -p test_pio.work cd test_pio.work for NEGTRIG in 0 1; do for INTYPE in 00 01 10 11; do for OUTTYPE in 0000 0110 1010 1110 0101 1001 1101 \ 0100 1000 1100 0111 1011 1111; do pf="test_pio_${OUTTYPE}${INTYPE}${NEGTRIG}" echo "Testing ${pf}..." if ! test -f ${pf}.bin; then cat > ${pf}.v <<- EOT module top ( inout pin, input latch_in, input clk_en, input clk_in, input clk_out, input oen, input dout_0, input dout_1, output din_0, output din_1, output global ); SB_GB_IO #( .PIN_TYPE(6'b${OUTTYPE}${INTYPE}), .PULLUP(1'b0), .NEG_TRIGGER(1'b${NEGTRIG}), .IO_STANDARD("SB_LVCMOS") ) pin_gb_io ( .PACKAGE_PIN(pin), .GLOBAL_BUFFER_OUTPUT(global), .LATCH_INPUT_VALUE(latch_in), .CLOCK_ENABLE(clk_en), .INPUT_CLK(clk_in), .OUTPUT_CLK(clk_out), .OUTPUT_ENABLE(oen), .D_OUT_0(dout_0), .D_OUT_1(dout_1), .D_IN_0(din_0), .D_IN_1(din_1) ); endmodule EOT bash ../../icecube.sh ${pf}.v > ${pf}.log 2>&1 fi python3 ../../../icebox/icebox_vlog.py -P ${pf}.psb ${pf}.asc > ${pf}_out.v iverilog -D"VCDFILE=\"${pf}_tb.vcd\"" -DINTYPE=${INTYPE} -o ${pf}_tb \ -s testbench ../test_pio_tb.v ${pf}.v ${pf}_out.v $lattice_simlib 2> /dev/null ./${pf}_tb > ${pf}_tb.txt if grep ERROR ${pf}_tb.txt; then exit 1; fi done; done; done echo "All tests passed." fpga-icestorm-0~20160913git266e758/icefuzz/tests/test_pio_tb.v000066400000000000000000000066041276746530600237230ustar00rootroot00000000000000module testbench; reg pin_reg; reg latch_in; reg clk_en; reg clk_in; reg clk_out; reg oen; reg dout_0; reg dout_1; wire gold_pin; wire gold_global; wire gold_din_0; wire gold_din_1; wire gate_pin; wire gate_global; wire gate_din_0; wire gate_din_1; top gold ( .pin (gold_pin ), .global (gold_global), .latch_in(latch_in ), .clk_en (clk_en ), .clk_in (clk_in ), .clk_out (clk_out ), .oen (oen ), .dout_0 (dout_0 ), .dout_1 (dout_1 ), .din_0 (gold_din_0 ), .din_1 (gold_din_1 ) ); chip gate ( .pin (gate_pin ), .global (gate_global), .latch_in(latch_in ), .clk_en (clk_en ), .clk_in (clk_in ), .clk_out (clk_out ), .oen (oen ), .dout_0 (dout_0 ), .dout_1 (dout_1 ), .din_0 (gate_din_0 ), .din_1 (gate_din_1 ) ); assign gold_pin = pin_reg; assign gate_pin = pin_reg; reg [63:0] xorshift64_state = 64'd88172645463325252; task xorshift64_next; begin // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14). xorshift64_state = xorshift64_state ^ (xorshift64_state << 13); xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7); xorshift64_state = xorshift64_state ^ (xorshift64_state << 17); end endtask reg error = 0; integer rndval; initial begin `ifdef VCDFILE $dumpfile(`VCDFILE); $dumpvars(0, testbench); `endif pin_reg <= 0; latch_in <= 0; clk_en <= 1; clk_in <= 0; clk_out <= 0; oen <= 0; dout_0 <= 0; dout_1 <= 0; pin_reg <= 0; repeat (5) #10 clk_in <= ~clk_in; repeat (5) #10 clk_out <= ~clk_out; pin_reg <= 1; repeat (5) #10 clk_in <= ~clk_in; repeat (5) #10 clk_out <= ~clk_out; pin_reg <= 'bz; repeat (5) #10 clk_in <= ~clk_in; repeat (5) #10 clk_out <= ~clk_out; repeat (1000) begin if ('b `INTYPE == 0) begin error = {gold_pin, gold_global, gold_din_0, gate_din_1} !== {gate_pin, gate_global, gate_din_0, gate_din_1}; $display({"pin=%b%b, global=%b%b, latch_in=%b, clk_en=%b, clk_in=%b, clk_out=%b, ", "oen=%b, dout_0=%b, dout_1=%b, din_0=%b%b, din_1=%b%b %s"}, gold_pin, gate_pin, gold_global, gate_global, latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1, gold_din_0, gate_din_0, gold_din_1, gate_din_1, error ? "ERROR" : "OK"); end else begin error = {gold_pin, gold_global, gold_din_0} !== {gate_pin, gate_global, gate_din_0}; $display({"pin=%b%b, global=%b%b, latch_in=%b, clk_en=%b, clk_in=%b, clk_out=%b, ", "oen=%b, dout_0=%b, dout_1=%b, din_0=%b%b %s"}, gold_pin, gate_pin, gold_global, gate_global, latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1, gold_din_0, gate_din_0, error ? "ERROR" : "OK"); end xorshift64_next; rndval = (xorshift64_state >> 16) & 'hffff; case (xorshift64_state % 5) 0: pin_reg <= 1'bz; 1: pin_reg <= 1'b0; 2: pin_reg <= 1'b1; `ifdef DISABLED // Lattice SB_IO clk_en model is b0rken // IceBox latch_in routing is non-existing default: {latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1} <= {latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1} ^ (1 << (rndval % 7)); `else default: {latch_in, clk_in, clk_out, oen, dout_0, dout_1} <= {latch_in, clk_in, clk_out, oen, dout_0, dout_1} ^ (1 << (rndval % 6)); `endif endcase #10; end end endmodule fpga-icestorm-0~20160913git266e758/icefuzz/timings.py000066400000000000000000000341301276746530600220760ustar00rootroot00000000000000#!/usr/bin/env python3 import getopt, sys, re ignore_cells = set([ "ADTTRIBUF", "DL", "GIOBUG", "LUT_MUX", "MUX4", "PLL40_2_FEEDBACK_PATH_DELAY", "PLL40_2_FEEDBACK_PATH_EXTERNAL", "PLL40_2_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_2_FEEDBACK_PATH_SIMPLE", "PLL40_2F_FEEDBACK_PATH_DELAY", "PLL40_2F_FEEDBACK_PATH_EXTERNAL", "PLL40_2F_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_2F_FEEDBACK_PATH_SIMPLE", "PLL40_FEEDBACK_PATH_DELAY", "PLL40_FEEDBACK_PATH_EXTERNAL", "PLL40_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_FEEDBACK_PATH_SIMPLE", "PRE_IO_PIN_TYPE", "sync_clk_enable", "TRIBUF" ]) database = dict() sdf_inputs = list() txt_inputs = list() output_mode = "txt" label = "unknown" edgefile = None def usage(): print(""" Usage: python3 timings.py [options] [sdf_file..] -t filename read TXT file -l label label for HTML file title -h edgefile output HTML, use specified edge file -s output SDF (not TXT) format """) sys.exit(0) try: opts, args = getopt.getopt(sys.argv[1:], "t:l:h:s") except: usage() for o, a in opts: if o == "-t": txt_inputs.append(a) elif o == "-l": label = a elif o == "-h": output_mode = "html" edgefile = a elif o == "-s": output_mode = "sdf" else: usage() sdf_inputs += args convert = lambda text: int(text) if text.isdigit() else text.lower() alphanum_key = lambda key: [ convert(c) for c in re.split('([0-9]+)', key) ] alphanum_key_list = lambda l: [len(l)] + [ alphanum_key(s) for s in l ] def skip_whitespace(text, cursor): while cursor < len(text) and text[cursor] in [" ", "\t", "\r", "\n"]: cursor += 1 return cursor def parse_sdf(text, cursor): cursor = skip_whitespace(text, cursor) if cursor < len(text) and text[cursor] == "(": expr = [] cursor += 1 while cursor < len(text) and text[cursor] != ")": child, cursor = parse_sdf(text, cursor) expr.append(child) cursor = skip_whitespace(text, cursor) return expr, cursor+1 if cursor < len(text) and text[cursor] == '"': expr = '"' cursor += 1 while cursor < len(text) and text[cursor] != '"': expr += text[cursor] cursor += 1 return expr + '"', cursor+1 expr = "" while cursor < len(text) and text[cursor] not in [" ", "\t", "\r", "\n", "(", ")"]: expr += text[cursor] cursor += 1 return expr, cursor def sdf_to_string(expr): if type(expr) is list: tokens = [] tokens.append("(") first_child = True for child in expr: if not first_child: tokens.append(" ") tokens.append(sdf_to_string(child)) first_child = False tokens.append(")") return "".join(tokens) else: return expr def dump_sdf(expr, indent=""): if type(expr) is list: if len(expr) > 0 and expr[0] in ["IOPATH", "SETUP", "HOLD", "CELLTYPE", "INSTANCE", "SDFVERSION", "DESIGN", "DATE", "VENDOR", "DIVIDER", "TIMESCALE", "RECOVERY", "REMOVAL"]: print(indent + sdf_to_string(expr)) else: print("%s(%s" % (indent, expr[0] if len(expr) > 0 else "")) for child in expr[1:]: dump_sdf(child, indent + " ") print("%s)" % indent) else: print("%s%s" % (indent, expr)) def generalize_instances(expr): if type(expr) is list: if len(expr) == 2 and expr[0] == "INSTANCE": expr[1] = "*" for child in expr: generalize_instances(child) def list_to_tuple(expr): if type(expr) is list: tup = [] for child in expr: tup.append(list_to_tuple(child)) return tuple(tup) return expr def uniquify_cells(expr): cache = set() filtered_expr = [] for child in expr: t = list_to_tuple(child) if t not in cache: filtered_expr.append(child) cache.add(t) return filtered_expr def rewrite_celltype(celltype): if celltype.startswith("PRE_IO_PIN_TYPE_"): celltype = "PRE_IO_PIN_TYPE" if celltype.startswith("Span4Mux"): if celltype == "Span4Mux": celltype = "Span4Mux_v4" elif celltype == "Span4Mux_v": celltype = "Span4Mux_v4" elif celltype == "Span4Mux_h": celltype = "Span4Mux_h4" else: match = re.match("Span4Mux_s(.*)_(h|v)", celltype) if match: celltype = "Span4Mux_%c%d" % (match.group(2), int(match.group(1))) if celltype.startswith("Span12Mux"): if celltype == "Span12Mux": celltype = "Span12Mux_v12" elif celltype == "Span12Mux_v": celltype = "Span12Mux_v12" elif celltype == "Span12Mux_h": celltype = "Span12Mux_h12" else: match = re.match("Span12Mux_s(.*)_(h|v)", celltype) if match: celltype = "Span12Mux_%c%d" % (match.group(2), int(match.group(1))) return celltype def add_entry(celltype, entry): entry = sdf_to_string(entry) entry = entry.replace("(posedge ", "posedge:") entry = entry.replace("(negedge ", "negedge:") entry = entry.replace("(", "") entry = entry.replace(")", "") entry = entry.split() if celltype.count("FEEDBACK") == 0 and entry[0] == "IOPATH" and entry[2].startswith("PLLOUT"): entry[3] = "*:*:*" entry[4] = "*:*:*" database[celltype].add(tuple(entry)) ########################################### # Parse SDF input files for filename in sdf_inputs: print("### reading SDF file %s" % filename, file=sys.stderr) intext = [] with open(filename, "r") as f: for line in f: line = re.sub("//.*", "", line) intext.append(line) sdfdata, _ = parse_sdf("".join(intext), 0) generalize_instances(sdfdata) sdfdata = uniquify_cells(sdfdata) for cell in sdfdata: if cell[0] != "CELL": continue celltype = None for stmt in cell: if stmt[0] == "CELLTYPE": celltype = rewrite_celltype(stmt[1][1:-1]) database.setdefault(celltype, set()) if stmt[0] == "DELAY": assert stmt[1][0] == "ABSOLUTE" for entry in stmt[1][1:]: assert entry[0] == "IOPATH" add_entry(celltype, entry) if stmt[0] == "TIMINGCHECK": for entry in stmt[1:]: add_entry(celltype, entry) ########################################### # Parse TXT input files for filename in txt_inputs: print("### reading TXT file %s" % filename, file=sys.stderr) with open(filename, "r") as f: celltype = None for line in f: line = line.split() if len(line) > 1: if line[0] == "CELL": celltype = rewrite_celltype(line[1]) database.setdefault(celltype, set()) else: add_entry(celltype, line) ########################################### # Filter database for celltype in ignore_cells: if celltype in database: del database[celltype] ########################################### # Create SDF output if output_mode == "sdf": print("(DELAYFILE") print(" (SDFVERSION \"3.0\")") print(" (TIMESCALE 1ps)") def format_entry(entry): text = [] for i in range(len(entry)): if i > 2: text.append("(%s)" % entry[i]) elif entry[i].startswith("posedge:"): text.append("(posedge %s)" % entry[i].replace("posedge:", "")) elif entry[i].startswith("negedge:"): text.append("(negedge %s)" % entry[i].replace("negedge:", "")) else: text.append(entry[i]) return " ".join(text) for celltype in sorted(database, key=alphanum_key): print(" (CELL") print(" (CELLTYPE \"%s\")" % celltype) print(" (INSTANCE *)") delay_abs_entries = list() timingcheck_entries = list() for entry in sorted(database[celltype], key=alphanum_key_list): if entry[0] == "IOPATH": delay_abs_entries.append(entry) else: timingcheck_entries.append(entry) if len(delay_abs_entries) != 0: print(" (DELAY") print(" (ABSOLUTE") for entry in delay_abs_entries: print(" (%s)" % format_entry(entry)) print(" )") print(" )") if len(timingcheck_entries) != 0: print(" (TIMINGCHECK") for entry in timingcheck_entries: print(" (%s)" % format_entry(entry)) print(" )") print(" )") print(")") ########################################### # Create TXT output if output_mode == "txt": for celltype in sorted(database, key=alphanum_key): print("CELL %s" % celltype) entries_lens = list() for entry in database[celltype]: for i in range(len(entry)): if i < len(entries_lens): entries_lens[i] = max(entries_lens[i], len(entry[i])) else: entries_lens.append(len(entry[i])) for entry in sorted(database[celltype], key=alphanum_key_list): for i in range(len(entry)): print("%s%-*s" % (" " if i != 0 else "", entries_lens[i] if i != len(entry)-1 else 0, entry[i]), end="") print() print() ########################################### # Create HTML output if output_mode == "html": print("

IceStorm Timing Model: %s

" % label) edge_celltypes = set() source_by_sink_desc = dict() sink_by_source_desc = dict() with open(edgefile, "r") as f: for line in f: source, sink = line.split() source_cell, source_port = source.split(".") sink_cell, sink_port = sink.split(".") source_cell = rewrite_celltype(source_cell) sink_cell = rewrite_celltype(sink_cell) assert source_cell not in ignore_cells assert sink_cell not in ignore_cells if source_cell in ["GND", "VCC"]: continue source_by_sink_desc.setdefault(sink_cell, set()) sink_by_source_desc.setdefault(source_cell, set()) source_by_sink_desc[sink_cell].add((sink_port, source_cell, source_port)) sink_by_source_desc[source_cell].add((source_port, sink_cell, sink_port)) edge_celltypes.add(source_cell) edge_celltypes.add(sink_cell) print("
    ") for celltype in sorted(database, key=alphanum_key): if celltype not in edge_celltypes: print("### ignoring unused cell type %s" % celltype, file=sys.stderr) else: print("
  • %s
    • " % (celltype, celltype)) print("
") for celltype in sorted(database, key=alphanum_key): if celltype not in edge_celltypes: continue print("

") print("

%s

" % (celltype, celltype)) if celltype in source_by_sink_desc: print("

Sources driving this cell type:

") print("") print("") for entry in sorted(source_by_sink_desc[celltype], key=alphanum_key_list): print("" % (entry[0], entry[1], entry[1], entry[2])) print("
Input PortSource CellSource Port
%s%s%s
") if celltype in sink_by_source_desc: print("

Sinks driven by this cell type:

") print("") print("") for entry in sorted(sink_by_source_desc[celltype], key=alphanum_key_list): print("" % (entry[0], entry[1], entry[1], entry[2])) print("
Output PortSink CellSink Port
%s%s%s
") delay_abs_entries = list() timingcheck_entries = list() for entry in sorted(database[celltype], key=alphanum_key_list): if entry[0] == "IOPATH": delay_abs_entries.append(entry) else: timingcheck_entries.append(entry) if len(delay_abs_entries) > 0: print("

Propagation Delays:

") print("") print("") print("") print("") for entry in delay_abs_entries: print("" % (entry[1].replace(":", " "), entry[2].replace(":", " ")), end="") print("" % tuple(entry[3].split(":")), end="") print("" % tuple(entry[4].split(":")), end="") print("") print("
Input PortOutput PortLow-High TransitionHigh-Low Transition
MinTypMaxMinTypMax
%s%s%s%s%s%s%s%s
") if len(timingcheck_entries) > 0: print("

Timing Checks:

") print("") print("") print("") print("") for entry in timingcheck_entries: print("" % (entry[0], entry[1].replace(":", " "), entry[2].replace(":", " ")), end="") print("" % tuple(entry[3].split(":")), end="") print("") print("
Check TypeInput PortOutput PortTiming
MinTypMax
%s%s%s%s%s%s
") fpga-icestorm-0~20160913git266e758/icefuzz/timings_hx1k.txt000066400000000000000000000641141276746530600232250ustar00rootroot00000000000000CELL CascadeBuf IOPATH I O 118.382:130.906:147.283 146.568:162.074:182.35 CELL CascadeMux IOPATH I O 0:0:0 0:0:0 CELL CEMux IOPATH I O 484.803:536.092:603.157 445.342:492.457:554.063 CELL ClkMux IOPATH I O 248.039:274.28:308.592 186.029:205.71:231.444 CELL gio2CtrlBuf IOPATH I O 0:0:0 0:0:0 CELL Glb2LocalMux IOPATH I O 360.783:398.952:448.861 287.499:317.915:357.686 CELL GlobalMux IOPATH I O 124.019:137.14:154.296 62.0096:68.5699:77.148 CELL ICE_CARRY_IN_MUX IOPATH carryinitin carryinitout 157.843:174.542:196.377 140.931:155.841:175.336 CELL ICE_GB IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 496.077:548.56:617.184 450.979:498.69:561.077 CELL InMux IOPATH I O 208.578:230.644:259.498 174.754:193.243:217.417 CELL INV IOPATH I O 0:0:0 0:0:0 CELL IO_PAD IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990 IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942 IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540 CELL IoInMux IOPATH I O 208.578:230.644:259.498 174.754:193.243:217.417 CELL IoSpan4Mux IOPATH I O 231.127:255.579:287.552 259.313:286.747:322.619 CELL LocalMux IOPATH I O 264.95:292.981:329.632 248.039:274.28:308.592 CELL LogicCell40 HOLD negedge:ce posedge:clk 0:0:0 HOLD negedge:in0 posedge:clk 0:0:0 HOLD negedge:in1 posedge:clk 0:0:0 HOLD negedge:in2 posedge:clk 0:0:0 HOLD negedge:in3 posedge:clk 0:0:0 HOLD negedge:sr posedge:clk -158.688:-175.477:-197.429 HOLD posedge:ce posedge:clk 0:0:0 HOLD posedge:in0 posedge:clk 0:0:0 HOLD posedge:in1 posedge:clk 0:0:0 HOLD posedge:in2 posedge:clk 0:0:0 HOLD posedge:in3 posedge:clk 0:0:0 HOLD posedge:sr posedge:clk -143.975:-159.207:-179.124 RECOVERY negedge:sr posedge:clk 128.36:141.94:159.696 RECOVERY posedge:sr posedge:clk 0:0:0 REMOVAL negedge:sr posedge:clk 0:0:0 REMOVAL posedge:sr posedge:clk 0:0:0 SETUP negedge:ce posedge:clk 0:0:0 SETUP negedge:in0 posedge:clk 321.323:355.317:399.767 SETUP negedge:in1 posedge:clk 304.411:336.616:378.727 SETUP negedge:in2 posedge:clk 259.313:286.747:322.619 SETUP negedge:in3 posedge:clk 174.754:193.243:217.417 SETUP negedge:sr posedge:clk 112.745:124.673:140.269 SETUP posedge:ce posedge:clk 0:0:0 SETUP posedge:in0 posedge:clk 377.695:417.653:469.902 SETUP posedge:in1 posedge:clk 321.323:355.317:399.767 SETUP posedge:in2 posedge:clk 298.774:330.382:371.713 SETUP posedge:in3 posedge:clk 219.852:243.112:273.525 SETUP posedge:sr posedge:clk 163.48:180.775:203.39 IOPATH carryin carryout 101.47:112.205:126.242 84.5586:93.5045:105.202 IOPATH in0 lcout 360.783:398.952:448.861 310.048:342.85:385.74 IOPATH in0 ltout 293.136:324.149:364.7 310.048:342.85:385.74 IOPATH in1 carryout 208.578:230.644:259.498 197.303:218.177:245.471 IOPATH in1 lcout 321.323:355.317:399.767 304.411:336.616:378.727 IOPATH in1 ltout 259.313:286.747:322.619 304.411:336.616:378.727 IOPATH in2 carryout 186.029:205.71:231.444 107.108:118.439:133.256 IOPATH in2 lcout 304.411:336.616:378.727 281.862:311.682:350.673 IOPATH in2 ltout 248.039:274.28:308.592 276.225:305.448:343.659 IOPATH in3 lcout 253.676:280.513:315.606 231.127:255.579:287.552 IOPATH in3 ltout 214.215:236.878:266.511 219.852:243.112:273.525 IOPATH posedge:clk lcout 434.067:479.99:540.036 434.067:479.99:540.036 IOPATH sr lcout 0:0:0 481.612:532.564:599.188 IOPATH sr lcout 481.589:532.539:599.16 0:0:0 CELL Odrv4 IOPATH I O 281.862:311.682:350.673 298.774:330.382:371.713 CELL Odrv12 IOPATH I O 394.607:436.354:490.942 434.067:479.99:540.036 CELL PLL40 IOPATH PLLIN PLLOUTCORE *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:* CELL PLL40_2 IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PLL40_2F IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PRE_IO HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:PADIN negedge:INPUTCLK 0:0:0 HOLD negedge:PADIN posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:PADIN negedge:INPUTCLK 0:0:0 HOLD posedge:PADIN posedge:INPUTCLK 0:0:0 SETUP negedge:CLOCKENABLE posedge:INPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:DOUT0 posedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:DOUT1 negedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:PADIN negedge:INPUTCLK 1316.46:1455.74:1637.85 SETUP negedge:PADIN posedge:INPUTCLK 1316.46:1455.74:1637.85 SETUP posedge:CLOCKENABLE posedge:INPUTCLK 62.0096:68.5699:77.148 SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:DOUT0 posedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:DOUT1 negedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:PADIN negedge:INPUTCLK 1322.1:1461.97:1644.87 SETUP posedge:PADIN posedge:INPUTCLK 1322.1:1461.97:1644.87 IOPATH DOUT0 PADOUT 1612.25:1782.82:2005.85 1798.28:1988.53:2237.29 IOPATH LATCHINPUTVALUE DIN0 276.225:305.448:343.659 298.774:330.382:371.713 IOPATH negedge:INPUTCLK DIN1 112.745:124.673:140.269 112.745:124.673:140.269 IOPATH negedge:OUTPUTCLK PADOUT 90.1958:99.7381:112.215 112.745:124.673:140.269 IOPATH OUTPUTENABLE PADOEN 140.931:155.841:175.336 169.117:187.009:210.404 IOPATH PADIN DIN0 496.077:548.56:617.184 372.058:411.42:462.888 IOPATH posedge:INPUTCLK DIN0 112.745:124.673:140.269 112.745:124.673:140.269 IOPATH posedge:OUTPUTCLK PADOEN 90.1958:99.7381:112.215 112.745:124.673:140.269 IOPATH posedge:OUTPUTCLK PADOUT 90.1958:99.7381:112.215 112.745:124.673:140.269 CELL PRE_IO_GBUF IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1132.07:1251.84:1408.44 1008.05:1114.7:1254.15 CELL SB_PLL40_2F_CORE IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:* CELL SB_PLL40_CORE IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:* CELL SB_RAM40_4K HOLD negedge:MASK[0] posedge:WCLK 0:0:0 HOLD negedge:MASK[1] posedge:WCLK 0:0:0 HOLD negedge:MASK[2] posedge:WCLK 0:0:0 HOLD negedge:MASK[3] posedge:WCLK 0:0:0 HOLD negedge:MASK[4] posedge:WCLK 0:0:0 HOLD negedge:MASK[5] posedge:WCLK 0:0:0 HOLD negedge:MASK[6] posedge:WCLK 0:0:0 HOLD negedge:MASK[7] posedge:WCLK 0:0:0 HOLD negedge:MASK[8] posedge:WCLK 0:0:0 HOLD negedge:MASK[9] posedge:WCLK 0:0:0 HOLD negedge:MASK[10] posedge:WCLK 0:0:0 HOLD negedge:MASK[11] posedge:WCLK 0:0:0 HOLD negedge:MASK[12] posedge:WCLK 0:0:0 HOLD negedge:MASK[13] posedge:WCLK 0:0:0 HOLD negedge:MASK[14] posedge:WCLK 0:0:0 HOLD negedge:MASK[15] posedge:WCLK 0:0:0 HOLD negedge:RADDR[0] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[1] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[2] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[3] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[4] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[5] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[6] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[7] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[8] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[9] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[10] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RCLKE posedge:RCLK 42.2793:46.7522:52.6009 HOLD negedge:RE posedge:RCLK 67.6469:74.8036:84.1615 HOLD negedge:WADDR[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WCLKE posedge:WCLK 21.9852:24.3112:27.3525 HOLD negedge:WDATA[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[11] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[12] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[13] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[14] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[15] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WE posedge:WCLK 39.4607:43.6354:49.0942 HOLD posedge:MASK[0] posedge:WCLK 0:0:0 HOLD posedge:MASK[1] posedge:WCLK 0:0:0 HOLD posedge:MASK[2] posedge:WCLK 0:0:0 HOLD posedge:MASK[3] posedge:WCLK 0:0:0 HOLD posedge:MASK[4] posedge:WCLK 0:0:0 HOLD posedge:MASK[5] posedge:WCLK 0:0:0 HOLD posedge:MASK[6] posedge:WCLK 0:0:0 HOLD posedge:MASK[7] posedge:WCLK 0:0:0 HOLD posedge:MASK[8] posedge:WCLK 0:0:0 HOLD posedge:MASK[9] posedge:WCLK 0:0:0 HOLD posedge:MASK[10] posedge:WCLK 0:0:0 HOLD posedge:MASK[11] posedge:WCLK 0:0:0 HOLD posedge:MASK[12] posedge:WCLK 0:0:0 HOLD posedge:MASK[13] posedge:WCLK 0:0:0 HOLD posedge:MASK[14] posedge:WCLK 0:0:0 HOLD posedge:MASK[15] posedge:WCLK 0:0:0 HOLD posedge:RADDR[0] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[1] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[2] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[3] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[4] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[5] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[6] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[7] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[8] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[9] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[10] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RCLKE posedge:RCLK 42.2793:46.7522:52.6009 HOLD posedge:RE posedge:RCLK 67.6469:74.8036:84.1615 HOLD posedge:WADDR[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WCLKE posedge:WCLK 21.9852:24.3112:27.3525 HOLD posedge:WDATA[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[11] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[12] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[13] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[14] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[15] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WE posedge:WCLK 39.4607:43.6354:49.0942 SETUP negedge:MASK[0] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[1] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[2] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[3] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[4] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[5] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[6] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[7] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[8] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[9] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[10] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[11] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[12] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[13] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[14] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[15] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:RADDR[0] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[1] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[2] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[3] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[4] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[5] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[6] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[7] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[8] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[9] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[10] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RCLKE posedge:RCLK 214.215:236.878:266.511 SETUP negedge:RE posedge:RCLK 78.9214:87.2708:98.1884 SETUP negedge:WADDR[0] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[1] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[2] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[3] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[4] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[5] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[6] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[7] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[8] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[9] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[10] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WCLKE posedge:WCLK 214.215:236.878:266.511 SETUP negedge:WDATA[0] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[1] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[2] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[3] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[4] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[5] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[6] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[7] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[8] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[9] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[10] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[11] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[12] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[13] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[14] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[15] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WE posedge:WCLK 107.108:118.439:133.256 SETUP posedge:MASK[0] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[1] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[2] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[3] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[4] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[5] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[6] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[7] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[8] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[9] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[10] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[11] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[12] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[13] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[14] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[15] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:RADDR[0] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[1] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[2] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[3] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[4] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[5] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[6] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[7] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[8] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[9] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[10] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RCLKE posedge:RCLK 214.215:236.878:266.511 SETUP posedge:RE posedge:RCLK 78.9214:87.2708:98.1884 SETUP posedge:WADDR[0] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[1] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[2] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[3] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[4] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[5] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[6] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[7] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[8] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[9] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[10] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WCLKE posedge:WCLK 214.215:236.878:266.511 SETUP posedge:WDATA[0] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[1] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[2] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[3] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[4] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[5] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[6] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[7] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[8] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[9] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[10] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[11] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[12] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[13] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[14] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[15] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WE posedge:WCLK 107.108:118.439:133.256 IOPATH posedge:RCLK RDATA[0] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[1] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[2] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[3] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[4] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[5] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[6] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[7] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[8] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[9] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[10] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[11] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[12] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[13] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[14] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[15] 1725:1907.49:2146.12 1725:1907.49:2146.12 CELL Sp12to4 IOPATH I O 343.872:380.251:427.821 360.783:398.952:448.861 CELL Span4Mux_h0 IOPATH I O 118.382:130.906:147.283 112.745:124.673:140.269 CELL Span4Mux_h1 IOPATH I O 140.931:155.841:175.336 135.294:149.607:168.323 CELL Span4Mux_h2 IOPATH I O 163.48:180.775:203.39 163.48:180.775:203.39 CELL Span4Mux_h3 IOPATH I O 186.029:205.71:231.444 186.029:205.71:231.444 CELL Span4Mux_h4 IOPATH I O 242.401:268.046:301.579 253.676:280.513:315.606 CELL Span4Mux_v0 IOPATH I O 163.48:180.775:203.39 152.205:168.308:189.363 CELL Span4Mux_v1 IOPATH I O 163.48:180.775:203.39 157.843:174.542:196.377 CELL Span4Mux_v2 IOPATH I O 202.941:224.411:252.484 202.941:224.411:252.484 CELL Span4Mux_v3 IOPATH I O 253.676:280.513:315.606 270.588:299.214:336.646 CELL Span4Mux_v4 IOPATH I O 281.862:311.682:350.673 298.774:330.382:371.713 CELL Span12Mux_h0 IOPATH I O 112.745:124.673:140.269 118.382:130.906:147.283 CELL Span12Mux_h1 IOPATH I O 107.108:118.439:133.256 107.108:118.439:133.256 CELL Span12Mux_h2 IOPATH I O 129.657:143.374:161.31 135.294:149.607:168.323 CELL Span12Mux_h3 IOPATH I O 135.294:149.607:168.323 146.568:162.074:182.35 CELL Span12Mux_h4 IOPATH I O 157.843:174.542:196.377 174.754:193.243:217.417 CELL Span12Mux_h5 IOPATH I O 186.029:205.71:231.444 208.578:230.644:259.498 CELL Span12Mux_h6 IOPATH I O 202.941:224.411:252.484 225.49:249.345:280.538 CELL Span12Mux_h7 IOPATH I O 231.127:255.579:287.552 259.313:286.747:322.619 CELL Span12Mux_h8 IOPATH I O 276.225:305.448:343.659 310.048:342.85:385.74 CELL Span12Mux_h9 IOPATH I O 315.685:349.083:392.754 349.509:386.485:434.834 CELL Span12Mux_h10 IOPATH I O 343.872:380.251:427.821 377.695:417.653:469.902 CELL Span12Mux_h11 IOPATH I O 377.695:417.653:469.902 422.793:467.522:526.009 CELL Span12Mux_h12 IOPATH I O 394.607:436.354:490.942 434.067:479.99:540.036 CELL Span12Mux_v0 IOPATH I O 78.9214:87.2708:98.1884 84.5586:93.5045:105.202 CELL Span12Mux_v1 IOPATH I O 84.5586:93.5045:105.202 84.5586:93.5045:105.202 CELL Span12Mux_v2 IOPATH I O 112.745:124.673:140.269 124.019:137.14:154.296 CELL Span12Mux_v3 IOPATH I O 118.382:130.906:147.283 135.294:149.607:168.323 CELL Span12Mux_v4 IOPATH I O 146.568:162.074:182.35 169.117:187.009:210.404 CELL Span12Mux_v5 IOPATH I O 191.666:211.943:238.458 214.215:236.878:266.511 CELL Span12Mux_v6 IOPATH I O 208.578:230.644:259.498 231.127:255.579:287.552 CELL Span12Mux_v7 IOPATH I O 225.49:249.345:280.538 253.676:280.513:315.606 CELL Span12Mux_v8 IOPATH I O 287.499:317.915:357.686 315.685:349.083:392.754 CELL Span12Mux_v9 IOPATH I O 304.411:336.616:378.727 338.234:374.018:420.807 CELL Span12Mux_v10 IOPATH I O 315.685:349.083:392.754 349.509:386.485:434.834 CELL Span12Mux_v11 IOPATH I O 332.597:367.784:413.794 366.421:405.186:455.875 CELL Span12Mux_v12 IOPATH I O 394.607:436.354:490.942 434.067:479.99:540.036 CELL SRMux IOPATH I O 372.058:411.42:462.888 287.499:317.915:357.686 fpga-icestorm-0~20160913git266e758/icefuzz/timings_hx8k.txt000066400000000000000000000641151276746530600232350ustar00rootroot00000000000000CELL CascadeBuf IOPATH I O 118.382:130.906:147.283 146.568:162.074:182.35 CELL CascadeMux IOPATH I O 0:0:0 0:0:0 CELL CEMux IOPATH I O 484.803:536.092:603.157 445.342:492.457:554.063 CELL ClkMux IOPATH I O 248.039:274.28:308.592 186.029:205.71:231.444 CELL gio2CtrlBuf IOPATH I O 0:0:0 0:0:0 CELL Glb2LocalMux IOPATH I O 360.783:398.952:448.861 287.499:317.915:357.686 CELL GlobalMux IOPATH I O 124.019:137.14:154.296 62.0096:68.5699:77.148 CELL ICE_CARRY_IN_MUX IOPATH carryinitin carryinitout 157.843:174.542:196.377 140.931:155.841:175.336 CELL ICE_GB IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 496.077:548.56:617.184 450.979:498.69:561.077 CELL InMux IOPATH I O 208.578:230.644:259.498 174.754:193.243:217.417 CELL INV IOPATH I O 0:0:0 0:0:0 CELL IO_PAD IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990 IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942 IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540 CELL IoInMux IOPATH I O 208.578:230.644:259.498 174.754:193.243:217.417 CELL IoSpan4Mux IOPATH I O 231.127:255.579:287.552 259.313:286.747:322.619 CELL LocalMux IOPATH I O 264.95:292.981:329.632 248.039:274.28:308.592 CELL LogicCell40 HOLD negedge:ce posedge:clk 0:0:0 HOLD negedge:in0 posedge:clk 0:0:0 HOLD negedge:in1 posedge:clk 0:0:0 HOLD negedge:in2 posedge:clk 0:0:0 HOLD negedge:in3 posedge:clk 0:0:0 HOLD negedge:sr posedge:clk -158.688:-175.477:-197.429 HOLD posedge:ce posedge:clk 0:0:0 HOLD posedge:in0 posedge:clk 0:0:0 HOLD posedge:in1 posedge:clk 0:0:0 HOLD posedge:in2 posedge:clk 0:0:0 HOLD posedge:in3 posedge:clk 0:0:0 HOLD posedge:sr posedge:clk -143.975:-159.207:-179.124 RECOVERY negedge:sr posedge:clk 128.36:141.94:159.696 RECOVERY posedge:sr posedge:clk 0:0:0 REMOVAL negedge:sr posedge:clk 0:0:0 REMOVAL posedge:sr posedge:clk 0:0:0 SETUP negedge:ce posedge:clk 0:0:0 SETUP negedge:in0 posedge:clk 321.323:355.317:399.767 SETUP negedge:in1 posedge:clk 304.411:336.616:378.727 SETUP negedge:in2 posedge:clk 259.313:286.747:322.619 SETUP negedge:in3 posedge:clk 174.754:193.243:217.417 SETUP negedge:sr posedge:clk 112.745:124.673:140.269 SETUP posedge:ce posedge:clk 0:0:0 SETUP posedge:in0 posedge:clk 377.695:417.653:469.902 SETUP posedge:in1 posedge:clk 321.323:355.317:399.767 SETUP posedge:in2 posedge:clk 298.774:330.382:371.713 SETUP posedge:in3 posedge:clk 219.852:243.112:273.525 SETUP posedge:sr posedge:clk 163.48:180.775:203.39 IOPATH carryin carryout 101.47:112.205:126.242 84.5586:93.5045:105.202 IOPATH in0 lcout 360.783:398.952:448.861 310.048:342.85:385.74 IOPATH in0 ltout 293.136:324.149:364.7 310.048:342.85:385.74 IOPATH in1 carryout 208.578:230.644:259.498 197.303:218.177:245.471 IOPATH in1 lcout 321.323:355.317:399.767 304.411:336.616:378.727 IOPATH in1 ltout 259.313:286.747:322.619 304.411:336.616:378.727 IOPATH in2 carryout 186.029:205.71:231.444 107.108:118.439:133.256 IOPATH in2 lcout 304.411:336.616:378.727 281.862:311.682:350.673 IOPATH in2 ltout 248.039:274.28:308.592 276.225:305.448:343.659 IOPATH in3 lcout 253.676:280.513:315.606 231.127:255.579:287.552 IOPATH in3 ltout 214.215:236.878:266.511 219.852:243.112:273.525 IOPATH posedge:clk lcout 434.067:479.99:540.036 434.067:479.99:540.036 IOPATH sr lcout 0:0:0 481.612:532.564:599.188 IOPATH sr lcout 481.589:532.539:599.16 0:0:0 CELL Odrv4 IOPATH I O 281.862:311.682:350.673 298.774:330.382:371.713 CELL Odrv12 IOPATH I O 394.607:436.354:490.942 434.067:479.99:540.036 CELL PLL40 IOPATH PLLIN PLLOUTCORE *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:* CELL PLL40_2 IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PLL40_2F IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PRE_IO HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:PADIN negedge:INPUTCLK 0:0:0 HOLD negedge:PADIN posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:PADIN negedge:INPUTCLK 0:0:0 HOLD posedge:PADIN posedge:INPUTCLK 0:0:0 SETUP negedge:CLOCKENABLE posedge:INPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:DOUT0 posedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:DOUT1 negedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 56.3724:62.3363:70.1346 SETUP negedge:PADIN negedge:INPUTCLK 1515.4:1675.72:1885.36 SETUP negedge:PADIN posedge:INPUTCLK 1515.4:1675.72:1885.36 SETUP posedge:CLOCKENABLE posedge:INPUTCLK 62.0096:68.5699:77.148 SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:DOUT0 posedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:DOUT1 negedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 62.0096:68.5699:77.148 SETUP posedge:PADIN negedge:INPUTCLK 1521.04:1681.96:1892.37 SETUP posedge:PADIN posedge:INPUTCLK 1521.04:1681.96:1892.37 IOPATH DOUT0 PADOUT 1612.25:1782.82:2005.85 1798.28:1988.53:2237.29 IOPATH LATCHINPUTVALUE DIN0 276.225:305.448:343.659 298.774:330.382:371.713 IOPATH negedge:INPUTCLK DIN1 112.745:124.673:140.269 112.745:124.673:140.269 IOPATH negedge:OUTPUTCLK PADOUT 90.1958:99.7381:112.215 112.745:124.673:140.269 IOPATH OUTPUTENABLE PADOEN 140.931:155.841:175.336 169.117:187.009:210.404 IOPATH PADIN DIN0 496.077:548.56:617.184 372.058:411.42:462.888 IOPATH posedge:INPUTCLK DIN0 112.745:124.673:140.269 112.745:124.673:140.269 IOPATH posedge:OUTPUTCLK PADOEN 90.1958:99.7381:112.215 112.745:124.673:140.269 IOPATH posedge:OUTPUTCLK PADOUT 90.1958:99.7381:112.215 112.745:124.673:140.269 CELL PRE_IO_GBUF IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1496.86:1655.22:1862.28 1372.84:1518.08:1707.99 CELL SB_PLL40_2F_CORE IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:* CELL SB_PLL40_CORE IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:* CELL SB_RAM40_4K HOLD negedge:MASK[0] posedge:WCLK 0:0:0 HOLD negedge:MASK[1] posedge:WCLK 0:0:0 HOLD negedge:MASK[2] posedge:WCLK 0:0:0 HOLD negedge:MASK[3] posedge:WCLK 0:0:0 HOLD negedge:MASK[4] posedge:WCLK 0:0:0 HOLD negedge:MASK[5] posedge:WCLK 0:0:0 HOLD negedge:MASK[6] posedge:WCLK 0:0:0 HOLD negedge:MASK[7] posedge:WCLK 0:0:0 HOLD negedge:MASK[8] posedge:WCLK 0:0:0 HOLD negedge:MASK[9] posedge:WCLK 0:0:0 HOLD negedge:MASK[10] posedge:WCLK 0:0:0 HOLD negedge:MASK[11] posedge:WCLK 0:0:0 HOLD negedge:MASK[12] posedge:WCLK 0:0:0 HOLD negedge:MASK[13] posedge:WCLK 0:0:0 HOLD negedge:MASK[14] posedge:WCLK 0:0:0 HOLD negedge:MASK[15] posedge:WCLK 0:0:0 HOLD negedge:RADDR[0] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[1] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[2] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[3] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[4] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[5] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[6] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[7] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[8] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[9] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RADDR[10] posedge:RCLK 45.0979:49.869:56.1077 HOLD negedge:RCLKE posedge:RCLK 42.2793:46.7522:52.6009 HOLD negedge:RE posedge:RCLK 67.6469:74.8036:84.1615 HOLD negedge:WADDR[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WADDR[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WCLKE posedge:WCLK 21.9852:24.3112:27.3525 HOLD negedge:WDATA[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[11] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[12] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[13] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[14] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WDATA[15] posedge:WCLK 28.1862:31.1682:35.0673 HOLD negedge:WE posedge:WCLK 39.4607:43.6354:49.0942 HOLD posedge:MASK[0] posedge:WCLK 0:0:0 HOLD posedge:MASK[1] posedge:WCLK 0:0:0 HOLD posedge:MASK[2] posedge:WCLK 0:0:0 HOLD posedge:MASK[3] posedge:WCLK 0:0:0 HOLD posedge:MASK[4] posedge:WCLK 0:0:0 HOLD posedge:MASK[5] posedge:WCLK 0:0:0 HOLD posedge:MASK[6] posedge:WCLK 0:0:0 HOLD posedge:MASK[7] posedge:WCLK 0:0:0 HOLD posedge:MASK[8] posedge:WCLK 0:0:0 HOLD posedge:MASK[9] posedge:WCLK 0:0:0 HOLD posedge:MASK[10] posedge:WCLK 0:0:0 HOLD posedge:MASK[11] posedge:WCLK 0:0:0 HOLD posedge:MASK[12] posedge:WCLK 0:0:0 HOLD posedge:MASK[13] posedge:WCLK 0:0:0 HOLD posedge:MASK[14] posedge:WCLK 0:0:0 HOLD posedge:MASK[15] posedge:WCLK 0:0:0 HOLD posedge:RADDR[0] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[1] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[2] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[3] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[4] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[5] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[6] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[7] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[8] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[9] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RADDR[10] posedge:RCLK 45.0979:49.869:56.1077 HOLD posedge:RCLKE posedge:RCLK 42.2793:46.7522:52.6009 HOLD posedge:RE posedge:RCLK 67.6469:74.8036:84.1615 HOLD posedge:WADDR[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WADDR[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WCLKE posedge:WCLK 21.9852:24.3112:27.3525 HOLD posedge:WDATA[0] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[1] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[2] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[3] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[4] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[5] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[6] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[7] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[8] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[9] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[10] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[11] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[12] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[13] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[14] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WDATA[15] posedge:WCLK 28.1862:31.1682:35.0673 HOLD posedge:WE posedge:WCLK 39.4607:43.6354:49.0942 SETUP negedge:MASK[0] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[1] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[2] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[3] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[4] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[5] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[6] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[7] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[8] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[9] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[10] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[11] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[12] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[13] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[14] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:MASK[15] posedge:WCLK 219.852:243.112:273.525 SETUP negedge:RADDR[0] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[1] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[2] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[3] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[4] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[5] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[6] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[7] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[8] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[9] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RADDR[10] posedge:RCLK 163.48:180.775:203.39 SETUP negedge:RCLKE posedge:RCLK 214.215:236.878:266.511 SETUP negedge:RE posedge:RCLK 78.9214:87.2708:98.1884 SETUP negedge:WADDR[0] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[1] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[2] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[3] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[4] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[5] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[6] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[7] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[8] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[9] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WADDR[10] posedge:WCLK 180.392:199.476:224.431 SETUP negedge:WCLKE posedge:WCLK 214.215:236.878:266.511 SETUP negedge:WDATA[0] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[1] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[2] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[3] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[4] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[5] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[6] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[7] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[8] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[9] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[10] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[11] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[12] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[13] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[14] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WDATA[15] posedge:WCLK 129.657:143.374:161.31 SETUP negedge:WE posedge:WCLK 107.108:118.439:133.256 SETUP posedge:MASK[0] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[1] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[2] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[3] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[4] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[5] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[6] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[7] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[8] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[9] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[10] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[11] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[12] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[13] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[14] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:MASK[15] posedge:WCLK 219.852:243.112:273.525 SETUP posedge:RADDR[0] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[1] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[2] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[3] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[4] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[5] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[6] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[7] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[8] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[9] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RADDR[10] posedge:RCLK 163.48:180.775:203.39 SETUP posedge:RCLKE posedge:RCLK 214.215:236.878:266.511 SETUP posedge:RE posedge:RCLK 78.9214:87.2708:98.1884 SETUP posedge:WADDR[0] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[1] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[2] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[3] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[4] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[5] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[6] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[7] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[8] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[9] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WADDR[10] posedge:WCLK 180.392:199.476:224.431 SETUP posedge:WCLKE posedge:WCLK 214.215:236.878:266.511 SETUP posedge:WDATA[0] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[1] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[2] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[3] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[4] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[5] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[6] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[7] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[8] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[9] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[10] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[11] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[12] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[13] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[14] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WDATA[15] posedge:WCLK 129.657:143.374:161.31 SETUP posedge:WE posedge:WCLK 107.108:118.439:133.256 IOPATH posedge:RCLK RDATA[0] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[1] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[2] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[3] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[4] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[5] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[6] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[7] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[8] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[9] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[10] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[11] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[12] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[13] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[14] 1725:1907.49:2146.12 1725:1907.49:2146.12 IOPATH posedge:RCLK RDATA[15] 1725:1907.49:2146.12 1725:1907.49:2146.12 CELL Sp12to4 IOPATH I O 343.872:380.251:427.821 360.783:398.952:448.861 CELL Span4Mux_h0 IOPATH I O 118.382:130.906:147.283 112.745:124.673:140.269 CELL Span4Mux_h1 IOPATH I O 140.931:155.841:175.336 135.294:149.607:168.323 CELL Span4Mux_h2 IOPATH I O 163.48:180.775:203.39 163.48:180.775:203.39 CELL Span4Mux_h3 IOPATH I O 186.029:205.71:231.444 186.029:205.71:231.444 CELL Span4Mux_h4 IOPATH I O 242.401:268.046:301.579 253.676:280.513:315.606 CELL Span4Mux_v0 IOPATH I O 163.48:180.775:203.39 152.205:168.308:189.363 CELL Span4Mux_v1 IOPATH I O 163.48:180.775:203.39 157.843:174.542:196.377 CELL Span4Mux_v2 IOPATH I O 202.941:224.411:252.484 202.941:224.411:252.484 CELL Span4Mux_v3 IOPATH I O 253.676:280.513:315.606 270.588:299.214:336.646 CELL Span4Mux_v4 IOPATH I O 281.862:311.682:350.673 298.774:330.382:371.713 CELL Span12Mux_h0 IOPATH I O 112.745:124.673:140.269 118.382:130.906:147.283 CELL Span12Mux_h1 IOPATH I O 107.108:118.439:133.256 107.108:118.439:133.256 CELL Span12Mux_h2 IOPATH I O 129.657:143.374:161.31 135.294:149.607:168.323 CELL Span12Mux_h3 IOPATH I O 135.294:149.607:168.323 146.568:162.074:182.35 CELL Span12Mux_h4 IOPATH I O 157.843:174.542:196.377 174.754:193.243:217.417 CELL Span12Mux_h5 IOPATH I O 186.029:205.71:231.444 208.578:230.644:259.498 CELL Span12Mux_h6 IOPATH I O 202.941:224.411:252.484 225.49:249.345:280.538 CELL Span12Mux_h7 IOPATH I O 231.127:255.579:287.552 259.313:286.747:322.619 CELL Span12Mux_h8 IOPATH I O 276.225:305.448:343.659 310.048:342.85:385.74 CELL Span12Mux_h9 IOPATH I O 315.685:349.083:392.754 349.509:386.485:434.834 CELL Span12Mux_h10 IOPATH I O 343.872:380.251:427.821 377.695:417.653:469.902 CELL Span12Mux_h11 IOPATH I O 377.695:417.653:469.902 422.793:467.522:526.009 CELL Span12Mux_h12 IOPATH I O 394.607:436.354:490.942 434.067:479.99:540.036 CELL Span12Mux_v0 IOPATH I O 78.9214:87.2708:98.1884 84.5586:93.5045:105.202 CELL Span12Mux_v1 IOPATH I O 84.5586:93.5045:105.202 84.5586:93.5045:105.202 CELL Span12Mux_v2 IOPATH I O 112.745:124.673:140.269 124.019:137.14:154.296 CELL Span12Mux_v3 IOPATH I O 118.382:130.906:147.283 135.294:149.607:168.323 CELL Span12Mux_v4 IOPATH I O 146.568:162.074:182.35 169.117:187.009:210.404 CELL Span12Mux_v5 IOPATH I O 191.666:211.943:238.458 214.215:236.878:266.511 CELL Span12Mux_v6 IOPATH I O 208.578:230.644:259.498 231.127:255.579:287.552 CELL Span12Mux_v7 IOPATH I O 225.49:249.345:280.538 253.676:280.513:315.606 CELL Span12Mux_v8 IOPATH I O 287.499:317.915:357.686 315.685:349.083:392.754 CELL Span12Mux_v9 IOPATH I O 304.411:336.616:378.727 338.234:374.018:420.807 CELL Span12Mux_v10 IOPATH I O 315.685:349.083:392.754 349.509:386.485:434.834 CELL Span12Mux_v11 IOPATH I O 332.597:367.784:413.794 366.421:405.186:455.875 CELL Span12Mux_v12 IOPATH I O 394.607:436.354:490.942 434.067:479.99:540.036 CELL SRMux IOPATH I O 372.058:411.42:462.888 287.499:317.915:357.686 fpga-icestorm-0~20160913git266e758/icefuzz/timings_lp1k.txt000066400000000000000000000621611276746530600232210ustar00rootroot00000000000000CELL CascadeBuf IOPATH I O 137.402:178.5:217.075 170.116:221:268.76 CELL CascadeMux IOPATH I O 0:0:0 0:0:0 CELL CEMux IOPATH I O 562.692:731:888.975 516.892:671.5:816.617 CELL ClkMux IOPATH I O 287.889:374:454.825 215.917:280.5:341.118 CELL gio2CtrlBuf IOPATH I O 0:0:0 0:0:0 CELL Glb2LocalMux IOPATH I O 418.748:544:661.563 333.689:433.5:527.183 CELL GlobalMux IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706 CELL ICE_CARRY_IN_MUX IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423 CELL ICE_GB IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954 CELL InMux IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 CELL INV IOPATH I O 0:0:0 0:0:0 CELL IO_PAD IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990 IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942 IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540 CELL IoInMux IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 CELL IoSpan4Mux IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 CELL LocalMux IOPATH I O 307.518:399.5:485.835 287.889:374:454.825 CELL LogicCell40 HOLD negedge:ce posedge:clk 0:0:0 HOLD negedge:in0 posedge:clk 0:0:0 HOLD negedge:in1 posedge:clk 0:0:0 HOLD negedge:in2 posedge:clk 0:0:0 HOLD negedge:in3 posedge:clk 0:0:0 HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984 HOLD posedge:ce posedge:clk 0:0:0 HOLD posedge:in0 posedge:clk 0:0:0 HOLD posedge:in1 posedge:clk 0:0:0 HOLD posedge:in2 posedge:clk 0:0:0 HOLD posedge:in3 posedge:clk 0:0:0 HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005 RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372 RECOVERY posedge:sr posedge:clk 0:0:0 REMOVAL negedge:sr posedge:clk 0:0:0 REMOVAL posedge:sr posedge:clk 0:0:0 SETUP negedge:ce posedge:clk 0:0:0 SETUP negedge:in0 posedge:clk 372.947:484.5:589.205 SETUP negedge:in1 posedge:clk 353.318:459:558.194 SETUP negedge:in2 posedge:clk 300.975:391:475.498 SETUP negedge:in3 posedge:clk 202.831:263.5:320.445 SETUP negedge:sr posedge:clk 130.859:170:206.738 SETUP posedge:ce posedge:clk 0:0:0 SETUP posedge:in0 posedge:clk 438.376:569.5:692.574 SETUP posedge:in1 posedge:clk 372.947:484.5:589.205 SETUP posedge:in2 posedge:clk 346.775:450.5:547.857 SETUP posedge:in3 posedge:clk 255.174:331.5:403.14 SETUP posedge:sr posedge:clk 189.745:246.5:299.771 IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054 IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531 IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531 IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792 IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194 IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194 IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402 IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846 IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509 IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814 IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14 IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943 IOPATH sr lcout 0:0:0 558.989:726.189:883.125 IOPATH sr lcout 558.963:726.155:883.083 0:0:0 CELL Odrv4 IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 CELL Odrv12 IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 CELL PLL40 IOPATH PLLIN PLLOUTCORE *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:* CELL PLL40_2 IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PLL40_2F IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PRE_IO HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:PADIN negedge:INPUTCLK 0:0:0 HOLD negedge:PADIN posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:PADIN negedge:INPUTCLK 0:0:0 HOLD posedge:PADIN posedge:INPUTCLK 0:0:0 SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369 SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:PADIN negedge:INPUTCLK 1527.97:1985:2413.98 SETUP negedge:PADIN posedge:INPUTCLK 1527.97:1985:2413.98 SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706 SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:PADIN negedge:INPUTCLK 1534.51:1993.5:2424.32 SETUP posedge:PADIN posedge:INPUTCLK 1534.51:1993.5:2424.32 IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48 IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857 IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738 IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108 IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237 IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738 IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738 IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 CELL PRE_IO_GBUF IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1313.95:1706.97:2075.86 1170.01:1519.97:1848.45 CELL SB_PLL40_2F_CORE IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:* CELL SB_PLL40_CORE IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:* CELL SB_RAM40_4K HOLD negedge:MASK[0] posedge:WCLK 0:0:0 HOLD negedge:MASK[1] posedge:WCLK 0:0:0 HOLD negedge:MASK[2] posedge:WCLK 0:0:0 HOLD negedge:MASK[3] posedge:WCLK 0:0:0 HOLD negedge:MASK[4] posedge:WCLK 0:0:0 HOLD negedge:MASK[5] posedge:WCLK 0:0:0 HOLD negedge:MASK[6] posedge:WCLK 0:0:0 HOLD negedge:MASK[7] posedge:WCLK 0:0:0 HOLD negedge:MASK[8] posedge:WCLK 0:0:0 HOLD negedge:MASK[9] posedge:WCLK 0:0:0 HOLD negedge:MASK[10] posedge:WCLK 0:0:0 HOLD negedge:MASK[11] posedge:WCLK 0:0:0 HOLD negedge:MASK[12] posedge:WCLK 0:0:0 HOLD negedge:MASK[13] posedge:WCLK 0:0:0 HOLD negedge:MASK[14] posedge:WCLK 0:0:0 HOLD negedge:MASK[15] posedge:WCLK 0:0:0 HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 HOLD negedge:RE posedge:RCLK 78.5152:102:124.043 HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585 HOLD posedge:MASK[0] posedge:WCLK 0:0:0 HOLD posedge:MASK[1] posedge:WCLK 0:0:0 HOLD posedge:MASK[2] posedge:WCLK 0:0:0 HOLD posedge:MASK[3] posedge:WCLK 0:0:0 HOLD posedge:MASK[4] posedge:WCLK 0:0:0 HOLD posedge:MASK[5] posedge:WCLK 0:0:0 HOLD posedge:MASK[6] posedge:WCLK 0:0:0 HOLD posedge:MASK[7] posedge:WCLK 0:0:0 HOLD posedge:MASK[8] posedge:WCLK 0:0:0 HOLD posedge:MASK[9] posedge:WCLK 0:0:0 HOLD posedge:MASK[10] posedge:WCLK 0:0:0 HOLD posedge:MASK[11] posedge:WCLK 0:0:0 HOLD posedge:MASK[12] posedge:WCLK 0:0:0 HOLD posedge:MASK[13] posedge:WCLK 0:0:0 HOLD posedge:MASK[14] posedge:WCLK 0:0:0 HOLD posedge:MASK[15] posedge:WCLK 0:0:0 HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 HOLD posedge:RE posedge:RCLK 78.5152:102:124.043 HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585 SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803 SETUP negedge:RE posedge:RCLK 91.601:119:144.717 SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781 SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803 SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402 SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803 SETUP posedge:RE posedge:RCLK 91.601:119:144.717 SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781 SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803 SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402 IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1 CELL Sp12to4 IOPATH I O 399.119:518.5:630.552 418.748:544:661.563 CELL Span4Mux_h0 IOPATH I O 137.402:178.5:217.075 130.859:170:206.738 CELL Span4Mux_h1 IOPATH I O 163.573:212.5:258.423 157.03:204:248.086 CELL Span4Mux_h2 IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771 CELL Span4Mux_h3 IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118 CELL Span4Mux_h4 IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161 CELL Span4Mux_v0 IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097 CELL Span4Mux_v1 IOPATH I O 189.745:246.5:299.771 183.202:238:289.434 CELL Span4Mux_v2 IOPATH I O 235.546:306:372.129 235.546:306:372.129 CELL Span4Mux_v3 IOPATH I O 294.432:382.5:465.161 314.061:408:496.172 CELL Span4Mux_v4 IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 CELL Span12Mux_h0 IOPATH I O 130.859:170:206.738 137.402:178.5:217.075 CELL Span12Mux_h1 IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402 CELL Span12Mux_h2 IOPATH I O 150.487:195.5:237.749 157.03:204:248.086 CELL Span12Mux_h3 IOPATH I O 157.03:204:248.086 170.116:221:268.76 CELL Span12Mux_h4 IOPATH I O 183.202:238:289.434 202.831:263.5:320.445 CELL Span12Mux_h5 IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466 CELL Span12Mux_h6 IOPATH I O 235.546:306:372.129 261.717:340:413.477 CELL Span12Mux_h7 IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 CELL Span12Mux_h8 IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531 CELL Span12Mux_h9 IOPATH I O 366.404:476:578.868 405.662:527:640.889 CELL Span12Mux_h10 IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574 CELL Span12Mux_h11 IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269 CELL Span12Mux_h12 IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 CELL Span12Mux_v0 IOPATH I O 91.601:119:144.717 98.144:127.5:155.054 CELL Span12Mux_v1 IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054 CELL Span12Mux_v2 IOPATH I O 130.859:170:206.738 143.944:187:227.412 CELL Span12Mux_v3 IOPATH I O 137.402:178.5:217.075 157.03:204:248.086 CELL Span12Mux_v4 IOPATH I O 170.116:221:268.76 196.288:255:310.108 CELL Span12Mux_v5 IOPATH I O 222.46:289:351.455 248.631:323:392.803 CELL Span12Mux_v6 IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814 CELL Span12Mux_v7 IOPATH I O 261.717:340:413.477 294.432:382.5:465.161 CELL Span12Mux_v8 IOPATH I O 333.689:433.5:527.183 366.404:476:578.868 CELL Span12Mux_v9 IOPATH I O 353.318:459:558.194 392.576:510:620.215 CELL Span12Mux_v10 IOPATH I O 366.404:476:578.868 405.662:527:640.889 CELL Span12Mux_v11 IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9 CELL Span12Mux_v12 IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 CELL SRMux IOPATH I O 431.833:561:682.237 333.689:433.5:527.183 fpga-icestorm-0~20160913git266e758/icefuzz/timings_lp8k.txt000066400000000000000000000621731276746530600232330ustar00rootroot00000000000000CELL CascadeBuf IOPATH I O 137.402:178.5:217.075 170.116:221:268.76 CELL CascadeMux IOPATH I O 0:0:0 0:0:0 CELL CEMux IOPATH I O 562.692:731:888.975 516.892:671.5:816.617 CELL ClkMux IOPATH I O 287.889:374:454.825 215.917:280.5:341.118 CELL gio2CtrlBuf IOPATH I O 0:0:0 0:0:0 CELL Glb2LocalMux IOPATH I O 418.748:544:661.563 333.689:433.5:527.183 CELL GlobalMux IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706 CELL ICE_CARRY_IN_MUX IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423 CELL ICE_GB IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954 CELL InMux IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 CELL INV IOPATH I O 0:0:0 0:0:0 CELL IO_PAD IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990 IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942 IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2 IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540 CELL IoInMux IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445 CELL IoSpan4Mux IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 CELL LocalMux IOPATH I O 307.518:399.5:485.835 287.889:374:454.825 CELL LogicCell40 HOLD negedge:ce posedge:clk 0:0:0 HOLD negedge:in0 posedge:clk 0:0:0 HOLD negedge:in1 posedge:clk 0:0:0 HOLD negedge:in2 posedge:clk 0:0:0 HOLD negedge:in3 posedge:clk 0:0:0 HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984 HOLD posedge:ce posedge:clk 0:0:0 HOLD posedge:in0 posedge:clk 0:0:0 HOLD posedge:in1 posedge:clk 0:0:0 HOLD posedge:in2 posedge:clk 0:0:0 HOLD posedge:in3 posedge:clk 0:0:0 HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005 RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372 RECOVERY posedge:sr posedge:clk 0:0:0 REMOVAL negedge:sr posedge:clk 0:0:0 REMOVAL posedge:sr posedge:clk 0:0:0 SETUP negedge:ce posedge:clk 0:0:0 SETUP negedge:in0 posedge:clk 372.947:484.5:589.205 SETUP negedge:in1 posedge:clk 353.318:459:558.194 SETUP negedge:in2 posedge:clk 300.975:391:475.498 SETUP negedge:in3 posedge:clk 202.831:263.5:320.445 SETUP negedge:sr posedge:clk 130.859:170:206.738 SETUP posedge:ce posedge:clk 0:0:0 SETUP posedge:in0 posedge:clk 438.376:569.5:692.574 SETUP posedge:in1 posedge:clk 372.947:484.5:589.205 SETUP posedge:in2 posedge:clk 346.775:450.5:547.857 SETUP posedge:in3 posedge:clk 255.174:331.5:403.14 SETUP posedge:sr posedge:clk 189.745:246.5:299.771 IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054 IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531 IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531 IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792 IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194 IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194 IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402 IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846 IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509 IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814 IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14 IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943 IOPATH sr lcout 0:0:0 558.989:726.189:883.125 IOPATH sr lcout 558.963:726.155:883.083 0:0:0 CELL Odrv4 IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 CELL Odrv12 IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 CELL PLL40 IOPATH PLLIN PLLOUTCORE *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:* CELL PLL40_2 IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PLL40_2F IOPATH PLLIN PLLOUTCOREA *:*:* *:*:* IOPATH PLLIN PLLOUTCOREB *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:* IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:* CELL PRE_IO HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD negedge:PADIN negedge:INPUTCLK 0:0:0 HOLD negedge:PADIN posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0 HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0 HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0 HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0 HOLD posedge:PADIN negedge:INPUTCLK 0:0:0 HOLD posedge:PADIN posedge:INPUTCLK 0:0:0 SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369 SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369 SETUP negedge:PADIN negedge:INPUTCLK 1758.87:2284.97:2778.77 SETUP negedge:PADIN posedge:INPUTCLK 1758.87:2284.97:2778.77 SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706 SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706 SETUP posedge:PADIN negedge:INPUTCLK 1765.41:2293.47:2789.11 SETUP posedge:PADIN posedge:INPUTCLK 1765.41:2293.47:2789.11 IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48 IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857 IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738 IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108 IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237 IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738 IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738 IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738 CELL PRE_IO_GBUF IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1737.34:2257:2744.76 1593.4:2070:2517.35 CELL SB_PLL40_2F_CORE IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:* CELL SB_PLL40_CORE IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:* IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:* CELL SB_RAM40_4K HOLD negedge:MASK[0] posedge:WCLK 0:0:0 HOLD negedge:MASK[1] posedge:WCLK 0:0:0 HOLD negedge:MASK[2] posedge:WCLK 0:0:0 HOLD negedge:MASK[3] posedge:WCLK 0:0:0 HOLD negedge:MASK[4] posedge:WCLK 0:0:0 HOLD negedge:MASK[5] posedge:WCLK 0:0:0 HOLD negedge:MASK[6] posedge:WCLK 0:0:0 HOLD negedge:MASK[7] posedge:WCLK 0:0:0 HOLD negedge:MASK[8] posedge:WCLK 0:0:0 HOLD negedge:MASK[9] posedge:WCLK 0:0:0 HOLD negedge:MASK[10] posedge:WCLK 0:0:0 HOLD negedge:MASK[11] posedge:WCLK 0:0:0 HOLD negedge:MASK[12] posedge:WCLK 0:0:0 HOLD negedge:MASK[13] posedge:WCLK 0:0:0 HOLD negedge:MASK[14] posedge:WCLK 0:0:0 HOLD negedge:MASK[15] posedge:WCLK 0:0:0 HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 HOLD negedge:RE posedge:RCLK 78.5152:102:124.043 HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585 HOLD posedge:MASK[0] posedge:WCLK 0:0:0 HOLD posedge:MASK[1] posedge:WCLK 0:0:0 HOLD posedge:MASK[2] posedge:WCLK 0:0:0 HOLD posedge:MASK[3] posedge:WCLK 0:0:0 HOLD posedge:MASK[4] posedge:WCLK 0:0:0 HOLD posedge:MASK[5] posedge:WCLK 0:0:0 HOLD posedge:MASK[6] posedge:WCLK 0:0:0 HOLD posedge:MASK[7] posedge:WCLK 0:0:0 HOLD posedge:MASK[8] posedge:WCLK 0:0:0 HOLD posedge:MASK[9] posedge:WCLK 0:0:0 HOLD posedge:MASK[10] posedge:WCLK 0:0:0 HOLD posedge:MASK[11] posedge:WCLK 0:0:0 HOLD posedge:MASK[12] posedge:WCLK 0:0:0 HOLD posedge:MASK[13] posedge:WCLK 0:0:0 HOLD posedge:MASK[14] posedge:WCLK 0:0:0 HOLD posedge:MASK[15] posedge:WCLK 0:0:0 HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954 HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269 HOLD posedge:RE posedge:RCLK 78.5152:102:124.043 HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314 HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846 HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585 SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803 SETUP negedge:RE posedge:RCLK 91.601:119:144.717 SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781 SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781 SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803 SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402 SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14 SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771 SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803 SETUP posedge:RE posedge:RCLK 91.601:119:144.717 SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781 SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781 SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803 SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749 SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402 IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1 IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1 CELL Sp12to4 IOPATH I O 399.119:518.5:630.552 418.748:544:661.563 CELL Span4Mux_h0 IOPATH I O 137.402:178.5:217.075 130.859:170:206.738 CELL Span4Mux_h1 IOPATH I O 163.573:212.5:258.423 157.03:204:248.086 CELL Span4Mux_h2 IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771 CELL Span4Mux_h3 IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118 CELL Span4Mux_h4 IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161 CELL Span4Mux_v0 IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097 CELL Span4Mux_v1 IOPATH I O 189.745:246.5:299.771 183.202:238:289.434 CELL Span4Mux_v2 IOPATH I O 235.546:306:372.129 235.546:306:372.129 CELL Span4Mux_v3 IOPATH I O 294.432:382.5:465.161 314.061:408:496.172 CELL Span4Mux_v4 IOPATH I O 327.147:425:516.846 346.775:450.5:547.857 CELL Span12Mux_h0 IOPATH I O 130.859:170:206.738 137.402:178.5:217.075 CELL Span12Mux_h1 IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402 CELL Span12Mux_h2 IOPATH I O 150.487:195.5:237.749 157.03:204:248.086 CELL Span12Mux_h3 IOPATH I O 157.03:204:248.086 170.116:221:268.76 CELL Span12Mux_h4 IOPATH I O 183.202:238:289.434 202.831:263.5:320.445 CELL Span12Mux_h5 IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466 CELL Span12Mux_h6 IOPATH I O 235.546:306:372.129 261.717:340:413.477 CELL Span12Mux_h7 IOPATH I O 268.26:348.5:423.814 300.975:391:475.498 CELL Span12Mux_h8 IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531 CELL Span12Mux_h9 IOPATH I O 366.404:476:578.868 405.662:527:640.889 CELL Span12Mux_h10 IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574 CELL Span12Mux_h11 IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269 CELL Span12Mux_h12 IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 CELL Span12Mux_v0 IOPATH I O 91.601:119:144.717 98.144:127.5:155.054 CELL Span12Mux_v1 IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054 CELL Span12Mux_v2 IOPATH I O 130.859:170:206.738 143.944:187:227.412 CELL Span12Mux_v3 IOPATH I O 137.402:178.5:217.075 157.03:204:248.086 CELL Span12Mux_v4 IOPATH I O 170.116:221:268.76 196.288:255:310.108 CELL Span12Mux_v5 IOPATH I O 222.46:289:351.455 248.631:323:392.803 CELL Span12Mux_v6 IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814 CELL Span12Mux_v7 IOPATH I O 261.717:340:413.477 294.432:382.5:465.161 CELL Span12Mux_v8 IOPATH I O 333.689:433.5:527.183 366.404:476:578.868 CELL Span12Mux_v9 IOPATH I O 353.318:459:558.194 392.576:510:620.215 CELL Span12Mux_v10 IOPATH I O 366.404:476:578.868 405.662:527:640.889 CELL Span12Mux_v11 IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9 CELL Span12Mux_v12 IOPATH I O 458.005:595:723.585 503.806:654.5:795.943 CELL SRMux IOPATH I O 431.833:561:682.237 333.689:433.5:527.183 fpga-icestorm-0~20160913git266e758/icefuzz/tmedges.txt000066400000000000000000000534001276746530600222440ustar00rootroot00000000000000CEMux.O LogicCell40.ce CEMux.O PRE_IO.CLOCKENABLE CEMux.O SB_RAM40_4K.RCLKE CEMux.O SB_RAM40_4K.WCLKE CascadeBuf.O CascadeMux.I CascadeMux.O CascadeBuf.I CascadeMux.O LogicCell40.in2 CascadeMux.O SB_RAM40_4K.RADDR[0] CascadeMux.O SB_RAM40_4K.RADDR[10] CascadeMux.O SB_RAM40_4K.RADDR[1] CascadeMux.O SB_RAM40_4K.RADDR[2] CascadeMux.O SB_RAM40_4K.RADDR[3] CascadeMux.O SB_RAM40_4K.RADDR[4] CascadeMux.O SB_RAM40_4K.RADDR[5] CascadeMux.O SB_RAM40_4K.RADDR[6] CascadeMux.O SB_RAM40_4K.RADDR[7] CascadeMux.O SB_RAM40_4K.RADDR[8] CascadeMux.O SB_RAM40_4K.RADDR[9] CascadeMux.O SB_RAM40_4K.WADDR[0] CascadeMux.O SB_RAM40_4K.WADDR[10] CascadeMux.O SB_RAM40_4K.WADDR[1] CascadeMux.O SB_RAM40_4K.WADDR[2] CascadeMux.O SB_RAM40_4K.WADDR[3] CascadeMux.O SB_RAM40_4K.WADDR[4] CascadeMux.O SB_RAM40_4K.WADDR[5] CascadeMux.O SB_RAM40_4K.WADDR[6] CascadeMux.O SB_RAM40_4K.WADDR[7] CascadeMux.O SB_RAM40_4K.WADDR[8] CascadeMux.O SB_RAM40_4K.WADDR[9] ClkMux.O INV.I ClkMux.O LogicCell40.clk ClkMux.O PRE_IO.INPUTCLK ClkMux.O PRE_IO.OUTPUTCLK ClkMux.O SB_RAM40_4K.RCLK ClkMux.O SB_RAM40_4K.WCLK GND.Y LogicCell40.carryin GND.Y LogicCell40.clk GND.Y LogicCell40.in0 GND.Y LogicCell40.in1 GND.Y LogicCell40.in2 GND.Y LogicCell40.in3 GND.Y LogicCell40.sr GND.Y PRE_IO.DOUT0 GND.Y SB_RAM40_4K.WCLK Glb2LocalMux.O LocalMux.I GlobalMux.O CEMux.I GlobalMux.O ClkMux.I GlobalMux.O Glb2LocalMux.I GlobalMux.O SRMux.I ICE_CARRY_IN_MUX.carryinitout InMux.I ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I INV.O LogicCell40.clk INV.O SB_RAM40_4K.RCLK INV.O SB_RAM40_4K.WCLK IO_PAD.DOUT PLL40.PLLIN IO_PAD.DOUT PLL40_2.PLLIN IO_PAD.DOUT PLL40_2F.PLLIN IO_PAD.DOUT PRE_IO.PADIN IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN InMux.O CascadeMux.I InMux.O LogicCell40.in0 InMux.O LogicCell40.in1 InMux.O LogicCell40.in3 InMux.O SB_RAM40_4K.MASK[0] InMux.O SB_RAM40_4K.MASK[10] InMux.O SB_RAM40_4K.MASK[11] InMux.O SB_RAM40_4K.MASK[12] InMux.O SB_RAM40_4K.MASK[13] InMux.O SB_RAM40_4K.MASK[14] InMux.O SB_RAM40_4K.MASK[15] InMux.O SB_RAM40_4K.MASK[1] InMux.O SB_RAM40_4K.MASK[2] InMux.O SB_RAM40_4K.MASK[3] InMux.O SB_RAM40_4K.MASK[4] InMux.O SB_RAM40_4K.MASK[5] InMux.O SB_RAM40_4K.MASK[6] InMux.O SB_RAM40_4K.MASK[7] InMux.O SB_RAM40_4K.MASK[8] InMux.O SB_RAM40_4K.MASK[9] InMux.O SB_RAM40_4K.WDATA[0] InMux.O SB_RAM40_4K.WDATA[10] InMux.O SB_RAM40_4K.WDATA[11] InMux.O SB_RAM40_4K.WDATA[12] InMux.O SB_RAM40_4K.WDATA[13] InMux.O SB_RAM40_4K.WDATA[14] InMux.O SB_RAM40_4K.WDATA[15] InMux.O SB_RAM40_4K.WDATA[1] InMux.O SB_RAM40_4K.WDATA[2] InMux.O SB_RAM40_4K.WDATA[3] InMux.O SB_RAM40_4K.WDATA[4] InMux.O SB_RAM40_4K.WDATA[5] InMux.O SB_RAM40_4K.WDATA[6] InMux.O SB_RAM40_4K.WDATA[7] InMux.O SB_RAM40_4K.WDATA[8] InMux.O SB_RAM40_4K.WDATA[9] IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER IoInMux.O PLL40.BYPASS IoInMux.O PLL40.DYNAMICDELAY[0] IoInMux.O PLL40.DYNAMICDELAY[1] IoInMux.O PLL40.DYNAMICDELAY[2] IoInMux.O PLL40.DYNAMICDELAY[3] IoInMux.O PLL40.DYNAMICDELAY[4] IoInMux.O PLL40.DYNAMICDELAY[5] IoInMux.O PLL40.DYNAMICDELAY[6] IoInMux.O PLL40.DYNAMICDELAY[7] IoInMux.O PLL40.EXTFEEDBACK IoInMux.O PLL40.LATCHINPUTVALUE IoInMux.O PLL40.RESETB IoInMux.O PLL40.SCLK IoInMux.O PLL40.SDI IoInMux.O PLL40_2.BYPASS IoInMux.O PLL40_2.DYNAMICDELAY[0] IoInMux.O PLL40_2.DYNAMICDELAY[1] IoInMux.O PLL40_2.DYNAMICDELAY[2] IoInMux.O PLL40_2.DYNAMICDELAY[3] IoInMux.O PLL40_2.DYNAMICDELAY[4] IoInMux.O PLL40_2.DYNAMICDELAY[5] IoInMux.O PLL40_2.DYNAMICDELAY[6] IoInMux.O PLL40_2.DYNAMICDELAY[7] IoInMux.O PLL40_2.EXTFEEDBACK IoInMux.O PLL40_2.LATCHINPUTVALUE IoInMux.O PLL40_2.RESETB IoInMux.O PLL40_2.SCLK IoInMux.O PLL40_2.SDI IoInMux.O PLL40_2F.BYPASS IoInMux.O PLL40_2F.DYNAMICDELAY[0] IoInMux.O PLL40_2F.DYNAMICDELAY[1] IoInMux.O PLL40_2F.DYNAMICDELAY[2] IoInMux.O PLL40_2F.DYNAMICDELAY[3] IoInMux.O PLL40_2F.DYNAMICDELAY[4] IoInMux.O PLL40_2F.DYNAMICDELAY[5] IoInMux.O PLL40_2F.DYNAMICDELAY[6] IoInMux.O PLL40_2F.DYNAMICDELAY[7] IoInMux.O PLL40_2F.EXTFEEDBACK IoInMux.O PLL40_2F.LATCHINPUTVALUE IoInMux.O PLL40_2F.RESETB IoInMux.O PLL40_2F.SCLK IoInMux.O PLL40_2F.SDI IoInMux.O PRE_IO.DOUT0 IoInMux.O PRE_IO.DOUT1 IoInMux.O PRE_IO.LATCHINPUTVALUE IoInMux.O PRE_IO.OUTPUTENABLE IoInMux.O SB_PLL40_2F_CORE.BYPASS IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[0] IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[1] IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[2] IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[3] IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[4] IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[5] IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[6] IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[7] IoInMux.O SB_PLL40_2F_CORE.EXTFEEDBACK IoInMux.O SB_PLL40_2F_CORE.LATCHINPUTVALUE IoInMux.O SB_PLL40_2F_CORE.REFERENCECLK IoInMux.O SB_PLL40_2F_CORE.RESETB IoInMux.O SB_PLL40_2F_CORE.SCLK IoInMux.O SB_PLL40_2F_CORE.SDI IoInMux.O SB_PLL40_CORE.BYPASS IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[0] IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[1] IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[2] IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[3] IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[4] IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[5] IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[6] IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[7] IoInMux.O SB_PLL40_CORE.EXTFEEDBACK IoInMux.O SB_PLL40_CORE.LATCHINPUTVALUE IoInMux.O SB_PLL40_CORE.REFERENCECLK IoInMux.O SB_PLL40_CORE.RESETB IoInMux.O SB_PLL40_CORE.SCLK IoInMux.O SB_PLL40_CORE.SDI IoSpan4Mux.O IoSpan4Mux.I IoSpan4Mux.O LocalMux.I IoSpan4Mux.O Span4Mux_h.I IoSpan4Mux.O Span4Mux_s0_h.I IoSpan4Mux.O Span4Mux_s0_v.I IoSpan4Mux.O Span4Mux_s1_h.I IoSpan4Mux.O Span4Mux_s1_v.I IoSpan4Mux.O Span4Mux_s2_h.I IoSpan4Mux.O Span4Mux_s2_v.I IoSpan4Mux.O Span4Mux_s3_h.I IoSpan4Mux.O Span4Mux_s3_v.I IoSpan4Mux.O Span4Mux_v.I LocalMux.O CEMux.I LocalMux.O ClkMux.I LocalMux.O InMux.I LocalMux.O IoInMux.I LocalMux.O SRMux.I LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin LogicCell40.carryout InMux.I LogicCell40.carryout LogicCell40.carryin LogicCell40.lcout LocalMux.I LogicCell40.lcout Odrv12.I LogicCell40.lcout Odrv4.I LogicCell40.ltout CascadeMux.I Odrv12.O LocalMux.I Odrv12.O Sp12to4.I Odrv12.O Span12Mux_h.I Odrv12.O Span12Mux_s0_h.I Odrv12.O Span12Mux_s0_v.I Odrv12.O Span12Mux_s10_h.I Odrv12.O Span12Mux_s10_v.I Odrv12.O Span12Mux_s11_h.I Odrv12.O Span12Mux_s11_v.I Odrv12.O Span12Mux_s1_h.I Odrv12.O Span12Mux_s1_v.I Odrv12.O Span12Mux_s2_h.I Odrv12.O Span12Mux_s2_v.I Odrv12.O Span12Mux_s3_h.I Odrv12.O Span12Mux_s3_v.I Odrv12.O Span12Mux_s4_h.I Odrv12.O Span12Mux_s4_v.I Odrv12.O Span12Mux_s5_h.I Odrv12.O Span12Mux_s5_v.I Odrv12.O Span12Mux_s6_h.I Odrv12.O Span12Mux_s6_v.I Odrv12.O Span12Mux_s7_h.I Odrv12.O Span12Mux_s7_v.I Odrv12.O Span12Mux_s8_h.I Odrv12.O Span12Mux_s8_v.I Odrv12.O Span12Mux_s9_h.I Odrv12.O Span12Mux_s9_v.I Odrv12.O Span12Mux_v.I Odrv4.O IoSpan4Mux.I Odrv4.O LocalMux.I Odrv4.O Span4Mux_h.I Odrv4.O Span4Mux_s0_h.I Odrv4.O Span4Mux_s0_v.I Odrv4.O Span4Mux_s1_h.I Odrv4.O Span4Mux_s1_v.I Odrv4.O Span4Mux_s2_h.I Odrv4.O Span4Mux_s2_v.I Odrv4.O Span4Mux_s3_h.I Odrv4.O Span4Mux_s3_v.I Odrv4.O Span4Mux_v.I PLL40.LOCK LocalMux.I PLL40.PLLOUTCORE LocalMux.I PLL40.PLLOUTCORE Odrv12.I PLL40.PLLOUTCORE Odrv4.I PLL40.PLLOUTGLOBAL GlobalMux.I PLL40.SDO LocalMux.I PLL40_2.LOCK LocalMux.I PLL40_2.PLLOUTCOREA LocalMux.I PLL40_2.PLLOUTCOREA Odrv12.I PLL40_2.PLLOUTCOREA Odrv4.I PLL40_2.PLLOUTCOREB LocalMux.I PLL40_2.PLLOUTCOREB Odrv12.I PLL40_2.PLLOUTCOREB Odrv4.I PLL40_2.PLLOUTGLOBALA GlobalMux.I PLL40_2.PLLOUTGLOBALB GlobalMux.I PLL40_2.SDO LocalMux.I PLL40_2F.LOCK LocalMux.I PLL40_2F.PLLOUTCOREA LocalMux.I PLL40_2F.PLLOUTCOREA Odrv12.I PLL40_2F.PLLOUTCOREA Odrv4.I PLL40_2F.PLLOUTCOREB LocalMux.I PLL40_2F.PLLOUTCOREB Odrv12.I PLL40_2F.PLLOUTCOREB Odrv4.I PLL40_2F.PLLOUTGLOBALA GlobalMux.I PLL40_2F.PLLOUTGLOBALB GlobalMux.I PLL40_2F.SDO LocalMux.I PRE_IO.DIN0 LocalMux.I PRE_IO.DIN0 Odrv12.I PRE_IO.DIN0 Odrv4.I PRE_IO.DIN1 LocalMux.I PRE_IO.DIN1 Odrv12.I PRE_IO.DIN1 Odrv4.I PRE_IO.PADOEN IO_PAD.OE PRE_IO.PADOUT IO_PAD.DIN PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I SB_PLL40_2F_CORE.LOCK LocalMux.I SB_PLL40_2F_CORE.PLLOUTCOREA LocalMux.I SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I SB_PLL40_2F_CORE.PLLOUTCOREA Odrv4.I SB_PLL40_2F_CORE.PLLOUTCOREB LocalMux.I SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I SB_PLL40_2F_CORE.PLLOUTCOREB Odrv4.I SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I SB_PLL40_2F_CORE.SDO LocalMux.I SB_PLL40_CORE.LOCK LocalMux.I SB_PLL40_CORE.PLLOUTCORE LocalMux.I SB_PLL40_CORE.PLLOUTCORE Odrv12.I SB_PLL40_CORE.PLLOUTCORE Odrv4.I SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I SB_PLL40_CORE.SDO LocalMux.I SB_RAM40_4K.RDATA[0] LocalMux.I SB_RAM40_4K.RDATA[0] Odrv12.I SB_RAM40_4K.RDATA[0] Odrv4.I SB_RAM40_4K.RDATA[10] LocalMux.I SB_RAM40_4K.RDATA[10] Odrv12.I SB_RAM40_4K.RDATA[10] Odrv4.I SB_RAM40_4K.RDATA[11] LocalMux.I SB_RAM40_4K.RDATA[11] Odrv12.I SB_RAM40_4K.RDATA[11] Odrv4.I SB_RAM40_4K.RDATA[12] LocalMux.I SB_RAM40_4K.RDATA[12] Odrv12.I SB_RAM40_4K.RDATA[12] Odrv4.I SB_RAM40_4K.RDATA[13] LocalMux.I SB_RAM40_4K.RDATA[13] Odrv12.I SB_RAM40_4K.RDATA[13] Odrv4.I SB_RAM40_4K.RDATA[14] LocalMux.I SB_RAM40_4K.RDATA[14] Odrv12.I SB_RAM40_4K.RDATA[14] Odrv4.I SB_RAM40_4K.RDATA[15] LocalMux.I SB_RAM40_4K.RDATA[15] Odrv12.I SB_RAM40_4K.RDATA[15] Odrv4.I SB_RAM40_4K.RDATA[1] LocalMux.I SB_RAM40_4K.RDATA[1] Odrv12.I SB_RAM40_4K.RDATA[1] Odrv4.I SB_RAM40_4K.RDATA[2] LocalMux.I SB_RAM40_4K.RDATA[2] Odrv12.I SB_RAM40_4K.RDATA[2] Odrv4.I SB_RAM40_4K.RDATA[3] LocalMux.I SB_RAM40_4K.RDATA[3] Odrv12.I SB_RAM40_4K.RDATA[3] Odrv4.I SB_RAM40_4K.RDATA[4] LocalMux.I SB_RAM40_4K.RDATA[4] Odrv12.I SB_RAM40_4K.RDATA[4] Odrv4.I SB_RAM40_4K.RDATA[5] LocalMux.I SB_RAM40_4K.RDATA[5] Odrv12.I SB_RAM40_4K.RDATA[5] Odrv4.I SB_RAM40_4K.RDATA[6] LocalMux.I SB_RAM40_4K.RDATA[6] Odrv12.I SB_RAM40_4K.RDATA[6] Odrv4.I SB_RAM40_4K.RDATA[7] LocalMux.I SB_RAM40_4K.RDATA[7] Odrv12.I SB_RAM40_4K.RDATA[7] Odrv4.I SB_RAM40_4K.RDATA[8] LocalMux.I SB_RAM40_4K.RDATA[8] Odrv12.I SB_RAM40_4K.RDATA[8] Odrv4.I SB_RAM40_4K.RDATA[9] LocalMux.I SB_RAM40_4K.RDATA[9] Odrv12.I SB_RAM40_4K.RDATA[9] Odrv4.I SRMux.O LogicCell40.sr SRMux.O SB_RAM40_4K.RE SRMux.O SB_RAM40_4K.WE Sp12to4.O IoSpan4Mux.I Sp12to4.O LocalMux.I Sp12to4.O Span4Mux_h.I Sp12to4.O Span4Mux_s0_h.I Sp12to4.O Span4Mux_s0_v.I Sp12to4.O Span4Mux_s1_h.I Sp12to4.O Span4Mux_s1_v.I Sp12to4.O Span4Mux_s2_h.I Sp12to4.O Span4Mux_s2_v.I Sp12to4.O Span4Mux_s3_h.I Sp12to4.O Span4Mux_s3_v.I Sp12to4.O Span4Mux_v.I Span12Mux_h.O LocalMux.I Span12Mux_h.O Sp12to4.I Span12Mux_h.O Span12Mux_h.I Span12Mux_h.O Span12Mux_s0_h.I Span12Mux_h.O Span12Mux_s0_v.I Span12Mux_h.O Span12Mux_s10_h.I Span12Mux_h.O Span12Mux_s10_v.I Span12Mux_h.O Span12Mux_s11_h.I Span12Mux_h.O Span12Mux_s11_v.I Span12Mux_h.O Span12Mux_s1_h.I Span12Mux_h.O Span12Mux_s1_v.I Span12Mux_h.O Span12Mux_s2_h.I Span12Mux_h.O Span12Mux_s2_v.I Span12Mux_h.O Span12Mux_s3_h.I Span12Mux_h.O Span12Mux_s3_v.I Span12Mux_h.O Span12Mux_s4_h.I Span12Mux_h.O Span12Mux_s4_v.I Span12Mux_h.O Span12Mux_s5_h.I Span12Mux_h.O Span12Mux_s5_v.I Span12Mux_h.O Span12Mux_s6_h.I Span12Mux_h.O Span12Mux_s6_v.I Span12Mux_h.O Span12Mux_s7_h.I Span12Mux_h.O Span12Mux_s7_v.I Span12Mux_h.O Span12Mux_s8_h.I Span12Mux_h.O Span12Mux_s8_v.I Span12Mux_h.O Span12Mux_s9_h.I Span12Mux_h.O Span12Mux_s9_v.I Span12Mux_h.O Span12Mux_v.I Span12Mux_s0_h.O LocalMux.I Span12Mux_s0_h.O Sp12to4.I Span12Mux_s0_h.O Span12Mux_h.I Span12Mux_s0_h.O Span12Mux_s11_h.I Span12Mux_s0_h.O Span12Mux_s1_v.I Span12Mux_s0_h.O Span12Mux_v.I Span12Mux_s0_v.O LocalMux.I Span12Mux_s0_v.O Sp12to4.I Span12Mux_s0_v.O Span12Mux_h.I Span12Mux_s0_v.O Span12Mux_v.I Span12Mux_s10_h.O LocalMux.I Span12Mux_s10_h.O Sp12to4.I Span12Mux_s10_h.O Span12Mux_h.I Span12Mux_s10_h.O Span12Mux_s10_v.I Span12Mux_s10_h.O Span12Mux_s11_v.I Span12Mux_s10_h.O Span12Mux_s2_v.I Span12Mux_s10_h.O Span12Mux_s4_v.I Span12Mux_s10_h.O Span12Mux_s5_v.I Span12Mux_s10_h.O Span12Mux_s6_v.I Span12Mux_s10_h.O Span12Mux_s8_v.I Span12Mux_s10_h.O Span12Mux_s9_v.I Span12Mux_s10_h.O Span12Mux_v.I Span12Mux_s10_v.O LocalMux.I Span12Mux_s10_v.O Sp12to4.I Span12Mux_s10_v.O Span12Mux_h.I Span12Mux_s10_v.O Span12Mux_s10_h.I Span12Mux_s10_v.O Span12Mux_s5_v.I Span12Mux_s10_v.O Span12Mux_s7_h.I Span12Mux_s10_v.O Span12Mux_s8_h.I Span12Mux_s10_v.O Span12Mux_s9_h.I Span12Mux_s10_v.O Span12Mux_v.I Span12Mux_s11_h.O LocalMux.I Span12Mux_s11_h.O Sp12to4.I Span12Mux_s11_h.O Span12Mux_h.I Span12Mux_s11_h.O Span12Mux_s0_h.I Span12Mux_s11_h.O Span12Mux_s10_v.I Span12Mux_s11_h.O Span12Mux_s11_v.I Span12Mux_s11_h.O Span12Mux_s6_v.I Span12Mux_s11_h.O Span12Mux_s9_v.I Span12Mux_s11_h.O Span12Mux_v.I Span12Mux_s11_v.O LocalMux.I Span12Mux_s11_v.O Sp12to4.I Span12Mux_s11_v.O Span12Mux_h.I Span12Mux_s11_v.O Span12Mux_s4_v.I Span12Mux_s11_v.O Span12Mux_s8_h.I Span12Mux_s11_v.O Span12Mux_s9_h.I Span12Mux_s11_v.O Span12Mux_v.I Span12Mux_s1_h.O LocalMux.I Span12Mux_s1_h.O Sp12to4.I Span12Mux_s1_h.O Span12Mux_h.I Span12Mux_s1_h.O Span12Mux_s10_h.I Span12Mux_s1_h.O Span12Mux_s3_v.I Span12Mux_s1_h.O Span12Mux_s6_v.I Span12Mux_s1_h.O Span12Mux_s9_v.I Span12Mux_s1_h.O Span12Mux_v.I Span12Mux_s1_v.O LocalMux.I Span12Mux_s1_v.O Sp12to4.I Span12Mux_s1_v.O Span12Mux_v.I Span12Mux_s2_h.O LocalMux.I Span12Mux_s2_h.O Sp12to4.I Span12Mux_s2_h.O Span12Mux_h.I Span12Mux_s2_h.O Span12Mux_s0_v.I Span12Mux_s2_h.O Span12Mux_s10_v.I Span12Mux_s2_h.O Span12Mux_s11_v.I Span12Mux_s2_h.O Span12Mux_s1_v.I Span12Mux_s2_h.O Span12Mux_s2_v.I Span12Mux_s2_h.O Span12Mux_s3_v.I Span12Mux_s2_h.O Span12Mux_s4_v.I Span12Mux_s2_h.O Span12Mux_s6_v.I Span12Mux_s2_h.O Span12Mux_s8_v.I Span12Mux_s2_h.O Span12Mux_s9_h.I Span12Mux_s2_h.O Span12Mux_s9_v.I Span12Mux_s2_h.O Span12Mux_v.I Span12Mux_s2_v.O LocalMux.I Span12Mux_s2_v.O Sp12to4.I Span12Mux_s2_v.O Span12Mux_h.I Span12Mux_s2_v.O Span12Mux_s2_h.I Span12Mux_s2_v.O Span12Mux_s5_h.I Span12Mux_s2_v.O Span12Mux_s9_h.I Span12Mux_s2_v.O Span12Mux_v.I Span12Mux_s3_h.O LocalMux.I Span12Mux_s3_h.O Sp12to4.I Span12Mux_s3_h.O Span12Mux_h.I Span12Mux_s3_h.O Span12Mux_s10_v.I Span12Mux_s3_h.O Span12Mux_s11_v.I Span12Mux_s3_h.O Span12Mux_s1_v.I Span12Mux_s3_h.O Span12Mux_s2_v.I Span12Mux_s3_h.O Span12Mux_s4_v.I Span12Mux_s3_h.O Span12Mux_s6_v.I Span12Mux_s3_h.O Span12Mux_s7_v.I Span12Mux_s3_h.O Span12Mux_s8_h.I Span12Mux_s3_h.O Span12Mux_s8_v.I Span12Mux_s3_h.O Span12Mux_s9_v.I Span12Mux_s3_h.O Span12Mux_v.I Span12Mux_s3_v.O LocalMux.I Span12Mux_s3_v.O Sp12to4.I Span12Mux_s3_v.O Span12Mux_h.I Span12Mux_s3_v.O Span12Mux_s8_h.I Span12Mux_s3_v.O Span12Mux_v.I Span12Mux_s4_h.O LocalMux.I Span12Mux_s4_h.O Sp12to4.I Span12Mux_s4_h.O Span12Mux_h.I Span12Mux_s4_h.O Span12Mux_s2_v.I Span12Mux_s4_h.O Span12Mux_s3_v.I Span12Mux_s4_h.O Span12Mux_s4_v.I Span12Mux_s4_h.O Span12Mux_s6_v.I Span12Mux_s4_h.O Span12Mux_s7_h.I Span12Mux_s4_h.O Span12Mux_s7_v.I Span12Mux_s4_h.O Span12Mux_s8_v.I Span12Mux_s4_h.O Span12Mux_v.I Span12Mux_s4_v.O LocalMux.I Span12Mux_s4_v.O Sp12to4.I Span12Mux_s4_v.O Span12Mux_h.I Span12Mux_s4_v.O Span12Mux_s10_h.I Span12Mux_s4_v.O Span12Mux_s11_h.I Span12Mux_s4_v.O Span12Mux_s11_v.I Span12Mux_s4_v.O Span12Mux_s2_h.I Span12Mux_s4_v.O Span12Mux_s8_h.I Span12Mux_s4_v.O Span12Mux_v.I Span12Mux_s5_h.O LocalMux.I Span12Mux_s5_h.O Sp12to4.I Span12Mux_s5_h.O Span12Mux_h.I Span12Mux_s5_h.O Span12Mux_s10_v.I Span12Mux_s5_h.O Span12Mux_s11_v.I Span12Mux_s5_h.O Span12Mux_s6_h.I Span12Mux_s5_h.O Span12Mux_s7_v.I Span12Mux_s5_h.O Span12Mux_s8_v.I Span12Mux_s5_h.O Span12Mux_s9_v.I Span12Mux_s5_h.O Span12Mux_v.I Span12Mux_s5_v.O LocalMux.I Span12Mux_s5_v.O Sp12to4.I Span12Mux_s5_v.O Span12Mux_h.I Span12Mux_s5_v.O Span12Mux_s10_h.I Span12Mux_s5_v.O Span12Mux_s10_v.I Span12Mux_s5_v.O Span12Mux_s5_h.I Span12Mux_s5_v.O Span12Mux_s8_h.I Span12Mux_s5_v.O Span12Mux_v.I Span12Mux_s6_h.O LocalMux.I Span12Mux_s6_h.O Sp12to4.I Span12Mux_s6_h.O Span12Mux_h.I Span12Mux_s6_h.O Span12Mux_s0_v.I Span12Mux_s6_h.O Span12Mux_s10_v.I Span12Mux_s6_h.O Span12Mux_s11_v.I Span12Mux_s6_h.O Span12Mux_s3_v.I Span12Mux_s6_h.O Span12Mux_s5_h.I Span12Mux_s6_h.O Span12Mux_s5_v.I Span12Mux_s6_h.O Span12Mux_s6_v.I Span12Mux_s6_h.O Span12Mux_s7_v.I Span12Mux_s6_h.O Span12Mux_s8_v.I Span12Mux_s6_h.O Span12Mux_s9_v.I Span12Mux_s6_h.O Span12Mux_v.I Span12Mux_s6_v.O LocalMux.I Span12Mux_s6_v.O Sp12to4.I Span12Mux_s6_v.O Span12Mux_h.I Span12Mux_s6_v.O Span12Mux_s10_h.I Span12Mux_s6_v.O Span12Mux_s5_h.I Span12Mux_s6_v.O Span12Mux_s7_h.I Span12Mux_s6_v.O Span12Mux_s8_h.I Span12Mux_s6_v.O Span12Mux_s9_h.I Span12Mux_s6_v.O Span12Mux_s9_v.I Span12Mux_s6_v.O Span12Mux_v.I Span12Mux_s7_h.O LocalMux.I Span12Mux_s7_h.O Sp12to4.I Span12Mux_s7_h.O Span12Mux_h.I Span12Mux_s7_h.O Span12Mux_s10_v.I Span12Mux_s7_h.O Span12Mux_s11_v.I Span12Mux_s7_h.O Span12Mux_s1_v.I Span12Mux_s7_h.O Span12Mux_s4_h.I Span12Mux_s7_h.O Span12Mux_s4_v.I Span12Mux_s7_h.O Span12Mux_s5_v.I Span12Mux_s7_h.O Span12Mux_s6_v.I Span12Mux_s7_h.O Span12Mux_s7_v.I Span12Mux_s7_h.O Span12Mux_s8_v.I Span12Mux_s7_h.O Span12Mux_s9_v.I Span12Mux_s7_h.O Span12Mux_v.I Span12Mux_s7_v.O LocalMux.I Span12Mux_s7_v.O Sp12to4.I Span12Mux_s7_v.O Span12Mux_h.I Span12Mux_s7_v.O Span12Mux_s10_h.I Span12Mux_s7_v.O Span12Mux_s11_h.I Span12Mux_s7_v.O Span12Mux_s6_h.I Span12Mux_s7_v.O Span12Mux_s7_h.I Span12Mux_s7_v.O Span12Mux_s8_h.I Span12Mux_s7_v.O Span12Mux_s8_v.I Span12Mux_s7_v.O Span12Mux_s9_h.I Span12Mux_s7_v.O Span12Mux_v.I Span12Mux_s8_h.O LocalMux.I Span12Mux_s8_h.O Sp12to4.I Span12Mux_s8_h.O Span12Mux_h.I Span12Mux_s8_h.O Span12Mux_s10_v.I Span12Mux_s8_h.O Span12Mux_s11_v.I Span12Mux_s8_h.O Span12Mux_s2_v.I Span12Mux_s8_h.O Span12Mux_s3_h.I Span12Mux_s8_h.O Span12Mux_s3_v.I Span12Mux_s8_h.O Span12Mux_s4_v.I Span12Mux_s8_h.O Span12Mux_s5_v.I Span12Mux_s8_h.O Span12Mux_s6_v.I Span12Mux_s8_h.O Span12Mux_s7_v.I Span12Mux_s8_h.O Span12Mux_s8_v.I Span12Mux_s8_h.O Span12Mux_s9_v.I Span12Mux_s8_h.O Span12Mux_v.I Span12Mux_s8_v.O LocalMux.I Span12Mux_s8_v.O Sp12to4.I Span12Mux_s8_v.O Span12Mux_h.I Span12Mux_s8_v.O Span12Mux_s10_h.I Span12Mux_s8_v.O Span12Mux_s11_h.I Span12Mux_s8_v.O Span12Mux_s2_h.I Span12Mux_s8_v.O Span12Mux_s7_h.I Span12Mux_s8_v.O Span12Mux_s7_v.I Span12Mux_s8_v.O Span12Mux_s8_h.I Span12Mux_s8_v.O Span12Mux_v.I Span12Mux_s9_h.O LocalMux.I Span12Mux_s9_h.O Sp12to4.I Span12Mux_s9_h.O Span12Mux_h.I Span12Mux_s9_h.O Span12Mux_s0_v.I Span12Mux_s9_h.O Span12Mux_s10_v.I Span12Mux_s9_h.O Span12Mux_s11_v.I Span12Mux_s9_h.O Span12Mux_s1_v.I Span12Mux_s9_h.O Span12Mux_s2_h.I Span12Mux_s9_h.O Span12Mux_s2_v.I Span12Mux_s9_h.O Span12Mux_s4_v.I Span12Mux_s9_h.O Span12Mux_s5_v.I Span12Mux_s9_h.O Span12Mux_s8_v.I Span12Mux_s9_h.O Span12Mux_s9_v.I Span12Mux_s9_h.O Span12Mux_v.I Span12Mux_s9_v.O LocalMux.I Span12Mux_s9_v.O Sp12to4.I Span12Mux_s9_v.O Span12Mux_h.I Span12Mux_s9_v.O Span12Mux_s11_h.I Span12Mux_s9_v.O Span12Mux_s5_h.I Span12Mux_s9_v.O Span12Mux_s6_v.I Span12Mux_s9_v.O Span12Mux_s7_h.I Span12Mux_s9_v.O Span12Mux_v.I Span12Mux_v.O LocalMux.I Span12Mux_v.O Sp12to4.I Span12Mux_v.O Span12Mux_h.I Span12Mux_v.O Span12Mux_s0_h.I Span12Mux_v.O Span12Mux_s0_v.I Span12Mux_v.O Span12Mux_s10_h.I Span12Mux_v.O Span12Mux_s10_v.I Span12Mux_v.O Span12Mux_s11_h.I Span12Mux_v.O Span12Mux_s11_v.I Span12Mux_v.O Span12Mux_s1_h.I Span12Mux_v.O Span12Mux_s1_v.I Span12Mux_v.O Span12Mux_s2_h.I Span12Mux_v.O Span12Mux_s2_v.I Span12Mux_v.O Span12Mux_s3_h.I Span12Mux_v.O Span12Mux_s3_v.I Span12Mux_v.O Span12Mux_s4_h.I Span12Mux_v.O Span12Mux_s4_v.I Span12Mux_v.O Span12Mux_s5_h.I Span12Mux_v.O Span12Mux_s5_v.I Span12Mux_v.O Span12Mux_s6_h.I Span12Mux_v.O Span12Mux_s6_v.I Span12Mux_v.O Span12Mux_s7_h.I Span12Mux_v.O Span12Mux_s7_v.I Span12Mux_v.O Span12Mux_s8_h.I Span12Mux_v.O Span12Mux_s8_v.I Span12Mux_v.O Span12Mux_s9_h.I Span12Mux_v.O Span12Mux_s9_v.I Span12Mux_v.O Span12Mux_v.I Span4Mux_h.O LocalMux.I Span4Mux_h.O Span4Mux_h.I Span4Mux_h.O Span4Mux_s0_h.I Span4Mux_h.O Span4Mux_s0_v.I Span4Mux_h.O Span4Mux_s1_h.I Span4Mux_h.O Span4Mux_s1_v.I Span4Mux_h.O Span4Mux_s2_h.I Span4Mux_h.O Span4Mux_s2_v.I Span4Mux_h.O Span4Mux_s3_h.I Span4Mux_h.O Span4Mux_s3_v.I Span4Mux_h.O Span4Mux_v.I Span4Mux_s0_h.O IoSpan4Mux.I Span4Mux_s0_h.O LocalMux.I Span4Mux_s0_h.O Span4Mux_h.I Span4Mux_s0_h.O Span4Mux_s0_v.I Span4Mux_s0_h.O Span4Mux_s1_v.I Span4Mux_s0_h.O Span4Mux_s2_v.I Span4Mux_s0_h.O Span4Mux_s3_v.I Span4Mux_s0_h.O Span4Mux_v.I Span4Mux_s0_v.O IoSpan4Mux.I Span4Mux_s0_v.O LocalMux.I Span4Mux_s0_v.O Span4Mux_h.I Span4Mux_s0_v.O Span4Mux_s0_h.I Span4Mux_s0_v.O Span4Mux_s1_h.I Span4Mux_s0_v.O Span4Mux_s2_h.I Span4Mux_s0_v.O Span4Mux_s3_h.I Span4Mux_s0_v.O Span4Mux_v.I Span4Mux_s1_h.O IoSpan4Mux.I Span4Mux_s1_h.O LocalMux.I Span4Mux_s1_h.O Span4Mux_h.I Span4Mux_s1_h.O Span4Mux_s0_v.I Span4Mux_s1_h.O Span4Mux_s1_v.I Span4Mux_s1_h.O Span4Mux_s2_v.I Span4Mux_s1_h.O Span4Mux_s3_v.I Span4Mux_s1_h.O Span4Mux_v.I Span4Mux_s1_v.O IoSpan4Mux.I Span4Mux_s1_v.O LocalMux.I Span4Mux_s1_v.O Span4Mux_h.I Span4Mux_s1_v.O Span4Mux_s0_h.I Span4Mux_s1_v.O Span4Mux_s1_h.I Span4Mux_s1_v.O Span4Mux_s2_h.I Span4Mux_s1_v.O Span4Mux_s3_h.I Span4Mux_s1_v.O Span4Mux_v.I Span4Mux_s2_h.O IoSpan4Mux.I Span4Mux_s2_h.O LocalMux.I Span4Mux_s2_h.O Span4Mux_h.I Span4Mux_s2_h.O Span4Mux_s0_v.I Span4Mux_s2_h.O Span4Mux_s1_v.I Span4Mux_s2_h.O Span4Mux_s2_v.I Span4Mux_s2_h.O Span4Mux_s3_v.I Span4Mux_s2_h.O Span4Mux_v.I Span4Mux_s2_v.O IoSpan4Mux.I Span4Mux_s2_v.O LocalMux.I Span4Mux_s2_v.O Span4Mux_h.I Span4Mux_s2_v.O Span4Mux_s0_h.I Span4Mux_s2_v.O Span4Mux_s1_h.I Span4Mux_s2_v.O Span4Mux_s2_h.I Span4Mux_s2_v.O Span4Mux_s3_h.I Span4Mux_s2_v.O Span4Mux_v.I Span4Mux_s3_h.O IoSpan4Mux.I Span4Mux_s3_h.O LocalMux.I Span4Mux_s3_h.O Span4Mux_h.I Span4Mux_s3_h.O Span4Mux_s0_v.I Span4Mux_s3_h.O Span4Mux_s1_v.I Span4Mux_s3_h.O Span4Mux_s2_v.I Span4Mux_s3_h.O Span4Mux_s3_v.I Span4Mux_s3_h.O Span4Mux_v.I Span4Mux_s3_v.O IoSpan4Mux.I Span4Mux_s3_v.O LocalMux.I Span4Mux_s3_v.O Span4Mux_h.I Span4Mux_s3_v.O Span4Mux_s0_h.I Span4Mux_s3_v.O Span4Mux_s1_h.I Span4Mux_s3_v.O Span4Mux_s2_h.I Span4Mux_s3_v.O Span4Mux_s3_h.I Span4Mux_s3_v.O Span4Mux_v.I Span4Mux_v.O LocalMux.I Span4Mux_v.O Span4Mux_h.I Span4Mux_v.O Span4Mux_s0_h.I Span4Mux_v.O Span4Mux_s0_v.I Span4Mux_v.O Span4Mux_s1_h.I Span4Mux_v.O Span4Mux_s1_v.I Span4Mux_v.O Span4Mux_s2_h.I Span4Mux_v.O Span4Mux_s2_v.I Span4Mux_v.O Span4Mux_s3_h.I Span4Mux_v.O Span4Mux_s3_v.I Span4Mux_v.O Span4Mux_v.I VCC.Y IO_PAD.OE VCC.Y PRE_IO.CLOCKENABLE gio2CtrlBuf.O GlobalMux.I fpga-icestorm-0~20160913git266e758/icefuzz/tmedges.ys000066400000000000000000000020751276746530600220620ustar00rootroot00000000000000hierarchy -generate LogicCell40 i:in* i:*in i:clk i:ce i:sr o:*out hierarchy -generate ICE_GB i:USERSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT hierarchy -generate PRE_IO_GBUF i:PADSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT hierarchy -generate VCC o:* hierarchy -generate GND o:* hierarchy -generate IO_PAD i:OE i:DIN o:DOUT io:PACKAGEPIN hierarchy -generate PRE_IO o:PADOEN o:PADOUT i:PADIN i:CLOCKENABLE o:DIN0 o:DIN1 \ i:DOUT0 i:DOUT1 i:INPUTCLK i:LATCHINPUTVALUE i:OUTPUTCLK i:OUTPUTENABLE hierarchy -generate *PLL40* i:PACKAGEPIN i:BYPASS i:DYNAMICDELAY i:EXTFEEDBACK i:LATCHINPUTVALUE \ o:LOCK o:PLLOUT* i:REFERENCECLK i:RESETB i:SCLK i:SDI o:SDO i:PLLIN hierarchy -generate SB_RAM40_4K o:RDATA i:RADDR i:WADDR i:MASK i:WDATA i:RCLKE i:RCLK i:RE i:WCLKE i:WCLK i:WE hierarchy -generate ICE_CARRY_IN_MUX i:*in o:*out hierarchy -generate *Mux* i:I o:O hierarchy -generate Odrv* i:I o:O hierarchy -generate Sp12to4 i:I o:O hierarchy -generate INV i:I o:O hierarchy -generate gio2CtrlBuf i:I o:O hierarchy -generate CascadeBuf i:I o:O hierarchy -check tee -a tmedges.tmp edgetypes fpga-icestorm-0~20160913git266e758/icemulti/000077500000000000000000000000001276746530600202055ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icemulti/.gitignore000066400000000000000000000000541276746530600221740ustar00rootroot00000000000000icemulti icemulti.exe icemulti.o icemulti.d fpga-icestorm-0~20160913git266e758/icemulti/Makefile000066400000000000000000000007311276746530600216460ustar00rootroot00000000000000include ../config.mk LDLIBS = -lm -lstdc++ CXXFLAGS = -MD -O0 -ggdb -Wall -std=c++11 ifeq ($(STATIC),1) LDFLAGS += -static endif all: icemulti$(EXE) icemulti$(EXE): icemulti.o $(CC) -o $@ $(LDFLAGS) $^ $(LDLIBS) install: all mkdir -p $(DESTDIR)$(PREFIX)/bin cp icemulti $(DESTDIR)$(PREFIX)/bin/icemulti uninstall: rm -f $(DESTDIR)$(PREFIX)/bin/icemulti clean: rm -f icemulti rm -f icemulti.exe rm -f *.o *.d -include *.d .PHONY: all install uninstall clean fpga-icestorm-0~20160913git266e758/icemulti/icemulti.cc000066400000000000000000000164021276746530600223320ustar00rootroot00000000000000// // Copyright (C) 2015 Marcus Comstedt // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. // #include #include #include #include #include #include #define log(...) fprintf(stderr, __VA_ARGS__); #define info(...) do { if (log_level > 0) fprintf(stderr, __VA_ARGS__); } while (0) #define error(...) do { fprintf(stderr, "Error: " __VA_ARGS__); exit(1); } while (0) int log_level = 0; static const int NUM_IMAGES = 4; static const int NUM_HEADERS = NUM_IMAGES + 1; static const int HEADER_SIZE = 32; static void write_byte(std::ostream &ofs, uint32_t &file_offset, uint8_t byte) { ofs << byte; file_offset++; } static void write_bytes(std::ostream &ofs, uint32_t &file_offset, const uint8_t *buf, size_t n) { if (n > 0) { ofs.write(reinterpret_cast(buf), n); file_offset += n; } } static void write_file(std::ostream &ofs, uint32_t &file_offset, std::istream &ifs) { const size_t bufsize = 8192; uint8_t *buffer = new uint8_t[bufsize]; while(!ifs.eof()) { ifs.read(reinterpret_cast(buffer), bufsize); if (ifs.bad()) error("Read error on input image"); write_bytes(ofs, file_offset, buffer, ifs.gcount()); } delete[] buffer; } static void pad_to(std::ostream &ofs, uint32_t &file_offset, uint32_t target) { if (target < file_offset) error("Trying to pad backwards!\n"); while(file_offset < target) write_byte(ofs, file_offset, 0xff); } class Image { std::ifstream ifs; uint32_t offs; public: Image(const char *filename) : ifs(filename, std::ifstream::binary) {} size_t size(); void write(std::ostream &ofs, uint32_t &file_offset); void place(uint32_t o) { offs = o; } uint32_t offset() const { return offs; } }; size_t Image::size() { ifs.seekg (0, ifs.end); size_t length = ifs.tellg(); ifs.seekg (0, ifs.beg); return length; } void Image::write(std::ostream &ofs, uint32_t &file_offset) { write_file(ofs, file_offset, ifs); } class Header { uint32_t image_offs; bool coldboot_flag; bool empty; public: Header() : empty(true) {} Header(const Image &i) : image_offs(i.offset()), coldboot_flag(false), empty(false) {} void set_coldboot_flag() { coldboot_flag = true; } void write(std::ostream &ofs, uint32_t &file_offset); }; void Header::write(std::ostream &ofs, uint32_t &file_offset) { if (empty) return; // Preamble write_byte(ofs, file_offset, 0x7e); write_byte(ofs, file_offset, 0xaa); write_byte(ofs, file_offset, 0x99); write_byte(ofs, file_offset, 0x7e); // Boot mode write_byte(ofs, file_offset, 0x92); write_byte(ofs, file_offset, 0x00); write_byte(ofs, file_offset, (coldboot_flag? 0x10: 0x00)); // Boot address write_byte(ofs, file_offset, 0x44); write_byte(ofs, file_offset, 0x03); write_byte(ofs, file_offset, (image_offs >> 16) & 0xff); write_byte(ofs, file_offset, (image_offs >> 8) & 0xff); write_byte(ofs, file_offset, image_offs & 0xff); // Bank offset write_byte(ofs, file_offset, 0x82); write_byte(ofs, file_offset, 0x00); write_byte(ofs, file_offset, 0x00); // Reboot write_byte(ofs, file_offset, 0x01); write_byte(ofs, file_offset, 0x08); // Zero out any unused bytes while (file_offset & (HEADER_SIZE - 1)) write_byte(ofs, file_offset, 0x00); } void usage() { log("\n"); log("Usage: icemulti [options] input-files\n"); log("\n"); log(" -c\n"); log(" coldboot mode, power on reset image is selected by CBSEL0/CBSEL1\n"); log("\n"); log(" -p0, -p1, -p2, -p3\n"); log(" select power on reset image when not using coldboot mode\n"); log("\n"); log(" -o filename\n"); log(" write output image to file instead of stdout\n"); log("\n"); log(" -v\n"); log(" verbose (repeat to increase verbosity)\n"); log("\n"); exit(1); } int main(int argc, char **argv) { bool coldboot = false; int por_image = 0; int image_count = 0; Header headers[NUM_HEADERS]; std::unique_ptr images[NUM_IMAGES]; const char *outfile_name = NULL; for (int i = 1; i < argc; i++) { if (argv[i][0] == '-' && argv[i][1]) { for (int j = 1; argv[i][j]; j++) if (argv[i][j] == 'c') { coldboot = true; } else if (argv[i][j] == 'p' && argv[i][j+1]) { por_image = argv[i][++j] - '0'; } else if (argv[i][j] == 'o') { if (argv[i][j+1]) outfile_name = &argv[i][j+1]; else if(i+1 < argc) outfile_name = argv[++i]; else usage(); break; } else if (argv[i][j] == 'v') { log_level++; } else usage(); continue; } if (image_count >= NUM_IMAGES) error("Too many images supplied\n"); images[image_count++].reset(new Image(argv[i])); } if (!image_count) usage(); if (coldboot && por_image != 0) error("Can't select power on reset boot image in cold boot mode\n"); if (por_image >= image_count) error("Specified non-existing image for power on reset\n"); // Place images uint32_t offs = 0x100; for (int i=0; iplace(offs); offs += images[i]->size(); // Align to 4K if (offs & 0xfff) { offs |= 0xfff; offs++; } } // Populate headers for (int i=0; ioffset()); images[i]->write(*osp, file_offset); } info("Done.\n"); return 0; } fpga-icestorm-0~20160913git266e758/icepack/000077500000000000000000000000001276746530600177715ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icepack/.gitignore000066400000000000000000000000621276746530600217570ustar00rootroot00000000000000icepack icepack.exe iceunpack icepack.o icepack.d fpga-icestorm-0~20160913git266e758/icepack/Makefile000066400000000000000000000013741276746530600214360ustar00rootroot00000000000000include ../config.mk LDLIBS = -lm -lstdc++ CXXFLAGS = -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include MXEGCC = /usr/local/src/mxe/usr/bin/i686-pc-mingw32-gcc ifeq ($(STATIC),1) LDFLAGS += -static endif all: icepack$(EXE) iceunpack$(EXE) icepack$(EXE): icepack.o $(CC) -o $@ $(LDFLAGS) $^ $(LDLIBS) iceunpack: icepack ln -sf icepack iceunpack iceunpack.exe: # no iceunpack.exe, use icepack -u install: all mkdir -p $(DESTDIR)$(PREFIX)/bin cp icepack $(DESTDIR)$(PREFIX)/bin/icepack ln -sf icepack $(DESTDIR)$(PREFIX)/bin/iceunpack uninstall: rm -f $(DESTDIR)$(PREFIX)/bin/icepack rm -f $(DESTDIR)$(PREFIX)/bin/iceunpack clean: rm -f icepack rm -f iceunpack rm -f icepack.exe rm -f *.o *.d -include *.d .PHONY: all install uninstall clean fpga-icestorm-0~20160913git266e758/icepack/icepack.cc000066400000000000000000000764431276746530600217150ustar00rootroot00000000000000// // Copyright (C) 2015 Clifford Wolf // // Based on a reference implementation provided by Mathias Lasser // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. // #if !defined(_WIN32) && !defined(_GNU_SOURCE) // for vasprintf() #define _GNU_SOURCE #endif #include #include #include #include #include #include #include #include #include #include #include #ifdef _WIN32 #define __PRETTY_FUNCTION__ __FUNCTION__ #endif using std::vector; using std::string; int log_level = 0; #define log(...) fprintf(stderr, __VA_ARGS__); #define info(...) do { if (log_level > 0) fprintf(stderr, __VA_ARGS__); } while (0) #define debug(...) do { if (log_level > 1) fprintf(stderr, __VA_ARGS__); } while (0) #define error(...) do { fprintf(stderr, "Error: " __VA_ARGS__); exit(1); } while (0) #define panic(fmt, ...) do { fprintf(stderr, "Internal Error at %s:%d: " fmt, __FILE__, __LINE__, ##__VA_ARGS__); abort(); } while (0) string vstringf(const char *fmt, va_list ap) { string string; char *str = NULL; #ifdef _WIN32 int sz = 64, rc; while (1) { va_list apc; va_copy(apc, ap); str = (char*)realloc(str, sz); rc = vsnprintf(str, sz, fmt, apc); va_end(apc); if (rc >= 0 && rc < sz) break; sz *= 2; } #else if (vasprintf(&str, fmt, ap) < 0) str = NULL; #endif if (str != NULL) { string = str; free(str); } return string; } string stringf(const char *fmt, ...) { string string; va_list ap; va_start(ap, fmt); string = vstringf(fmt, ap); va_end(ap); return string; } // ================================================================== // FpgaConfig stuff struct FpgaConfig { string device; string freqrange; string warmboot; // cram[BANK][X][Y] int cram_width, cram_height; vector>> cram; // bram[BANK][X][Y] int bram_width, bram_height; vector>> bram; // data before preamble vector initblop; // bitstream i/o void read_bits(std::istream &ifs); void write_bits(std::ostream &ofs) const; // icebox i/o void read_ascii(std::istream &ifs); void write_ascii(std::ostream &ofs) const; // netpbm i/o void write_cram_pbm(std::ostream &ofs, int bank_num = -1) const; void write_bram_pbm(std::ostream &ofs, int bank_num = -1) const; // query chip type metadata int chip_width() const; int chip_height() const; vector chip_cols() const; // query tile metadata string tile_type(int x, int y) const; int tile_width(const string &type) const; // cram bit manipulation void cram_clear(); void cram_fill_tiles(); void cram_checkerboard(int m = 0); }; struct CramIndexConverter { const FpgaConfig *fpga; int tile_x, tile_y; string tile_type; int tile_width; int column_width; bool left_right_io; bool right_half; bool top_half; int bank_num; int bank_tx; int bank_ty; int bank_xoff; int bank_yoff; CramIndexConverter(const FpgaConfig *fpga, int tile_x, int tile_y); void get_cram_index(int bit_x, int bit_y, int &cram_bank, int &cram_x, int &cram_y) const; }; struct BramIndexConverter { const FpgaConfig *fpga; int tile_x, tile_y; int bank_num; int bank_off; BramIndexConverter(const FpgaConfig *fpga, int tile_x, int tile_y); void get_bram_index(int bit_x, int bit_y, int &bram_bank, int &bram_x, int &bram_y) const; }; static void update_crc16(uint16_t &crc, uint8_t byte) { // CRC-16-CCITT, Initialize to 0xFFFF, No zero padding for (int i = 7; i >= 0; i--) { uint16_t xor_value = ((crc >> 15) ^ ((byte >> i) & 1)) ? 0x1021 : 0; crc = (crc << 1) ^ xor_value; } } static uint8_t read_byte(std::istream &ifs, uint16_t &crc_value, int &file_offset) { int byte = ifs.get(); if (byte < 0) error("Unexpected end of file.\n"); file_offset++; update_crc16(crc_value, byte); return byte; } static void write_byte(std::ostream &ofs, uint16_t &crc_value, int &file_offset, uint8_t byte) { ofs << byte; file_offset++; update_crc16(crc_value, byte); } void FpgaConfig::read_bits(std::istream &ifs) { int file_offset = 0; uint16_t crc_value = 0; debug("## %s\n", __PRETTY_FUNCTION__); info("Parsing bitstream file..\n"); // skip initial comments until preamble is found uint32_t preamble = 0; while (1) { uint8_t byte = read_byte(ifs, crc_value, file_offset); preamble = (preamble << 8) | byte; if (preamble == 0xffffffff) error("No preamble found in bitstream.\n"); if (preamble == 0x7EAA997E) { info("Found preamble at offset %d.\n", file_offset-4); break; } initblop.push_back(byte); } initblop.pop_back(); initblop.pop_back(); initblop.pop_back(); // main parser loop int current_bank = 0; int current_width = 0; int current_height = 0; int current_offset = 0; bool wakeup = false; this->cram_width = 0; this->cram_height = 0; this->bram_width = 0; this->bram_height = 0; while (!wakeup) { // one command byte. the lower 4 bits of the command byte specify // the length of the command payload. uint8_t command = read_byte(ifs, crc_value, file_offset); uint32_t payload = 0; for (int i = 0; i < (command & 0x0f); i++) payload = (payload << 8) | read_byte(ifs, crc_value, file_offset); debug("Next command at offset %d: 0x%02x 0x%0*x\n", file_offset - 1 - (command & 0x0f), command, 2*(command & 0x0f), payload); uint16_t end_token; switch (command & 0xf0) { case 0x00: switch (payload) { case 0x01: info("CRAM Data [%d]: %d x %d bits = %d bits = %d bytes\n", current_bank, current_width, current_height, current_height*current_width, (current_height*current_width)/8); this->cram_width = std::max(this->cram_width, current_width); this->cram_height = std::max(this->cram_height, current_offset + current_height); this->cram.resize(4); this->cram[current_bank].resize(this->cram_width); for (int x = 0; x < current_width; x++) this->cram[current_bank][x].resize(this->cram_height); for (int i = 0; i < (current_height*current_width)/8; i++) { uint8_t byte = read_byte(ifs, crc_value, file_offset); for (int j = 0; j < 8; j++) { int x = (i*8 + j) % current_width; int y = (i*8 + j) / current_width + current_offset; this->cram[current_bank][x][y] = ((byte << j) & 0x80) != 0; } } end_token = read_byte(ifs, crc_value, file_offset); end_token = (end_token << 8) | read_byte(ifs, crc_value, file_offset); if (end_token) error("Expeded 0x0000 after CRAM data, got 0x%04x\n", end_token); break; case 0x03: info("BRAM Data [%d]: %d x %d bits = %d bits = %d bytes\n", current_bank, current_width, current_height, current_height*current_width, (current_height*current_width)/8); this->bram_width = std::max(this->bram_width, current_width); this->bram_height = std::max(this->bram_height, current_offset + current_height); this->bram.resize(4); this->bram[current_bank].resize(this->bram_width); for (int x = 0; x < current_width; x++) this->bram[current_bank][x].resize(this->bram_height); for (int i = 0; i < (current_height*current_width)/8; i++) { uint8_t byte = read_byte(ifs, crc_value, file_offset); for (int j = 0; j < 8; j++) { int x = (i*8 + j) % current_width; int y = (i*8 + j) / current_width + current_offset; this->bram[current_bank][x][y] = ((byte << j) & 0x80) != 0; } } end_token = read_byte(ifs, crc_value, file_offset); end_token = (end_token << 8) | read_byte(ifs, crc_value, file_offset); if (end_token) error("Expeded 0x0000 after BRAM data, got 0x%04x\n", end_token); break; case 0x05: debug("Resetting CRC.\n"); crc_value = 0xffff; break; case 0x06: info("Wakeup.\n"); wakeup = true; break; default: error("Unknown command: 0x%02x 0x%02x\n", command, payload); } break; case 0x10: current_bank = payload; debug("Set bank to %d.\n", current_bank); break; case 0x20: if (crc_value != 0) error("CRC Check FAILED.\n"); info("CRC Check OK.\n"); break; case 0x50: if (payload == 0) this->freqrange = "low"; else if (payload == 1) this->freqrange = "medium"; else if (payload == 2) this->freqrange = "high"; else error("Unknown freqrange payload 0x%02x\n", payload); info("Setting freqrange to '%s'.\n", this->freqrange.c_str()); break; case 0x60: current_width = payload + 1; debug("Setting bank width to %d.\n", current_width); break; case 0x70: current_height = payload; debug("Setting bank height to %d.\n", current_height); break; case 0x80: current_offset = payload; debug("Setting bank offset to %d.\n", current_offset); break; case 0x90: if (payload == 0) this->warmboot = "disabled"; else if (payload == 32) this->warmboot = "enabled"; else error("Unknown warmboot payload 0x%02x\n", payload); info("Setting warmboot to '%s'.\n", this->warmboot.c_str()); break; default: error("Unknown command: 0x%02x 0x%02x\n", command, payload); } } if (this->cram_width == 332 && this->cram_height == 144) this->device = "1k"; else if (this->cram_width == 872 && this->cram_height == 272) this->device = "8k"; else error("Failed to detect chip type.\n"); info("Chip type is '%s'.\n", this->device.c_str()); } void FpgaConfig::write_bits(std::ostream &ofs) const { int file_offset = 0; uint16_t crc_value = 0; debug("## %s\n", __PRETTY_FUNCTION__); info("Writing bitstream file..\n"); for (auto byte : this->initblop) ofs << byte; debug("Writing preamble.\n"); write_byte(ofs, crc_value, file_offset, 0x7E); write_byte(ofs, crc_value, file_offset, 0xAA); write_byte(ofs, crc_value, file_offset, 0x99); write_byte(ofs, crc_value, file_offset, 0x7E); debug("Setting freqrange to '%s'.\n", this->freqrange.c_str()); write_byte(ofs, crc_value, file_offset, 0x51); if (this->freqrange == "low") write_byte(ofs, crc_value, file_offset, 0x00); else if (this->freqrange == "medium") write_byte(ofs, crc_value, file_offset, 0x01); else if (this->freqrange == "high") write_byte(ofs, crc_value, file_offset, 0x02); else error("Unknown freqrange '%s'.\n", this->freqrange.c_str()); debug("Resetting CRC.\n"); write_byte(ofs, crc_value, file_offset, 0x01); write_byte(ofs, crc_value, file_offset, 0x05); crc_value = 0xffff; debug("Setting warmboot to '%s'.\n", this->warmboot.c_str()); write_byte(ofs, crc_value, file_offset, 0x92); write_byte(ofs, crc_value, file_offset, 0x00); if (this->warmboot == "disabled") write_byte(ofs, crc_value, file_offset, 0x00); else if (this->warmboot == "enabled") write_byte(ofs, crc_value, file_offset, 0x20); else error("Unknown warmboot setting '%s'.\n", this->warmboot.c_str()); debug("CRAM: Setting bank width to %d.\n", this->cram_width); write_byte(ofs, crc_value, file_offset, 0x62); write_byte(ofs, crc_value, file_offset, (this->cram_width-1) >> 8); write_byte(ofs, crc_value, file_offset, (this->cram_width-1)); debug("CRAM: Setting bank height to %d.\n", this->cram_height); write_byte(ofs, crc_value, file_offset, 0x72); write_byte(ofs, crc_value, file_offset, this->cram_height >> 8); write_byte(ofs, crc_value, file_offset, this->cram_height); debug("CRAM: Setting bank offset to 0.\n"); write_byte(ofs, crc_value, file_offset, 0x82); write_byte(ofs, crc_value, file_offset, 0x00); write_byte(ofs, crc_value, file_offset, 0x00); for (int cram_bank = 0; cram_bank < 4; cram_bank++) { vector cram_bits; for (int cram_y = 0; cram_y < this->cram_height; cram_y++) for (int cram_x = 0; cram_x < this->cram_width; cram_x++) cram_bits.push_back(this->cram[cram_bank][cram_x][cram_y]); debug("CRAM: Setting bank %d.\n", cram_bank); write_byte(ofs, crc_value, file_offset, 0x11); write_byte(ofs, crc_value, file_offset, cram_bank); debug("CRAM: Writing bank %d data.\n", cram_bank); write_byte(ofs, crc_value, file_offset, 0x01); write_byte(ofs, crc_value, file_offset, 0x01); for (int i = 0; i < int(cram_bits.size()); i += 8) { uint8_t byte = 0; for (int j = 0; j < 8; j++) byte = (byte << 1) | (cram_bits[i+j] ? 1 : 0); write_byte(ofs, crc_value, file_offset, byte); } write_byte(ofs, crc_value, file_offset, 0x00); write_byte(ofs, crc_value, file_offset, 0x00); } int bram_chunk_size = 128; debug("BRAM: Setting bank width to %d.\n", this->bram_width); write_byte(ofs, crc_value, file_offset, 0x62); write_byte(ofs, crc_value, file_offset, (this->bram_width-1) >> 8); write_byte(ofs, crc_value, file_offset, (this->bram_width-1)); debug("BRAM: Setting bank height to %d.\n", this->bram_height); write_byte(ofs, crc_value, file_offset, 0x72); write_byte(ofs, crc_value, file_offset, bram_chunk_size >> 8); write_byte(ofs, crc_value, file_offset, bram_chunk_size); for (int bram_bank = 0; bram_bank < 4; bram_bank++) { debug("BRAM: Setting bank %d.\n", bram_bank); write_byte(ofs, crc_value, file_offset, 0x11); write_byte(ofs, crc_value, file_offset, bram_bank); for (int offset = 0; offset < this->bram_height; offset += bram_chunk_size) { vector bram_bits; for (int bram_y = 0; bram_y < bram_chunk_size; bram_y++) for (int bram_x = 0; bram_x < this->bram_width; bram_x++) bram_bits.push_back(this->bram[bram_bank][bram_x][bram_y+offset]); debug("BRAM: Setting bank offset to %d.\n", offset); write_byte(ofs, crc_value, file_offset, 0x82); write_byte(ofs, crc_value, file_offset, offset >> 8); write_byte(ofs, crc_value, file_offset, offset); debug("BRAM: Writing bank %d data.\n", bram_bank); write_byte(ofs, crc_value, file_offset, 0x01); write_byte(ofs, crc_value, file_offset, 0x03); for (int i = 0; i < int(bram_bits.size()); i += 8) { uint8_t byte = 0; for (int j = 0; j < 8; j++) byte = (byte << 1) | (bram_bits[i+j] ? 1 : 0); write_byte(ofs, crc_value, file_offset, byte); } write_byte(ofs, crc_value, file_offset, 0x00); write_byte(ofs, crc_value, file_offset, 0x00); } } debug("Writing CRC value.\n"); write_byte(ofs, crc_value, file_offset, 0x22); uint8_t crc_hi = crc_value >> 8, crc_lo = crc_value; write_byte(ofs, crc_value, file_offset, crc_hi); write_byte(ofs, crc_value, file_offset, crc_lo); debug("Wakeup.\n"); write_byte(ofs, crc_value, file_offset, 0x01); write_byte(ofs, crc_value, file_offset, 0x06); debug("Padding byte.\n"); write_byte(ofs, crc_value, file_offset, 0x00); } void FpgaConfig::read_ascii(std::istream &ifs) { debug("## %s\n", __PRETTY_FUNCTION__); info("Parsing ascii file..\n"); bool got_device = false; this->cram.clear(); this->bram.clear(); this->freqrange = "low"; this->warmboot = "enabled"; bool reuse_line = true; string line, command; while (reuse_line || getline(ifs, line)) { reuse_line = false; std::istringstream is(line); is >> command; if (command.empty()) continue; debug("Next command: %s\n", line.c_str()); if (command == ".comment") { this->initblop.clear(); this->initblop.push_back(0xff); this->initblop.push_back(0x00); while (getline(ifs, line)) { if (line.substr(0, 1) == ".") { reuse_line = true; break; } for (auto ch : line) this->initblop.push_back(ch); this->initblop.push_back(0); } this->initblop.push_back(0x00); this->initblop.push_back(0xff); continue; } if (command == ".device") { if (got_device) error("More than one .device statement.\n"); is >> this->device; if (this->device == "1k") { this->cram_width = 332; this->cram_height = 144; this->bram_width = 64; this->bram_height = 2 * 128; } else if (this->device == "8k") { this->cram_width = 872; this->cram_height = 272; this->bram_width = 128; this->bram_height = 2 * 128; } else error("Unsupported chip type '%s'.\n", this->device.c_str()); this->cram.resize(4); for (int i = 0; i < 4; i++) { this->cram[i].resize(this->cram_width); for (int x = 0; x < this->cram_width; x++) this->cram[i][x].resize(this->cram_height); } this->bram.resize(4); for (int i = 0; i < 4; i++) { this->bram[i].resize(this->bram_width); for (int x = 0; x < this->bram_width; x++) this->bram[i][x].resize(this->bram_height); } got_device = true; continue; } if (command == ".io_tile" || command == ".logic_tile" || command == ".ramb_tile" || command == ".ramt_tile") { if (!got_device) error("Missing .device statement before %s.\n", command.c_str()); int tile_x, tile_y; is >> tile_x >> tile_y; CramIndexConverter cic(this, tile_x, tile_y); if (("." + cic.tile_type + "_tile") != command) error("Got %s statement for %s tile %d %d.\n", command.c_str(), cic.tile_type.c_str(), tile_x, tile_y); for (int bit_y = 0; bit_y < 16 && getline(ifs, line); bit_y++) { if (line.substr(0, 1) == ".") { reuse_line = true; break; } for (int bit_x = 0; bit_x < int(line.size()) && bit_x < cic.tile_width; bit_x++) if (line[bit_x] == '1') { int cram_bank, cram_x, cram_y; cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y); this->cram[cram_bank][cram_x][cram_y] = true; } } continue; } if (command == ".ram_data") { if (!got_device) error("Missing .device statement before %s.\n", command.c_str()); int tile_x, tile_y; is >> tile_x >> tile_y; BramIndexConverter bic(this, tile_x, tile_y); for (int bit_y = 0; bit_y < 16 && getline(ifs, line); bit_y++) { if (line.substr(0, 1) == ".") { reuse_line = true; break; } for (int bit_x = 256-4, ch_idx = 0; ch_idx < int(line.size()) && bit_x >= 0; bit_x -= 4, ch_idx++) { int value = -1; if ('0' <= line[ch_idx] && line[ch_idx] <= '9') value = line[ch_idx] - '0'; if ('a' <= line[ch_idx] && line[ch_idx] <= 'f') value = line[ch_idx] - 'a' + 10; if ('A' <= line[ch_idx] && line[ch_idx] <= 'F') value = line[ch_idx] - 'A' + 10; if (value < 0) error("Not a hex character: '%c' (in line '%s')\n", line[ch_idx], line.c_str()); for (int i = 0; i < 4; i++) if ((value & (1 << i)) != 0) { int bram_bank, bram_x, bram_y; bic.get_bram_index(bit_x+i, bit_y, bram_bank, bram_x, bram_y); this->bram[bram_bank][bram_x][bram_y] = true; } } } continue; } if (command == ".extra_bit") { if (!got_device) error("Missing .device statement before %s.\n", command.c_str()); int cram_bank, cram_x, cram_y; is >> cram_bank >> cram_x >> cram_y; this->cram[cram_bank][cram_x][cram_y] = true; continue; } if (command == ".sym") continue; if (command.substr(0, 1) == ".") error("Unknown statement: %s\n", command.c_str()); error("Unexpected data line: %s\n", line.c_str()); } } void FpgaConfig::write_ascii(std::ostream &ofs) const { debug("## %s\n", __PRETTY_FUNCTION__); info("Writing ascii file..\n"); ofs << ".comment"; bool insert_newline = true; for (auto ch : this->initblop) { if (ch == 0) { insert_newline = true; } else if (ch == 0xff) { insert_newline = false; } else { if (insert_newline) ofs << '\n'; ofs << ch; insert_newline = false; } } ofs << stringf("\n.device %s\n", this->device.c_str()); typedef std::tuple tile_bit_t; std::set tile_bits; for (int y = 0; y <= this->chip_height()+1; y++) for (int x = 0; x <= this->chip_width()+1; x++) { CramIndexConverter cic(this, x, y); if (cic.tile_type == "corner") continue; ofs << stringf(".%s_tile %d %d\n", cic.tile_type.c_str(), x, y); for (int bit_y = 0; bit_y < 16; bit_y++) { for (int bit_x = 0; bit_x < cic.tile_width; bit_x++) { int cram_bank, cram_x, cram_y; cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y); tile_bits.insert(tile_bit_t(cram_bank, cram_x, cram_y)); ofs << (this->cram[cram_bank][cram_x][cram_y] ? '1' : '0'); } ofs << '\n'; } if (cic.tile_type == "ramb") { BramIndexConverter bic(this, x, y); ofs << stringf(".ram_data %d %d\n", x, y); for (int bit_y = 0; bit_y < 16; bit_y++) { for (int bit_x = 256-4; bit_x >= 0; bit_x -= 4) { int value = 0; for (int i = 0; i < 4; i++) { int bram_bank, bram_x, bram_y; bic.get_bram_index(bit_x+i, bit_y, bram_bank, bram_x, bram_y); if (this->bram[bram_bank][bram_x][bram_y]) value += 1 << i; } ofs << "0123456789abcdef"[value]; } ofs << '\n'; } } } for (int i = 0; i < 4; i++) for (int x = 0; x < this->cram_width; x++) for (int y = 0; y < this->cram_height; y++) if (this->cram[i][x][y] && tile_bits.count(tile_bit_t(i, x, y)) == 0) ofs << stringf(".extra_bit %d %d %d\n", i, x, y); #if 0 for (int i = 0; i < 4; i++) { ofs << stringf(".bram_bank %d\n", i); for (int x = 0; x < this->bram_width; x++) { for (int y = 0; y < this->bram_height; y += 4) ofs << "0123456789abcdef"[(this->bram[i][x][y] ? 1 : 0) + (this->bram[i][x][y+1] ? 2 : 0) + (this->bram[i][x][y+2] ? 4 : 0) + (this->bram[i][x][y+3] ? 8 : 0)]; ofs << '\n'; } } #endif } void FpgaConfig::write_cram_pbm(std::ostream &ofs, int bank_num) const { debug("## %s\n", __PRETTY_FUNCTION__); info("Writing cram pbm file..\n"); ofs << "P1\n"; ofs << stringf("%d %d\n", 2*this->cram_width, 2*this->cram_height); for (int y = 2*this->cram_height-1; y >= 0; y--) { for (int x = 0; x < 2*this->cram_width; x++) { int bank = 0, bank_x = x, bank_y = y; if (bank_x >= this->cram_width) bank |= 1, bank_x = 2*this->cram_width - bank_x - 1; if (bank_y >= this->cram_height) bank |= 2, bank_y = 2*this->cram_height - bank_y - 1; if (bank_num >= 0 && bank != bank_num) ofs << " 0"; else ofs << (this->cram[bank][bank_x][bank_y] ? " 1" : " 0"); } ofs << '\n'; } } void FpgaConfig::write_bram_pbm(std::ostream &ofs, int bank_num) const { debug("## %s\n", __PRETTY_FUNCTION__); info("Writing bram pbm file..\n"); ofs << "P1\n"; ofs << stringf("%d %d\n", 2*this->bram_width, 2*this->bram_height); for (int y = 2*this->bram_height-1; y >= 0; y--) { for (int x = 0; x < 2*this->bram_width; x++) { int bank = 0, bank_x = x, bank_y = y; if (bank_x >= this->bram_width) bank |= 1, bank_x = 2*this->bram_width - bank_x - 1; if (bank_y >= this->bram_height) bank |= 2, bank_y = 2*this->bram_height - bank_y - 1; if (bank_num >= 0 && bank != bank_num) ofs << " 0"; else ofs << (this->bram[bank][bank_x][bank_y] ? " 1" : " 0"); } ofs << '\n'; } } int FpgaConfig::chip_width() const { if (this->device == "1k") return 12; if (this->device == "8k") return 32; panic("Unknown chip type '%s'.\n", this->device.c_str()); } int FpgaConfig::chip_height() const { if (this->device == "1k") return 16; if (this->device == "8k") return 32; panic("Unknown chip type '%s'.\n", this->device.c_str()); } vector FpgaConfig::chip_cols() const { if (this->device == "1k") return vector({18, 54, 54, 42, 54, 54, 54}); if (this->device == "8k") return vector({18, 54, 54, 54, 54, 54, 54, 54, 42, 54, 54, 54, 54, 54, 54, 54, 54}); panic("Unknown chip type '%s'.\n", this->device.c_str()); } string FpgaConfig::tile_type(int x, int y) const { if ((x == 0 || x == this->chip_width()+1) && (y == 0 || y == this->chip_height()+1)) return "corner"; if ((x == 0 || x == this->chip_width()+1) || (y == 0 || y == this->chip_height()+1)) return "io"; if (this->device == "1k") { if (x == 3 || x == 10) return y % 2 == 1 ? "ramb" : "ramt"; return "logic"; } if (this->device == "8k") { if (x == 8 || x == 25) return y % 2 == 1 ? "ramb" : "ramt"; return "logic"; } panic("Unknown chip type '%s'.\n", this->device.c_str()); } int FpgaConfig::tile_width(const string &type) const { if (type == "corner") return 0; if (type == "logic") return 54; if (type == "ramb") return 42; if (type == "ramt") return 42; if (type == "io") return 18; panic("Unknown tile type '%s'.\n", type.c_str()); } void FpgaConfig::cram_clear() { for (int i = 0; i < 4; i++) for (int x = 0; x < this->cram_width; x++) for (int y = 0; y < this->cram_height; y++) this->cram[i][x][y] = false; } void FpgaConfig::cram_fill_tiles() { for (int y = 0; y <= this->chip_height()+1; y++) for (int x = 0; x <= this->chip_width()+1; x++) { CramIndexConverter cic(this, x, y); for (int bit_y = 0; bit_y < 16; bit_y++) for (int bit_x = 0; bit_x < cic.tile_width; bit_x++) { int cram_bank, cram_x, cram_y; cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y); this->cram[cram_bank][cram_x][cram_y] = true; } } } void FpgaConfig::cram_checkerboard(int m) { for (int y = 0; y <= this->chip_height()+1; y++) for (int x = 0; x <= this->chip_width()+1; x++) { if ((x+y) % 2 == m) continue; CramIndexConverter cic(this, x, y); for (int bit_y = 0; bit_y < 16; bit_y++) for (int bit_x = 0; bit_x < cic.tile_width; bit_x++) { int cram_bank, cram_x, cram_y; cic.get_cram_index(bit_x, bit_y, cram_bank, cram_x, cram_y); this->cram[cram_bank][cram_x][cram_y] = true; } } } CramIndexConverter::CramIndexConverter(const FpgaConfig *fpga, int tile_x, int tile_y) { this->fpga = fpga; this->tile_x = tile_x; this->tile_y = tile_y; this->tile_type = fpga->tile_type(this->tile_x, this->tile_y); this->tile_width = fpga->tile_width(this->tile_type); auto chip_width = fpga->chip_width(); auto chip_height = fpga->chip_height(); auto chip_cols = fpga->chip_cols(); this->left_right_io = this->tile_x == 0 || this->tile_x == chip_width+1; this->right_half = this->tile_x > chip_width / 2; this->top_half = this->tile_y > chip_height / 2; this->bank_num = 0; if (this->top_half) this->bank_num |= 1; if (this->right_half) this->bank_num |= 2; this->bank_tx = this->right_half ? chip_width + 1 - this->tile_x : this->tile_x; this->bank_ty = this->top_half ? chip_height + 1 - this->tile_y : this->tile_y; this->bank_xoff = 0; for (int i = 0; i < this->bank_tx; i++) this->bank_xoff += chip_cols.at(i); this->bank_yoff = 16 * this->bank_ty; this->column_width = chip_cols.at(this->bank_tx); } void CramIndexConverter::get_cram_index(int bit_x, int bit_y, int &cram_bank, int &cram_x, int &cram_y) const { static const int io_top_bottom_permx[18] = {23, 25, 26, 27, 16, 17, 18, 19, 20, 14, 32, 33, 34, 35, 36, 37, 4, 5}; static const int io_top_bottom_permy[16] = {0, 1, 3, 2, 4, 5, 7, 6, 8, 9, 11, 10, 12, 13, 15, 14}; cram_bank = bank_num; if (tile_type == "io") { if (left_right_io) { cram_x = bank_xoff + column_width - 1 - bit_x; if (top_half) cram_y = bank_yoff + 15 - bit_y; else cram_y = bank_yoff + bit_y; } else { cram_y = bank_yoff + 15 - io_top_bottom_permy[bit_y]; if (right_half) cram_x = bank_xoff + column_width - 1 - io_top_bottom_permx[bit_x]; else cram_x = bank_xoff + io_top_bottom_permx[bit_x]; } } else { if (right_half) cram_x = bank_xoff + column_width - 1 - bit_x; else cram_x = bank_xoff + bit_x; if (top_half) cram_y = bank_yoff + (15 - bit_y); else cram_y = bank_yoff + bit_y; } } BramIndexConverter::BramIndexConverter(const FpgaConfig *fpga, int tile_x, int tile_y) { this->fpga = fpga; this->tile_x = tile_x; this->tile_y = tile_y; auto chip_width = fpga->chip_width(); auto chip_height = fpga->chip_height(); bool right_half = this->tile_x > chip_width / 2; bool top_half = this->tile_y > chip_height / 2; this->bank_num = 0; if (top_half) this->bank_num |= 1; if (right_half) this->bank_num |= 2; this->bank_off = 16 * ((top_half ? this->tile_y - chip_height / 2 : this->tile_y - 1) / 2); } void BramIndexConverter::get_bram_index(int bit_x, int bit_y, int &bram_bank, int &bram_x, int &bram_y) const { int index = 256 * bit_y + (16*(bit_x/16) + 15 - bit_x%16); bram_bank = bank_num; bram_x = bank_off + index % 16; bram_y = index / 16; } // ================================================================== // Main program void usage() { log("\n"); log("Usage: icepack [options] [input-file [output-file]]\n"); log("\n"); log(" -u\n"); log(" unpack mode (implied when called as 'iceunpack')\n"); log("\n"); log(" -v\n"); log(" verbose (repeat to increase verbosity)\n"); log("\n"); log(" -b\n"); log(" write cram bitmap as netpbm file\n"); log("\n"); log(" -f\n"); log(" write cram bitmap (fill tiles) as netpbm file\n"); log("\n"); log(" -c\n"); log(" write cram bitmap (checkerboard) as netpbm file\n"); log(" repeat to flip the selection of tiles\n"); log("\n"); log(" -r\n"); log(" write bram data, not cram, to the netpbm file\n"); log("\n"); log(" -B0, -B1, -B2, -B3\n"); log(" only include the specified bank in the netpbm file\n"); log("\n"); exit(1); } int main(int argc, char **argv) { vector parameters; bool unpack_mode = false; bool netpbm_mode = false; bool netpbm_bram = false; bool netpbm_fill_tiles = false; bool netpbm_checkerboard = false; int netpbm_banknum = -1; int checkerboard_m = 1; for (int i = 0; argv[0][i]; i++) if (string(argv[0]+i) == "iceunpack") unpack_mode = true; for (int i = 1; i < argc; i++) { string arg(argv[i]); if (arg[0] == '-' && arg.size() > 1) { for (int i = 1; i < int(arg.size()); i++) if (arg[i] == 'u') { unpack_mode = true; } else if (arg[i] == 'b') { netpbm_mode = true; } else if (arg[i] == 'r') { netpbm_mode = true; netpbm_bram = true; } else if (arg[i] == 'f') { netpbm_mode = true; netpbm_fill_tiles = true; } else if (arg[i] == 'c') { netpbm_mode = true; netpbm_checkerboard = true; checkerboard_m = !checkerboard_m; } else if (arg[i] == 'B') { netpbm_mode = true; netpbm_banknum = arg[++i] - '0'; } else if (arg[i] == 'v') { log_level++; } else usage(); continue; } parameters.push_back(arg); } std::ifstream ifs; std::ofstream ofs; std::istream *isp; std::ostream *osp; if (parameters.size() >= 1 && parameters[0] != "-") { ifs.open(parameters[0], std::ios::binary); if (!ifs.is_open()) error("Failed to open input file.\n"); isp = &ifs; } else { isp = &std::cin; } if (parameters.size() >= 2 && parameters[1] != "-") { ofs.open(parameters[1], std::ios::binary); if (!ofs.is_open()) error("Failed to open output file.\n"); osp = &ofs; } else { osp = &std::cout; } if (parameters.size() > 2) usage(); FpgaConfig fpga_config; if (unpack_mode) { fpga_config.read_bits(*isp); if (!netpbm_mode) fpga_config.write_ascii(*osp); } else { fpga_config.read_ascii(*isp); if (!netpbm_mode) fpga_config.write_bits(*osp); } if (netpbm_checkerboard) { fpga_config.cram_clear(); fpga_config.cram_checkerboard(checkerboard_m); } if (netpbm_fill_tiles) fpga_config.cram_fill_tiles(); if (netpbm_mode) { if (netpbm_bram) fpga_config.write_bram_pbm(*osp, netpbm_banknum); else fpga_config.write_cram_pbm(*osp, netpbm_banknum); } info("Done.\n"); return 0; } fpga-icestorm-0~20160913git266e758/icepll/000077500000000000000000000000001276746530600176425ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icepll/.gitignore000066400000000000000000000000441276746530600216300ustar00rootroot00000000000000icepll icepll.exe icepll.o icepll.d fpga-icestorm-0~20160913git266e758/icepll/Makefile000066400000000000000000000007361276746530600213100ustar00rootroot00000000000000include ../config.mk LDLIBS = -lm -lstdc++ CXXFLAGS = -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include ifeq ($(STATIC),1) LDFLAGS += -static endif all: icepll$(EXE) icepll$(EXE): icepll.o $(CC) -o $@ $(LDFLAGS) $^ $(LDLIBS) install: all mkdir -p $(DESTDIR)$(PREFIX)/bin cp icepll $(DESTDIR)$(PREFIX)/bin/icepll uninstall: rm -f $(DESTDIR)$(PREFIX)/bin/icepll clean: rm -f icepll rm -f icepll.exe rm -f *.o *.d -include *.d .PHONY: all install uninstall clean fpga-icestorm-0~20160913git266e758/icepll/icepll.cc000066400000000000000000000105541276746530600214260ustar00rootroot00000000000000// // Copyright (C) 2015 Clifford Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. // #include #include #include #include #include const char *binstr(int v, int n) { static char buffer[16]; char *p = buffer; for (int i = n-1; i >= 0; i--) *(p++) = ((v >> i) & 1) ? '1' : '0'; *(p++) = 0; return buffer; } void help(const char *cmd) { printf("\n"); printf("Usage: %s [options]\n", cmd); printf("\n"); printf(" -i \n"); printf(" PLL Input Frequency (default: 12 MHz)\n"); printf("\n"); printf(" -o \n"); printf(" PLL Output Frequency (default: 60 MHz)\n"); printf("\n"); printf(" -S\n"); printf(" Disable SIMPLE feedback path mode\n"); printf("\n"); exit(1); } int main(int argc, char **argv) { double f_pllin = 12; double f_pllout = 60; bool simple_feedback = true; int opt; while ((opt = getopt(argc, argv, "i:o:S")) != -1) { switch (opt) { case 'i': f_pllin = atof(optarg); break; case 'o': f_pllout = atof(optarg); break; case 'S': simple_feedback = false; break; default: help(argv[0]); } } if (optind != argc) help(argv[0]); bool found_something = false; double best_fout = 0; int best_divr = 0; int best_divf = 0; int best_divq = 0; if (f_pllin < 10 || f_pllin > 133) { fprintf(stderr, "Error: PLL input frequency %.3f MHz is outside range 10 MHz - 133 MHz!\n", f_pllin); exit(1); } if (f_pllout < 16 || f_pllout > 275) { fprintf(stderr, "Error: PLL output frequency %.3f MHz is outside range 16 MHz - 275 MHz!\n", f_pllout); exit(1); } for (int divr = 0; divr <= 15; divr++) { double f_pfd = f_pllin / (divr + 1); if (f_pfd < 10 || f_pfd > 133) continue; for (int divf = 0; divf <= 127; divf++) { if (simple_feedback) { double f_vco = f_pfd * (divf + 1); if (f_vco < 533 || f_vco > 1066) continue; for (int divq = 1; divq <= 6; divq++) { double fout = f_vco * exp2(-divq); if (fabs(fout - f_pllout) < fabs(best_fout - f_pllout) || !found_something) { best_fout = fout; best_divr = divr; best_divf = divf; best_divq = divq; found_something = true; } } } else { for (int divq = 1; divq <= 6; divq++) { double f_vco = f_pfd * (divf + 1) * exp2(divq); if (f_vco < 533 || f_vco > 1066) continue; double fout = f_vco * exp2(-divq); if (fabs(fout - f_pllout) < fabs(best_fout - f_pllout) || !found_something) { best_fout = fout; best_divr = divr; best_divf = divf; best_divq = divq; found_something = true; } } } } } double f_pfd = f_pllin / (best_divr + 1);; double f_vco = f_pfd * (best_divf + 1); int filter_range = f_pfd < 17 ? 1 : f_pfd < 26 ? 2 : f_pfd < 44 ? 3 : f_pfd < 66 ? 4 : f_pfd < 101 ? 5 : 6; if (!simple_feedback) f_vco *= exp2(best_divq); if (!found_something) { fprintf(stderr, "Error: No valid configuration found!\n"); exit(1); } printf("\n"); printf("F_PLLIN: %8.3f MHz (given)\n", f_pllin); printf("F_PLLOUT: %8.3f MHz (requested)\n", f_pllout); printf("F_PLLOUT: %8.3f MHz (achieved)\n", best_fout); printf("\n"); printf("FEEDBACK: %s\n", simple_feedback ? "SIMPLE" : "NON_SIMPLE"); printf("F_PFD: %8.3f MHz\n", f_pfd); printf("F_VCO: %8.3f MHz\n", f_vco); printf("\n"); printf("DIVR: %2d (4'b%s)\n", best_divr, binstr(best_divr, 4)); printf("DIVF: %2d (7'b%s)\n", best_divf, binstr(best_divf, 7)); printf("DIVQ: %2d (3'b%s)\n", best_divq, binstr(best_divq, 3)); printf("\n"); printf("FILTER_RANGE: %d (3'b%s)\n", filter_range, binstr(filter_range, 3)); printf("\n"); return 0; } fpga-icestorm-0~20160913git266e758/iceprog/000077500000000000000000000000001276746530600200225ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/iceprog/.gitignore000066400000000000000000000000501276746530600220050ustar00rootroot00000000000000iceprog iceprog.exe iceprog.o iceprog.d fpga-icestorm-0~20160913git266e758/iceprog/Makefile000066400000000000000000000023201276746530600214570ustar00rootroot00000000000000include ../config.mk ifneq ($(shell uname -s),Darwin) LDLIBS = -L/usr/local/lib -lm CFLAGS = -MD -O0 -ggdb -Wall -std=c99 -I/usr/local/include else LIBFTDI_NAME = $(shell $(PKG_CONFIG) --exists libftdi1 && echo ftdi1 || echo ftdi) LDLIBS = -L/usr/local/lib -l$(LIBFTDI_NAME) -lm CFLAGS = -MD -O0 -ggdb -Wall -std=c99 -I/usr/local/include endif ifeq ($(STATIC),1) LDFLAGS += -static LDLIBS += $(shell for pkg in libftdi1 libftdi; do $(PKG_CONFIG) --silence-errors --static --libs $$pkg && exit; done; echo -lftdi; ) CFLAGS += $(shell for pkg in libftdi1 libftdi; do $(PKG_CONFIG) --silence-errors --static --cflags $$pkg && exit; done; ) else LDLIBS += $(shell for pkg in libftdi1 libftdi; do $(PKG_CONFIG) --silence-errors --libs $$pkg && exit; done; echo -lftdi; ) CFLAGS += $(shell for pkg in libftdi1 libftdi; do $(PKG_CONFIG) --silence-errors --cflags $$pkg && exit; done; ) endif all: iceprog$(EXE) iceprog$(EXE): iceprog.o $(CC) -o $@ $(LDFLAGS) $^ $(LDLIBS) install: all mkdir -p $(DESTDIR)$(PREFIX)/bin cp iceprog $(DESTDIR)$(PREFIX)/bin/iceprog uninstall: rm -f $(DESTDIR)$(PREFIX)/bin/iceprog clean: rm -f iceprog rm -f iceprog.exe rm -f *.o *.d -include *.d .PHONY: all install uninstall clean fpga-icestorm-0~20160913git266e758/iceprog/iceprog.c000066400000000000000000000412011276746530600216140ustar00rootroot00000000000000/* * iceprog -- simple programming tool for FTDI-based Lattice iCE programmers * * Copyright (C) 2015 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * Relevant Documents: * ------------------- * http://www.latticesemi.com/~/media/Documents/UserManuals/EI/icestickusermanual.pdf * http://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf * http://www.ftdichip.com/Support/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf */ #define _GNU_SOURCE #include #include #include #include #include #include #include #include #include #include struct ftdi_context ftdic; bool ftdic_open = false; bool verbose = false; void check_rx() { while (1) { uint8_t data; int rc = ftdi_read_data(&ftdic, &data, 1); if (rc <= 0) break; fprintf(stderr, "unexpected rx byte: %02X\n", data); } } void error() { check_rx(); fprintf(stderr, "ABORT.\n"); if (ftdic_open) ftdi_usb_close(&ftdic); ftdi_deinit(&ftdic); exit(1); } uint8_t recv_byte() { uint8_t data; while (1) { int rc = ftdi_read_data(&ftdic, &data, 1); if (rc < 0) { fprintf(stderr, "Read error.\n"); error(); } if (rc == 1) break; usleep(100); } return data; } void send_byte(uint8_t data) { int rc = ftdi_write_data(&ftdic, &data, 1); if (rc != 1) { fprintf(stderr, "Write error (single byte, rc=%d, expected %d).\n", rc, 1); error(); } } void send_spi(uint8_t *data, int n) { if (n < 1) return; send_byte(0x11); send_byte(n-1); send_byte((n-1) >> 8); int rc = ftdi_write_data(&ftdic, data, n); if (rc != n) { fprintf(stderr, "Write error (chunk, rc=%d, expected %d).\n", rc, n); error(); } } void xfer_spi(uint8_t *data, int n) { if (n < 1) return; send_byte(0x31); send_byte(n-1); send_byte((n-1) >> 8); int rc = ftdi_write_data(&ftdic, data, n); if (rc != n) { fprintf(stderr, "Write error (chunk, rc=%d, expected %d).\n", rc, n); error(); } for (int i = 0; i < n; i++) data[i] = recv_byte(); } void set_gpio(int slavesel_b, int creset_b) { uint8_t gpio = 1; if (slavesel_b) { // ADBUS4 (GPIOL0) gpio |= 0x10; } if (creset_b) { // ADBUS7 (GPIOL3) gpio |= 0x80; } send_byte(0x80); send_byte(gpio); send_byte(0x93); } int get_cdone() { uint8_t data; send_byte(0x81); data = recv_byte(); // ADBUS6 (GPIOL2) return (data & 0x40) != 0; } void flash_read_id() { // fprintf(stderr, "read flash ID..\n"); uint8_t data[21] = { 0x9F }; set_gpio(0, 0); xfer_spi(data, 21); set_gpio(1, 0); fprintf(stderr, "flash ID:"); for (int i = 1; i < 21; i++) fprintf(stderr, " 0x%02X", data[i]); fprintf(stderr, "\n"); } void flash_power_up() { uint8_t data[1] = { 0xAB }; set_gpio(0, 0); xfer_spi(data, 1); set_gpio(1, 0); } void flash_power_down() { uint8_t data[1] = { 0xB9 }; set_gpio(0, 0); xfer_spi(data, 1); set_gpio(1, 0); } void flash_write_enable() { if (verbose) fprintf(stderr, "write enable..\n"); uint8_t data[1] = { 0x06 }; set_gpio(0, 0); xfer_spi(data, 1); set_gpio(1, 0); } void flash_bulk_erase() { fprintf(stderr, "bulk erase..\n"); uint8_t data[1] = { 0xc7 }; set_gpio(0, 0); xfer_spi(data, 1); set_gpio(1, 0); } void flash_64kB_sector_erase(int addr) { fprintf(stderr, "erase 64kB sector at 0x%06X..\n", addr); uint8_t command[4] = { 0xd8, (uint8_t)(addr >> 16), (uint8_t)(addr >> 8), (uint8_t)addr }; set_gpio(0, 0); send_spi(command, 4); set_gpio(1, 0); } void flash_prog(int addr, uint8_t *data, int n) { if (verbose) fprintf(stderr, "prog 0x%06X +0x%03X..\n", addr, n); uint8_t command[4] = { 0x02, (uint8_t)(addr >> 16), (uint8_t)(addr >> 8), (uint8_t)addr }; set_gpio(0, 0); send_spi(command, 4); send_spi(data, n); set_gpio(1, 0); if (verbose) for (int i = 0; i < n; i++) fprintf(stderr, "%02x%c", data[i], i == n-1 || i % 32 == 31 ? '\n' : ' '); } void flash_read(int addr, uint8_t *data, int n) { if (verbose) fprintf(stderr, "read 0x%06X +0x%03X..\n", addr, n); uint8_t command[4] = { 0x03, (uint8_t)(addr >> 16), (uint8_t)(addr >> 8), (uint8_t)addr }; set_gpio(0, 0); send_spi(command, 4); memset(data, 0, n); xfer_spi(data, n); set_gpio(1, 0); if (verbose) for (int i = 0; i < n; i++) fprintf(stderr, "%02x%c", data[i], i == n-1 || i % 32 == 31 ? '\n' : ' '); } void flash_wait() { if (verbose) fprintf(stderr, "waiting.."); while (1) { uint8_t data[2] = { 0x05 }; set_gpio(0, 0); xfer_spi(data, 2); set_gpio(1, 0); if ((data[1] & 0x01) == 0) break; if (verbose) { fprintf(stderr, "."); fflush(stdout); } usleep(1000); } if (verbose) fprintf(stderr, "\n"); } void help(const char *progname) { fprintf(stderr, "\n"); fprintf(stderr, "iceprog -- simple programming tool for FTDI-based Lattice iCE programmers\n"); fprintf(stderr, "\n"); fprintf(stderr, "\n"); fprintf(stderr, "Notes for iCEstick (iCE40HX-1k devel board):\n"); fprintf(stderr, " An unmodified iCEstick can only be programmed via the serial flash.\n"); fprintf(stderr, " Direct programming of the SRAM is not supported. For direct SRAM\n"); fprintf(stderr, " programming the flash chip and one zero ohm resistor must be desoldered\n"); fprintf(stderr, " and the FT2232H SI pin must be connected to the iCE SPI_SI pin, as shown\n"); fprintf(stderr, " in this picture: http://www.clifford.at/gallery/2014-elektronik/IMG_20141115_183838\n"); fprintf(stderr, "\n"); fprintf(stderr, "\n"); fprintf(stderr, "Notes for the iCE40-HX8K Breakout Board:\n"); fprintf(stderr, " Make sure that the jumper settings on the board match the selected\n"); fprintf(stderr, " mode (SRAM or FLASH). See the iCE40-HX8K user manual for details.\n"); fprintf(stderr, "\n"); fprintf(stderr, "\n"); fprintf(stderr, "Usage: %s [options] \n", progname); fprintf(stderr, "\n"); fprintf(stderr, " -d \n"); fprintf(stderr, " use the specified USB device:\n"); fprintf(stderr, "\n"); fprintf(stderr, " d: (e.g. d:002/005)\n"); fprintf(stderr, " i:: (e.g. i:0x0403:0x6010)\n"); fprintf(stderr, " i::: (e.g. i:0x0403:0x6010:0)\n"); fprintf(stderr, " s:::\n"); fprintf(stderr, "\n"); fprintf(stderr, " -I [ABCD]\n"); fprintf(stderr, " connect to the specified interface on the FTDI chip\n"); fprintf(stderr, "\n"); fprintf(stderr, " -r\n"); fprintf(stderr, " read first 256 kB from flash and write to file\n"); fprintf(stderr, "\n"); fprintf(stderr, " -R \n"); fprintf(stderr, " read the specified number of bytes from flash\n"); fprintf(stderr, " (append 'k' to the argument for size in kilobytes, or\n"); fprintf(stderr, " 'M' for size in megabytes)\n"); fprintf(stderr, "\n"); fprintf(stderr, " -o \n"); fprintf(stderr, " start address for read/write (instead of zero)\n"); fprintf(stderr, " (append 'k' to the argument for size in kilobytes, or\n"); fprintf(stderr, " 'M' for size in megabytes)\n"); fprintf(stderr, "\n"); fprintf(stderr, " -c\n"); fprintf(stderr, " do not write flash, only verify (check)\n"); fprintf(stderr, "\n"); fprintf(stderr, " -b\n"); fprintf(stderr, " bulk erase entire flash before writing\n"); fprintf(stderr, "\n"); fprintf(stderr, " -n\n"); fprintf(stderr, " do not erase flash before writing\n"); fprintf(stderr, "\n"); fprintf(stderr, " -S\n"); fprintf(stderr, " perform SRAM programming\n"); fprintf(stderr, "\n"); fprintf(stderr, " -t\n"); fprintf(stderr, " just read the flash ID sequence\n"); fprintf(stderr, "\n"); fprintf(stderr, " -v\n"); fprintf(stderr, " verbose output\n"); fprintf(stderr, "\n"); fprintf(stderr, "Without -b or -n, iceprog will erase aligned chunks of 64kB in write mode.\n"); fprintf(stderr, "This means that some data after the written data (or even before when -o is\n"); fprintf(stderr, "used) may be erased as well.\n"); fprintf(stderr, "\n"); exit(1); } int main(int argc, char **argv) { int read_size = 256 * 1024; int rw_offset = 0; bool read_mode = false; bool check_mode = false; bool bulk_erase = false; bool dont_erase = false; bool prog_sram = false; bool test_mode = false; const char *filename = NULL; const char *devstr = NULL; enum ftdi_interface ifnum = INTERFACE_A; int opt; char *endptr; while ((opt = getopt(argc, argv, "d:I:rR:o:cbnStv")) != -1) { switch (opt) { case 'd': devstr = optarg; break; case 'I': if (!strcmp(optarg, "A")) ifnum = INTERFACE_A; else if (!strcmp(optarg, "B")) ifnum = INTERFACE_B; else if (!strcmp(optarg, "C")) ifnum = INTERFACE_C; else if (!strcmp(optarg, "D")) ifnum = INTERFACE_D; else help(argv[0]); break; case 'r': read_mode = true; break; case 'R': read_mode = true; read_size = strtol(optarg, &endptr, 0); if (!strcmp(endptr, "k")) read_size *= 1024; if (!strcmp(endptr, "M")) read_size *= 1024 * 1024; break; case 'o': rw_offset = strtol(optarg, &endptr, 0); if (!strcmp(endptr, "k")) rw_offset *= 1024; if (!strcmp(endptr, "M")) rw_offset *= 1024 * 1024; break; case 'c': check_mode = true; break; case 'b': bulk_erase = true; break; case 'n': dont_erase = true; break; case 'S': prog_sram = true; break; case 't': test_mode = true; break; case 'v': verbose = true; break; default: help(argv[0]); } } if (read_mode + check_mode + prog_sram + test_mode > 1) help(argv[0]); if (bulk_erase && dont_erase) help(argv[0]); if (optind+1 != argc && !test_mode) { if (bulk_erase && optind == argc) filename = "/dev/null"; else help(argv[0]); } else filename = argv[optind]; // --------------------------------------------------------- // Initialize USB connection to FT2232H // --------------------------------------------------------- fprintf(stderr, "init..\n"); ftdi_init(&ftdic); ftdi_set_interface(&ftdic, ifnum); if (devstr != NULL) { if (ftdi_usb_open_string(&ftdic, devstr)) { fprintf(stderr, "Can't find iCE FTDI USB device (device string %s).\n", devstr); error(); } } else { if (ftdi_usb_open(&ftdic, 0x0403, 0x6010)) { fprintf(stderr, "Can't find iCE FTDI USB device (vedor_id 0x0403, device_id 0x6010).\n"); error(); } } ftdic_open = true; if (ftdi_usb_reset(&ftdic)) { fprintf(stderr, "Failed to reset iCE FTDI USB device.\n"); error(); } if (ftdi_usb_purge_buffers(&ftdic)) { fprintf(stderr, "Failed to purge buffers on iCE FTDI USB device.\n"); error(); } if (ftdi_set_bitmode(&ftdic, 0xff, BITMODE_MPSSE) < 0) { fprintf(stderr, "Failed set BITMODE_MPSSE on iCE FTDI USB device.\n"); error(); } // enable clock divide by 5 send_byte(0x8b); // set 6 MHz clock send_byte(0x86); send_byte(0x00); send_byte(0x00); fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low"); set_gpio(1, 1); usleep(100000); if (test_mode) { fprintf(stderr, "reset..\n"); set_gpio(1, 0); usleep(250000); fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low"); flash_power_up(); flash_read_id(); flash_power_down(); set_gpio(1, 1); usleep(250000); fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low"); } else if (prog_sram) { // --------------------------------------------------------- // Reset // --------------------------------------------------------- fprintf(stderr, "reset..\n"); set_gpio(0, 0); usleep(100); set_gpio(0, 1); usleep(2000); fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low"); // --------------------------------------------------------- // Program // --------------------------------------------------------- FILE *f = (strcmp(filename, "-") == 0) ? stdin : fopen(filename, "rb"); if (f == NULL) { fprintf(stderr, "Error: Can't open '%s' for reading: %s\n", filename, strerror(errno)); error(); } fprintf(stderr, "programming..\n"); while (1) { static unsigned char buffer[4096]; int rc = fread(buffer, 1, 4096, f); if (rc <= 0) break; if (verbose) fprintf(stderr, "sending %d bytes.\n", rc); send_spi(buffer, rc); } if (f != stdin) fclose(f); // add 48 dummy bits send_byte(0x8f); send_byte(0x05); send_byte(0x00); // add 1 more dummy bit send_byte(0x8e); send_byte(0x00); fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low"); } else { // --------------------------------------------------------- // Reset // --------------------------------------------------------- fprintf(stderr, "reset..\n"); set_gpio(1, 0); usleep(250000); fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low"); flash_power_up(); flash_read_id(); // --------------------------------------------------------- // Program // --------------------------------------------------------- if (!read_mode && !check_mode) { FILE *f = (strcmp(filename, "-") == 0) ? stdin : fopen(filename, "rb"); if (f == NULL) { fprintf(stderr, "Error: Can't open '%s' for reading: %s\n", filename, strerror(errno)); error(); } if (!dont_erase) { if (bulk_erase) { flash_write_enable(); flash_bulk_erase(); flash_wait(); } else { struct stat st_buf; if (stat(filename, &st_buf)) { fprintf(stderr, "Error: Can't stat '%s': %s\n", filename, strerror(errno)); error(); } fprintf(stderr, "file size: %d\n", (int)st_buf.st_size); int begin_addr = rw_offset & ~0xffff; int end_addr = (rw_offset + (int)st_buf.st_size + 0xffff) & ~0xffff; for (int addr = begin_addr; addr < end_addr; addr += 0x10000) { flash_write_enable(); flash_64kB_sector_erase(addr); flash_wait(); } } } fprintf(stderr, "programming..\n"); for (int rc, addr = 0; true; addr += rc) { uint8_t buffer[256]; int page_size = 256 - (rw_offset + addr) % 256; rc = fread(buffer, 1, page_size, f); if (rc <= 0) break; flash_write_enable(); flash_prog(rw_offset + addr, buffer, rc); flash_wait(); } if (f != stdin) fclose(f); } // --------------------------------------------------------- // Read/Verify // --------------------------------------------------------- if (read_mode) { FILE *f = (strcmp(filename, "-") == 0) ? stdout : fopen(filename, "wb"); if (f == NULL) { fprintf(stderr, "Error: Can't open '%s' for writing: %s\n", filename, strerror(errno)); error(); } fprintf(stderr, "reading..\n"); for (int addr = 0; addr < read_size; addr += 256) { uint8_t buffer[256]; flash_read(rw_offset + addr, buffer, 256); fwrite(buffer, 256, 1, f); } if (f != stdout) fclose(f); } else { FILE *f = (strcmp(filename, "-") == 0) ? stdin : fopen(filename, "rb"); if (f == NULL) { fprintf(stderr, "Error: Can't open '%s' for reading: %s\n", filename, strerror(errno)); error(); } fprintf(stderr, "reading..\n"); for (int addr = 0; true; addr += 256) { uint8_t buffer_flash[256], buffer_file[256]; int rc = fread(buffer_file, 1, 256, f); if (rc <= 0) break; flash_read(rw_offset + addr, buffer_flash, rc); if (memcmp(buffer_file, buffer_flash, rc)) { fprintf(stderr, "Found difference between flash and file!\n"); error(); } } fprintf(stderr, "VERIFY OK\n"); if (f != stdin) fclose(f); } // --------------------------------------------------------- // Reset // --------------------------------------------------------- flash_power_down(); set_gpio(1, 1); usleep(250000); fprintf(stderr, "cdone: %s\n", get_cdone() ? "high" : "low"); } // --------------------------------------------------------- // Exit // --------------------------------------------------------- fprintf(stderr, "Bye.\n"); ftdi_disable_bitbang(&ftdic); ftdi_usb_close(&ftdic); ftdi_deinit(&ftdic); return 0; } fpga-icestorm-0~20160913git266e758/icetime/000077500000000000000000000000001276746530600200115ustar00rootroot00000000000000fpga-icestorm-0~20160913git266e758/icetime/.gitignore000066400000000000000000000000631276746530600220000ustar00rootroot00000000000000icetime icetime.exe timings.inc test[0-9]* *.d *.o fpga-icestorm-0~20160913git266e758/icetime/Makefile000066400000000000000000000026351276746530600214570ustar00rootroot00000000000000include ../config.mk LDLIBS = -lm -lstdc++ CXXFLAGS = -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include -DPREFIX='"$(PREFIX)"' ifeq ($(STATIC),1) LDFLAGS += -static endif all: icetime$(EXE) icetime$(EXE): icetime.o $(CC) -o $@ $(LDFLAGS) $^ $(LDLIBS) icetime.o: icetime.cc timings.inc timings.inc: timings.py ../icefuzz/timings_*.txt python3 timings.py > timings.inc.new mv timings.inc.new timings.inc install: all mkdir -p $(DESTDIR)$(PREFIX)/bin cp icetime $(DESTDIR)$(PREFIX)/bin/icetime uninstall: rm -f $(DESTDIR)$(PREFIX)/bin/icetime # View timing netlist: # yosys -qp 'read_verilog -lib cells.v; prep; show' test0_ref.v # yosys -qp 'read_verilog -lib cells.v; prep; show' test0_out.v test0 test1 test2 test3 test4 test5 test6 test7 test8 test9: icetime test -f $@_ref.v || python3 mktest.py $@ ./icetime -m -d hx1k -P tq144 -p $@.pcf -o $@_out.v $@.asc yosys $@.ys run0 run1 run2 run3 run4 run5 run6 run7 run8 run9: icetime ./icetime -t -d hx1k -P tq144 -p $(subst run,test,$@).pcf $(subst run,test,$@).asc show0 show1 show2 show3 show4 show5 show6 show7 show8 show9: icetime bash show.sh $(subst show,test,$@) xdot $(subst show,test,$@).dot test: test0 test1 test2 test3 test4 test5 test6 test7 test8 test9 show: show0 show1 show2 show3 show4 show5 show6 show7 show8 show9 clean: rm -f icetime icetime.exe timings.inc *.o *.d rm -rf test[0-9]* -include *.d .PHONY: all install uninstall clean fpga-icestorm-0~20160913git266e758/icetime/cells.v000066400000000000000000000330471276746530600213110ustar00rootroot00000000000000module AND2(A, B, O); input A; input B; output O; endmodule module CEMux(I, O); input I; output O; endmodule module CascadeBuf(I, O); input I; output O; endmodule module CascadeMux(I, O); input I; output O; endmodule module ClkMux(I, O); input I; output O; endmodule module ColCtrlBuf(I, O); input I; output O; endmodule module DummyBuf(I, O); input I; output O; endmodule module Glb2LocalMux(I, O); input I; output O; endmodule module GlobalMux(I, O); input I; output O; endmodule module ICE_CARRY_IN_MUX(carryinitout, carryinitin); input carryinitin; output carryinitout; endmodule module ICE_GB(GLOBALBUFFEROUTPUT, USERSIGNALTOGLOBALBUFFER); output GLOBALBUFFEROUTPUT; input USERSIGNALTOGLOBALBUFFER; endmodule module ICE_GB_IO(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0, GLOBALBUFFEROUTPUT); input CLOCKENABLE; output DIN0; output DIN1; input DOUT0; input DOUT1; output GLOBALBUFFEROUTPUT; input INPUTCLK; input LATCHINPUTVALUE; input OUTPUTCLK; input OUTPUTENABLE; inout PACKAGEPIN; endmodule module ICE_IO(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); input CLOCKENABLE; output DIN0; output DIN1; input DOUT0; input DOUT1; input INPUTCLK; input LATCHINPUTVALUE; input OUTPUTCLK; input OUTPUTENABLE; inout PACKAGEPIN; endmodule module ICE_IO_DLY(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0, SCLK, SDI, CRSEL, SDO); input CLOCKENABLE; input CRSEL; output DIN0; output DIN1; input DOUT0; input DOUT1; input INPUTCLK; input LATCHINPUTVALUE; input OUTPUTCLK; input OUTPUTENABLE; inout PACKAGEPIN; input SCLK; input SDI; output SDO; endmodule module ICE_IO_DS(PACKAGEPIN, PACKAGEPINB, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); input CLOCKENABLE; output DIN0; output DIN1; input DOUT0; input DOUT1; input INPUTCLK; input LATCHINPUTVALUE; input OUTPUTCLK; input OUTPUTENABLE; inout PACKAGEPIN; inout PACKAGEPINB; endmodule module ICE_IO_OD(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); input CLOCKENABLE; output DIN0; output DIN1; input DOUT0; input DOUT1; input INPUTCLK; input LATCHINPUTVALUE; input OUTPUTCLK; input OUTPUTENABLE; inout PACKAGEPIN; endmodule module ICE_IR500_DRV(IRLEDEN, IRPWM, CURREN, IRLEDEN2, IRPWM2, IRLED1, IRLED2); input CURREN; output IRLED1; output IRLED2; input IRLEDEN; input IRLEDEN2; input IRPWM; input IRPWM2; endmodule module INV(I, O); input I; output O; endmodule module IO_PAD(PACKAGEPIN, DOUT, DIN, OE); input DIN; output DOUT; input OE; inout PACKAGEPIN; endmodule module InMux(I, O); input I; output O; endmodule module IoInMux(I, O); input I; output O; endmodule module IoSpan4Mux(I, O); input I; output O; endmodule module IpInMux(I, O); input I; output O; endmodule module IpOutMux(I, O); input I; output O; endmodule module LocalMux(I, O); input I; output O; endmodule module LogicCell(carryout, lcout, carryin, clk, clkb, in0, in1, in2, in3, sr); input carryin; output carryout; input clk; input clkb; input in0; input in1; input in2; input in3; output lcout; input sr; endmodule module LogicCell2(carryout, lcout, carryin, clk, in0, in1, in2, in3, sr, ce); input carryin; output carryout; input ce; input clk; input in0; input in1; input in2; input in3; output lcout; input sr; endmodule module LogicCell40(carryout, lcout, ltout, carryin, clk, in0, in1, in2, in3, sr, ce); input carryin; output carryout; input ce; input clk; input in0; input in1; input in2; input in3; output lcout; output ltout; input sr; endmodule module Odrv12(I, O); input I; output O; endmodule module Odrv4(I, O); input I; output O; endmodule module PAD_BANK0(PAD, PADIN, PADOUT, PADOEN); inout PAD; output PADIN; input PADOEN; input PADOUT; endmodule module PAD_BANK1(PAD, PADIN, PADOUT, PADOEN); inout PAD; output PADIN; input PADOEN; input PADOUT; endmodule module PAD_BANK2(PAD, PADIN, PADOUT, PADOEN); inout PAD; output PADIN; input PADOEN; input PADOUT; endmodule module PAD_BANK3(PAD, PADIN, PADOUT, PADOEN); inout PAD; output PADIN; input PADOEN; input PADOUT; endmodule module PLL40(PLLIN, PLLOUTCORE, PLLOUTGLOBAL, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE); input BYPASS; input [7:0] DYNAMICDELAY; input EXTFEEDBACK; input LATCHINPUTVALUE; output LOCK; input PLLIN; output PLLOUTCORE; output PLLOUTGLOBAL; input RESETB; input SCLK; input SDI; output SDO; endmodule module PLL40_2(PLLIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE); input BYPASS; input [7:0] DYNAMICDELAY; input EXTFEEDBACK; input LATCHINPUTVALUE; output LOCK; input PLLIN; output PLLOUTCOREA; output PLLOUTCOREB; output PLLOUTGLOBALA; output PLLOUTGLOBALB; input RESETB; input SCLK; input SDI; output SDO; endmodule module PLL40_2F(PLLIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE); input BYPASS; input [7:0] DYNAMICDELAY; input EXTFEEDBACK; input LATCHINPUTVALUE; output LOCK; input PLLIN; output PLLOUTCOREA; output PLLOUTCOREB; output PLLOUTGLOBALA; output PLLOUTGLOBALB; input RESETB; input SCLK; input SDI; output SDO; endmodule module PREIO(PADIN, PADOUT, PADOEN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); input CLOCKENABLE; output DIN0; output DIN1; input DOUT0; input DOUT1; input INPUTCLK; input LATCHINPUTVALUE; input OUTPUTCLK; input OUTPUTENABLE; input PADIN; output PADOEN; output PADOUT; endmodule module PRE_IO(PADIN, PADOUT, PADOEN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0); input CLOCKENABLE; output DIN0; output DIN1; input DOUT0; input DOUT1; input INPUTCLK; input LATCHINPUTVALUE; input OUTPUTCLK; input OUTPUTENABLE; input PADIN; output PADOEN; output PADOUT; endmodule module PRE_IO_GBUF(GLOBALBUFFEROUTPUT, PADSIGNALTOGLOBALBUFFER); output GLOBALBUFFEROUTPUT; input PADSIGNALTOGLOBALBUFFER; endmodule module QuadClkMux(I, O); input I; output O; endmodule module SB_G2TBuf(I, O); input I; output O; endmodule module SMCCLK(CLK); output CLK; endmodule module SRMux(I, O); input I; output O; endmodule module Sp12to4(I, O); input I; output O; endmodule module Span12Mux(I, O); input I; output O; endmodule module Span12Mux_h(I, O); input I; output O; endmodule module Span12Mux_s0_h(I, O); input I; output O; endmodule module Span12Mux_s0_v(I, O); input I; output O; endmodule module Span12Mux_s10_h(I, O); input I; output O; endmodule module Span12Mux_s10_v(I, O); input I; output O; endmodule module Span12Mux_s11_h(I, O); input I; output O; endmodule module Span12Mux_s11_v(I, O); input I; output O; endmodule module Span12Mux_s1_h(I, O); input I; output O; endmodule module Span12Mux_s1_v(I, O); input I; output O; endmodule module Span12Mux_s2_h(I, O); input I; output O; endmodule module Span12Mux_s2_v(I, O); input I; output O; endmodule module Span12Mux_s3_h(I, O); input I; output O; endmodule module Span12Mux_s3_v(I, O); input I; output O; endmodule module Span12Mux_s4_h(I, O); input I; output O; endmodule module Span12Mux_s4_v(I, O); input I; output O; endmodule module Span12Mux_s5_h(I, O); input I; output O; endmodule module Span12Mux_s5_v(I, O); input I; output O; endmodule module Span12Mux_s6_h(I, O); input I; output O; endmodule module Span12Mux_s6_v(I, O); input I; output O; endmodule module Span12Mux_s7_h(I, O); input I; output O; endmodule module Span12Mux_s7_v(I, O); input I; output O; endmodule module Span12Mux_s8_h(I, O); input I; output O; endmodule module Span12Mux_s8_v(I, O); input I; output O; endmodule module Span12Mux_s9_h(I, O); input I; output O; endmodule module Span12Mux_s9_v(I, O); input I; output O; endmodule module Span12Mux_v(I, O); input I; output O; endmodule module Span4Mux(I, O); input I; output O; endmodule module Span4Mux_h(I, O); input I; output O; endmodule module Span4Mux_s0_h(I, O); input I; output O; endmodule module Span4Mux_s0_v(I, O); input I; output O; endmodule module Span4Mux_s1_h(I, O); input I; output O; endmodule module Span4Mux_s1_v(I, O); input I; output O; endmodule module Span4Mux_s2_h(I, O); input I; output O; endmodule module Span4Mux_s2_v(I, O); input I; output O; endmodule module Span4Mux_s3_h(I, O); input I; output O; endmodule module Span4Mux_s3_v(I, O); input I; output O; endmodule module Span4Mux_v(I, O); input I; output O; endmodule module carry_logic(cout, carry_in, a, a_bar, b, b_bar, vg_en); input a; input a_bar; input b; input b_bar; input carry_in; output cout; input vg_en; endmodule module clut4(lut4, in0, in1, in2, in3, in0b, in1b, in2b, in3b, cbit); input [15:0] cbit; input in0; input in0b; input in1; input in1b; input in2; input in2b; input in3; input in3b; output lut4; endmodule module coredffr(q, d, purst, S_R, cbit, clk, clkb); input S_R; input [1:0] cbit; input clk; input clkb; input d; input purst; output q; endmodule module coredffr2(q, d, purst, S_R, cbit, clk, clkb, ce); input S_R; input [1:0] cbit; input ce; input clk; input clkb; input d; input purst; output q; endmodule module gio2CtrlBuf(I, O); input I; output O; endmodule module inv_hvt(Y, A); input A; output Y; endmodule module logic_cell(carry_out, lc_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r); input carry_in; output carry_out; input [20:0] cbit; input clk; input clkb; input in0; input in1; input in2; input in3; output lc_out; input prog; input purst; input s_r; endmodule module logic_cell2(carry_out, lc_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r, ce); input carry_in; output carry_out; input [20:0] cbit; input ce; input clk; input clkb; input in0; input in1; input in2; input in3; output lc_out; input prog; input purst; input s_r; endmodule module logic_cell40(carry_out, lc_out, lt_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r, ce); input carry_in; output carry_out; input [20:0] cbit; input ce; input clk; input clkb; input in0; input in1; input in2; input in3; output lc_out; output lt_out; input prog; input purst; input s_r; endmodule module o_mux(O, in0, in1, cbit, prog); output O; input cbit; input in0; input in1; input prog; endmodule module sync_clk_enable(D, NC, Q); input D; input NC; output Q; endmodule module Span4Mux_h0(I, O); input I; output O; endmodule module Span4Mux_h1(I, O); input I; output O; endmodule module Span4Mux_h2(I, O); input I; output O; endmodule module Span4Mux_h3(I, O); input I; output O; endmodule module Span4Mux_h4(I, O); input I; output O; endmodule module Span4Mux_v0(I, O); input I; output O; endmodule module Span4Mux_v1(I, O); input I; output O; endmodule module Span4Mux_v2(I, O); input I; output O; endmodule module Span4Mux_v3(I, O); input I; output O; endmodule module Span4Mux_v4(I, O); input I; output O; endmodule module Span12Mux_h0(I, O); input I; output O; endmodule module Span12Mux_h1(I, O); input I; output O; endmodule module Span12Mux_h2(I, O); input I; output O; endmodule module Span12Mux_h3(I, O); input I; output O; endmodule module Span12Mux_h4(I, O); input I; output O; endmodule module Span12Mux_h5(I, O); input I; output O; endmodule module Span12Mux_h6(I, O); input I; output O; endmodule module Span12Mux_h7(I, O); input I; output O; endmodule module Span12Mux_h8(I, O); input I; output O; endmodule module Span12Mux_h9(I, O); input I; output O; endmodule module Span12Mux_h10(I, O); input I; output O; endmodule module Span12Mux_h11(I, O); input I; output O; endmodule module Span12Mux_h12(I, O); input I; output O; endmodule module Span12Mux_v0(I, O); input I; output O; endmodule module Span12Mux_v1(I, O); input I; output O; endmodule module Span12Mux_v2(I, O); input I; output O; endmodule module Span12Mux_v3(I, O); input I; output O; endmodule module Span12Mux_v4(I, O); input I; output O; endmodule module Span12Mux_v5(I, O); input I; output O; endmodule module Span12Mux_v6(I, O); input I; output O; endmodule module Span12Mux_v7(I, O); input I; output O; endmodule module Span12Mux_v8(I, O); input I; output O; endmodule module Span12Mux_v9(I, O); input I; output O; endmodule module Span12Mux_v10(I, O); input I; output O; endmodule module Span12Mux_v11(I, O); input I; output O; endmodule module Span12Mux_v12(I, O); input I; output O; endmodule module GND(Y); output Y; endmodule module VCC(Y); output Y; endmodule module INTERCONN(I, O); input I; output O; endmodule module SB_RAM40_4K(RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA); output [15:0] RDATA; input RCLK, RCLKE, RE; input [10:0] RADDR; input WCLK, WCLKE, WE; input [10:0] WADDR; input [15:0] MASK, WDATA; endmodule fpga-icestorm-0~20160913git266e758/icetime/icetime.cc000066400000000000000000002001541276746530600217410ustar00rootroot00000000000000// // Copyright (C) 2015 Clifford Wolf // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. // #if !defined(_WIN32) && !defined(_GNU_SOURCE) // for vasprintf() #define _GNU_SOURCE #endif #include #include #include #include #include #include #include #include #include #include #include #include // add this number of ns as estimate for clock distribution mismatch #define GLOBAL_CLK_DIST_JITTER 0.1 FILE *fin = nullptr, *fout = nullptr, *frpt = nullptr; FILE *fjson = nullptr; bool verbose = false; bool max_span_hack = false; bool json_firstentry = true; std::string config_device, device_type, selected_package; std::vector> config_tile_type; std::vector>>> config_bits; std::map, std::string> pin_pos; std::map pin_names; std::set> extra_bits; std::set io_names; std::map net_symbols; struct net_segment_t { int x, y, net; std::string name; net_segment_t() : x(-1), y(-1), net(-1) { } net_segment_t(int x, int y, int net, std::string name) : x(x), y(y), net(net), name(name) { } bool operator==(const net_segment_t &other) const { return (x == other.x) && (y == other.y) && (name == other.name); } bool operator!=(const net_segment_t &other) const { return (x != other.x) || (y != other.y) || (name != other.name); } bool operator<(const net_segment_t &other) const { if (x != other.x) return x < other.x; if (y != other.y) return y < other.y; return name < other.name; } }; std::set segments; std::map> net_to_segments; std::map, int> x_y_name_net; std::map, net_segment_t> x_y_net_segment; std::map> net_buffers, net_rbuffers, net_routing; std::map, std::pair> connection_pos; std::set used_nets, graph_nets; std::set interconn_src, interconn_dst; std::set no_interconn_net; int tname_cnt = 0; // netlist_cell_ports[cell_name][port_name] = port_expr std::map> netlist_cell_ports; std::map> netlist_cell_params; std::map netlist_cell_types; std::set extra_wires; std::vector extra_vlog; std::map net_assignments; std::set declared_nets; int dangling_cnt = 0; std::map>> logic_tile_bits, io_tile_bits, ramb_tile_bits, ramt_tile_bits; std::string vstringf(const char *fmt, va_list ap) { std::string string; char *str = NULL; #ifdef _WIN32 int sz = 64, rc; while (1) { va_list apc; va_copy(apc, ap); str = (char*)realloc(str, sz); rc = vsnprintf(str, sz, fmt, apc); va_end(apc); if (rc >= 0 && rc < sz) break; sz *= 2; } #else if (vasprintf(&str, fmt, ap) < 0) str = NULL; #endif if (str != NULL) { string = str; free(str); } return string; } std::string stringf(const char *fmt, ...) { std::string string; va_list ap; va_start(ap, fmt); string = vstringf(fmt, ap); va_end(ap); return string; } std::string tname() { return stringf("t%d", tname_cnt++); } std::string net_name(int net) { declared_nets.insert(net); return stringf("net_%d", net); } std::string seg_name(const net_segment_t &seg, int idx = 0) { std::string str = stringf("seg_%d_%d_%s_%d", seg.x, seg.y, seg.name.c_str(), seg.net); for (auto &ch : str) if (ch == '/') ch = '_'; if (idx != 0) str += stringf("_i%d", idx); extra_wires.insert(str); return str; } void read_pcf(const char *filename) { FILE *f = fopen(filename, "r"); if (f == nullptr) { perror("Can't open pcf file"); exit(1); } char buffer[128]; while (fgets(buffer, 128, f)) { for (int i = 0; buffer[i]; i++) if (buffer[i] == '#') { buffer[i] = 0; break; } const char *tok = strtok(buffer, " \t\r\n"); if (tok == nullptr || strcmp(tok, "set_io")) continue; std::vector args; while ((tok = strtok(nullptr, " \t\r\n")) != nullptr) { if (!strcmp(tok, "--warn-no-port")) continue; args.push_back(tok); } assert(args.size() == 2); pin_names[args[1]] = args[0]; } fclose(f); } void read_config() { char buffer[128]; int tile_x, tile_y, line_nr = -1; while (fgets(buffer, 128, fin)) { if (buffer[0] == '.') { line_nr = -1; const char *tok = strtok(buffer, " \t\r\n"); if (!strcmp(tok, ".device")) { config_device = strtok(nullptr, " \t\r\n"); } else if (!strcmp(tok, ".io_tile") || !strcmp(tok, ".logic_tile") || !strcmp(tok, ".ramb_tile") || !strcmp(tok, ".ramt_tile")) { line_nr = 0; tile_x = atoi(strtok(nullptr, " \t\r\n")); tile_y = atoi(strtok(nullptr, " \t\r\n")); if (tile_x >= int(config_tile_type.size())) { config_tile_type.resize(tile_x+1); config_bits.resize(tile_x+1); } if (tile_y >= int(config_tile_type.at(tile_x).size())) { config_tile_type.at(tile_x).resize(tile_y+1); config_bits.at(tile_x).resize(tile_y+1); } if (!strcmp(tok, ".io_tile")) config_tile_type.at(tile_x).at(tile_y) = "io"; if (!strcmp(tok, ".logic_tile")) config_tile_type.at(tile_x).at(tile_y) = "logic"; if (!strcmp(tok, ".ramb_tile")) config_tile_type.at(tile_x).at(tile_y) = "ramb"; if (!strcmp(tok, ".ramt_tile")) config_tile_type.at(tile_x).at(tile_y) = "ramt"; } else if (!strcmp(tok, ".extra_bit")) { int b = atoi(strtok(nullptr, " \t\r\n")); int x = atoi(strtok(nullptr, " \t\r\n")); int y = atoi(strtok(nullptr, " \t\r\n")); std::tuple key(b, x, y); extra_bits.insert(key); } else if (!strcmp(tok, ".sym")) { int net = atoi(strtok(nullptr, " \t\r\n")); const char *name = strtok(nullptr, " \t\r\n"); net_symbols[net] = name; } } else if (line_nr >= 0) { assert(int(config_bits.at(tile_x).at(tile_y).size()) == line_nr); config_bits.at(tile_x).at(tile_y).resize(line_nr+1); for (int i = 0; buffer[i] == '0' || buffer[i] == '1'; i++) config_bits.at(tile_x).at(tile_y).at(line_nr).push_back(buffer[i] == '1'); line_nr++; } } } void read_chipdb() { char buffer[1024]; if (PREFIX[0] == '~' && PREFIX[1] == '/') { std::string homedir; #ifdef _WIN32 if (getenv("USERPROFILE") != nullptr) { homedir += getenv("USERPROFILE"); } else { if (getenv("HOMEDRIVE") != nullptr && getenv("HOMEPATH") != nullptr) { homedir += getenv("HOMEDRIVE"); homedir += getenv("HOMEPATH"); } } #else homedir += getenv("HOME"); #endif snprintf(buffer, 1024, "%s%s/share/icebox/chipdb-%s.txt", homedir.c_str(), PREFIX+1, config_device.c_str()); } else snprintf(buffer, 1024, "%s/share/icebox/chipdb-%s.txt", PREFIX, config_device.c_str()); FILE *fdb = fopen(buffer, "r"); if (fdb == nullptr) { perror("Can't open chipdb file"); exit(1); } std::string mode; int current_net = -1; int tile_x = -1, tile_y = -1; std::string thiscfg; std::vector> gbufin; std::vector> gbufpin; std::set extrabitfunc; while (fgets(buffer, 1024, fdb)) { if (buffer[0] == '#') continue; const char *tok = strtok(buffer, " \t\r\n"); if (tok == nullptr) continue; if (tok[0] == '.') { mode = tok; if (mode == ".pins") { if (strtok(nullptr, " \t\r\n") != selected_package) mode = ""; continue; } if (mode == ".net") { current_net = atoi(strtok(nullptr, " \t\r\n")); continue; } if (mode == ".buffer" || mode == ".routing") { tile_x = atoi(strtok(nullptr, " \t\r\n")); tile_y = atoi(strtok(nullptr, " \t\r\n")); current_net = atoi(strtok(nullptr, " \t\r\n")); thiscfg = ""; while ((tok = strtok(nullptr, " \t\r\n")) != nullptr) { int bit_row, bit_col, rc; rc = sscanf(tok, "B%d[%d]", &bit_row, &bit_col); assert(rc == 2); thiscfg.push_back(config_bits[tile_x][tile_y][bit_row][bit_col] ? '1' : '0'); } continue; } continue; } if (mode == ".pins") { int pos_x = atoi(strtok(nullptr, " \t\r\n")); int pos_y = atoi(strtok(nullptr, " \t\r\n")); int pos_z = atoi(strtok(nullptr, " \t\r\n")); std::tuple key(pos_x, pos_y, pos_z); pin_pos[key] = tok; } if (mode == ".net") { int tile_x = atoi(tok); int tile_y = atoi(strtok(nullptr, " \t\r\n")); std::string segment_name = strtok(nullptr, " \t\r\n"); net_segment_t seg(tile_x, tile_y, current_net, segment_name); std::tuple x_y_name(tile_x, tile_y, segment_name); net_to_segments[current_net].insert(seg); segments.insert(seg); } if (mode == ".buffer" && !strcmp(tok, thiscfg.c_str())) { int other_net = atoi(strtok(nullptr, " \t\r\n")); net_rbuffers[current_net].insert(other_net); net_buffers[other_net].insert(current_net); connection_pos[std::pair(current_net, other_net)] = connection_pos[std::pair(other_net, current_net)] = std::pair(tile_x, tile_y); used_nets.insert(current_net); used_nets.insert(other_net); } if (mode == ".routing" && !strcmp(tok, thiscfg.c_str())) { int other_net = atoi(strtok(nullptr, " \t\r\n")); net_routing[current_net].insert(other_net); net_routing[other_net].insert(current_net); connection_pos[std::pair(current_net, other_net)] = connection_pos[std::pair(other_net, current_net)] = std::pair(tile_x, tile_y); used_nets.insert(current_net); used_nets.insert(other_net); } if (mode == ".gbufin" || mode == ".gbufpin") { std::vector items; while (tok != nullptr) { items.push_back(atoi(tok)); tok = strtok(nullptr, " \t\r\n"); } if (mode == ".gbufin") gbufin.push_back(items); else gbufpin.push_back(items); } if (mode == ".logic_tile_bits" || mode == ".io_tile_bits" || mode == ".ramb_tile_bits" || mode == ".ramt_tile_bits") { std::vector> items; while (1) { const char *s = strtok(nullptr, " \t\r\n"); if (s == nullptr) break; std::pair item; int rc = sscanf(s, "B%d[%d]", &item.first, &item.second); assert(rc == 2); items.push_back(item); } if (mode == ".logic_tile_bits") logic_tile_bits[tok] = items; if (mode == ".io_tile_bits") io_tile_bits[tok] = items; if (mode == ".ramb_tile_bits") ramb_tile_bits[tok] = items; if (mode == ".ramt_tile_bits") ramt_tile_bits[tok] = items; } if (mode == ".extra_bits") { int b = atoi(strtok(nullptr, " \t\r\n")); int x = atoi(strtok(nullptr, " \t\r\n")); int y = atoi(strtok(nullptr, " \t\r\n")); std::tuple key(b, x, y); if (extra_bits.count(key)) extrabitfunc.insert(tok); } } fclose(fdb); // purge unused nets from memory int max_net = net_to_segments.rbegin()->first; for (int net = 0; net <= max_net; net++) { if (used_nets.count(net)) continue; for (auto seg : net_to_segments[net]) segments.erase(seg); net_to_segments.erase(net); for (auto other : net_buffers[net]) net_rbuffers[other].erase(net); net_buffers.erase(net); for (auto other : net_rbuffers[net]) net_buffers[other].erase(net); net_rbuffers.erase(net); for (auto other : net_routing[net]) net_routing[other].erase(net); net_routing.erase(net); } // create index for (auto seg : segments) { std::tuple key(seg.x, seg.y, seg.net); x_y_net_segment[key] = seg; } for (auto seg : segments) { std::tuple key(seg.x, seg.y, seg.name); x_y_name_net[key] = seg.net; } for (auto &it : gbufin) { int x = it[0], y = it[1], g = it[2]; std::tuple fabout_x_y_name(x, y, "fabout"); std::tuple glbl_x_y_name(x, y, stringf("glb_netwk_%d", g)); if (!x_y_name_net.count(fabout_x_y_name) || !x_y_name_net.count(glbl_x_y_name)) continue; int fabout_net = x_y_name_net.at(fabout_x_y_name); int glbl_net = x_y_name_net.at(glbl_x_y_name); assert(used_nets.count(fabout_net)); assert(used_nets.count(glbl_net)); net_rbuffers[glbl_net].insert(fabout_net); net_buffers[fabout_net].insert(glbl_net); connection_pos[std::pair(glbl_net, fabout_net)] = connection_pos[std::pair(fabout_net, glbl_net)] = std::pair(x, y); } if (verbose) { for (int net : used_nets) { printf("// NET %d:\n", net); for (auto seg : net_to_segments[net]) printf("// SEG %d %d %s\n", seg.x, seg.y, seg.name.c_str()); for (auto other : net_buffers[net]) printf("// BUFFER %d %d %d\n", connection_pos[std::pair(net, other)].first, connection_pos[std::pair(net, other)].second, other); for (auto other : net_rbuffers[net]) printf("// RBUFFER %d %d %d\n", connection_pos[std::pair(net, other)].first, connection_pos[std::pair(net, other)].second, other); for (auto other : net_routing[net]) printf("// ROUTE %d %d %d\n", connection_pos[std::pair(net, other)].first, connection_pos[std::pair(net, other)].second, other); } } } bool is_primary(std::string cell_name, std::string out_port) { auto cell_type = netlist_cell_types[cell_name]; if (cell_type == "SB_RAM40_4K") return true; if (cell_type == "LogicCell40" && out_port == "lcout") { // SEQ_MODE = "4'bX..."; bool dff_enable = netlist_cell_params[cell_name]["SEQ_MODE"][3] == '1'; return dff_enable; } if (cell_type == "PRE_IO") return true; return false; } const std::set &get_inports(std::string cell_type) { static bool first_call = true; static std::map> inports_map; if (first_call) { first_call = false; inports_map["Span4Mux_h0"] = { "I" }; inports_map["Span4Mux_h1"] = { "I" }; inports_map["Span4Mux_h2"] = { "I" }; inports_map["Span4Mux_h3"] = { "I" }; inports_map["Span4Mux_h4"] = { "I" }; inports_map["Span4Mux_v0"] = { "I" }; inports_map["Span4Mux_v1"] = { "I" }; inports_map["Span4Mux_v2"] = { "I" }; inports_map["Span4Mux_v3"] = { "I" }; inports_map["Span4Mux_v4"] = { "I" }; inports_map["Span12Mux_h0"] = { "I" }; inports_map["Span12Mux_h1"] = { "I" }; inports_map["Span12Mux_h2"] = { "I" }; inports_map["Span12Mux_h3"] = { "I" }; inports_map["Span12Mux_h4"] = { "I" }; inports_map["Span12Mux_h5"] = { "I" }; inports_map["Span12Mux_h6"] = { "I" }; inports_map["Span12Mux_h7"] = { "I" }; inports_map["Span12Mux_h8"] = { "I" }; inports_map["Span12Mux_h9"] = { "I" }; inports_map["Span12Mux_h10"] = { "I" }; inports_map["Span12Mux_h11"] = { "I" }; inports_map["Span12Mux_h12"] = { "I" }; inports_map["Span12Mux_v0"] = { "I" }; inports_map["Span12Mux_v1"] = { "I" }; inports_map["Span12Mux_v2"] = { "I" }; inports_map["Span12Mux_v3"] = { "I" }; inports_map["Span12Mux_v4"] = { "I" }; inports_map["Span12Mux_v5"] = { "I" }; inports_map["Span12Mux_v6"] = { "I" }; inports_map["Span12Mux_v7"] = { "I" }; inports_map["Span12Mux_v8"] = { "I" }; inports_map["Span12Mux_v9"] = { "I" }; inports_map["Span12Mux_v10"] = { "I" }; inports_map["Span12Mux_v11"] = { "I" }; inports_map["Span12Mux_v12"] = { "I" }; inports_map["Odrv4"] = { "I" }; inports_map["Odrv12"] = { "I" }; inports_map["Sp12to4"] = { "I" }; inports_map["InMux"] = { "I" }; inports_map["IoInMux"] = { "I" }; inports_map["IoSpan4Mux"] = { "I" }; inports_map["IpInMux"] = { "I" }; inports_map["IpOutMux"] = { "I" }; inports_map["LocalMux"] = { "I" }; inports_map["CEMux"] = { "I" }; inports_map["SRMux"] = { "I" }; inports_map["ClkMux"] = { "I" }; inports_map["CascadeBuf"] = { "I" }; inports_map["CascadeMux"] = { "I" }; inports_map["GlobalMux"] = { "I" }; inports_map["gio2CtrlBuf"] = { "I" }; inports_map["ICE_GB"] = { "USERSIGNALTOGLOBALBUFFER" }; inports_map["ICE_CARRY_IN_MUX"] = { "carryinitin" }; inports_map["LogicCell40"] = { "clk", "carryin", "in0", "in1", "in2", "in3", "sr", "ce" }; inports_map["PRE_IO"] = { "INPUTCLK", "OUTPUTCLK", "LATCHINPUTVALUE", "CLOCKENABLE", "OUTPUTENABLE", "DOUT1", "DOUT0", "PADIN" }; inports_map["SB_RAM40_4K"] = { "RCLK", "RCLKE", "RE", "WCLK", "WCLKE", "WE" }; for (int i = 0; i < 16; i++) { inports_map["SB_RAM40_4K"].insert(stringf("MASK[%d]", i)); inports_map["SB_RAM40_4K"].insert(stringf("WDATA[%d]", i)); } for (int i = 0; i < 11; i++) { inports_map["SB_RAM40_4K"].insert(stringf("RADDR[%d]", i)); inports_map["SB_RAM40_4K"].insert(stringf("WADDR[%d]", i)); } inports_map["INTERCONN"] = { "I" }; } if (inports_map.count(cell_type) == 0) { fprintf(stderr, "Missing entry in inports_map for cell type %s!\n", cell_type.c_str()); exit(1); } return inports_map.at(cell_type); } #include "timings.inc" double get_delay(std::string cell_type, std::string in_port, std::string out_port) { if (cell_type == "INTERCONN") return 0; if (device_type == "lp1k") return get_delay_lp1k(cell_type, in_port, out_port); if (device_type == "lp8k") return get_delay_lp8k(cell_type, in_port, out_port); if (device_type == "hx1k") return get_delay_hx1k(cell_type, in_port, out_port); if (device_type == "hx8k") return get_delay_hx8k(cell_type, in_port, out_port); fprintf(stderr, "No built-in timing database for '%s' devices!\n", device_type.c_str()); exit(1); } struct TimingAnalysis { // net_driver[] = { , } std::map> net_driver; // net_max_setup[] = { , , } std::map> net_max_setup; // net_max_path_parent[] = { , , , , } std::map> net_max_path_parent; std::map net_max_path_delay; std::string global_max_path_net; double global_max_path_delay; bool interior_timing; std::set interior_nets; double calc_net_max_path_delay(const std::string &net) { if (net_max_path_delay.count(net)) return net_max_path_delay.at(net); if (net_driver.count(net) == 0) return 0; double max_path_delay = -1e6; net_max_path_delay[net] = 1e6; auto &driver_cell = net_driver.at(net).first; auto &driver_port = net_driver.at(net).second; auto &driver_type = netlist_cell_types.at(driver_cell); if (is_primary(driver_cell, driver_port)) { if (interior_timing && driver_type == "PRE_IO") net_max_path_delay[net] = -1e3; else net_max_path_delay[net] = get_delay(driver_type, "*clkedge*", driver_port) + GLOBAL_CLK_DIST_JITTER; return net_max_path_delay[net]; } for (auto &inport : get_inports(driver_type)) { if (inport == "clk" || inport == "INPUTCLK" || inport == "OUTPUTCLK" || inport == "PADIN") continue; if (driver_type == "LogicCell40" && driver_port == "carryout") { if (inport == "in0" || inport == "in3" || inport == "ce" || inport == "sr") continue; } if (driver_type == "LogicCell40" && (driver_port == "ltout" || driver_port == "lcout")) { if (inport == "carryin") continue; } std::string *in_net = &netlist_cell_ports.at(driver_cell).at(inport); while (net_assignments.count(*in_net)) in_net = &net_assignments.at(*in_net); if (*in_net == "" || *in_net == "vcc" || *in_net == "gnd") continue; double this_cell_delay = get_delay(driver_type, inport, driver_port); double this_path_delay = calc_net_max_path_delay(*in_net) + this_cell_delay; if (this_path_delay >= max_path_delay) { net_max_path_parent[net] = std::make_tuple(*in_net, driver_cell, inport, driver_port, this_cell_delay); max_path_delay = this_path_delay; } } net_max_path_delay[net] = max_path_delay; return net_max_path_delay.at(net); } void mark_interior(std::string net) { if (net.empty()) return; while (net_assignments.count(net)) { interior_nets.insert(net); net = net_assignments.at(net); } interior_nets.insert(net); } TimingAnalysis(bool interior_timing) : interior_timing(interior_timing) { std::set all_nets; for (auto &it : netlist_cell_ports) for (auto &it2 : it.second) { auto &cell_name = it.first; auto &port_name = it2.first; auto &net_name = it2.second; if (net_name == "") continue; auto &cell_type = netlist_cell_types.at(cell_name); if (get_inports(cell_type).count(port_name)) { std::string n = net_name; while (1) { double setup_time = get_delay(cell_type, port_name, "*setup*"); if (setup_time >= std::get<0>(net_max_setup[n])) net_max_setup[n] = std::make_tuple(setup_time, cell_name, port_name); if (net_assignments.count(n) == 0) break; n = net_assignments.at(n); } if (interior_timing && cell_type != "PRE_IO" && is_primary(cell_name, "lcout")) mark_interior(net_name); continue; } net_driver[net_name] = { cell_name, port_name }; all_nets.insert(net_name); } global_max_path_delay = 0; for (auto &net : all_nets) { if (interior_timing && interior_nets.count(net) == 0) continue; double d = calc_net_max_path_delay(net) + std::get<0>(net_max_setup[net]); if (d > global_max_path_delay) { global_max_path_delay = d; global_max_path_net = net; } } } double report(std::string n = std::string()) { std::vector rpt_lines; std::vector json_lines; std::set visited_nets; if (n.empty()) { n = global_max_path_net; if (n.empty()) { fprintf(stderr, "No path found!\n"); exit(1); } if (frpt) { int i = fprintf(frpt, "Report for critical path:\n"); while (--i) fputc('-', frpt); fprintf(frpt, "\n\n"); } } else if (frpt) { int i = fprintf(frpt, "Report for %s:\n", n.c_str()); while (--i) fputc('-', frpt); fprintf(frpt, "\n\n"); } if (net_max_path_delay.count(n) == 0) { fprintf(stderr, "Net not found: %s\n", n.c_str()); exit(1); } double delay = net_max_path_delay.at(n); std::string net_sym; std::vector> sym_list; std::map outsym_list; int logic_levels = 0; bool last_line = true; auto &user = net_max_setup[n]; if (!std::get<1>(user).empty()) { delay += std::get<0>(user); std::string outnet, outnethw, outnetsym; auto &inports = get_inports(netlist_cell_types.at(std::get<1>(user))); for (auto &it : netlist_cell_ports.at(std::get<1>(user))) { if (inports.count(it.first) || it.second.empty()) continue; int netidx; char dummy_ch; outnetsym = outnethw = outnet = it.second; if (sscanf(it.second.c_str(), "net_%d%c", &netidx, &dummy_ch) == 1 && net_symbols.count(netidx)) { outnetsym = outsym_list[it.first] = net_symbols[netidx]; outnet += stringf(" (%s)", outnetsym.c_str()); } } rpt_lines.push_back(stringf("%10.3f ns %s", delay, outnet.c_str())); rpt_lines.push_back(stringf(" %s (%s) %s [setup]: %.3f ns", std::get<1>(user).c_str(), netlist_cell_types.at(std::get<1>(user)).c_str(), std::get<2>(user).c_str(), std::get<0>(user))); std::string netprop = outnetsym == outnethw ? "" : stringf("\"net\": \"%s\", ", outnetsym.c_str()); json_lines.push_back(stringf(" { %s\"hwnet\": \"%s\", \"cell\": \"%s\", \"cell_type\": \"%s\", \"cell_in_port\": \"%s\", \"cell_out_port\": \"[setup]\", \"delay_ns\": %.3f },", netprop.c_str(), outnethw.c_str(), std::get<1>(user).c_str(), netlist_cell_types.at(std::get<1>(user)).c_str(), std::get<2>(user).c_str(), delay)); } while (1) { int netidx; char dummy_ch; std::string outnetsym = n; if (sscanf(n.c_str(), "net_%d%c", &netidx, &dummy_ch) == 1 && net_symbols.count(netidx)) { sym_list.push_back(std::make_pair(calc_net_max_path_delay(n), net_symbols[netidx])); if (net_sym.empty() || net_sym[0] == '$') net_sym = sym_list.back().second; } if (net_max_path_parent.count(n) == 0) { rpt_lines.push_back(stringf("%10.3f ns %s", calc_net_max_path_delay(n), n.c_str())); if (!net_sym.empty()) { rpt_lines.back() += stringf(" (%s)", net_sym.c_str()); outnetsym = net_sym; net_sym.clear(); } if (net_driver.count(n)) { auto &driver_cell = net_driver.at(n).first; auto &driver_port = net_driver.at(n).second; auto &driver_type = netlist_cell_types.at(driver_cell); std::string netprop = outnetsym == n ? "" : stringf("\"net\": \"%s\", ", outnetsym.c_str()); json_lines.push_back(stringf(" { %s\"hwnet\": \"%s\", \"cell\": \"%s\", \"cell_type\": \"%s\", \"cell_in_port\": \"[clk]\", \"cell_out_port\": \"%s\", \"delay_ns\": %.3f },", netprop.c_str(), n.c_str(), driver_cell.c_str(), driver_type.c_str(), driver_port.c_str(), calc_net_max_path_delay(n))); rpt_lines.push_back(stringf(" %s (%s) [clk] -> %s: %.3f ns", driver_cell.c_str(), driver_type.c_str(), driver_port.c_str(), calc_net_max_path_delay(n))); } else { rpt_lines.push_back(stringf(" no driver model at %s", n.c_str())); } break; } if (visited_nets.count(n)) { rpt_lines.push_back(stringf(" loop-start at %s", n.c_str())); break; } auto &entry = net_max_path_parent.at(n); if (last_line || netlist_cell_types.at(std::get<1>(entry)) == "LogicCell40") { rpt_lines.push_back(stringf("%10.3f ns %s", calc_net_max_path_delay(n), n.c_str())); logic_levels++; if (!net_sym.empty()) { rpt_lines.back() += stringf(" (%s)", net_sym.c_str()); outnetsym = net_sym; net_sym.clear(); } } std::string netprop = outnetsym == n ? "" : stringf("\"net\": \"%s\", ", outnetsym.c_str()); json_lines.push_back(stringf(" { %s\"hwnet\": \"%s\", \"cell\": \"%s\", \"cell_type\": \"%s\", \"cell_in_port\": \"%s\", \"cell_out_port\": \"%s\", \"delay_ns\": %.3f },", netprop.c_str(), n.c_str(), std::get<1>(entry).c_str(), netlist_cell_types.at(std::get<1>(entry)).c_str(), std::get<2>(entry).c_str(), std::get<3>(entry).c_str(), calc_net_max_path_delay(n))); rpt_lines.push_back(stringf(" %s (%s) %s -> %s: %.3f ns", std::get<1>(entry).c_str(), netlist_cell_types.at(std::get<1>(entry)).c_str(), std::get<2>(entry).c_str(), std::get<3>(entry).c_str(), std::get<4>(entry))); visited_nets.insert(n); n = std::get<0>(entry); last_line = false; } if (fjson) { if (!json_firstentry) fprintf(fjson, " ],\n"); fprintf(fjson, " [\n"); for (int i = int(json_lines.size())-1; i >= 0; i--) { std::string line = json_lines[i]; if (i == 0 && line.back() == ',') line.pop_back(); fprintf(fjson, "%s\n", line.c_str()); } json_firstentry = false; } if (frpt) { for (int i = int(rpt_lines.size())-1; i >= 0; i--) fprintf(frpt, "%s\n", rpt_lines[i].c_str()); if (!sym_list.empty() || !outsym_list.empty()) { fprintf(frpt, "\n"); fprintf(frpt, "Resolvable net names on path:\n"); std::string last_net; double first_time, last_time; for (int i = int(sym_list.size())-1; i >= 0; i--) { if (last_net != sym_list[i].second) { if (!last_net.empty()) fprintf(frpt, "%10.3f ns ..%7.3f ns %s\n", first_time, last_time, last_net.c_str()); first_time = sym_list[i].first; last_net = sym_list[i].second; } last_time = sym_list[i].first; } if (!last_net.empty()) fprintf(frpt, "%10.3f ns ..%7.3f ns %s\n", first_time, last_time, last_net.c_str()); for (auto &it : outsym_list) fprintf(frpt, "%23s -> %s\n", it.first.c_str(), it.second.c_str()); } fprintf(frpt, "\n"); fprintf(frpt, "Total number of logic levels: %d\n", logic_levels); fprintf(frpt, "Total path delay: %.2f ns (%.2f MHz)\n", delay, 1000.0 / delay); fprintf(frpt, "\n"); } return delay; } }; void register_interconn_src(int x, int y, int net) { std::tuple key(x, y, net); interconn_src.insert(x_y_net_segment.at(key)); } void register_interconn_dst(int x, int y, int net) { std::tuple key(x, y, net); interconn_dst.insert(x_y_net_segment.at(key)); } std::string make_seg_pre_io(int x, int y, int z) { auto cell = stringf("pre_io_%d_%d_%d", x, y, z); if (netlist_cell_types.count(cell)) return cell; netlist_cell_types[cell] = "PRE_IO"; netlist_cell_ports[cell]["PADIN"] = stringf("io_pad_%d_%d_%d_dout", x, y, z); netlist_cell_ports[cell]["PADOUT"] = stringf("io_pad_%d_%d_%d_din", x, y, z); netlist_cell_ports[cell]["PADOEN"] = stringf("io_pad_%d_%d_%d_oe", x, y, z); netlist_cell_ports[cell]["LATCHINPUTVALUE"] = ""; netlist_cell_ports[cell]["CLOCKENABLE"] = ""; netlist_cell_ports[cell]["INPUTCLK"] = ""; netlist_cell_ports[cell]["OUTPUTCLK"] = ""; netlist_cell_ports[cell]["OUTPUTENABLE"] = ""; netlist_cell_ports[cell]["DOUT1"] = ""; netlist_cell_ports[cell]["DOUT0"] = ""; netlist_cell_ports[cell]["DIN1"] = ""; netlist_cell_ports[cell]["DIN0"] = ""; std::string pintype; std::pair bitpos; for (int i = 0; i < 6; i++) { bitpos = io_tile_bits[stringf("IOB_%d.PINTYPE_%d", z, 5-i)][0]; pintype.push_back(config_bits[x][y][bitpos.first][bitpos.second] ? '1' : '0'); } bitpos = io_tile_bits["NegClk"][0]; char negclk = config_bits[x][y][bitpos.first][bitpos.second] ? '1' : '0'; netlist_cell_params[cell]["NEG_TRIGGER"] = stringf("1'b%c", negclk); netlist_cell_params[cell]["PIN_TYPE"] = stringf("6'b%s", pintype.c_str()); std::string io_name; std::tuple key(x, y, z); if (pin_pos.count(key)) { io_name = pin_pos.at(key); io_name = pin_names.count(io_name) ? pin_names.at(io_name) : "io_" + io_name; } else { io_name = stringf("io_%d_%d_%d", x, y, z); } io_names.insert(io_name); extra_vlog.push_back(stringf(" inout %s;\n", io_name.c_str())); extra_vlog.push_back(stringf(" wire io_pad_%d_%d_%d_din;\n", x, y, z)); extra_vlog.push_back(stringf(" wire io_pad_%d_%d_%d_dout;\n", x, y, z)); extra_vlog.push_back(stringf(" wire io_pad_%d_%d_%d_oe;\n", x, y, z)); extra_vlog.push_back(stringf(" IO_PAD io_pad_%d_%d_%d (\n", x, y, z)); extra_vlog.push_back(stringf(" .DIN(io_pad_%d_%d_%d_din),\n", x, y, z)); extra_vlog.push_back(stringf(" .DOUT(io_pad_%d_%d_%d_dout),\n", x, y, z)); extra_vlog.push_back(stringf(" .OE(io_pad_%d_%d_%d_oe),\n", x, y, z)); extra_vlog.push_back(stringf(" .PACKAGEPIN(%s)\n", io_name.c_str())); extra_vlog.push_back(stringf(" );\n")); return cell; } std::string make_lc40(int x, int y, int z) { assert(0 < x && 0 < y && 0 <= z && z < 8); auto cell = stringf("lc40_%d_%d_%d", x, y, z); if (netlist_cell_types.count(cell)) return cell; netlist_cell_types[cell] = "LogicCell40"; netlist_cell_ports[cell]["carryin"] = "gnd"; netlist_cell_ports[cell]["ce"] = ""; netlist_cell_ports[cell]["clk"] = "gnd"; netlist_cell_ports[cell]["in0"] = "gnd"; netlist_cell_ports[cell]["in1"] = "gnd"; netlist_cell_ports[cell]["in2"] = "gnd"; netlist_cell_ports[cell]["in3"] = "gnd"; netlist_cell_ports[cell]["sr"] = "gnd"; netlist_cell_ports[cell]["carryout"] = ""; netlist_cell_ports[cell]["lcout"] = ""; netlist_cell_ports[cell]["ltout"] = ""; char lcbits[20]; auto &lcbits_pos = logic_tile_bits[stringf("LC_%d", z)]; for (int i = 0; i < 20; i++) lcbits[i] = config_bits[x][y][lcbits_pos[i].first][lcbits_pos[i].second] ? '1' : '0'; // FIXME: fill in the '0' netlist_cell_params[cell]["C_ON"] = stringf("1'b%c", lcbits[8]); netlist_cell_params[cell]["SEQ_MODE"] = stringf("4'b%c%c%c%c", lcbits[9], '0', '0', '0'); netlist_cell_params[cell]["LUT_INIT"] = stringf("16'b%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c", lcbits[0], lcbits[10], lcbits[11], lcbits[1], lcbits[2], lcbits[12], lcbits[13], lcbits[3], lcbits[7], lcbits[17], lcbits[16], lcbits[6], lcbits[5], lcbits[15], lcbits[14], lcbits[4]); if (lcbits[8] == '1') { if (z == 0) { auto co_cell = 1 < y ? make_lc40(x, y-1, 7) : std::string(); std::string n1, n2; char cinit_1 = config_bits[x][y][1][49] ? '1' : '0'; char cinit_0 = config_bits[x][y][1][50] ? '1' : '0'; if (cinit_1 == '1') { std::tuple key(x, y-1, "lutff_7/cout"); if (x_y_name_net.count(key)) { n1 = net_name(x_y_name_net.at(key)); } else { n1 = tname(); assert(!co_cell.empty()); netlist_cell_ports[co_cell]["carryout"] = n1; extra_wires.insert(n1); } } std::tuple key(x, y, "carry_in_mux"); if (x_y_name_net.count(key)) { n2 = net_name(x_y_name_net.at(key)); } else { n2 = tname(); extra_wires.insert(n2); } std::string tn = tname(); netlist_cell_types[tn] = "ICE_CARRY_IN_MUX"; netlist_cell_params[tn]["C_INIT"] = stringf("2'b%c%c", cinit_1, cinit_0); netlist_cell_ports[tn]["carryinitin"] = n1; netlist_cell_ports[tn]["carryinitout"] = n2; netlist_cell_ports[cell]["carryin"] = n2; } else { auto co_cell = make_lc40(x, y, z-1); std::tuple key(x, y, stringf("lutff_%d/cout", z-1)); auto n = x_y_name_net.count(key) ? net_name(x_y_name_net.at(key)) : tname(); netlist_cell_ports[co_cell]["carryout"] = n; netlist_cell_ports[cell]["carryin"] = n; extra_wires.insert(n); } std::tuple key(x, y, stringf("lutff_%d/cout", z-1)); } return cell; } std::string make_ram(int x, int y) { auto cell = stringf("ram_%d_%d", x, y); if (netlist_cell_types.count(cell)) return cell; netlist_cell_types[cell] = "SB_RAM40_4K"; for (int i = 0; i < 16; i++) { netlist_cell_ports[cell][stringf("MASK[%d]", i)] = ""; netlist_cell_ports[cell][stringf("RDATA[%d]", i)] = ""; netlist_cell_ports[cell][stringf("WDATA[%d]", i)] = ""; } for (int i = 0; i < 11; i++) { netlist_cell_ports[cell][stringf("RADDR[%d]", i)] = ""; netlist_cell_ports[cell][stringf("WADDR[%d]", i)] = ""; } netlist_cell_ports[cell]["RE"] = ""; netlist_cell_ports[cell]["RCLK"] = ""; netlist_cell_ports[cell]["RCLKE"] = ""; netlist_cell_ports[cell]["WE"] = ""; netlist_cell_ports[cell]["WCLK"] = ""; netlist_cell_ports[cell]["WCLKE"] = ""; return cell; } bool dff_uses_clock(int x, int y, int z) { auto bitpos = logic_tile_bits[stringf("LC_%d", z)][9]; return config_bits[x][y][bitpos.first][bitpos.second]; } void make_odrv(int x, int y, int src) { for (int dst : net_buffers[src]) { auto cell = stringf("odrv_%d_%d_%d_%d", x, y, src, dst); if (netlist_cell_types.count(cell)) continue; bool is4 = false, is12 = false; for (auto &seg : net_to_segments[dst]) { if (seg.name.substr(0, 4) == "sp4_") is4 = true; if (seg.name.substr(0, 5) == "sp12_") is12 = true; if (seg.name.substr(0, 6) == "span4_") is4 = true; if (seg.name.substr(0, 7) == "span12_") is12 = true; } if (!is4 && !is12) { register_interconn_src(x, y, src); continue; } assert(is4 != is12); netlist_cell_types[cell] = is4 ? "Odrv4" : "Odrv12"; netlist_cell_ports[cell]["I"] = net_name(src); netlist_cell_ports[cell]["O"] = net_name(dst); register_interconn_src(x, y, dst); } } void make_inmux(int x, int y, int dst, std::string muxtype = "") { for (int src : net_rbuffers[dst]) { std::tuple key(x, y, src); std::string src_name = x_y_net_segment.at(key).name; int cascade_n = 0; if (src_name.size() > 6) { cascade_n = src_name[6] - '0'; src_name[6] = 'X'; } if (src_name == "lutff_X/lout") { auto cell = make_lc40(x, y, cascade_n); netlist_cell_ports[cell]["ltout"] = net_name(dst); continue; } auto cell = stringf("inmux_%d_%d_%d_%d", x, y, src, dst); if (netlist_cell_types.count(cell)) continue; netlist_cell_types[cell] = muxtype.empty() ? (config_tile_type[x][y] == "io" ? "IoInMux" : "InMux") : muxtype; netlist_cell_ports[cell]["I"] = net_name(src); netlist_cell_ports[cell]["O"] = net_name(dst); register_interconn_dst(x, y, src); no_interconn_net.insert(dst); } } std::string cascademuxed(std::string n) { std::string nc = n + "_cascademuxed"; extra_wires.insert(nc); std::string tn = tname(); netlist_cell_types[tn] = "CascadeMux"; netlist_cell_ports[tn]["I"] = n; netlist_cell_ports[tn]["O"] = nc; return nc; } void make_seg_cell(int net, const net_segment_t &seg) { int a = -1, b = -1; char c = 0; if (sscanf(seg.name.c_str(), "io_%d/D_IN_%d", &a, &b) == 2) { auto cell = make_seg_pre_io(seg.x, seg.y, a); netlist_cell_ports[cell][stringf("DIN%d", b)] = net_name(net); make_odrv(seg.x, seg.y, net); return; } if (sscanf(seg.name.c_str(), "io_%d/D_OUT_%d", &a, &b) == 2) { auto cell = make_seg_pre_io(seg.x, seg.y, a); netlist_cell_ports[cell][stringf("DOUT%d", b)] = net_name(net); make_inmux(seg.x, seg.y, net); return; } if (sscanf(seg.name.c_str(), "lutff_%d/in_%d", &a, &b) == 2) { auto cell = make_lc40(seg.x, seg.y, a); if (b == 2) { // Lattice tools always put a CascadeMux on in2 netlist_cell_ports[cell][stringf("in%d", b)] = cascademuxed(net_name(net)); } else { netlist_cell_ports[cell][stringf("in%d", b)] = net_name(net); } make_inmux(seg.x, seg.y, net); return; } if (sscanf(seg.name.c_str(), "lutff_%d/ou%c", &a, &c) == 2 && c == 't') { for (int dst_net : net_buffers.at(seg.net)) for (auto &dst_seg : net_to_segments.at(dst_net)) { std::string n = dst_seg.name; if (n.size() > 6) n[6] = 'X'; if (n != "lutff_X/in_2") goto use_lcout; } return; use_lcout: auto cell = make_lc40(seg.x, seg.y, a); netlist_cell_ports[cell]["lcout"] = net_name(net); make_odrv(seg.x, seg.y, net); return; } if (sscanf(seg.name.c_str(), "lutff_%d/cou%c", &a, &c) == 2 && c == 't') { auto cell = make_lc40(seg.x, seg.y, a); netlist_cell_ports[cell]["carryout"] = net_name(net); return; } if (seg.name.substr(0, 4) == "ram/") { auto cell = make_ram(seg.x, 2*((seg.y-1) >> 1) + 1); if (sscanf(seg.name.c_str(), "ram/MASK_%d", &a) == 1) { netlist_cell_ports[cell][stringf("MASK[%d]", a)] = net_name(net); make_inmux(seg.x, seg.y, net); } else if (sscanf(seg.name.c_str(), "ram/RADDR_%d", &a) == 1) { netlist_cell_ports[cell][stringf("RADDR[%d]", a)] = cascademuxed(net_name(net)); make_inmux(seg.x, seg.y, net); } else if (sscanf(seg.name.c_str(), "ram/RDATA_%d", &a) == 1) { netlist_cell_ports[cell][stringf("RDATA[%d]", a)] = net_name(net); make_odrv(seg.x, seg.y, net); } else if (sscanf(seg.name.c_str(), "ram/WADDR_%d", &a) == 1) { netlist_cell_ports[cell][stringf("WADDR[%d]", a)] = cascademuxed(net_name(net)); make_inmux(seg.x, seg.y, net); } else if (sscanf(seg.name.c_str(), "ram/WDATA_%d", &a) == 1) { netlist_cell_ports[cell][stringf("WDATA[%d]", a)] = net_name(net); make_inmux(seg.x, seg.y, net); } else { netlist_cell_ports[cell][seg.name.substr(4)] = net_name(net); if (seg.name == "ram/RCLK" || seg.name == "ram/WCLK") make_inmux(seg.x, seg.y, net, "ClkMux"); else if (seg.name == "ram/RCLKE" || seg.name == "ram/WCLKE") make_inmux(seg.x, seg.y, net, "CEMux"); else make_inmux(seg.x, seg.y, net, "SRMux"); } return; } if (seg.name == "lutff_global/clk" || seg.name == "lutff_global/cen" || seg.name == "lutff_global/s_r") { for (int i = 0; i < 8; i++) { if (!dff_uses_clock(seg.x, seg.y, i)) continue; std::tuple key(seg.x, seg.y, stringf("lutff_%d/out", i)); if (x_y_name_net.count(key)) { auto cell = make_lc40(seg.x, seg.y, i); if (seg.name == "lutff_global/clk") { make_inmux(seg.x, seg.y, net, "ClkMux"); netlist_cell_ports[cell]["clk"] = net_name(seg.net); } if (seg.name == "lutff_global/cen") { make_inmux(seg.x, seg.y, net, "CEMux"); netlist_cell_ports[cell]["ce"] = net_name(seg.net); } if (seg.name == "lutff_global/s_r") { make_inmux(seg.x, seg.y, net, "SRMux"); netlist_cell_ports[cell]["sr"] = net_name(seg.net); } } } return; } if (seg.name == "io_global/inclk" || seg.name == "io_global/outclk" || seg.name == "io_global/cen") { for (int z = 0; z < 2; z++) { std::string pintype; std::pair bitpos; for (int i = 0; i < 6; i++) { bitpos = io_tile_bits[stringf("IOB_%d.PINTYPE_%d", z, 5-i)][0]; pintype.push_back(config_bits[seg.x][seg.y][bitpos.first][bitpos.second] ? '1' : '0'); } bool use_inclk = false; bool use_outclk = false; if (pintype[5-0] == '0') use_inclk = true; if (pintype[5-5] == '1' && pintype[5-4] == '1') use_outclk = true; if (pintype[5-5] == '1' || pintype[5-4] == '1') { if (pintype[5-2] == '1' || pintype[5-3] == '0') use_outclk = true; } std::tuple din0_key(seg.x, seg.y, stringf("io_%d/D_IN_%d", z, 0)); std::tuple din1_key(seg.x, seg.y, stringf("io_%d/D_IN_%d", z, 1)); if (x_y_name_net.count(din0_key) == 0 && x_y_name_net.count(din1_key) == 0) use_inclk = false; std::tuple dout0_key(seg.x, seg.y, stringf("io_%d/D_OUT_%d", z, 0)); std::tuple dout1_key(seg.x, seg.y, stringf("io_%d/D_OUT_%d", z, 1)); if (x_y_name_net.count(dout0_key) == 0 && x_y_name_net.count(dout1_key) == 0) use_outclk = false; if (!use_inclk && !use_outclk) continue; auto cell = make_seg_pre_io(seg.x, seg.y, z); if (seg.name == "io_global/inclk" && use_inclk) { netlist_cell_ports[cell]["INPUTCLK"] = net_name(seg.net); make_inmux(seg.x, seg.y, seg.net, "ClkMux"); } if (seg.name == "io_global/outclk" && use_outclk) { netlist_cell_ports[cell]["OUTPUTCLK"] = net_name(seg.net); make_inmux(seg.x, seg.y, seg.net, "ClkMux"); } if (seg.name == "io_global/cen") { netlist_cell_ports[cell]["CLOCKENABLE"] = net_name(seg.net); make_inmux(seg.x, seg.y, seg.net, "CEMux"); } else { if (netlist_cell_ports[cell]["CLOCKENABLE"] == "") netlist_cell_ports[cell]["CLOCKENABLE"] = "vcc"; } } } } struct make_interconn_worker_t { std::map> net_tree; std::map> seg_tree; std::map seg_parents; std::map porch_segs; std::set target_segs, handled_segs; std::set handled_global_nets; std::map> cell_log; void build_net_tree(int src) { auto &children = net_tree[src]; for (auto &other : net_buffers[src]) if (!net_tree.count(other) && !no_interconn_net.count(other)) { build_net_tree(other); children.insert(other); } for (auto &other : net_routing[src]) if (!net_tree.count(other) && !no_interconn_net.count(other)) { build_net_tree(other); children.insert(other); } } void build_seg_tree(const net_segment_t &src) { std::set queue, targets; std::map distances; std::map reverse_edges; queue.insert(src); std::map> seg_connections; porch_segs[src] = 1; for (auto &it: net_tree) for (int child : it.second) { auto pos = connection_pos.at(std::pair(it.first, child)); std::tuple key_parent(pos.first, pos.second, it.first); std::tuple key_child(pos.first, pos.second, child); seg_connections[x_y_net_segment.at(key_parent)].insert(x_y_net_segment.at(key_child)); const std::string &parent_name = x_y_net_segment.at(key_parent).name; const std::string &child_name = x_y_net_segment.at(key_child).name; if (parent_name.substr(0, 7) == "span12_" || parent_name.substr(0, 5) == "sp12_") if (child_name.substr(0, 6) == "span4_" || child_name.substr(0, 4) == "sp4_") porch_segs[x_y_net_segment.at(key_child)] = 1; } for (int distance_counter = 0; !queue.empty(); distance_counter++) { std::set next_queue; for (auto &seg : queue) distances[seg] = distance_counter; for (auto &seg : queue) { if (seg != src) assert(interconn_src.count(seg) == 0); if (interconn_dst.count(seg)) targets.insert(seg); if (seg_connections.count(seg)) for (auto &child : seg_connections.at(seg)) { if (distances.count(child) != 0 || interconn_src.count(child) != 0) continue; reverse_edges[child] = seg; next_queue.insert(child); } for (int x = seg.x-1; x <= seg.x+1; x++) for (int y = seg.y-1; y <= seg.y+1; y++) { std::tuple key(x, y, seg.net); if (x_y_net_segment.count(key) == 0) continue; auto &child = x_y_net_segment.at(key); if (distances.count(child) != 0) continue; if (porch_segs.count(seg)) porch_segs[child] = porch_segs[seg]+1; reverse_edges[child] = seg; next_queue.insert(child); } } queue.swap(next_queue); } for (auto &trg : targets) { target_segs.insert(trg); seg_tree[trg]; } while (!targets.empty()) { std::set next_targets; for (auto &trg : targets) if (reverse_edges.count(trg)) { seg_tree[reverse_edges.at(trg)].insert(trg); next_targets.insert(reverse_edges.at(trg)); } targets.swap(next_targets); } for (auto &it : seg_tree) for (auto &child : it.second) { assert(seg_parents.count(child) == 0); seg_parents[child] = it.first; } } void create_cells(const net_segment_t &trg) { if (handled_segs.count(trg) || handled_global_nets.count(trg.net)) return; handled_segs.insert(trg); if (seg_parents.count(trg) == 0) { net_assignments[seg_name(trg)] = net_name(trg.net); return; } const net_segment_t *cursor = &seg_parents.at(trg); std::string tn; // Local Mux if (trg.name.substr(0, 6) == "local_") { tn = tname(); netlist_cell_types[tn] = "LocalMux"; netlist_cell_ports[tn]["I"] = seg_name(*cursor); netlist_cell_ports[tn]["O"] = seg_name(trg); cell_log[trg] = std::make_pair(*cursor, "LocalMux"); goto continue_at_cursor; } // Span4Mux if (trg.name.substr(0, 6) == "span4_" || trg.name.substr(0, 4) == "sp4_") { bool horiz = trg.name.substr(0, 6) == "sp4_h_"; int count_length = 0; while (seg_parents.count(*cursor) && cursor->net == trg.net) { horiz = horiz || (cursor->name.substr(0, 6) == "sp4_h_"); cursor = &seg_parents.at(*cursor); count_length++; } if (cursor->net == trg.net) goto skip_to_cursor; count_length = std::min(std::max(count_length, 0), 4); if (max_span_hack) count_length = 4; if (cursor->name.substr(0, 7) == "span12_" || cursor->name.substr(0, 5) == "sp12_") { tn = tname(); netlist_cell_types[tn] = "Sp12to4"; netlist_cell_ports[tn]["I"] = seg_name(*cursor); netlist_cell_ports[tn]["O"] = seg_name(trg); cell_log[trg] = std::make_pair(*cursor, "Sp12to4"); } else if (cursor->name.substr(0, 6) == "span4_") { tn = tname(); netlist_cell_types[tn] = "IoSpan4Mux"; netlist_cell_ports[tn]["I"] = seg_name(*cursor); netlist_cell_ports[tn]["O"] = seg_name(trg); cell_log[trg] = std::make_pair(*cursor, "IoSpan4Mux"); } else { tn = tname(); netlist_cell_types[tn] = stringf("Span4Mux_%c%d", horiz ? 'h' : 'v', count_length); netlist_cell_ports[tn]["I"] = seg_name(*cursor); netlist_cell_ports[tn]["O"] = seg_name(trg); cell_log[trg] = std::make_pair(*cursor, stringf("Span4Mux_%c%d", horiz ? 'h' : 'v', count_length)); } goto continue_at_cursor; } // Span12Mux if (trg.name.substr(0, 7) == "span12_" || trg.name.substr(0, 5) == "sp12_") { bool horiz = trg.name.substr(0, 7) == "sp12_h_"; int count_length = 0; while (seg_parents.count(*cursor) && cursor->net == trg.net) { horiz = horiz || (cursor->name.substr(0, 7) == "sp12_h_"); cursor = &seg_parents.at(*cursor); count_length++; } if (cursor->net == trg.net) goto skip_to_cursor; count_length = std::min(std::max(count_length, 0), 12); if (max_span_hack) count_length = 12; tn = tname(); netlist_cell_types[tn] = stringf("Span12Mux_%c%d", horiz ? 'h' : 'v', count_length); netlist_cell_ports[tn]["I"] = seg_name(*cursor); netlist_cell_ports[tn]["O"] = seg_name(trg); cell_log[trg] = std::make_pair(*cursor, stringf("Span12Mux_%c%d", horiz ? 'h' : 'v', count_length)); goto continue_at_cursor; } // Global nets if (trg.name.substr(0, 10) == "glb_netwk_") { while (seg_parents.count(*cursor) && (cursor->net == trg.net || cursor->name == "fabout")) cursor = &seg_parents.at(*cursor); if (cursor->net == trg.net) goto skip_to_cursor; tn = tname(); netlist_cell_types[tn] = "GlobalMux"; netlist_cell_ports[tn]["I"] = seg_name(*cursor, 3); netlist_cell_ports[tn]["O"] = seg_name(trg); tn = tname(); netlist_cell_types[tn] = "gio2CtrlBuf"; netlist_cell_ports[tn]["I"] = seg_name(*cursor, 2); netlist_cell_ports[tn]["O"] = seg_name(*cursor, 3); tn = tname(); netlist_cell_types[tn] = "ICE_GB"; netlist_cell_ports[tn]["USERSIGNALTOGLOBALBUFFER"] = seg_name(*cursor, 1); netlist_cell_ports[tn]["GLOBALBUFFEROUTPUT"] = seg_name(*cursor, 2); tn = tname(); netlist_cell_types[tn] = "IoInMux"; netlist_cell_ports[tn]["I"] = seg_name(*cursor); netlist_cell_ports[tn]["O"] = seg_name(*cursor, 1); cell_log[trg] = std::make_pair(*cursor, "GlobalMux -> ICE_GB -> IoInMux"); handled_global_nets.insert(trg.net); goto continue_at_cursor; } // Default handler while (seg_parents.count(*cursor) && cursor->net == trg.net) cursor = &seg_parents.at(*cursor); if (cursor->net == trg.net) goto skip_to_cursor; tn = tname(); netlist_cell_types[tn] = "INTERCONN"; netlist_cell_ports[tn]["I"] = seg_name(*cursor); netlist_cell_ports[tn]["O"] = seg_name(trg); cell_log[trg] = std::make_pair(*cursor, "INTERCONN"); goto continue_at_cursor; skip_to_cursor: net_assignments[seg_name(trg)] = seg_name(*cursor); continue_at_cursor: create_cells(*cursor); } static std::string graph_seg_name(const net_segment_t &seg) { std::string str = stringf("seg_%d_%d_%s", seg.x, seg.y, seg.name.c_str()); for (auto &ch : str) if (ch == '/') ch = '_'; return str; } static std::string graph_cell_name(const net_segment_t &seg) { std::string str = stringf("cell_%d_%d_%s", seg.x, seg.y, seg.name.c_str()); for (auto &ch : str) if (ch == '/') ch = '_'; return str; } void show_seg_tree_worker(FILE *f, const net_segment_t &src, std::vector &global_lines) { std::string porch_str = porch_segs.count(src) ? stringf("\\n[P%d]", porch_segs.at(src)) : ""; fprintf(f, " %s [ shape=octagon, label=\"%d %d\\n%s%s\" ];\n", graph_seg_name(src).c_str(), src.x, src.y, src.name.c_str(), porch_str.c_str()); std::vector other_net_children; for (auto &child : seg_tree.at(src)) { if (child.net != src.net) { other_net_children.push_back(child); } else show_seg_tree_worker(f, child, global_lines); global_lines.push_back(stringf(" %s -> %s;\n", graph_seg_name(src).c_str(), graph_seg_name(child).c_str())); } if (!other_net_children.empty()) { for (auto &child : other_net_children) { fprintf(f, " }\n"); fprintf(f, " subgraph cluster_net_%d {\n", child.net); fprintf(f, " label = \"net %d\";\n", child.net); show_seg_tree_worker(f, child, global_lines); } } if (cell_log.count(src)) { auto &cell = cell_log.at(src); global_lines.push_back(stringf(" %s [ label=\"%s\" ];\n", graph_cell_name(src).c_str(), cell.second.c_str())); global_lines.push_back(stringf(" %s -> %s;\n", graph_seg_name(cell.first).c_str(), graph_cell_name(src).c_str())); global_lines.push_back(stringf(" %s -> %s;\n", graph_cell_name(src).c_str(), graph_seg_name(src).c_str())); } } void show_seg_tree(const net_segment_t &src, FILE *f) { fprintf(f, " subgraph cluster_net_%d {\n", src.net); fprintf(f, " label = \"net %d\";\n", src.net); std::vector global_lines; show_seg_tree_worker(f, src, global_lines); fprintf(f, " }\n"); for (auto &line : global_lines) { fprintf(f, "%s", line.c_str()); } } }; void make_interconn(const net_segment_t &src, FILE *graph_f) { make_interconn_worker_t worker; worker.build_net_tree(src.net); worker.build_seg_tree(src); if (verbose) { printf("// INTERCONN %d %d %s %d\n", src.x, src.y, src.name.c_str(), src.net); std::function print_net_tree = [&] (int net, int indent) { printf("// %*sNET_TREE %d\n", indent, "", net); for (int child : worker.net_tree.at(net)) print_net_tree(child, indent+2); }; std::function print_seg_tree = [&] (const net_segment_t &seg, int indent, bool chain) { printf("// %*sSEG_TREE %d %d %s %d\n", indent, chain ? "`" : "", seg.x, seg.y, seg.name.c_str(), seg.net); if (worker.seg_tree.count(seg)) { auto &children = worker.seg_tree.at(seg); bool child_chain = children.size() == 1; for (auto &child : children) print_seg_tree(child, child_chain ? (chain ? indent : indent+1) : indent+2, child_chain); } else { printf("// %*s DEAD_END (!)\n", indent, ""); } }; print_net_tree(src.net, 2); print_seg_tree(src, 2, false); } for (auto &seg : worker.target_segs) { net_assignments[net_name(seg.net)] = seg_name(seg); worker.create_cells(seg); } for (int n : graph_nets) if (worker.net_tree.count(n)) { worker.show_seg_tree(src, graph_f); break; } } void help(const char *cmd) { printf("\n"); printf("Usage: %s [options] input.asc\n", cmd); printf("\n"); printf(" -p \n"); printf(" -P \n"); printf(" provide this two options for correct IO pin names\n"); printf("\n"); printf(" -g \n"); printf(" write a graphviz description of the interconnect tree\n"); printf(" that includes the given net to 'icetime_graph.dot'.\n"); printf("\n"); printf(" -o \n"); printf(" write verilog netlist to the file. use '-' for stdout\n"); printf("\n"); printf(" -r \n"); printf(" write timing report to the file (instead of stdout)\n"); printf("\n"); printf(" -j \n"); printf(" write timing report in json format to the file\n"); printf("\n"); printf(" -d lp1k|hx1k|lp8k|hx8k\n"); printf(" select the device type (default = lp variant)\n"); printf("\n"); printf(" -m\n"); printf(" enable max_span_hack for conservative timing estimates\n"); printf("\n"); printf(" -i\n"); printf(" only consider interior timing paths (not to/from IOs)\n"); printf("\n"); printf(" -t\n"); printf(" print a timing report (based on topological timing\n"); printf(" analysis)\n"); printf("\n"); printf(" -T \n"); printf(" print a timing report for the specified net\n"); printf("\n"); printf(" -c \n"); printf(" check timing estimate against clock constraint\n"); printf("\n"); printf(" -v\n"); printf(" verbose mode (print all interconnect trees)\n"); printf("\n"); exit(1); } int main(int argc, char **argv) { bool print_timing = false; bool interior_timing = false; double clock_constr = 0; std::vector print_timing_nets; int opt; while ((opt = getopt(argc, argv, "p:P:g:o:r:j:d:mitT:vc:")) != -1) { switch (opt) { case 'p': printf("// Reading input .pcf file..\n"); fflush(stdout); read_pcf(optarg); break; case 'P': selected_package = optarg; break; case 'g': graph_nets.insert(atoi(optarg)); break; case 'o': if (!strcmp(optarg, "-")) { fout = stdout; } else { fout = fopen(optarg, "w"); if (fout == nullptr) { perror("Can't open output file"); exit(1); } } break; case 'r': frpt = fopen(optarg, "w"); if (frpt == nullptr) { perror("Can't open report file"); exit(1); } break; case 'j': fjson = fopen(optarg, "w"); if (fjson == nullptr) { perror("Can't open json file"); exit(1); } break; case 'd': device_type = optarg; break; case 'm': max_span_hack = true; break; case 'i': interior_timing = true; break; case 't': print_timing = true; break; case 'T': print_timing_nets.push_back(optarg); break; case 'c': clock_constr = strtod(optarg, NULL); break; case 'v': verbose = true; break; default: help(argv[0]); } } if (optind+1 == argc) { fin = fopen(argv[optind], "r"); if (fin == nullptr) { perror("Can't open input file"); exit(1); } } else help(argv[0]); printf("// Reading input .asc file..\n"); fflush(stdout); read_config(); if (device_type.empty()) { device_type = "lp" + config_device; printf("// Warning: Missing -d parameter. Assuming '%s' device.\n", device_type.c_str()); } if (device_type == "lp1k" || device_type == "hx1k") { if (config_device != "1k") goto device_chip_mismatch; } else if (device_type == "lp8k" || device_type == "hx8k") { if (config_device != "8k") goto device_chip_mismatch; } else { fprintf(stderr, "Error: Invalid device type '%s'.\n", device_type.c_str()); exit(1); } if (0) { device_chip_mismatch: printf("// Warning: Device type '%s' and chip '%s' do not match.\n", device_type.c_str(), config_device.c_str()); fflush(stdout); } printf("// Reading %s chipdb file..\n", config_device.c_str()); fflush(stdout); read_chipdb(); printf("// Creating timing netlist..\n"); fflush(stdout); for (int net : used_nets) for (auto &seg : net_to_segments[net]) make_seg_cell(net, seg); for (int x = 0; x < int(config_tile_type.size()); x++) for (int y = 0; y < int(config_tile_type[x].size()); y++) { auto const &tile_type = config_tile_type[x][y]; if (tile_type == "ramb") { bool cascade_cbits[4] = {false, false, false, false}; bool &cascade_cbit_4 = cascade_cbits[0]; // bool &cascade_cbit_5 = cascade_cbits[1]; bool &cascade_cbit_6 = cascade_cbits[2]; // bool &cascade_cbit_7 = cascade_cbits[3]; std::pair bitpos; for (int i = 0; i < 4; i++) { std::string cbit_name = stringf("RamCascade.CBIT_%d", i+4); if (ramb_tile_bits.count(cbit_name)) { bitpos = ramb_tile_bits.at(cbit_name)[0]; cascade_cbits[i] = config_bits[x][y][bitpos.first][bitpos.second]; } if (ramt_tile_bits.count(cbit_name)) { bitpos = ramt_tile_bits.at(cbit_name)[0]; cascade_cbits[i] = config_bits[x][y+1][bitpos.first][bitpos.second]; } } if (cascade_cbit_4) { std::string src_cell = stringf("ram_%d_%d", x, y+2); std::string dst_cell = stringf("ram_%d_%d", x, y); for (int i = 0; i < 11; i++) { std::string port = stringf("WADDR[%d]", i); if (netlist_cell_ports[src_cell][port] == "") continue; std::string srcnet = netlist_cell_ports[src_cell][port]; std::string tmpnet = tname(); extra_wires.insert(tmpnet); std::string tn = tname(); netlist_cell_types[tn] = "CascadeBuf"; netlist_cell_ports[tn]["I"] = srcnet; netlist_cell_ports[tn]["O"] = tmpnet; netlist_cell_ports[dst_cell][port] = cascademuxed(tmpnet); } } if (cascade_cbit_6) { std::string src_cell = stringf("ram_%d_%d", x, y+2); std::string dst_cell = stringf("ram_%d_%d", x, y); for (int i = 0; i < 11; i++) { std::string port = stringf("RADDR[%d]", i); if (netlist_cell_ports[src_cell][port] == "") continue; std::string srcnet = netlist_cell_ports[src_cell][port]; std::string tmpnet = tname(); extra_wires.insert(tmpnet); std::string tn = tname(); netlist_cell_types[tn] = "CascadeBuf"; netlist_cell_ports[tn]["I"] = srcnet; netlist_cell_ports[tn]["O"] = tmpnet; netlist_cell_ports[dst_cell][port] = cascademuxed(tmpnet); } } } } FILE *graph_f = nullptr; if (!graph_nets.empty()) { graph_f = fopen("icetime_graph.dot", "w"); if (graph_f == nullptr) { perror("Can't open 'icetime_graph.dot' for writing"); exit(1); } fprintf(graph_f, "digraph \"icetime net-segment graph \" {\n"); fprintf(graph_f, " rankdir = \"LR\";\n"); } for (auto &seg : interconn_src) make_interconn(seg, graph_f); if (graph_f) { fprintf(graph_f, "}\n"); fclose(graph_f); } for (auto it : netlist_cell_types) for (auto &port : netlist_cell_ports[it.first]) if (port.second == "") { size_t open_bracket_pos = port.first.find('['); if (open_bracket_pos == std::string::npos) continue; port.second = stringf("dangling_wire_%d", dangling_cnt++); extra_wires.insert(port.second); } if (fout != NULL) { fprintf(fout, "module chip ("); const char *io_sep = ""; for (auto io : io_names) { fprintf(fout, "%s%s", io_sep, io.c_str()); io_sep = ", "; } fprintf(fout, ");\n"); for (int net : declared_nets) fprintf(fout, " wire net_%d;\n", net); for (auto net : extra_wires) fprintf(fout, " wire %s;\n", net.c_str()); for (auto &it : net_assignments) fprintf(fout, " assign %s = %s;\n", it.first.c_str(), it.second.c_str()); fprintf(fout, " wire gnd, vcc;\n"); fprintf(fout, " GND gnd_cell (.Y(gnd));\n"); fprintf(fout, " VCC vcc_cell (.Y(vcc));\n"); for (auto &str : extra_vlog) fprintf(fout, "%s", str.c_str()); for (auto it : netlist_cell_types) { const char *sep = ""; fprintf(fout, " %s ", it.second.c_str()); if (netlist_cell_params.count(it.first)) { fprintf(fout, "#("); for (auto port : netlist_cell_params[it.first]) { fprintf(fout, "%s\n .%s(%s)", sep, port.first.c_str(), port.second.c_str()); sep = ","; } fprintf(fout, "\n ) "); sep = ""; } fprintf(fout, "%s (", it.first.c_str()); std::map> multibit_ports; for (auto port : netlist_cell_ports[it.first]) { size_t open_bracket_pos = port.first.find('['); if (open_bracket_pos != std::string::npos) { std::string base_name = port.first.substr(0, open_bracket_pos); int bit_index = atoi(port.first.substr(open_bracket_pos+1).c_str()); if (int(multibit_ports[base_name].size()) <= bit_index) multibit_ports[base_name].resize(bit_index+1); multibit_ports[base_name][bit_index] = port.second; continue; } fprintf(fout, "%s\n .%s(%s)", sep, port.first.c_str(), port.second.c_str()); sep = ","; } for (auto it : multibit_ports) { fprintf(fout, "%s\n .%s({", sep, it.first.c_str()); sep = ","; const char *sepsep = ""; for (int i = int(it.second.size())-1; i >= 0; i--) { std::string wire_name = it.second[i]; fprintf(fout, "%s%s", sepsep, wire_name.c_str()); sepsep = ", "; } fprintf(fout, "})"); } fprintf(fout, "\n );\n"); } fprintf(fout, "endmodule\n"); } double max_path_delay = 0; if (fjson) fprintf(fjson, "[\n"); if (print_timing || !print_timing_nets.empty()) { TimingAnalysis ta(interior_timing); if (frpt == nullptr) frpt = stdout; else printf("// Timing estimate: %.2f ns (%.2f MHz)\n", ta.global_max_path_delay, 1000.0 / ta.global_max_path_delay); fprintf(frpt, "\n"); fprintf(frpt, "icetime topological timing analysis report\n"); fprintf(frpt, "==========================================\n"); fprintf(frpt, "\n"); fprintf(frpt, "Warning: This timing analysis report is an estimate!\n"); if (max_span_hack) fprintf(frpt, "Info: max_span_hack is enabled: estimate is conservative.\n"); fprintf(frpt, "\n"); for (auto &n : print_timing_nets) max_path_delay = std::max(max_path_delay, ta.report(n)); if (print_timing) max_path_delay = ta.report(); } else { TimingAnalysis ta(interior_timing); printf("// Timing estimate: %.2f ns (%.2f MHz)\n", ta.global_max_path_delay, 1000.0 / ta.global_max_path_delay); max_path_delay = ta.report(); } if (clock_constr > 0) { printf("// Checking %.2f ns (%.2f MHz) clock constraint: ", 1000.0 / clock_constr, clock_constr); if (max_path_delay <= 1000.0 / clock_constr) { printf("PASSED.\n"); } else { printf("FAILED.\n"); return 1; } } if (fjson) { if (!json_firstentry) fprintf(fjson, " ]\n"); fprintf(fjson, "]\n"); } return 0; } fpga-icestorm-0~20160913git266e758/icetime/mktest.py000066400000000000000000000243421276746530600216770ustar00rootroot00000000000000#!/usr/bin/env python3 import sys, os, re, shutil import numpy as np max_span_hack = True pins = np.random.permutation(""" 1 2 3 4 7 8 9 10 11 12 19 22 23 24 25 26 28 29 31 32 33 34 37 38 41 42 43 44 45 47 48 52 56 58 60 61 62 63 64 73 74 75 76 78 79 80 81 87 88 90 91 95 96 97 98 101 102 104 105 106 107 112 113 114 115 116 117 118 119 120 121 122 134 135 136 137 138 139 141 142 143 144 """.split()) io_names = None mode = sys.argv[1] with open("%s.v" % sys.argv[1], "w") as f: if mode == "test0": io_names = [ "clk", "i0", "o0", "o1", "o2" ] print("module top(input clk, i0, output o0, o1, o2);", file=f) print(" reg [31:0] state;", file=f) print(" always @(posedge clk) state <= ((state << 5) + state) ^ i0;", file=f) print(" assign o0 = ^state, o1 = |state, o2 = state[31:16] + state[15:0];", file=f) print("endmodule", file=f) if mode == "test1": io_names = [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3" ] print("module top(input clk, i0, i1, i2, i3, output o0, o1, o2, o3);", file=f) print(" reg [15:0] din, dout;", file=f) print(" always @(posedge clk) din <= {din, i3, i2, i1, i0};", file=f) print(" always @(posedge clk) dout <= din + {din[7:0], din[15:8]};", file=f) print(" assign {o3, o2, o1, o0} = dout >> din;", file=f) print("endmodule", file=f) if mode == "test2": io_names = [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3" ] print(""" module top(input clk, i0, i1, i2, i3, output reg o0, o1, o2, o3); reg [7:0] raddr, waddr, rdata, wdata; reg [7:0] memory [0:255]; always @(posedge clk) begin case ({i0, i1, i2}) 0: raddr <= {raddr, i3}; 1: waddr <= {waddr, i3}; 2: wdata <= {wdata, i3}; 3: rdata <= memory[raddr]; 4: memory[waddr] <= wdata; 5: {o0, o1, o2, o3} <= rdata[3:0]; 6: {o0, o1, o2, o3} <= rdata[7:4]; endcase end endmodule """, file=f) if mode == "test3": io_names = [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3", "o4" ] print(""" module top(input clk, i0, i1, i2, i3, output reg o0, o1, o2, o3, o4); reg [9:0] raddr, waddr, rdata, wdata; reg [9:0] memory [0:1023]; always @(posedge clk) begin case ({i0, i1, i2}) 0: raddr <= {raddr, i3}; 1: waddr <= {waddr, i3}; 2: wdata <= {wdata, i3}; 3: rdata <= memory[raddr]; 4: memory[waddr] <= wdata; 5: rdata <= memory[waddr]; 6: {o0, o1, o2, o3, o4} <= rdata[4:0]; 7: {o0, o1, o2, o3, o4} <= rdata[9:5]; endcase end endmodule """, file=f) if mode == "test4": io_names = [ "clk", "i", "s", "o" ] print(""" module top(input clk, i, s, output reg o); reg re1, rclke1, we1, wclke1; reg [7:0] raddr1, waddr1; reg [15:0] rdata1, wdata1, mask1; wire [15:0] rdata1_unreg; reg re2, rclke2, we2, wclke2; reg [7:0] raddr2, waddr2; reg [15:0] rdata2, wdata2, mask2; wire [15:0] rdata2_unreg; always @(posedge clk) begin o <= rdata1[15]; {rdata1, rdata2} <= {rdata1, rdata2} << 1; {raddr1, waddr1, wdata1, mask1, re1, rclke1, we1, wclke1, raddr2, waddr2, wdata2, mask2, re2, rclke2, we2, wclke2} <= ({raddr1, waddr1, wdata1, mask1, re1, rclke1, we1, wclke1, raddr2, waddr2, wdata2, mask2, re2, rclke2, we2, wclke2} << 1) | i; if (s) begin rdata1 <= rdata1_unreg; rdata2 <= rdata2_unreg; end end SB_RAM40_4K mem1 ( .RDATA(rdata1_unreg), .RCLK(clk), .RCLKE(rclke1), .RE(re1), .RADDR(raddr1), .WCLK(clk), .WCLKE(wclke1), .WE(we1), .WADDR(waddr1), .MASK(mask1), .WDATA(wdata1) ); SB_RAM40_4K mem2 ( .RDATA(rdata2_unreg), .RCLK(clk), .RCLKE(rclke2), .RE(re2), .RADDR(raddr1), // <- cascade .WCLK(clk), .WCLKE(wclke2), .WE(we2), .WADDR(waddr1), // <- cascade .MASK(mask2), .WDATA(wdata2) ); endmodule """, file=f) with open("%s.pcf" % sys.argv[1], "w") as f: for i, name in enumerate(io_names): print("set_io %s %s" % (name, pins[i]), file=f) with open("%s.ys" % sys.argv[1], "w") as f: print("echo on", file=f) print("read_verilog -lib cells.v", file=f) print("read_verilog %s_ref.v" % sys.argv[1], file=f) print("read_verilog %s_out.v" % sys.argv[1], file=f) print("prep", file=f) print("equiv_make top chip equiv", file=f) print("# check -assert", file=f) print("cd equiv", file=f) print("script %s.lc" % sys.argv[1], file=f) print("rename -hide w:N_*", file=f) print("equiv_struct -maxiter 100", file=f) print("opt_clean -purge", file=f) print("write_ilang %s.il" % sys.argv[1], file=f) print("equiv_status -assert", file=f) assert os.system("bash ../icefuzz/icecube.sh %s.v" % sys.argv[1]) == 0 os.rename("%s.v" % sys.argv[1], "%s_in.v" % sys.argv[1]) if False: assert os.system("python3 ../icebox/icebox_explain.py %s.asc > %s.ex" % (sys.argv[1], sys.argv[1])) == 0 with open("%s_ref.v" % sys.argv[1], "w") as f: for line in open("%s.vsb" % sys.argv[1], "r"): if re.match(r" *defparam .*\.(IO_STANDARD|PULLUP|INIT_.|WRITE_MODE|READ_MODE)=", line): continue line = line.replace(" Span4Mux_s0_h ", " Span4Mux_h4 " if max_span_hack else " Span4Mux_h0 ") line = line.replace(" Span4Mux_s1_h ", " Span4Mux_h4 " if max_span_hack else " Span4Mux_h1 ") line = line.replace(" Span4Mux_s2_h ", " Span4Mux_h4 " if max_span_hack else " Span4Mux_h2 ") line = line.replace(" Span4Mux_s3_h ", " Span4Mux_h4 " if max_span_hack else " Span4Mux_h3 ") line = line.replace(" Span4Mux_h ", " Span4Mux_h4 " if max_span_hack else " Span4Mux_h4 ") line = line.replace(" Span4Mux_s0_v ", " Span4Mux_v4 " if max_span_hack else " Span4Mux_v0 ") line = line.replace(" Span4Mux_s1_v ", " Span4Mux_v4 " if max_span_hack else " Span4Mux_v1 ") line = line.replace(" Span4Mux_s2_v ", " Span4Mux_v4 " if max_span_hack else " Span4Mux_v2 ") line = line.replace(" Span4Mux_s3_v ", " Span4Mux_v4 " if max_span_hack else " Span4Mux_v3 ") line = line.replace(" Span4Mux_v ", " Span4Mux_v4 " if max_span_hack else " Span4Mux_v4 ") line = line.replace(" Span4Mux ", " Span4Mux_v4 " if max_span_hack else " Span4Mux_v4 ") line = line.replace(" Span12Mux_s0_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h0 ") line = line.replace(" Span12Mux_s1_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h1 ") line = line.replace(" Span12Mux_s2_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h2 ") line = line.replace(" Span12Mux_s3_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h3 ") line = line.replace(" Span12Mux_s4_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h4 ") line = line.replace(" Span12Mux_s5_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h5 ") line = line.replace(" Span12Mux_s6_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h6 ") line = line.replace(" Span12Mux_s7_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h7 ") line = line.replace(" Span12Mux_s8_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h8 ") line = line.replace(" Span12Mux_s9_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h9 ") line = line.replace(" Span12Mux_s10_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h10 ") line = line.replace(" Span12Mux_s11_h ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h11 ") line = line.replace(" Span12Mux ", " Span12Mux_h12 " if max_span_hack else " Span12Mux_h12 ") line = line.replace(" Span12Mux_s0_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v0 ") line = line.replace(" Span12Mux_s1_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v1 ") line = line.replace(" Span12Mux_s2_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v2 ") line = line.replace(" Span12Mux_s3_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v3 ") line = line.replace(" Span12Mux_s4_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v4 ") line = line.replace(" Span12Mux_s5_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v5 ") line = line.replace(" Span12Mux_s6_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v6 ") line = line.replace(" Span12Mux_s7_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v7 ") line = line.replace(" Span12Mux_s8_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v8 ") line = line.replace(" Span12Mux_s9_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v9 ") line = line.replace(" Span12Mux_s10_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v10 ") line = line.replace(" Span12Mux_s11_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v11 ") line = line.replace(" Span12Mux_v ", " Span12Mux_v12 " if max_span_hack else " Span12Mux_v12 ") f.write(line) assert os.system("yosys -qp 'select -write %s.lc t:LogicCell40' %s_ref.v" % (sys.argv[1], sys.argv[1])) == 0 assert os.system(r"sed -i -r 's,.*/(.*)LC_(.*),equiv_add -try -cell \1LC_\2_gold lc40_\2_gate,' %s.lc" % sys.argv[1]) == 0 os.remove("%s.bin" % sys.argv[1]) os.remove("%s.vsb" % sys.argv[1]) os.remove("%s.glb" % sys.argv[1]) os.remove("%s.psb" % sys.argv[1]) os.remove("%s.sdf" % sys.argv[1]) shutil.rmtree("%s.tmp" % sys.argv[1]) fpga-icestorm-0~20160913git266e758/icetime/show.sh000066400000000000000000000012621276746530600213260ustar00rootroot00000000000000#!/bin/bash set -ex yosys -p ' cd equiv equiv_mark select -write equiv_graph.segs w:seg_*_gate a:equiv_region!=0 %i show -prefix equiv_graph -format dot a:equiv_region!=0 %co2 a:equiv_region!=0 %ci2 ' $1.il ./icetime -P tq144 -p $1.pcf $1.asc $( sed 's,_gate$,,; s,.*_,-g ,;' < equiv_graph.segs ) > /dev/null { egrep -v '^}' icetime_graph.dot egrep -v '^(digraph|label=|})' equiv_graph.dot for seg in $( sed 's,equiv/,,' equiv_graph.segs ); do n=$( awk "/$seg/ { print \$1; }" equiv_graph.dot ) s=$( echo $seg | sed 's,_[0-9]*_gate$,,' ) echo " $n:s -> $s:n [style=bold];" done echo "}" } > $1.dot rm -f equiv_graph.segs rm -f equiv_graph.dot rm -f icetime_graph.dot fpga-icestorm-0~20160913git266e758/icetime/timings.py000066400000000000000000000032131276746530600220340ustar00rootroot00000000000000#!/usr/bin/env python3 import re print("// auto-generated by timings.py from ../icefuzz/timings_*.txt") def timings_to_c(chip, f): print("") print("double get_delay_%s(std::string cell_type, std::string in_port, std::string out_port)" % chip) print("{") in_cell = False for line in f: fields = line.split() if len(fields) == 0: continue if fields[0] == "CELL": if in_cell: print(" }") print(" if (cell_type == \"%s\") {" % fields[1]) in_cell = True if fields[0] == "SETUP": inport = fields[1].split(":")[1] delay = max([0 if s == "*" else float(s) / 1000 for s in fields[3].split(":")]) print(" if (in_port == \"%s\" && out_port == \"*setup*\") return %.5f;" % (inport, delay)) if fields[0] == "IOPATH": if fields[1].startswith("posedge:") or fields[1].startswith("negedge:"): fields[1] = "*clkedge*" delay = max([0 if s == "*" else float(s) / 1000 for s in fields[3].split(":") + fields[4].split(":")]) print(" if (in_port == \"%s\" && out_port == \"%s\") return %.5f;" % (fields[1], fields[2], delay)) if in_cell: print(" }") print(" if (in_port == \"*clkedge*\"|| out_port == \"*setup*\") return 0;") print(" fprintf(stderr, \"Unable to resolve delay for path %s -> %s in cell type %s!\\n\", in_port.c_str(), out_port.c_str(), cell_type.c_str());") print(" exit(1);") print("}") for db in "lp1k lp8k hx1k hx8k".split(): with open("../icefuzz/timings_%s.txt" % db, "r") as f: timings_to_c(db, f);