pax_global_header 0000666 0000000 0000000 00000000064 11454012162 0014506 g ustar 00root root 0000000 0000000 52 comment=8d51d9477995f852d4dd50ee8797826cf78c2fa7
AUTHORS 0000664 0000000 0000000 00000000636 11454012162 0012127 0 ustar 00root root 0000000 0000000 Gnucap is primarily the work of Albert Davis.
Here is a list of some of the contributors who have contributed more
than a bug report:
Dan McMahill - "autoconf" interface, NetBSD package
Stuart Brorson - configuration mods
Hamish Moffatt - Debian package
Telford Tendys - documentation and convergence
Dmitry Nadezhin - "electric" interface
Simon Hoffe - Command line editing and history
COPYING 0000664 0000000 0000000 00000104513 11454012162 0012111 0 ustar 00root root 0000000 0000000 GNU GENERAL PUBLIC LICENSE
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.
ChangeLog 0000664 0000000 0000000 00000112250 11454012162 0012625 0 ustar 00root root 0000000 0000000 Gnucap revision history
------------------------------------------------------------------
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Gnucap 0.34 release notes (02/01/2004)
This is a bug fix and compatibility release.
1. Fix bug causing incorrect interpolation of backwards tables.
2. Fix tanh overflow bug.
3. Fix some parsing bugs.
4. Fix occasional "double load" bug.
5. Fix AC sweep with one point.
6. Transient start time really works.
7. Fix occasional assert fail after option short is changed.
8. Fix memory leak resulting from failure to delete unused common.
9. Fix a Z probe bug that sometimes gave wrong answers.
10. Fix a limiting bug that sometimes caused non-convergence.
11. Configure handles isnan.
12. Improvements to logic initialization. It is still not correct.
------------------------------------------------------------------
Gnucap 0.33 release notes (01/12/2003)
This is a bug fix and compatibility release.
0.32 was not widely distributed due to password problems and a heavy
work load, so the release notes are repeated after the current ones.
New features:
1. Add inductance probes, like capacitor.
Bug fixes:
1. Fix xprobe duplicate default arg bug - shows in g++3.2.
2. Fix bug that sometimes caused a crash when changing a model after
analysis.
3. Fix bug that caused an assert to fail (debug build) after removing
a probe from an element.
4. Fix a dumb typo hack bug ddHAS_READLINE. Now history and command
line editing really works. It was working, but somehow the hack
slipped into the release code.
------------------------------------------------------------------
Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
------------------------------------------------------------------
Gnucap 0.31 release notes (03/25/2002)
The most significant changes are the BJT model and "binning".
New features:
1. BJT model.
2. "Binning" for all MOS models.
3. Internal element: non-quasi-static poly-capacitor. (needed by BJT).
4. Enhancements to the data structures and model compiler to support
binning in general.
5. A line prefixed by "*>" is not ignored, in spite of the fact that
"*" usually begins a comment. This is a deliberate incompatibility
with Spice. If you prefix a line by "*>" it will be interpreted as a
non-comment in Gnucap, but a comment in Spice.
6. Circuit line prefixes of ">" and command prefixes of "-->" are
ignored. This is so you can copy and paste whole lines, without
having to manually remove the prompt string.
Changes that may or may not be improvements.
1. It is not the default to include stray resistance in device models.
The option "norstray" will revert to the old behavior. This is only a
change to the default value of "rstray".
Significant internal changes:
1. The internal element non-quasi-static poly-capacitor actually
works. It is used by the BJT model, and will eventually be used by
MOSFET models.
2. There are now two poly_g devices: "CPOLY_G" and "FPOLY_G". There
are interface differences that impact modeling. Previously, there was
only one, which is equivalent to the "FPOLY_G".
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
General comments:
The new BJT model seems to pass the CircuitSim90 test cases as well as
anything else, except where a missing feature prevented it from
working. A few files would not run because of named nodes. One file
(ring11) failed completely. This file also has MOSFETs, with level 2
models. The MOS level 2 model is not as robust as the BJT. I believe
the problem is due to the voltage sync bug that still impacts the MOS
model.
Most of the models have has a reasonable amount of testing in DC, but
inadequate testing in AC and transient. The BJT model has had more
testing than the others in AC and transient. All differences
(relative to other simulators) that were observed can be attributed to
differences in transient step size control or tolerance checking.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
------------------------------------------------------------------
GNUCAP 0.30 release notes (10/29/2001)
The primary effort has been to finish the model compiler, to the point
where it can handle most modeling issues. The second change is to
re-release as "gnucap", and add some configuration features to be more
consistent with other GNU software.
New features:
1. More complete model compiler.
2. "./configure" makes compiling more like other GNU software.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
3. Configure still doesn't handle everything.
4. The model compiler still requires too much raw coding.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
------------------------------------------------------------------
ACS 0.29 release notes (06/30/2001)
The primary effort has been to implement IBIS, which is still not
done. The changes here are mostly infrastructure changes needed to
support IBIS.
New features:
1. "Fit" function has choice of fit order and extrapolation. You can
have order 0, 1, 2, or 3.
2. "Posy" has even and odd options, to determine what happens in the
negative region.
3. Modelgen improvements. It now is useful for the whole device,
sometimes. It now handles probes and the device side of the model.
The diode uses it completely. There are still a few missing features
needed for the MOSFET and BJT.
4. Spice-3 compatible semiconductor resistor and capacitor.
5. "Table" model statement.
Improvements, bug fixes, etc.
1. Option "numdgt" really works.
2. Better error messages from modelgen.
3. Code changes for optimization of commons. This should reduce
memory use, sometimes, by sharing commons. Common sharing is still
not fully implemented.
4. Fix two bugs that sometimes caused problems after a "modify" or on
a "fault".
5. Better handling of "vmin" and "vmax". It should be much less
likely that limiting causes convergence to a nonsense result.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. On some systems, you will get a warning from the linker that "the
use of 'tmpnam' is dangerous". You can ignore this warning.
------------------------------------------------------------------
ACS 0.28 release notes (09/05/2000)
New features:
1. New probes: diode G, mos IBD, IBS, GBD, GBS.
2. New options: "floor" and "vfloor". (Floor was in the manual, but
not in the simulator.)
Improvements, bug fixes, etc.
1. There is a change to the way behavioral modeling conditionals are
handled. It should now be 100% compatible with SPICE, considering the
subset that duplicates SPICE. There are still significant extensions
beyond SPICE, particularly that you can have behavioral resistors,
capacitors, inductors, etc.
2. Parameter default calculations are now done in a manner consistent
with Spice 3f5. Previously, it was supposedly consistent with Spice
2g6.
3. A bug in calculation of threshold voltage of the level 6 model, for
P channel devices, has been fixed.
4. A bug in calculation of Meyer capacitances when the device is
reversed has been fixed. This bug sometimes caused a discontinuity at
vds=0.
5. I have added some smoothing to the Meyer mos capacitor models.
This improves convergence. The down side is that sometimes the
answers are different. It is probably a little better, when
considering closeness to reality, but it is still Meyer's model.
6. MOSFET parasitic diodes are now the same as those used in Spice.
7. There are subtle changes in the diode model. I think this usually
improves convergence.
8. Charge calculation in Meyer capacitors and diode capacitiors is now
supposedly Spice 3 compatible.
9. An error in BSIM3 scaling has been fixed.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. A bad setting of "vmax" and "vmin" can lead to convergence to a
nonsense result. It is not as bad now as it used to be.
------------------------------------------------------------------
ACS 0.27 release notes (06/03/2000)
New features:
1. BSIM3 model, DC.
They work for AC and transient analysis, but only the DC effects
actually work. The next release should have the charge effects. For
now, it fakes it with Meyer's model.
2. A first cut at a model compiler, to aid in development of new
models. Models are described in a ".model" file, which is processed
to automatically generate the ".h" and ".cc" files. This version
fully handles the ".model" statement part of it, but leaves the device
and common sections the old way. Eventually, the entire process will
be automated. The old way still works.
3. "Fit" behavioral modeling function, which fits a curve to a set of
data. You can specify the order of the fit, which is piecewise
polynomials. For now, the order may be 1 (linear, like PWL) or 3
(cubic splines). You may also specify the boundary consitions.
4. More probes.
Some things that are partially implemented:
1. Internal element: non-quasi-static poly-capacitor. It is needed by
the BSIM3 and EKV models. Eventually, it will be available as a
netlist item, but not yet.
Bug fixes:
1. PWL could fail if there were duplicate points at the beginning. It
still does, but gives a reasonable error message.
2. Some "dot commands" were ignored if there were spaces before the
dot. This was particularly annoying if the line was supposed to be
".end" which should make it exit. It didn't, leaving it in
interactive mode, a major annoyance in a script.
Other improvements:
1. There is a change to the way integration in capacitors is done. It
is now strictly based on charge (i = dq/dt). The old version was
based on capacitance (i = C * dv/dt) which is strictly incorrect. The
dC/dt term was missing (i = C * dv/dt + v * dC/dt). This is a
non-issue when C is constant.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. The command line is a little different. In the old version,
"acs file" would run it, and whether it exited or not depended on
whether there was an ".end" line. Now, by default, it just loads the
file in preparation for interactive use. If you want batch mode, say
"acs -b file".
2. The regression suite is included in the standard distribution.
Changes that are not really improvements:
1. Due to the model compiler, the build process is a little more
complicated. To do a complete build, you must build the model
compiler first, then the simulator. If you are not making any new
models, you can probably get away with just building the simulator.
This will change in a future release.
Bugs:
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
------------------------------------------------------------------
ACS 0.26 release notes (02/02/2000)
New features:
1. BSIM1, BSIM2 models -- DC only.
They work for AC and transient analysis, but only the
DC effects actually work. The next release should
have the charge effects.
2. New elements:
trans-capacitor
voltage controlled capacitor
voltage controlled conductance
voltage controlled resistor
This is a side effect of the BSIM work.
3. Optional new syntax, with type first so component labels can start
with any letter, and the choice of components is no longer limited by
the 26 letters. This was necessary for a clean syntax
for #2.
4. Some new parameters on existing devices, also a side
effect of the BSIM work.
5. The manual in HTML form. The manual source is still in LaTeX,
which can be used to generate HTML, PDF, Postscript, or many other
formats.
Bug fixes:
1. An error causing truncation error to be underestimated has been fixed.
Other improvements:
1. MOSFET model evaluation is a little faster, due to use of one of
the new elements to replace several old ones. I have seen 40%, but
20% is more likely. The improvement is most evident on busy circuits,
where the ACS speed enhancements based on latency exploitation
contribute more overhead than their value, that is .. the type of
circuit that has run faster in Spice than ACS.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. Truncation error based step control is disabled when Euler's method
is selected. The justification for this is that the reason for
selecting Euler's method is to avoid the artifacts of high order
methods on "stiff" poles. Without this change, a "stiff" pole would
cause an unreasonably small step size. This did not appear to be much
of a problem in the old release because the use of an incorrect
formula for estimating truncation error. A "stiff" pole is one that
has a response so fast it can be thought of as instantaneous.
2. The "help" command, with its 4 year old help file, has been
removed. The concept is really obsolete. With the HTML form of the
manual, a full online manual is a better replacement.
------------------------------------------------------------------
ACS 0.25 release notes (11/04/99)
New features:
None!
Bug fixes:
1. A name conflict that caused compile to fail with gcc 2.95 has been
fixed.
2. A problem that caused switches to lose state when a simulation is
stopped and restarted when a switch is in transition has been fixed.
3. Two unrelated problems with transmission lines have been fixed.
(Short lines and lines in subcircuits.)
Changes that may or may not be improvements:
1. Several queues have been added, to manage model evaluation
scheduling. This is part of work on multi-rate and mixed-mode
simulation, and it replaces the traditional bypass scheme. In this
release, probably the only noticeable difference will be that it runs
a little faster.
Known bugs:
1. The help file has not been updated for 4 years.
------------------------------------------------------------------
ACS 0.24 release notes (08/21/99)
New features:
1. Enhanced (now documented) behavioral modeling.
2. Transmission line in transient analysis.
3. More documentation of internals.
4. Better batch mode error handling.
Bug fixes:
1. Control-C trap works.
2. A bug that could cause a crash when a device had an improper number
of nodes has been fixed. It now issues a warning, and grounds the
unspecified nodes.
3. A bug that could cause a crash when a model or subcircuit is
deleted then accessed has been fixed.
4. A scoping bug that sometimes put subckt parts in the root circuit
has been fixed.
5. A bug in "fanout" that listed internal subckt nodes incorrectly has
been fixed.
Changes that may or may not be improvements:
1. "Make2" files for some systems have been removed. These have not
been tested in years, and ACS and the compilers have both evolved
significantly, so any portability patches that old are probably
completely wrong now.
Known bugs:
1. The help file has not been updated for 4 years.
------------------------------------------------------------------
ACS 0.23 release notes (06/15/99)
New features:
1. Level 6 mos model.
2. HSpice style PWL and POLY(1).
3. "Table" behavioral modeling function.
4. Mixed-mode digital initialization.
The bug fixes:
1. The alarm range worked backwards, now fixed.
2. Keep track of commons better.
3. Improved mixed-mode simulation. It still has not been tested as
well as I would like, but is better. Digital initialization works
now.
4. Another case of "zero time step" has been fixed. This one was
relatively benign, in that it only caused a single extra full
evaluation, with immediate recovery to a normal step size.
5. "Z" probe gave wrong results when probing a voltage source.
Other improvements: (?)
1. Some subtractions now de-noise the result, eliminating the tiny
numbers that result from subtracting two nearly equal numbers. The
threshold can be set by the option "roundofftol". It is best left set
at 1e-13. This improves speed slightly because 0 will prevent a
matrix reload, but any non-zero number will not. It improves
convergence slightly because the tiny numbers (which result from
numerical problems) tend to cause further numerical problems. These
tiny numbers are an artifact of the machine math, and vary depending
on optimization and machine implementation details.
2. MOS temperature effects are computed at run time, instead of at
load time, so you can change the temperature after loading and get
correct results.
3. The options for integration method have changed, and are more
flexible. The default is still trapezoidal, but that may change in a
future release. You can specify the mode individually for capacitors
and inductors. The information is in the data structure for all
components, but it isn't always parsed. A future release will let you
specify it by component or by model. The names are Spectre
compatible, not Spice compatible, because it is more flexible. The
Spice names are accepted, but may not act the same as they do in
Spice. Choices are: unknown, euler, euleronly, trap, traponly.
Options accepted and coerced into something else are: gear2,
gear2only, trapgear, trapeuler. In general, gear is treated as euler,
and each element will use either euler or trap. The device choice
wins over the option command choice, but "only" wins over non-only.
4. Logic device syntax is changed. There are two more nodes, so
power, ground, and enable are passed in. Power and enable are not
used (except possibly in subckt models) but are required for
consistency.
5. In many (not all) cases, arbitrary limits, due to fixed size
arrays, have been removed.
6. More rigorous testing. I actually have a regression suite now. It
is still not rigorous enough.
7. More rigorous convergence criteria. This should solve some of the
false convergence problems. ACS convergence criteria has always been
more rigorous than Spice.
The cosmetic changes:
1. Convert most containers to STL.
2. Complete migration to the "common" tree, and eliminating reference
to the old C "x" structure extensions.
3. Rearrangement of MOS model hierarchy, to make it easier to install
other models. (BSIM family is coming.)
------------------------------------------------------------------
ACS 0.22 release notes (10/16/98)
This release contains a few bug fixes, and a few cosmetic changes to the
code.
The bug fixes:
1. Fixes convergence failures in circuits with linear inductors,
linear mutual inductors, and linear current controlled sources.
2. Fixes a bypass problem, which shows as transient analysis failure
with the message "very backward time step".
3. Failed assertion on switch.
The cosmetic changes:
1. The "OMSTREAM" class, as a step in migrating the i/o to C++ style.
2. A cleaner event queue, using a generic heap class.
That's really all. I have not been actively working on ACS, mostly
due to employment at a semiconductor company in their "corporate CAD"
department. This will change soon, because my new employer (a CAD
tool vendor) says it is ok to work on ACS.
------------------------------------------------------------------
ACS 0.21 release notes (03/30/96)
There are several changes, most of which are only visible in subtle
ways from the outside.
1. The code is more conformant with the upcoming standard, particularly
in the use of complex, templates, lifetime of temporaries, and for
scope. This should fix problems compiling with g++ 2.7.
2. Element commons are freed properly.
3. The manner in which elements are loaded into the matrix is
different, and should be faster for large circuits with latency.
Model bypass is more complete, because it is no longer necessary
to do anything with a latent model. It makes little difference
for small circuits, and circuits that are mostly active. Speed
gains on small circuits are offset by #4.
4. The bypass criteria are more strict. It was possible to get
incorrect results through interaction between model evaluation
bypass and iteration damping. This release will not bypass anything
when damping is in effect. There is a slight speed penalty.
5. Logic devices work even when there is no analog model. The bug
causing a failure in this case has been fixed. The "bug" (that
could in a twisted sense be called a feature) that leads to random
mapping on start-up is still there. The logic model still needs
work.
6. The code is somewhat more object-oriented. Some classes have
been changed to be more general.
------------------------------------------------------------------
ACS 0.20 release notes (11/22/95)
This release adds the level-3 MOSFET model. It is Spice compatible.
Actually, it was there a long time ago but was removed because it
didn't work correctly. This one has been tested and seems to match
Spice results, and have convergence characteristics a little better
than Spice 2g6. Like the level 1 and 2 models, only Meyer's
capacitance model is implemented. (like Spice 3).
------------------------------------------------------------------
ACS 0.19 release notes (10/31/95)
This release offers "improved" convergence.
Several new options have been added to control iteration damping.
In some cases, the program will take a partial step in an attempt
to tame the wild fluctuations that can occur during iteration with
Newton's method. This version appears to be considerably more
robust than Spice 2g6. Several test circuits that fail to converge
on Spice do converge on ACS. The cost of this is sometimes slower
convergence. It generally takes about 2 more iterations per step
than the previous version. This can be turned off, using the
"dampstrategy" option at a slight cost in robustness. See the
manual on the options command for more information.
------------------------------------------------------------------
ACS 0.18 release notes (05/12/95)
This release offers improved memory management and exception
handling, primarily aimed at MSDOS systems.
Bug fixes:
1. For all ... Out of memory exceptions are properly trapped.
Version 0.17 would crash if it ran out of memory. Now you get a
reasonable message. It was only a real problem on MSDOS systems.
2. MSDOS floating point exceptions are trapped. In 0.17, underflow
exceptions and null floating point exceptions could sometimes cause
an abort. I don't know why, but the 80287 can generate a null
exception when apparently nothing is wrong.
3. MSDOS only: Evade underflow in exp(). A large negative argument
to exp can give bogus results. This was a known (to me) in Microsoft
C 5.1. Apparently Borland has the same behavior. It may be a
hardware problem. The fix is to not call exp with an argument
beyond -200, and return 0 instead.
4. Don't use "-fast-math" with g++. (Makefile change). It doesn't
make any difference in speed, and it sometimes causes problems,
particularly the one in #3 above.
Performance improvements:
1. Most elements no longer store values from the past. Only
inductors and capacitors do. This means that some probes are no
longer available. Some other data has been moved to improve memory
usage. This change increases the capacity of the MSDOS version by
about 10 transistors. Unix systems will swap less.
Other visible changes:
1. The method of attaching models to devices has been changed, to
improve maintainability. There are a few noticeable side effects.
a. The default models -d-, -n- are no longer available. These were
not documented.
b. Model names must now be unique. If you have a diode model named
"foo", you may not also have a mosfet model named "foo".
c. A diode can reference a mosfet model. The diode will be equivalent
to the source-bulk diode in the mosfet. This is a byproduct of
using C++ derived classes. The mosfet model is derived from the
diode model.
2. Exception handling in batch mode is different. It is still not
right.
------------------------------------------------------------------
ACS 0.17 release notes (04/21/95)
The primary difference in this release is reorganization and C++.
A side benefit is that it is slightly faster, and uses slightly
less memory. (The program is bigger, but it stores data more
efficiently, for a net improvement.) It is a transitional release,
with some of the code still in C. I hope to have a full C++ version
this summer.
Bug fixes:
1. Voltage source (vs, vcvs, ccvs) probes (current, power, etc.)
now really work.
2. Fixed bug that caused strange results with mutual inductance
after other parts of the circuit are changed.
3. Fixed memory leak in subcircuits and complex devices.
4. Fixed bug that caused a crash when probed elements were deleted.
------------------------------------------------------------------
ACS 0.16 release notes (12/10/94)
New features:
1. New components: current controlled switch, current controlled
current source, current controlled voltage source. Any simple two
terminal element (not a diode) can be used as a probe, not just
a voltage source.
2. Diode transit time parameter works.
3. Mutual inductance. The coupled coils must be linear. Only
pairs of coupled inductors are supported in this release. A future
release will probably support multiply coupled inductors.
Bug fixes:
1. Continuing a transient analysis now works as documented.
------------------------------------------------------------------
ACS 0.15 release notes (07/31/94)
Version 0.15 is supposed to be a minimal bug fix release to 0.14,
but does have one new component.
1. Some additional ports are supported, including VMS. An HP port
is supplied as a user contribution, but I have not tested it.
2. New component: voltage controlled switch. Spice-3 compatible.
3. Fixed bug that caused unpredictable behavior (usually loss of
a probe, sometimes a crash) after replacing a component.
4. Fixed bug that caused incorrect evaluation and initialization
of logic devices when there is no analog model.
5. Fixed a bug in truncation error control that sometimes caused
it to become a no-op. It still seems to usually work the same as
Spice, except that ACS will actually use at least the time steps
you ask for. Spice will pick all the steps and interpolate for
the points you ask for. This will usually cause ACS to use more
time steps than Spice, hence often slower simulations.
6. Fixed another bug in truncation error that sometimes caused a
divide by zero.
------------------------------------------------------------------
ACS 0.14 release notes (07/05/94)
Version 0.14 was supposed to be a minimal bug fix release to 0.13.
The same bugs are still there and there are a few small additions
mostly aimed at coping with convergence problems.
1. The truncation error formula was changed to use the third
derivative of charge instead of the second derivative of current.
These two numbers are theoretically equal, but in practice they
are not. The second derivative of current uses 3 terms to compute
by divided differences. The third derivative of charge uses 4
terms. Using the odd number of terms catches the error due to the
oscillatory nature of the trapezoid rule. An even number of terms
tends to lose this error. Also, using charge tends to mask it.
So, I have changed it to a less accurate, more optimistic method,
the same as Spice. It now seems to work about the same as Spice,
in the sense that it usually chooses about the same step sizes.
Strictly, the old method is "better" but it tends to run away on
stiff poles, trying for excess accuracy that doesn't matter. Your
comments on this matter are welcome. If you know of any good papers
on this, please let me know.
2. The "stiff" option has been removed from the transient command.
Instead, use the .options "trapezoid" or "gear". For now, "gear"
implies first order and is equivalent to the old "stiff". (A
cop-out.) Actually, for stiff poles you want a first order method
because the error is lower.
3. You can specify the integration method individually on any
capacitor or inductor.
4. A bug causing the MSDOS version (2 byte integers) to mess up
probes of other than nodes was fixed.
5. A bug that sometimes caused it to perpetually repeat the same
time step was fixed. (SPICE would have reported "time step too
small" and stopped.)
6. A bug that messed up step control when a dormant model wakes up
and finds out it has been sleeping too long has been fixed.
7. "Mosflags" and "diodeflags" are different and there are more of
them. There are lots of them and they may be useful in taming
convergence problems. They control the heuristics that are applied
when there appears to be a convergence problem. I have yet to find
a circuit that could not be made to converge by judicious application
of the flags and options, but any one setting is no better than
Spice, and many are worse. One combination of flags gives Spice
style limiting, which more often than not makes convergence worse.
8. "vmax" and "vmin" options as part of convergence heuristics.
The default value of "limit" now large enough to essentially remove
it. These limits sometimes help convergence, but more often hurt.
9. The "damp" option actually works.
10. The diode "off" flag works correctly.
11. There is a new command "alarm" that prints a message when a
value exceeds a range. The syntax is the same as the "plot" command.
------------------------------------------------------------------
ACS 0.13 release notes (03/11/94)
Version 0.13 adds several new features and has several bug fixes
and performance improvements.
1. Fourier analysis really works.
The "Fourier" command does a transient analysis but prints the
results in the frequency domain. It is similar to the Spice command
of the same name but not exactly the same. It is significantly
more accurate than Spice because the transient time steps are chosen
for the best match to the Fast Fourier Transform. Considerably
more flexibility is available than in Spice.
2. Transient time step control by truncation error (finally).
3. Several options have been added to display diagnostics.
4. Fixed the default value for idsat, issat, ad, and as in the
mos-diode. In 0.12, the default area was 1 square meter, which
gave mosfet capacitors in the 500 uf range. This sometimes caused
strange results.
5. Added some node probes, mostly for diagnostic use.
6. Fixed the "F" probe on linear elements. (Capacitor charge,
inductor flux, admittance current, resistor voltage) It used to
give an obviously bogus answer.
Other changes:
1. Some general changes in the interest of improving code quality
in general.
2. Function headers are in ANSI style, rather than K&R style. This
version will compile as either C or C++. Future versions will
require a C++ compiler.
------------------------------------------------------------------
ACS 0.12 release notes (10/09/93)
Version 0.12 is a maintenance release. It adds no features (except Ultrix
support) but fixes several bugs and changes some porting details. It
should be easier to port this version than previous versions.
The bug fixes are significant enough that you should upgrade to 0.12 even
if you are not having any problems.
------------------------------------------------------------------
ACS 0.11 release notes (07/26/93)
Version 0.11 fixes a few bugs in 0.10. 0.10 was supposed to be
posted on alt.sources but due to a problem with the feed it never
happened.
New features:
1. New MOSFET and diode probes. All information available from
the Spice 2 "op" analysis is now available as probes. For MOSFET
these include cbd, cbs, cgsovl, cgdovl, cgbovl, cgs, cgd, cgb,
vdsat, vth. Other (non-spice) new probes include cgst, cgdt, cgbt.
(cgst = Cgs total = cgsovl + cgs.) These were available before by
probing the value of the internal element but it was less convenient.
Now it is simple and has the same name as in Spice. These probes
are also available in transient analysis, so you can see (for
example) the dynamic variations in capacitance.
Bugs fixed:
1. Pass arguments to tr_volts and family by pointer instead of the
whole structure. This is less likely to tickle a bug in Microsoft
C. The MSDOS version of ACS 0.10 crashed frequently due to this
bug. (Strictly, this is a Microsoft-C bug, not an ACS bug but the
effect is the same.)
2. The AC "Z" probes work again. They were broken in 0.10.
3. The size of the buffer for text plots is increased allowing
support for wider screens. The old version would crash if you did
plots with outwidth set to wider than 128. The fix is to make it
bigger, with a new constant MAXWIDTH, and trap the width setting
bigger than MAXWIDTH. The current max is 256 for MSDOS and 512
for unix. The plotting code should probably be redone.
4. Width is narrower by 1 so setting width to 80 won't leave blank
lines on an 80 column screen.
5. MOSFET capacitance now matches Spice (Meyer model)
6. Level 1 model linear region gds calculation was wrong, but close
enough to often go unnoticed. It is correct and matches Spice now.
7. The value of an AC source now is compatible with Spice. That
is, plain value is the DC-tran value. In old versions of ACS a
plain value applied to all analyses including AC. You needed to
prefix the value with "DC" to make it not apply to AC. Actually,
it worked as documented. Now it works like Spice, which makes more
sense. This was a major source of strange results in AC analysis.
------------------------------------------------------------------
------------------------------------------------------------------
INSTALL 0000664 0000000 0000000 00000022432 11454012162 0012106 0 ustar 00root root 0000000 0000000 Installation Instructions
*************************
Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005 Free
Software Foundation, Inc.
This file is free documentation; the Free Software Foundation gives
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Basic Installation
==================
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# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
Makefile.template 0000664 0000000 0000000 00000002106 11454012162 0014323 0 ustar 00root root 0000000 0000000 # SDB changed configure and Makefile operation in -*- Makefile -*-
# the following way: The configure script now
# copies the subdir Makefiles over to Makefile.original,
# and then uses sed to put the --prefix target into
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# Use the target "unconfig" to move Makefile.original
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all: modelgen gnucap
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NEWS 0000664 0000000 0000000 00000000000 11454012162 0011537 0 ustar 00root root 0000000 0000000 README 0000664 0000000 0000000 00000003446 11454012162 0011741 0 ustar 00root root 0000000 0000000 Readme for development snapshot 2007-02-21
This is a development snapshot. As such, there may be problems due to
new work.
The most important change here is enhanced plugin support, and the 3
new model packages, distributed separately.
Also, commands use the dispatcher, so they can be added as plugins.
Readme for development snapshot 2006-12-04
This is a development snapshot. As such, there may be problems due to
new work.
New features: "attach" and "detach" commands, for attaching and
detaching compiled modules.
To use ....
Start with a .model file.
Compile it .....
>> gnucap-modelgen my-model.model
.. produces my-model.h amd my-model.cc
Compile that, with "-fPIC -shared" options
>> g++ -fPIC -shared my-model.cc
.. produces a.out (you could name it with -o ..)
Now, run gnucap
>> gnucap
(signs on..)
then you can attach the model..
gnucap> attach ./a.out
gnucap>
.. now you can use your model!!
This snapshot includes some new verilog code, which is incomplete and
not ready for anyone but a developer. You can safely ignore it for
now.
It also changes the way models, devices, and functions are dispatched.
The new version uses a dispatcher object, that is built on start-up,
based on what modules are linked. Models, devices, and functions can
be added simply by linking them in. There is no need to change
anything else. Likewise, if you don't need a model, device, or
function, and want a version with it missing, just remove it from
"Make1" and relink.
The latest "stable" version is 0.35. If you want to help development,
use this snapshot and tell us what you find. If you don't want to
live on the edge, use the stable version.
If you are making binary packages for distribution, please try this
version and let me know how it works, but continue to distribute 0.35.
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# Just in case
sleep 1
echo timestamp > conftest.file
# Reject unsafe characters in $srcdir or the absolute working directory
# name. Accept space and tab only in the latter.
am_lf='
'
case `pwd` in
*[[\\\"\#\$\&\'\`$am_lf]]*)
AC_MSG_ERROR([unsafe absolute working directory name]);;
esac
case $srcdir in
*[[\\\"\#\$\&\'\`$am_lf\ \ ]]*)
AC_MSG_ERROR([unsafe srcdir value: `$srcdir']);;
esac
# Do `set' in a subshell so we don't clobber the current shell's
# arguments. Must try -L first in case configure is actually a
# symlink; some systems play weird games with the mod time of symlinks
# (eg FreeBSD returns the mod time of the symlink's containing
# directory).
if (
set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null`
if test "$[*]" = "X"; then
# -L didn't work.
set X `ls -t "$srcdir/configure" conftest.file`
fi
rm -f conftest.file
if test "$[*]" != "X $srcdir/configure conftest.file" \
&& test "$[*]" != "X conftest.file $srcdir/configure"; then
# If neither matched, then we have a broken ls. This can happen
# if, for instance, CONFIG_SHELL is bash and it inherits a
# broken ls alias from the environment. This has actually
# happened. Such a system could not be considered "sane".
AC_MSG_ERROR([ls -t appears to fail. Make sure there is not a broken
alias in your environment])
fi
test "$[2]" = conftest.file
)
then
# Ok.
:
else
AC_MSG_ERROR([newly created file is older than distributed files!
Check your system clock])
fi
AC_MSG_RESULT(yes)])
# Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc.
#
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# AM_PROG_INSTALL_STRIP
# ---------------------
# One issue with vendor `install' (even GNU) is that you can't
# specify the program used to strip binaries. This is especially
# annoying in cross-compiling environments, where the build's strip
# is unlikely to handle the host's binaries.
# Fortunately install-sh will honor a STRIPPROG variable, so we
# always use install-sh in `make install-strip', and initialize
# STRIPPROG with the value of the STRIP variable (set by the user).
AC_DEFUN([AM_PROG_INSTALL_STRIP],
[AC_REQUIRE([AM_PROG_INSTALL_SH])dnl
# Installed binaries are usually stripped using `strip' when the user
# run `make install-strip'. However `strip' might not be the right
# tool to use in cross-compilation environments, therefore Automake
# will honor the `STRIP' environment variable to overrule this program.
dnl Don't test for $cross_compiling = yes, because it might be `maybe'.
if test "$cross_compiling" != no; then
AC_CHECK_TOOL([STRIP], [strip], :)
fi
INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s"
AC_SUBST([INSTALL_STRIP_PROGRAM])])
# Copyright (C) 2006, 2008 Free Software Foundation, Inc.
#
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# serial 2
# _AM_SUBST_NOTMAKE(VARIABLE)
# ---------------------------
# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in.
# This macro is traced by Automake.
AC_DEFUN([_AM_SUBST_NOTMAKE])
# AM_SUBST_NOTMAKE(VARIABLE)
# ---------------------------
# Public sister of _AM_SUBST_NOTMAKE.
AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)])
# Check how to create a tarball. -*- Autoconf -*-
# Copyright (C) 2004, 2005 Free Software Foundation, Inc.
#
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# serial 2
# _AM_PROG_TAR(FORMAT)
# --------------------
# Check how to create a tarball in format FORMAT.
# FORMAT should be one of `v7', `ustar', or `pax'.
#
# Substitute a variable $(am__tar) that is a command
# writing to stdout a FORMAT-tarball containing the directory
# $tardir.
# tardir=directory && $(am__tar) > result.tar
#
# Substitute a variable $(am__untar) that extract such
# a tarball read from stdin.
# $(am__untar) < result.tar
AC_DEFUN([_AM_PROG_TAR],
[# Always define AMTAR for backward compatibility.
AM_MISSING_PROG([AMTAR], [tar])
m4_if([$1], [v7],
[am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -'],
[m4_case([$1], [ustar],, [pax],,
[m4_fatal([Unknown tar format])])
AC_MSG_CHECKING([how to create a $1 tar archive])
# Loop over all known methods to create a tar archive until one works.
_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none'
_am_tools=${am_cv_prog_tar_$1-$_am_tools}
# Do not fold the above two line into one, because Tru64 sh and
# Solaris sh will not grok spaces in the rhs of `-'.
for _am_tool in $_am_tools
do
case $_am_tool in
gnutar)
for _am_tar in tar gnutar gtar;
do
AM_RUN_LOG([$_am_tar --version]) && break
done
am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"'
am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"'
am__untar="$_am_tar -xf -"
;;
plaintar)
# Must skip GNU tar: if it does not support --format= it doesn't create
# ustar tarball either.
(tar --version) >/dev/null 2>&1 && continue
am__tar='tar chf - "$$tardir"'
am__tar_='tar chf - "$tardir"'
am__untar='tar xf -'
;;
pax)
am__tar='pax -L -x $1 -w "$$tardir"'
am__tar_='pax -L -x $1 -w "$tardir"'
am__untar='pax -r'
;;
cpio)
am__tar='find "$$tardir" -print | cpio -o -H $1 -L'
am__tar_='find "$tardir" -print | cpio -o -H $1 -L'
am__untar='cpio -i -H $1 -d'
;;
none)
am__tar=false
am__tar_=false
am__untar=false
;;
esac
# If the value was cached, stop now. We just wanted to have am__tar
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rm -rf conftest.dir
AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool])
AC_MSG_RESULT([$am_cv_prog_tar_$1])])
AC_SUBST([am__tar])
AC_SUBST([am__untar])
]) # _AM_PROG_TAR
autogen.sh 0000775 0000000 0000000 00000000771 11454012162 0013060 0 ustar 00root root 0000000 0000000 #! /bin/sh
#
# $Id$
#
# Run the various GNU autotools to bootstrap the build
# system. Should only need to be done once.
# for now avoid using bash as not everyone has that installed
CONFIG_SHELL=/bin/sh
export CONFIG_SHELL
echo "Running aclocal..."
aclocal $ACLOCAL_FLAGS || exit 1
echo "Running autoheader..."
autoheader || exit 1
echo "Running automake..."
automake -a -c --gnu || exit 1
echo "Running autoconf..."
autoconf || exit 1
echo "not Running configure..."
##./configure $@ || exit 1
config.h.in 0000664 0000000 0000000 00000001560 11454012162 0013077 0 ustar 00root root 0000000 0000000 /* config.h.in. Generated from configure.ac by autoheader. */
/* Define to 1 if you have the `dl' library (-ldl). */
#undef HAVE_LIBDL
/* Define to 1 if you have the `readline' library (-lreadline). */
#undef HAVE_LIBREADLINE
/* Define to 1 if you have the `termcap' library (-ltermcap). */
#undef HAVE_LIBTERMCAP
/* Name of package */
#undef PACKAGE
/* Define to the address where bug reports for this package should be sent. */
#undef PACKAGE_BUGREPORT
/* Define to the full name of this package. */
#undef PACKAGE_NAME
/* Define to the full name and version of this package. */
#undef PACKAGE_STRING
/* Define to the one symbol short name of this package. */
#undef PACKAGE_TARNAME
/* Define to the home page for this package. */
#undef PACKAGE_URL
/* Define to the version of this package. */
#undef PACKAGE_VERSION
/* Version number of package */
#undef VERSION
configure 0000775 0000000 0000000 00000422572 11454012162 0012775 0 ustar 00root root 0000000 0000000 #! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
# Generated by GNU Autoconf 2.65.
#
#
# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
# Inc.
#
#
# This configure script is free software; the Free Software Foundation
# gives unlimited permission to copy, distribute and modify it.
## -------------------- ##
## M4sh Initialization. ##
## -------------------- ##
# Be more Bourne compatible
DUALCASE=1; export DUALCASE # for MKS sh
if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
emulate sh
NULLCMD=:
# Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
# is contrary to our usage. Disable this feature.
alias -g '${1+"$@"}'='"$@"'
setopt NO_GLOB_SUBST
else
case `(set -o) 2>/dev/null` in #(
*posix*) :
set -o posix ;; #(
*) :
;;
esac
fi
as_nl='
'
export as_nl
# Printing a long string crashes Solaris 7 /usr/bin/printf.
as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
# Prefer a ksh shell builtin over an external printf program on Solaris,
# but without wasting forks for bash or zsh.
if test -z "$BASH_VERSION$ZSH_VERSION" \
&& (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='print -r --'
as_echo_n='print -rn --'
elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='printf %s\n'
as_echo_n='printf %s'
else
if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
as_echo_n='/usr/ucb/echo -n'
else
as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
as_echo_n_body='eval
arg=$1;
case $arg in #(
*"$as_nl"*)
expr "X$arg" : "X\\(.*\\)$as_nl";
arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
esac;
expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
'
export as_echo_n_body
as_echo_n='sh -c $as_echo_n_body as_echo'
fi
export as_echo_body
as_echo='sh -c $as_echo_body as_echo'
fi
# The user is always right.
if test "${PATH_SEPARATOR+set}" != set; then
PATH_SEPARATOR=:
(PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
(PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
PATH_SEPARATOR=';'
}
fi
# IFS
# We need space, tab and new line, in precisely that order. Quoting is
# there to prevent editors from complaining about space-tab.
# (If _AS_PATH_WALK were called with IFS unset, it would disable word
# splitting by setting IFS to empty value.)
IFS=" "" $as_nl"
# Find who we are. Look in the path if we contain no directory separator.
case $0 in #((
*[\\/]* ) as_myself=$0 ;;
*) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
for as_dir in $PATH
do
IFS=$as_save_IFS
test -z "$as_dir" && as_dir=.
test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
done
IFS=$as_save_IFS
;;
esac
# We did not find ourselves, most probably we were run as `sh COMMAND'
# in which case we are not to be found in the path.
if test "x$as_myself" = x; then
as_myself=$0
fi
if test ! -f "$as_myself"; then
$as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
exit 1
fi
# Unset variables that we do not need and which cause bugs (e.g. in
# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
# suppresses any "Segmentation fault" message there. '((' could
# trigger a bug in pdksh 5.2.14.
for as_var in BASH_ENV ENV MAIL MAILPATH
do eval test x\${$as_var+set} = xset \
&& ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
done
PS1='$ '
PS2='> '
PS4='+ '
# NLS nuisances.
LC_ALL=C
export LC_ALL
LANGUAGE=C
export LANGUAGE
# CDPATH.
(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
if test "x$CONFIG_SHELL" = x; then
as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then :
emulate sh
NULLCMD=:
# Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which
# is contrary to our usage. Disable this feature.
alias -g '\${1+\"\$@\"}'='\"\$@\"'
setopt NO_GLOB_SUBST
else
case \`(set -o) 2>/dev/null\` in #(
*posix*) :
set -o posix ;; #(
*) :
;;
esac
fi
"
as_required="as_fn_return () { (exit \$1); }
as_fn_success () { as_fn_return 0; }
as_fn_failure () { as_fn_return 1; }
as_fn_ret_success () { return 0; }
as_fn_ret_failure () { return 1; }
exitcode=0
as_fn_success || { exitcode=1; echo as_fn_success failed.; }
as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; }
as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; }
as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; }
if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then :
else
exitcode=1; echo positional parameters were not saved.
fi
test x\$exitcode = x0 || exit 1"
as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO
as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO
eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" &&
test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1"
if (eval "$as_required") 2>/dev/null; then :
as_have_required=yes
else
as_have_required=no
fi
if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then :
else
as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
as_found=false
for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
do
IFS=$as_save_IFS
test -z "$as_dir" && as_dir=.
as_found=:
case $as_dir in #(
/*)
for as_base in sh bash ksh sh5; do
# Try only shells that exist, to save several forks.
as_shell=$as_dir/$as_base
if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
{ $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then :
CONFIG_SHELL=$as_shell as_have_required=yes
if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then :
break 2
fi
fi
done;;
esac
as_found=false
done
$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } &&
{ $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then :
CONFIG_SHELL=$SHELL as_have_required=yes
fi; }
IFS=$as_save_IFS
if test "x$CONFIG_SHELL" != x; then :
# We cannot yet assume a decent shell, so we have to provide a
# neutralization value for shells without unset; and this also
# works around shells that cannot unset nonexistent variables.
BASH_ENV=/dev/null
ENV=/dev/null
(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
export CONFIG_SHELL
exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"}
fi
if test x$as_have_required = xno; then :
$as_echo "$0: This script requires a shell more modern than all"
$as_echo "$0: the shells that I found on your system."
if test x${ZSH_VERSION+set} = xset ; then
$as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should"
$as_echo "$0: be upgraded to zsh 4.3.4 or later."
else
$as_echo "$0: Please tell bug-autoconf@gnu.org about your system,
$0: including any error possibly output before this
$0: message. Then install a modern shell, or manually run
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fi
exit 1
fi
fi
fi
SHELL=${CONFIG_SHELL-/bin/sh}
export SHELL
# Unset more variables known to interfere with behavior of common tools.
CLICOLOR_FORCE= GREP_OPTIONS=
unset CLICOLOR_FORCE GREP_OPTIONS
## --------------------- ##
## M4sh Shell Functions. ##
## --------------------- ##
# as_fn_unset VAR
# ---------------
# Portably unset VAR.
as_fn_unset ()
{
{ eval $1=; unset $1;}
}
as_unset=as_fn_unset
# as_fn_set_status STATUS
# -----------------------
# Set $? to STATUS, without forking.
as_fn_set_status ()
{
return $1
} # as_fn_set_status
# as_fn_exit STATUS
# -----------------
# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
as_fn_exit ()
{
set +e
as_fn_set_status $1
exit $1
} # as_fn_exit
# as_fn_mkdir_p
# -------------
# Create "$as_dir" as a directory, including parents if necessary.
as_fn_mkdir_p ()
{
case $as_dir in #(
-*) as_dir=./$as_dir;;
esac
test -d "$as_dir" || eval $as_mkdir_p || {
as_dirs=
while :; do
case $as_dir in #(
*\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
*) as_qdir=$as_dir;;
esac
as_dirs="'$as_qdir' $as_dirs"
as_dir=`$as_dirname -- "$as_dir" ||
$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$as_dir" : 'X\(//\)[^/]' \| \
X"$as_dir" : 'X\(//\)$' \| \
X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$as_dir" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
test -d "$as_dir" && break
done
test -z "$as_dirs" || eval "mkdir $as_dirs"
} || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir"
} # as_fn_mkdir_p
# as_fn_append VAR VALUE
# ----------------------
# Append the text in VALUE to the end of the definition contained in VAR. Take
# advantage of any shell optimizations that allow amortized linear growth over
# repeated appends, instead of the typical quadratic growth present in naive
# implementations.
if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
eval 'as_fn_append ()
{
eval $1+=\$2
}'
else
as_fn_append ()
{
eval $1=\$$1\$2
}
fi # as_fn_append
# as_fn_arith ARG...
# ------------------
# Perform arithmetic evaluation on the ARGs, and store the result in the
# global $as_val. Take advantage of shells that can avoid forks. The arguments
# must be portable across $(()) and expr.
if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
eval 'as_fn_arith ()
{
as_val=$(( $* ))
}'
else
as_fn_arith ()
{
as_val=`expr "$@" || test $? -eq 1`
}
fi # as_fn_arith
# as_fn_error ERROR [LINENO LOG_FD]
# ---------------------------------
# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
# script with status $?, using 1 if that was 0.
as_fn_error ()
{
as_status=$?; test $as_status -eq 0 && as_status=1
if test "$3"; then
as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
$as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3
fi
$as_echo "$as_me: error: $1" >&2
as_fn_exit $as_status
} # as_fn_error
if expr a : '\(a\)' >/dev/null 2>&1 &&
test "X`expr 00001 : '.*\(...\)'`" = X001; then
as_expr=expr
else
as_expr=false
fi
if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
as_basename=basename
else
as_basename=false
fi
if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
as_dirname=dirname
else
as_dirname=false
fi
as_me=`$as_basename -- "$0" ||
$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
X"$0" : 'X\(//\)$' \| \
X"$0" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X/"$0" |
sed '/^.*\/\([^/][^/]*\)\/*$/{
s//\1/
q
}
/^X\/\(\/\/\)$/{
s//\1/
q
}
/^X\/\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
# Avoid depending upon Character Ranges.
as_cr_letters='abcdefghijklmnopqrstuvwxyz'
as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
as_cr_Letters=$as_cr_letters$as_cr_LETTERS
as_cr_digits='0123456789'
as_cr_alnum=$as_cr_Letters$as_cr_digits
as_lineno_1=$LINENO as_lineno_1a=$LINENO
as_lineno_2=$LINENO as_lineno_2a=$LINENO
eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" &&
test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || {
# Blame Lee E. McMahon (1931-1989) for sed's syntax. :-)
sed -n '
p
/[$]LINENO/=
' <$as_myself |
sed '
s/[$]LINENO.*/&-/
t lineno
b
:lineno
N
:loop
s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/
t loop
s/-\n.*//
' >$as_me.lineno &&
chmod +x "$as_me.lineno" ||
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\`configure' configures this package to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
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--with-readline support command line editing [default=yes]
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LDFLAGS linker flags, e.g. -L if you have libraries in a
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LIBS libraries to pass to the linker, e.g. -l
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configure
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Copyright (C) 2009 Free Software Foundation, Inc.
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{ $as_echo "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5
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if test "$ac_new_set" = set; then
case $ac_new_val in
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done
if $ac_cache_corrupted; then
{ $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
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{ $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5
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as_fn_error "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5
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## -------------------- ##
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## -------------------- ##
ac_ext=c
ac_cpp='$CPP $CPPFLAGS'
ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
ac_compiler_gnu=$ac_cv_c_compiler_gnu
# this is any file in the source directory
# used as a check to be sure we found it
am__api_version='1.11'
ac_aux_dir=
for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do
for ac_t in install-sh install.sh shtool; do
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ac_aux_dir=$ac_dir
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break 2
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done
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as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5
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# These three variables are undocumented and unsupported,
# and are intended to be withdrawn in a future Autoconf release.
# They can cause serious problems if a builder's source tree is in a directory
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ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var.
ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var.
ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var.
# Find a good install program. We prefer a C program (faster),
# so one script is as good as another. But avoid the broken or
# incompatible versions:
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# SunOS /usr/etc/install
# IRIX /sbin/install
# AIX /bin/install
# AmigaOS /C/install, which installs bootblocks on floppy discs
# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
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# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5
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then
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fi
done
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;;
esac
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IFS=$as_save_IFS
rm -rf conftest.one conftest.two conftest.dir
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if test "${ac_cv_path_install+set}" = set; then
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5
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set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null`
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# Installed binaries are usually stripped using `strip' when the user
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ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
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if test "x$ac_ct_STRIP" = x; then
STRIP=":"
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case $cross_compiling:$ac_tool_warned in
yes:)
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
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ac_tool_warned=yes ;;
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STRIP=$ac_ct_STRIP
fi
else
STRIP="$ac_cv_prog_STRIP"
fi
fi
INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s"
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a thread-safe mkdir -p" >&5
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'mkdir (coreutils) '* | \
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ac_cv_path_mkdir=$as_dir/$ac_prog$ac_exec_ext
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done
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fi
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $MKDIR_P" >&5
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mkdir_p="$MKDIR_P"
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for ac_prog in gawk mawk nawk awk
do
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as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
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fi
AWK=$ac_cv_prog_AWK
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
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{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5
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cat >conftest.make <<\_ACEOF
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all:
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eval ac_cv_prog_make_${ac_make}_set=yes;;
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eval ac_cv_prog_make_${ac_make}_set=no;;
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rm -f conftest.make
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SET_MAKE=
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{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
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SET_MAKE="MAKE=${MAKE-make}"
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rm -rf .tst 2>/dev/null
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am__leading_dot=.
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am__leading_dot=_
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fi
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CYGPATH_W=echo
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fi
# Define the identity of the package.
PACKAGE=gnucap
VERSION=2009-12-07
cat >>confdefs.h <<_ACEOF
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cat >>confdefs.h <<_ACEOF
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AUTOCONF=${AUTOCONF-"${am_missing_run}autoconf"}
AUTOMAKE=${AUTOMAKE-"${am_missing_run}automake-${am__api_version}"}
AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"}
MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"}
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AMTAR=${AMTAR-"${am_missing_run}tar"}
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ac_config_headers="$ac_config_headers config.h"
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fi
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ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
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CXX=$CCC
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fi
# If we are cross compiling, then we need to search for a
# gnucap-modelgen program to use for our build. This can
# either be an installed modelgen or it can be specified
# like:
# env MODELGEN=/build/i686--linux/modelgen/gnucap-modelgen /srcs/gnucap/configure
# --host=alpha--netbsd --build=i686--linux
#
if test "$cross_compiling" = yes; then
# Extract the first word of "gnucap-modelgen", so it can be a program name with args.
set dummy gnucap-modelgen; ac_word=$2
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
$as_echo_n "checking for $ac_word... " >&6; }
if test "${ac_cv_path_MODELGEN+set}" = set; then :
$as_echo_n "(cached) " >&6
else
case $MODELGEN in
[\\/]* | ?:[\\/]*)
ac_cv_path_MODELGEN="$MODELGEN" # Let the user override the test with a path.
;;
*)
as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
for as_dir in $PATH
do
IFS=$as_save_IFS
test -z "$as_dir" && as_dir=.
for ac_exec_ext in '' $ac_executable_extensions; do
if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then
ac_cv_path_MODELGEN="$as_dir/$ac_word$ac_exec_ext"
$as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
break 2
fi
done
done
IFS=$as_save_IFS
;;
esac
fi
MODELGEN=$ac_cv_path_MODELGEN
if test -n "$MODELGEN"; then
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $MODELGEN" >&5
$as_echo "$MODELGEN" >&6; }
else
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
$as_echo "no" >&6; }
fi
else
MODELGEN=../modelgen/gnucap-modelgen
fi
# for building the documentation
#AC_PATH_PROG(DVIPDFM, dvipdfm, notfound)
#AM_CONDITIONAL(MISSING_DVIPDFM, test x$DVIPDFM = xnotfound)
#AC_PATH_PROG(HACHA, hacha, notfound)
#AC_PATH_PROG(HEVEA, hevea, notfound)
#AM_CONDITIONAL(MISSING_HEVEA, test x$HEVEA = xnotfound -o x$HACHA = xnotfound)
#AC_PATH_PROG(LATEX, latex, notfound)
#AC_PATH_PROG(MAKEINDEX, makeindex, notfound)
#AM_CONDITIONAL(MISSING_LATEX, test x$LATEX = xnotfound -o x$MAKEINDEX = xnotfound)
# Checks for libraries.
# this is a c++ program so use c++ for the tests
ac_ext=cpp
ac_cpp='$CXXCPP $CPPFLAGS'
ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5'
ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
#AC_CHECK_LIB([termcap], [main])
#AC_CHECK_LIB([readline], [main])
# Check whether --with-readline was given.
if test "${with_readline+set}" = set; then :
withval=$with_readline;
else
with_readline=yes
fi
if test "x$with_readline" != xno ; then
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for main in -ltermcap" >&5
$as_echo_n "checking for main in -ltermcap... " >&6; }
if test "${ac_cv_lib_termcap_main+set}" = set; then :
$as_echo_n "(cached) " >&6
else
ac_check_lib_save_LIBS=$LIBS
LIBS="-ltermcap $LIBS"
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
/* end confdefs.h. */
int
main ()
{
return main ();
;
return 0;
}
_ACEOF
if ac_fn_cxx_try_link "$LINENO"; then :
ac_cv_lib_termcap_main=yes
else
ac_cv_lib_termcap_main=no
fi
rm -f core conftest.err conftest.$ac_objext \
conftest$ac_exeext conftest.$ac_ext
LIBS=$ac_check_lib_save_LIBS
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_termcap_main" >&5
$as_echo "$ac_cv_lib_termcap_main" >&6; }
if test "x$ac_cv_lib_termcap_main" = x""yes; then :
cat >>confdefs.h <<_ACEOF
#define HAVE_LIBTERMCAP 1
_ACEOF
LIBS="-ltermcap $LIBS"
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for main in -lreadline" >&5
$as_echo_n "checking for main in -lreadline... " >&6; }
if test "${ac_cv_lib_readline_main+set}" = set; then :
$as_echo_n "(cached) " >&6
else
ac_check_lib_save_LIBS=$LIBS
LIBS="-lreadline $LIBS"
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
/* end confdefs.h. */
int
main ()
{
return main ();
;
return 0;
}
_ACEOF
if ac_fn_cxx_try_link "$LINENO"; then :
ac_cv_lib_readline_main=yes
else
ac_cv_lib_readline_main=no
fi
rm -f core conftest.err conftest.$ac_objext \
conftest$ac_exeext conftest.$ac_ext
LIBS=$ac_check_lib_save_LIBS
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_readline_main" >&5
$as_echo "$ac_cv_lib_readline_main" >&6; }
if test "x$ac_cv_lib_readline_main" = x""yes; then :
cat >>confdefs.h <<_ACEOF
#define HAVE_LIBREADLINE 1
_ACEOF
LIBS="-lreadline $LIBS"
fi
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5
$as_echo_n "checking for dlopen in -ldl... " >&6; }
if test "${ac_cv_lib_dl_dlopen+set}" = set; then :
$as_echo_n "(cached) " >&6
else
ac_check_lib_save_LIBS=$LIBS
LIBS="-ldl $LIBS"
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
/* end confdefs.h. */
/* Override any GCC internal prototype to avoid an error.
Use char because int might match the return type of a GCC
builtin and then its argument prototype would still apply. */
#ifdef __cplusplus
extern "C"
#endif
char dlopen ();
int
main ()
{
return dlopen ();
;
return 0;
}
_ACEOF
if ac_fn_cxx_try_link "$LINENO"; then :
ac_cv_lib_dl_dlopen=yes
else
ac_cv_lib_dl_dlopen=no
fi
rm -f core conftest.err conftest.$ac_objext \
conftest$ac_exeext conftest.$ac_ext
LIBS=$ac_check_lib_save_LIBS
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5
$as_echo "$ac_cv_lib_dl_dlopen" >&6; }
if test "x$ac_cv_lib_dl_dlopen" = x""yes; then :
cat >>confdefs.h <<_ACEOF
#define HAVE_LIBDL 1
_ACEOF
LIBS="-ldl $LIBS"
fi
# Checks for header files.
#AC_CHECK_HEADERS([fcntl.h unistd.h])
# Checks for typedefs, structures, and compiler characteristics.
# Checks for library functions.
if test "$enable_debug" = "yes" ; then
CPPFLAGS="$CPPFLAGS -DTRACE_UNTESTED"
else
CPPFLAGS="$CPPFLAGS -DNDEBUG"
fi
# if we have gcc and we've asked for debugging then add lots of -W
if test "x$GCC" = "xyes" -a "$enable_debug" = "yes"; then
for flag in -DTRACE_UNTESTED -Wall -W -Wno-sign-compare \
-Wpointer-arith -Wcast-qual \
-Wwrite-strings -Wconversion \
-Woverloaded-virtual -O2 -Wlong-long \
-Wsign-compare -Wcast-align ; do
case " ${CFLAGS} " in
*\ ${flag}\ *)
# flag is already present
;;
*)
CFLAGS="$CFLAGS ${flag}"
;;
esac
case " ${CXXFLAGS} " in
*\ ${flag}\ *)
# flag is already present
;;
*)
CXXFLAGS="$CXXFLAGS ${flag}"
;;
esac
done
fi
# exports symbols to plugins
LDFLAGS="$LDFLAGS -rdynamic"
#AC_OUTPUT([
# Makefile
# doc/Makefile
# examples/Makefile
# man/Makefile
# man/Addmodel/Makefile
# man/Behavior/Makefile
# man/Circuit/Makefile
# man/Commands/Makefile
# man/Tech/Makefile
# modelgen/Makefile
# src/Makefile
# ])
ac_config_files="$ac_config_files Makefile doc/Makefile examples/Makefile modelgen/Makefile src/Makefile"
cat >confcache <<\_ACEOF
# This file is a shell script that caches the results of configure
# tests run on this system so they can be shared between configure
# scripts and configure runs, see configure's option --config-cache.
# It is not useful on other systems. If it contains results you don't
# want to keep, you may remove or edit it.
#
# config.status only pays attention to the cache file if you give it
# the --recheck option to rerun configure.
#
# `ac_cv_env_foo' variables (set or unset) will be overridden when
# loading this file, other *unset* `ac_cv_foo' will be assigned the
# following values.
_ACEOF
# The following way of writing the cache mishandles newlines in values,
# but we know of no workaround that is simple, portable, and efficient.
# So, we kill variables containing newlines.
# Ultrix sh set writes to stderr and can't be redirected directly,
# and sets the high bit in the cache file unless we assign to the vars.
(
for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do
eval ac_val=\$$ac_var
case $ac_val in #(
*${as_nl}*)
case $ac_var in #(
*_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
esac
case $ac_var in #(
_ | IFS | as_nl) ;; #(
BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
*) { eval $ac_var=; unset $ac_var;} ;;
esac ;;
esac
done
(set) 2>&1 |
case $as_nl`(ac_space=' '; set) 2>&1` in #(
*${as_nl}ac_space=\ *)
# `set' does not quote correctly, so add quotes: double-quote
# substitution turns \\\\ into \\, and sed turns \\ into \.
sed -n \
"s/'/'\\\\''/g;
s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
;; #(
*)
# `set' quotes correctly as required by POSIX, so do not add quotes.
sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
;;
esac |
sort
) |
sed '
/^ac_cv_env_/b end
t clear
:clear
s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
t end
s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
:end' >>confcache
if diff "$cache_file" confcache >/dev/null 2>&1; then :; else
if test -w "$cache_file"; then
test "x$cache_file" != "x/dev/null" &&
{ $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5
$as_echo "$as_me: updating cache $cache_file" >&6;}
cat confcache >$cache_file
else
{ $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5
$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;}
fi
fi
rm -f confcache
test "x$prefix" = xNONE && prefix=$ac_default_prefix
# Let make expand exec_prefix.
test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
DEFS=-DHAVE_CONFIG_H
ac_libobjs=
ac_ltlibobjs=
for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
# 1. Remove the extension, and $U if already installed.
ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'
ac_i=`$as_echo "$ac_i" | sed "$ac_script"`
# 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR
# will be set to the directory where LIBOBJS objects are built.
as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext"
as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo'
done
LIBOBJS=$ac_libobjs
LTLIBOBJS=$ac_ltlibobjs
if test -n "$EXEEXT"; then
am__EXEEXT_TRUE=
am__EXEEXT_FALSE='#'
else
am__EXEEXT_TRUE='#'
am__EXEEXT_FALSE=
fi
if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then
as_fn_error "conditional \"MAINTAINER_MODE\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then
as_fn_error "conditional \"AMDEP\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
if test -z "${am__fastdepCXX_TRUE}" && test -z "${am__fastdepCXX_FALSE}"; then
as_fn_error "conditional \"am__fastdepCXX\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
: ${CONFIG_STATUS=./config.status}
ac_write_fail=0
ac_clean_files_save=$ac_clean_files
ac_clean_files="$ac_clean_files $CONFIG_STATUS"
{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5
$as_echo "$as_me: creating $CONFIG_STATUS" >&6;}
as_write_fail=0
cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1
#! $SHELL
# Generated by $as_me.
# Run this file to recreate the current configuration.
# Compiler output produced by configure, useful for debugging
# configure, is in config.log if it exists.
debug=false
ac_cs_recheck=false
ac_cs_silent=false
SHELL=\${CONFIG_SHELL-$SHELL}
export SHELL
_ASEOF
cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1
## -------------------- ##
## M4sh Initialization. ##
## -------------------- ##
# Be more Bourne compatible
DUALCASE=1; export DUALCASE # for MKS sh
if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
emulate sh
NULLCMD=:
# Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
# is contrary to our usage. Disable this feature.
alias -g '${1+"$@"}'='"$@"'
setopt NO_GLOB_SUBST
else
case `(set -o) 2>/dev/null` in #(
*posix*) :
set -o posix ;; #(
*) :
;;
esac
fi
as_nl='
'
export as_nl
# Printing a long string crashes Solaris 7 /usr/bin/printf.
as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
# Prefer a ksh shell builtin over an external printf program on Solaris,
# but without wasting forks for bash or zsh.
if test -z "$BASH_VERSION$ZSH_VERSION" \
&& (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='print -r --'
as_echo_n='print -rn --'
elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='printf %s\n'
as_echo_n='printf %s'
else
if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
as_echo_n='/usr/ucb/echo -n'
else
as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
as_echo_n_body='eval
arg=$1;
case $arg in #(
*"$as_nl"*)
expr "X$arg" : "X\\(.*\\)$as_nl";
arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
esac;
expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
'
export as_echo_n_body
as_echo_n='sh -c $as_echo_n_body as_echo'
fi
export as_echo_body
as_echo='sh -c $as_echo_body as_echo'
fi
# The user is always right.
if test "${PATH_SEPARATOR+set}" != set; then
PATH_SEPARATOR=:
(PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
(PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
PATH_SEPARATOR=';'
}
fi
# IFS
# We need space, tab and new line, in precisely that order. Quoting is
# there to prevent editors from complaining about space-tab.
# (If _AS_PATH_WALK were called with IFS unset, it would disable word
# splitting by setting IFS to empty value.)
IFS=" "" $as_nl"
# Find who we are. Look in the path if we contain no directory separator.
case $0 in #((
*[\\/]* ) as_myself=$0 ;;
*) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
for as_dir in $PATH
do
IFS=$as_save_IFS
test -z "$as_dir" && as_dir=.
test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
done
IFS=$as_save_IFS
;;
esac
# We did not find ourselves, most probably we were run as `sh COMMAND'
# in which case we are not to be found in the path.
if test "x$as_myself" = x; then
as_myself=$0
fi
if test ! -f "$as_myself"; then
$as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
exit 1
fi
# Unset variables that we do not need and which cause bugs (e.g. in
# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
# suppresses any "Segmentation fault" message there. '((' could
# trigger a bug in pdksh 5.2.14.
for as_var in BASH_ENV ENV MAIL MAILPATH
do eval test x\${$as_var+set} = xset \
&& ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
done
PS1='$ '
PS2='> '
PS4='+ '
# NLS nuisances.
LC_ALL=C
export LC_ALL
LANGUAGE=C
export LANGUAGE
# CDPATH.
(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
# as_fn_error ERROR [LINENO LOG_FD]
# ---------------------------------
# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
# script with status $?, using 1 if that was 0.
as_fn_error ()
{
as_status=$?; test $as_status -eq 0 && as_status=1
if test "$3"; then
as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
$as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3
fi
$as_echo "$as_me: error: $1" >&2
as_fn_exit $as_status
} # as_fn_error
# as_fn_set_status STATUS
# -----------------------
# Set $? to STATUS, without forking.
as_fn_set_status ()
{
return $1
} # as_fn_set_status
# as_fn_exit STATUS
# -----------------
# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
as_fn_exit ()
{
set +e
as_fn_set_status $1
exit $1
} # as_fn_exit
# as_fn_unset VAR
# ---------------
# Portably unset VAR.
as_fn_unset ()
{
{ eval $1=; unset $1;}
}
as_unset=as_fn_unset
# as_fn_append VAR VALUE
# ----------------------
# Append the text in VALUE to the end of the definition contained in VAR. Take
# advantage of any shell optimizations that allow amortized linear growth over
# repeated appends, instead of the typical quadratic growth present in naive
# implementations.
if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
eval 'as_fn_append ()
{
eval $1+=\$2
}'
else
as_fn_append ()
{
eval $1=\$$1\$2
}
fi # as_fn_append
# as_fn_arith ARG...
# ------------------
# Perform arithmetic evaluation on the ARGs, and store the result in the
# global $as_val. Take advantage of shells that can avoid forks. The arguments
# must be portable across $(()) and expr.
if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
eval 'as_fn_arith ()
{
as_val=$(( $* ))
}'
else
as_fn_arith ()
{
as_val=`expr "$@" || test $? -eq 1`
}
fi # as_fn_arith
if expr a : '\(a\)' >/dev/null 2>&1 &&
test "X`expr 00001 : '.*\(...\)'`" = X001; then
as_expr=expr
else
as_expr=false
fi
if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
as_basename=basename
else
as_basename=false
fi
if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
as_dirname=dirname
else
as_dirname=false
fi
as_me=`$as_basename -- "$0" ||
$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
X"$0" : 'X\(//\)$' \| \
X"$0" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X/"$0" |
sed '/^.*\/\([^/][^/]*\)\/*$/{
s//\1/
q
}
/^X\/\(\/\/\)$/{
s//\1/
q
}
/^X\/\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
# Avoid depending upon Character Ranges.
as_cr_letters='abcdefghijklmnopqrstuvwxyz'
as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
as_cr_Letters=$as_cr_letters$as_cr_LETTERS
as_cr_digits='0123456789'
as_cr_alnum=$as_cr_Letters$as_cr_digits
ECHO_C= ECHO_N= ECHO_T=
case `echo -n x` in #(((((
-n*)
case `echo 'xy\c'` in
*c*) ECHO_T=' ';; # ECHO_T is single tab character.
xy) ECHO_C='\c';;
*) echo `echo ksh88 bug on AIX 6.1` > /dev/null
ECHO_T=' ';;
esac;;
*)
ECHO_N='-n';;
esac
rm -f conf$$ conf$$.exe conf$$.file
if test -d conf$$.dir; then
rm -f conf$$.dir/conf$$.file
else
rm -f conf$$.dir
mkdir conf$$.dir 2>/dev/null
fi
if (echo >conf$$.file) 2>/dev/null; then
if ln -s conf$$.file conf$$ 2>/dev/null; then
as_ln_s='ln -s'
# ... but there are two gotchas:
# 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
# 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
# In both cases, we have to default to `cp -p'.
ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
as_ln_s='cp -p'
elif ln conf$$.file conf$$ 2>/dev/null; then
as_ln_s=ln
else
as_ln_s='cp -p'
fi
else
as_ln_s='cp -p'
fi
rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
rmdir conf$$.dir 2>/dev/null
# as_fn_mkdir_p
# -------------
# Create "$as_dir" as a directory, including parents if necessary.
as_fn_mkdir_p ()
{
case $as_dir in #(
-*) as_dir=./$as_dir;;
esac
test -d "$as_dir" || eval $as_mkdir_p || {
as_dirs=
while :; do
case $as_dir in #(
*\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
*) as_qdir=$as_dir;;
esac
as_dirs="'$as_qdir' $as_dirs"
as_dir=`$as_dirname -- "$as_dir" ||
$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$as_dir" : 'X\(//\)[^/]' \| \
X"$as_dir" : 'X\(//\)$' \| \
X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$as_dir" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
test -d "$as_dir" && break
done
test -z "$as_dirs" || eval "mkdir $as_dirs"
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} # as_fn_mkdir_p
if mkdir -p . 2>/dev/null; then
as_mkdir_p='mkdir -p "$as_dir"'
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test -d ./-p && rmdir ./-p
as_mkdir_p=false
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if test -x / >/dev/null 2>&1; then
as_test_x='test -x'
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if ls -dL / >/dev/null 2>&1; then
as_ls_L_option=L
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as_ls_L_option=
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as_test_x='
eval sh -c '\''
if test -d "$1"; then
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case $1 in #(
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# Sed expression to map a string onto a valid variable name.
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exec 6>&1
## ----------------------------------- ##
## Main body of $CONFIG_STATUS script. ##
## ----------------------------------- ##
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test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1
cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# Save the log message, to keep $0 and so on meaningful, and to
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ac_log="
This file was extended by $as_me, which was
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CONFIG_FILES = $CONFIG_FILES
CONFIG_HEADERS = $CONFIG_HEADERS
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$ $0 $@
on `(hostname || uname -n) 2>/dev/null | sed 1q`
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case $ac_config_files in *"
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# Files that config.status was made for.
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cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
ac_cs_usage="\
\`$as_me' instantiates files and other configuration actions
from templates according to the current configuration. Unless the files
and actions are specified as TAGs, all are instantiated by default.
Usage: $0 [OPTION]... [TAG]...
-h, --help print this help, then exit
-V, --version print version number and configuration settings, then exit
--config print configuration, then exit
-q, --quiet, --silent
do not print progress messages
-d, --debug don't remove temporary files
--recheck update $as_me by reconfiguring in the same conditions
--file=FILE[:TEMPLATE]
instantiate the configuration file FILE
--header=FILE[:TEMPLATE]
instantiate the configuration header FILE
Configuration files:
$config_files
Configuration headers:
$config_headers
Configuration commands:
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Report bugs to the package provider."
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cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
config.status
configured by $0, generated by GNU Autoconf 2.65,
with options \\"\$ac_cs_config\\"
Copyright (C) 2009 Free Software Foundation, Inc.
This config.status script is free software; the Free Software Foundation
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ac_pwd='$ac_pwd'
srcdir='$srcdir'
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cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# The default lists apply if the user does not specify any file.
ac_need_defaults=:
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ac_option=`expr "X$1" : 'X\([^=]*\)='`
ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
ac_shift=:
;;
*)
ac_option=$1
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ac_cs_recheck=: ;;
--version | --versio | --versi | --vers | --ver | --ve | --v | -V )
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--config | --confi | --conf | --con | --co | --c )
$as_echo "$ac_cs_config"; exit ;;
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case $ac_optarg in
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--he | --h)
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as_fn_error "ambiguous option: \`$1'
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--help | --hel | -h )
$as_echo "$ac_cs_usage"; exit ;;
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ac_cs_silent=: ;;
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shift
done
ac_configure_extra_args=
if $ac_cs_silent; then
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ac_configure_extra_args="$ac_configure_extra_args --silent"
fi
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cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
if \$ac_cs_recheck; then
set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
shift
\$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6
CONFIG_SHELL='$SHELL'
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exec "\$@"
fi
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cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
exec 5>>config.log
{
echo
sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
## Running $as_me. ##
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$as_echo "$ac_log"
} >&5
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cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
#
# INIT-COMMANDS
#
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cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# Handling of arguments.
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do
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"config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;;
"depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;;
"Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;;
"doc/Makefile") CONFIG_FILES="$CONFIG_FILES doc/Makefile" ;;
"examples/Makefile") CONFIG_FILES="$CONFIG_FILES examples/Makefile" ;;
"modelgen/Makefile") CONFIG_FILES="$CONFIG_FILES modelgen/Makefile" ;;
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*) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
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done
# If the user did not use the arguments to specify the items to instantiate,
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# bizarre bug on SunOS 4.1.3.
if $ac_need_defaults; then
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test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
fi
# Have a temporary directory for convenience. Make it in the build tree
# simply because there is no reason against having it here, and in addition,
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$debug ||
{
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trap 'as_fn_exit 1' 1 2 13 15
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# Create a (secure) tmp directory for tmp files.
{
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{
tmp=./conf$$-$RANDOM
(umask 077 && mkdir "$tmp")
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# Set up the scripts for CONFIG_FILES section.
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# On cygwin, bash can eat \r inside `` if the user requested igncr.
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ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null`
if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
ac_cs_awk_cr='\r'
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ac_cs_awk_cr=$ac_cr
fi
echo 'BEGIN {' >"$tmp/subs1.awk" &&
_ACEOF
{
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as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'`
ac_delim='%!_!# '
for ac_last_try in false false false false false :; do
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as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
if test $ac_delim_n = $ac_delim_num; then
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as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
else
ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
fi
done
rm -f conf$$subs.sh
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
cat >>"\$tmp/subs1.awk" <<\\_ACAWK &&
_ACEOF
sed -n '
h
s/^/S["/; s/!.*/"]=/
p
g
s/^[^!]*!//
:repl
t repl
s/'"$ac_delim"'$//
t delim
:nl
h
s/\(.\{148\}\)..*/\1/
t more1
s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/
p
n
b repl
:more1
s/["\\]/\\&/g; s/^/"/; s/$/"\\/
p
g
s/.\{148\}//
t nl
:delim
h
s/\(.\{148\}\)..*/\1/
t more2
s/["\\]/\\&/g; s/^/"/; s/$/"/
p
b
:more2
s/["\\]/\\&/g; s/^/"/; s/$/"\\/
p
g
s/.\{148\}//
t delim
' >$CONFIG_STATUS || ac_write_fail=1
rm -f conf$$subs.awk
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
_ACAWK
cat >>"\$tmp/subs1.awk" <<_ACAWK &&
for (key in S) S_is_set[key] = 1
FS = ""
}
{
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for (i = 2; i < nfields; i++) {
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if (S_is_set[key]) {
value = S[key]
line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
len += length(value) + length(field[++i])
substed = 1
} else
len += 1 + keylen
}
print line
}
_ACAWK
_ACEOF
cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
else
cat
fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \
|| as_fn_error "could not setup config files machinery" "$LINENO" 5
_ACEOF
# VPATH may cause trouble with some makes, so we remove $(srcdir),
# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
# trailing colons and then remove the whole line if VPATH becomes empty
# (actually we leave an empty line to preserve line numbers).
if test "x$srcdir" = x.; then
ac_vpsub='/^[ ]*VPATH[ ]*=/{
s/:*\$(srcdir):*/:/
s/:*\${srcdir}:*/:/
s/:*@srcdir@:*/:/
s/^\([^=]*=[ ]*\):*/\1/
s/:*$//
s/^[^=]*=[ ]*$//
}'
fi
cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
fi # test -n "$CONFIG_FILES"
# Set up the scripts for CONFIG_HEADERS section.
# No need to generate them if there are no CONFIG_HEADERS.
# This happens for instance with `./config.status Makefile'.
if test -n "$CONFIG_HEADERS"; then
cat >"$tmp/defines.awk" <<\_ACAWK ||
BEGIN {
_ACEOF
# Transform confdefs.h into an awk script `defines.awk', embedded as
# here-document in config.status, that substitutes the proper values into
# config.h.in to produce config.h.
# Create a delimiter string that does not exist in confdefs.h, to ease
# handling of long lines.
ac_delim='%!_!# '
for ac_last_try in false false :; do
ac_t=`sed -n "/$ac_delim/p" confdefs.h`
if test -z "$ac_t"; then
break
elif $ac_last_try; then
as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5
else
ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
fi
done
# For the awk script, D is an array of macro values keyed by name,
# likewise P contains macro parameters if any. Preserve backslash
# newline sequences.
ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]*
sed -n '
s/.\{148\}/&'"$ac_delim"'/g
t rset
:rset
s/^[ ]*#[ ]*define[ ][ ]*/ /
t def
d
:def
s/\\$//
t bsnl
s/["\\]/\\&/g
s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\
D["\1"]=" \3"/p
s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p
d
:bsnl
s/["\\]/\\&/g
s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\
D["\1"]=" \3\\\\\\n"\\/p
t cont
s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p
t cont
d
:cont
n
s/.\{148\}/&'"$ac_delim"'/g
t clear
:clear
s/\\$//
t bsnlc
s/["\\]/\\&/g; s/^/"/; s/$/"/p
d
:bsnlc
s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p
b cont
' >$CONFIG_STATUS || ac_write_fail=1
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
for (key in D) D_is_set[key] = 1
FS = ""
}
/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ {
line = \$ 0
split(line, arg, " ")
if (arg[1] == "#") {
defundef = arg[2]
mac1 = arg[3]
} else {
defundef = substr(arg[1], 2)
mac1 = arg[2]
}
split(mac1, mac2, "(") #)
macro = mac2[1]
prefix = substr(line, 1, index(line, defundef) - 1)
if (D_is_set[macro]) {
# Preserve the white space surrounding the "#".
print prefix "define", macro P[macro] D[macro]
next
} else {
# Replace #undef with comments. This is necessary, for example,
# in the case of _POSIX_SOURCE, which is predefined and required
# on some systems where configure will not decide to define it.
if (defundef == "undef") {
print "/*", prefix defundef, macro, "*/"
next
}
}
}
{ print }
_ACAWK
_ACEOF
cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
as_fn_error "could not setup config headers machinery" "$LINENO" 5
fi # test -n "$CONFIG_HEADERS"
eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS"
shift
for ac_tag
do
case $ac_tag in
:[FHLC]) ac_mode=$ac_tag; continue;;
esac
case $ac_mode$ac_tag in
:[FHL]*:*);;
:L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;;
:[FH]-) ac_tag=-:-;;
:[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
esac
ac_save_IFS=$IFS
IFS=:
set x $ac_tag
IFS=$ac_save_IFS
shift
ac_file=$1
shift
case $ac_mode in
:L) ac_source=$1;;
:[FH])
ac_file_inputs=
for ac_f
do
case $ac_f in
-) ac_f="$tmp/stdin";;
*) # Look for the file first in the build tree, then in the source tree
# (if the path is not absolute). The absolute path cannot be DOS-style,
# because $ac_f cannot contain `:'.
test -f "$ac_f" ||
case $ac_f in
[\\/$]*) false;;
*) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
esac ||
as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;;
esac
case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
as_fn_append ac_file_inputs " '$ac_f'"
done
# Let's still pretend it is `configure' which instantiates (i.e., don't
# use $as_me), people would be surprised to read:
# /* config.h. Generated by config.status. */
configure_input='Generated from '`
$as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
`' by configure.'
if test x"$ac_file" != x-; then
configure_input="$ac_file. $configure_input"
{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
$as_echo "$as_me: creating $ac_file" >&6;}
fi
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case $configure_input in #(
*\&* | *\|* | *\\* )
ac_sed_conf_input=`$as_echo "$configure_input" |
sed 's/[\\\\&|]/\\\\&/g'`;; #(
*) ac_sed_conf_input=$configure_input;;
esac
case $ac_tag in
*:-:* | *:-) cat >"$tmp/stdin" \
|| as_fn_error "could not create $ac_file" "$LINENO" 5 ;;
esac
;;
esac
ac_dir=`$as_dirname -- "$ac_file" ||
$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$ac_file" : 'X\(//\)[^/]' \| \
X"$ac_file" : 'X\(//\)$' \| \
X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$ac_file" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
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s/.*/./; q'`
as_dir="$ac_dir"; as_fn_mkdir_p
ac_builddir=.
case "$ac_dir" in
.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
*)
ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
# A ".." for each directory in $ac_dir_suffix.
ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
case $ac_top_builddir_sub in
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*) ac_top_build_prefix=$ac_top_builddir_sub/ ;;
esac ;;
esac
ac_abs_top_builddir=$ac_pwd
ac_abs_builddir=$ac_pwd$ac_dir_suffix
# for backward compatibility:
ac_top_builddir=$ac_top_build_prefix
case $srcdir in
.) # We are building in place.
ac_srcdir=.
ac_top_srcdir=$ac_top_builddir_sub
ac_abs_top_srcdir=$ac_pwd ;;
[\\/]* | ?:[\\/]* ) # Absolute name.
ac_srcdir=$srcdir$ac_dir_suffix;
ac_top_srcdir=$srcdir
ac_abs_top_srcdir=$srcdir ;;
*) # Relative name.
ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
ac_top_srcdir=$ac_top_build_prefix$srcdir
ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
esac
ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
case $ac_mode in
:F)
#
# CONFIG_FILE
#
case $INSTALL in
[\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
*) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
esac
ac_MKDIR_P=$MKDIR_P
case $MKDIR_P in
[\\/$]* | ?:[\\/]* ) ;;
*/*) ac_MKDIR_P=$ac_top_build_prefix$MKDIR_P ;;
esac
_ACEOF
cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# If the template does not know about datarootdir, expand it.
# FIXME: This hack should be removed a few years after 2.60.
ac_datarootdir_hack=; ac_datarootdir_seen=
ac_sed_dataroot='
/datarootdir/ {
p
q
}
/@datadir@/p
/@docdir@/p
/@infodir@/p
/@localedir@/p
/@mandir@/p'
case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
*datarootdir*) ac_datarootdir_seen=yes;;
*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
_ACEOF
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_datarootdir_hack='
s&@datadir@&$datadir&g
s&@docdir@&$docdir&g
s&@infodir@&$infodir&g
s&@localedir@&$localedir&g
s&@mandir@&$mandir&g
s&\\\${datarootdir}&$datarootdir&g' ;;
esac
_ACEOF
# Neutralize VPATH when `$srcdir' = `.'.
# Shell code in configure.ac might set extrasub.
# FIXME: do we really want to maintain this feature?
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_sed_extra="$ac_vpsub
$extrasub
_ACEOF
cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
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/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
s|@configure_input@|$ac_sed_conf_input|;t t
s&@top_builddir@&$ac_top_builddir_sub&;t t
s&@top_build_prefix@&$ac_top_build_prefix&;t t
s&@srcdir@&$ac_srcdir&;t t
s&@abs_srcdir@&$ac_abs_srcdir&;t t
s&@top_srcdir@&$ac_top_srcdir&;t t
s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
s&@builddir@&$ac_builddir&;t t
s&@abs_builddir@&$ac_abs_builddir&;t t
s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
s&@INSTALL@&$ac_INSTALL&;t t
s&@MKDIR_P@&$ac_MKDIR_P&;t t
$ac_datarootdir_hack
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eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$tmp/subs.awk" >$tmp/out \
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test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
{ ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } &&
{ ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } &&
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
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rm -f "$tmp/stdin"
case $ac_file in
-) cat "$tmp/out" && rm -f "$tmp/out";;
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|| as_fn_error "could not create $ac_file" "$LINENO" 5
;;
:H)
#
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#
if test x"$ac_file" != x-; then
{
$as_echo "/* $configure_input */" \
&& eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs"
} >"$tmp/config.h" \
|| as_fn_error "could not create $ac_file" "$LINENO" 5
if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then
{ $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5
$as_echo "$as_me: $ac_file is unchanged" >&6;}
else
rm -f "$ac_file"
mv "$tmp/config.h" "$ac_file" \
|| as_fn_error "could not create $ac_file" "$LINENO" 5
fi
else
$as_echo "/* $configure_input */" \
&& eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \
|| as_fn_error "could not create -" "$LINENO" 5
fi
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_am_arg="$ac_file"
_am_stamp_count=1
for _am_header in $config_headers :; do
case $_am_header in
$_am_arg | $_am_arg:* )
break ;;
* )
_am_stamp_count=`expr $_am_stamp_count + 1` ;;
esac
done
echo "timestamp for $_am_arg" >`$as_dirname -- "$_am_arg" ||
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X"$_am_arg" : 'X\(//\)[^/]' \| \
X"$_am_arg" : 'X\(//\)$' \| \
X"$_am_arg" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$_am_arg" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
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;;
:C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5
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# if we detect the quoting.
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*) set x $CONFIG_FILES ;;
esac
shift
for mf
do
# Strip MF so we end up with the name of the file.
mf=`echo "$mf" | sed -e 's/:.*$//'`
# Check whether this is an Automake generated Makefile or not.
# We used to match only the files named `Makefile.in', but
# some people rename them; so instead we look at the file content.
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# each Makefile.in and add a new line on top of each file to say so.
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X"$mf" : 'X\(/\)' \| . 2>/dev/null ||
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sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
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/^X\(\/\/\)[^/].*/{
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q
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/^X\(\/\/\)$/{
s//\1/
q
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/^X\(\/\).*/{
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s/.*/./; q'`
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continue
fi
# Extract the definition of DEPDIR, am__include, and am__quote
# from the Makefile without running `make'.
DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"`
test -z "$DEPDIR" && continue
am__include=`sed -n 's/^am__include = //p' < "$mf"`
test -z "am__include" && continue
am__quote=`sed -n 's/^am__quote = //p' < "$mf"`
# When using ansi2knr, U may be empty or an underscore; expand it
U=`sed -n 's/^U = //p' < "$mf"`
# Find all dependency output files, they are included files with
# $(DEPDIR) in their names. We invoke sed twice because it is the
# simplest approach to changing $(DEPDIR) to its actual value in the
# expansion.
for file in `sed -n "
s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \
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X"$file" : 'X\(/\)' \| . 2>/dev/null ||
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sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
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q
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s/.*/./; q'`
as_dir=$dirpart/$fdir; as_fn_mkdir_p
# echo "creating $dirpart/$file"
echo '# dummy' > "$dirpart/$file"
done
done
}
;;
esac
done # for ac_tag
as_fn_exit 0
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# output is simply discarded. So we exec the FD to /dev/null,
# effectively closing config.log, so it can be properly (re)opened and
# appended to by config.status. When coming back to configure, we
# need to make the FD available again.
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ac_config_status_args=
test "$silent" = yes &&
ac_config_status_args="$ac_config_status_args --quiet"
exec 5>/dev/null
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exec 5>>config.log
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# would make configure fail if this is the last instruction.
$ac_cs_success || as_fn_exit $?
fi
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{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5
$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;}
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result:
** Configuration summary for $PACKAGE $VERSION:
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CPPFLAGS: $CPPFLAGS
CFLAGS: $CFLAGS
CXXFLAGS: $CXXFLAGS
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LIBS: $LIBS
" >&5
$as_echo "
** Configuration summary for $PACKAGE $VERSION:
prefix: $prefix
CPPFLAGS: $CPPFLAGS
CFLAGS: $CFLAGS
CXXFLAGS: $CXXFLAGS
LDFLAGS: $LDFLAGS
LIBS: $LIBS
" >&6; }
configure.ac 0000664 0000000 0000000 00000010532 11454012162 0013341 0 ustar 00root root 0000000 0000000 # -*- Autoconf -*-
# Process this file with autoconf to produce a configure script.
# $Id$
#
# COPYRIGHT
#
# Copyright (C) 2005, 2006 Dan McMahill
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
AC_PREREQ(2.59)
AC_INIT([src/main.cc])
# this is any file in the source directory
# used as a check to be sure we found it
AM_INIT_AUTOMAKE(gnucap, 2009-12-07)
AM_CONFIG_HEADER([config.h])
AM_MAINTAINER_MODE
AC_MSG_CHECKING([if debug code should be compiled in])
AC_ARG_ENABLE([debug],
[ --enable-debug Enable building of debug code. [[default: disabled]]],
[
if test "X$enable_debug" = "Xno" ; then
AC_MSG_RESULT([no])
else
AC_MSG_RESULT([yes])
enable_debug=yes
fi
],
[
AC_MSG_RESULT([no])
enable_debug=no
])
# Checks for programs.
AC_PROG_CXX
# If we are cross compiling, then we need to search for a
# gnucap-modelgen program to use for our build. This can
# either be an installed modelgen or it can be specified
# like:
# env MODELGEN=/build/i686--linux/modelgen/gnucap-modelgen /srcs/gnucap/configure
# --host=alpha--netbsd --build=i686--linux
#
if test "$cross_compiling" = yes; then
AC_PATH_PROG(MODELGEN, gnucap-modelgen)
else
MODELGEN=../modelgen/gnucap-modelgen
AC_SUBST([MODELGEN])
fi
# for building the documentation
#AC_PATH_PROG(DVIPDFM, dvipdfm, notfound)
#AM_CONDITIONAL(MISSING_DVIPDFM, test x$DVIPDFM = xnotfound)
#AC_PATH_PROG(HACHA, hacha, notfound)
#AC_PATH_PROG(HEVEA, hevea, notfound)
#AM_CONDITIONAL(MISSING_HEVEA, test x$HEVEA = xnotfound -o x$HACHA = xnotfound)
#AC_PATH_PROG(LATEX, latex, notfound)
#AC_PATH_PROG(MAKEINDEX, makeindex, notfound)
#AM_CONDITIONAL(MISSING_LATEX, test x$LATEX = xnotfound -o x$MAKEINDEX = xnotfound)
# Checks for libraries.
# this is a c++ program so use c++ for the tests
AC_LANG([C++])
#AC_CHECK_LIB([termcap], [main])
#AC_CHECK_LIB([readline], [main])
AC_ARG_WITH([readline],
[AS_HELP_STRING([--with-readline],
[support command line editing @<:@default=yes@:>@])],
[],
[with_readline=yes])
if test "x$with_readline" != xno ; then
AC_CHECK_LIB([termcap], [main])
AC_CHECK_LIB([readline], [main])
fi
AC_CHECK_LIB([dl], [dlopen])
# Checks for header files.
#AC_CHECK_HEADERS([fcntl.h unistd.h])
# Checks for typedefs, structures, and compiler characteristics.
# Checks for library functions.
if test "$enable_debug" = "yes" ; then
CPPFLAGS="$CPPFLAGS -DTRACE_UNTESTED"
else
CPPFLAGS="$CPPFLAGS -DNDEBUG"
fi
# if we have gcc and we've asked for debugging then add lots of -W
if test "x$GCC" = "xyes" -a "$enable_debug" = "yes"; then
for flag in -DTRACE_UNTESTED -Wall -W -Wno-sign-compare \
-Wpointer-arith -Wcast-qual \
-Wwrite-strings -Wconversion \
-Woverloaded-virtual -O2 -Wlong-long \
-Wsign-compare -Wcast-align ; do
case " ${CFLAGS} " in
*\ ${flag}\ *)
# flag is already present
;;
*)
CFLAGS="$CFLAGS ${flag}"
;;
esac
case " ${CXXFLAGS} " in
*\ ${flag}\ *)
# flag is already present
;;
*)
CXXFLAGS="$CXXFLAGS ${flag}"
;;
esac
done
fi
# exports symbols to plugins
LDFLAGS="$LDFLAGS -rdynamic"
#AC_OUTPUT([
# Makefile
# doc/Makefile
# examples/Makefile
# man/Makefile
# man/Addmodel/Makefile
# man/Behavior/Makefile
# man/Circuit/Makefile
# man/Commands/Makefile
# man/Tech/Makefile
# modelgen/Makefile
# src/Makefile
# ])
AC_OUTPUT([
Makefile
doc/Makefile
examples/Makefile
modelgen/Makefile
src/Makefile
])
AC_MSG_RESULT([
** Configuration summary for $PACKAGE $VERSION:
prefix: $prefix
CPPFLAGS: $CPPFLAGS
CFLAGS: $CFLAGS
CXXFLAGS: $CXXFLAGS
LDFLAGS: $LDFLAGS
LIBS: $LIBS
])
configure.old 0000775 0000000 0000000 00000001654 11454012162 0013544 0 ustar 00root root 0000000 0000000 #!/bin/sh
#---------------------------------------------------
# This stuff introduced by SDB to enable --prefix
# at configure time
# echo Input flag = $1
if test "x$1" != "x"; then
# echo Found input parameter -- $1
# Now see if the parameter is --prefix=
if test "x${1#--prefix=}" != "x$1"; then
# echo "Found --prefix in input args. Setting prefix directory."
prefix=${1#--prefix=}
else
# echo "Found unrecognized parameter in input args."
# Just use the default prefix dir.
prefix=/usr/local
fi
else
# echo "No input parameter found."
# Just use the default prefix dir
prefix=/usr/local
fi
args="--prefix=$prefix"
echo "Configuring gnucap using $args"
#---------------------------------------------------
cp Makefile.template Makefile
#echo man
#(cd man; ./configure.old $args)
echo modelgen
(cd modelgen; ./configure.old $args)
echo src
(cd src; ./configure.old $args)
echo done
exit 0
depcomp 0000775 0000000 0000000 00000037100 11454012162 0012430 0 ustar 00root root 0000000 0000000 #! /bin/sh
# depcomp - compile a program generating dependencies as side-effects
scriptversion=2005-07-09.11
# Copyright (C) 1999, 2000, 2003, 2004, 2005 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
# Originally written by Alexandre Oliva .
case $1 in
'')
echo "$0: No command. Try \`$0 --help' for more information." 1>&2
exit 1;
;;
-h | --h*)
cat <<\EOF
Usage: depcomp [--help] [--version] PROGRAM [ARGS]
Run PROGRAMS ARGS to compile a file, generating dependencies
as side-effects.
Environment variables:
depmode Dependency tracking mode.
source Source file read by `PROGRAMS ARGS'.
object Object file output by `PROGRAMS ARGS'.
DEPDIR directory where to store dependencies.
depfile Dependency file to output.
tmpdepfile Temporary file to use when outputing dependencies.
libtool Whether libtool is used (yes/no).
Report bugs to .
EOF
exit $?
;;
-v | --v*)
echo "depcomp $scriptversion"
exit $?
;;
esac
if test -z "$depmode" || test -z "$source" || test -z "$object"; then
echo "depcomp: Variables source, object and depmode must be set" 1>&2
exit 1
fi
# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po.
depfile=${depfile-`echo "$object" |
sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`}
tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`}
rm -f "$tmpdepfile"
# Some modes work just like other modes, but use different flags. We
# parameterize here, but still list the modes in the big case below,
# to make depend.m4 easier to write. Note that we *cannot* use a case
# here, because this file can only contain one case statement.
if test "$depmode" = hp; then
# HP compiler uses -M and no extra arg.
gccflag=-M
depmode=gcc
fi
if test "$depmode" = dashXmstdout; then
# This is just like dashmstdout with a different argument.
dashmflag=-xM
depmode=dashmstdout
fi
case "$depmode" in
gcc3)
## gcc 3 implements dependency tracking that does exactly what
## we want. Yay! Note: for some reason libtool 1.4 doesn't like
## it if -MD -MP comes after the -MF stuff. Hmm.
"$@" -MT "$object" -MD -MP -MF "$tmpdepfile"
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
mv "$tmpdepfile" "$depfile"
;;
gcc)
## There are various ways to get dependency output from gcc. Here's
## why we pick this rather obscure method:
## - Don't want to use -MD because we'd like the dependencies to end
## up in a subdir. Having to rename by hand is ugly.
## (We might end up doing this anyway to support other compilers.)
## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like
## -MM, not -M (despite what the docs say).
## - Using -M directly means running the compiler twice (even worse
## than renaming).
if test -z "$gccflag"; then
gccflag=-MD,
fi
"$@" -Wp,"$gccflag$tmpdepfile"
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
rm -f "$depfile"
echo "$object : \\" > "$depfile"
alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz
## The second -e expression handles DOS-style file names with drive letters.
sed -e 's/^[^:]*: / /' \
-e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile"
## This next piece of magic avoids the `deleted header file' problem.
## The problem is that when a header file which appears in a .P file
## is deleted, the dependency causes make to die (because there is
## typically no way to rebuild the header). We avoid this by adding
## dummy dependencies for each header file. Too bad gcc doesn't do
## this for us directly.
tr ' ' '
' < "$tmpdepfile" |
## Some versions of gcc put a space before the `:'. On the theory
## that the space means something, we add a space to the output as
## well.
## Some versions of the HPUX 10.20 sed can't process this invocation
## correctly. Breaking it into two sed invocations is a workaround.
sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
hp)
# This case exists only to let depend.m4 do its work. It works by
# looking at the text of this script. This case will never be run,
# since it is checked for above.
exit 1
;;
sgi)
if test "$libtool" = yes; then
"$@" "-Wp,-MDupdate,$tmpdepfile"
else
"$@" -MDupdate "$tmpdepfile"
fi
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
rm -f "$depfile"
if test -f "$tmpdepfile"; then # yes, the sourcefile depend on other files
echo "$object : \\" > "$depfile"
# Clip off the initial element (the dependent). Don't try to be
# clever and replace this with sed code, as IRIX sed won't handle
# lines with more than a fixed number of characters (4096 in
# IRIX 6.2 sed, 8192 in IRIX 6.5). We also remove comment lines;
# the IRIX cc adds comments like `#:fec' to the end of the
# dependency line.
tr ' ' '
' < "$tmpdepfile" \
| sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' | \
tr '
' ' ' >> $depfile
echo >> $depfile
# The second pass generates a dummy entry for each header file.
tr ' ' '
' < "$tmpdepfile" \
| sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \
>> $depfile
else
# The sourcefile does not contain any dependencies, so just
# store a dummy comment line, to avoid errors with the Makefile
# "include basename.Plo" scheme.
echo "#dummy" > "$depfile"
fi
rm -f "$tmpdepfile"
;;
aix)
# The C for AIX Compiler uses -M and outputs the dependencies
# in a .u file. In older versions, this file always lives in the
# current directory. Also, the AIX compiler puts `$object:' at the
# start of each line; $object doesn't have directory information.
# Version 6 uses the directory in both cases.
stripped=`echo "$object" | sed 's/\(.*\)\..*$/\1/'`
tmpdepfile="$stripped.u"
if test "$libtool" = yes; then
"$@" -Wc,-M
else
"$@" -M
fi
stat=$?
if test -f "$tmpdepfile"; then :
else
stripped=`echo "$stripped" | sed 's,^.*/,,'`
tmpdepfile="$stripped.u"
fi
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
if test -f "$tmpdepfile"; then
outname="$stripped.o"
# Each line is of the form `foo.o: dependent.h'.
# Do two passes, one to just change these to
# `$object: dependent.h' and one to simply `dependent.h:'.
sed -e "s,^$outname:,$object :," < "$tmpdepfile" > "$depfile"
sed -e "s,^$outname: \(.*\)$,\1:," < "$tmpdepfile" >> "$depfile"
else
# The sourcefile does not contain any dependencies, so just
# store a dummy comment line, to avoid errors with the Makefile
# "include basename.Plo" scheme.
echo "#dummy" > "$depfile"
fi
rm -f "$tmpdepfile"
;;
icc)
# Intel's C compiler understands `-MD -MF file'. However on
# icc -MD -MF foo.d -c -o sub/foo.o sub/foo.c
# ICC 7.0 will fill foo.d with something like
# foo.o: sub/foo.c
# foo.o: sub/foo.h
# which is wrong. We want:
# sub/foo.o: sub/foo.c
# sub/foo.o: sub/foo.h
# sub/foo.c:
# sub/foo.h:
# ICC 7.1 will output
# foo.o: sub/foo.c sub/foo.h
# and will wrap long lines using \ :
# foo.o: sub/foo.c ... \
# sub/foo.h ... \
# ...
"$@" -MD -MF "$tmpdepfile"
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile"
exit $stat
fi
rm -f "$depfile"
# Each line is of the form `foo.o: dependent.h',
# or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'.
# Do two passes, one to just change these to
# `$object: dependent.h' and one to simply `dependent.h:'.
sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile"
# Some versions of the HPUX 10.20 sed can't process this invocation
# correctly. Breaking it into two sed invocations is a workaround.
sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" |
sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
tru64)
# The Tru64 compiler uses -MD to generate dependencies as a side
# effect. `cc -MD -o foo.o ...' puts the dependencies into `foo.o.d'.
# At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put
# dependencies in `foo.d' instead, so we check for that too.
# Subdirectories are respected.
dir=`echo "$object" | sed -e 's|/[^/]*$|/|'`
test "x$dir" = "x$object" && dir=
base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'`
if test "$libtool" = yes; then
# With Tru64 cc, shared objects can also be used to make a
# static library. This mecanism is used in libtool 1.4 series to
# handle both shared and static libraries in a single compilation.
# With libtool 1.4, dependencies were output in $dir.libs/$base.lo.d.
#
# With libtool 1.5 this exception was removed, and libtool now
# generates 2 separate objects for the 2 libraries. These two
# compilations output dependencies in in $dir.libs/$base.o.d and
# in $dir$base.o.d. We have to check for both files, because
# one of the two compilations can be disabled. We should prefer
# $dir$base.o.d over $dir.libs/$base.o.d because the latter is
# automatically cleaned when .libs/ is deleted, while ignoring
# the former would cause a distcleancheck panic.
tmpdepfile1=$dir.libs/$base.lo.d # libtool 1.4
tmpdepfile2=$dir$base.o.d # libtool 1.5
tmpdepfile3=$dir.libs/$base.o.d # libtool 1.5
tmpdepfile4=$dir.libs/$base.d # Compaq CCC V6.2-504
"$@" -Wc,-MD
else
tmpdepfile1=$dir$base.o.d
tmpdepfile2=$dir$base.d
tmpdepfile3=$dir$base.d
tmpdepfile4=$dir$base.d
"$@" -MD
fi
stat=$?
if test $stat -eq 0; then :
else
rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4"
exit $stat
fi
for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4"
do
test -f "$tmpdepfile" && break
done
if test -f "$tmpdepfile"; then
sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile"
# That's a tab and a space in the [].
sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile"
else
echo "#dummy" > "$depfile"
fi
rm -f "$tmpdepfile"
;;
#nosideeffect)
# This comment above is used by automake to tell side-effect
# dependency tracking mechanisms from slower ones.
dashmstdout)
# Important note: in order to support this mode, a compiler *must*
# always write the preprocessed file to stdout, regardless of -o.
"$@" || exit $?
# Remove the call to Libtool.
if test "$libtool" = yes; then
while test $1 != '--mode=compile'; do
shift
done
shift
fi
# Remove `-o $object'.
IFS=" "
for arg
do
case $arg in
-o)
shift
;;
$object)
shift
;;
*)
set fnord "$@" "$arg"
shift # fnord
shift # $arg
;;
esac
done
test -z "$dashmflag" && dashmflag=-M
# Require at least two characters before searching for `:'
# in the target name. This is to cope with DOS-style filenames:
# a dependency such as `c:/foo/bar' could be seen as target `c' otherwise.
"$@" $dashmflag |
sed 's:^[ ]*[^: ][^:][^:]*\:[ ]*:'"$object"'\: :' > "$tmpdepfile"
rm -f "$depfile"
cat < "$tmpdepfile" > "$depfile"
tr ' ' '
' < "$tmpdepfile" | \
## Some versions of the HPUX 10.20 sed can't process this invocation
## correctly. Breaking it into two sed invocations is a workaround.
sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
dashXmstdout)
# This case only exists to satisfy depend.m4. It is never actually
# run, as this mode is specially recognized in the preamble.
exit 1
;;
makedepend)
"$@" || exit $?
# Remove any Libtool call
if test "$libtool" = yes; then
while test $1 != '--mode=compile'; do
shift
done
shift
fi
# X makedepend
shift
cleared=no
for arg in "$@"; do
case $cleared in
no)
set ""; shift
cleared=yes ;;
esac
case "$arg" in
-D*|-I*)
set fnord "$@" "$arg"; shift ;;
# Strip any option that makedepend may not understand. Remove
# the object too, otherwise makedepend will parse it as a source file.
-*|$object)
;;
*)
set fnord "$@" "$arg"; shift ;;
esac
done
obj_suffix="`echo $object | sed 's/^.*\././'`"
touch "$tmpdepfile"
${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@"
rm -f "$depfile"
cat < "$tmpdepfile" > "$depfile"
sed '1,2d' "$tmpdepfile" | tr ' ' '
' | \
## Some versions of the HPUX 10.20 sed can't process this invocation
## correctly. Breaking it into two sed invocations is a workaround.
sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile"
rm -f "$tmpdepfile" "$tmpdepfile".bak
;;
cpp)
# Important note: in order to support this mode, a compiler *must*
# always write the preprocessed file to stdout.
"$@" || exit $?
# Remove the call to Libtool.
if test "$libtool" = yes; then
while test $1 != '--mode=compile'; do
shift
done
shift
fi
# Remove `-o $object'.
IFS=" "
for arg
do
case $arg in
-o)
shift
;;
$object)
shift
;;
*)
set fnord "$@" "$arg"
shift # fnord
shift # $arg
;;
esac
done
"$@" -E |
sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \
-e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' |
sed '$ s: \\$::' > "$tmpdepfile"
rm -f "$depfile"
echo "$object : \\" > "$depfile"
cat < "$tmpdepfile" >> "$depfile"
sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile"
rm -f "$tmpdepfile"
;;
msvisualcpp)
# Important note: in order to support this mode, a compiler *must*
# always write the preprocessed file to stdout, regardless of -o,
# because we must use -o when running libtool.
"$@" || exit $?
IFS=" "
for arg
do
case "$arg" in
"-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI")
set fnord "$@"
shift
shift
;;
*)
set fnord "$@" "$arg"
shift
shift
;;
esac
done
"$@" -E |
sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::echo "`cygpath -u \\"\1\\"`":p' | sort | uniq > "$tmpdepfile"
rm -f "$depfile"
echo "$object : \\" > "$depfile"
. "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s:: \1 \\:p' >> "$depfile"
echo " " >> "$depfile"
. "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s::\1\::p' >> "$depfile"
rm -f "$tmpdepfile"
;;
none)
exec "$@"
;;
*)
echo "Unknown depmode $depmode" 1>&2
exit 1
;;
esac
exit 0
# Local Variables:
# mode: shell-script
# sh-indentation: 2
# eval: (add-hook 'write-file-hooks 'time-stamp)
# time-stamp-start: "scriptversion="
# time-stamp-format: "%:y-%02m-%02d.%02H"
# time-stamp-end: "$"
# End:
doc/ 0000775 0000000 0000000 00000000000 11454012162 0011617 5 ustar 00root root 0000000 0000000 doc/COPYING 0000664 0000000 0000000 00000043122 11454012162 0012654 0 ustar 00root root 0000000 0000000 GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Library General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must give the recipients all the rights that
you have. You must make sure that they, too, receive or can get the
source code. And you must show them these terms so they know their
rights.
We protect your rights with two steps: (1) copyright the software, and
(2) offer you this license which gives you legal permission to copy,
distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain
that everyone understands that there is no warranty for this free
software. If the software is modified by someone else and passed on, we
want its recipients to know that what they have is not the original, so
that any problems introduced by others will not reflect on the original
authors' reputations.
Finally, any free program is threatened constantly by software
patents. We wish to avoid the danger that redistributors of a free
program will individually obtain patent licenses, in effect making the
program proprietary. To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
parties under the terms of this License.
c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
a storage or distribution medium does not bring the other work under
the scope of this License.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
machine-readable copy of the corresponding source code, to be
distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer
to distribute corresponding source code. (This alternative is
allowed only for noncommercial distribution and only if you
received the program in object code or executable form with such
an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for
making modifications to it. For an executable work, complete source
code means all the source code for all modules it contains, plus any
associated interface definition files, plus the scripts used to
control compilation and installation of the executable. However, as a
special exception, the source code distributed need not include
anything that is normally distributed (in either source or binary
form) with the major components (compiler, kernel, and so on) of the
operating system on which the executable runs, unless that component
itself accompanies the executable.
If distribution of executable or object code is made by offering
access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
void, and will automatically terminate your rights under this License.
However, parties who have received copies, or rights, from you under
this License will not have their licenses terminated so long as such
parties remain in full compliance.
5. You are not required to accept this License, since you have not
signed it. However, nothing else grants you permission to modify or
distribute the Program or its derivative works. These actions are
prohibited by law if you do not accept this License. Therefore, by
modifying or distributing the Program (or any work based on the
Program), you indicate your acceptance of this License to do so, and
all its terms and conditions for copying, distributing or modifying
the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the
Program), the recipient automatically receives a license from the
original licensor to copy, distribute or modify the Program subject to
these terms and conditions. You may not impose any further
restrictions on the recipients' exercise of the rights granted herein.
You are not responsible for enforcing compliance by third parties to
this License.
7. If, as a consequence of a court judgment or allegation of patent
infringement or for any other reason (not limited to patent issues),
conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot
distribute so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you
may not distribute the Program at all. For example, if a patent
license would not permit royalty-free redistribution of the Program by
all those who receive copies directly or indirectly through you, then
the only way you could satisfy both it and this License would be to
refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under
any particular circumstance, the balance of the section is intended to
apply and the section as a whole is intended to apply in other
circumstances.
It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the free software distribution system, which is
implemented by public license practices. Many people have made
generous contributions to the wide range of software distributed
through that system in reliance on consistent application of that
system; it is up to the author/donor to decide if he or she is willing
to distribute software through any other system and a licensee cannot
impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
may add an explicit geographical distribution limitation excluding
those countries, so that distribution is permitted only in or among
countries not thus excluded. In such case, this License incorporates
the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and conditions
either of that version or of any later version published by the Free
Software Foundation. If the Program does not specify a version number of
this License, you may choose any version ever published by the Free Software
Foundation.
10. If you wish to incorporate parts of the Program into other free
programs whose distribution conditions are different, write to the author
to ask for permission. For software which is copyrighted by the Free
Software Foundation, write to the Free Software Foundation; we sometimes
make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
Copyright (C)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General
Public License instead of this License.
doc/INSTALL 0000664 0000000 0000000 00000005001 11454012162 0012644 0 ustar 00root root 0000000 0000000 GnuCap 0.30 installation instructions (10/29/2001)
For this version, you can use either the GNU style "configure;make"
style build process, or the old ACS style. If it works for you, use
the GNU style.
For the GNU style build, just type "./configure" then "make" from the
project's root directory. This will configure both the model compiler
and the simulator, and then build the model compiler first, then use
it to build the simulator. That should be all that is needed. You do
not to read any further.
It that doesn't work for you, a two step manual configuration may be
required. First you build the model compiler, then you build the
simulator. You can usually get away with only building the simulator.
So ..
cd to modelgen, type make (as below)
then go back down and cd to src, type make (as below)
If it fails, go into its build directory (the one containing the .o
files) and manually create a symbolic link to the model compiler.
"Type make" really means ......
Usually, you can just type "make". This will make a "release"
version, with optimization on and extra debug code out. It will build
in the O subdirectory. This assumes you have g++ in a reasonable
configuration.
To make a "debug" version (slow, with additional error checking), type
"make debug". If you have a recent g++ compiler, this should build it
in the O-DEBUG subdirectory.
If your compiler is not g=++, but called by "CC", try "make CC". This
is believed to work with some compilers. Some of them do not
implement the full language, so they cannot be used. Try it. There
is a special one "sun4-CC" for a Sun running Solaris with the most
recent version of Sun's compiler. It will not work with older
versions.
To make a "release" version for a particular system, type make
followed by your system type, such as "make linux". This will build
it in a subdirectory (in this case LINUX). With this method, you can
build for multiple systems in the same directory.
Look at "Makefile" for a list of supported systems, and clues of how
to do it on others. Most of them have not been tried in years.
If it doesn't work, edit only a "Make2.*" file, and possibly md.h or
md.cc. All nonportabilities are confined to these files.
It does require a recent and proper C++ compiler with a proper
library, including STL. Gnu compilers older than 2.8 will probably
not work. Anything else that old will also probably not work. Any
high quality C++ compiler available today should work.
To install ....
Just move or copy the executable to where you want it.
doc/Makefile.am 0000664 0000000 0000000 00000000350 11454012162 0013651 0 ustar 00root root 0000000 0000000 ## $Id$
##
dist_man_MANS= gnucap.1 gnucap-ibis.1
pkgdocsdir= ${pkgdatadir}/doc
dist_pkgdocs_DATA= \
acs-tutorial COPYING history INSTALL relnotes.029 \
relnotes.030 relnotes.031 relnotes.032 relnotes.033 relnotes.034 whatisit
doc/Makefile.in 0000664 0000000 0000000 00000032272 11454012162 0013672 0 ustar 00root root 0000000 0000000 # Makefile.in generated by automake 1.11 from Makefile.am.
# @configure_input@
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
# Inc.
# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.
@SET_MAKE@
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# Tell versions [3.59,3.63) of GNU make to not export all variables.
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doc/acs-tutorial 0000664 0000000 0000000 00000074711 11454012162 0014163 0 ustar 00root root 0000000 0000000 Tutorial for acs V0.02
Copyright 1999 Telford Tendys
>>> Introduction
This is not an alternative to reading the acs manual. The manual is
very nicely presented in LaTeX and you should print it out and keep
it handy when working with acs. This document is organised starting
from easy and working towards difficult and presumes that you have some
idea of what electrical circuits are but don't know much about simulators.
The acs manual is organised in alphabetical order and in groups of concepts
and it presumes that you know SPICE already.
>>> The basic concept of a nodal analysis.
Using nodes is one way to describe a lumped element circuit.
Lumped elements are used because there is no consideration of what is
occuring inside a given component, only what is happening on the terminals
of the component. For example, this analysis makes no attempt to find the
voltage in the middle of a resistor, only at the ends of the resistor.
The whole circuit model consists of ``nodes'' and ``components''.
A node is (electrically speaking) a single point, it has exactly one voltage
value at any given time value. A component will connect to two or more nodes
(usually two) and represents some method by which the voltages at those nodes
affect one another. Describing which components connect to which nodes will
completely describe the structure of the circuit.
One additional concept is a ``branch''. The current though a branch is the
amount of current flowing from a node into a component that connects to that
node. Some branch currents (such as the current through a voltage source)
are explicitly calcualted, others (such as the current through a resistor) are
implicitly calculated as a result of calculating the node voltages.
>>> The basic concept of a circuit file.
Tradition has it that acs input files have the extension ``.ckt''. The
format is similar to that used by version 2 of the SPICE simulator; it
is a line oriented format with items separated by whitespace. The overall
file structure is:
* Header line (first line of the file) contains the name of
the circuit, traditionally in all capitals.
* blank lines do nothing
* comment lines are any line beginning with a star ``*''.
These can be anywhere in the file except the header line.
* component lines begin with a letter and represent some component
that is in the circuit. The order that components are listed
does not matter because the topology is described by the nodes
that the components are connected to.
* continuation lines begin with a plus ``+'' and continue the
previous line so that long lines can be written neatly.
* command lines begin with a dot ``.'' and are not considered
to be part of the circuit, they cause the simulator to execute
some analysis or change some options. They are also used to
delimit special parts of the file such as subcircuits.
>>> The simplest possible circuit file
--------------------------------------------------------------------- eg1.ckt
RESISTOR DRIVEN BY VOLTAGE SOURCE
Vsupply 0 2 10
R1 0 2 1k
----------------------------------------------------------------------
This file defines a circuit containing two nodes and two components.
The components have the names ``Vsupply'' and ``R1'', the first letter of
the component name tells what that component is so ``Vsupply'' is a voltage
source and ``R1'' is a resistor. Each component has a value, the voltage
source is 10 volts and the resistor is 1000 ohms. The nodes have the
numbers ``0'' and ``2''. Note that there is no node ``1'' but this doesn't
matter, not every node number needs to be used. Like SPICE version 2 (but
unlike version 3) nodes must be numbered in acs.
In order to load this circuit into the simulator the following command
would be used:
acs eg1.ckt
What happens is that acs loads in the circuit, finds no commands to execute
(since this file has no command lines) and so enters interactive mode with
a ``-->'' prompt. From the interactive mode it is possible to exercise the
circuit model, firstly by putting a probe on the node that needs measuring
(using the print statement) then by starting the simulation:
print dc v(2)
dc
Needless to say, ``dc'' is a steady state direct current analysis and
the ``print'' command used here is saying, ``when you do a DC analysis,
tell me the voltage at node 2''. The result should be -10 volts. At
first glance, it might seem like it should be 10 volts... but (same as SPICE)
the voltage sources are listed with their positive terminal first, then
their negative terminal. Node 0 is the ground node (or reference node) which
is always 0 volts so node 2 is at -10 volts. Wiring ``Vsupply'' the other way
around would change the answer to 10 volts. Things get trickier when dealing
with current sources where the node at the tail end of the current source
arrow is listed first (and called ``+'') and the pointy head end of the arrow
is listed second (and called ``-''). Although this convention may seem
disorienting to someone who was brought up testing their circuits with
batteries or a bench power supply and poking their meter probes into things,
it is a well established SPICE convention and probably never going to change.
However, the voltage of the node may not be the answer required. What about
the current going through the source? We can move our probe to look at
current instead:
print dc i(R1) i(Vsupply)
dc
Now we can see 10 milliamps going through both components, note the sign
convention when probing current; once more this is something that you must
simply learn, you might draw diagrams of the main components and mark the
important conventions of [+] terminal, [-] terminal and current flow.
You might also realise that this convention does have its own logical
consistency which makes it easier to remember. For example, consider a
resistor: the terminal called [+] is listed first and the internal current
flow is positive when current flows into the [+] terminal, through the
resistor and out of the [-] terminal. In the case of a resistor this sounds
quite sensible because the [+] terminal WOULD be more positive when
the current flows in this manner. The sources merely maintain the same
convention as is applied to a resistor, what is important to remember is
that [+] and [-] terminals are just names that provide a sign convention
they don't insist that one terminal is a higher voltage than the other.
This example should provide enough information for analysis of any network
of voltage sources and resistors and for inspection of any current or voltage
in such a circuit. The power and resistance of each component can be measured:
print dc p(R1) p(Vsupply) r(R1) r(Vsupply)
dc
quit
Note that the supply shows negative power to it is putting power into
the system while the resistor shows positive power meaning that it is
taking power out of the system. Also notice that the resistance measurement
will attempt to find the resistance of the source without error but the
resulting value is huge (this seems wrong, I would expect it to be zero).
>>> Networks of Resistors and Sources
The previous example covers enough concepts to model arbitrarily complex
networks of resistors and sources. These are essentially linear circuits
that have no relation to time. A more elaborate example is presented below:
--------------------------------------------------------------------- eg2.ckt
NETWORK OF RESISTORS AND VOLTAGE SOURCES
V1 2 1 10
V2 4 3 5
V3 0 3 3
R1 1 2 220
R2 2 3 4.7k
R3 4 5 3k3
R4 3 5 10k
R5 0 1 22k
R6 0 5 15k
----------------------------------------------------------------------
Run this with:
acs eg2.ckt
print dc v(1) v(2) v(3) v(4) v(5)
dc
quit
Note that this is about the limit of what can be done with these two
components. Other components that offer further possibilities are
the current source (any component with a name that begins with ``I''
is a current source) and the dependent sources:
first letter output input
of name type type
-----------------------------------------
E voltage voltage
F current current
G current voltage
H voltage current
-----------------------------------------
Each of these has a gain value expressing the relation between its
output and its input and they allow the modeling of linear amplifiers
and other such devices. As mentioned above, none of these components
understand time nor can they be used to represent a nonlinear device.
Thus, any network constructed from the components that have been seen
so far will be reducible to a Thevenin or Norton equivalent circuit
when considered from the point of view of one particular node and the
ground node 0.
--------------------------------------------------------------------- eg3.ckt
NETWORK OF RESISTORS AND DEPENDENT SOURCES
*
* Reduce this complicated collection of dependencies
* down to a single Thevenin equivalent between node 2 and
* the ground node 0
*
I1 1 4 2
V1 1 0 5
E1 5 2 1 3 0.4
F1 5 6 R1 3e-2
G1 2 3 4 6 1.3
H1 3 0 R3 1
R1 4 5 2.2
R2 1 2 470
R3 0 2 330
R4 3 6 1k
R5 5 6 1e4
*
* Look at the voltage at node 2 and the impedance looking into node 2
*
.print dc v(2) z(2)
.dc
.end
----------------------------------------------------------------------
Notice that this example file contains some lines that begin with a dot.
These are command lines and behave exactly like the commands you type
in interactive mode. These command lines are dotted because of the old
SPICE tradition of executing all of the component lines first and then
the command lines, acs doesn't bother with this, it executes every line
in the order that it sees them, but it still follows the old idea of dotting
the command lines as a little tribute to SPICE and to make it easier to
see what is going on when you read a .ckt file.
When you run this example, you might try:
acs eg3.ckt
And (all going well) you will see that node 2 is equivalent to a
source of 54.343 volts in series with an 0.83888 ohm resistor.
You should also notice that acs never goes into interactive command mode.
This is because of the ``.end'' command that tells acs to finish at this point.
You may want to use this example circuit in interactive mode, to achieve this
you could either delete the .end command, or (from the system prompt) type:
acs
get eg3.ckt
Then you can use other interactive commands. Note that you can modify the
circuit interactively too. Consider adding another resistor by typing the
following at the acs interactive prompt:
build R3
R6 3 4 12k
Which allows you to adjust the topology of the circuit in memory. This
includes adding components and modifying existing components. You can
interactively remove components from the circuit using the ``delete'' command
or you can wipe out the entire circuit using the ``clear'' command.
To put the adjusted topology into a file you use the save command:
save eg3_mod.ckt
quit
cat eg3_mod.ckt
Looking at what you have saved you will probably notice a few things:
firstly, acs has remembered your comment lines and command lines and
saved them too; secondly, your extra line was inserted into the file
before the line containing component ``R3'', this is caused by the
argument on the ``build'' command and allows you to insert your build
lines where you want them.
>>> Things That Can Go Wrong
--------------------------------------------------------------------- eg4.ckt
VOLTAGE SOURCES IN PARALLEL
V1 1 0 10.0
V2 1 0 10.2
.print dc v(1) i(V1) i(V2)
.dc
.end
----------------------------------------------------------------------
Here we have V1 and V2 both driving the same node at about 10 volts.
Actually, V2 is very slightly higher than 10 volts so there will be
some argument between V1 and V2 as to exactly what the final voltage
at node 1 really is. You should see that huge currents are flowing
through the supplies (10,000 amps) just due to this small voltage
difference. Also note that acs does not throw in the towel and give
up, nor does it fail to converge... the answer that it gets for v(1)
is a compromise, halfway between the two sources.
What is does is introduce a slight imperfection in the voltage sources
so that they do have a small internal series resistor. This allows it
to make the best guess that it can in a difficult situation. How much is
this resistance? You can find out like so:
acs
options
Look at the value of the option called ``short'' (near the middle of
the block of options), this is the value (in ohms) of the internal
resistance of a voltage source. The ``u'' character means ``micro''
or 1e-6 so the default value of a short circuit is 1e-5 ohms. You
might decide that a different short circuit value is more appropriate
for running the above circuit so you can type (from the acs prompt):
options short=0.5
get eg4.ckt
dc
exit
Which should show you the same voltage (10.1) but now the current
has reduced to only one fifth of an Amp (still not small but a lot
more reasonable if you were building this with real supplies).
Other option values can be altered in much the same way and input
files can contain ``.options'' command lines in order to set these
options whenever the circuit is loaded.
--------------------------------------------------------------------- eg5.ckt
CURRENT SOURCES IN SERIES
I1 0 1 2.0001
I2 1 0 2.0
.print dc v(1) i(I1) i(I2)
.dc
.end
----------------------------------------------------------------------
The case of putting two current sources in series is much the same
concept as two voltage sources in parallel. However notice that acs
copes with it in a different manner. It cannot find a compromise current
that is partway between the two sources and it always gives a huge
value for the voltage at node 1. At least it doesn't crash and it does
give results that give some suggestion as to where the problem might
be. There is no option that introduces resistance into a current
source but you can explicitly add these resistors if you like by putting
the resistor in parallel with the current source.
What if you had a big, complex circuit, you messed up by putting
two current sources in series but you never thought about checking
the strange node? How would you ever know that the circuit was broken?
Try this exercise:
acs
get eg5.ckt
alarm dc v(*)(-1e3,1e3)
dc
quit
Now you get a warning whenever any component gets more that 1000 volts
across it. This can be used to test component breakdown if you know
that you are using components that cannot tolerate high voltages. It can
also be used to ensure that your simulated circuit stays within what you
might expect to be the absolute maximum values.
>>> Nonlinear Devices -- Diodes
All of the previous circuits have been linear. This is to say that all
the devices (voltage sources, current sources, dependent source and
resistors) are linear devices and the overall ``shape'' of the problem
does not change as the values of the system are scaled up or down.
For example, if a circuit is solved once, then after that all of the voltage
sources in the circuit are doubled, the circuit doesn't need to be solved
a second time because all the node voltages will merely be double those
of the first solution. Try it yourself if you disbelieve.
Linear circuits also obey the principle of ``superposition'' which is
to say that the circuit can be solved for each source separately and
then all of those solutions can be added up to get the solution of a
circuit containing many sources. A textbook in basic circuit theory will
explain superposition in linear circuits and you can try working through
the textbook examples on the simulator using what has been explained so far.
At this point, we take the step into nonlinear circuits which do NOT
obey superposition and do NOT scale. The most elementary nonlinear
component is a diode.
--------------------------------------------------------------------- eg6.ckt
DIODE CASCADE
.model 1N414 D IS=2e-14
Vcc 1 0 5
Dx 1 10 1N414
Dy 10 20 1N414
Dz 20 30 1N414
Rd1 10 0 1k
Rd2 20 0 1k
Rd3 30 0 1k
.print dc v(10) v(20) v(30)
.dc Vcc 0 5 0.5 >eg6.dat
.end
----------------------------------------------------------------------
You can run this example and look at the results like so:
acs eg6.ckt
gnuplot
set data style lines
plot 'eg6.dat' using 1:2, 'eg6.dat' using 1:3, 'eg6.dat' using 1:4
exit
You may not like using gnuplot and may prefer some other plotting program
such as gwave or gle. Acs output can be used by most plotting programs
in much the same manner as above by using the redirection arrow on the
command that runs the simulation (``dc'' in this case). Note that it usually
won't work to redirect the normal output to a file using your shell and then
cut and paste that output into your plotting program because the normal output
does not use standard scientific notation, using the internal redirection
option provided by acs also guarantees you get a nice, portable data file
in standard exponential notation.
If the above did work you should have been able to see the node voltages
as a function of supply voltage and see the diodes move into their conductive
band one by one. And see the traditional 0.7 volt drop across each diode.
However, various diodes behave differently so acs needs to know what sort
of diode you are using. That is what the ``.model'' command line is doing
for you -- it associated parameters in the diode model with a name that
you choose to assign to your diodes. (By the way, I have no idea what the
true measured parameters are for a real 1N414).
>>> Multiplying Two Voltages Using Diode Nonlinearity
The above example shows diode voltage drop behaviour but the diode can
also be used as an exponential function. In this example, a group of
diodes are used to construct a voltage multiplier. Most circuit components
add and subtract voltages and currents but multiplication is a bit special.
What is done in this circuit is to use the exponential behaviour of the
diodes to take the logarithm of two input voltages, then add those up and
use another diode to find the exponential of the sum. This works in the same
way as a slide rule does.
--------------------------------------------------------------------- eg7.ckt
MULTILPLY TWO NUMBERS
.subckt multiplier 1 2 3
* 1 = input A (voltage)
* 2 = input B (voltage)
* 3 = output (voltage)
* Note that there are scaling factors on inputs and output to keep
* diodes in the exponential region.
.model dexp D EG=0 CJ=0 FC=0 gparallel=0
G1 0 4 1 0 1e-3
D1 4 0 dexp
G2 0 5 2 0 1e-3
D2 5 0 dexp
I3 0 6 1
D3 6 0 dexp
E1 7 0 4 0 1
E2 8 7 5 0 1
E3 8 9 6 0 1
V1 9 10 0
D4 10 0 dexp
H1 3 0 V1 1e6
.ends
V1 1 0 0
V2 2 0 0.5
X1 1 2 3 multiplier
R1 3 0 1
.options vmin=-1e5 vmax=1e5
.print dc V(3) V(2) V(E1.X1) V(E2.X1) V(E3.X1)
.!rm eg7_1.dat eg7_2.dat eg7_3.dat
.dc v1 0 1 0.01 > eg7_1.dat QUIET
.modify V2=100
.dc v1 0 1 0.01 > eg7_2.dat QUIET
.dc v1 0 1000 1 > eg7_3.dat QUIET
.end
---------------------------------------------------------------------
This example does not attempt to go beyond the multiplication of two
numbers, using the DC sweep to test a few ranges of the inputs.
The output files can be plotted to check the linearity of the outputs.
If you wanted to build a real circuit to perform analog multiplication,
you would need something a lot more complex than the above example
because the dependent voltage and current sources used in this example
would not be possible to construct in a real circuit.
Even with those ideal simulator components available, this example will
still only multiply correctly within a limited range. Using it outside
that range requires adjustment of the input and output scaling factors
so that the diodes themselves stay close to exponential functions.
This example introduces the concept of a subcircuit which is like a macro
facility for circuit simulation. The subcircuit is contained between the
``.subckt'' and ``.ends'' lines and nodes within the subcircuit can use their
own numbering, independent of the outside world. The subcircuit gets a
name (in this case ``multiplier'') and the component ``X1'' becomes an
instance of that subcircuit. Note the way that probes can be put on devices
inside the subcircuit, for example ``E1.X1'' refers to the sub-component
named ``E1'' inside the subcircuit ``X1''.
Another new command here is ``.modify''. In this example, we want to test
the multiplier on a few DC sweeps but want to change the value of ``V2''
between the sweeps. This allows a single batch run to test multiple
possibilities, or it can also be used interactively to trim a component
value into the value that gives the desired operating point.
>>> A Matter of Time -- AC Analysis
So far the only type of analysis that has been studied has been steady
state direct current (or DC). Although a lot can be done with this, it
doesn't give you the full picture when your circuit contains capacitors
and inductors. These are important devices because they can store energy
and because they determine what the time constants of the circuit will
be. Time constants have no meaning in steady state DC analysis but the
effect of the time constant can be seen by using AC analysis. This allows
us to study filter circuits.
This example looks at a simple passive filter that is driven by a
single voltage source and that contains resistors, capacitors and
inductors. This concept could be extended to active filters by using
the dependent sources described above or by building op-amp models
but for the sake of simplicity passive components are used here.
eg8 --
passive 2-port network, use AC sweep to generate bode plot
and explain break-points, etc. Explain log plots and why bode is
plotted on log-log paper. Explain decibel scale (briefly).
Very brief explanation of feedback stability.
eg9 --
[explain AC analysis here with some bode plots and pole-zero stuff,
can acs do root-locus?]
two examples here eg8.ckt, eg9.ckt
AC Analysis has the limitation that it is a LINEAR analysis only.
This means that the nonlinear devices (such as diodes) must be regarded
as behaving like linear devices. In order to achieve this, acs finds
the DC operating point first and then presumes that the AC signal is
some small value that will slightly perturb the DC operating point
but will not be large enough for any nonlinear effect to be visible.
Note that circuits that depend on their nonlinearity to extract some
feature from the input signal (especially circuits containing diodes)
will not behave the same under AC analysis as they might on the test bench.
>>> Using the Generator in Transient Analysis
At last, we are ready to look at some time domain analysis. Time domain
means as it happens in time and is also called ``transient analysis''.
The outputs should be the same as you would see looking into an oscilloscope
if you were testing a real circuit.
This is a simple circuit showing how to calculate a real result for a simple
real life problem. The problem is to magnetise some permanent magnets using an
electromagnetic coil. Ignoring the physical side of the setup and considering
only the electronics, we have an coil which consists of a resistor in
series with an inductor, this is being driven by a sinusoidal supply but the
supply is only switched on for half a cycle.
Here in Australia, the mains supply is 240V RMS AC at 50Hz. Thus, one half
cycle lasts for 10 miliseconds. The ``generator'' device provided by acs is
the ideal thing to create a pulse such as this.
--------------------------------------------------------------------- eg10.ckt
MAINS PULSE HITS MAGNETISING RIG
V1 1 0 generator 1
R1 0 2 850m
L1 1 2 6mH
.options vmin=-1e5 vmax=1e5
.generator freq=50 width=10m ampl=339.4
.print tran I(L1) V(1)
.op
.tran 1e-4 30e-3 >eg10.dat
.end
----------------------------------------------------------------------
This can be run in batch mode and the output will be in plottable format
in the file ``eg10.dat''. Looking at the plot, it is easy to see the peak
current of around 250 Amps (needless to say, don't try the practical experiment
at home unless you can handle such surges). Also note the shape of the current
pulse is a little bit like an exponential decay and a little bit like a sine
wave.
You might notice a number of new commands in the above example. Firstly,
the word ``generator'' appears in two places. The output end of the generator
appears in the specification of V1. When used like this, the generator function
is being invoked and the only parameter this function has is a scaling factor
(in this case 1 for simplicity). Later n the generator command is invoked on
a command line (i.e. begins with dot) and this has a bunch of parameters
(three of which are used in this example). It is important not to get confused
between the generator function and the generator command, the name is the same
but the syntax is different and they are used in different places.
As well as the generator, some options are being changed. These options are the
maximum and minimum voltages that act as limits for convergence purposes. The
default values are suitable for typical amplifier circuits but if you want to
work with higher voltages (such as power circuits) then you must explicitly
tell the simulator by adjusting these options. You can try the above circuit
with lower values for these or with the default values and see that it does
alter the output calculation. Currently, there is no warning system to tell
you something is wrong so make sure you set them comfortably higher than any
voltage you expect to encounter in the circuit.
Now there is the transient analysis itself. This analysis works by taking time
steps and you must specify how small you want these steps to be and how long
the analysis should run for. The output redirection option is the same as
for other analyses. One special point about the transient analysis is that you
must run an ``op'' analysis first in order to establish the initial conditions.
In the example it really is not very important but in other cases it can make
a significant difference to transient behaviour.
--------------------------------------------------------------------- eg11.ckt
CAPACITOR PULSE FOR MAGNETISING RIG
.model switch SW VT=150 VH=150 RON=0.1 ROFF=1Meg
.model diode D
V1 1 0 340
R1 1 2 500
C1 2 0 2000u IC=299.8
S1 2 3 2 0 switch OFF
R2 3 4 850m
L1 4 0 6mH IC=0
D1 5 3 diode
R3 5 0 5
C2 5 0 200u
.options vmin=-1e5 vmax=1e5
.print tran I(L1) V(2) V(3) V(5)
.tran 0 20e-3 1e-6 >eg11.dat UIC QUIET
.end
----------------------------------------------------------------------
This example shows another approach to generating a magnetising pulse --
discharge a capacitor into the coil, depending on the capacitor as a high
current source. This also uses some new components and different techniques.
Firstly, the coil is still modeled using an inductor in series with a
resistor (in this case L1 and R2). The main energy storage capacitor (C1) is
fed from a 340V DC source through resistor R1, the value of R1 is such that
C1 slowly charges. Since the full charge cycle of C1 is boring, we just tell
the simulator that C1 is almost fully charged.
To achieve this the option, ``IC=299.8'' is used which implies that the initial
condition of C1 is to be charged up to 299.8 volts. Similarly, L1 is also given
an initial contition, ``IC=0'', which is to say that at time 0 there is no
current flowing in the inductor. Thanks to these initial condition
specifications, we don't need to run an ``.op'' operating point analysis
prior to the transient analysis. We do, however, need to specify ``UIC''
on the transient analysis command where UIC means ``Use Initial Conditions''.
The result is that the simulation shows only the last bit of the slow charge
through R1 until the capacitor reaches 300 volts and the switch activates.
There are a few more special things about this circuit. Consider the component
S1 that connects the capacitor to the coil. This component is a voltage
controlled switch. The parameters for the switch are given in the .model
command, defining a model called (rather unimaginatively) ``switch''. This
defines what the ``ON'' resistance of the switch is and what the ``OFF''
resistance is as well as the thresholds for changing state ON to OFF and
OFF to ON. Many devices such as MOSFETs, relays and optocouplers can
be approximated by a switch -- admittedly it is an idealised representation,
but that may be desirable in some situations and at least acceptable in others.
Note that the switch too is given an initial condition (OFF).
Run the simulation in batch mode as follows:
acs eg19.ckt
gnuplot
set data style lines
plot 'eg11.dat', 'eg11.dat' using 1:3, 'eg11.dat' using 1:4
replot 'eg11.dat' using 1:5
exit
Since this run produces rather a lot of output, the ``Quiet'' option is
added to the transient analysis in order to avoid excessive scrolling.
It should be evident that the voltage in C1 slowly charges up to 300 volts
while the switch stays open and nothing much else happens. Then the switch
shuts and the C1 voltage starts to fall while the current in L1 rises and
the energy is transfered from the capacitor to the inductor. With a resistance
of 100 miliohms in the switch and another 850 miliohms in the coil, some
of the energy is lost to heat and the inductor reaches peak current (approx
120A) before the capacitor is fully discharged -- ideally the switch could be
opened there but in this case the switch is programed to open when the
capacitor voltage reaches zero.
Finally the capacitor voltage does reach zero and the switch opens. This leaves
a noticable kink in the plot of the inductor current and it starts the
inductor energy transfering into C2 and R3 through D1. Finally all the energy
is dumped into R3 as heat. An interesting thing happens when the inductor
current reaches zero and D1 goes back into reverse bias -- the voltage at node
3 goes into a brief high frequency oscillation. Is the simulator playing up
here? What is going on?
Actually, this is correct behaviour as the last tiny burst of energy in
L1 has nowhere to go, it sets up an oscillation between the junction
capacitance in D1 and the inductance of L1. This is a property of using
diodes to switch a coil and does occur in real circuits too. The simulator
does not know the junction capacitance of D1 because it has not been specified
in the ``.model'' line (actually with no junction capacitance specified,
acs drops the capacitor out of the diode model completely) so the oscillation
flips back and forth with each time step and the magnitude of the swing
at node 3 is dependent on the size of the timestep used (try a longer timestep
and see that node 3 shows a larger voltage swing at this point).
In this case, the inductor current is the result of interest but if it
were necessary to know exactly how node 3 behaved at the end of the pulse
then more care would be required in determining the capacitance at work
around node 3 (in particular the diode and switch behaviour).
doc/gnucap-ibis.1 0000664 0000000 0000000 00000004332 11454012162 0014104 0 ustar 00root root 0000000 0000000 .\" Hey, Emacs! This is an -*- nroff -*- source file.
.TH GNUCAP-IBIS 1 "November 2001" "Debian Project" "Debian GNU"
.SH NAME
gnucap-ibis \- GNU Circuit Analysis Package IBIS translator
.SH SYNOPSIS
.B gnucap-ibis
[\fB--typ\fP] [\fB--min\fP] [\fB--max\fP] [\fB--power-on\fP] [\fB--on\fP] [\fB--off\fP] filename [\fB--dump\fP [filename]] [\fB--spice\fP [filename]]
.br
.SH DESCRIPTION
.I GNUCAP-IBIS
is a IBIS translator tool in the GNUCAP suite. It will transform IBIS models
into SPICE models for use in SPICE simulations.
.PP
The IBIS model in \fIfilename\fP is being parsed and can be translated to
whatever format is requested. By using the \fB--spice\fP option a SPICE model
can be generated. By using the \fB--dump\fP option a IBIS dump may be performed
(mainly for testing purposes). A typical usage can be
gnucap-ibis mymodel.ibis -spice
.SH OPTIONS
.TP
\fI--typ\fI
sets simulation mode to typical values (default)
.TP
\fI--min\fI
sets simulation mode to minimal values
.TP
\fI--max\fI
sets simulation mode to maximal values
.TP
\fI--power-on\fI
sets device state to power on
.TP
\fI--on\fI
sets device state to on
.TP
\fI--off\fI
sets device state to off
.TP
\fI--prefix prefix\fI
sets the prefix on generated code (default no prefix)
.TP
\fI--dump [filename]\fI
enable the dumping of the interprented IBIS file in IBIS format. Optionally an
output filename may be given (default filename is incomming filename with .dump
postfix)
.TP
\fI--spice [filename]\fI
enable the dumping of a SPICE model. Optionally an output filename may be given
(default filename is incomming filename . mode .ckt).
.SH BUGS
See
.B /usr/share/doc/gnucap/bugs
for a list of known bugs in this release.
.PP
GNUCAP is an ongoing research project. It is being released in a
preliminary phase in hopes that it will be useful and that others
will use it as a thrust or base for their research. I also hope
for some comments that may help me direct my research.
.SH AUTHOR
GNUCAP is being written by Albert Davis
.PP
This manual page was written by Magnus Danielson and
maintained by Hamish Moffatt for the Debian package of
gnucap.
For the full LaTeX documentation, please see
.B /usr/share/doc/gnucap/manual.
doc/gnucap.1 0000664 0000000 0000000 00000005707 11454012162 0013167 0 ustar 00root root 0000000 0000000 .\" Hey, Emacs! This is an -*- nroff -*- source file.
.TH GNUCAP 1 "November 2001" "Debian Project" "Debian GNU"
.SH NAME
gnucap \- GNU Circuit Analysis Package
.SH SYNOPSIS
.B gnucap
[\fB-b\fP filename] [\fB-i\fP filename]
.br
.SH DESCRIPTION
.I GNUCAP
is a general purpose circuit simulator. It performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1,2,3) and diode are included in this
release.
.PP
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design. It is also well suited to undergraduate teaching where
Spice in batch mode can be quite intimidating. This version, while
still officially in beta test, should be stable enough for basic
undergraduate teaching and courses in MOS design, but not for
bipolar design.
.PP
In batch mode it is mostly Spice compatible, so it is often possible
to use the same file for both GNUCAP and Spice.
.PP
The analog simulation is based on traditional nodal analysis with
iteration by Newton's method and LU decomposition. An event queue
and incremental matrix update speed up the solution for large
circuits (at some expense for small circuits).
.PP
It also has digital devices for mixed signal simulation. The
digital devices may be implemented as either analog subcircuits or
as true digital models. The simulator will automatically determine
which to use. Networks of digital devices are simulated as digital,
with no conversions to analog between gates. This results in
digital circuits being simulated faster than on a typical analog
simulator, even with behavioral models. The digital mode is
experimental and needs work. There will be substantial improvements
in future releases.
.SH OPTIONS
Two command-line options are available. Only one of these may be
specified. If no parameters are given, gnucap will start in interactive
mode.
.TP
\fI-b filename\fP
execute the commands in the named file then exit (batch mode)
.TP
\fI-i filename\fI
execute the commands in the named file then go into interactive mode
.SH BUGS
See
.B /usr/share/doc/gnucap/bugs
for a list of known bugs in this release.
.PP
GNUCAP is an ongoing research project. It is being released in a
preliminary phase in hopes that it will be useful and that others
will use it as a thrust or base for their research. I also hope
for some comments that may help me direct my research.
.SH AUTHOR
GNUCAP is being written by Albert Davis
.PP
This manual page was written by Jon Rabone and maintained
by Hamish Moffatt for the Debian package of gnucap.
For the full LaTeX documentation, please see
.B /usr/share/doc/gnucap/manual.
doc/history 0000664 0000000 0000000 00000112250 11454012162 0013244 0 ustar 00root root 0000000 0000000 Gnucap revision history
------------------------------------------------------------------
------------------------------------------------------------------
Gnucap 0.34 release notes (02/01/2004)
This is a bug fix and compatibility release.
1. Fix bug causing incorrect interpolation of backwards tables.
2. Fix tanh overflow bug.
3. Fix some parsing bugs.
4. Fix occasional "double load" bug.
5. Fix AC sweep with one point.
6. Transient start time really works.
7. Fix occasional assert fail after option short is changed.
8. Fix memory leak resulting from failure to delete unused common.
9. Fix a Z probe bug that sometimes gave wrong answers.
10. Fix a limiting bug that sometimes caused non-convergence.
11. Configure handles isnan.
12. Improvements to logic initialization. It is still not correct.
------------------------------------------------------------------
Gnucap 0.33 release notes (01/12/2003)
This is a bug fix and compatibility release.
0.32 was not widely distributed due to password problems and a heavy
work load, so the release notes are repeated after the current ones.
New features:
1. Add inductance probes, like capacitor.
Bug fixes:
1. Fix xprobe duplicate default arg bug - shows in g++3.2.
2. Fix bug that sometimes caused a crash when changing a model after
analysis.
3. Fix bug that caused an assert to fail (debug build) after removing
a probe from an element.
4. Fix a dumb typo hack bug ddHAS_READLINE. Now history and command
line editing really works. It was working, but somehow the hack
slipped into the release code.
------------------------------------------------------------------
Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
------------------------------------------------------------------
Gnucap 0.31 release notes (03/25/2002)
The most significant changes are the BJT model and "binning".
New features:
1. BJT model.
2. "Binning" for all MOS models.
3. Internal element: non-quasi-static poly-capacitor. (needed by BJT).
4. Enhancements to the data structures and model compiler to support
binning in general.
5. A line prefixed by "*>" is not ignored, in spite of the fact that
"*" usually begins a comment. This is a deliberate incompatibility
with Spice. If you prefix a line by "*>" it will be interpreted as a
non-comment in Gnucap, but a comment in Spice.
6. Circuit line prefixes of ">" and command prefixes of "-->" are
ignored. This is so you can copy and paste whole lines, without
having to manually remove the prompt string.
Changes that may or may not be improvements.
1. It is not the default to include stray resistance in device models.
The option "norstray" will revert to the old behavior. This is only a
change to the default value of "rstray".
Significant internal changes:
1. The internal element non-quasi-static poly-capacitor actually
works. It is used by the BJT model, and will eventually be used by
MOSFET models.
2. There are now two poly_g devices: "CPOLY_G" and "FPOLY_G". There
are interface differences that impact modeling. Previously, there was
only one, which is equivalent to the "FPOLY_G".
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
General comments:
The new BJT model seems to pass the CircuitSim90 test cases as well as
anything else, except where a missing feature prevented it from
working. A few files would not run because of named nodes. One file
(ring11) failed completely. This file also has MOSFETs, with level 2
models. The MOS level 2 model is not as robust as the BJT. I believe
the problem is due to the voltage sync bug that still impacts the MOS
model.
Most of the models have has a reasonable amount of testing in DC, but
inadequate testing in AC and transient. The BJT model has had more
testing than the others in AC and transient. All differences
(relative to other simulators) that were observed can be attributed to
differences in transient step size control or tolerance checking.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
------------------------------------------------------------------
GNUCAP 0.30 release notes (10/29/2001)
The primary effort has been to finish the model compiler, to the point
where it can handle most modeling issues. The second change is to
re-release as "gnucap", and add some configuration features to be more
consistent with other GNU software.
New features:
1. More complete model compiler.
2. "./configure" makes compiling more like other GNU software.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
3. Configure still doesn't handle everything.
4. The model compiler still requires too much raw coding.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
------------------------------------------------------------------
ACS 0.29 release notes (06/30/2001)
The primary effort has been to implement IBIS, which is still not
done. The changes here are mostly infrastructure changes needed to
support IBIS.
New features:
1. "Fit" function has choice of fit order and extrapolation. You can
have order 0, 1, 2, or 3.
2. "Posy" has even and odd options, to determine what happens in the
negative region.
3. Modelgen improvements. It now is useful for the whole device,
sometimes. It now handles probes and the device side of the model.
The diode uses it completely. There are still a few missing features
needed for the MOSFET and BJT.
4. Spice-3 compatible semiconductor resistor and capacitor.
5. "Table" model statement.
Improvements, bug fixes, etc.
1. Option "numdgt" really works.
2. Better error messages from modelgen.
3. Code changes for optimization of commons. This should reduce
memory use, sometimes, by sharing commons. Common sharing is still
not fully implemented.
4. Fix two bugs that sometimes caused problems after a "modify" or on
a "fault".
5. Better handling of "vmin" and "vmax". It should be much less
likely that limiting causes convergence to a nonsense result.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. On some systems, you will get a warning from the linker that "the
use of 'tmpnam' is dangerous". You can ignore this warning.
------------------------------------------------------------------
ACS 0.28 release notes (09/05/2000)
New features:
1. New probes: diode G, mos IBD, IBS, GBD, GBS.
2. New options: "floor" and "vfloor". (Floor was in the manual, but
not in the simulator.)
Improvements, bug fixes, etc.
1. There is a change to the way behavioral modeling conditionals are
handled. It should now be 100% compatible with SPICE, considering the
subset that duplicates SPICE. There are still significant extensions
beyond SPICE, particularly that you can have behavioral resistors,
capacitors, inductors, etc.
2. Parameter default calculations are now done in a manner consistent
with Spice 3f5. Previously, it was supposedly consistent with Spice
2g6.
3. A bug in calculation of threshold voltage of the level 6 model, for
P channel devices, has been fixed.
4. A bug in calculation of Meyer capacitances when the device is
reversed has been fixed. This bug sometimes caused a discontinuity at
vds=0.
5. I have added some smoothing to the Meyer mos capacitor models.
This improves convergence. The down side is that sometimes the
answers are different. It is probably a little better, when
considering closeness to reality, but it is still Meyer's model.
6. MOSFET parasitic diodes are now the same as those used in Spice.
7. There are subtle changes in the diode model. I think this usually
improves convergence.
8. Charge calculation in Meyer capacitors and diode capacitiors is now
supposedly Spice 3 compatible.
9. An error in BSIM3 scaling has been fixed.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. A bad setting of "vmax" and "vmin" can lead to convergence to a
nonsense result. It is not as bad now as it used to be.
------------------------------------------------------------------
ACS 0.27 release notes (06/03/2000)
New features:
1. BSIM3 model, DC.
They work for AC and transient analysis, but only the DC effects
actually work. The next release should have the charge effects. For
now, it fakes it with Meyer's model.
2. A first cut at a model compiler, to aid in development of new
models. Models are described in a ".model" file, which is processed
to automatically generate the ".h" and ".cc" files. This version
fully handles the ".model" statement part of it, but leaves the device
and common sections the old way. Eventually, the entire process will
be automated. The old way still works.
3. "Fit" behavioral modeling function, which fits a curve to a set of
data. You can specify the order of the fit, which is piecewise
polynomials. For now, the order may be 1 (linear, like PWL) or 3
(cubic splines). You may also specify the boundary consitions.
4. More probes.
Some things that are partially implemented:
1. Internal element: non-quasi-static poly-capacitor. It is needed by
the BSIM3 and EKV models. Eventually, it will be available as a
netlist item, but not yet.
Bug fixes:
1. PWL could fail if there were duplicate points at the beginning. It
still does, but gives a reasonable error message.
2. Some "dot commands" were ignored if there were spaces before the
dot. This was particularly annoying if the line was supposed to be
".end" which should make it exit. It didn't, leaving it in
interactive mode, a major annoyance in a script.
Other improvements:
1. There is a change to the way integration in capacitors is done. It
is now strictly based on charge (i = dq/dt). The old version was
based on capacitance (i = C * dv/dt) which is strictly incorrect. The
dC/dt term was missing (i = C * dv/dt + v * dC/dt). This is a
non-issue when C is constant.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. The command line is a little different. In the old version,
"acs file" would run it, and whether it exited or not depended on
whether there was an ".end" line. Now, by default, it just loads the
file in preparation for interactive use. If you want batch mode, say
"acs -b file".
2. The regression suite is included in the standard distribution.
Changes that are not really improvements:
1. Due to the model compiler, the build process is a little more
complicated. To do a complete build, you must build the model
compiler first, then the simulator. If you are not making any new
models, you can probably get away with just building the simulator.
This will change in a future release.
Bugs:
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
------------------------------------------------------------------
ACS 0.26 release notes (02/02/2000)
New features:
1. BSIM1, BSIM2 models -- DC only.
They work for AC and transient analysis, but only the
DC effects actually work. The next release should
have the charge effects.
2. New elements:
trans-capacitor
voltage controlled capacitor
voltage controlled conductance
voltage controlled resistor
This is a side effect of the BSIM work.
3. Optional new syntax, with type first so component labels can start
with any letter, and the choice of components is no longer limited by
the 26 letters. This was necessary for a clean syntax
for #2.
4. Some new parameters on existing devices, also a side
effect of the BSIM work.
5. The manual in HTML form. The manual source is still in LaTeX,
which can be used to generate HTML, PDF, Postscript, or many other
formats.
Bug fixes:
1. An error causing truncation error to be underestimated has been fixed.
Other improvements:
1. MOSFET model evaluation is a little faster, due to use of one of
the new elements to replace several old ones. I have seen 40%, but
20% is more likely. The improvement is most evident on busy circuits,
where the ACS speed enhancements based on latency exploitation
contribute more overhead than their value, that is .. the type of
circuit that has run faster in Spice than ACS.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. Truncation error based step control is disabled when Euler's method
is selected. The justification for this is that the reason for
selecting Euler's method is to avoid the artifacts of high order
methods on "stiff" poles. Without this change, a "stiff" pole would
cause an unreasonably small step size. This did not appear to be much
of a problem in the old release because the use of an incorrect
formula for estimating truncation error. A "stiff" pole is one that
has a response so fast it can be thought of as instantaneous.
2. The "help" command, with its 4 year old help file, has been
removed. The concept is really obsolete. With the HTML form of the
manual, a full online manual is a better replacement.
------------------------------------------------------------------
ACS 0.25 release notes (11/04/99)
New features:
None!
Bug fixes:
1. A name conflict that caused compile to fail with gcc 2.95 has been
fixed.
2. A problem that caused switches to lose state when a simulation is
stopped and restarted when a switch is in transition has been fixed.
3. Two unrelated problems with transmission lines have been fixed.
(Short lines and lines in subcircuits.)
Changes that may or may not be improvements:
1. Several queues have been added, to manage model evaluation
scheduling. This is part of work on multi-rate and mixed-mode
simulation, and it replaces the traditional bypass scheme. In this
release, probably the only noticeable difference will be that it runs
a little faster.
Known bugs:
1. The help file has not been updated for 4 years.
------------------------------------------------------------------
ACS 0.24 release notes (08/21/99)
New features:
1. Enhanced (now documented) behavioral modeling.
2. Transmission line in transient analysis.
3. More documentation of internals.
4. Better batch mode error handling.
Bug fixes:
1. Control-C trap works.
2. A bug that could cause a crash when a device had an improper number
of nodes has been fixed. It now issues a warning, and grounds the
unspecified nodes.
3. A bug that could cause a crash when a model or subcircuit is
deleted then accessed has been fixed.
4. A scoping bug that sometimes put subckt parts in the root circuit
has been fixed.
5. A bug in "fanout" that listed internal subckt nodes incorrectly has
been fixed.
Changes that may or may not be improvements:
1. "Make2" files for some systems have been removed. These have not
been tested in years, and ACS and the compilers have both evolved
significantly, so any portability patches that old are probably
completely wrong now.
Known bugs:
1. The help file has not been updated for 4 years.
------------------------------------------------------------------
ACS 0.23 release notes (06/15/99)
New features:
1. Level 6 mos model.
2. HSpice style PWL and POLY(1).
3. "Table" behavioral modeling function.
4. Mixed-mode digital initialization.
The bug fixes:
1. The alarm range worked backwards, now fixed.
2. Keep track of commons better.
3. Improved mixed-mode simulation. It still has not been tested as
well as I would like, but is better. Digital initialization works
now.
4. Another case of "zero time step" has been fixed. This one was
relatively benign, in that it only caused a single extra full
evaluation, with immediate recovery to a normal step size.
5. "Z" probe gave wrong results when probing a voltage source.
Other improvements: (?)
1. Some subtractions now de-noise the result, eliminating the tiny
numbers that result from subtracting two nearly equal numbers. The
threshold can be set by the option "roundofftol". It is best left set
at 1e-13. This improves speed slightly because 0 will prevent a
matrix reload, but any non-zero number will not. It improves
convergence slightly because the tiny numbers (which result from
numerical problems) tend to cause further numerical problems. These
tiny numbers are an artifact of the machine math, and vary depending
on optimization and machine implementation details.
2. MOS temperature effects are computed at run time, instead of at
load time, so you can change the temperature after loading and get
correct results.
3. The options for integration method have changed, and are more
flexible. The default is still trapezoidal, but that may change in a
future release. You can specify the mode individually for capacitors
and inductors. The information is in the data structure for all
components, but it isn't always parsed. A future release will let you
specify it by component or by model. The names are Spectre
compatible, not Spice compatible, because it is more flexible. The
Spice names are accepted, but may not act the same as they do in
Spice. Choices are: unknown, euler, euleronly, trap, traponly.
Options accepted and coerced into something else are: gear2,
gear2only, trapgear, trapeuler. In general, gear is treated as euler,
and each element will use either euler or trap. The device choice
wins over the option command choice, but "only" wins over non-only.
4. Logic device syntax is changed. There are two more nodes, so
power, ground, and enable are passed in. Power and enable are not
used (except possibly in subckt models) but are required for
consistency.
5. In many (not all) cases, arbitrary limits, due to fixed size
arrays, have been removed.
6. More rigorous testing. I actually have a regression suite now. It
is still not rigorous enough.
7. More rigorous convergence criteria. This should solve some of the
false convergence problems. ACS convergence criteria has always been
more rigorous than Spice.
The cosmetic changes:
1. Convert most containers to STL.
2. Complete migration to the "common" tree, and eliminating reference
to the old C "x" structure extensions.
3. Rearrangement of MOS model hierarchy, to make it easier to install
other models. (BSIM family is coming.)
------------------------------------------------------------------
ACS 0.22 release notes (10/16/98)
This release contains a few bug fixes, and a few cosmetic changes to the
code.
The bug fixes:
1. Fixes convergence failures in circuits with linear inductors,
linear mutual inductors, and linear current controlled sources.
2. Fixes a bypass problem, which shows as transient analysis failure
with the message "very backward time step".
3. Failed assertion on switch.
The cosmetic changes:
1. The "OMSTREAM" class, as a step in migrating the i/o to C++ style.
2. A cleaner event queue, using a generic heap class.
That's really all. I have not been actively working on ACS, mostly
due to employment at a semiconductor company in their "corporate CAD"
department. This will change soon, because my new employer (a CAD
tool vendor) says it is ok to work on ACS.
------------------------------------------------------------------
ACS 0.21 release notes (03/30/96)
There are several changes, most of which are only visible in subtle
ways from the outside.
1. The code is more conformant with the upcoming standard, particularly
in the use of complex, templates, lifetime of temporaries, and for
scope. This should fix problems compiling with g++ 2.7.
2. Element commons are freed properly.
3. The manner in which elements are loaded into the matrix is
different, and should be faster for large circuits with latency.
Model bypass is more complete, because it is no longer necessary
to do anything with a latent model. It makes little difference
for small circuits, and circuits that are mostly active. Speed
gains on small circuits are offset by #4.
4. The bypass criteria are more strict. It was possible to get
incorrect results through interaction between model evaluation
bypass and iteration damping. This release will not bypass anything
when damping is in effect. There is a slight speed penalty.
5. Logic devices work even when there is no analog model. The bug
causing a failure in this case has been fixed. The "bug" (that
could in a twisted sense be called a feature) that leads to random
mapping on start-up is still there. The logic model still needs
work.
6. The code is somewhat more object-oriented. Some classes have
been changed to be more general.
------------------------------------------------------------------
ACS 0.20 release notes (11/22/95)
This release adds the level-3 MOSFET model. It is Spice compatible.
Actually, it was there a long time ago but was removed because it
didn't work correctly. This one has been tested and seems to match
Spice results, and have convergence characteristics a little better
than Spice 2g6. Like the level 1 and 2 models, only Meyer's
capacitance model is implemented. (like Spice 3).
------------------------------------------------------------------
ACS 0.19 release notes (10/31/95)
This release offers "improved" convergence.
Several new options have been added to control iteration damping.
In some cases, the program will take a partial step in an attempt
to tame the wild fluctuations that can occur during iteration with
Newton's method. This version appears to be considerably more
robust than Spice 2g6. Several test circuits that fail to converge
on Spice do converge on ACS. The cost of this is sometimes slower
convergence. It generally takes about 2 more iterations per step
than the previous version. This can be turned off, using the
"dampstrategy" option at a slight cost in robustness. See the
manual on the options command for more information.
------------------------------------------------------------------
ACS 0.18 release notes (05/12/95)
This release offers improved memory management and exception
handling, primarily aimed at MSDOS systems.
Bug fixes:
1. For all ... Out of memory exceptions are properly trapped.
Version 0.17 would crash if it ran out of memory. Now you get a
reasonable message. It was only a real problem on MSDOS systems.
2. MSDOS floating point exceptions are trapped. In 0.17, underflow
exceptions and null floating point exceptions could sometimes cause
an abort. I don't know why, but the 80287 can generate a null
exception when apparently nothing is wrong.
3. MSDOS only: Evade underflow in exp(). A large negative argument
to exp can give bogus results. This was a known (to me) in Microsoft
C 5.1. Apparently Borland has the same behavior. It may be a
hardware problem. The fix is to not call exp with an argument
beyond -200, and return 0 instead.
4. Don't use "-fast-math" with g++. (Makefile change). It doesn't
make any difference in speed, and it sometimes causes problems,
particularly the one in #3 above.
Performance improvements:
1. Most elements no longer store values from the past. Only
inductors and capacitors do. This means that some probes are no
longer available. Some other data has been moved to improve memory
usage. This change increases the capacity of the MSDOS version by
about 10 transistors. Unix systems will swap less.
Other visible changes:
1. The method of attaching models to devices has been changed, to
improve maintainability. There are a few noticeable side effects.
a. The default models -d-, -n- are no longer available. These were
not documented.
b. Model names must now be unique. If you have a diode model named
"foo", you may not also have a mosfet model named "foo".
c. A diode can reference a mosfet model. The diode will be equivalent
to the source-bulk diode in the mosfet. This is a byproduct of
using C++ derived classes. The mosfet model is derived from the
diode model.
2. Exception handling in batch mode is different. It is still not
right.
------------------------------------------------------------------
ACS 0.17 release notes (04/21/95)
The primary difference in this release is reorganization and C++.
A side benefit is that it is slightly faster, and uses slightly
less memory. (The program is bigger, but it stores data more
efficiently, for a net improvement.) It is a transitional release,
with some of the code still in C. I hope to have a full C++ version
this summer.
Bug fixes:
1. Voltage source (vs, vcvs, ccvs) probes (current, power, etc.)
now really work.
2. Fixed bug that caused strange results with mutual inductance
after other parts of the circuit are changed.
3. Fixed memory leak in subcircuits and complex devices.
4. Fixed bug that caused a crash when probed elements were deleted.
------------------------------------------------------------------
ACS 0.16 release notes (12/10/94)
New features:
1. New components: current controlled switch, current controlled
current source, current controlled voltage source. Any simple two
terminal element (not a diode) can be used as a probe, not just
a voltage source.
2. Diode transit time parameter works.
3. Mutual inductance. The coupled coils must be linear. Only
pairs of coupled inductors are supported in this release. A future
release will probably support multiply coupled inductors.
Bug fixes:
1. Continuing a transient analysis now works as documented.
------------------------------------------------------------------
ACS 0.15 release notes (07/31/94)
Version 0.15 is supposed to be a minimal bug fix release to 0.14,
but does have one new component.
1. Some additional ports are supported, including VMS. An HP port
is supplied as a user contribution, but I have not tested it.
2. New component: voltage controlled switch. Spice-3 compatible.
3. Fixed bug that caused unpredictable behavior (usually loss of
a probe, sometimes a crash) after replacing a component.
4. Fixed bug that caused incorrect evaluation and initialization
of logic devices when there is no analog model.
5. Fixed a bug in truncation error control that sometimes caused
it to become a no-op. It still seems to usually work the same as
Spice, except that ACS will actually use at least the time steps
you ask for. Spice will pick all the steps and interpolate for
the points you ask for. This will usually cause ACS to use more
time steps than Spice, hence often slower simulations.
6. Fixed another bug in truncation error that sometimes caused a
divide by zero.
------------------------------------------------------------------
ACS 0.14 release notes (07/05/94)
Version 0.14 was supposed to be a minimal bug fix release to 0.13.
The same bugs are still there and there are a few small additions
mostly aimed at coping with convergence problems.
1. The truncation error formula was changed to use the third
derivative of charge instead of the second derivative of current.
These two numbers are theoretically equal, but in practice they
are not. The second derivative of current uses 3 terms to compute
by divided differences. The third derivative of charge uses 4
terms. Using the odd number of terms catches the error due to the
oscillatory nature of the trapezoid rule. An even number of terms
tends to lose this error. Also, using charge tends to mask it.
So, I have changed it to a less accurate, more optimistic method,
the same as Spice. It now seems to work about the same as Spice,
in the sense that it usually chooses about the same step sizes.
Strictly, the old method is "better" but it tends to run away on
stiff poles, trying for excess accuracy that doesn't matter. Your
comments on this matter are welcome. If you know of any good papers
on this, please let me know.
2. The "stiff" option has been removed from the transient command.
Instead, use the .options "trapezoid" or "gear". For now, "gear"
implies first order and is equivalent to the old "stiff". (A
cop-out.) Actually, for stiff poles you want a first order method
because the error is lower.
3. You can specify the integration method individually on any
capacitor or inductor.
4. A bug causing the MSDOS version (2 byte integers) to mess up
probes of other than nodes was fixed.
5. A bug that sometimes caused it to perpetually repeat the same
time step was fixed. (SPICE would have reported "time step too
small" and stopped.)
6. A bug that messed up step control when a dormant model wakes up
and finds out it has been sleeping too long has been fixed.
7. "Mosflags" and "diodeflags" are different and there are more of
them. There are lots of them and they may be useful in taming
convergence problems. They control the heuristics that are applied
when there appears to be a convergence problem. I have yet to find
a circuit that could not be made to converge by judicious application
of the flags and options, but any one setting is no better than
Spice, and many are worse. One combination of flags gives Spice
style limiting, which more often than not makes convergence worse.
8. "vmax" and "vmin" options as part of convergence heuristics.
The default value of "limit" now large enough to essentially remove
it. These limits sometimes help convergence, but more often hurt.
9. The "damp" option actually works.
10. The diode "off" flag works correctly.
11. There is a new command "alarm" that prints a message when a
value exceeds a range. The syntax is the same as the "plot" command.
------------------------------------------------------------------
ACS 0.13 release notes (03/11/94)
Version 0.13 adds several new features and has several bug fixes
and performance improvements.
1. Fourier analysis really works.
The "Fourier" command does a transient analysis but prints the
results in the frequency domain. It is similar to the Spice command
of the same name but not exactly the same. It is significantly
more accurate than Spice because the transient time steps are chosen
for the best match to the Fast Fourier Transform. Considerably
more flexibility is available than in Spice.
2. Transient time step control by truncation error (finally).
3. Several options have been added to display diagnostics.
4. Fixed the default value for idsat, issat, ad, and as in the
mos-diode. In 0.12, the default area was 1 square meter, which
gave mosfet capacitors in the 500 uf range. This sometimes caused
strange results.
5. Added some node probes, mostly for diagnostic use.
6. Fixed the "F" probe on linear elements. (Capacitor charge,
inductor flux, admittance current, resistor voltage) It used to
give an obviously bogus answer.
Other changes:
1. Some general changes in the interest of improving code quality
in general.
2. Function headers are in ANSI style, rather than K&R style. This
version will compile as either C or C++. Future versions will
require a C++ compiler.
------------------------------------------------------------------
ACS 0.12 release notes (10/09/93)
Version 0.12 is a maintenance release. It adds no features (except Ultrix
support) but fixes several bugs and changes some porting details. It
should be easier to port this version than previous versions.
The bug fixes are significant enough that you should upgrade to 0.12 even
if you are not having any problems.
------------------------------------------------------------------
ACS 0.11 release notes (07/26/93)
Version 0.11 fixes a few bugs in 0.10. 0.10 was supposed to be
posted on alt.sources but due to a problem with the feed it never
happened.
New features:
1. New MOSFET and diode probes. All information available from
the Spice 2 "op" analysis is now available as probes. For MOSFET
these include cbd, cbs, cgsovl, cgdovl, cgbovl, cgs, cgd, cgb,
vdsat, vth. Other (non-spice) new probes include cgst, cgdt, cgbt.
(cgst = Cgs total = cgsovl + cgs.) These were available before by
probing the value of the internal element but it was less convenient.
Now it is simple and has the same name as in Spice. These probes
are also available in transient analysis, so you can see (for
example) the dynamic variations in capacitance.
Bugs fixed:
1. Pass arguments to tr_volts and family by pointer instead of the
whole structure. This is less likely to tickle a bug in Microsoft
C. The MSDOS version of ACS 0.10 crashed frequently due to this
bug. (Strictly, this is a Microsoft-C bug, not an ACS bug but the
effect is the same.)
2. The AC "Z" probes work again. They were broken in 0.10.
3. The size of the buffer for text plots is increased allowing
support for wider screens. The old version would crash if you did
plots with outwidth set to wider than 128. The fix is to make it
bigger, with a new constant MAXWIDTH, and trap the width setting
bigger than MAXWIDTH. The current max is 256 for MSDOS and 512
for unix. The plotting code should probably be redone.
4. Width is narrower by 1 so setting width to 80 won't leave blank
lines on an 80 column screen.
5. MOSFET capacitance now matches Spice (Meyer model)
6. Level 1 model linear region gds calculation was wrong, but close
enough to often go unnoticed. It is correct and matches Spice now.
7. The value of an AC source now is compatible with Spice. That
is, plain value is the DC-tran value. In old versions of ACS a
plain value applied to all analyses including AC. You needed to
prefix the value with "DC" to make it not apply to AC. Actually,
it worked as documented. Now it works like Spice, which makes more
sense. This was a major source of strange results in AC analysis.
------------------------------------------------------------------
------------------------------------------------------------------
doc/relnotes.029 0000664 0000000 0000000 00000005126 11454012162 0013712 0 ustar 00root root 0000000 0000000 ACS 0.29 release notes (06/30/2001)
The primary effort has been to implement IBIS, which is still not
done. The changes here are mostly infrastructure changes needed to
support IBIS.
New features:
1. "Fit" function has choice of fit order and extrapolation. You can
have order 0, 1, 2, or 3.
2. "Posy" has even and odd options, to determine what happens in the
negative region.
3. Modelgen improvements. It now is useful for the whole device,
sometimes. It now handles probes and the device side of the model.
The diode uses it completely. There are still a few missing features
needed for the MOSFET and BJT.
4. Spice-3 compatible semiconductor resistor and capacitor.
5. "Table" model statement.
Improvements, bug fixes, etc.
1. Option "numdgt" really works.
2. Better error messages from modelgen.
3. Code changes for optimization of commons. This should reduce
memory use, sometimes, by sharing commons. Common sharing is still
not fully implemented.
4. Fix two bugs that sometimes caused problems after a "modify" or on
a "fault".
5. Better handling of "vmin" and "vmax". It should be much less
likely that limiting causes convergence to a nonsense result.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. On some systems, you will get a warning from the linker that "the
use of 'tmpnam' is dangerous". You can ignore this warning.
Hot items for a future release (no promises, but highly probable):
1. Charge effects and substrate current (alpha0) in BSIM models. They
are computed, but not loaded to the matrix.
2. Completion of model compiler, and its documentation.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. A "trigger" element, so time dependent values can be triggered by
the circuit, as an alternate to simple time.
8. IBIS support.
9. Spice-3 compatible "B" device.
To reach me, try this email address:
aldavis@ieee.org
ACS ftp sites:
ftp://ftp.geda.seul.org/pub/geda/dist/acs-0.29.tar.gz
http://www.geda.seul.org/dist/acs-0.29.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/acs-0.29.tar.gz
doc/relnotes.030 0000664 0000000 0000000 00000003217 11454012162 0013701 0 ustar 00root root 0000000 0000000 GNUCAP 0.30 release notes (10/29/2001)
The primary effort has been to finish the model compiler, to the point
where it can handle most modeling issues. The second change is to
re-release as "gnucap", and add some configuration features to be more
consistent with other GNU software.
New features:
1. More complete model compiler.
2. "./configure" makes compiling more like other GNU software.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
3. Configure still doesn't handle everything.
4. The model compiler still requires too much raw coding.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
Hot items for a future release (no promises, but highly probable):
1. BJT model. The model compiler is complete enough that it should be
easy now.
2. Charge effects and substrate current (alpha0) in BSIM models. They
are computed, but not loaded to the matrix.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. Spice-3 compatible "B" device.
To reach me, try this email address:
aldavis@ieee.org
ftp sites:
ftp://ftp.gnu.org/gnu/gnucap/gnucap-0.30.tar.gz
ftp://ftp.geda.seul.org/pub/geda/dist/gnucap-0.30.tar.gz
http://www.geda.seul.org/dist/gnucap-0.30.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/gnucap-0.30.tar.gz
doc/relnotes.031 0000664 0000000 0000000 00000010535 11454012162 0013703 0 ustar 00root root 0000000 0000000 Gnucap 0.31 release notes (03/25/2002)
The most significant changes are the BJT model and "binning".
New features:
1. BJT model.
2. "Binning" for all MOS models.
3. Internal element: non-quasi-static poly-capacitor. (needed by BJT).
4. Enhancements to the data structures and model compiler to support
binning in general.
5. A line prefixed by "*>" is not ignored, in spite of the fact that
"*" usually begins a comment. This is a deliberate incompatibility
with Spice. If you prefix a line by "*>" it will be interpreted as a
non-comment in Gnucap, but a comment in Spice.
6. Circuit line prefixes of ">" and command prefixes of "-->" are
ignored. This is so you can copy and paste whole lines, without
having to manually remove the prompt string.
Changes that may or may not be improvements.
1. It is not the default to include stray resistance in device models.
The option "norstray" will revert to the old behavior. This is only a
change to the default value of "rstray".
Significant internal changes:
1. The internal element non-quasi-static poly-capacitor actually
works. It is used by the BJT model, and will eventually be used by
MOSFET models.
2. There are now two poly_g devices: "CPOLY_G" and "FPOLY_G". There
are interface differences that impact modeling. Previously, there was
only one, which is equivalent to the "FPOLY_G".
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
General comments:
The new BJT model seems to pass the CircuitSim90 test cases as well as
anything else, except where a missing feature prevented it from
working. A few files would not run because of named nodes. One file
(ring11) failed completely. This file also has MOSFETs, with level 2
models. The MOS level 2 model is not as robust as the BJT. I believe
the problem is due to the voltage sync bug that still impacts the MOS
model.
Most of the models have has a reasonable amount of testing in DC, but
inadequate testing in AC and transient. The BJT model has had more
testing than the others in AC and transient. All differences
(relative to other simulators) that were observed can be attributed to
differences in transient step size control or tolerance checking.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
Bugs (newly discovered, not fixed):
1. In some cases, it is possible for the voltages at various stages of
model evaluation to get out of sync with each other. In particular,
when device limiting occurs, the conversion from FPOLY to CPOLY form
may use the unlimited voltages, resulting in an erroneous conversion.
This problem has been fixed (before release) in the DC BJT model. The
charge portion of the BJT model may still have the problem, but the
symptom rarely shows. The MOS model is known to still have the
problem. The symptom of the problem is occasional slow convergence or
non convergence. There can be a single incorrect iteration that
throws the solution far from the intended path, then it usually
recovers eventually. The fix is known, but I wanted to get the BJT
model out, so this fix will wait for the next release.
2. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
Hot items for a future release (no promises, but highly probable):
1. Charge effects and substrate current (alpha0) in BSIM models. They
are computed, but not loaded to the matrix. It was deferred waiting
for the poly-cap, but now that the poly-cap works, this missing part
of the MOS models should be working soon.
2. JFET model.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. Spice-3 compatible "B" device.
To reach me, try this email address:
aldavis@ieee.org
ftp sites:
ftp://ftp.gnu.org/gnu/gnucap/gnucap-0.31.tar.gz
ftp://ftp.geda.seul.org/pub/geda/dist/gnucap-0.31.tar.gz
http://www.geda.seul.org/dist/gnucap-0.31.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/gnucap-0.31.tar.gz
doc/relnotes.032 0000664 0000000 0000000 00000010072 11454012162 0013700 0 ustar 00root root 0000000 0000000 Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
Hot items for a future release (no promises, but highly probable):
1. Charge effects and substrate current (alpha0) in BSIM models. They
are computed, but not loaded to the matrix. It was deferred waiting
for the poly-cap, but now that the poly-cap works, this missing part
of the MOS models should be working soon.
2. JFET model.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. Spice-3 compatible "B" device.
To reach me, try this email address:
aldavis@gnu.org
ftp sites:
ftp://ftp.gnu.org/gnu/gnucap/gnucap-0.32.tar.gz
ftp://ftp.geda.seul.org/pub/geda/dist/gnucap-0.32.tar.gz
http://www.geda.seul.org/dist/gnucap-0.32.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/gnucap-0.32.tar.gz
doc/relnotes.033 0000664 0000000 0000000 00000011471 11454012162 0013705 0 ustar 00root root 0000000 0000000 Gnucap 0.33 release notes (01/12/2003)
This is a bug fix and compatibility release.
0.32 was not widely distributed due to password problems and a heavy
work load, so the release notes are repeated after the current ones.
New features:
1. Add inductance probes, like capacitor.
Bug fixes:
1. Fix xprobe duplicate default arg bug - shows in g++3.2.
2. Fix bug that sometimes caused a crash when changing a model after
analysis.
3. Fix bug that caused an assert to fail (debug build) after removing
a probe from an element.
4. Fix a dumb typo hack bug ddHAS_READLINE. Now history and command
line editing really works. It was working, but somehow the hack
slipped into the release code.
=================================================================
Gnucap 0.32 release notes (09/30/2002)
New features:
1. Series resistance in the diode. It took 5 minutes to do,
so it is embarrasing that it wasn't done before.
2. History and command line editing, using Gnu Readline. Thanks to
Simon Hoffe for sending me the patch.
3. More parameters in the BJT model. This gives it better
compatibility with commercial simulators. These parameters are beyond
Spice 3f5.
4. "M" parameter in diode, BJT and MOS devices. M is the number of
parallel devices. Some commercial simulators have this.
Changes that may or may not be improvements.
1. The definition of the transient option "UIC" has changed. It is
now Spice compatible, which means to not attempt to do any solution or
consistency check. Just apply the values, assuming anything that
isn't specified is 0. The old behavior was to attempt a solution
while holding the IC values.
Bug fixes:
1. voltage sync bug. It still doesn't fix the MOS 2 convergence
problem.
2. Fix memory leak in POLY components.
3. Fix bug in Fourier that sometimes causes overrun (crash) and time
sync errors.
4. Modelgen: fix bug in list parsing.
5. Some changes to eliminate warnings when compiling with g++ 3.1.
6. Use Euler differentiation on first step, because trap used a value
that cannot be known then. Usually, this doesn't make much
difference, but there are a few cases where the error can get
magnified and trigger trapezoidal ringing, leading to a totally bogus
result. It most cases, you could hide it with small enough steps.
These cases should work with default settings now.
7. Fix bug that sometimes caused incorrect handling of initial
conditions (UIC),
8. Fix bug that caused continuing a transient analysis to give
incorrect results.
Significant internal changes:
1. The inductor uses all of the same support functions as the
capacitor, including "integrate", which is now correctly called
"differentiate".
2. Most of the code is in place for named nodes. It mostly works and
can be turned on with the option "namednodes". It is off by default
because it is not complete. Most likely, it will be finished in the
next release.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. The "modify" command with multiple arguments seems to take only the
first one. It used to work, but is broken in this release. I am not
sure when it broke.
Hot items for a future release (no promises, but highly probable):
1. Charge effects and substrate current (alpha0) in BSIM models. They
are computed, but not loaded to the matrix. It was deferred waiting
for the poly-cap, but now that the poly-cap works, this missing part
of the MOS models should be working soon.
2. JFET model.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. Spice-3 compatible "B" device.
To reach me, try this email address:
aldavis@gnu.org
ftp sites:
ftp://ftp.gnu.org/gnu/gnucap/gnucap-0.32.tar.gz
ftp://ftp.geda.seul.org/pub/geda/dist/gnucap-0.32.tar.gz
http://www.geda.seul.org/dist/gnucap-0.32.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/gnucap-0.32.tar.gz
doc/relnotes.034 0000664 0000000 0000000 00000003510 11454012162 0013701 0 ustar 00root root 0000000 0000000 Gnucap 0.34 release notes (02/01/2004)
This is a bug fix and compatibility release.
1. Fix bug causing incorrect interpolation of backwards tables.
2. Fix tanh overflow bug.
3. Fix some parsing bugs.
4. Fix occasional "double load" bug.
5. Fix AC sweep with one point.
6. Transient start time really works.
7. Fix occasional assert fail after option short is changed.
8. Fix memory leak resulting from failure to delete unused common.
9. Fix a Z probe bug that sometimes gave wrong answers.
10. Fix a limiting bug that sometimes caused non-convergence.
11. Configure handles isnan.
12. Improvements to logic initialization. It is still not correct.
Some things that are still partially implemented:
1. BSIM models, charge effects, "alpha0" parameter. (computed then
ignored)
2. Configure still doesn't handle everything.
3. The model compiler still requires too much raw coding.
4. Named nodes. If you set the option "namednodes", it will support
named nodes, but some things don't work, so it is off by default.
5. The preliminary IBIS code is now included. For now, it is a
standalone executable, that reads an IBIS file and generates a
netlist. The netlist requires some editing to use, and is not fully
compatible anyway. It is included in hopes of recruiting help in
finishing the project.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. An occasional bogus calculation in MOSFETS occurs when a device is
reversed. This sometimes causes nonconvergence.
3. Initialization is strange when repeating an analysis without an
intermediate edit.
Hot items for a future release (no promises, but highly probable):
1. Verilog-AMS and VHDL-AMS support.
doc/whatisit 0000664 0000000 0000000 00000006436 11454012162 0013407 0 ustar 00root root 0000000 0000000 ACS is a general purpose circuit simulator. It performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1-7) and diode are included in this
release.
ACS is not based on Berkeley Spice, but some of the models have been
derived from the Berleley models.
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design. It is also well suited to undergraduate teaching where
Spice in batch mode can be quite intimidating. This version, while
still officially in beta test, should be stable enough for basic
undergraduate teaching and courses in MOS design, but not for
bipolar design.
In batch mode it is mostly Spice compatible, so it is often possible
to use the same file for both ACS and Spice.
The analog simulation is based on traditional nodal analysis with
iteration by Newton's method and LU decomposition. An event queue
and incremental matrix update speed up the solution for large
circuits (at some expense for small circuits).
It also has digital devices for mixed signal simulation. The
digital devices may be implemented as either analog subcircuits or
as true digital models. The simulator will automatically determine
which to use. Networks of digital devices are simulated as digital,
with no conversions to analog between gates. This results in
digital circuits being simulated faster than on a typical analog
simulator, even with behavioral models. The digital mode is
experimental and needs work. There will be substantial improvements
in future releases.
ACS also has a simple behavioral modeling language that allows
simple behavioral descriptions of most components including capacitors
and inductors.
ACS uses an object oriented approach to modeling. Complex models like
MOSFETS are made of simpler ones like resistors, capacitors, diodes,
and any other models that may already exist. The model designer does
not need to worry about details like convergence checking, bypass
checking, integration, or how the new device plugs into the solution
matrix because these are already taken care of by the basic models.
In addition to this, a model generator automates the most tedious and
most simulator dependent parts. This results in a dramatic improvement
in the time it takes a researcher or model designer to install a new
model, compared to Spice.
If you are tired of Spice and want a second opinion, you want to
play with the circuit and want a simulator that is interactive, or
you want to study the source code and want something easier to
follow than Spice, try ACS.
ACS is an ongoing research project. It is being released in a
preliminary phase in hopes that it will be useful and that others
will use it as a thrust or base for their research. I also hope
for some comments that may help me direct my research.
ACS ftp sites:
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/acs-0.27.tar.gz
ftp://ftp.geda.seul.org/pub/geda/dist/acs-0.27.tar.gz
http://www.geda.seul.org/dist/acs-0.27.tar.gz
Albert Davis
aldavis@ieee.org
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eq4-4609.ckt eq4-6913.ckt eq4-9217.ckt eq4-9217.tran-slow.ckt \
eq4-9217.tran.ckt eq5-.ac.ckt eq5-.tran.ckt eq5-.tran.euler.fast.ckt \
eq5-.tran.fast.ckt eq5-.tran.like-spice.ckt eq5-.tran.slow.ckt \
eq5-.tran.vfast.ckt eq5-.tran.vvfast.ckt eq5-.tran.vvvfast.ckt \
eq6-.tran.vvvfast.ckt eq7-.tran.vvvfast.ckt eqboost.ckt eqflat.ckt \
eqmodify.ckt killzap.ckt killzap.doc nmos.doc nmos100.ckt nmos15.ckt \
nmos18.ckt nmos30.ckt nmosgen.c nmp100.ckt nmpgen.c opamp-ol.ckt \
opamp-vf.ckt opamp.doc runall runall.out sc18.ckt
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examples/README 0000664 0000000 0000000 00000001256 11454012162 0013554 0 ustar 00root root 0000000 0000000 Here are some ACS example circuits. Some of these will also run on
Spice and can be used for comparison.
You can run them in batch mode by typing "acs -b name" from the shell.
You can run them interactively by starting acs then "get name". Then
play, change probes, rerun, change values, etc.
The file "runall" is a script so you can automate the testing. Read
it before using it.
"runall.out" is the result of running "runall". Ideally, you should
get identical results, but there are often small differences in the
machine math functions that will give small differences in the
results. Any numerically significant difference represents a serious
bug and should be addressed.
examples/eq.doc 0000664 0000000 0000000 00000001710 11454012162 0013763 0 ustar 00root root 0000000 0000000 There a whole bunch of "eq" circuits of various types and more
are coming.
This is a 10 band graphic equalizer that I have used as a benchmark
since my early days of working on simulation. I have it in more forms
that are not here. By using different models for op-amps, cascading
them, and other tricks I have used it to test just about everything.
This is a working product of my design that was (and may still be)
very popular among record producers in the late 70's and early 80's.
It was designed using a predecessor to ACS on a TRS-80.
eqboost.ckt the 1k band is boosted 12 db
eqflat.ckt all bands are set flat
eqmodify.ckt both. run it batch.
eq?-????.ckt A bunch of them cascaded to test the sparse matrix.
Try these on Spice if you have lots of CPU time.
ACS time growth is almost linear. Spice-2 growth is quadratic.
These probably won't work on a PC.
The biggest one has over 9000 nodes.
Don't bother with them on MSDOS. Not enough memory.
examples/eq2-145.ckt 0000664 0000000 0000000 00000004032 11454012162 0014370 0 ustar 00root root 0000000 0000000 A 145 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq4
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq2-289.ckt 0000664 0000000 0000000 00000004052 11454012162 0014403 0 ustar 00root root 0000000 0000000 A 289 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq4
x2 2 3 eq4
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2) v(3)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq2-577.ckt 0000664 0000000 0000000 00000004112 11454012162 0014400 0 ustar 00root root 0000000 0000000 A 577 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2) v(3) v(4) v(5)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq3-1153.ckt 0000664 0000000 0000000 00000004230 11454012162 0014451 0 ustar 00root root 0000000 0000000 A 1153 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq32
.subckt eq32 1 3
x1 1 2 eq16
x2 2 3 eq16
.ends eq32
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq4-2305.ckt 0000664 0000000 0000000 00000004260 11454012162 0014455 0 ustar 00root root 0000000 0000000 A 2305 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq64
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq4-4609.ckt 0000664 0000000 0000000 00000004301 11454012162 0014462 0 ustar 00root root 0000000 0000000 A 4609 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq64
x2 2 3 eq64
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2) v(3)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq4-6913.ckt 0000664 0000000 0000000 00000004322 11454012162 0014465 0 ustar 00root root 0000000 0000000 A 6913 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2) v(3) v(4)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq4-9217.ckt 0000664 0000000 0000000 00000004343 11454012162 0014470 0 ustar 00root root 0000000 0000000 A 9217 node circuit
Vin 1 0 dc 1 ac 1
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
.print op iter(0) v(1) v(2) v(3) v(4) v(5)
.print dc v(2)
.print ac vm(2) vdb(2) vp(2)
.dc Vin 1 10 1
.ac oct 1 31.25 16000
.end
examples/eq4-9217.tran-slow.ckt 0000664 0000000 0000000 00000004276 11454012162 0016422 0 ustar 00root root 0000000 0000000 A 9217 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall noincmode nobypass
.print tran v(5)
.tran .00001 .001 0
.end
examples/eq4-9217.tran.ckt 0000664 0000000 0000000 00000004253 11454012162 0015433 0 ustar 00root root 0000000 0000000 A 9217 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall
.print tran v(5)
.tran .00001 .001 0
.end
examples/eq5-.ac.ckt 0000664 0000000 0000000 00000004432 11454012162 0014527 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0 ac 1
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall
*>.print op v(nodes)
.op
.print ac v(5)
.ac oct 2 31.25 16k
.end
examples/eq5-.tran.ckt 0000664 0000000 0000000 00000004376 11454012162 0015117 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall
.print tran v(5)
.tran .00001 .001 0
.end
examples/eq5-.tran.euler.fast.ckt 0000664 0000000 0000000 00000004425 11454012162 0017161 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0 method=euler
.print tran v(5)
.tran .00001 .001 0
.end
examples/eq5-.tran.fast.ckt 0000664 0000000 0000000 00000004410 11454012162 0016040 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0
.print tran v(5)
.tran .00001 .001 0
.end
examples/eq5-.tran.like-spice.ckt 0000664 0000000 0000000 00000004507 11454012162 0017137 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall noincmode nobypass notraceload nolubypass nofbbypass
*>.option itermin=0
.print tran v(5)
.tran .00002 .001 0
.end
examples/eq5-.tran.slow.ckt 0000664 0000000 0000000 00000004463 11454012162 0016077 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall noincmode nobypass notraceload nolubypass nofbbypass
.print tran v(5)
.tran .00001 .001 0
.end
examples/eq5-.tran.vfast.ckt 0000664 0000000 0000000 00000004410 11454012162 0016226 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0
.print tran v(5)
.tran .00002 .001 0
.end
examples/eq5-.tran.vvfast.ckt 0000664 0000000 0000000 00000004410 11454012162 0016414 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq5-.tran.vvvfast.ckt 0000664 0000000 0000000 00000004425 11454012162 0016610 0 ustar 00root root 0000000 0000000 A 36865 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0 method=euler
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq6-.tran.vvvfast.ckt 0000664 0000000 0000000 00000004556 11454012162 0016616 0 ustar 00root root 0000000 0000000 A 147457 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0 method=euler
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.default.ckt 0000664 0000000 0000000 00000004657 11454012162 0016546 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.nobypass.ckt 0000664 0000000 0000000 00000004670 11454012162 0016753 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall nobypass
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.nofbbypass.ckt 0000664 0000000 0000000 00000004672 11454012162 0017265 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall nofbbypass
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.noincmode.ckt 0000664 0000000 0000000 00000004671 11454012162 0017071 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall noincmode
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.nolcbypass.ckt 0000664 0000000 0000000 00000004672 11454012162 0017274 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall nolcbypass
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.nolubypass.ckt 0000664 0000000 0000000 00000004672 11454012162 0017316 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall nolubypass
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.notraceload.ckt 0000664 0000000 0000000 00000004673 11454012162 0017413 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall notraceload
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.slow.ckt 0000664 0000000 0000000 00000004757 11454012162 0016107 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall nobypass noincmode nolcbypass nolubypass nofbbypass notraceload
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.spice-accurate.ckt 0000664 0000000 0000000 00000004671 11454012162 0020006 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0
.print tran v(5)
.tran .00005 .001 0
.end
examples/eq7-.tran.vvvfast.ckt 0000664 0000000 0000000 00000004706 11454012162 0016614 0 ustar 00root root 0000000 0000000 A 589825 node circuit
Vin 1 0 dc sin 0 1 1k 0 0
x1 1 2 eq4096
x2 2 3 eq4096
x3 3 4 eq4096
x4 4 5 eq4096
.subckt eq4096 1 5
x1 1 2 eq1024
x2 2 3 eq1024
x3 3 4 eq1024
x4 4 5 eq1024
.ends eq4096
.subckt eq1024 1 5
x1 1 2 eq256
x2 2 3 eq256
x3 3 4 eq256
x4 4 5 eq256
.ends eq1024
.subckt eq256 1 5
x1 1 2 eq64
x2 2 3 eq64
x3 3 4 eq64
x4 4 5 eq64
.ends eq256
.subckt eq64 1 5
x1 1 2 eq16
x2 2 3 eq16
x3 3 4 eq16
x4 4 5 eq16
.ends eq64
.subckt eq16 1 5
x1 1 2 eq4
x2 2 3 eq4
x3 3 4 eq4
x4 4 5 eq4
.ends eq16
.subckt eq4 1 5
x1 1 2 eq
x2 2 3 eq
x3 3 4 eq
x4 4 5 eq
.ends eq4
.subckt eq 31 37
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.ends eq
*>.option acct showall itermin=0 method=euler
.print tran v(5)
.tran .00005 .001 0
.end
examples/eqboost.ckt 0000664 0000000 0000000 00000003614 11454012162 0015053 0 ustar 00root root 0000000 0000000 Graphic equalizer -- boost 1k
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 100.K
R106b 33 16 1
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
Vin 31 0 dc 1 ac 1
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.print ac vdb(37) vdb(31) vdb(34)
.ac oct 4 31.25 32k
.end
examples/eqflat.ckt 0000664 0000000 0000000 00000003641 11454012162 0014653 0 ustar 00root root 0000000 0000000 Graphic equalizer -- all bands flat, modify test
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
Vin 31 0 dc 1 ac 1
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.print ac vdb(37) vdb(31) vdb(34)
.ac oct 4 31.25 32k
.end
examples/eqmodify.ckt 0000664 0000000 0000000 00000003710 11454012162 0015211 0 ustar 00root root 0000000 0000000 Graphic equalizer -- all bands flat, modify test
R101a 35 1 50.K
R101b 36 1 50.K
R102a 32 4 50.K
R102b 33 4 50.K
R103a 35 7 50.K
R103b 36 7 50.K
R104a 32 10 50.K
R104b 33 10 50.K
R105a 35 13 50.K
R105b 36 13 50.K
R106a 32 16 50.K
R106b 33 16 50.K
R107a 35 19 50.K
R107b 36 19 50.K
R108a 32 22 50.K
R108b 33 22 50.K
R109a 35 25 50.K
R109b 36 25 50.K
R110a 32 28 50.K
R110b 33 28 50.K
C1 1 2 1.5u
C2 4 5 748.n
C3 7 8 408.n
C4 10 11 206.n
C5 13 14 100.n
C6 16 17 50.9n
C7 19 20 25.3n
C8 22 23 12.7n
C9 25 26 5.9n
C10 28 29 2.95n
C11 2 3 15.n
C12 5 6 6.8n
C13 8 9 3.3n
C14 11 12 1.8n
C15 14 15 1.n
C16 17 18 470.p
C17 20 21 220.p
C18 23 24 120.p
C19 26 27 68.p
C20 29 30 33.p
R1 3 0 475.K
R2 6 0 536.K
R3 9 0 549.K
R4 12 0 499.K
R5 15 0 464.K
R6 18 0 475.K
R7 21 0 523.K
R8 24 0 475.K
R9 27 0 412.K
R10 30 0 422.K
G5a 2 0 3 0 -.000416666
R11 2 0 2.4K
G5b 5 0 6 0 -.000416666
R12 5 0 2.4K
G6a 8 0 9 0 -.000454545
R13 8 0 2.2K
G6b 11 0 12 0 -.000454545
R14 11 0 2.2K
G7a 14 0 15 0 -.000454545
R15 14 0 2.2K
G7b 17 0 18 0 -.000454545
R16 17 0 2.2K
G8a 20 0 21 0 -.000454545
R17 20 0 2.2K
G8b 23 0 24 0 -.000454545
R18 23 0 2.2K
G9a 26 0 27 0 -.000416666
R19 26 0 2.4K
G9b 29 0 30 0 -.000416666
R20 29 0 2.4K
R29 31 32 9.1K
R30 33 34 9.1K
R31 34 35 9.1K
R32 36 37 9.1K
C25 31 32 150.p
C26 33 34 150.p
C27 34 35 150.p
C28 36 37 150.p
Vin 31 0 dc 1 ac 1
E2 34 0 32 33 10.K
E3 37 0 35 36 10.K
.print ac vdb(37) vdb(31) vdb(34)
.ac oct 4 31.25 32k
.modify R106a=100k
.modify R106b=1
.ac
.end
examples/killzap.ckt 0000664 0000000 0000000 00000000176 11454012162 0015045 0 ustar 00root root 0000000 0000000 '
V1 1 0 ac 1.
R2 1 2 1.
C3 2 0 complex( 0. 1. )
.print ac vm(2) vdb(2) vp(2)
.ac 1p 1g dec
.ac .1 .2 .005
.end
examples/killzap.doc 0000664 0000000 0000000 00000000515 11454012162 0015026 0 ustar 00root root 0000000 0000000 This "circuit" has a transfer function of 1 / (js+1).
There is one complex pole at (-1,1).
The capacitor value is j1.
It has an interesting frequency response.
The original purpose was to trick another program "zap"
(zeros and poles) into giving bogus answers. It did!!
We all know that poles come in conjugate pairs.....
AC only!
examples/nmos.doc 0000664 0000000 0000000 00000002024 11454012162 0014331 0 ustar 00root root 0000000 0000000 Here are a few strings of NMOS inverters.
NMOS is harder to simulate than CMOS.
nmos22.ckt all one power supply
nmos30.ckt
nmos100.ckt
nmp100.ckt separate power supplies
The number is the number of gates.
Power supply coupling can hinder convergence, so the big circuits
have separate power supplies for each gate. At 1000 gates it makes
the difference between convergence and non-convergence. At 100
gates, it slows it down a bit but doesn't change the number of
iterations. The latency exploitation doesn't work as well with
common power supplies. The reason for the problem is that the
voltage source in ACS is non-ideal. A future release will have an
ideal voltage source.
Still... Spice 2g6 doesn't converge on either 100 gate circuit.
Another point is that these large circuits show why ACS doesn't
automatically print everything when you do an "op" analysis.
Everything Spice gives you is available. We just don't print it
automatically.
The two .c files nmosgen.c and nmpgen.c are what I used to generate
these circuits.
examples/nmos100.ckt 0000664 0000000 0000000 00000015605 11454012162 0014577 0 ustar 00root root 0000000 0000000 100 cascaded NMOS inverters
md1 3 2 0 0 modeld w=10u l=2u
ml1 1 1 3 0 modell w=2u l=2u
md2 4 3 0 0 modeld w=10u l=2u
ml2 1 1 4 0 modell w=2u l=2u
md3 5 4 0 0 modeld w=10u l=2u
ml3 1 1 5 0 modell w=2u l=2u
md4 6 5 0 0 modeld w=10u l=2u
ml4 1 1 6 0 modell w=2u l=2u
md5 7 6 0 0 modeld w=10u l=2u
ml5 1 1 7 0 modell w=2u l=2u
md6 8 7 0 0 modeld w=10u l=2u
ml6 1 1 8 0 modell w=2u l=2u
md7 9 8 0 0 modeld w=10u l=2u
ml7 1 1 9 0 modell w=2u l=2u
md8 10 9 0 0 modeld w=10u l=2u
ml8 1 1 10 0 modell w=2u l=2u
md9 11 10 0 0 modeld w=10u l=2u
ml9 1 1 11 0 modell w=2u l=2u
md10 12 11 0 0 modeld w=10u l=2u
ml10 1 1 12 0 modell w=2u l=2u
md11 13 12 0 0 modeld w=10u l=2u
ml11 1 1 13 0 modell w=2u l=2u
md12 14 13 0 0 modeld w=10u l=2u
ml12 1 1 14 0 modell w=2u l=2u
md13 15 14 0 0 modeld w=10u l=2u
ml13 1 1 15 0 modell w=2u l=2u
md14 16 15 0 0 modeld w=10u l=2u
ml14 1 1 16 0 modell w=2u l=2u
md15 17 16 0 0 modeld w=10u l=2u
ml15 1 1 17 0 modell w=2u l=2u
md16 18 17 0 0 modeld w=10u l=2u
ml16 1 1 18 0 modell w=2u l=2u
md17 19 18 0 0 modeld w=10u l=2u
ml17 1 1 19 0 modell w=2u l=2u
md18 20 19 0 0 modeld w=10u l=2u
ml18 1 1 20 0 modell w=2u l=2u
md19 21 20 0 0 modeld w=10u l=2u
ml19 1 1 21 0 modell w=2u l=2u
md20 22 21 0 0 modeld w=10u l=2u
ml20 1 1 22 0 modell w=2u l=2u
md21 23 22 0 0 modeld w=10u l=2u
ml21 1 1 23 0 modell w=2u l=2u
md22 24 23 0 0 modeld w=10u l=2u
ml22 1 1 24 0 modell w=2u l=2u
md23 25 24 0 0 modeld w=10u l=2u
ml23 1 1 25 0 modell w=2u l=2u
md24 26 25 0 0 modeld w=10u l=2u
ml24 1 1 26 0 modell w=2u l=2u
md25 27 26 0 0 modeld w=10u l=2u
ml25 1 1 27 0 modell w=2u l=2u
md26 28 27 0 0 modeld w=10u l=2u
ml26 1 1 28 0 modell w=2u l=2u
md27 29 28 0 0 modeld w=10u l=2u
ml27 1 1 29 0 modell w=2u l=2u
md28 30 29 0 0 modeld w=10u l=2u
ml28 1 1 30 0 modell w=2u l=2u
md29 31 30 0 0 modeld w=10u l=2u
ml29 1 1 31 0 modell w=2u l=2u
md30 32 31 0 0 modeld w=10u l=2u
ml30 1 1 32 0 modell w=2u l=2u
md31 33 32 0 0 modeld w=10u l=2u
ml31 1 1 33 0 modell w=2u l=2u
md32 34 33 0 0 modeld w=10u l=2u
ml32 1 1 34 0 modell w=2u l=2u
md33 35 34 0 0 modeld w=10u l=2u
ml33 1 1 35 0 modell w=2u l=2u
md34 36 35 0 0 modeld w=10u l=2u
ml34 1 1 36 0 modell w=2u l=2u
md35 37 36 0 0 modeld w=10u l=2u
ml35 1 1 37 0 modell w=2u l=2u
md36 38 37 0 0 modeld w=10u l=2u
ml36 1 1 38 0 modell w=2u l=2u
md37 39 38 0 0 modeld w=10u l=2u
ml37 1 1 39 0 modell w=2u l=2u
md38 40 39 0 0 modeld w=10u l=2u
ml38 1 1 40 0 modell w=2u l=2u
md39 41 40 0 0 modeld w=10u l=2u
ml39 1 1 41 0 modell w=2u l=2u
md40 42 41 0 0 modeld w=10u l=2u
ml40 1 1 42 0 modell w=2u l=2u
md41 43 42 0 0 modeld w=10u l=2u
ml41 1 1 43 0 modell w=2u l=2u
md42 44 43 0 0 modeld w=10u l=2u
ml42 1 1 44 0 modell w=2u l=2u
md43 45 44 0 0 modeld w=10u l=2u
ml43 1 1 45 0 modell w=2u l=2u
md44 46 45 0 0 modeld w=10u l=2u
ml44 1 1 46 0 modell w=2u l=2u
md45 47 46 0 0 modeld w=10u l=2u
ml45 1 1 47 0 modell w=2u l=2u
md46 48 47 0 0 modeld w=10u l=2u
ml46 1 1 48 0 modell w=2u l=2u
md47 49 48 0 0 modeld w=10u l=2u
ml47 1 1 49 0 modell w=2u l=2u
md48 50 49 0 0 modeld w=10u l=2u
ml48 1 1 50 0 modell w=2u l=2u
md49 51 50 0 0 modeld w=10u l=2u
ml49 1 1 51 0 modell w=2u l=2u
md50 52 51 0 0 modeld w=10u l=2u
ml50 1 1 52 0 modell w=2u l=2u
md51 53 52 0 0 modeld w=10u l=2u
ml51 1 1 53 0 modell w=2u l=2u
md52 54 53 0 0 modeld w=10u l=2u
ml52 1 1 54 0 modell w=2u l=2u
md53 55 54 0 0 modeld w=10u l=2u
ml53 1 1 55 0 modell w=2u l=2u
md54 56 55 0 0 modeld w=10u l=2u
ml54 1 1 56 0 modell w=2u l=2u
md55 57 56 0 0 modeld w=10u l=2u
ml55 1 1 57 0 modell w=2u l=2u
md56 58 57 0 0 modeld w=10u l=2u
ml56 1 1 58 0 modell w=2u l=2u
md57 59 58 0 0 modeld w=10u l=2u
ml57 1 1 59 0 modell w=2u l=2u
md58 60 59 0 0 modeld w=10u l=2u
ml58 1 1 60 0 modell w=2u l=2u
md59 61 60 0 0 modeld w=10u l=2u
ml59 1 1 61 0 modell w=2u l=2u
md60 62 61 0 0 modeld w=10u l=2u
ml60 1 1 62 0 modell w=2u l=2u
md61 63 62 0 0 modeld w=10u l=2u
ml61 1 1 63 0 modell w=2u l=2u
md62 64 63 0 0 modeld w=10u l=2u
ml62 1 1 64 0 modell w=2u l=2u
md63 65 64 0 0 modeld w=10u l=2u
ml63 1 1 65 0 modell w=2u l=2u
md64 66 65 0 0 modeld w=10u l=2u
ml64 1 1 66 0 modell w=2u l=2u
md65 67 66 0 0 modeld w=10u l=2u
ml65 1 1 67 0 modell w=2u l=2u
md66 68 67 0 0 modeld w=10u l=2u
ml66 1 1 68 0 modell w=2u l=2u
md67 69 68 0 0 modeld w=10u l=2u
ml67 1 1 69 0 modell w=2u l=2u
md68 70 69 0 0 modeld w=10u l=2u
ml68 1 1 70 0 modell w=2u l=2u
md69 71 70 0 0 modeld w=10u l=2u
ml69 1 1 71 0 modell w=2u l=2u
md70 72 71 0 0 modeld w=10u l=2u
ml70 1 1 72 0 modell w=2u l=2u
md71 73 72 0 0 modeld w=10u l=2u
ml71 1 1 73 0 modell w=2u l=2u
md72 74 73 0 0 modeld w=10u l=2u
ml72 1 1 74 0 modell w=2u l=2u
md73 75 74 0 0 modeld w=10u l=2u
ml73 1 1 75 0 modell w=2u l=2u
md74 76 75 0 0 modeld w=10u l=2u
ml74 1 1 76 0 modell w=2u l=2u
md75 77 76 0 0 modeld w=10u l=2u
ml75 1 1 77 0 modell w=2u l=2u
md76 78 77 0 0 modeld w=10u l=2u
ml76 1 1 78 0 modell w=2u l=2u
md77 79 78 0 0 modeld w=10u l=2u
ml77 1 1 79 0 modell w=2u l=2u
md78 80 79 0 0 modeld w=10u l=2u
ml78 1 1 80 0 modell w=2u l=2u
md79 81 80 0 0 modeld w=10u l=2u
ml79 1 1 81 0 modell w=2u l=2u
md80 82 81 0 0 modeld w=10u l=2u
ml80 1 1 82 0 modell w=2u l=2u
md81 83 82 0 0 modeld w=10u l=2u
ml81 1 1 83 0 modell w=2u l=2u
md82 84 83 0 0 modeld w=10u l=2u
ml82 1 1 84 0 modell w=2u l=2u
md83 85 84 0 0 modeld w=10u l=2u
ml83 1 1 85 0 modell w=2u l=2u
md84 86 85 0 0 modeld w=10u l=2u
ml84 1 1 86 0 modell w=2u l=2u
md85 87 86 0 0 modeld w=10u l=2u
ml85 1 1 87 0 modell w=2u l=2u
md86 88 87 0 0 modeld w=10u l=2u
ml86 1 1 88 0 modell w=2u l=2u
md87 89 88 0 0 modeld w=10u l=2u
ml87 1 1 89 0 modell w=2u l=2u
md88 90 89 0 0 modeld w=10u l=2u
ml88 1 1 90 0 modell w=2u l=2u
md89 91 90 0 0 modeld w=10u l=2u
ml89 1 1 91 0 modell w=2u l=2u
md90 92 91 0 0 modeld w=10u l=2u
ml90 1 1 92 0 modell w=2u l=2u
md91 93 92 0 0 modeld w=10u l=2u
ml91 1 1 93 0 modell w=2u l=2u
md92 94 93 0 0 modeld w=10u l=2u
ml92 1 1 94 0 modell w=2u l=2u
md93 95 94 0 0 modeld w=10u l=2u
ml93 1 1 95 0 modell w=2u l=2u
md94 96 95 0 0 modeld w=10u l=2u
ml94 1 1 96 0 modell w=2u l=2u
md95 97 96 0 0 modeld w=10u l=2u
ml95 1 1 97 0 modell w=2u l=2u
md96 98 97 0 0 modeld w=10u l=2u
ml96 1 1 98 0 modell w=2u l=2u
md97 99 98 0 0 modeld w=10u l=2u
ml97 1 1 99 0 modell w=2u l=2u
md98 100 99 0 0 modeld w=10u l=2u
ml98 1 1 100 0 modell w=2u l=2u
md99 101 100 0 0 modeld w=10u l=2u
ml99 1 1 101 0 modell w=2u l=2u
md100 102 101 0 0 modeld w=10u l=2u
ml100 1 1 102 0 modell w=2u l=2u
vdd 1 0 5
vin 2 0 .8
.MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.PRINT OP iter(0) V(nodes)
.option vmin=-.1 short=1u dampstrategy=10
.op
.end
examples/nmos15.ckt 0000664 0000000 0000000 00000002274 11454012162 0014522 0 ustar 00root root 0000000 0000000 15 cascaded NMOS inverters
md1 3 2 0 0 modeld w=10u l=2u
ml1 1 1 3 0 modell w=2u l=2u
md2 4 3 0 0 modeld w=10u l=2u
ml2 1 1 4 0 modell w=2u l=2u
md3 5 4 0 0 modeld w=10u l=2u
ml3 1 1 5 0 modell w=2u l=2u
md4 6 5 0 0 modeld w=10u l=2u
ml4 1 1 6 0 modell w=2u l=2u
md5 7 6 0 0 modeld w=10u l=2u
ml5 1 1 7 0 modell w=2u l=2u
md6 8 7 0 0 modeld w=10u l=2u
ml6 1 1 8 0 modell w=2u l=2u
md7 9 8 0 0 modeld w=10u l=2u
ml7 1 1 9 0 modell w=2u l=2u
md8 10 9 0 0 modeld w=10u l=2u
ml8 1 1 10 0 modell w=2u l=2u
md9 11 10 0 0 modeld w=10u l=2u
ml9 1 1 11 0 modell w=2u l=2u
md10 12 11 0 0 modeld w=10u l=2u
ml10 1 1 12 0 modell w=2u l=2u
md11 13 12 0 0 modeld w=10u l=2u
ml11 1 1 13 0 modell w=2u l=2u
md12 14 13 0 0 modeld w=10u l=2u
ml12 1 1 14 0 modell w=2u l=2u
md13 15 14 0 0 modeld w=10u l=2u
ml13 1 1 15 0 modell w=2u l=2u
md14 16 15 0 0 modeld w=10u l=2u
ml14 1 1 16 0 modell w=2u l=2u
md15 17 16 0 0 modeld w=10u l=2u
ml15 1 1 17 0 modell w=2u l=2u
vdd 1 0 5
vin 2 0 .8
.MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.PRINT OP iter(0) V(nodes)
.op
.end
examples/nmos18.ckt 0000664 0000000 0000000 00000002610 11454012162 0014517 0 ustar 00root root 0000000 0000000 18 cascaded NMOS inverters
md1 3 2 0 0 modeld w=10u l=2u
ml1 1 1 3 0 modell w=2u l=2u
md2 4 3 0 0 modeld w=10u l=2u
ml2 1 1 4 0 modell w=2u l=2u
md3 5 4 0 0 modeld w=10u l=2u
ml3 1 1 5 0 modell w=2u l=2u
md4 6 5 0 0 modeld w=10u l=2u
ml4 1 1 6 0 modell w=2u l=2u
md5 7 6 0 0 modeld w=10u l=2u
ml5 1 1 7 0 modell w=2u l=2u
md6 8 7 0 0 modeld w=10u l=2u
ml6 1 1 8 0 modell w=2u l=2u
md7 9 8 0 0 modeld w=10u l=2u
ml7 1 1 9 0 modell w=2u l=2u
md8 10 9 0 0 modeld w=10u l=2u
ml8 1 1 10 0 modell w=2u l=2u
md9 11 10 0 0 modeld w=10u l=2u
ml9 1 1 11 0 modell w=2u l=2u
md10 12 11 0 0 modeld w=10u l=2u
ml10 1 1 12 0 modell w=2u l=2u
md11 13 12 0 0 modeld w=10u l=2u
ml11 1 1 13 0 modell w=2u l=2u
md12 14 13 0 0 modeld w=10u l=2u
ml12 1 1 14 0 modell w=2u l=2u
md13 15 14 0 0 modeld w=10u l=2u
ml13 1 1 15 0 modell w=2u l=2u
md14 16 15 0 0 modeld w=10u l=2u
ml14 1 1 16 0 modell w=2u l=2u
md15 17 16 0 0 modeld w=10u l=2u
ml15 1 1 17 0 modell w=2u l=2u
md16 18 17 0 0 modeld w=10u l=2u
ml16 1 1 18 0 modell w=2u l=2u
md17 19 18 0 0 modeld w=10u l=2u
ml17 1 1 19 0 modell w=2u l=2u
md18 20 19 0 0 modeld w=10u l=2u
ml18 1 1 20 0 modell w=2u l=2u
vdd 1 0 5
vin 2 0 .8
.MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.PRINT OP iter(0) V(nodes)
.op
.end
examples/nmos30.ckt 0000664 0000000 0000000 00000004270 11454012162 0014515 0 ustar 00root root 0000000 0000000 30 cascaded NMOS inverters
md1 3 2 0 0 modeld w=10u l=2u
ml1 1 1 3 0 modell w=2u l=2u
md2 4 3 0 0 modeld w=10u l=2u
ml2 1 1 4 0 modell w=2u l=2u
md3 5 4 0 0 modeld w=10u l=2u
ml3 1 1 5 0 modell w=2u l=2u
md4 6 5 0 0 modeld w=10u l=2u
ml4 1 1 6 0 modell w=2u l=2u
md5 7 6 0 0 modeld w=10u l=2u
ml5 1 1 7 0 modell w=2u l=2u
md6 8 7 0 0 modeld w=10u l=2u
ml6 1 1 8 0 modell w=2u l=2u
md7 9 8 0 0 modeld w=10u l=2u
ml7 1 1 9 0 modell w=2u l=2u
md8 10 9 0 0 modeld w=10u l=2u
ml8 1 1 10 0 modell w=2u l=2u
md9 11 10 0 0 modeld w=10u l=2u
ml9 1 1 11 0 modell w=2u l=2u
md10 12 11 0 0 modeld w=10u l=2u
ml10 1 1 12 0 modell w=2u l=2u
md11 13 12 0 0 modeld w=10u l=2u
ml11 1 1 13 0 modell w=2u l=2u
md12 14 13 0 0 modeld w=10u l=2u
ml12 1 1 14 0 modell w=2u l=2u
md13 15 14 0 0 modeld w=10u l=2u
ml13 1 1 15 0 modell w=2u l=2u
md14 16 15 0 0 modeld w=10u l=2u
ml14 1 1 16 0 modell w=2u l=2u
md15 17 16 0 0 modeld w=10u l=2u
ml15 1 1 17 0 modell w=2u l=2u
md16 18 17 0 0 modeld w=10u l=2u
ml16 1 1 18 0 modell w=2u l=2u
md17 19 18 0 0 modeld w=10u l=2u
ml17 1 1 19 0 modell w=2u l=2u
md18 20 19 0 0 modeld w=10u l=2u
ml18 1 1 20 0 modell w=2u l=2u
md19 21 20 0 0 modeld w=10u l=2u
ml19 1 1 21 0 modell w=2u l=2u
md20 22 21 0 0 modeld w=10u l=2u
ml20 1 1 22 0 modell w=2u l=2u
md21 23 22 0 0 modeld w=10u l=2u
ml21 1 1 23 0 modell w=2u l=2u
md22 24 23 0 0 modeld w=10u l=2u
ml22 1 1 24 0 modell w=2u l=2u
md23 25 24 0 0 modeld w=10u l=2u
ml23 1 1 25 0 modell w=2u l=2u
md24 26 25 0 0 modeld w=10u l=2u
ml24 1 1 26 0 modell w=2u l=2u
md25 27 26 0 0 modeld w=10u l=2u
ml25 1 1 27 0 modell w=2u l=2u
md26 28 27 0 0 modeld w=10u l=2u
ml26 1 1 28 0 modell w=2u l=2u
md27 29 28 0 0 modeld w=10u l=2u
ml27 1 1 29 0 modell w=2u l=2u
md28 30 29 0 0 modeld w=10u l=2u
ml28 1 1 30 0 modell w=2u l=2u
md29 31 30 0 0 modeld w=10u l=2u
ml29 1 1 31 0 modell w=2u l=2u
md30 32 31 0 0 modeld w=10u l=2u
ml30 1 1 32 0 modell w=2u l=2u
vdd 1 0 5
vin 2 0 .8
.MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.PRINT OP iter(0) V(nodes)
.op
.end
examples/nmosgen.c 0000664 0000000 0000000 00000001451 11454012162 0014503 0 ustar 00root root 0000000 0000000 /* gen.c 03/19/93
* Generate cascased nmos inverters to test simulators
*/
#include
void main(argc,argv)
int argc;
const char *argv[];
{
unsigned count, ii;
(void)sscanf(argv[1], "%u", &count);
printf("%u cascaded NMOS inverters\n", count);
for (ii = 1; ii <= count; ii++){
int jj = ii+1;
int kk = jj+1;
printf("md%u %u %u %u %u modeld w=10u l=2u\n", ii, kk, jj, 0, 0);
printf("ml%u %u %u %u %u modell w=2u l=2u\n", ii, 1, 1, kk, 0);
}
printf("vdd 1 0 5\n");
printf("vin 2 0 .8\n");
printf(".MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)\n");
printf(".MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)\n");
printf(".PRINT OP iter(0) V(nodes)\n");
printf(".op\n");
printf(".options acct\n");
printf(".end\n");
}
examples/nmp100.ckt 0000664 0000000 0000000 00000020747 11454012162 0014420 0 ustar 00root root 0000000 0000000 100 cascaded NMOS inverters
vd1 2 0 5
md1 3 1 0 0 modeld w=10u l=2u
ml1 2 2 3 0 modell w=2u l=2u
vd2 4 0 5
md2 5 3 0 0 modeld w=10u l=2u
ml2 4 4 5 0 modell w=2u l=2u
vd3 6 0 5
md3 7 5 0 0 modeld w=10u l=2u
ml3 6 6 7 0 modell w=2u l=2u
vd4 8 0 5
md4 9 7 0 0 modeld w=10u l=2u
ml4 8 8 9 0 modell w=2u l=2u
vd5 10 0 5
md5 11 9 0 0 modeld w=10u l=2u
ml5 10 10 11 0 modell w=2u l=2u
vd6 12 0 5
md6 13 11 0 0 modeld w=10u l=2u
ml6 12 12 13 0 modell w=2u l=2u
vd7 14 0 5
md7 15 13 0 0 modeld w=10u l=2u
ml7 14 14 15 0 modell w=2u l=2u
vd8 16 0 5
md8 17 15 0 0 modeld w=10u l=2u
ml8 16 16 17 0 modell w=2u l=2u
vd9 18 0 5
md9 19 17 0 0 modeld w=10u l=2u
ml9 18 18 19 0 modell w=2u l=2u
vd10 20 0 5
md10 21 19 0 0 modeld w=10u l=2u
ml10 20 20 21 0 modell w=2u l=2u
vd11 22 0 5
md11 23 21 0 0 modeld w=10u l=2u
ml11 22 22 23 0 modell w=2u l=2u
vd12 24 0 5
md12 25 23 0 0 modeld w=10u l=2u
ml12 24 24 25 0 modell w=2u l=2u
vd13 26 0 5
md13 27 25 0 0 modeld w=10u l=2u
ml13 26 26 27 0 modell w=2u l=2u
vd14 28 0 5
md14 29 27 0 0 modeld w=10u l=2u
ml14 28 28 29 0 modell w=2u l=2u
vd15 30 0 5
md15 31 29 0 0 modeld w=10u l=2u
ml15 30 30 31 0 modell w=2u l=2u
vd16 32 0 5
md16 33 31 0 0 modeld w=10u l=2u
ml16 32 32 33 0 modell w=2u l=2u
vd17 34 0 5
md17 35 33 0 0 modeld w=10u l=2u
ml17 34 34 35 0 modell w=2u l=2u
vd18 36 0 5
md18 37 35 0 0 modeld w=10u l=2u
ml18 36 36 37 0 modell w=2u l=2u
vd19 38 0 5
md19 39 37 0 0 modeld w=10u l=2u
ml19 38 38 39 0 modell w=2u l=2u
vd20 40 0 5
md20 41 39 0 0 modeld w=10u l=2u
ml20 40 40 41 0 modell w=2u l=2u
vd21 42 0 5
md21 43 41 0 0 modeld w=10u l=2u
ml21 42 42 43 0 modell w=2u l=2u
vd22 44 0 5
md22 45 43 0 0 modeld w=10u l=2u
ml22 44 44 45 0 modell w=2u l=2u
vd23 46 0 5
md23 47 45 0 0 modeld w=10u l=2u
ml23 46 46 47 0 modell w=2u l=2u
vd24 48 0 5
md24 49 47 0 0 modeld w=10u l=2u
ml24 48 48 49 0 modell w=2u l=2u
vd25 50 0 5
md25 51 49 0 0 modeld w=10u l=2u
ml25 50 50 51 0 modell w=2u l=2u
vd26 52 0 5
md26 53 51 0 0 modeld w=10u l=2u
ml26 52 52 53 0 modell w=2u l=2u
vd27 54 0 5
md27 55 53 0 0 modeld w=10u l=2u
ml27 54 54 55 0 modell w=2u l=2u
vd28 56 0 5
md28 57 55 0 0 modeld w=10u l=2u
ml28 56 56 57 0 modell w=2u l=2u
vd29 58 0 5
md29 59 57 0 0 modeld w=10u l=2u
ml29 58 58 59 0 modell w=2u l=2u
vd30 60 0 5
md30 61 59 0 0 modeld w=10u l=2u
ml30 60 60 61 0 modell w=2u l=2u
vd31 62 0 5
md31 63 61 0 0 modeld w=10u l=2u
ml31 62 62 63 0 modell w=2u l=2u
vd32 64 0 5
md32 65 63 0 0 modeld w=10u l=2u
ml32 64 64 65 0 modell w=2u l=2u
vd33 66 0 5
md33 67 65 0 0 modeld w=10u l=2u
ml33 66 66 67 0 modell w=2u l=2u
vd34 68 0 5
md34 69 67 0 0 modeld w=10u l=2u
ml34 68 68 69 0 modell w=2u l=2u
vd35 70 0 5
md35 71 69 0 0 modeld w=10u l=2u
ml35 70 70 71 0 modell w=2u l=2u
vd36 72 0 5
md36 73 71 0 0 modeld w=10u l=2u
ml36 72 72 73 0 modell w=2u l=2u
vd37 74 0 5
md37 75 73 0 0 modeld w=10u l=2u
ml37 74 74 75 0 modell w=2u l=2u
vd38 76 0 5
md38 77 75 0 0 modeld w=10u l=2u
ml38 76 76 77 0 modell w=2u l=2u
vd39 78 0 5
md39 79 77 0 0 modeld w=10u l=2u
ml39 78 78 79 0 modell w=2u l=2u
vd40 80 0 5
md40 81 79 0 0 modeld w=10u l=2u
ml40 80 80 81 0 modell w=2u l=2u
vd41 82 0 5
md41 83 81 0 0 modeld w=10u l=2u
ml41 82 82 83 0 modell w=2u l=2u
vd42 84 0 5
md42 85 83 0 0 modeld w=10u l=2u
ml42 84 84 85 0 modell w=2u l=2u
vd43 86 0 5
md43 87 85 0 0 modeld w=10u l=2u
ml43 86 86 87 0 modell w=2u l=2u
vd44 88 0 5
md44 89 87 0 0 modeld w=10u l=2u
ml44 88 88 89 0 modell w=2u l=2u
vd45 90 0 5
md45 91 89 0 0 modeld w=10u l=2u
ml45 90 90 91 0 modell w=2u l=2u
vd46 92 0 5
md46 93 91 0 0 modeld w=10u l=2u
ml46 92 92 93 0 modell w=2u l=2u
vd47 94 0 5
md47 95 93 0 0 modeld w=10u l=2u
ml47 94 94 95 0 modell w=2u l=2u
vd48 96 0 5
md48 97 95 0 0 modeld w=10u l=2u
ml48 96 96 97 0 modell w=2u l=2u
vd49 98 0 5
md49 99 97 0 0 modeld w=10u l=2u
ml49 98 98 99 0 modell w=2u l=2u
vd50 100 0 5
md50 101 99 0 0 modeld w=10u l=2u
ml50 100 100 101 0 modell w=2u l=2u
vd51 102 0 5
md51 103 101 0 0 modeld w=10u l=2u
ml51 102 102 103 0 modell w=2u l=2u
vd52 104 0 5
md52 105 103 0 0 modeld w=10u l=2u
ml52 104 104 105 0 modell w=2u l=2u
vd53 106 0 5
md53 107 105 0 0 modeld w=10u l=2u
ml53 106 106 107 0 modell w=2u l=2u
vd54 108 0 5
md54 109 107 0 0 modeld w=10u l=2u
ml54 108 108 109 0 modell w=2u l=2u
vd55 110 0 5
md55 111 109 0 0 modeld w=10u l=2u
ml55 110 110 111 0 modell w=2u l=2u
vd56 112 0 5
md56 113 111 0 0 modeld w=10u l=2u
ml56 112 112 113 0 modell w=2u l=2u
vd57 114 0 5
md57 115 113 0 0 modeld w=10u l=2u
ml57 114 114 115 0 modell w=2u l=2u
vd58 116 0 5
md58 117 115 0 0 modeld w=10u l=2u
ml58 116 116 117 0 modell w=2u l=2u
vd59 118 0 5
md59 119 117 0 0 modeld w=10u l=2u
ml59 118 118 119 0 modell w=2u l=2u
vd60 120 0 5
md60 121 119 0 0 modeld w=10u l=2u
ml60 120 120 121 0 modell w=2u l=2u
vd61 122 0 5
md61 123 121 0 0 modeld w=10u l=2u
ml61 122 122 123 0 modell w=2u l=2u
vd62 124 0 5
md62 125 123 0 0 modeld w=10u l=2u
ml62 124 124 125 0 modell w=2u l=2u
vd63 126 0 5
md63 127 125 0 0 modeld w=10u l=2u
ml63 126 126 127 0 modell w=2u l=2u
vd64 128 0 5
md64 129 127 0 0 modeld w=10u l=2u
ml64 128 128 129 0 modell w=2u l=2u
vd65 130 0 5
md65 131 129 0 0 modeld w=10u l=2u
ml65 130 130 131 0 modell w=2u l=2u
vd66 132 0 5
md66 133 131 0 0 modeld w=10u l=2u
ml66 132 132 133 0 modell w=2u l=2u
vd67 134 0 5
md67 135 133 0 0 modeld w=10u l=2u
ml67 134 134 135 0 modell w=2u l=2u
vd68 136 0 5
md68 137 135 0 0 modeld w=10u l=2u
ml68 136 136 137 0 modell w=2u l=2u
vd69 138 0 5
md69 139 137 0 0 modeld w=10u l=2u
ml69 138 138 139 0 modell w=2u l=2u
vd70 140 0 5
md70 141 139 0 0 modeld w=10u l=2u
ml70 140 140 141 0 modell w=2u l=2u
vd71 142 0 5
md71 143 141 0 0 modeld w=10u l=2u
ml71 142 142 143 0 modell w=2u l=2u
vd72 144 0 5
md72 145 143 0 0 modeld w=10u l=2u
ml72 144 144 145 0 modell w=2u l=2u
vd73 146 0 5
md73 147 145 0 0 modeld w=10u l=2u
ml73 146 146 147 0 modell w=2u l=2u
vd74 148 0 5
md74 149 147 0 0 modeld w=10u l=2u
ml74 148 148 149 0 modell w=2u l=2u
vd75 150 0 5
md75 151 149 0 0 modeld w=10u l=2u
ml75 150 150 151 0 modell w=2u l=2u
vd76 152 0 5
md76 153 151 0 0 modeld w=10u l=2u
ml76 152 152 153 0 modell w=2u l=2u
vd77 154 0 5
md77 155 153 0 0 modeld w=10u l=2u
ml77 154 154 155 0 modell w=2u l=2u
vd78 156 0 5
md78 157 155 0 0 modeld w=10u l=2u
ml78 156 156 157 0 modell w=2u l=2u
vd79 158 0 5
md79 159 157 0 0 modeld w=10u l=2u
ml79 158 158 159 0 modell w=2u l=2u
vd80 160 0 5
md80 161 159 0 0 modeld w=10u l=2u
ml80 160 160 161 0 modell w=2u l=2u
vd81 162 0 5
md81 163 161 0 0 modeld w=10u l=2u
ml81 162 162 163 0 modell w=2u l=2u
vd82 164 0 5
md82 165 163 0 0 modeld w=10u l=2u
ml82 164 164 165 0 modell w=2u l=2u
vd83 166 0 5
md83 167 165 0 0 modeld w=10u l=2u
ml83 166 166 167 0 modell w=2u l=2u
vd84 168 0 5
md84 169 167 0 0 modeld w=10u l=2u
ml84 168 168 169 0 modell w=2u l=2u
vd85 170 0 5
md85 171 169 0 0 modeld w=10u l=2u
ml85 170 170 171 0 modell w=2u l=2u
vd86 172 0 5
md86 173 171 0 0 modeld w=10u l=2u
ml86 172 172 173 0 modell w=2u l=2u
vd87 174 0 5
md87 175 173 0 0 modeld w=10u l=2u
ml87 174 174 175 0 modell w=2u l=2u
vd88 176 0 5
md88 177 175 0 0 modeld w=10u l=2u
ml88 176 176 177 0 modell w=2u l=2u
vd89 178 0 5
md89 179 177 0 0 modeld w=10u l=2u
ml89 178 178 179 0 modell w=2u l=2u
vd90 180 0 5
md90 181 179 0 0 modeld w=10u l=2u
ml90 180 180 181 0 modell w=2u l=2u
vd91 182 0 5
md91 183 181 0 0 modeld w=10u l=2u
ml91 182 182 183 0 modell w=2u l=2u
vd92 184 0 5
md92 185 183 0 0 modeld w=10u l=2u
ml92 184 184 185 0 modell w=2u l=2u
vd93 186 0 5
md93 187 185 0 0 modeld w=10u l=2u
ml93 186 186 187 0 modell w=2u l=2u
vd94 188 0 5
md94 189 187 0 0 modeld w=10u l=2u
ml94 188 188 189 0 modell w=2u l=2u
vd95 190 0 5
md95 191 189 0 0 modeld w=10u l=2u
ml95 190 190 191 0 modell w=2u l=2u
vd96 192 0 5
md96 193 191 0 0 modeld w=10u l=2u
ml96 192 192 193 0 modell w=2u l=2u
vd97 194 0 5
md97 195 193 0 0 modeld w=10u l=2u
ml97 194 194 195 0 modell w=2u l=2u
vd98 196 0 5
md98 197 195 0 0 modeld w=10u l=2u
ml98 196 196 197 0 modell w=2u l=2u
vd99 198 0 5
md99 199 197 0 0 modeld w=10u l=2u
ml99 198 198 199 0 modell w=2u l=2u
vd100 200 0 5
md100 201 199 0 0 modeld w=10u l=2u
ml100 200 200 201 0 modell w=2u l=2u
vin 1 0 .8
.MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)
.PRINT OP iter(0) V(nodes)
.op
.end
examples/nmpgen.c 0000664 0000000 0000000 00000001527 11454012162 0014325 0 ustar 00root root 0000000 0000000 /* gen.c 03/19/93
* Generate cascased nmos inverters to test simulators
*/
#include
void main(argc,argv)
int argc;
const char *argv[];
{
unsigned count, ii;
(void)sscanf(argv[1], "%u", &count);
printf("%u cascaded NMOS inverters\n", count);
for (ii = 1; ii <= count; ii++){
int in = ii*2-1;
int out = ii*2+1;
int pwr = ii*2;
printf("vd%u %u 0 5\n", ii, pwr);
printf("md%u %u %u %u %u modeld w=10u l=2u\n", ii, out, in, 0, 0);
printf("ml%u %u %u %u %u modell w=2u l=2u\n", ii, pwr, pwr, out, 0);
}
printf("vin 1 0 .8\n");
printf(".MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)\n");
printf(".MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5)\n");
printf(".PRINT OP iter(0) V(nodes)\n");
printf(".op\n");
printf(".options acct\n");
printf(".end\n");
}
examples/opamp-ol.ckt 0000664 0000000 0000000 00000003610 11454012162 0015117 0 ustar 00root root 0000000 0000000 2 stage op-amp open loop 02/16/88
*
m1 3 2 5 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m2 4 1 5 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m3 3 3 9 9 cmosp w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m4 4 3 9 9 cmosp w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m5 5 7 8 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m6 6 4 9 9 cmosp w=9u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m7 6 7 8 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m8 7 7 8 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
cc 4 6 5.0p
ib 9 7 .36u
vdd 9 0 2.5
vss 8 0 -2.5
cl 6 0 20p
*
vin 1 0 dc=0 ac=.5
ein 0 2 1 0 1
*
.model cmosn nmos (level=2 ld=0.265073u tox=418.0e-10
+ nsub=1.53142e+16 vto=0.844345 kp=4.15964e-05 gamma=0.863074
+ phi=0.6 uo=503.521 uexp=0.163917 ucrit=161166
+ delta=1e-06 vmax=55903.5 xj=0.400000u lambda=0.01
+ nfs=3.5934e+12 neff=1.001 nss=1e+12 tpg=1.000000
+ rsh=29.3 cgdo=2.18971e-10 cgso=2.18971e-10
+ cj=0.0003844 mj=0.488400 cjsw=5.272e-10 mjsw=0.300200 pb=0.700000)
.model cmosp pmos (level=2 ld=0.299878u tox=418.0e-10
+ nsub=4.19363e+15 vto=-0.79089 kp=1.64047e-05 gamma=0.451645
+ phi=0.6 uo=198.577 uexp=0.343935 ucrit=110988
+ delta=0.956806 vmax=41456.3 xj=0.400000u lambda=0.02
+ nfs=1e+12 neff=1.001 nss=1e+12 tpg=-1.000000
+ rsh=107.6 cgdo=2.47722e-10 cgso=2.47722e-10
+ cj=0.0002281 mj=0.508000 cjsw=3.077e-10 mjsw=0.193500 pb=0.740000)
*
.print op iter(0) v(nodes)
.op
*
.plot ac vdb(6) (0,80) vp(6) (-180,180)
.ac dec 5 1 10meg
*ac steps start stop
*
.plot dc v(6) (-4,4)
.dc vin -500u 500u 20u
*dc start stop stepsize
*
* Try this in Spice. Compare to the AC analysis above. (same sweep parameters)
* It uses the last step in the DC analysis as the bias point.
.ac
*
* Try this in Spice.
.plot dc cgs(m7)(5f 7f)
.dc
*.plot dc cgs(m7)(5f 7f) cgs(m6)(15f 25f)
*.dc
*.print dc region(m*)
*.dc
*
.end
examples/opamp-vf.ckt 0000664 0000000 0000000 00000003330 11454012162 0015117 0 ustar 00root root 0000000 0000000 2 stage op-amp, conected as voltage follower 02/16/88
*
m1 3 6 5 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m2 4 1 5 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m3 3 3 9 9 cmosp w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m4 4 3 9 9 cmosp w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m5 5 7 8 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m6 6 4 9 9 cmosp w=9u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m7 6 7 8 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
m8 7 7 8 8 cmosn w=5u l=5u ad=45p as=45p pd=28u ps=28u nrd=1.8 nrs=1.8
cc 4 6 5.0p
ib 9 7 .36u
vdd 9 0 2.5
vss 8 0 -2.5
cl 6 0 20p
*
vin 1 0 dc pulse(-1.0 1.0 200u 1u 1u 300u 600u) ac=1
*
.model cmosn nmos (level=2 ld=0.265073u tox=418.0e-10
+ nsub=1.53142e+16 vto=0.844345 kp=4.15964e-05 gamma=0.863074
+ phi=0.6 uo=503.521 uexp=0.163917 ucrit=161166
+ delta=1e-06 vmax=55903.5 xj=0.400000u lambda=0.01
+ nfs=3.5934e+12 neff=1.001 nss=1e+12 tpg=1.000000
+ rsh=29.3 cgdo=2.18971e-10 cgso=2.18971e-10
+ cj=0.0003844 mj=0.488400 cjsw=5.272e-10 mjsw=0.300200 pb=0.700000)
.model cmosp pmos (level=2 ld=0.299878u tox=418.0e-10
+ nsub=4.19363e+15 vto=-0.79089 kp=1.64047e-05 gamma=0.451645
+ phi=0.6 uo=198.577 uexp=0.343935 ucrit=110988
+ delta=0.956806 vmax=41456.3 xj=0.400000u lambda=0.02
+ nfs=1e+12 neff=1.001 nss=1e+12 tpg=-1.000000
+ rsh=107.6 cgdo=2.47722e-10 cgso=2.47722e-10
+ cj=0.0002281 mj=0.508000 cjsw=3.077e-10 mjsw=0.193500 pb=0.740000)
*
.print op iter(0) v(nodes)
.op
*
.plot ac vdb(6) (-90,30) vp(6) (-180,180)
.ac dec 5 1 10meg
*ac steps start stop
*
.plot dc v(6) (-4,4)
.dc vin -5 5 .2
*dc start stop stepsize
*
.plot tran v(6) (-4,4)
.tran 10u 1000u 0
*tran step stop start
.end
examples/opamp.doc 0000664 0000000 0000000 00000001342 11454012162 0014473 0 ustar 00root root 0000000 0000000 Here are two variations on a CMOS op-amp, similar to the sample 2
stage one in Allen & Holberg's "CMOS Analog Circuit Design" text.
It is not an optimal design, just one to play with. The results
are the same as Spice, as expected.
The files:
opamp-ol.ckt open loop: op, ac, dc
opamp-vf.ckt voltage follower: op, ac, dc, tran
We do a few extras, like a plot of Cgs(M7) vs. input voltage. Try
that in Spice.
Then, there's another one. An ac analysis at saturation. Try that
in Spice.
Spice shows you everything, whether you like it or not, on an "op"
analysis. You can't see them at all in any other. But those values
are not constant. They vary with the signals. ACS will show you
(if you want) how they vary with the signal.
examples/runall 0000775 0000000 0000000 00000000425 11454012162 0014114 0 ustar 00root root 0000000 0000000 #
$1 -b eq2-145.ckt
$1 -b eq2-289.ckt
$1 -b eq2-577.ckt
$1 -b eq3-1153.ckt
$1 -b eq4-2305.ckt
$1 -b eqboost.ckt
$1 -b eqflat.ckt
$1 -b eqmodify.ckt
$1 -b killzap.ckt
$1 -b nmos100.ckt
$1 -b nmos18.ckt
$1 -b nmos30.ckt
$1 -b nmp100.ckt
$1 -b opamp-ol.ckt
$1 -b opamp-vf.ckt
examples/runall.out 0000664 0000000 0000000 00000161235 11454012162 0014726 0 ustar 00root root 0000000 0000000 ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
A 145 node circuit
# v(2)
1. 0.99847
2. 1.9969
3. 2.9954
4. 3.9939
5. 4.9924
6. 5.9908
7. 6.9893
8. 7.9878
9. 8.9863
10. 9.9847
#Freq vm(2) vdb(2) vp(2)
31.25 0.99847 -0.013271 11.171u
62.5 0.99847 -0.013271 22.349u
125. 0.99847 -0.013271 44.705u
250. 0.99847 -0.013271 89.415u
500. 0.99847 -0.013271 178.83u
1.K 0.99847 -0.01327 357.64u
2.K 0.99847 -0.013269 715.13u
4.K 0.99847 -0.013263 0.001429
8.K 0.99848 -0.013241 0.002848
16.K 0.99849 -0.013154 0.005617
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
A 289 node circuit
# v(2)
1. 0.99847
2. 1.9969
3. 2.9954
4. 3.9939
5. 4.9924
6. 5.9908
7. 6.9893
8. 7.9878
9. 8.9863
10. 9.9847
#Freq vm(2) vdb(2) vp(2)
31.25 0.99847 -0.013271 11.171u
62.5 0.99847 -0.013271 22.349u
125. 0.99847 -0.013271 44.705u
250. 0.99847 -0.013271 89.415u
500. 0.99847 -0.013271 178.83u
1.K 0.99847 -0.01327 357.64u
2.K 0.99847 -0.013269 715.13u
4.K 0.99847 -0.013263 0.001429
8.K 0.99848 -0.013241 0.002848
16.K 0.99849 -0.013154 0.005617
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
A 577 node circuit
# v(2)
1. 0.99847
2. 1.9969
3. 2.9954
4. 3.9939
5. 4.9924
6. 5.9908
7. 6.9893
8. 7.9878
9. 8.9863
10. 9.9847
#Freq vm(2) vdb(2) vp(2)
31.25 0.99847 -0.013271 11.171u
62.5 0.99847 -0.013271 22.349u
125. 0.99847 -0.013271 44.705u
250. 0.99847 -0.013271 89.415u
500. 0.99847 -0.013271 178.83u
1.K 0.99847 -0.01327 357.64u
2.K 0.99847 -0.013269 715.13u
4.K 0.99847 -0.013263 0.001429
8.K 0.99848 -0.013241 0.002848
16.K 0.99849 -0.013154 0.005617
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
A 1153 node circuit
# v(2)
1. 0.98785
2. 1.9757
3. 2.9636
4. 3.9514
5. 4.9393
6. 5.9271
7. 6.915
8. 7.9028
9. 8.8907
10. 9.8785
#Freq vm(2) vdb(2) vp(2)
31.25 0.98785 -0.10617 89.411u
62.5 0.98785 -0.10617 178.83u
125. 0.98785 -0.10617 357.67u
250. 0.98785 -0.10617 715.34u
500. 0.98785 -0.10617 0.0014307
1.K 0.98785 -0.10616 0.0028612
2.K 0.98785 -0.10615 0.0057211
4.K 0.98786 -0.10611 0.011432
8.K 0.98788 -0.10593 0.022784
16.K 0.98796 -0.10523 0.044936
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
A 2305 node circuit
# v(2)
1. 0.97585
2. 1.9517
3. 2.9276
4. 3.9034
5. 4.8793
6. 5.8551
7. 6.831
8. 7.8068
9. 8.7827
10. 9.7585
#Freq vm(2) vdb(2) vp(2)
31.25 0.97585 -0.21233 178.83u
62.5 0.97585 -0.21233 357.67u
125. 0.97585 -0.21233 715.34u
250. 0.97585 -0.21233 0.0014307
500. 0.97585 -0.21233 0.0028613
1.K 0.97585 -0.21232 0.0057223
2.K 0.97585 -0.2123 0.011442
4.K 0.97586 -0.21221 0.022864
8.K 0.9759 -0.21186 0.045567
16.K 0.97606 -0.21046 0.089872
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
Graphic equalizer -- boost 1k
#Freq vdb(37) vdb(31) vdb(34)
31.25 0.095167 -2.0118n 0.096826
37.163 0.11409 -2.1032n 0.11575
44.194 0.13781 -2.1809n 0.13947
52.556 0.16848 -2.2446n 0.17014
62.5 0.20922 -2.2952n 0.21088
74.325 0.26444 -2.3344n 0.2661
88.388 0.34021 -2.3642n 0.34187
105.11 0.44477 -2.3866n 0.44643
125. 0.58911 -2.4035n 0.59077
148.65 0.78769 -2.4165n 0.78934
176.78 1.059 -2.4266n 1.0607
210.22 1.4262 -2.4349n 1.4279
250. 1.9169 -2.4421n 1.9186
297.3 2.5634 -2.4488n 2.565
353.55 3.4014 -2.4552n 3.403
420.45 4.4697 -2.4615n 4.4714
500. 5.8076 -2.4678n 5.8093
594.6 7.4426 -2.4741n 7.4443
707.11 9.3356 -2.4804n 9.3373
840.9 11.183 -2.4867n 11.184
1.K 12.091 -2.4928n 12.092
1.1892K 11.281 -2.4985n 11.283
1.4142K 9.4491 -2.5039n 9.4508
1.6818K 7.5303 -2.5088n 7.532
2.K 5.8651 -2.5129n 5.8667
2.3784K 4.5032 -2.5158n 4.5049
2.8284K 3.4187 -2.5174n 3.4204
3.3636K 2.5711 -2.5176n 2.5728
4.K 1.9198 -2.5164n 1.9214
4.7568K 1.427 -2.5136n 1.4286
5.6569K 1.0593 -2.5093n 1.061
6.7272K 0.78815 -2.5028n 0.78981
8.K 0.58993 -2.4938n 0.59159
9.5137K 0.44583 -2.4813n 0.44748
11.314K 0.34124 -2.4642n 0.34289
13.454K 0.26508 -2.4413n 0.26673
16.K 0.20907 -2.4112n 0.21072
19.027K 0.16712 -2.3724n 0.16876
22.627K 0.13481 -2.3241n 0.13644
26.909K 0.10904 -2.2657n 0.11066
32.K 0.087701 -2.1976n 0.089304
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
Graphic equalizer -- all bands flat, modify test
#Freq vdb(37) vdb(31) vdb(34)
31.25 -0.0033177 -2.1364n -0.0016588
37.163 -0.0033177 -2.2546n -0.0016588
44.194 -0.0033177 -2.3648n -0.0016588
52.556 -0.0033177 -2.4681n -0.0016588
62.5 -0.0033177 -2.5656n -0.0016588
74.325 -0.0033177 -2.6589n -0.0016588
88.388 -0.0033177 -2.7484n -0.0016588
105.11 -0.0033177 -2.8333n -0.0016588
125. -0.0033177 -2.9121n -0.0016588
148.65 -0.0033177 -2.9828n -0.0016588
176.78 -0.0033177 -3.044n -0.0016588
210.22 -0.0033177 -3.0952n -0.0016588
250. -0.0033177 -3.1368n -0.0016588
297.3 -0.0033177 -3.17n -0.0016588
353.55 -0.0033177 -3.1961n -0.0016588
420.45 -0.0033177 -3.2165n -0.0016588
500. -0.0033177 -3.2324n -0.0016588
594.6 -0.0033177 -3.2448n -0.0016588
707.11 -0.0033176 -3.2544n -0.0016588
840.9 -0.0033176 -3.2618n -0.0016588
1.K -0.0033176 -3.2673n -0.0016588
1.1892K -0.0033175 -3.2709n -0.0016588
1.4142K -0.0033175 -3.2725n -0.0016587
1.6818K -0.0033174 -3.2716n -0.0016587
2.K -0.0033172 -3.2674n -0.0016586
2.3784K -0.003317 -3.2592n -0.0016585
2.8284K -0.0033168 -3.2458n -0.0016584
3.3636K -0.0033164 -3.2263n -0.0016582
4.K -0.0033158 -3.1994n -0.0016579
4.7568K -0.0033151 -3.1644n -0.0016575
5.6569K -0.003314 -3.1205n -0.001657
6.7272K -0.0033125 -3.0678n -0.0016562
8.K -0.0033103 -3.0072n -0.0016551
9.5137K -0.0033072 -2.9404n -0.0016536
11.314K -0.003303 -2.8693n -0.0016515
13.454K -0.0032969 -2.7957n -0.0016485
16.K -0.0032885 -2.7202n -0.0016442
19.027K -0.0032767 -2.6425n -0.0016384
22.627K -0.0032603 -2.5619n -0.0016302
26.909K -0.0032378 -2.4772n -0.0016189
32.K -0.003207 -2.388n -0.0016035
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
Graphic equalizer -- all bands flat, modify test
#Freq vdb(37) vdb(31) vdb(34)
31.25 -0.0033177 -2.1364n -0.0016588
37.163 -0.0033177 -2.2546n -0.0016588
44.194 -0.0033177 -2.3648n -0.0016588
52.556 -0.0033177 -2.4681n -0.0016588
62.5 -0.0033177 -2.5656n -0.0016588
74.325 -0.0033177 -2.6589n -0.0016588
88.388 -0.0033177 -2.7484n -0.0016588
105.11 -0.0033177 -2.8333n -0.0016588
125. -0.0033177 -2.9121n -0.0016588
148.65 -0.0033177 -2.9828n -0.0016588
176.78 -0.0033177 -3.044n -0.0016588
210.22 -0.0033177 -3.0952n -0.0016588
250. -0.0033177 -3.1368n -0.0016588
297.3 -0.0033177 -3.17n -0.0016588
353.55 -0.0033177 -3.1961n -0.0016588
420.45 -0.0033177 -3.2165n -0.0016588
500. -0.0033177 -3.2324n -0.0016588
594.6 -0.0033177 -3.2448n -0.0016588
707.11 -0.0033176 -3.2544n -0.0016588
840.9 -0.0033176 -3.2618n -0.0016588
1.K -0.0033176 -3.2673n -0.0016588
1.1892K -0.0033175 -3.2709n -0.0016588
1.4142K -0.0033175 -3.2725n -0.0016587
1.6818K -0.0033174 -3.2716n -0.0016587
2.K -0.0033172 -3.2674n -0.0016586
2.3784K -0.003317 -3.2592n -0.0016585
2.8284K -0.0033168 -3.2458n -0.0016584
3.3636K -0.0033164 -3.2263n -0.0016582
4.K -0.0033158 -3.1994n -0.0016579
4.7568K -0.0033151 -3.1644n -0.0016575
5.6569K -0.003314 -3.1205n -0.001657
6.7272K -0.0033125 -3.0678n -0.0016562
8.K -0.0033103 -3.0072n -0.0016551
9.5137K -0.0033072 -2.9404n -0.0016536
11.314K -0.003303 -2.8693n -0.0016515
13.454K -0.0032969 -2.7957n -0.0016485
16.K -0.0032885 -2.7202n -0.0016442
19.027K -0.0032767 -2.6425n -0.0016384
22.627K -0.0032603 -2.5619n -0.0016302
26.909K -0.0032378 -2.4772n -0.0016189
32.K -0.003207 -2.388n -0.0016035
#Freq vdb(37) vdb(31) vdb(34)
31.25 0.095167 -2.0118n 0.096826
37.163 0.11409 -2.1032n 0.11575
44.194 0.13781 -2.1809n 0.13947
52.556 0.16848 -2.2446n 0.17014
62.5 0.20922 -2.2952n 0.21088
74.325 0.26444 -2.3344n 0.2661
88.388 0.34021 -2.3642n 0.34187
105.11 0.44477 -2.3866n 0.44643
125. 0.58911 -2.4035n 0.59077
148.65 0.78769 -2.4165n 0.78934
176.78 1.059 -2.4266n 1.0607
210.22 1.4262 -2.4349n 1.4279
250. 1.9169 -2.4421n 1.9186
297.3 2.5634 -2.4488n 2.565
353.55 3.4014 -2.4552n 3.403
420.45 4.4697 -2.4615n 4.4714
500. 5.8076 -2.4678n 5.8093
594.6 7.4426 -2.4741n 7.4443
707.11 9.3356 -2.4804n 9.3373
840.9 11.183 -2.4867n 11.184
1.K 12.091 -2.4928n 12.092
1.1892K 11.281 -2.4985n 11.283
1.4142K 9.4491 -2.5039n 9.4508
1.6818K 7.5303 -2.5088n 7.532
2.K 5.8651 -2.5129n 5.8667
2.3784K 4.5032 -2.5158n 4.5049
2.8284K 3.4187 -2.5174n 3.4204
3.3636K 2.5711 -2.5176n 2.5728
4.K 1.9198 -2.5164n 1.9214
4.7568K 1.427 -2.5136n 1.4286
5.6569K 1.0593 -2.5093n 1.061
6.7272K 0.78815 -2.5028n 0.78981
8.K 0.58993 -2.4938n 0.59159
9.5137K 0.44583 -2.4813n 0.44748
11.314K 0.34124 -2.4642n 0.34289
13.454K 0.26508 -2.4413n 0.26673
16.K 0.20907 -2.4112n 0.21072
19.027K 0.16712 -2.3724n 0.16876
22.627K 0.13481 -2.3241n 0.13644
26.909K 0.10904 -2.2657n 0.11066
32.K 0.087701 -2.1976n 0.089304
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
'
#Freq vm(2) vdb(2) vp(2)
1.p 1. 54.575p 0.
10.p 1. 545.76p 0.
100.p 1. 5.4576n 0.
1.n 1. 54.576n 0.
10.n 1. 545.76n 0.
100.n 1. 5.4576u 0.
1.u 1. 54.576u 0.
10.u 1.0001 545.77u 0.
100.u 1.0006 0.0054593 0.
0.001 1.0063 0.054748 0.
0.01 1.067 0.56366 0.
0.1 2.6905 8.5967 0.
1. 0.18928 -14.458 -180.
10. 0.016173 -35.824 -180.
100. 0.0015941 -55.95 -180.
1.K 159.18u -75.962 -180.
10.K 15.916u -95.964 -180.
100.K 1.5915u -115.96 -180.
1.Meg 159.15n -135.96 -180.
10.Meg 15.915n -155.96 -180.
100.Meg 1.5915n -175.96 -180.
1.G 159.15p -195.96 -180.
#Freq vm(2) vdb(2) vp(2)
0.1 2.6905 8.5967 0.
0.105 2.9389 9.3638 0.
0.11 3.2379 10.205 0.
0.115 3.6046 11.137 0.
0.12 4.0649 12.181 0.
0.125 4.66 13.368 0.
0.13 5.4592 14.743 0.
0.135 6.5893 16.377 0.
0.14 8.3094 18.391 0.
0.145 11.245 21.019 0.
0.15 17.387 24.805 0.
0.155 38.319 31.668 0.
0.16 187.98 45.482 -180.
0.165 27.221 28.698 -180.
0.17 14.673 23.33 -180.
0.175 10.043 20.038 -180.
0.18 7.6345 17.656 -180.
0.185 6.1576 15.788 -180.
0.19 5.1595 14.252 -180.
0.195 4.4398 12.947 -180.
0.2 3.8964 11.813 -180.
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
100 cascaded NMOS inverters
# iter(0) V(1) V(2) V(3) V(4) V(5)
+ V(6) V(7) V(8) V(9) V(10) V(11) V(12)
+ V(13) V(14) V(15) V(16) V(17) V(18) V(19)
+ V(20) V(21) V(22) V(23) V(24) V(25) V(26)
+ V(27) V(28) V(29) V(30) V(31) V(32) V(33)
+ V(34) V(35) V(36) V(37) V(38) V(39) V(40)
+ V(41) V(42) V(43) V(44) V(45) V(46) V(47)
+ V(48) V(49) V(50) V(51) V(52) V(53) V(54)
+ V(55) V(56) V(57) V(58) V(59) V(60) V(61)
+ V(62) V(63) V(64) V(65) V(66) V(67) V(68)
+ V(69) V(70) V(71) V(72) V(73) V(74) V(75)
+ V(76) V(77) V(78) V(79) V(80) V(81) V(82)
+ V(83) V(84) V(85) V(86) V(87) V(88) V(89)
+ V(90) V(91) V(92) V(93) V(94) V(95) V(96)
+ V(97) V(98) V(99) V(100) V(101) V(102)
300.15 32. 5. 0.8 3.0455 0.49727 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
18 cascaded NMOS inverters
# iter(0) V(1) V(2) V(3) V(4) V(5)
+ V(6) V(7) V(8) V(9) V(10) V(11) V(12)
+ V(13) V(14) V(15) V(16) V(17) V(18) V(19)
+ V(20)
300.15 24. 5. 0.8 3.0455 0.49727 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
30 cascaded NMOS inverters
# iter(0) V(1) V(2) V(3) V(4) V(5)
+ V(6) V(7) V(8) V(9) V(10) V(11) V(12)
+ V(13) V(14) V(15) V(16) V(17) V(18) V(19)
+ V(20) V(21) V(22) V(23) V(24) V(25) V(26)
+ V(27) V(28) V(29) V(30) V(31) V(32)
300.15 45. 5. 0.8 3.0455 0.49727 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034
+ 0.46622 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
+ 3.2034 0.46622 3.2034 0.46622 3.2034 0.46622
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
100 cascaded NMOS inverters
# iter(0) V(1) V(2) V(3) V(4) V(5)
+ V(6) V(7) V(8) V(9) V(10) V(11) V(12)
+ V(13) V(14) V(15) V(16) V(17) V(18) V(19)
+ V(20) V(21) V(22) V(23) V(24) V(25) V(26)
+ V(27) V(28) V(29) V(30) V(31) V(32) V(33)
+ V(34) V(35) V(36) V(37) V(38) V(39) V(40)
+ V(41) V(42) V(43) V(44) V(45) V(46) V(47)
+ V(48) V(49) V(50) V(51) V(52) V(53) V(54)
+ V(55) V(56) V(57) V(58) V(59) V(60) V(61)
+ V(62) V(63) V(64) V(65) V(66) V(67) V(68)
+ V(69) V(70) V(71) V(72) V(73) V(74) V(75)
+ V(76) V(77) V(78) V(79) V(80) V(81) V(82)
+ V(83) V(84) V(85) V(86) V(87) V(88) V(89)
+ V(90) V(91) V(92) V(93) V(94) V(95) V(96)
+ V(97) V(98) V(99) V(100) V(101) V(102) V(103)
+ V(104) V(105) V(106) V(107) V(108) V(109) V(110)
+ V(111) V(112) V(113) V(114) V(115) V(116) V(117)
+ V(118) V(119) V(120) V(121) V(122) V(123) V(124)
+ V(125) V(126) V(127) V(128) V(129) V(130) V(131)
+ V(132) V(133) V(134) V(135) V(136) V(137) V(138)
+ V(139) V(140) V(141) V(142) V(143) V(144) V(145)
+ V(146) V(147) V(148) V(149) V(150) V(151) V(152)
+ V(153) V(154) V(155) V(156) V(157) V(158) V(159)
+ V(160) V(161) V(162) V(163) V(164) V(165) V(166)
+ V(167) V(168) V(169) V(170) V(171) V(172) V(173)
+ V(174) V(175) V(176) V(177) V(178) V(179) V(180)
+ V(181) V(182) V(183) V(184) V(185) V(186) V(187)
+ V(188) V(189) V(190) V(191) V(192) V(193) V(194)
+ V(195) V(196) V(197) V(198) V(199) V(200) V(201)
300.15 24. 0.8 5. 3.0455 5. 0.49727
+ 5. 3.2034 5. 0.46622 5. 3.2034 5.
+ 0.46622 5. 3.2034 5. 0.46622 5. 3.2034
+ 5. 0.46622 5. 3.2034 5. 0.46622 5.
+ 3.2034 5. 0.46622 5. 3.2034 5. 0.46622
+ 5. 3.2034 5. 0.46622 5. 3.2034 5.
+ 0.46622 5. 3.2034 5. 0.46622 5. 3.2034
+ 5. 0.46622 5. 3.2034 5. 0.46622 5.
+ 3.2034 5. 0.46622 5. 3.2034 5. 0.46622
+ 5. 3.2034 5. 0.46622 5. 3.2034 5.
+ 0.46622 5. 3.2034 5. 0.46622 5. 3.2034
+ 5. 0.46622 5. 3.2034 5. 0.46622 5.
+ 3.2034 5. 0.46622 5. 3.2034 5. 0.46622
+ 5. 3.2034 5. 0.46622 5. 3.2034 5.
+ 0.46622 5. 3.2034 5. 0.46622 5. 3.2034
+ 5. 0.46622 5. 3.2034 5. 0.46622 5.
+ 3.2034 5. 0.46622 5. 3.2034 5. 0.46622
+ 5. 3.2034 5. 0.46622 5. 3.2034 5.
+ 0.46622 5. 3.2034 5. 0.46622 5. 3.2034
+ 5. 0.46622 5. 3.2034 5. 0.46622 5.
+ 3.2034 5. 0.46622 5. 3.2034 5. 0.46622
+ 5. 3.2034 5. 0.46622 5. 3.2034 5.
+ 0.46622 5. 3.2034 5. 0.46622 5. 3.2034
+ 5. 0.46622 5. 3.2034 5. 0.46622 5.
+ 3.2034 5. 0.46622 5. 3.2034 5. 0.46622
+ 5. 3.2034 5. 0.46622 5. 3.2034 5.
+ 0.46622 5. 3.2034 5. 0.46622 5. 3.2034
+ 5. 0.46622 5. 3.2034 5. 0.46622 5.
+ 3.2034 5. 0.46622 5. 3.2034 5. 0.46622
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
2 stage op-amp open loop 02/16/88
# iter(0) v(1) v(2) v(3) v(4) v(5)
+ v(6) v(7) v(8) v(9)
300.15 18. 0. 0. 0.87501 0.87512 -1.1707
+-0.23876 -1.6303 -2.5 2.5
vdb(6) 0. 20. 40. 60. 80.
vp(6)-180. -90. 0. 90. 180.
+-----------------+----------------+-----------------+----------------+
1. | . +. . * |
1.5849 | . + . . * |
2.5119 | . + . . * |
3.9811 | . + . . * |
6.3096 | . + . . * |
10. | . + . . * |
15.849 | . + . . * |
25.119 | . + . * |
39.811 | . + . * . |
63.096 | .+ . * . |
100. | + . * . |
158.49 | + . * . |
251.19 | + .* . |
398.11 | + * . . |
630.96 | +. * . . |
1.K | +. * . . |
1.5849K| +. * . . |
2.5119K| +* . . |
3.9811K| *+ . . . |
6.3096K| * + . . . |
10.K | * + . . . |
15.849K| * + . . . |
25.119K* + . . . |
39.811K* + . . . |
63.096K*+ . . . |
100.K * . . . + |
158.49K* . . . + |
251.19K* . . . + |
398.11K* . . . + |
630.96K* . . . + |
1.Meg * . . .+ |
1.5849M* . . +. |
2.5119M* . . + . |
3.9811M* . . + . |
6.3096M* . . + . |
10.Meg * . . + . |
+-----------------+----------------+-----------------+----------------+
v(6) -4. -2. 0. 2. 4.
+-----------------+----------------+-----------------+----------------+
-500.u | * . . . |
-480.u | * . . . |
-460.u | * . . . |
-440.u | * . . . |
-420.u | * . . . |
-400.u | * . . . |
-380.u | * . . . |
-360.u | * . . . |
-340.u | * . . . |
-320.u | * . . . |
-300.u | * . . . |
-280.u | * . . . |
-260.u | * . . . |
-240.u | * . . . |
-220.u | * . . . |
-200.u | * . . . |
-180.u | * . . . |
-160.u | * . . . |
-140.u | * . . . |
-120.u | *. . . |
-100.u | . * . . |
-80.u | . * . . |
-60.u | . * . . |
-40.u | . * . . |
-20.u | . * . . |
0. | . * . . |
20.u | . * . |
40.u | . . * . |
60.u | . . * . |
80.u | . . * . |
100.u | . . * . |
120.u | . . * . |
140.u | . . * . |
160.u | . . * . |
180.u | . . * |
200.u | . . .* |
220.u | . . . * |
240.u | . . . * |
260.u | . . . * |
280.u | . . . * |
300.u | . . . * |
320.u | . . . * |
340.u | . . . * |
360.u | . . . * |
380.u | . . . * |
400.u | . . . * |
420.u | . . . * |
440.u | . . . * |
460.u | . . . * |
480.u | . . . * |
500.u | . . . * |
+-----------------+----------------+-----------------+----------------+
vdb(6) 0. 20. 40. 60. 80.
vp(6)-180. -90. 0. 90. 180.
+-----------------+----------------+-----------------+----------------+
1. | . * + . |
1.5849 | . * + . |
2.5119 | . * + . |
3.9811 | . * + . |
6.3096 | . * + . |
10. | . * + . |
15.849 | . * + . |
25.119 | . * +. . |
39.811 | . * +. . |
63.096 | . * + . . |
100. | . * + . . |
158.49 | . * + . . |
251.19 | . * + . . |
398.11 | . * + . . |
630.96 | . * + . . |
1.K | * + . . |
1.5849K| * . + . . |
2.5119K| * .+ . . |
3.9811K| * +. . . |
6.3096K| * + . . . |
10.K |* + . . . |
15.849K* + . . . |
25.119K* + . . . |
39.811K* + . . . |
63.096K* . . . |
100.K * . . . + |
158.49K* . . . + |
251.19K* . . . + |
398.11K* . . . + |
630.96K* . . .+ |
1.Meg * . . + |
1.5849M* . . +. |
2.5119M* . . + . |
3.9811M* . . + . |
6.3096M* . . + . |
10.Meg * . . + . |
+-----------------+----------------+-----------------+----------------+
cgs(M7)
5.f 5.5f 6.f 6.5f 7.f
+-----------------+----------------+-----------------+----------------+
-500.u | * . . |
-480.u | .* . . |
-460.u | . * . . |
-440.u | . * . . |
-420.u | . * . . |
-400.u | . * . . |
-380.u | . * . . |
-360.u | . * . . |
-340.u | . * . . |
-320.u | . * . . |
-300.u | . * . . |
-280.u | . * . . |
-260.u | . .* . |
-240.u | . . * . |
-220.u | . . * . |
-200.u | . . * . |
-180.u | . . * . |
-160.u | . . * . |
-140.u | . . *. |
-120.u | . . .* |
-100.u | . . . * |
-80.u | . . . * |
-60.u | . . . * |
-40.u | . . . * |
-20.u | . . . * |
0. | . . . * |
20.u | . . . * |
40.u | . . . * |
60.u | . . . * |
80.u | . . . * |
100.u | . . . * |
120.u | . . . * |
140.u | . . . * |
160.u | . . . *|
180.u | . . . *|
200.u | . . . *
220.u | . . . *
240.u | . . . *
260.u | . . . *
280.u | . . . *
300.u | . . . *
320.u | . . . *
340.u | . . . *
360.u | . . . *
380.u | . . . *
400.u | . . . *
420.u | . . . *
440.u | . . . *
460.u | . . . *
480.u | . . . *
500.u | . . . *
+-----------------+----------------+-----------------+----------------+
ACS (Al's Circuit Simulator) 0.2808
Never trust any version less than 1.0
Copyright 1982-2000, Albert Davis
ACS comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details
2 stage op-amp, conected as voltage follower 02/16/88
# iter(0) v(1) v(3) v(4) v(5) v(6)
+ v(7) v(8) v(9)
300.15 20. -1. 0.87713 0.88005 -1.9308 -0.99992
+-1.6303 -2.5 2.5
vdb(6)-90. -60. -30. 0. 30.
vp(6)-180. -90. 0. 90. 180.
+-----------------+----------------+-----------------+----------------+
1. | . + *. |
1.5849 | . + *. |
2.5119 | . + *. |
3.9811 | . + *. |
6.3096 | . + *. |
10. | . + *. |
15.849 | . + *. |
25.119 | . + *. |
39.811 | . + *. |
63.096 | . + *. |
100. | . + *. |
158.49 | . + *. |
251.19 | . + *. |
398.11 | . + *. |
630.96 | . + * |
1.K | . + * |
1.5849K| . +. * |
2.5119K| . +. * |
3.9811K| . + . * |
6.3096K| . + . * |
10.K | . + . * |
15.849K| . + . * |
25.119K| . + . * |
39.811K| + . . * . |
63.096K| + . . * . |
100.K | . . * . + |
158.49K| . . * . + |
251.19K| . * . + |
398.11K| . * . . + |
630.96K| . * . . + |
1.Meg | . * . .+ |
1.5849M| . * . +. |
2.5119M| . * . +. |
3.9811M| .* . +. |
6.3096M| *. . +. |
10.Meg | * . . + |
+-----------------+----------------+-----------------+----------------+
v(6) -4. -2. 0. 2. 4.
+-----------------+----------------+-----------------+----------------+
-5. | * . . . |
-4.8 | * . . . |
-4.6 | * . . . |
-4.4 | * . . . |
-4.2 | * . . . |
-4. | * . . . |
-3.8 | * . . . |
-3.6 | * . . . |
-3.4 | * . . . |
-3.2 | * . . . |
-3. | * . . . |
-2.8 | * . . . |
-2.6 | * . . . |
-2.4 | * . . . |
-2.2 | * . . . |
-2. | *. . . |
-1.8 | .* . . |
-1.6 | . * . . |
-1.4 | . * . . |
-1.2 | . * . . |
-1. | . * . . |
-0.8 | . * . . |
-0.6 | . * . . |
-0.4 | . * . . |
-0.2 | . * . . |
0. | . * . |
0.2 | . . * . |
0.4 | . . * . |
0.6 | . . * . |
0.8 | . . * . |
1. | . . * . |
1.2 | . . * . |
1.4 | . . * . |
1.6 | . . * . |
1.8 | . . * . |
2. | . . *. |
2.2 | . . .* |
2.4 | . . . * |
2.6 | . . . * |
2.8 | . . . * |
3. | . . . * |
3.2 | . . . * |
3.4 | . . . * |
3.6 | . . . * |
3.8 | . . . * |
4. | . . . * |
4.2 | . . . * |
4.4 | . . . * |
4.6 | . . . * |
4.8 | . . . * |
5. | . . . * |
+-----------------+----------------+-----------------+----------------+
v(6) -4. -2. 0. 2. 4.
+-----------------+----------------+-----------------+----------------+
0. | . * . . |
10.u | . * . . |
20.u | . * . . |
30.u | . * . . |
40.u | . * . . |
50.u | . * . . |
60.u | . * . . |
70.u | . * . . |
80.u | . * . . |
90.u | . * . . |
100.u | . * . . |
110.u | . * . . |
120.u | . * . . |
130.u | . * . . |
140.u | . * . . |
150.u | . * . . |
160.u | . * . . |
170.u | . * . . |
180.u | . * . . |
190.u | . * . . |
200.u | . * . . |
210.u | . * . . |
220.u | . *. . |
230.u | . . * . |
240.u | . . * . |
250.u | . . * . |
260.u | . . * . |
270.u | . . * . |
280.u | . . * . |
290.u | . . * . |
300.u | . . * . |
310.u | . . * . |
320.u | . . * . |
330.u | . . * . |
340.u | . . * . |
350.u | . . * . |
360.u | . . * . |
370.u | . . * . |
380.u | . . * . |
390.u | . . * . |
400.u | . . * . |
410.u | . . * . |
420.u | . . * . |
430.u | . . * . |
440.u | . . * . |
450.u | . . * . |
460.u | . . * . |
470.u | . . * . |
480.u | . . * . |
490.u | . . * . |
500.u | . . * . |
510.u | . . * . |
520.u | . . * . |
530.u | . . * . |
540.u | . . * . |
550.u | . . * . |
560.u | . . * . |
570.u | . . * . |
580.u | . .* . |
590.u | . * . |
600.u | . *. . |
610.u | . * . . |
620.u | . * . . |
630.u | . * . . |
640.u | . * . . |
650.u | . * . . |
660.u | . * . . |
670.u | . * . . |
680.u | . * . . |
690.u | . * . . |
700.u | . * . . |
710.u | . * . . |
720.u | . * . . |
730.u | . * . . |
740.u | . * . . |
750.u | . * . . |
760.u | . * . . |
770.u | . * . . |
780.u | . * . . |
790.u | . * . . |
800.u | . * . . |
810.u | . * . . |
820.u | . *. . |
830.u | . . * . |
840.u | . . * . |
850.u | . . * . |
860.u | . . * . |
870.u | . . * . |
880.u | . . * . |
890.u | . . * . |
900.u | . . * . |
910.u | . . * . |
920.u | . . * . |
930.u | . . * . |
940.u | . . * . |
950.u | . . * . |
960.u | . . * . |
970.u | . . * . |
980.u | . . * . |
990.u | . . * . |
0.001 | . . * . |
+-----------------+----------------+-----------------+----------------+
examples/sc18.ckt 0000664 0000000 0000000 00000002632 11454012162 0014154 0 ustar 00root root 0000000 0000000 18 cascaded NMOS inverters
md1 3 2 0 0 modeld w=10u l=2u
ml1 1 1 3 0 modell w=2u l=2u
md2 4 3 0 0 modeld w=10u l=2u
ml2 1 1 4 0 modell w=2u l=2u
md3 5 4 0 0 modeld w=10u l=2u
ml3 1 1 5 0 modell w=2u l=2u
md4 6 5 0 0 modeld w=10u l=2u
ml4 1 1 6 0 modell w=2u l=2u
md5 7 6 0 0 modeld w=10u l=2u
ml5 1 1 7 0 modell w=2u l=2u
md6 8 7 0 0 modeld w=10u l=2u
ml6 1 1 8 0 modell w=2u l=2u
md7 9 8 0 0 modeld w=10u l=2u
ml7 1 1 9 0 modell w=2u l=2u
md8 10 9 0 0 modeld w=10u l=2u
ml8 1 1 10 0 modell w=2u l=2u
md9 11 10 0 0 modeld w=10u l=2u
ml9 1 1 11 0 modell w=2u l=2u
md10 12 11 0 0 modeld w=10u l=2u
ml10 1 1 12 0 modell w=2u l=2u
md11 13 12 0 0 modeld w=10u l=2u
ml11 1 1 13 0 modell w=2u l=2u
md12 14 13 0 0 modeld w=10u l=2u
ml12 1 1 14 0 modell w=2u l=2u
md13 15 14 0 0 modeld w=10u l=2u
ml13 1 1 15 0 modell w=2u l=2u
md14 16 15 0 0 modeld w=10u l=2u
ml14 1 1 16 0 modell w=2u l=2u
md15 17 16 0 0 modeld w=10u l=2u
ml15 1 1 17 0 modell w=2u l=2u
md16 18 17 0 0 modeld w=10u l=2u
ml16 1 1 18 0 modell w=2u l=2u
md17 19 18 0 0 modeld w=10u l=2u
ml17 1 1 19 0 modell w=2u l=2u
md18 20 19 0 0 modeld w=10u l=2u
ml18 1 1 20 0 modell w=2u l=2u
vdd 1 0 5
vin 2 0 .8
.MODEL MODELD NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5 nfs=1e12)
.MODEL MODELL NMOS (level=2 KP=28U VTO=0.7 LAMBDA=0.01 GAMMA=0.9 PHI=0.5 nfs=1e12)
.PRINT OP iter(0) V(nodes)
.op
.end
install-sh 0000775 0000000 0000000 00000022021 11454012162 0013053 0 ustar 00root root 0000000 0000000 #!/bin/sh
# install - install a program, script, or datafile
scriptversion=2005-05-14.22
# This originates from X11R5 (mit/util/scripts/install.sh), which was
# later released in X11R6 (xc/config/util/install.sh) with the
# following copyright and license.
#
# Copyright (C) 1994 X Consortium
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to
# deal in the Software without restriction, including without limitation the
# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
# sell copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC-
# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#
# Except as contained in this notice, the name of the X Consortium shall not
# be used in advertising or otherwise to promote the sale, use or other deal-
# ings in this Software without prior written authorization from the X Consor-
# tium.
#
#
# FSF changes to this file are in the public domain.
#
# Calling this script install-sh is preferred over install.sh, to prevent
# `make' implicit rules from creating a file called install from it
# when there is no Makefile.
#
# This script is compatible with the BSD install script, but was written
# from scratch. It can only install one file at a time, a restriction
# shared with many OS's install programs.
# set DOITPROG to echo to test this script
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doit="${DOITPROG-}"
# put in absolute paths if you don't have them in your path; or use env. vars.
mvprog="${MVPROG-mv}"
cpprog="${CPPROG-cp}"
chmodprog="${CHMODPROG-chmod}"
chownprog="${CHOWNPROG-chown}"
chgrpprog="${CHGRPPROG-chgrp}"
stripprog="${STRIPPROG-strip}"
rmprog="${RMPROG-rm}"
mkdirprog="${MKDIRPROG-mkdir}"
chmodcmd="$chmodprog 0755"
chowncmd=
chgrpcmd=
stripcmd=
rmcmd="$rmprog -f"
mvcmd="$mvprog"
src=
dst=
dir_arg=
dstarg=
no_target_directory=
usage="Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE
or: $0 [OPTION]... SRCFILES... DIRECTORY
or: $0 [OPTION]... -t DIRECTORY SRCFILES...
or: $0 [OPTION]... -d DIRECTORIES...
In the 1st form, copy SRCFILE to DSTFILE.
In the 2nd and 3rd, copy all SRCFILES to DIRECTORY.
In the 4th, create DIRECTORIES.
Options:
-c (ignored)
-d create directories instead of installing files.
-g GROUP $chgrpprog installed files to GROUP.
-m MODE $chmodprog installed files to MODE.
-o USER $chownprog installed files to USER.
-s $stripprog installed files.
-t DIRECTORY install into DIRECTORY.
-T report an error if DSTFILE is a directory.
--help display this help and exit.
--version display version info and exit.
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shift
continue;;
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-m) chmodcmd="$chmodprog $2"
shift
shift
continue;;
-o) chowncmd="$chownprog $2"
shift
shift
continue;;
-s) stripcmd=$stripprog
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shift
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done
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for src
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oIFS=$IFS
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set x `echo "$dstdir" | sed -e 's@/@%@g' -e 's@^%@/@'`
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trap '(exit $?); exit' 1 2 13 15
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# and set any options; do chmod last to preserve setuid bits.
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{ test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } \
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{ $doit $mvcmd -f "$dsttmp" "$dstdir/$dstfile" 2>/dev/null \
|| {
# The rename failed, perhaps because mv can't rename something else
# to itself, or perhaps because mv is so ancient that it does not
# support -f.
# Now remove or move aside any old file at destination location.
# We try this two ways since rm can't unlink itself on some
# systems and the destination file might be busy for other
# reasons. In this case, the final cleanup might fail but the new
# file should still install successfully.
{
if test -f "$dstdir/$dstfile"; then
$doit $rmcmd -f "$dstdir/$dstfile" 2>/dev/null \
|| $doit $mvcmd -f "$dstdir/$dstfile" "$rmtmp" 2>/dev/null \
|| {
echo "$0: cannot unlink or rename $dstdir/$dstfile" >&2
(exit 1); exit 1
}
else
:
fi
} &&
# Now rename the file to the real destination.
$doit $mvcmd "$dsttmp" "$dstdir/$dstfile"
}
}
fi || { (exit 1); exit 1; }
done
# The final little trick to "correctly" pass the exit status to the exit trap.
{
(exit 0); exit 0
}
# Local variables:
# eval: (add-hook 'write-file-hooks 'time-stamp)
# time-stamp-start: "scriptversion="
# time-stamp-format: "%:y-%02m-%02d.%02H"
# time-stamp-end: "$"
# End:
missing 0000775 0000000 0000000 00000025406 11454012162 0012460 0 ustar 00root root 0000000 0000000 #! /bin/sh
# Common stub for a few missing GNU programs while installing.
scriptversion=2005-06-08.21
# Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004, 2005
# Free Software Foundation, Inc.
# Originally by Fran,cois Pinard , 1996.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
if test $# -eq 0; then
echo 1>&2 "Try \`$0 --help' for more information"
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fi
run=:
# In the cases where this matters, `missing' is being run in the
# srcdir already.
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fi
msg="missing on your system"
case "$1" in
--run)
# Try to run requested program, and just exit if it succeeds.
run=
shift
"$@" && exit 0
# Exit code 63 means version mismatch. This often happens
# when the user try to use an ancient version of a tool on
# a file that requires a minimum version. In this case we
# we should proceed has if the program had been absent, or
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run=:
msg="probably too old"
fi
;;
-h|--h|--he|--hel|--help)
echo "\
$0 [OPTION]... PROGRAM [ARGUMENT]...
Handle \`PROGRAM [ARGUMENT]...' for when PROGRAM is missing, or return an
error status if there is no known handling for PROGRAM.
Options:
-h, --help display this help and exit
-v, --version output version information and exit
--run try to run the given command, and emulate it if it fails
Supported PROGRAM values:
aclocal touch file \`aclocal.m4'
autoconf touch file \`configure'
autoheader touch file \`config.h.in'
automake touch all \`Makefile.in' files
bison create \`y.tab.[ch]', if possible, from existing .[ch]
flex create \`lex.yy.c', if possible, from existing .c
help2man touch the output file
lex create \`lex.yy.c', if possible, from existing .c
makeinfo touch the output file
tar try tar, gnutar, gtar, then tar without non-portable flags
yacc create \`y.tab.[ch]', if possible, from existing .[ch]
Send bug reports to ."
exit $?
;;
-v|--v|--ve|--ver|--vers|--versi|--versio|--version)
echo "missing $scriptversion (GNU Automake)"
exit $?
;;
-*)
echo 1>&2 "$0: Unknown \`$1' option"
echo 1>&2 "Try \`$0 --help' for more information"
exit 1
;;
esac
# Now exit if we have it, but it failed. Also exit now if we
# don't have it and --version was passed (most likely to detect
# the program).
case "$1" in
lex|yacc)
# Not GNU programs, they don't have --version.
;;
tar)
if test -n "$run"; then
echo 1>&2 "ERROR: \`tar' requires --run"
exit 1
elif test "x$2" = "x--version" || test "x$2" = "x--help"; then
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;;
*)
if test -z "$run" && ($1 --version) > /dev/null 2>&1; then
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# running `$TOOL --version' or `$TOOL --help' to check whether
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;;
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aclocal*)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`acinclude.m4' or \`${configure_ac}'. You might want
to install the \`Automake' and \`Perl' packages. Grab them from
any GNU archive site."
touch aclocal.m4
;;
autoconf)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`${configure_ac}'. You might want to install the
\`Autoconf' and \`GNU m4' packages. Grab them from any GNU
archive site."
touch configure
;;
autoheader)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`acconfig.h' or \`${configure_ac}'. You might want
to install the \`Autoconf' and \`GNU m4' packages. Grab them
from any GNU archive site."
files=`sed -n 's/^[ ]*A[CM]_CONFIG_HEADER(\([^)]*\)).*/\1/p' ${configure_ac}`
test -z "$files" && files="config.h"
touch_files=
for f in $files; do
case "$f" in
*:*) touch_files="$touch_files "`echo "$f" |
sed -e 's/^[^:]*://' -e 's/:.*//'`;;
*) touch_files="$touch_files $f.in";;
esac
done
touch $touch_files
;;
automake*)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified \`Makefile.am', \`acinclude.m4' or \`${configure_ac}'.
You might want to install the \`Automake' and \`Perl' packages.
Grab them from any GNU archive site."
find . -type f -name Makefile.am -print |
sed 's/\.am$/.in/' |
while read f; do touch "$f"; done
;;
autom4te)
echo 1>&2 "\
WARNING: \`$1' is needed, but is $msg.
You might have modified some files without having the
proper tools for further handling them.
You can get \`$1' as part of \`Autoconf' from any GNU
archive site."
file=`echo "$*" | sed -n 's/.*--output[ =]*\([^ ]*\).*/\1/p'`
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touch $file
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test -z "$file" || exec >$file
echo "#! /bin/sh"
echo "# Created by GNU Automake missing as a replacement of"
echo "# $ $@"
echo "exit 0"
chmod +x $file
exit 1
fi
;;
bison|yacc)
echo 1>&2 "\
WARNING: \`$1' $msg. You should only need it if
you modified a \`.y' file. You may need the \`Bison' package
in order for those modifications to take effect. You can get
\`Bison' from any GNU archive site."
rm -f y.tab.c y.tab.h
if [ $# -ne 1 ]; then
eval LASTARG="\${$#}"
case "$LASTARG" in
*.y)
SRCFILE=`echo "$LASTARG" | sed 's/y$/c/'`
if [ -f "$SRCFILE" ]; then
cp "$SRCFILE" y.tab.c
fi
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if [ -f "$SRCFILE" ]; then
cp "$SRCFILE" y.tab.h
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;;
esac
fi
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echo >y.tab.h
fi
if [ ! -f y.tab.c ]; then
echo 'main() { return 0; }' >y.tab.c
fi
;;
lex|flex)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified a \`.l' file. You may need the \`Flex' package
in order for those modifications to take effect. You can get
\`Flex' from any GNU archive site."
rm -f lex.yy.c
if [ $# -ne 1 ]; then
eval LASTARG="\${$#}"
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SRCFILE=`echo "$LASTARG" | sed 's/l$/c/'`
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cp "$SRCFILE" lex.yy.c
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;;
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fi
if [ ! -f lex.yy.c ]; then
echo 'main() { return 0; }' >lex.yy.c
fi
;;
help2man)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified a dependency of a manual page. You may need the
\`Help2man' package in order for those modifications to take
effect. You can get \`Help2man' from any GNU archive site."
file=`echo "$*" | sed -n 's/.*-o \([^ ]*\).*/\1/p'`
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echo ".ab help2man is required to generate this page"
exit 1
fi
;;
makeinfo)
echo 1>&2 "\
WARNING: \`$1' is $msg. You should only need it if
you modified a \`.texi' or \`.texinfo' file, or any other file
indirectly affecting the aspect of the manual. The spurious
call might also be the consequence of using a buggy \`make' (AIX,
DU, IRIX). You might want to install the \`Texinfo' package or
the \`GNU make' package. Grab either from any GNU archive site."
# The file to touch is that specified with -o ...
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# ... or it is derived from the source name (dir/f.texi becomes f.info)
test -z "$file" && file=`echo "$infile" | sed 's,.*/,,;s,.[^.]*$,,'`.info
fi
# If the file does not exist, the user really needs makeinfo;
# let's fail without touching anything.
test -f $file || exit 1
touch $file
;;
tar)
shift
# We have already tried tar in the generic part.
# Look for gnutar/gtar before invocation to avoid ugly error
# messages.
if (gnutar --version > /dev/null 2>&1); then
gnutar "$@" && exit 0
fi
if (gtar --version > /dev/null 2>&1); then
gtar "$@" && exit 0
fi
firstarg="$1"
if shift; then
case "$firstarg" in
*o*)
firstarg=`echo "$firstarg" | sed s/o//`
tar "$firstarg" "$@" && exit 0
;;
esac
case "$firstarg" in
*h*)
firstarg=`echo "$firstarg" | sed s/h//`
tar "$firstarg" "$@" && exit 0
;;
esac
fi
echo 1>&2 "\
WARNING: I can't seem to be able to run \`tar' with the given arguments.
You may want to install GNU tar or Free paxutils, or check the
command line arguments."
exit 1
;;
*)
echo 1>&2 "\
WARNING: \`$1' is needed, and is $msg.
You might have modified some files without having the
proper tools for further handling them. Check the \`README' file,
it often tells you about the needed prerequisites for installing
this package. You may also peek at any GNU archive site, in case
some other package would contain this missing \`$1' program."
exit 1
;;
esac
exit 0
# Local variables:
# eval: (add-hook 'write-file-hooks 'time-stamp)
# time-stamp-start: "scriptversion="
# time-stamp-format: "%:y-%02m-%02d.%02H"
# time-stamp-end: "$"
# End:
modelgen/ 0000775 0000000 0000000 00000000000 11454012162 0012644 5 ustar 00root root 0000000 0000000 modelgen/Make.depend 0000664 0000000 0000000 00000002556 11454012162 0014712 0 ustar 00root root 0000000 0000000 mg_main.o: mg_main.cc u_opt.h mode.h io_.h l_lib.h md.h io_trace.h \
io_error.h mg_out.h mg_.h ap.h patchlev.h
mg_error.o: mg_error.cc ap.h md.h io_trace.h io_error.h
mg_in.o: mg_in.cc mg_.h md.h io_trace.h io_error.h ap.h
mg_out_h.o: mg_out_h.cc mg_out.h mg_.h md.h io_trace.h io_error.h ap.h
mg_out_dump.o: mg_out_dump.cc md.h io_trace.h io_error.h mg_out.h mg_.h \
ap.h
mg_out_common.o: mg_out_common.cc mg_out.h mg_.h md.h io_trace.h \
io_error.h ap.h
mg_out_dev.o: mg_out_dev.cc mg_out.h mg_.h md.h io_trace.h io_error.h \
ap.h
mg_out_lib.o: mg_out_lib.cc mg_out.h mg_.h md.h io_trace.h io_error.h \
ap.h
mg_out_model.o: mg_out_model.cc mg_out.h mg_.h md.h io_trace.h io_error.h \
ap.h
mg_out_root.o: mg_out_root.cc md.h io_trace.h io_error.h mg_out.h mg_.h \
ap.h
ap_construct.o: ap_construct.cc u_opt.h mode.h io_.h l_lib.h md.h \
io_trace.h io_error.h ap.h
ap_convert.o: ap_convert.cc u_opt.h mode.h io_.h l_lib.h md.h io_trace.h \
io_error.h ap.h
ap_get.o: ap_get.cc ap.h md.h io_trace.h io_error.h
ap_match.o: ap_match.cc u_opt.h mode.h io_.h l_lib.h md.h io_trace.h \
io_error.h ap.h
ap_skip.o: ap_skip.cc ap.h md.h io_trace.h io_error.h
l_trim.o: l_trim.cc
u_opt1.o: u_opt1.cc u_opt.h mode.h io_.h l_lib.h md.h io_trace.h \
io_error.h
io_out.o: io_out.cc u_opt.h mode.h io_.h l_lib.h md.h io_trace.h \
io_error.h
io.o: io.cc io_.h l_lib.h md.h io_trace.h io_error.h
modelgen/Make1 0000664 0000000 0000000 00000006714 11454012162 0013535 0 ustar 00root root 0000000 0000000 #$Id: Make1,v 26.81 2008/05/27 05:33:43 al Exp $ -*- Makefile -*-
#
# Copyright (C) 2001 Albert Davis
# Author: Albert Davis
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
#------------------------------------------------------------------------
TARGET = gnucap-modelgen
#------------------------------------------------------------------------
DELETED =
#------------------------------------------------------------------------
#------------------------------------------------------------------------
RAW_SRCS = \
mg_main.cc mg_error.cc mg_in.cc mg_out_h.cc mg_out_dump.cc \
mg_out_common.cc mg_out_dev.cc mg_out_lib.cc mg_out_model.cc mg_out_root.cc
#------------------------------------------------------------------------
RAW_HDRS = mg_.h mg_out.h declare.h
#------------------------------------------------------------------------
RAW_OTHER = \
configure.old Make1 \
Makefile.am
#------------------------------------------------------------------------
RAW = $(RAW_HDRS) $(RAW_SRCS) $(RAW_OTHER)
#------------------------------------------------------------------------
#------------------------------------------------------------------------
IMPORTED_SRCS = \
ap_construct.cc ap_convert.cc ap_get.cc ap_match.cc ap_skip.cc \
l_trim.cc u_opt1.cc io_out.cc io.cc
IMPORTED_HDRS = \
ap.h io_.h io_error.h io_trace.h l_lib.h md.h patchlev.h u_opt.h mode.h
IMPORTED_OTHER = Makefile.in \
Make2.g++ Make2.Debug Make2.mingw32 Make3 Makefile.template
IMPORTED = $(IMPORTED_SRCS) $(IMPORTED_HDRS) $(IMPORTED_OTHER)
#------------------------------------------------------------------------
#------------------------------------------------------------------------
GENERATED_SRCS =
GENERATED_HDRS =
GENERATED_OTHER = Make.aux
GENERATED = $(GENERATED_HDRS) $(GENERATED_SRCS) $(GENERATED_OTHER)
#------------------------------------------------------------------------
#------------------------------------------------------------------------
GENERATED_DIST = Make.depend
IMPORTED_DIST = $(IMPORTED)
DISTFILES = $(RAW) $(GENERATED_DIST) $(IMPORTED_DIST)
#------------------------------------------------------------------------
#------------------------------------------------------------------------
SRCS = $(RAW_SRCS) $(GENERATED_SRCS) $(IMPORTED_SRCS)
HDRS = $(RAW_HDRS) $(GENERATED_HDRS) $(IMPORTED_HDRS)
OBJS = ${SRCS:.cc=.o}
TARGET_DEPENDS = $(OBJS) $(RAW)
#------------------------------------------------------------------------
#------------------------------------------------------------------------
MOSTLYCLEANFILES = $(OBJS) $(GENERATED)
CLEANFILES = $(MOSTLYCLEANFILES)
DISTCLEANFILES = $(CLEANFILES)
MAINTAINERCLEANFILES = $(DISTCLEANFILES)
#------------------------------------------------------------------------
#------------------------------------------------------------------------
modelgen/Make2.Debug 0000664 0000000 0000000 00000007222 11454012162 0014556 0 ustar 00root root 0000000 0000000 #$Id: Make2.Debug,v 26.97 2008/10/11 03:13:53 al Exp $ -*- Makefile -*-
# Copyright (C) 2001 Albert Davis
# Author: Albert Davis
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
#------------------------------------------------------------------------
VPATH = .:..
# Standard base for g++, debugging, a little optimization
# Running the program will give a spew of line markers for debugging.
CCC = g++
CCFLAGS = \
-DHAVE_LIBREADLINE \
-DUNIX -g -O0 -I. -I.. -DTRACE_UNTESTED \
-Wall -Wextra \
-Wswitch-enum -Wundef -Wpointer-arith -Woverloaded-virtual \
-Wcast-qual -Wcast-align -Wpacked -Wshadow -Wconversion \
-Winit-self -Wmissing-include-dirs -Winvalid-pch \
-Wvolatile-register-var -Wstack-protector \
-Wlogical-op -Wvla -Woverlength-strings -Wsign-conversion
#last line not in 4.1
LIBS = \
-lreadline -ltermcap \
LDFLAGS = -rdynamic
%.SUFFIXES:
.SUFFIXES: .o .cc
.cc.o:; $(CCC) $(CCFLAGS) -c $<
#------------------------------------------------------------------------
$(TARGET): $(TARGET_DEPENDS)
rm -f $@
$(CCC) $(CCFLAGS) $(OBJS) $(LIBS) $(LDFLAGS) -o $@
#------------------------------------------------------------
# warnings turned off, because they warn of nothing wrong
# 4.3
#-Wswitch-default -- lack of default is correct with enum
#-Wfloat-equal -- warns on NA, div by zero trap
#-Wpadded -- a bool in a class is enough
#-Wredundant-decls -- in both header and func is an error check
#-Wmissing-declarations -- pascal style
#-Wmissing-noreturn -- warns when always throws exception
#-Wunreachable-code -- warns even if reachable .. compiler bug??
#-Waggregate-return -- warns even if passed by reference
#-Wunsafe-loop-optimizations -- if can't unroll a loop
#-Winline
#-Wdisabled-optimization -- -O0 disables optimization, so it warns
# 4.2
#-Wpadded -- a bool in a class is enough
#-Winline
#-Waggregate-return -- warns even if passed by reference
#-Wfloat-equal -- warns on NA, div by zero trap
#-Wredundant-decls -- in both header and func is an error check
#-Wunsafe-loop-optimizations -- warns on any loop with variable count
# warnings turned off, because of the public headers
#-Wunreachable-code -- didn't use nonportable syntax to hide
#-Wmissing-noreturn -- didn't use nonportable syntax to hide
# warnings that should be on, but ...
#-Wshadow -- lambda functions
#------------------------------------------------------------
# If you are porting and using g++, you should use this file as a start,
# for a "debug" version, with extra warnings and run-time tracing.
# If you get errors or warnings, make a copy of it and modify that.
# After it works, use the file "Make2.g++" as a start for
# executable to use.
# If the port is non-trivial, check with me first because someone else
# may have already done it.
# If it works without changes, send me a note so I can put it in the docs.
# Please send the changes to aldavis@gnu.org
#------------------------------------------------------------
#------------------------------------------------------------
modelgen/Make2.g++ 0000664 0000000 0000000 00000004226 11454012162 0014105 0 ustar 00root root 0000000 0000000 #$Id: Make2.g++,v 26.134 2009/11/29 03:47:06 al Exp $ -*- Makefile -*-
# Copyright (C) 2001 Albert Davis
# Author: Albert Davis
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
#------------------------------------------------------------------------
VPATH = .:..
# Standard base for g++.
CCC = g++
CCFLAGS = \
-DHAVE_LIBREADLINE \
-DUNIX -O3 -DNDEBUG -I.. -I. -W
LIBS = \
-lreadline -ltermcap \
LDFLAGS = -rdynamic
.SUFFIXES:
.SUFFIXES: .o .cc
.cc.o:; $(CCC) $(CCFLAGS) -c $<
#------------------------------------------------------------------------
$(TARGET): $(TARGET_DEPENDS)
rm -f $@
$(CCC) $(CCFLAGS) $(OBJS) $(LIBS) $(LDFLAGS) -o $@
#------------------------------------------------------------
# If you are porting and using g++, you should use this file as a start,
# for a "release" version, optimized with run-time tracing removed.
# If you get errors or warnings, make a copy of it and modify that.
# For the first cut, use "Make2.Debug" as the start for more tracing,
# or "Make2.Trace" for an extreme amount of tracing.
# After it works, use the file "Make2.g++" as a start for
# executable to use.
# If the port is non-trivial, check with me first because someone else
# may have already done it.
# If it works without changes, send me a note so I can put it in the docs.
# Please send the changes to aldavis@gnu.org
#------------------------------------------------------------
#------------------------------------------------------------
modelgen/Make2.mingw32 0000664 0000000 0000000 00000004672 11454012162 0015024 0 ustar 00root root 0000000 0000000 #$Id: Make2.mingw32,v 26.81 2008/05/27 05:34:00 al Exp $ -*- Makefile -*-
# Copyright (C) 2001 Albert Davis
# Author: Albert Davis
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
#------------------------------------------------------------------------
VPATH = .:..
# Standard base for g++.
CCC = i586-mingw32msvc-g++
DLLTOOL = i586-mingw32msvc-dlltool
CCFLAGS = \
-O2 -DNDEBUG -I.. -I.
LIBS = \
LDFLAGS =
.SUFFIXES:
.SUFFIXES: .o .cc
.cc.o:; $(CCC) $(CCFLAGS) -c $<
#------------------------------------------------------------------------
$(TARGET): $(TARGET).exe lib$(TARGET).a
#------------------------------------------------------------------------
$(TARGET).exe: $(TARGET_DEPENDS)
rm -f $@
$(CCC) $(CCFLAGS) $(OBJS) $(LIBS) $(LDFLAGS) -o $@
#------------------------------------------------------------------------
lib$(TARGET).a: $(TARGET_DEPENDS) $(TARGET).exe
rm -f $@
$(DLLTOOL) -l $@ -D $(TARGET).exe $(OBJS) $(LIBS)
#------------------------------------------------------------
# If you are porting and using g++, you should use this file as a start,
# for a "release" version, optimized with run-time tracing removed.
# If you get errors or warnings, make a copy of it and modify that.
# For the first cut, use "Make2.Debug" as the start for more tracing,
# or "Make2.Trace" for an extreme amount of tracing.
# After it works, use the file "Make2.g++" as a start for
# executable to use.
# If the port is non-trivial, check with me first because someone else
# may have already done it.
# If it works without changes, send me a note so I can put it in the docs.
# Please send the changes to aldavis@gnu.org
#------------------------------------------------------------
#------------------------------------------------------------
modelgen/Make3 0000664 0000000 0000000 00000006004 11454012162 0013527 0 ustar 00root root 0000000 0000000 #$Id: Make3,v 26.133 2009/11/26 04:58:04 al Exp $ -*- Makefile -*-
# Copyright (C) 2001 Albert Davis
# Author: Albert Davis
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
#------------------------------------------------------------------------
# Part 3 of a Makefile
#------------------------------------------------------------------------
tags: $(HDRS) $(SRCS)
etags --c++ $(HDRS) $(SRCS)
#------------------------------------------------------------------------
checkin:
date "+#define PATCHLEVEL \"%Y.%m.%d RCS `cat rcsversion`\"" \
>patchlev.h
-ci -u`cat rcsversion` -m. -t/dev/null $(RAW)
-ci -r`cat rcsversion` -m. -t/dev/null $(DELETED) $(GENERATED)
touch patchlev.h
#------------------------------------------------------------------------
checkout:
co $(RAW)
#------------------------------------------------------------------------
#unclean:
# rm $(ALL)
#------------------------------------------------------------------------
backup:
-mkdir BACKUP
cp $(RAW) BACKUP
#------------------------------------------------------------------------
depend: Make.depend
Make.depend: $(SRCS) $(HDRS)
$(CCC) -MM $(CCFLAGS) $(SRCS) > Make.depend
#-----------------------------------------------------------------------------
date:
date "+#define PATCHLEVEL \"%Y.%m.%d RCS `cat rcsversion` +\"" \
>patchlev.h
#-----------------------------------------------------------------------------
header-check:
$(CCC) -o /dev/null $(RAW_HDRS)
#-----------------------------------------------------------------------------
manifest: MANIFEST
MANIFEST: $(DISTFILES)
echo $(DISTFILES) | sed 's/ /\n/g' >MANIFEST
#-----------------------------------------------------------------------------
md5sums: MD5SUMS
MD5SUMS: $(DISTFILES)
md5sum $(DISTFILES) | grep -v MD5SUMS >MD5SUMS
#-----------------------------------------------------------------------------
mostlyclean:
rm -rf $(MOSTLYCLEANFILES)
rm -f */*.o */*.obj */*.h */*.cc
clean:
rm -rf $(CLEANFILES)
rm -f */*.o */*.obj */*.h */*.cc
distclean:
rm -rf $(DISTCLEANFILES)
rm -f */*.o */*.obj */*.h */*.cc
rm -f *~ \#*\#
maintainer-clean:
rm -rf $(MAINTAINERCLEANFILES)
rm -f */*.o */*.obj */*.h */*.cc
rm -f *~ \#*\#
#-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
modelgen/Makefile.am 0000664 0000000 0000000 00000002776 11454012162 0014714 0 ustar 00root root 0000000 0000000 # -*- Automake -*-
#
# $Id: Makefile.am,v 26.70 2008/02/05 02:03:56 al Exp $
#
# Process this file with autoconf to produce a configure script.
#
#
# COPYRIGHT
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# Copyright (C) 2005 Dan McMahill
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
bin_PROGRAMS= gnucap-modelgen
gnucap_modelgen_SOURCES= \
ap_construct.cc ap_convert.cc ap_get.cc ap_match.cc ap_skip.cc \
l_trim.cc u_opt1.cc io_out.cc io.cc \
ap.h io_.h io_error.h io_trace.h l_lib.h md.h patchlev.h u_opt.h mode.h \
mg_main.cc mg_error.cc mg_in.cc mg_out_h.cc mg_out_dump.cc \
mg_out_common.cc mg_out_dev.cc mg_out_lib.cc mg_out_model.cc mg_out_root.cc \
mg_.h mg_out.h declare.h
EXTRA_DIST= \
Make1 Make3 Make.depend Make2.g++ Make2.Debug Make2.mingw32 \
configure.old Makefile.template
INCLUDES= -I$(top_srcdir)/src
modelgen/Makefile.in 0000664 0000000 0000000 00000042146 11454012162 0014720 0 ustar 00root root 0000000 0000000 # Makefile.in generated by automake 1.11 from Makefile.am.
# @configure_input@
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
# Inc.
# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.
@SET_MAKE@
# -*- Automake -*-
#
# $Id: Makefile.am,v 26.70 2008/02/05 02:03:56 al Exp $
#
# Process this file with autoconf to produce a configure script.
#
#
# COPYRIGHT
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# Copyright (C) 2005 Dan McMahill
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
VPATH = @srcdir@
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INSTALL_HEADER = $(INSTALL_DATA)
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NORMAL_INSTALL = :
PRE_INSTALL = :
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gnucap_modelgen_SOURCES = \
ap_construct.cc ap_convert.cc ap_get.cc ap_match.cc ap_skip.cc \
l_trim.cc u_opt1.cc io_out.cc io.cc \
ap.h io_.h io_error.h io_trace.h l_lib.h md.h patchlev.h u_opt.h mode.h \
mg_main.cc mg_error.cc mg_in.cc mg_out_h.cc mg_out_dump.cc \
mg_out_common.cc mg_out_dev.cc mg_out_lib.cc mg_out_model.cc mg_out_root.cc \
mg_.h mg_out.h declare.h
EXTRA_DIST = \
Make1 Make3 Make.depend Make2.g++ Make2.Debug Make2.mingw32 \
configure.old Makefile.template
INCLUDES = -I$(top_srcdir)/src
all: all-am
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gnucap-modelgen$(EXEEXT): $(gnucap_modelgen_OBJECTS) $(gnucap_modelgen_DEPENDENCIES)
@rm -f gnucap-modelgen$(EXEEXT)
$(CXXLINK) $(gnucap_modelgen_OBJECTS) $(gnucap_modelgen_LDADD) $(LIBS)
mostlyclean-compile:
-rm -f *.$(OBJEXT)
distclean-compile:
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ap_construct.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ap_convert.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ap_get.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ap_match.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ap_skip.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/io.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/io_out.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/l_trim.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_error.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_in.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_main.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_out_common.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_out_dev.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_out_dump.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_out_h.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_out_lib.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_out_model.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mg_out_root.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/u_opt1.Po@am__quote@
.cc.o:
@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ $<
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@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
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ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
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done | \
$(AWK) '{ files[$$0] = 1; nonempty = 1; } \
END { if (nonempty) { for (i in files) print i; }; }'`; \
mkid -fID $$unique
tags: TAGS
TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
$(TAGS_FILES) $(LISP)
set x; \
here=`pwd`; \
list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
unique=`for i in $$list; do \
if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
done | \
$(AWK) '{ files[$$0] = 1; nonempty = 1; } \
END { if (nonempty) { for (i in files) print i; }; }'`; \
shift; \
if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
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if test $$# -gt 0; then \
$(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
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CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
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test -z "$(CTAGS_ARGS)$$unique" \
|| $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
$$unique
GTAGS:
here=`$(am__cd) $(top_builddir) && pwd` \
&& $(am__cd) $(top_srcdir) \
&& gtags -i $(GTAGS_ARGS) "$$here"
distclean-tags:
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distdir: $(DISTFILES)
@srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
list='$(DISTFILES)'; \
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sed -e "s|^$$srcdirstrip/||;t" \
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cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
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# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
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modelgen/Makefile.template 0000664 0000000 0000000 00000011460 11454012162 0016120 0 ustar 00root root 0000000 0000000 #$Id: Makefile.template,v 26.34 2007/07/03 22:49:52 al Exp $ -*- Makefile -*-
# Copyright (C) 2001 Albert Davis
# Author: Albert Davis
#
# This file is part of "Gnucap", the Gnu Circuit Analysis Package
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
# 02110-1301, USA.
#------------------------------------------------------------------------
# In most cases you can just type "make" to build it.
# Generally, you will want "make your-system".
# Look in this file for the choices.
# If yours is not here, look for a similar one and copy.
# The special configurations listed here allow you to do multiple builds
# from the same source directory, and patch some problems.
#-----------------------------------------------------------------------------
# The default is to use the makefile built by "configure"
default: nothing
-mkdir O
cat Make1 Make2 Make3 Make.depend >O/Makefile
(cd O; ${MAKE} -k)
#-----------------------------------------------------------------------------
# The most common configuration is g++
# This should work if it is properly installed
# and has the proper libraries and headers.
# It is optimized for speed. Debugging is off.
g++: nothing
-mkdir O
cat Make1 Make2.g++ Make3 Make.depend >O/Makefile
(cd O; ${MAKE} -k)
#-----------------------------------------------------------------------------
# This one makes a "debug" build ...
# Asserts and some tracing is turned on.
# It prints a trace when "untested" code is exercised.
# "Untested" means the regressions don't test it.
# It doesn't mean TOTALLY untested.
debug: nothing
-mkdir O-DEBUG
cat Make1 Make2.Debug Make3 Make.depend >O-DEBUG/Makefile
(cd O-DEBUG; ${MAKE} -k)
#-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
# MS Windows using mingw32
mingw: nothing
-mkdir MSW
cat Make1 Make2.mingw32 Make3 Make.depend >MSW/Makefile
(cd MSW; ${MAKE} -k)
#-----------------------------------------------------------------------------
tags: nothing
cat Make1 Make2.g++ Make3 >Make.aux
(${MAKE} tags -f Make.aux)
#-----------------------------------------------------------------------------
depend: nothing
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux depend
#-----------------------------------------------------------------------------
checkin: nothing
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux checkin
#-----------------------------------------------------------------------------
checkout: nothing
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux checkout
#-----------------------------------------------------------------------------
# Note that the /usr/local directory is overwritten by configure.
install: nothing
if test -d /usr/local/bin; then \
cp O/gnucap /usr/local/bin/gnucap; \
else \
mkdir -p /usr/local/bin && \
cp O/gnucap /usr/local/bin/gnucap; \
fi
#-----------------------------------------------------------------------------
uninstall: clean
-rm /usr/local/bin/gnucap
#-----------------------------------------------------------------------------
unconfig:
rm -f Makefile
#-----------------------------------------------------------------------------
date: nothing
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux date
#-----------------------------------------------------------------------------
manifest:
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux manifest
#-----------------------------------------------------------------------------
md5sums:
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux md5sums
#-----------------------------------------------------------------------------
mostlyclean:
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux mostlyclean
clean:
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux clean
distclean:
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux distclean
maintainer-clean:
cat Make1 Make2.g++ Make3 >Make.aux
${MAKE} -f Make.aux maintainer-clean
#-----------------------------------------------------------------------------
nothing:
#-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
modelgen/ap.h 0000664 0000000 0000000 00000017310 11454012162 0013417 0 ustar 00root root 0000000 0000000 /*$Id: ap.h,v 26.130 2009/11/15 21:51:59 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* stuff for the "ap" family of parsing functions
*/
//testing=script,sparse 2006.07.17
#ifndef AP_H
#define AP_H
#include "md.h"
/*--------------------------------------------------------------------------*/
char* getcmd(const char*,char*,int);
/*--------------------------------------------------------------------------*/
enum AP_MOD{
mNONE, /* nothing special */
mSCALE, /* scale it after reading */
mOFFSET, /* add an offset */
mINVERT, /* save 1 / the number */
mPOSITIVE, /* store absolute value */
mOCTAL, /* read the number in octal */
mHEX /* read the number in hex */
};
const bool ONE_OF = false;
class INTERFACE CS {
public:
enum STDIN {_STDIN};
enum INC_FILE {_INC_FILE};
enum WHOLE_FILE {_WHOLE_FILE};
enum STRING {_STRING};
private:
FILE* _file;
std::string _name;
std::string _cmd;
unsigned _cnt;
unsigned _length;
unsigned _begin_match;
unsigned _end_match;
bool _ok;
int _line_number;
public:
// construction, destruction, and re-construction
explicit CS(STDIN);
explicit CS(INC_FILE, const std::string& name);
explicit CS(WHOLE_FILE, const std::string& name);
explicit CS(STRING, const std::string& s);
explicit CS(const CS& p);
CS& operator=(const std::string& s);
CS& operator=(const CS& p);
CS& get_line(const std::string& prompt);
~CS() {if (is_file()) {fclose(_file);}}
// status - non-consuming
unsigned cursor()const {return _cnt;}
bool stuck(unsigned* last) {bool ok=*last<_cnt; *last=_cnt; return !ok;}
bool gotit(unsigned last) {return last<_cnt;}
operator bool()const {return _ok;}
// get -- non-consuming
const std::string fullstring()const {return _cmd;}
const std::string substr(unsigned i)const {return ((_cmd.length()>=i) ? _cmd.substr(i) : "");}
const std::string substr(unsigned i, unsigned n)const {return _cmd.substr(i,n);}
const std::string tail()const {return substr(_cnt);}
char peek()const {return _cmd[_cnt];}
// status - may consume whitespace only
bool ns_more()const {return peek()!='\0';}
bool more() {skipbl(); return ns_more();}
bool is_end() {return !more();}
bool is_file() {return (_file && !isatty(fileno(_file)));}
bool is_first_read()const {untested(); return (_line_number == 0);}
// control
CS& reset(unsigned c=0) {_cnt=c; _ok=true; return *this;}
// exception handling (ap_error.cc) non-consuming
CS& check(int, const std::string&);
CS& warn(int, unsigned, const std::string&);
CS& warn(int i, const std::string& s) {return warn(i,cursor(), s);}
// string matching (ap_match.cc) possibly consuming, sets _ok
CS& umatch(const std::string&);
CS& scan(const std::string&);
std::string last_match()const;
std::string trimmed_last_match(const std::string& = " ,=;")const;
// character tests - non-consuming, no _ok
bool match1(char c)const{return (peek()==c);}
bool match1(const std::string& c)const
{return ns_more() && strchr(c.c_str(),peek());}
size_t find1(const std::string& c)const
{return ((ns_more()) ? c.find_first_of(peek()) : std::string::npos);}
bool is_xdigit()const
{untested(); return (match1("0123456789abcdefABCDEF"));}
bool is_digit()const {return (match1("0123456789"));}
bool is_pfloat()const {return (match1(".0123456789"));}
bool is_float()const {return (match1("+-.0123456789"));}
bool is_argsym()const {return (match1("*?$%_&@"));}
bool is_alpha()const {return !!isalpha(toascii(peek()));}
bool is_alnum()const {return !!isalnum(toascii(peek()));}
bool is_term(const std::string& t = ",=(){};")
{char c=peek(); return (c=='\0' || isspace(c) || match1(t));}
// conversions (ap_convert.cc) always consuming
char ctoc();
void ctostr(char*,int,const std::string&);
std::string ctos(const std::string& term=",=(){};",
const std::string& b="\"'{",
const std::string& e="\"'}",
const std::string& trap="");
std::string get_to(const std::string& term);
// conversions (ap_convert.cc) consumes if successful, sets _ok
double ctof();
bool ctob();
int ctoi();
unsigned ctou();
int ctoo();
int ctox();
double ctopf() {return std::abs(ctof());}
CS& operator>>(bool& x) {x=ctob();return *this;}
CS& operator>>(char& x) {untested(); x=ctoc();return *this;}
CS& operator>>(int& x) {x=ctoi();return *this;}
CS& operator>>(unsigned& x) {x=ctou();return *this;}
CS& operator>>(double& x) {x=ctof();return *this;}
CS& operator>>(std::string& x) {x=ctos();return *this;}
// skip (ap_skip.cc) possibly consuming, sets _ok
CS& skip(int c=1)
{_cnt=static_cast(static_cast(_cnt)+c); _ok=_cnt<=_length; return *this;}
CS& skipbl();
CS& skip1b(char);
CS& skip1(char);
CS& skip1b(const std::string&);
CS& skip1(const std::string&);
CS& skiparg();
CS& skipto1(const std::string&);
CS& skipto1(char);
CS& skipcom() {return skip1b(",");}
CS& operator>>(const char& x) {return skip1b(x);}
CS& operator>>(const char* x) {return umatch(x);}
};
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
// these are non-member to provide a consistent interface,
// like the templates to follow
INTERFACE bool Get(CS& cmd, const std::string&, bool*);
INTERFACE bool Get(CS& cmd, const std::string&, int*, AP_MOD=mNONE, int=0);
INTERFACE bool Get(CS& cmd, const std::string&, double*, AP_MOD, double=0.);
/*--------------------------------------------------------------------------*/
template
bool Get(CS& cmd, const std::string& key, T* val)
{
if (cmd.umatch(key + " {=}")) {
cmd >> *val;
return true;
}else{
return false;
}
}
/*--------------------------------------------------------------------------*/
template
inline bool scan_get(CS& cmd, const std::string& key, T* val)
{
if (cmd.scan(key)) {
cmd >> '=' >> *val;
return true;
}else{
return false;
}
}
/*--------------------------------------------------------------------------*/
template
inline bool Set(CS& cmd, const std::string& key, T* val, T newval)
{
if (cmd.umatch(key + ' ')) {
*val = newval;
return true;
}else{
return false;
}
}
/*--------------------------------------------------------------------------*/
template
inline CS& operator>>(CS& cmd, T& val)
{
val.parse(cmd);
return cmd;
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
#endif
modelgen/ap_construct.cc 0000664 0000000 0000000 00000015735 11454012162 0015672 0 ustar 00root root 0000000 0000000 /*$Id: ap_construct.cc,v 26.130 2009/11/15 21:51:59 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* construction, copy, etc.
*/
//testing=script,sparse 2006.07.17
#include "u_opt.h"
#include "ap.h"
#if defined(HAVE_LIBREADLINE)
#include
#include
#endif
/*--------------------------------------------------------------------------*/
static std::string getlines(FILE*);
OMSTREAM mout; // > file bitmap //BUG//encapsulation
OMSTREAM mlog; // log file bitmap
/*--------------------------------------------------------------------------*/
CS::CS(CS::STDIN)
:_file(stdin),
_name(),
_cmd(),
_cnt(0),
_length(0),
_begin_match(0),
_end_match(0),
_ok(true),
_line_number(0)
{
}
/*--------------------------------------------------------------------------*/
CS::CS(CS::INC_FILE, const std::string& name)
:_file(fopen(name.c_str(), "r")),
_name(name),
_cmd(),
_cnt(0),
_length(0),
_begin_match(0),
_end_match(0),
_ok(true),
_line_number(0)
{
if (!_file) {itested();
throw Exception_File_Open(name + ':' + strerror(errno));
}else{
}
}
/*--------------------------------------------------------------------------*/
CS::CS(CS::WHOLE_FILE, const std::string& name)
:_file(NULL),
_name(name),
_cmd(),
_cnt(0),
_length(0),
_begin_match(0),
_end_match(0),
_ok(true),
_line_number(0)
{
int f = open(name.c_str(), O_RDONLY);
if (f == EOF) {itested();
throw Exception_File_Open(name + ':' + strerror(errno));
}else{
}
_length = static_cast(lseek(f, off_t(0), SEEK_END));
lseek(f, off_t(0), SEEK_SET);
char* cmd = new char[_length+2];
read(f, cmd, _length);
cmd[_length++] = '\0';
_cmd = cmd;
close(f);
}
/*--------------------------------------------------------------------------*/
CS::CS(CS::STRING, const std::string& s)
:_file(NULL),
_name(),
_cmd(s),
_cnt(0),
_length(static_cast(s.length())),
_begin_match(0),
_end_match(0),
_ok(true),
_line_number(0)
{
}
/*--------------------------------------------------------------------------*/
#if 0
CS::CS(const CS& p)
:_file(NULL),
_name(p._name),
_cmd(p._cmd),
_cnt(p._cnt),
_length(p._length),
_begin_match(0),
_end_match(0),
_ms(p._ms),
_ok(p._ok),
_line_number(0)
{untested();
}
#endif
/*--------------------------------------------------------------------------*/
CS& CS::operator=(const std::string& s)
{untested();
assert(!_file);
_cmd = s;
_cnt = 0;
_ok = true;
_length = static_cast(s.length());
return *this;
}
/*--------------------------------------------------------------------------*/
#if 0
CS& CS::operator=(const CS& p)
{untested();
assert(&p != this);
_name = p._name;
_file = p._file;
_cmd = p._cmd;
_cnt = p._cnt;
_ok = p._ok;
_length = p._length;
return *this;
}
#endif
/*--------------------------------------------------------------------------*/
CS& CS::get_line(const std::string& prompt)
{
++_line_number;
if (is_file()) {
_cmd = getlines(_file);
_cnt = 0;
_length = static_cast(_cmd.length());
_ok = true;
}else{itested();
assert(_file == stdin);
char cmdbuf[BUFLEN];
getcmd(prompt.c_str(), cmdbuf, BUFLEN);
_cmd = cmdbuf;
_cnt = 0;
_length = static_cast(_cmd.length());
_ok = true;
}
if (OPT::listing) {
IO::mstdout << "\"" << fullstring() << "\"\n";
}else{
}
return *this;
}
/*--------------------------------------------------------------------------*/
/* getcmd: get a command.
* if "fin" is stdin, display a prompt first.
* Also, actually do logging, echo, etc.
*/
char *getcmd(const char *prompt, char *buffer, int buflen)
{
assert(prompt);
assert(buffer);
if (isatty(fileno(stdin))) {
// stdin is keyboard
#if defined(HAVE_LIBREADLINE)
if (OPT::edit) {
char* line_read = readline(prompt);
if (!line_read) {itested();
throw Exception_End_Of_Input("EOF on stdin");
}else{
}
// readline gets a new buffer every time, so copy it to where we want it
char* end_of_line = (char*)memccpy(buffer, line_read, 0, static_cast(buflen-1));
if (!end_of_line) {
buffer[buflen-1] = '\0';
}else{
*end_of_line = '\0';
}
free(line_read);
if (*buffer) {
add_history(buffer);
}else{
}
}else
#endif
{
IO::mstdout << prompt; /* prompt & flush buffer */
if (!fgets(buffer, buflen, stdin)) {untested(); /* read line */
throw Exception_End_Of_Input("EOF on stdin");
}else{
}
}
(IO::mstdout - mout) << '\r'; /* reset col counter */
trim(buffer);
(mlog + mout) << buffer << '\n';
return buffer;
}else{
// stdin is file
if (!fgets(buffer, buflen, stdin)) {itested(); /* read line */
throw Exception_End_Of_Input("EOF on stdin");
}else{
}
trim(buffer);
(mlog + mout) << buffer << '\n';
return buffer;
}
}
/*--------------------------------------------------------------------------*/
static std::string getlines(FILE *fileptr)
{
assert(fileptr);
const int buffer_size = BIGBUFLEN;
std::string s;
bool need_to_get_more = true; // get another line (extend)
while (need_to_get_more) {
char buffer[buffer_size+1];
char* got_something = fgets(buffer, buffer_size, fileptr);
if (!got_something) { // probably end of file
need_to_get_more = false;
if (s == "") {
throw Exception_End_Of_Input("");
}else{untested();
}
}else{
trim(buffer);
size_t count = strlen(buffer);
if (buffer[count-1] == '\\') {itested();
buffer[count-1] = '\0';
}else{
// look ahead at next line
//int c = fgetc(fileptr);
int c;
while (isspace(c = fgetc(fileptr))) {
// skip
}
if (c == '+') {
need_to_get_more = true;
}else if (c == '\n') {unreachable();
need_to_get_more = true;
ungetc(c,fileptr);
}else{
need_to_get_more = false;
ungetc(c,fileptr);
}
}
s += buffer;
s += ' ';
}
}
return s;
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
modelgen/ap_convert.cc 0000664 0000000 0000000 00000021773 11454012162 0015325 0 ustar 00root root 0000000 0000000 /*$Id: ap_convert.cc,v 26.125 2009/10/15 20:58:21 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
//testing=script 2006.07.17
#include "u_opt.h"
#include "ap.h"
/*--------------------------------------------------------------------------*/
// char CS::ctoc();
// void CS::ctostr(char* d, int l, const string& t);
// string CS::ctos(const string& term);
// int CS::ctoi();
// unsigned CS::ctou();
// int CS::ctoo();
// int CS::ctox();
// double CS::ctof();
/*--------------------------------------------------------------------------*/
/* ctoc: character input to character
*/
char CS::ctoc()
{
char c=_cmd[_cnt];
if(_cnt<=_length) {
++_cnt;
}else{untested();
}
return c;
}
/*--------------------------------------------------------------------------*/
/* ctostr: character input to string
* scan (and eat) an input string (cmd) using index (cnt).
* result in (des) (null terminated).
* max length (actual char count) is (len).
* (des) must be at least (len)+1 characters long.
* (cmd) unchanged. (*cnt) updated to point to next argument.
* skips leading whitespace. skips trailing whitespace and comma
* skips parts of input word too big for destination
*/
void CS::ctostr(char* des, int len, const std::string& term)
{
skipbl();
int ii;
for (ii = 0; ii < len && !is_term(term); ++ii) {
des[ii] = ctoc();
}
des[ii] = '\0';
while (!is_term(term)) {untested();
skip();
}
skipcom();
}
/*--------------------------------------------------------------------------*/
std::string CS::ctos(const std::string& term,
const std::string& begin_quote,
const std::string& end_quote,
const std::string& trap)
{
assert(begin_quote.length() == end_quote.length());
skipbl();
unsigned begin_string = cursor();
unsigned end_string = cursor();
std::string s;
std::string::size_type which_quote = find1(begin_quote);
if (which_quote != std::string::npos) {
int quotes = 1;
skip(); // the quote
begin_string = cursor();
char the_begin_quote = begin_quote[which_quote];
char the_end_quote = end_quote[which_quote];
for (;;) {
if (!ns_more()) {itested();
end_string = cursor();
warn(bDANGER, std::string("need ") + the_end_quote);
break;
}else if (skip1(the_end_quote)) {
if (--quotes <= 0) {
end_string = cursor() - 1;
break;
}else{
}
}else if (skip1(the_begin_quote)) {
++quotes;
skip();
}else if (skip1('\\')) {
end_string = cursor() - 1;
s += _cmd.substr(begin_string, end_string-begin_string);
begin_string = cursor();
skip1(the_end_quote);
}else{
skip();
}
}
s += _cmd.substr(begin_string, end_string-begin_string);
}else{
while(ns_more() && !is_term(term)) {
skip();
}
if (match1(trap)) {untested();
warn(bDANGER, "ap_convert trap-exit");
}else{
}
end_string = cursor();
s = _cmd.substr(begin_string, end_string-begin_string);
}
skipcom();
_ok = end_string > begin_string;
return s;
}
/*--------------------------------------------------------------------------*/
std::string CS::get_to(const std::string& term)
{
std::string des;
while(ns_more() && !match1(term)) {
des += ctoc();
}
return des;
}
/*--------------------------------------------------------------------------*/
/* ctob: character input to bool
* no match makes it true;
* Mismatch belongs to next token
*/
bool CS::ctob()
{
skipbl();
unsigned here = cursor();
bool val = true;
ONE_OF
|| Set(*this, "1", &val, true)
|| Set(*this, "0", &val, false)
|| Set(*this, "t{rue}", &val, true)
|| Set(*this, "f{alse}", &val, false)
|| Set(*this, "y{es}", &val, true)
|| Set(*this, "n{o}", &val, false)
|| Set(*this, "#t{rue}", &val, true)
|| Set(*this, "#f{alse}",&val, false)
;
skipcom();
_ok = cursor() > here;
return val;
}
/*--------------------------------------------------------------------------*/
/* ctoi: character input to integer
* Returns signed integer, or 0 if the string is not a number.
* Input must be integer: no multipliers, no decimal point.
* Dot or letter belongs to the next token.
*/
int CS::ctoi()
{
int val = 0;
int sign = 1;
skipbl();
unsigned here = cursor();
if (skip1("-")) {
sign = -1;
}else{
skip1("+");
}
while (is_digit()) {
val = 10 * val + (ctoc()-'0');
}
skipcom();
_ok = cursor() > here;
return val * sign;
}
/*--------------------------------------------------------------------------*/
/* ctou: character input to unsigned integer
* Returns unsigned integer, or 0 if the string is not a number.
* Input must be integer: no multipliers, no decimal point.
* Dot or letter belongs to the next token.
*/
unsigned CS::ctou()
{
unsigned val = 0;
skipbl();
unsigned here = cursor();
while (is_digit()) {
val = 10 * val + static_cast(ctoc()-'0');
}
skipcom();
_ok = cursor() > here;
return val;
}
/*--------------------------------------------------------------------------*/
/* ctoo: character octal input to integer
* Returns integer, or 0 if the string is not a number.
* Input must be integer: no multipliers, no decimal point.
* Dot or letter belongs to the next token.
* There is no check against '8' and '9'.
*/
int CS::ctoo()
{
int val = 0;
skipbl();
unsigned here = cursor();
while (is_digit()) {
val = 8 * val + (ctoc()-'0');
}
skipcom();
_ok = cursor() > here;
return val;
}
/*--------------------------------------------------------------------------*/
/* ctox: character hex input to unsigned integer
* Returns integer, or 0 if the string is not a number.
* Input must be hex integer: no multipliers, no decimal point.
* Dot or letter belongs to the next token.
*/
int CS::ctox()
{untested();
int val = 0;
skipbl();
unsigned here = cursor();
while (is_xdigit()) {untested();
if (is_digit()) {untested();
val = 16 * val + (ctoc()-'0');
}else{untested();
val = 16 * val + (tolower(ctoc())-'a'+10);
}
}
skipcom();
_ok = cursor() > here;
return val;
}
/*--------------------------------------------------------------------------*/
/* ctof: floating point input
* return double number if got, else 0
* supports letter multipliers (spice style)
* skips trailing letters (10uhenries == 10u)
* skips trailing spaces and one comma
* pointer points to char following comma
* or first non-space following number just got
* or first non-space (if non-number)
*/
double CS::ctof()
{
double val = 0.0;
double power = 1.0;
int sign = 1;
skipbl();
if (!is_float()) {
skipcom();
_ok = false;
return 0.;
}else{
}
if (skip1("-")) { // sign
sign = -1;
}else{
skip1("+");
}
while (is_digit()) { // up to dec pt
val = 10.0 * val + (ctoc()-'0');
}
skip1("."); // dec pt
while (is_digit()) { // after dec pt
val = 10.0 * val + (ctoc()-'0');
power *= .1;
}
if (skip1("eE")) { // exponent: E form
int expo = 0;
int es = 1;
if (skip1("-")) {
es = -1;
}else{
skip1("+");
}
while (is_digit())
expo = 10 * expo + (ctoc()-'0');
expo *= es;
power *= pow(10., expo);
}else if ((OPT::units == uSPICE) && skip1("mM")) { // M is special
if (skip1("eE")) { // meg
power *= 1e6;
}else if (skip1("iI")) { // mil
power *= 25.4e-6;
}else{ // plain m (milli)
power *= 1e-3;
}
}else if (skip1("M")) {
assert(OPT::units == uSI);
power *= 1e6;
}else if (skip1("m")) {
assert(OPT::units == uSI);
power *= 1e-3;
}else if (skip1("uU")) { // other letters
power *= 1e-6;
}else if (skip1("nN")) {
power *= 1e-9;
}else if (skip1("p")) {
power *= 1e-12;
}else if (skip1("P")) {
power *= ((OPT::units == uSI) ? (1e15) : 1e-12);
}else if (skip1("fF")) {
power *= 1e-15;
}else if (skip1("kK")) {
power *= 1e3;
}else if (skip1("gG")) {
power *= 1e9;
}else if (skip1("tT")) {
power *= 1e12;
}else if (skip1("%")) {untested();
power *= 1e-2;
}else{
}
while (is_alpha()) { // skip letters
skip();
}
skipcom();
_ok = true;
return (sign*val*power);
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
modelgen/ap_get.cc 0000664 0000000 0000000 00000006027 11454012162 0014417 0 ustar 00root root 0000000 0000000 /*$Id: ap_get.cc,v 26.85 2008/06/19 05:01:15 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* get value for matching keyword
*/
//testing=script 2006.07.17
#include "ap.h"
/*--------------------------------------------------------------------------*/
/* special version of "get" for "bool"
* so "nofoo" works as an equivalent to foo=false
*/
bool Get(CS& cmd, const std::string& key, bool* val)
{
if (cmd.umatch(key + ' ')) {
if (cmd.skip1b('=')) {itested();
cmd >> *val;
}else{
*val = true;
}
return true;
}else if (cmd.umatch("no" + key)) {
*val = false;
return true;
}else{
return false;
}
}
/*--------------------------------------------------------------------------*/
bool Get(CS& cmd, const std::string& key, int* val, AP_MOD mod, int scale)
{
if (cmd.umatch(key + " {=}")) {
switch(mod) {
case mNONE: *val = int(cmd.ctof()); break;
case mSCALE: untested(); *val = int(cmd.ctof())*scale; break;
case mOFFSET: untested(); *val = int(cmd.ctof())+scale; break;
case mINVERT: untested(); *val = 1 / int(cmd.ctof()); break;
case mPOSITIVE: untested(); *val = std::abs(int(cmd.ctof())); break;
case mOCTAL: *val = cmd.ctoo(); break;
case mHEX: untested(); *val = cmd.ctox(); break;
}
return true;
}else{
return false;
}
}
/*--------------------------------------------------------------------------*/
bool Get(CS& cmd, const std::string& key, double* val, AP_MOD mod, double scale)
{
if (cmd.umatch(key + " {=}")) {
switch(mod) {
case mNONE: untested(); *val = cmd.ctof(); break;
case mSCALE: untested(); *val = cmd.ctof()*scale; break;
case mOFFSET: untested(); *val = cmd.ctof()+scale; break;
case mINVERT: untested(); *val = 1 / cmd.ctof(); break;
case mPOSITIVE: *val = std::abs(cmd.ctof()); break;
case mOCTAL: untested(); *val = cmd.ctoo(); break;
case mHEX: untested(); *val = cmd.ctox(); break;
}
return true;
}else{
return false;
}
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
modelgen/ap_match.cc 0000664 0000000 0000000 00000006635 11454012162 0014741 0 ustar 00root root 0000000 0000000 /*$Id: ap_match.cc,v 26.131 2009/11/20 08:22:10 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* string compare
*/
//testing=script 2006.07.17
#include "u_opt.h"
#include "ap.h"
/*--------------------------------------------------------------------------*/
/* umatch = universal match
*/
CS& CS::umatch(const std::string& s)
{
unsigned start = cursor();
skipbl();
unsigned begin_match = cursor();
const char* str2 = s.c_str();
bool optional = 0;
for (;;) {
if ((!*str2) || (*str2 == '|')) {
_ok = true;
break;
}else if ((str2[0] == '\\') && (peek() == str2[1])) {
skip();
str2 += 2;
}else if ((!optional) && (*str2 == '{')) {
++str2;
optional = true;
}else if ((optional) && (*str2 == '}')) {
++str2;
optional = false;
}else if ((*str2 == ' ') && is_term()) {
// blank in ref string matches anything that delimits tokens
skipbl();
++str2;
}else if (peek() == *str2) {
skip();
++str2;
}else if ((OPT::case_insensitive) && (tolower(peek()) == tolower(*str2))) {
skip();
++str2;
}else if (optional) {
while (*str2 != '}') {
++str2;
}
}else{
// mismatch
const char* bar = strchr(str2, '|');
if (bar && (bar[-1] != '\\')) {
str2 = bar+1;
reset(start);
}else{
_ok = false;
break;
}
}
}
if (_ok) {
_begin_match = begin_match;
_end_match = cursor();
skipcom();
_ok = true;
}else{
reset(start);
_ok = false;
}
return *this;
}
/*--------------------------------------------------------------------------*/
CS& CS::scan(const std::string& s)
{
unsigned start = cursor();
for (;;) {
if (umatch(s)) { // found it
_ok = true;
break;
}else if (!more()) { // ran out
reset(start);
_ok = false;
break;
}else{ // skip and try again
skiparg();
}
}
return *this;
}
/*--------------------------------------------------------------------------*/
std::string CS::last_match()const
{
return _cmd.substr(_begin_match, _end_match-_begin_match);
}
/*--------------------------------------------------------------------------*/
std::string CS::trimmed_last_match(const std::string& suf)const
{
unsigned real_end = _end_match;
while (strchr(suf.c_str(), _cmd[real_end-1])) {
--real_end;
}
return _cmd.substr(_begin_match, real_end-_begin_match);
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
modelgen/ap_skip.cc 0000664 0000000 0000000 00000007556 11454012162 0014616 0 ustar 00root root 0000000 0000000 /*$Id: ap_skip.cc,v 26.81 2008/05/27 05:34:00 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* collection of functions to skip input
* all except skip1 skip leading whitespace, skip whatever is being skipped,
* then skip trailing whitespace.
*/
//testing=script 2006.07.17
#include "ap.h"
/*--------------------------------------------------------------------------*/
/* skipbl: skip whitespace. (any non-graphic character is ws)
* =,(,) are also ws
* update string pointer
* pointer points to first non-space
* does NOT update _ok flag
*/
CS& CS::skipbl()
{
while (peek() && (!isgraph(peek()))) {
skip();
}
return *this;
}
/*--------------------------------------------------------------------------*/
/* skip1b: skip 1 matching character and surrounding blanks
* _ok = did it
*/
CS& CS::skip1b(char t)
{
skipbl();
skip1(t);
skipbl();
return *this;
}
/*--------------------------------------------------------------------------*/
/* skip1: skip 1 character matching any in t
* _ok = did it
*/
CS& CS::skip1(char t)
{
if (match1(t)) {
skip();
assert(_ok);
}else{
_ok = false;
}
return *this;
}
/*--------------------------------------------------------------------------*/
/* skip1b: skip 1 matching character and surrounding blanks
* _ok = did it
*/
CS& CS::skip1b(const std::string& t)
{
skipbl();
skip1(t);
skipbl();
return *this;
}
/*--------------------------------------------------------------------------*/
/* skip1: skip 1 character matching any in t
* _ok = did it
*/
CS& CS::skip1(const std::string& t)
{
if (match1(t)) {
skip();
assert(_ok);
}else{
_ok = false;
}
return *this;
}
/*--------------------------------------------------------------------------*/
/* skiparg: skip an argument (maybe just a comma)
* _ok = skipped something
*/
CS& CS::skiparg()
{
unsigned here = cursor();
if (!skipcom()) {
if (peek()) {
skip();
}else{
}
while (is_alpha() || is_float() || is_argsym()) {
skip();
}
skipcom();
}else{untested();
// empty field, just a comma
}
_ok = cursor() > here;
return *this;
}
/*--------------------------------------------------------------------------*/
/* skipto: skip to a character (one of ...)
* _ok = skipped something
*/
CS& CS::skipto1(const std::string& t)
{untested();
unsigned here = cursor();
while (ns_more() && !match1(t)) {untested();
skip();
}
_ok = ns_more();
if (!_ok) {untested();
reset(here);
}else{untested();
}
return *this;
}
/*--------------------------------------------------------------------------*/
/* skipto: skip to a character (explicit)
* _ok = skipped something
*/
CS& CS::skipto1(char c)
{
unsigned here = cursor();
while (ns_more() && !match1(c)) {
skip();
}
_ok = ns_more();
if (!_ok) {untested();
reset(here);
}else{
}
return *this;
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
modelgen/configure.old 0000775 0000000 0000000 00000002611 11454012162 0015330 0 ustar 00root root 0000000 0000000 #!/bin/sh
mkdir O
echo "CCFLAGS = \\" >Make.ccflags
echo "LIBS = \\" >Make.libs
echo "-DUNIX -O2 -DNDEBUG -I.. -I. -W" >>Make.ccflags
echo "" >>Make.libs
echo "" >>Make.libs
cat <Make.sys
#------------------------------------------------------------------------
VPATH = .:..
CCC = g++
LDFLAGS =
.SUFFIXES : .o .cc
.cc.o:; \$(CCC) \$(CCFLAGS) -c \$<
#------------------------------------------------------------------------
\$(TARGET): \$(OBJS)
rm -f \$@
\$(CCC) \$(CCFLAGS) \$(OBJS) -o \$@ \$(LIBS) \$(LDFLAGS)
#------------------------------------------------------------------------
CAT_EOF
cat Make.ccflags Make.libs Make.sys >Make2
cat Make1 Make2 Make3 Make.depend >O/Makefile
#------------- Stuff added to enable --prefix --------------
if test "x$1" != "x"; then
# echo Found input parameter -- $1
# Now see if the parameter is --prefix=
if test "x${1#--prefix=}" != "x$1"; then
# echo "Found --prefix in input args. Setting prefix directory."
prefix=${1#--prefix=}
else
# echo "Found unrecognized parameter in input args."
# Just use the default prefix dir.
prefix=/usr/local
fi
else
# echo "No input parameter found."
# Just use the default prefix dir
prefix=/usr/local
fi
sed -e "s#/usr/local#$prefix#" Makefile.template > Makefile
#----------------------------------------------------------------
exit 0
modelgen/declare.h 0000664 0000000 0000000 00000000063 11454012162 0014413 0 ustar 00root root 0000000 0000000 /* dummy file, to cover some code in transition */
modelgen/io.cc 0000664 0000000 0000000 00000002436 11454012162 0013567 0 ustar 00root root 0000000 0000000 /*$Id: io.cc,v 26.81 2008/05/27 05:34:00 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* shared data for all io functions, initialization, default values
*/
//testing=trivial 2006.07.17
#include "io_.h"
OMSTREAM IO::mstdout(stdout);
OMSTREAM IO::error(stdout);
OMSTREAM IO::plotout;
bool IO::plotset(false);
int IO::formaat(0);
bool IO::incipher(false);
FILE* IO::stream[MAXHANDLE+1] = {0, stdout, stderr};
modelgen/io_.h 0000664 0000000 0000000 00000011271 11454012162 0013565 0 ustar 00root root 0000000 0000000 /*$Id: io_.h,v 26.81 2008/05/27 05:34:00 al Exp $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* shared data for all io functions
* other io related stuff, like files and formatting
*/
//testing=script 2006.07.17
#ifndef IO_H
#define IO_H
#include "l_lib.h"
/*--------------------------------------------------------------------------*/
class CS;
const int MAXHANDLE = CHAR_BIT*sizeof(int)-1;
/*--------------------------------------------------------------------------*/
class INTERFACE OMSTREAM {
private:
int _mask;
int _fltdig; /* max precision for float/double numbers */
int _fltwid; /* fixed(min)width for float/double numbers */
int _format; /* how to format io. Basic option. */
static unsigned _cpos[MAXHANDLE+1];/* character counter */
bool _cipher; /* flag: encrypt output file */
bool _pack; /* flag: convert whitespace to tabs on out */
OMSTREAM(int m)
:_mask(m),_fltdig(7),_fltwid(0),_format(0),_cipher(false),_pack(false) {}
public:
explicit OMSTREAM(FILE* f = 0)
:_mask(0),_fltdig(7),_fltwid(0),_format(0),_cipher(false), _pack(false)
{_mask = (f) ? 1<(p));}
OMSTREAM& form(const char*,...);
OMSTREAM& operator<<(char c);
OMSTREAM& operator<<(const char* s);
OMSTREAM& operator<<(double x)
{return (*this)<