pax_global_header00006660000000000000000000000064143553661260014525gustar00rootroot0000000000000052 comment=cfc2f3451486f6f05cc5e05ff6b5308269980fe3 hackrf-0.0~git20230104.cfc2f34/000077500000000000000000000000001435536612600154715ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/.gitignore000066400000000000000000000007311435536612600174620ustar00rootroot00000000000000*.d *.o *.bin *.hex *.list *.srec *.a *.elf lib/*.ld *.swp \#* .\#* *~ *.map *.log html/ latex/ *.pdf *.tag .DS_Store # These are generated include/libopencm3/**/nvic.h include/libopencm3/**/**/nvic.h lib/**/vector_nvic.c lib/**/**/vector_nvic.c include/libopencmsis/efm32/ include/libopencmsis/lm3s/ include/libopencmsis/lpc13xx/ include/libopencmsis/lpc17xx/ include/libopencmsis/lpc43xx/ include/libopencmsis/stm32/ include/libopencmsis/sam3x/ include/libopencmsis/sam/ hackrf-0.0~git20230104.cfc2f34/COPYING.GPL3000066400000000000000000001043741435536612600172410ustar00rootroot00000000000000 GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc. 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The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such. 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License "or any later version" applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation. If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program. Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version. 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . Also add information on how to contact you by electronic and paper mail. If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode: Copyright (C) This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an "about box". You should also get your employer (if you work as a programmer) or school, if any, to sign a "copyright disclaimer" for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see . The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read . hackrf-0.0~git20230104.cfc2f34/COPYING.LGPL3000066400000000000000000000167431435536612600173570ustar00rootroot00000000000000 GNU LESSER GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc. Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. This version of the GNU Lesser General Public License incorporates the terms and conditions of version 3 of the GNU General Public License, supplemented by the additional permissions listed below. 0. Additional Definitions. As used herein, "this License" refers to version 3 of the GNU Lesser General Public License, and the "GNU GPL" refers to version 3 of the GNU General Public License. "The Library" refers to a covered work governed by this License, other than an Application or a Combined Work as defined below. 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If you modify a copy of the Library, and, in your modifications, a facility refers to a function or data to be supplied by an Application that uses the facility (other than as an argument passed when the facility is invoked), then you may convey a copy of the modified version: a) under this License, provided that you make a good faith effort to ensure that, in the event an Application does not supply the function or data, the facility still operates, and performs whatever part of its purpose remains meaningful, or b) under the GNU GPL, with none of the additional permissions of this License applicable to that copy. 3. Object Code Incorporating Material from Library Header Files. The object code form of an Application may incorporate material from a header file that is part of the Library. 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You may convey a Combined Work under terms of your choice that, taken together, effectively do not restrict modification of the portions of the Library contained in the Combined Work and reverse engineering for debugging such modifications, if you also do each of the following: a) Give prominent notice with each copy of the Combined Work that the Library is used in it and that the Library and its use are covered by this License. b) Accompany the Combined Work with a copy of the GNU GPL and this license document. c) For a Combined Work that displays copyright notices during execution, include the copyright notice for the Library among these notices, as well as a reference directing the user to the copies of the GNU GPL and this license document. d) Do one of the following: 0) Convey the Minimal Corresponding Source under the terms of this License, and the Corresponding Application Code in a form suitable for, and under terms that permit, the user to recombine or relink the Application with a modified version of the Linked Version to produce a modified Combined Work, in the manner specified by section 6 of the GNU GPL for conveying Corresponding Source. 1) Use a suitable shared library mechanism for linking with the Library. A suitable mechanism is one that (a) uses at run time a copy of the Library already present on the user's computer system, and (b) will operate properly with a modified version of the Library that is interface-compatible with the Linked Version. e) Provide Installation Information, but only if you would otherwise be required to provide such information under section 6 of the GNU GPL, and only to the extent that such information is necessary to install and execute a modified version of the Combined Work produced by recombining or relinking the Application with a modified version of the Linked Version. (If you use option 4d0, the Installation Information must accompany the Minimal Corresponding Source and Corresponding Application Code. If you use option 4d1, you must provide the Installation Information in the manner specified by section 6 of the GNU GPL for conveying Corresponding Source.) 5. Combined Libraries. You may place library facilities that are a work based on the Library side by side in a single library together with other library facilities that are not Applications and are not covered by this License, and convey such a combined library under terms of your choice, if you do both of the following: a) Accompany the combined library with a copy of the same work based on the Library, uncombined with any other library facilities, conveyed under the terms of this License. b) Give prominent notice with the combined library that part of it is a work based on the Library, and explaining where to find the accompanying uncombined form of the same work. 6. Revised Versions of the GNU Lesser General Public License. The Free Software Foundation may publish revised and/or new versions of the GNU Lesser General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Library as you received it specifies that a certain numbered version of the GNU Lesser General Public License "or any later version" applies to it, you have the option of following the terms and conditions either of that published version or of any later version published by the Free Software Foundation. If the Library as you received it does not specify a version number of the GNU Lesser General Public License, you may choose any version of the GNU Lesser General Public License ever published by the Free Software Foundation. If the Library as you received it specifies that a proxy can decide whether future versions of the GNU Lesser General Public License shall apply, that proxy's public statement of acceptance of any version is permanent authorization for you to choose that version for the Library. hackrf-0.0~git20230104.cfc2f34/HACKING000066400000000000000000000073371435536612600164720ustar00rootroot00000000000000------------------------------------------------------------------------------ HACKING ------------------------------------------------------------------------------ Coding style ------------ The whole library is programmed using the Linux kernel coding style, see http://lxr.linux.no/linux/Documentation/CodingStyle for details. Please use the same style for any code contributions, thanks! Amendments to the Linux kernel coding style ------------------------------------------- 1) We use the stdint types. The linux kernel accepts the abbreviated types (u8, s8, u16 and so on) for legacy reasons. We should in general not introduce things like types ourselves as long as they are not necessary to make our job possible of refining the hardware and make it easier to be used. stdint is a standard and it is not in the scope of our project to introduce a new type standard. 2) Based on the same logic as in (1) we do not use __packed and __aligned definitions, it is not our job to add compiler extensions. If we need to deal with compiler incompatibility we will do that the same way we are dealing with the depricated attribute by introducing a normal macro that is not in the compiler reserved keyword space. 3) We accept to write an empty body busy waiting while loop like this: while (1); there is no need to put the colon on the next line as per linux kernel style. 4) We always add brackets around bodies of if, while and for statements, even if the body contains only one expression. It is dangerous to not have them as it easily happens that one adds a second expression and is hunting for hours why the code is not working just because of a missing bracket pair. Development guidelines ---------------------- - Every new file added must have the usual license header, see the existing files for examples. - In general, please try to keep the register and bit naming as close as possible to the official vendor datasheets. Among other reasons, this makes it easier for users to find what they're looking for in the datasheets, programming manuals, and application notes. - All register definitions should follow the following naming conventions: - The #define names should be all-caps, parts are separated by an underscore. - The name should be of the form SUBSYSTEM_REGISTER_BIT, e.g. ADC_CR2_DMA, where ADC is the subsystem name, CR2 is the register NAME, and DMA is the name of the bit in the register that is defined. - All subsystem-specific function names should be prefixed with the subsystem name. For example, gpio_set_mode() or rcc_osc_on(). - Please consistently use the short form types from , e.g. u8, u16, u32, and so on. - Variables that are used to store register values read from registers or to be stored in a register should be named reg8, reg16, reg32 etc. - In the examples directory, the following structure should be used: - One (or more) subdirectories for the type of microcontroller, e.g. lm3s, lpc13xx, stm32/f1, stm32/f2, stm32/f4. - One subdirectory in there for each eval board or piece of hardware, e.g. stm32-h103, lisa-m, stm32vl-discovery, stm32f4-discovery, etc. - One subdirectory in there for each example, e.g. miniblink, button, usart, usb_dfu, etc. Tips and tricks --------------- SublimeText users: - The project contains a sublime project description file with some basic settings provided to make hacking on libopencm3 easier. - Recommended SublimeText plugins when hacking on libopencm3: - TrailingSpaces: Show and trim trailing line spaces. - SublimeLinter: Run checkpatch.pl in the background while you write your code and indicate possible coding style issues on the fly. hackrf-0.0~git20230104.cfc2f34/HACKING_COMMON_DOC000066400000000000000000000060621435536612600202210ustar00rootroot00000000000000Files for each peripheral (examples given for STM32 GPIO) --------------------------------------------------------- In include/libopencm3/stm32. A "dispatch" header to point to the subfamily header (gpio.h) In include/libopencm3/stm32/f* A file with defines that are specific to the subfamily, and an include of needed common header files (gpio.h). In include/libopencm3/stm32/common A file with defines common to all subfamilies. Includes the cm3 common header (gpio_common_all.h). In include/libopencm3/stm32/common May be one other file with defines common to a subgroup of devices. This includes the file common to all (gpio_common_f24.h). In lib/stm32/f* A file with functions specific to the subfamily. Includes the "dispatch" header and any common headers needed (gpio.c). In lib/stm32/common Has functions common to all subfamilies. Includes the "dispatch" header (gpio_common_all.c). In lib/stm32/common May be one other file with functions common to a group of subfamilies. Includes the "dispatch" header and the file common to all (gpio_common_f24.h). Makefiles in lib/stm32/f? have the common object files added and the common directory added to VPATH. NOTE: The common source files MUST have the "dispatch" header so that compilation will use the specific defines for the subfamily being compiled. These can differ between subfamilies. NOTE: The common source files must have a line of the form #ifdef LIBOPENCM3_xxx_H where xxx is the associated peripheral name. This prevents the common files from being included accidentally into a user's application. This however causes doxygen to skip processing of the remainder of the file. Thus a @cond ... @endcond directive must be placed around the statement to prevent doxygen from processing it. This works only for doxygen 1.8.4 or later. At the present time most distros have an earlier buggy version. Documentation ------------- In include/libopencm3/stm32/f* A file doc-stm32f*.h contains a definition of the particular family grouping. This grouping will appear in the main index of the resulting document with all documentation under it. All header files for a peripheral (common or otherwise) will subgroup under a name which is the same in all families (such as gpio_defines). The peripheral header file in include/libopencm3/stm32/f* will then include this group as a subgroup under the specific family group. Doxygen is run separately for each family so there is no danger of accidentally including the wrong stuff. Similarly for the source files for a peripheral which will subgroup under a same name (such as gpio_files). The peripheral source file in lib/stm32/f* will include this as a subgroup under the specific family group. DOXYFILE for a particular family will list the family specific and common files (headers and source) that are to be included. The result (in the long run) will be that all peripherals will appear under the same family grouping in the documentation, even if they are identical over a number of families. That is probably most useful to end users who only need to see the documentation for one family. hackrf-0.0~git20230104.cfc2f34/Makefile000066400000000000000000000066071435536612600171420ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf STYLECHECK := scripts/checkpatch.pl STYLECHECKFLAGS := --no-tree -f --terse --mailback ifeq ($(DETECT_TOOLCHAIN),) DESTDIR ?= /usr/local else DESTDIR ?= $(shell dirname $(shell readlink -f $(shell which $(PREFIX)-gcc)))/.. endif INCDIR := $(DESTDIR)/$(PREFIX)/include LIBDIR := $(DESTDIR)/$(PREFIX)/lib SHAREDIR := $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL := install SRCLIBDIR:= $(realpath lib) TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/l1 lpc13xx lpc17xx \ lpc43xx/m4 lpc43xx/m0 lm3s lm4f \ efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg sam/3x sam/3n # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) Q := @ # Do not print "Entering directory ...". MAKEFLAGS += --no-print-directory endif YAMLFILES := $(shell find . -name 'irq.yaml') STYLECHECKFILES := $(shell find . -name '*.[ch]') all: build build: lib %.genhdr: @printf " GENHDR $*\n"; @./scripts/irq2nvic_h ./$*; %.cleanhdr: @printf " CLNHDR $*\n"; @./scripts/irq2nvic_h --remove ./$* LIB_DIRS:=$(wildcard $(addprefix lib/,$(TARGETS))) $(LIB_DIRS): $(YAMLFILES:=.genhdr) @printf " BUILD $@\n"; $(Q)$(MAKE) --directory=$@ SRCLIBDIR=$(SRCLIBDIR) lib: $(LIB_DIRS) $(Q)true install: lib @printf " INSTALL headers\n" $(Q)$(INSTALL) -d $(INCDIR)/libopencm3 $(Q)$(INSTALL) -d $(INCDIR)/libopencmsis $(Q)$(INSTALL) -d $(LIBDIR) $(Q)$(INSTALL) -d $(SHAREDIR) $(Q)cp -r include/libopencm3/* $(INCDIR)/libopencm3 $(Q)cp -r include/libopencmsis/* $(INCDIR)/libopencmsis @printf " INSTALL libs\n" $(Q)$(INSTALL) -m 0644 lib/*.a $(LIBDIR) @printf " INSTALL ldscripts\n" $(Q)$(INSTALL) -m 0644 lib/*.ld $(LIBDIR) $(Q)$(INSTALL) -m 0644 lib/efm32/*/*.ld $(LIBDIR) @printf " INSTALL scripts\n" $(Q)$(INSTALL) -m 0644 scripts/*.scr $(SHAREDIR) doc: $(Q)$(MAKE) -C doc html clean: $(YAMLFILES:=.cleanhdr) $(LIB_DIRS:=.clean) $(EXAMPLE_DIRS:=.clean) doc.clean styleclean %.clean: $(Q)if [ -d $* ]; then \ printf " CLEAN $*\n"; \ $(MAKE) -C $* clean SRCLIBDIR=$(SRCLIBDIR) || exit $?; \ fi; stylecheck: $(STYLECHECKFILES:=.stylecheck) styleclean: $(STYLECHECKFILES:=.styleclean) # the cat is due to multithreaded nature - we like to have consistent chunks of text on the output %.stylecheck: $(Q)if ! grep -q "* It was generated by the irq2nvic_h script." $* ; then \ $(STYLECHECK) $(STYLECHECKFLAGS) $* > $*.stylecheck; \ if [ -s $*.stylecheck ]; then \ cat $*.stylecheck; \ else \ rm -f $*.stylecheck; \ fi; \ fi; %.styleclean: $(Q)rm -f $*.stylecheck; .PHONY: build lib $(LIB_DIRS) install doc clean stylecheck styleclean hackrf-0.0~git20230104.cfc2f34/README000066400000000000000000000114251435536612600163540ustar00rootroot00000000000000------------------------------------------------------------------------------ README ------------------------------------------------------------------------------ The libopencm3 project aims to create an open-source firmware library for various ARM Cortex-M3 microcontrollers. Currently (at least partly) supported microcontrollers: - ST STM32F1 series - ST STM32F2 series - ST STM32F4 series - NXP LPC1311/13/42/43 The library is written completely from scratch based on the vendor datasheets, programming manuals, and application notes. The code is meant to be used with a GCC toolchain for ARM (arm-elf or arm-none-eabi), flashing of the code to a microcontroller can be done using the OpenOCD ARM JTAG software. Status and API -------------- The libopencm3 project is currently work in progress. Not all subsystems of the microcontrollers are supported, yet. IMPORTANT: The API of the library is NOT yet considered stable! Please do not rely on it, yet! Changes to function names, macro names etc. can happen at any time without prior notice! TIP: Include this repository as a GIT submodule in your project. To make sure your users get the right version of the library to compile your project. For how that can be done refer to the libopencm3-examples repository. Prerequisites ------------- Building requires python, and a python YAML module. (Some code is generated) For Ubuntu $ [sudo] apt-get install python-yaml For Fedora $ [sudo] yum install PyYAML For Windows Download and install: msys - sourceforge.net/projects/mingw/files/MSYS/Base/msys-core/msys-1.0.11/MSYS-1.0.11.exe Python - http://www.python.org/ftp/python/2.7/python-2.7.msi (use installer to get the right registry keys for PyYAML) PyYAML - http://pyyaml.org/download/pyyaml/PyYAML-3.10.win32-py2.7.exe arm-none-eabi toolchain - for example this one https://launchpad.net/gcc-arm-embedded Run msys shell and set the path without standard Windows paths, so Windows programs such as 'find' won't interfere: export PATH="/c//Python27:/c/ARMToolchain/bin:/usr/local/bin:/usr/bin:/bin" After that you can navigate to the folder where you've extracted libopencm3 and build it. Building -------- $ make You may want to override the toolchain (e.g., arm-elf or arm-none-eabi): $ PREFIX=arm-none-eabi make For a more verbose build you can use $ make V=1 Fine-tuning the build --------------------- The build may be fine-tuned with a limited number of parameters, by specifying them as environment variables, for example: $ VARIABLE=value make * FP_FLAGS - Control the floating-point ABI If the Cortex-M core supports a hard float ABI, it will be compiled with floating-point support by default. In cases where this is not desired, the behavior can be specified by setting FP_FLAGS. Currently, M4F cores default to "-mfloat-abi=hard -mfpu=fpv4-sp-d16" and others to no FP flags Examples: $ FP_FLAGS="-mfloat-abi=soft" make # No hardfloat $ FP_FLAGS="-mfloat-abi=hard -mfpu=magic" make # New FPU we don't know of Example projects ---------------- The libopencm3 community has written and is maintaining a huge collection of examples, displaying the capabilities and uses of the library. You can find all of them in the libopencm3-examples repository: https://github.com/libopencm3/libopencm3-examples Installation ------------ $ make install This will install the library into /usr/local. (permissions permitting) If you want to install it elsewhere, use the following syntax: $ make DESTDIR=/opt/libopencm3 install If you want to attempt to install into your toolchain, use this: $ make DETECT_TOOLCHAIN=1 install Note: If you install this into your toolchain, you don't need to pass any extra -L or -I flags into your projects. However, this also means you must NOT pass any -L or -I flags that point into the toolchain. This _will_ confuse the linker. (ie, for summon-arm-toolchain, do NOT pass -L/home/user/sat/lib) Common symptoms of confusing the linker are hard faults caused by branches into arm code. You can use objdump to check for this in your final elf. Coding style and development guidelines --------------------------------------- See HACKING. License ------- The libopencm3 code is released under the terms of the GNU Lesser General Public License (LGPL), version 3 or later. See COPYING.GPL3 and COPYING.LGPL3 for details. IRC --- * You can reach us in #libopencm3 on the freenode IRC network. Mailing lists ------------- * Developer mailing list (for patches and discussions): https://lists.sourceforge.net/lists/listinfo/libopencm3-devel * Commits mailing list (receives one mail per 'git push'): https://lists.sourceforge.net/lists/listinfo/libopencm3-commits Website ------- http://libopencm3.org http://sourceforge.net/projects/libopencm3/ hackrf-0.0~git20230104.cfc2f34/doc/000077500000000000000000000000001435536612600162365ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/Doxyfile000066400000000000000000000022411435536612600177430ustar00rootroot00000000000000# Doxygen include file to generate top level entry document # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ./Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- INPUT = ../include/libopencm3/docmain.dox LAYOUT_FILE = DoxygenLayout.xml GENERATE_LATEX = NO TAGFILES = ./cm3/cm3.tag=../cm3/html \ ./stm32/stm32.tag=../stm32/html \ ./stm32f1/stm32f1.tag=../stm32f1/html \ ./stm32f4/stm32f4.tag=../stm32f4/html \ ./lm3s/lm3s.tag=../lm3s/html \ ./lm4f/lm4f.tag=../lm4f/html \ ./lpc13xx/lpc13xx.tag=../lpc13xx/html \ ./lpc17xx/lpc17xx.tag=../lpc17xx/html \ ./lpc43xx/lpc43xx.tag=../lpc43xx/html hackrf-0.0~git20230104.cfc2f34/doc/Doxyfile_common000066400000000000000000002270631435536612600213260ustar00rootroot00000000000000# Doxyfile 1.8.2 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project. # # All text after a hash (#) is considered a comment and will be ignored. # The format is: # TAG = value [value, ...] # For lists items can also be appended using: # TAG += value [value, ...] # Values that contain spaces should be placed between quotes (" "). #--------------------------------------------------------------------------- # Project related configuration options #--------------------------------------------------------------------------- # This tag specifies the encoding used for all characters in the config file # that follow. The default is UTF-8 which is also the encoding used for all # text before the first occurrence of this tag. Doxygen uses libiconv (or the # iconv built into libc) for the transcoding. See # http://www.gnu.org/software/libiconv for the list of possible encodings. DOXYFILE_ENCODING = UTF-8 # The PROJECT_NAME tag is a single word (or sequence of words) that should # identify the project. Note that if you do not use Doxywizard you need # to put quotes around the project name if it contains spaces. PROJECT_NAME = libopencm3 # The PROJECT_NUMBER tag can be used to enter a project or revision number. # This could be handy for archiving the generated documentation or # if some version control system is used. PROJECT_NUMBER = # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer # a quick idea about the purpose of the project. Keep the description short. PROJECT_BRIEF = "A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers." # With the PROJECT_LOGO tag one can specify an logo or icon that is # included in the documentation. The maximum height of the logo should not # exceed 55 pixels and the maximum width should not exceed 200 pixels. # Doxygen will copy the logo to the output directory. PROJECT_LOGO = # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. # If a relative path is entered, it will be relative to the location # where doxygen was started. If left blank the current directory will be used. OUTPUT_DIRECTORY = # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create # 4096 sub-directories (in 2 levels) under the output directory of each output # format and will distribute the generated files over these directories. # Enabling this option can be useful when feeding doxygen a huge amount of # source files, where putting all generated files in the same directory would # otherwise cause performance problems for the file system. CREATE_SUBDIRS = NO # The OUTPUT_LANGUAGE tag is used to specify the language in which all # documentation generated by doxygen is written. Doxygen will use this # information to generate all constant output in the proper language. # The default language is English, other supported languages are: # Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, # Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, # Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English # messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, # Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, # Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. OUTPUT_LANGUAGE = English # If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will # include brief member descriptions after the members that are listed in # the file and class documentation (similar to JavaDoc). # Set to NO to disable this. BRIEF_MEMBER_DESC = YES # If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend # the brief description of a member or function before the detailed description. # Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the # brief descriptions will be completely suppressed. REPEAT_BRIEF = YES # This tag implements a quasi-intelligent brief description abbreviator # that is used to form the text in various listings. Each string # in this list, if found as the leading text of the brief description, will be # stripped from the text and the result after processing the whole list, is # used as the annotated text. Otherwise, the brief description is used as-is. # If left blank, the following values are used ("$name" is automatically # replaced with the name of the entity): "The $name class" "The $name widget" # "The $name file" "is" "provides" "specifies" "contains" # "represents" "a" "an" "the" ABBREVIATE_BRIEF = # If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then # Doxygen will generate a detailed section even if there is only a brief # description. ALWAYS_DETAILED_SEC = NO # If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all # inherited members of a class in the documentation of that class as if those # members were ordinary class members. Constructors, destructors and assignment # operators of the base classes will not be shown. INLINE_INHERITED_MEMB = NO # If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full # path before files name in the file list and in the header files. If set # to NO the shortest path that makes the file name unique will be used. FULL_PATH_NAMES = NO # If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag # can be used to strip a user-defined part of the path. Stripping is # only done if one of the specified strings matches the left-hand part of # the path. The tag can be used to show relative paths in the file list. # If left blank the directory from which doxygen is run is used as the # path to strip. Note that you specify absolute paths here, but also # relative paths, which will be relative from the directory where doxygen is # started. STRIP_FROM_PATH = # The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of # the path mentioned in the documentation of a class, which tells # the reader which header file to include in order to use a class. # If left blank only the name of the header file containing the class # definition is used. Otherwise one should specify the include paths that # are normally passed to the compiler using the -I flag. STRIP_FROM_INC_PATH = # If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter # (but less readable) file names. This can be useful if your file system # doesn't support long names like on DOS, Mac, or CD-ROM. SHORT_NAMES = NO # If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen # will interpret the first line (until the first dot) of a JavaDoc-style # comment as the brief description. If set to NO, the JavaDoc # comments will behave just like regular Qt-style comments # (thus requiring an explicit @brief command for a brief description.) JAVADOC_AUTOBRIEF = YES # If the QT_AUTOBRIEF tag is set to YES then Doxygen will # interpret the first line (until the first dot) of a Qt-style # comment as the brief description. If set to NO, the comments # will behave just like regular Qt-style comments (thus requiring # an explicit \brief command for a brief description.) QT_AUTOBRIEF = NO # The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen # treat a multi-line C++ special comment block (i.e. a block of //! or /// # comments) as a brief description. This used to be the default behaviour. # The new default is to treat a multi-line C++ comment block as a detailed # description. Set this tag to YES if you prefer the old behaviour instead. MULTILINE_CPP_IS_BRIEF = NO # If the INHERIT_DOCS tag is set to YES (the default) then an undocumented # member inherits the documentation from any documented member that it # re-implements. INHERIT_DOCS = YES # If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce # a new page for each member. If set to NO, the documentation of a member will # be part of the file/class/namespace that contains it. SEPARATE_MEMBER_PAGES = NO # The TAB_SIZE tag can be used to set the number of spaces in a tab. # Doxygen uses this value to replace tabs by spaces in code fragments. TAB_SIZE = 8 # This tag can be used to specify a number of aliases that acts # as commands in the documentation. An alias has the form "name=value". # For example adding "sideeffect=\par Side Effects:\n" will allow you to # put the command \sideeffect (or @sideeffect) in the documentation, which # will result in a user-defined paragraph with heading "Side Effects:". # You can put \n's in the value part of an alias to insert newlines. ALIASES = # This tag can be used to specify a number of word-keyword mappings (TCL only). # A mapping has the form "name=value". For example adding # "class=itcl::class" will allow you to use the command class in the # itcl::class meaning. TCL_SUBST = # Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C # sources only. Doxygen will then generate output that is more tailored for C. # For instance, some of the names that are used will be different. The list # of all members will be omitted, etc. OPTIMIZE_OUTPUT_FOR_C = YES # Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java # sources only. Doxygen will then generate output that is more tailored for # Java. For instance, namespaces will be presented as packages, qualified # scopes will look different, etc. OPTIMIZE_OUTPUT_JAVA = NO # Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran # sources only. Doxygen will then generate output that is more tailored for # Fortran. OPTIMIZE_FOR_FORTRAN = NO # Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL # sources. Doxygen will then generate output that is tailored for # VHDL. OPTIMIZE_OUTPUT_VHDL = NO # Doxygen selects the parser to use depending on the extension of the files it # parses. With this tag you can assign which parser to use for a given # extension. Doxygen has a built-in mapping, but you can override or extend it # using this tag. The format is ext=language, where ext is a file extension, # and language is one of the parsers supported by doxygen: IDL, Java, # Javascript, CSharp, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, # C++. For instance to make doxygen treat .inc files as Fortran files (default # is PHP), and .f files as C (default is Fortran), use: inc=Fortran f=C. Note # that for custom extensions you also need to set FILE_PATTERNS otherwise the # files are not read by doxygen. EXTENSION_MAPPING = # If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all # comments according to the Markdown format, which allows for more readable # documentation. See http://daringfireball.net/projects/markdown/ for details. # The output of markdown processing is further processed by doxygen, so you # can mix doxygen, HTML, and XML commands with Markdown formatting. # Disable only in case of backward compatibilities issues. MARKDOWN_SUPPORT = YES # When enabled doxygen tries to link words that correspond to documented classes, # or namespaces to their corresponding documentation. Such a link can be # prevented in individual cases by by putting a % sign in front of the word or # globally by setting AUTOLINK_SUPPORT to NO. AUTOLINK_SUPPORT = YES # If you use STL classes (i.e. std::string, std::vector, etc.) but do not want # to include (a tag file for) the STL sources as input, then you should # set this tag to YES in order to let doxygen match functions declarations and # definitions whose arguments contain STL classes (e.g. func(std::string); v.s. # func(std::string) {}). This also makes the inheritance and collaboration # diagrams that involve STL classes more complete and accurate. BUILTIN_STL_SUPPORT = NO # If you use Microsoft's C++/CLI language, you should set this option to YES to # enable parsing support. CPP_CLI_SUPPORT = NO # Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. # Doxygen will parse them like normal C++ but will assume all classes use public # instead of private inheritance when no explicit protection keyword is present. SIP_SUPPORT = NO # For Microsoft's IDL there are propget and propput attributes to indicate getter and setter methods for a property. Setting this option to YES (the default) will make doxygen replace the get and set methods by a property in the documentation. This will only work if the methods are indeed getting or setting a simple type. If this is not the case, or you want to show the methods anyway, you should set this option to NO. IDL_PROPERTY_SUPPORT = YES # If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC # tag is set to YES, then doxygen will reuse the documentation of the first # member in the group (if any) for the other members of the group. By default # all members of a group must be documented explicitly. DISTRIBUTE_GROUP_DOC = NO # Set the SUBGROUPING tag to YES (the default) to allow class member groups of # the same type (for instance a group of public functions) to be put as a # subgroup of that type (e.g. under the Public Functions section). Set it to # NO to prevent subgrouping. Alternatively, this can be done per class using # the \nosubgrouping command. SUBGROUPING = YES # When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and # unions are shown inside the group in which they are included (e.g. using # @ingroup) instead of on a separate page (for HTML and Man pages) or # section (for LaTeX and RTF). INLINE_GROUPED_CLASSES = NO # When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and # unions with only public data fields will be shown inline in the documentation # of the scope in which they are defined (i.e. file, namespace, or group # documentation), provided this scope is documented. If set to NO (the default), # structs, classes, and unions are shown on a separate page (for HTML and Man # pages) or section (for LaTeX and RTF). INLINE_SIMPLE_STRUCTS = NO # When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum # is documented as struct, union, or enum with the name of the typedef. So # typedef struct TypeS {} TypeT, will appear in the documentation as a struct # with name TypeT. When disabled the typedef will appear as a member of a file, # namespace, or class. And the struct will be named TypeS. This can typically # be useful for C code in case the coding convention dictates that all compound # types are typedef'ed and only the typedef is referenced, never the tag name. TYPEDEF_HIDES_STRUCT = NO # The SYMBOL_CACHE_SIZE determines the size of the internal cache use to # determine which symbols to keep in memory and which to flush to disk. # When the cache is full, less often used symbols will be written to disk. # For small to medium size projects (<1000 input files) the default value is # probably good enough. For larger projects a too small cache size can cause # doxygen to be busy swapping symbols to and from disk most of the time # causing a significant performance penalty. # If the system has enough physical memory increasing the cache will improve the # performance by keeping more symbols in memory. Note that the value works on # a logarithmic scale so increasing the size by one will roughly double the # memory usage. The cache size is given by this formula: # 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, # corresponding to a cache size of 2^16 = 65536 symbols. SYMBOL_CACHE_SIZE = 0 # Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be # set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given # their name and scope. Since this can be an expensive process and often the # same symbol appear multiple times in the code, doxygen keeps a cache of # pre-resolved symbols. If the cache is too small doxygen will become slower. # If the cache is too large, memory is wasted. The cache size is given by this # formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0, # corresponding to a cache size of 2^16 = 65536 symbols. LOOKUP_CACHE_SIZE = 0 #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- # If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in # documentation are documented, even if no documentation was available. # Private class members and static file members will be hidden unless # the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES EXTRACT_ALL = YES # If the EXTRACT_PRIVATE tag is set to YES all private members of a class # will be included in the documentation. EXTRACT_PRIVATE = YES # If the EXTRACT_PACKAGE tag is set to YES all members with package or internal # scope will be included in the documentation. EXTRACT_PACKAGE = NO # If the EXTRACT_STATIC tag is set to YES all static members of a file # will be included in the documentation. EXTRACT_STATIC = YES # If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) # defined locally in source files will be included in the documentation. # If set to NO only classes defined in header files are included. EXTRACT_LOCAL_CLASSES = YES # This flag is only useful for Objective-C code. When set to YES local # methods, which are defined in the implementation section but not in # the interface are included in the documentation. # If set to NO (the default) only methods in the interface are included. EXTRACT_LOCAL_METHODS = NO # If this flag is set to YES, the members of anonymous namespaces will be # extracted and appear in the documentation as a namespace called # 'anonymous_namespace{file}', where file will be replaced with the base # name of the file that contains the anonymous namespace. By default # anonymous namespaces are hidden. EXTRACT_ANON_NSPACES = NO # If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all # undocumented members of documented classes, files or namespaces. # If set to NO (the default) these members will be included in the # various overviews, but no documentation section is generated. # This option has no effect if EXTRACT_ALL is enabled. HIDE_UNDOC_MEMBERS = NO # If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all # undocumented classes that are normally visible in the class hierarchy. # If set to NO (the default) these classes will be included in the various # overviews. This option has no effect if EXTRACT_ALL is enabled. HIDE_UNDOC_CLASSES = NO # If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all # friend (class|struct|union) declarations. # If set to NO (the default) these declarations will be included in the # documentation. HIDE_FRIEND_COMPOUNDS = NO # If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any # documentation blocks found inside the body of a function. # If set to NO (the default) these blocks will be appended to the # function's detailed documentation block. HIDE_IN_BODY_DOCS = NO # The INTERNAL_DOCS tag determines if documentation # that is typed after a \internal command is included. If the tag is set # to NO (the default) then the documentation will be excluded. # Set it to YES to include the internal documentation. INTERNAL_DOCS = NO # If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate # file names in lower-case letters. If set to YES upper-case letters are also # allowed. This is useful if you have classes or files whose names only differ # in case and if your file system supports case sensitive file names. Windows # and Mac users are advised to set this option to NO. CASE_SENSE_NAMES = YES # If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen # will show members with their full class and namespace scopes in the # documentation. If set to YES the scope will be hidden. HIDE_SCOPE_NAMES = NO # If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen # will put a list of the files that are included by a file in the documentation # of that file. SHOW_INCLUDE_FILES = YES # If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen # will list include files with double quotes in the documentation # rather than with sharp brackets. FORCE_LOCAL_INCLUDES = NO # If the INLINE_INFO tag is set to YES (the default) then a tag [inline] # is inserted in the documentation for inline members. INLINE_INFO = YES # If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen # will sort the (detailed) documentation of file and class members # alphabetically by member name. If set to NO the members will appear in # declaration order. SORT_MEMBER_DOCS = YES # If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the # brief documentation of file, namespace and class members alphabetically # by member name. If set to NO (the default) the members will appear in # declaration order. SORT_BRIEF_DOCS = NO # If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen # will sort the (brief and detailed) documentation of class members so that # constructors and destructors are listed first. If set to NO (the default) # the constructors will appear in the respective orders defined by # SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. # This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO # and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. SORT_MEMBERS_CTORS_1ST = NO # If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the # hierarchy of group names into alphabetical order. If set to NO (the default) # the group names will appear in their defined order. SORT_GROUP_NAMES = NO # If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be # sorted by fully-qualified names, including namespaces. If set to # NO (the default), the class list will be sorted only by class name, # not including the namespace part. # Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. # Note: This option applies only to the class list, not to the # alphabetical list. SORT_BY_SCOPE_NAME = NO # If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to # do proper type resolution of all parameters of a function it will reject a # match between the prototype and the implementation of a member function even # if there is only one candidate or it is obvious which candidate to choose # by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen # will still accept a match between prototype and implementation in such cases. STRICT_PROTO_MATCHING = NO # The GENERATE_TODOLIST tag can be used to enable (YES) or # disable (NO) the todo list. This list is created by putting \todo # commands in the documentation. GENERATE_TODOLIST = NO # The GENERATE_TESTLIST tag can be used to enable (YES) or # disable (NO) the test list. This list is created by putting \test # commands in the documentation. GENERATE_TESTLIST = YES # The GENERATE_BUGLIST tag can be used to enable (YES) or # disable (NO) the bug list. This list is created by putting \bug # commands in the documentation. GENERATE_BUGLIST = YES # The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or # disable (NO) the deprecated list. This list is created by putting # \deprecated commands in the documentation. GENERATE_DEPRECATEDLIST= NO # The ENABLED_SECTIONS tag can be used to enable conditional # documentation sections, marked by \if sectionname ... \endif. ENABLED_SECTIONS = # The MAX_INITIALIZER_LINES tag determines the maximum number of lines # the initial value of a variable or macro consists of for it to appear in # the documentation. If the initializer consists of more lines than specified # here it will be hidden. Use a value of 0 to hide initializers completely. # The appearance of the initializer of individual variables and macros in the # documentation can be controlled using \showinitializer or \hideinitializer # command in the documentation regardless of this setting. MAX_INITIALIZER_LINES = 30 # Set the SHOW_USED_FILES tag to NO to disable the list of files generated # at the bottom of the documentation of classes and structs. If set to YES the # list will mention the files that were used to generate the documentation. SHOW_USED_FILES = YES # Set the SHOW_FILES tag to NO to disable the generation of the Files page. # This will remove the Files entry from the Quick Index and from the # Folder Tree View (if specified). The default is YES. SHOW_FILES = YES # Set the SHOW_NAMESPACES tag to NO to disable the generation of the # Namespaces page. # This will remove the Namespaces entry from the Quick Index # and from the Folder Tree View (if specified). The default is YES. SHOW_NAMESPACES = YES # The FILE_VERSION_FILTER tag can be used to specify a program or script that # doxygen should invoke to get the current version for each file (typically from # the version control system). Doxygen will invoke the program by executing (via # popen()) the command , where is the value of # the FILE_VERSION_FILTER tag, and is the name of an input file # provided by doxygen. Whatever the program writes to standard output # is used as the file version. See the manual for examples. FILE_VERSION_FILTER = # The LAYOUT_FILE tag can be used to specify a layout file which will be parsed # by doxygen. The layout file controls the global structure of the generated # output files in an output format independent way. To create the layout file # that represents doxygen's defaults, run doxygen with the -l option. # You can optionally specify a file name after the option, if omitted # DoxygenLayout.xml will be used as the name of the layout file. LAYOUT_FILE = DoxygenLayout.xml # The CITE_BIB_FILES tag can be used to specify one or more bib files # containing the references data. This must be a list of .bib files. The # .bib extension is automatically appended if omitted. Using this command # requires the bibtex tool to be installed. See also # http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style # of the bibliography can be controlled using LATEX_BIB_STYLE. To use this # feature you need bibtex and perl available in the search path. CITE_BIB_FILES = #--------------------------------------------------------------------------- # configuration options related to warning and progress messages #--------------------------------------------------------------------------- # The QUIET tag can be used to turn on/off the messages that are generated # by doxygen. Possible values are YES and NO. If left blank NO is used. QUIET = NO # The WARNINGS tag can be used to turn on/off the warning messages that are # generated by doxygen. Possible values are YES and NO. If left blank # NO is used. WARNINGS = YES # If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings # for undocumented members. If EXTRACT_ALL is set to YES then this flag will # automatically be disabled. WARN_IF_UNDOCUMENTED = YES # If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for # potential errors in the documentation, such as not documenting some # parameters in a documented function, or documenting parameters that # don't exist or using markup commands wrongly. WARN_IF_DOC_ERROR = YES # The WARN_NO_PARAMDOC option can be enabled to get warnings for # functions that are documented, but have no documentation for their parameters # or return value. If set to NO (the default) doxygen will only warn about # wrong or incomplete parameter documentation, but not about the absence of # documentation. WARN_NO_PARAMDOC = NO # The WARN_FORMAT tag determines the format of the warning messages that # doxygen can produce. The string should contain the $file, $line, and $text # tags, which will be replaced by the file and line number from which the # warning originated and the warning text. Optionally the format may contain # $version, which will be replaced by the version of the file (if it could # be obtained via FILE_VERSION_FILTER) WARN_FORMAT = "$file:$line: $text" # The WARN_LOGFILE tag can be used to specify a file to which warning # and error messages should be written. If left blank the output is written # to stderr. WARN_LOGFILE = doxygen.log #--------------------------------------------------------------------------- # configuration options related to the input files #--------------------------------------------------------------------------- # The INPUT tag can be used to specify the files and/or directories that contain # documented source files. You may enter file names like "myfile.cpp" or # directories like "/usr/src/myproject". Separate the files or directories # with spaces. INPUT = # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is # also the default input encoding. Doxygen uses libiconv (or the iconv built # into libc) for the transcoding. See http://www.gnu.org/software/libiconv for # the list of possible encodings. INPUT_ENCODING = UTF-8 # If the value of the INPUT tag contains directories, you can use the # FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp # and *.h) to filter out the source-files in the directories. If left # blank the following patterns are tested: # *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh # *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py # *.f90 *.f *.for *.vhd *.vhdl FILE_PATTERNS = # The RECURSIVE tag can be used to turn specify whether or not subdirectories # should be searched for input files as well. Possible values are YES and NO. # If left blank NO is used. RECURSIVE = NO # The EXCLUDE tag can be used to specify files and/or directories that should be # excluded from the INPUT source files. This way you can easily exclude a # subdirectory from a directory tree whose root is specified with the INPUT tag. # Note that relative paths are relative to the directory from which doxygen is # run. EXCLUDE = # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or # directories that are symbolic links (a Unix file system feature) are excluded # from the input. EXCLUDE_SYMLINKS = NO # If the value of the INPUT tag contains directories, you can use the # EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude # certain files from those directories. Note that the wildcards are matched # against the file with absolute path, so to exclude all test directories # for example use the pattern */test/* EXCLUDE_PATTERNS = */*.d # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # (namespaces, classes, functions, etc.) that should be excluded from the # output. The symbol name can be a fully qualified name, a word, or if the # wildcard * is used, a substring. Examples: ANamespace, AClass, # AClass::ANamespace, ANamespace::*Test EXCLUDE_SYMBOLS = # The EXAMPLE_PATH tag can be used to specify one or more files or # directories that contain example code fragments that are included (see # the \include command). EXAMPLE_PATH = # If the value of the EXAMPLE_PATH tag contains directories, you can use the # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp # and *.h) to filter out the source-files in the directories. If left # blank all files are included. EXAMPLE_PATTERNS = # If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be # searched for input files to be used with the \include or \dontinclude # commands irrespective of the value of the RECURSIVE tag. # Possible values are YES and NO. If left blank NO is used. EXAMPLE_RECURSIVE = NO # The IMAGE_PATH tag can be used to specify one or more files or # directories that contain image that are included in the documentation (see # the \image command). IMAGE_PATH = # The INPUT_FILTER tag can be used to specify a program that doxygen should # invoke to filter for each input file. Doxygen will invoke the filter program # by executing (via popen()) the command , where # is the value of the INPUT_FILTER tag, and is the name of an # input file. Doxygen will then use the output that the filter program writes # to standard output. # If FILTER_PATTERNS is specified, this tag will be # ignored. INPUT_FILTER = # The FILTER_PATTERNS tag can be used to specify filters on a per file pattern # basis. # Doxygen will compare the file name with each pattern and apply the # filter if there is a match. # The filters are a list of the form: # pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further # info on how filters are used. If FILTER_PATTERNS is empty or if # non of the patterns match the file name, INPUT_FILTER is applied. FILTER_PATTERNS = # If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using # INPUT_FILTER) will be used to filter the input files when producing source # files to browse (i.e. when SOURCE_BROWSER is set to YES). FILTER_SOURCE_FILES = NO # The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file # pattern. A pattern will override the setting for FILTER_PATTERN (if any) # and it is also possible to disable source filtering for a specific pattern # using *.ext= (so without naming a filter). This option only has effect when # FILTER_SOURCE_FILES is enabled. FILTER_SOURCE_PATTERNS = #--------------------------------------------------------------------------- # configuration options related to source browsing #--------------------------------------------------------------------------- # If the SOURCE_BROWSER tag is set to YES then a list of source files will # be generated. Documented entities will be cross-referenced with these sources. # Note: To get rid of all source code in the generated output, make sure also # VERBATIM_HEADERS is set to NO. SOURCE_BROWSER = YES # Setting the INLINE_SOURCES tag to YES will include the body # of functions and classes directly in the documentation. INLINE_SOURCES = NO # Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct # doxygen to hide any special comment blocks from generated source code # fragments. Normal C, C++ and Fortran comments will always remain visible. STRIP_CODE_COMMENTS = NO # If the REFERENCED_BY_RELATION tag is set to YES # then for each documented function all documented # functions referencing it will be listed. REFERENCED_BY_RELATION = YES # If the REFERENCES_RELATION tag is set to YES # then for each documented function all documented entities # called/used by that function will be listed. REFERENCES_RELATION = YES # If the REFERENCES_LINK_SOURCE tag is set to YES (the default) # and SOURCE_BROWSER tag is set to YES, then the hyperlinks from # functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will # link to the source code. # Otherwise they will link to the documentation. REFERENCES_LINK_SOURCE = YES # If the USE_HTAGS tag is set to YES then the references to source code # will point to the HTML generated by the htags(1) tool instead of doxygen # built-in source browser. The htags tool is part of GNU's global source # tagging system (see http://www.gnu.org/software/global/global.html). You # will need version 4.8.6 or higher. USE_HTAGS = NO # If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen # will generate a verbatim copy of the header file for each class for # which an include is specified. Set to NO to disable this. VERBATIM_HEADERS = YES #--------------------------------------------------------------------------- # configuration options related to the alphabetical class index #--------------------------------------------------------------------------- # If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index # of all compounds will be generated. Enable this if the project # contains a lot of classes, structs, unions or interfaces. ALPHABETICAL_INDEX = YES # If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then # the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns # in which this list will be split (can be a number in the range [1..20]) COLS_IN_ALPHA_INDEX = 5 # In case all classes in a project start with a common prefix, all # classes will be put under the same header in the alphabetical index. # The IGNORE_PREFIX tag can be used to specify one or more prefixes that # should be ignored while generating the index headers. IGNORE_PREFIX = #--------------------------------------------------------------------------- # configuration options related to the HTML output #--------------------------------------------------------------------------- # If the GENERATE_HTML tag is set to YES (the default) Doxygen will # generate HTML output. GENERATE_HTML = YES # The HTML_OUTPUT tag is used to specify where the HTML docs will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `html' will be used as the default path. HTML_OUTPUT = html # The HTML_FILE_EXTENSION tag can be used to specify the file extension for # each generated HTML page (for example: .htm,.php,.asp). If it is left blank # doxygen will generate files with .html extension. HTML_FILE_EXTENSION = .html # The HTML_HEADER tag can be used to specify a personal HTML header for # each generated HTML page. If it is left blank doxygen will generate a # standard header. Note that when using a custom header you are responsible # for the proper inclusion of any scripts and style sheets that doxygen # needs, which is dependent on the configuration options used. # It is advised to generate a default header using "doxygen -w html # header.html footer.html stylesheet.css YourConfigFile" and then modify # that header. Note that the header is subject to change so you typically # have to redo this when upgrading to a newer version of doxygen or when # changing the value of configuration settings such as GENERATE_TREEVIEW! HTML_HEADER = # The HTML_FOOTER tag can be used to specify a personal HTML footer for # each generated HTML page. If it is left blank doxygen will generate a # standard footer. HTML_FOOTER = # The HTML_STYLESHEET tag can be used to specify a user-defined cascading # style sheet that is used by each HTML page. It can be used to # fine-tune the look of the HTML output. If left blank doxygen will # generate a default style sheet. Note that it is recommended to use # HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this # tag will in the future become obsolete. HTML_STYLESHEET = # The HTML_EXTRA_STYLESHEET tag can be used to specify an additional # user-defined cascading style sheet that is included after the standard # style sheets created by doxygen. Using this option one can overrule # certain style aspects. This is preferred over using HTML_STYLESHEET # since it does not replace the standard style sheet and is therefor more # robust against future updates. Doxygen will copy the style sheet file to # the output directory. HTML_EXTRA_STYLESHEET = # The HTML_EXTRA_FILES tag can be used to specify one or more extra images or # other source files which should be copied to the HTML output directory. Note # that these files will be copied to the base HTML output directory. Use the # $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these # files. In the HTML_STYLESHEET file, use the file name only. Also note that # the files will be copied as-is; there are no commands or markers available. HTML_EXTRA_FILES = # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. # Doxygen will adjust the colors in the style sheet and background images # according to this color. Hue is specified as an angle on a colorwheel, # see http://en.wikipedia.org/wiki/Hue for more information. # For instance the value 0 represents red, 60 is yellow, 120 is green, # 180 is cyan, 240 is blue, 300 purple, and 360 is red again. # The allowed range is 0 to 359. HTML_COLORSTYLE_HUE = 220 # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of # the colors in the HTML output. For a value of 0 the output will use # grayscales only. A value of 255 will produce the most vivid colors. HTML_COLORSTYLE_SAT = 100 # The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to # the luminance component of the colors in the HTML output. Values below # 100 gradually make the output lighter, whereas values above 100 make # the output darker. The value divided by 100 is the actual gamma applied, # so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, # and 100 does not change the gamma. HTML_COLORSTYLE_GAMMA = 80 # If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML # page will contain the date and time when the page was generated. Setting # this to NO can help when comparing the output of multiple runs. HTML_TIMESTAMP = YES # If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML # documentation will contain sections that can be hidden and shown after the # page has loaded. HTML_DYNAMIC_SECTIONS = NO # With HTML_INDEX_NUM_ENTRIES one can control the preferred number of # entries shown in the various tree structured indices initially; the user # can expand and collapse entries dynamically later on. Doxygen will expand # the tree to such a level that at most the specified number of entries are # visible (unless a fully collapsed tree already exceeds this amount). # So setting the number of entries 1 will produce a full collapsed tree by # default. 0 is a special value representing an infinite number of entries # and will result in a full expanded tree by default. HTML_INDEX_NUM_ENTRIES = 100 # If the GENERATE_DOCSET tag is set to YES, additional index files # will be generated that can be used as input for Apple's Xcode 3 # integrated development environment, introduced with OSX 10.5 (Leopard). # To create a documentation set, doxygen will generate a Makefile in the # HTML output directory. Running make will produce the docset in that # directory and running "make install" will install the docset in # ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find # it at startup. # See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html # for more information. GENERATE_DOCSET = NO # When GENERATE_DOCSET tag is set to YES, this tag determines the name of the # feed. A documentation feed provides an umbrella under which multiple # documentation sets from a single provider (such as a company or product suite) # can be grouped. DOCSET_FEEDNAME = "Doxygen generated docs" # When GENERATE_DOCSET tag is set to YES, this tag specifies a string that # should uniquely identify the documentation set bundle. This should be a # reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen # will append .docset to the name. DOCSET_BUNDLE_ID = org.doxygen.Project # When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely # identify the documentation publisher. This should be a reverse domain-name # style string, e.g. com.mycompany.MyDocSet.documentation. DOCSET_PUBLISHER_ID = org.doxygen.Publisher # The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. DOCSET_PUBLISHER_NAME = Publisher # If the GENERATE_HTMLHELP tag is set to YES, additional index files # will be generated that can be used as input for tools like the # Microsoft HTML help workshop to generate a compiled HTML help file (.chm) # of the generated HTML documentation. GENERATE_HTMLHELP = NO # If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can # be used to specify the file name of the resulting .chm file. You # can add a path in front of the file if the result should not be # written to the html output directory. CHM_FILE = # If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can # be used to specify the location (absolute path including file name) of # the HTML help compiler (hhc.exe). If non-empty doxygen will try to run # the HTML help compiler on the generated index.hhp. HHC_LOCATION = # If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag # controls if a separate .chi index file is generated (YES) or that # it should be included in the master .chm file (NO). GENERATE_CHI = NO # If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING # is used to encode HtmlHelp index (hhk), content (hhc) and project file # content. CHM_INDEX_ENCODING = # If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag # controls whether a binary table of contents is generated (YES) or a # normal table of contents (NO) in the .chm file. BINARY_TOC = NO # The TOC_EXPAND flag can be set to YES to add extra items for group members # to the contents of the HTML help documentation and to the tree view. TOC_EXPAND = NO # If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and # QHP_VIRTUAL_FOLDER are set, an additional index file will be generated # that can be used as input for Qt's qhelpgenerator to generate a # Qt Compressed Help (.qch) of the generated HTML documentation. GENERATE_QHP = NO # If the QHG_LOCATION tag is specified, the QCH_FILE tag can # be used to specify the file name of the resulting .qch file. # The path specified is relative to the HTML output folder. QCH_FILE = # The QHP_NAMESPACE tag specifies the namespace to use when generating # Qt Help Project output. For more information please see # http://doc.trolltech.com/qthelpproject.html#namespace QHP_NAMESPACE = org.doxygen.Project # The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating # Qt Help Project output. For more information please see # http://doc.trolltech.com/qthelpproject.html#virtual-folders QHP_VIRTUAL_FOLDER = doc # If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to # add. For more information please see # http://doc.trolltech.com/qthelpproject.html#custom-filters QHP_CUST_FILTER_NAME = # The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the # custom filter to add. For more information please see # # Qt Help Project / Custom Filters. QHP_CUST_FILTER_ATTRS = # The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this # project's # filter section matches. # # Qt Help Project / Filter Attributes. QHP_SECT_FILTER_ATTRS = # If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can # be used to specify the location of Qt's qhelpgenerator. # If non-empty doxygen will try to run qhelpgenerator on the generated # .qhp file. QHG_LOCATION = # If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files # will be generated, which together with the HTML files, form an Eclipse help # plugin. To install this plugin and make it available under the help contents # menu in Eclipse, the contents of the directory containing the HTML and XML # files needs to be copied into the plugins directory of eclipse. The name of # the directory within the plugins directory should be the same as # the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before # the help appears. GENERATE_ECLIPSEHELP = NO # A unique identifier for the eclipse help plugin. When installing the plugin # the directory name containing the HTML and XML files should also have # this name. ECLIPSE_DOC_ID = org.doxygen.Project # The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) # at top of each HTML page. The value NO (the default) enables the index and # the value YES disables it. Since the tabs have the same information as the # navigation tree you can set this option to NO if you already set # GENERATE_TREEVIEW to YES. DISABLE_INDEX = NO # The GENERATE_TREEVIEW tag is used to specify whether a tree-like index # structure should be generated to display hierarchical information. # If the tag value is set to YES, a side panel will be generated # containing a tree-like index structure (just like the one that # is generated for HTML Help). For this to work a browser that supports # JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). # Windows users are probably better off using the HTML help feature. # Since the tree basically has the same information as the tab index you # could consider to set DISABLE_INDEX to NO when enabling this option. GENERATE_TREEVIEW = YES # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values # (range [0,1..20]) that doxygen will group on one line in the generated HTML # documentation. Note that a value of 0 will completely suppress the enum # values from appearing in the overview section. ENUM_VALUES_PER_LINE = 4 # If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be # used to set the initial width (in pixels) of the frame in which the tree # is shown. TREEVIEW_WIDTH = 250 # When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open # links to external symbols imported via tag files in a separate window. EXT_LINKS_IN_WINDOW = NO # Use this tag to change the font size of Latex formulas included # as images in the HTML documentation. The default is 10. Note that # when you change the font size after a successful doxygen run you need # to manually remove any form_*.png images from the HTML output directory # to force them to be regenerated. FORMULA_FONTSIZE = 10 # Use the FORMULA_TRANPARENT tag to determine whether or not the images # generated for formulas are transparent PNGs. Transparent PNGs are # not supported properly for IE 6.0, but are supported on all modern browsers. # Note that when changing this option you need to delete any form_*.png files # in the HTML output before the changes have effect. FORMULA_TRANSPARENT = YES # Enable the USE_MATHJAX option to render LaTeX formulas using MathJax # (see http://www.mathjax.org) which uses client side Javascript for the # rendering instead of using prerendered bitmaps. Use this if you do not # have LaTeX installed or if you want to formulas look prettier in the HTML # output. When enabled you may also need to install MathJax separately and # configure the path to it using the MATHJAX_RELPATH option. USE_MATHJAX = NO # When MathJax is enabled you need to specify the location relative to the # HTML output directory using the MATHJAX_RELPATH option. The destination # directory should contain the MathJax.js script. For instance, if the mathjax # directory is located at the same level as the HTML output directory, then # MATHJAX_RELPATH should be ../mathjax. The default value points to # the MathJax Content Delivery Network so you can quickly see the result without # installing MathJax. # However, it is strongly recommended to install a local # copy of MathJax from http://www.mathjax.org before deployment. MATHJAX_RELPATH = http://www.mathjax.org/mathjax # The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension # names that should be enabled during MathJax rendering. MATHJAX_EXTENSIONS = # When the SEARCHENGINE tag is enabled doxygen will generate a search box # for the HTML output. The underlying search engine uses javascript # and DHTML and should work on any modern browser. Note that when using # HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets # (GENERATE_DOCSET) there is already a search function so this one should # typically be disabled. For large projects the javascript based search engine # can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. SEARCHENGINE = YES # When the SERVER_BASED_SEARCH tag is enabled the search engine will be # implemented using a PHP enabled web server instead of at the web client # using Javascript. Doxygen will generate the search PHP script and index # file to put on the web server. The advantage of the server # based approach is that it scales better to large projects and allows # full text search. The disadvantages are that it is more difficult to setup # and does not have live searching capabilities. SERVER_BASED_SEARCH = NO #--------------------------------------------------------------------------- # configuration options related to the LaTeX output #--------------------------------------------------------------------------- # If the GENERATE_LATEX tag is set to YES (the default) Doxygen will # generate Latex output. GENERATE_LATEX = NO # The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `latex' will be used as the default path. LATEX_OUTPUT = latex # The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be # invoked. If left blank `latex' will be used as the default command name. # Note that when enabling USE_PDFLATEX this option is only used for # generating bitmaps for formulas in the HTML output, but not in the # Makefile that is written to the output directory. LATEX_CMD_NAME = latex # The MAKEINDEX_CMD_NAME tag can be used to specify the command name to # generate index for LaTeX. If left blank `makeindex' will be used as the # default command name. MAKEINDEX_CMD_NAME = makeindex # If the COMPACT_LATEX tag is set to YES Doxygen generates more compact # LaTeX documents. This may be useful for small projects and may help to # save some trees in general. COMPACT_LATEX = NO # The PAPER_TYPE tag can be used to set the paper type that is used # by the printer. Possible values are: a4, letter, legal and # executive. If left blank a4wide will be used. PAPER_TYPE = a4 # The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX # packages that should be included in the LaTeX output. EXTRA_PACKAGES = # The LATEX_HEADER tag can be used to specify a personal LaTeX header for # the generated latex document. The header should contain everything until # the first chapter. If it is left blank doxygen will generate a # standard header. Notice: only use this tag if you know what you are doing! LATEX_HEADER = # The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for # the generated latex document. The footer should contain everything after # the last chapter. If it is left blank doxygen will generate a # standard footer. Notice: only use this tag if you know what you are doing! LATEX_FOOTER = # If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated # is prepared for conversion to pdf (using ps2pdf). The pdf file will # contain links (just like the HTML output) instead of page references # This makes the output suitable for online browsing using a pdf viewer. PDF_HYPERLINKS = YES # If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of # plain latex in the generated Makefile. Set this option to YES to get a # higher quality PDF documentation. USE_PDFLATEX = YES # If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. # command to the generated LaTeX files. This will instruct LaTeX to keep # running if errors occur, instead of asking the user for help. # This option is also used when generating formulas in HTML. LATEX_BATCHMODE = NO # If LATEX_HIDE_INDICES is set to YES then doxygen will not # include the index chapters (such as File Index, Compound Index, etc.) # in the output. LATEX_HIDE_INDICES = NO # If LATEX_SOURCE_CODE is set to YES then doxygen will include # source code with syntax highlighting in the LaTeX output. # Note that which sources are shown also depends on other settings # such as SOURCE_BROWSER. LATEX_SOURCE_CODE = NO # The LATEX_BIB_STYLE tag can be used to specify the style to use for the # bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See # http://en.wikipedia.org/wiki/BibTeX for more info. LATEX_BIB_STYLE = plain #--------------------------------------------------------------------------- # configuration options related to the RTF output #--------------------------------------------------------------------------- # If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output # The RTF output is optimized for Word 97 and may not look very pretty with # other RTF readers or editors. GENERATE_RTF = NO # The RTF_OUTPUT tag is used to specify where the RTF docs will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `rtf' will be used as the default path. RTF_OUTPUT = rtf # If the COMPACT_RTF tag is set to YES Doxygen generates more compact # RTF documents. This may be useful for small projects and may help to # save some trees in general. COMPACT_RTF = NO # If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated # will contain hyperlink fields. The RTF file will # contain links (just like the HTML output) instead of page references. # This makes the output suitable for online browsing using WORD or other # programs which support those fields. # Note: wordpad (write) and others do not support links. RTF_HYPERLINKS = NO # Load style sheet definitions from file. Syntax is similar to doxygen's # config file, i.e. a series of assignments. You only have to provide # replacements, missing definitions are set to their default value. RTF_STYLESHEET_FILE = # Set optional variables used in the generation of an rtf document. # Syntax is similar to doxygen's config file. RTF_EXTENSIONS_FILE = #--------------------------------------------------------------------------- # configuration options related to the man page output #--------------------------------------------------------------------------- # If the GENERATE_MAN tag is set to YES (the default) Doxygen will # generate man pages GENERATE_MAN = NO # The MAN_OUTPUT tag is used to specify where the man pages will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `man' will be used as the default path. MAN_OUTPUT = man # The MAN_EXTENSION tag determines the extension that is added to # the generated man pages (default is the subroutine's section .3) MAN_EXTENSION = .3 # If the MAN_LINKS tag is set to YES and Doxygen generates man output, # then it will generate one additional man file for each entity # documented in the real man page(s). These additional files # only source the real man page, but without them the man command # would be unable to find the correct page. The default is NO. MAN_LINKS = NO #--------------------------------------------------------------------------- # configuration options related to the XML output #--------------------------------------------------------------------------- # If the GENERATE_XML tag is set to YES Doxygen will # generate an XML file that captures the structure of # the code including all documentation. GENERATE_XML = NO # The XML_OUTPUT tag is used to specify where the XML pages will be put. # If a relative path is entered the value of OUTPUT_DIRECTORY will be # put in front of it. If left blank `xml' will be used as the default path. XML_OUTPUT = xml # The XML_SCHEMA tag can be used to specify an XML schema, # which can be used by a validating XML parser to check the # syntax of the XML files. XML_SCHEMA = # The XML_DTD tag can be used to specify an XML DTD, # which can be used by a validating XML parser to check the # syntax of the XML files. XML_DTD = # If the XML_PROGRAMLISTING tag is set to YES Doxygen will # dump the program listings (including syntax highlighting # and cross-referencing information) to the XML output. Note that # enabling this will significantly increase the size of the XML output. XML_PROGRAMLISTING = YES #--------------------------------------------------------------------------- # configuration options for the AutoGen Definitions output #--------------------------------------------------------------------------- # If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will # generate an AutoGen Definitions (see autogen.sf.net) file # that captures the structure of the code including all # documentation. Note that this feature is still experimental # and incomplete at the moment. GENERATE_AUTOGEN_DEF = NO #--------------------------------------------------------------------------- # configuration options related to the Perl module output #--------------------------------------------------------------------------- # If the GENERATE_PERLMOD tag is set to YES Doxygen will # generate a Perl module file that captures the structure of # the code including all documentation. Note that this # feature is still experimental and incomplete at the # moment. GENERATE_PERLMOD = NO # If the PERLMOD_LATEX tag is set to YES Doxygen will generate # the necessary Makefile rules, Perl scripts and LaTeX code to be able # to generate PDF and DVI output from the Perl module output. PERLMOD_LATEX = NO # If the PERLMOD_PRETTY tag is set to YES the Perl module output will be # nicely formatted so it can be parsed by a human reader. # This is useful # if you want to understand what is going on. # On the other hand, if this # tag is set to NO the size of the Perl module output will be much smaller # and Perl will parse it just the same. PERLMOD_PRETTY = YES # The names of the make variables in the generated doxyrules.make file # are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. # This is useful so different doxyrules.make files included by the same # Makefile don't overwrite each other's variables. PERLMOD_MAKEVAR_PREFIX = #--------------------------------------------------------------------------- # Configuration options related to the preprocessor #--------------------------------------------------------------------------- # If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will # evaluate all C-preprocessor directives found in the sources and include # files. ENABLE_PREPROCESSING = YES # If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro # names in the source code. If set to NO (the default) only conditional # compilation will be performed. Macro expansion can be done in a controlled # way by setting EXPAND_ONLY_PREDEF to YES. MACRO_EXPANSION = YES # If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES # then the macro expansion is limited to the macros specified with the # PREDEFINED and EXPAND_AS_DEFINED tags. EXPAND_ONLY_PREDEF = YES # If the SEARCH_INCLUDES tag is set to YES (the default) the includes files # pointed to by INCLUDE_PATH will be searched when a #include is found. SEARCH_INCLUDES = YES # The INCLUDE_PATH tag can be used to specify one or more directories that # contain include files that are not input files but should be processed by # the preprocessor. INCLUDE_PATH = # You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard # patterns (like *.h and *.hpp) to filter out the header-files in the # directories. If left blank, the patterns specified with FILE_PATTERNS will # be used. INCLUDE_FILE_PATTERNS = # The PREDEFINED tag can be used to specify one or more macro names that # are defined before the preprocessor is started (similar to the -D option of # gcc). The argument of the tag is a list of macros of the form: name # or name=definition (no spaces). If the definition and the = are # omitted =1 is assumed. To prevent a macro definition from being # undefined via #undef or recursively expanded use the := operator # instead of the = operator. PREDEFINED = __attribute__(x)= BEGIN_DECLS END_DECLS # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then # this tag can be used to specify a list of macro names that should be expanded. # The macro definition that is found in the sources will be used. # Use the PREDEFINED tag if you want to use a different macro definition that # overrules the definition found in the source code. EXPAND_AS_DEFINED = # If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then # doxygen's preprocessor will remove all references to function-like macros # that are alone on a line, have an all uppercase name, and do not end with a # semicolon, because these will confuse the parser if not removed. SKIP_FUNCTION_MACROS = YES #--------------------------------------------------------------------------- # Configuration::additions related to external references #--------------------------------------------------------------------------- # The TAGFILES option can be used to specify one or more tagfiles. For each # tag file the location of the external documentation should be added. The # format of a tag file without this location is as follows: # # TAGFILES = file1 file2 ... # Adding location for the tag files is done as follows: # # TAGFILES = file1=loc1 "file2 = loc2" ... # where "loc1" and "loc2" can be relative or absolute paths # or URLs. Note that each tag file must have a unique name (where the name does # NOT include the path). If a tag file is not located in the directory in which # doxygen is run, you must also specify the path to the tagfile here. TAGFILES = # When a file name is specified after GENERATE_TAGFILE, doxygen will create # a tag file that is based on the input files it reads. GENERATE_TAGFILE = # If the ALLEXTERNALS tag is set to YES all external classes will be listed # in the class index. If set to NO only the inherited external classes # will be listed. ALLEXTERNALS = NO # If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed # in the modules index. If set to NO, only the current project's groups will # be listed. EXTERNAL_GROUPS = NO # The PERL_PATH should be the absolute path and name of the perl script # interpreter (i.e. the result of `which perl'). PERL_PATH = /usr/bin/perl #--------------------------------------------------------------------------- # Configuration options related to the dot tool #--------------------------------------------------------------------------- # If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will # generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base # or super classes. Setting the tag to NO turns the diagrams off. Note that # this option also works with HAVE_DOT disabled, but it is recommended to # install and use dot, since it yields more powerful graphs. CLASS_DIAGRAMS = YES # You can define message sequence charts within doxygen comments using the \msc # command. Doxygen will then run the mscgen tool (see # http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the # documentation. The MSCGEN_PATH tag allows you to specify the directory where # the mscgen tool resides. If left empty the tool is assumed to be found in the # default search path. MSCGEN_PATH = # If set to YES, the inheritance and collaboration graphs will hide # inheritance and usage relations if the target is undocumented # or is not a class. HIDE_UNDOC_RELATIONS = YES # If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is # available from the path. This tool is part of Graphviz, a graph visualization # toolkit from AT&T and Lucent Bell Labs. The other options in this section # have no effect if this option is set to NO (the default) HAVE_DOT = YES # The DOT_NUM_THREADS specifies the number of dot invocations doxygen is # allowed to run in parallel. When set to 0 (the default) doxygen will # base this on the number of processors available in the system. You can set it # explicitly to a value larger than 0 to get control over the balance # between CPU load and processing speed. DOT_NUM_THREADS = 0 # By default doxygen will use the Helvetica font for all dot files that # doxygen generates. When you want a differently looking font you can specify # the font name using DOT_FONTNAME. You need to make sure dot is able to find # the font, which can be done by putting it in a standard location or by setting # the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the # directory containing the font. DOT_FONTNAME = Helvetica # The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. # The default size is 10pt. DOT_FONTSIZE = 10 # By default doxygen will tell dot to use the Helvetica font. # If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to # set the path where dot can find it. DOT_FONTPATH = # If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen # will generate a graph for each documented class showing the direct and # indirect inheritance relations. Setting this tag to YES will force the # CLASS_DIAGRAMS tag to NO. CLASS_GRAPH = YES # If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen # will generate a graph for each documented class showing the direct and # indirect implementation dependencies (inheritance, containment, and # class references variables) of the class with other documented classes. COLLABORATION_GRAPH = YES # If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen # will generate a graph for groups, showing the direct groups dependencies GROUP_GRAPHS = YES # If the UML_LOOK tag is set to YES doxygen will generate inheritance and # collaboration diagrams in a style similar to the OMG's Unified Modeling # Language. UML_LOOK = NO # If the UML_LOOK tag is enabled, the fields and methods are shown inside # the class node. If there are many fields or methods and many nodes the # graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS # threshold limits the number of items for each type to make the size more # managable. Set this to 0 for no limit. Note that the threshold may be # exceeded by 50% before the limit is enforced. UML_LIMIT_NUM_FIELDS = 10 # If set to YES, the inheritance and collaboration graphs will show the # relations between templates and their instances. TEMPLATE_RELATIONS = NO # If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT # tags are set to YES then doxygen will generate a graph for each documented # file showing the direct and indirect include dependencies of the file with # other documented files. INCLUDE_GRAPH = YES # If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and # HAVE_DOT tags are set to YES then doxygen will generate a graph for each # documented header file showing the documented files that directly or # indirectly include this file. INCLUDED_BY_GRAPH = YES # If the CALL_GRAPH and HAVE_DOT options are set to YES then # doxygen will generate a call dependency graph for every global function # or class method. Note that enabling this option will significantly increase # the time of a run. So in most cases it will be better to enable call graphs # for selected functions only using the \callgraph command. CALL_GRAPH = YES # If the CALLER_GRAPH and HAVE_DOT tags are set to YES then # doxygen will generate a caller dependency graph for every global function # or class method. Note that enabling this option will significantly increase # the time of a run. So in most cases it will be better to enable caller # graphs for selected functions only using the \callergraph command. CALLER_GRAPH = YES # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen # will generate a graphical hierarchy of all classes instead of a textual one. GRAPHICAL_HIERARCHY = YES # If the DIRECTORY_GRAPH and HAVE_DOT tags are set to YES # then doxygen will show the dependencies a directory has on other directories # in a graphical way. The dependency relations are determined by the #include # relations between the files in the directories. DIRECTORY_GRAPH = YES # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images # generated by dot. Possible values are svg, png, jpg, or gif. # If left blank png will be used. If you choose svg you need to set # HTML_FILE_EXTENSION to xhtml in order to make the SVG files # visible in IE 9+ (other browsers do not have this requirement). DOT_IMAGE_FORMAT = png # If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to # enable generation of interactive SVG images that allow zooming and panning. # Note that this requires a modern browser other than Internet Explorer. # Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you # need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files # visible. Older versions of IE do not have SVG support. INTERACTIVE_SVG = NO # The tag DOT_PATH can be used to specify the path where the dot tool can be # found. If left blank, it is assumed the dot tool can be found in the path. DOT_PATH = # The DOTFILE_DIRS tag can be used to specify one or more directories that # contain dot files that are included in the documentation (see the # \dotfile command). DOTFILE_DIRS = # The MSCFILE_DIRS tag can be used to specify one or more directories that # contain msc files that are included in the documentation (see the # \mscfile command). MSCFILE_DIRS = # The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of # nodes that will be shown in the graph. If the number of nodes in a graph # becomes larger than this value, doxygen will truncate the graph, which is # visualized by representing a node as a red box. Note that doxygen if the # number of direct children of the root node in a graph is already larger than # DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note # that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. DOT_GRAPH_MAX_NODES = 50 # The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the # graphs generated by dot. A depth value of 3 means that only nodes reachable # from the root by following a path via at most 3 edges will be shown. Nodes # that lay further from the root node will be omitted. Note that setting this # option to 1 or 2 may greatly reduce the computation time needed for large # code bases. Also note that the size of a graph can be further restricted by # DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. MAX_DOT_GRAPH_DEPTH = 0 # Set the DOT_TRANSPARENT tag to YES to generate images with a transparent # background. This is disabled by default, because dot on Windows does not # seem to support this out of the box. Warning: Depending on the platform used, # enabling this option may lead to badly anti-aliased labels on the edges of # a graph (i.e. they become hard to read). DOT_TRANSPARENT = NO # Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output # files in one run (i.e. multiple -o and -T options on the command line). This # makes dot run faster, but since only newer versions of dot (>1.8.10) # support this, this feature is disabled by default. DOT_MULTI_TARGETS = YES # If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will # generate a legend page explaining the meaning of the various boxes and # arrows in the dot generated graphs. GENERATE_LEGEND = YES # If the DOT_CLEANUP tag is set to YES (the default) Doxygen will # remove the intermediate dot files that are used to generate # the various graphs. DOT_CLEANUP = YES hackrf-0.0~git20230104.cfc2f34/doc/DoxygenLayout.xml000066400000000000000000000153771435536612600216100ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/HACKING000066400000000000000000000077571435536612600172450ustar00rootroot00000000000000libopencm3 Documentation 12 October 2012 (C) K Sarkies ----------------------------- Each family and subfamily of devices has a separate directory and configuration files. Doxygen is run independently on each of these and the result is integrated under a single HTML page. LaTeX and pdf files are produced separately. Due to relative referencing used in the files, the directory structure is important and should be maintained. Each of the subdirectories has a configuration file, a layout file and subdirectories for the documentation. Doxygen is intended to be run inside these subdirectories. The Makefile will handle this in the appropriate order. Tag files are generated and used by other doxygen runs to resolve links. Tagfiles -------- Tagfiles contain all information about the document, and are used to resolve references in other documents. The groups defined in these external documents are not shown when EXTERNAL_GROUPS = NO. The high level tagfiles must be generated before any others so order is important. As well as the processor families, a "cm3" subdirectory is used to generate a tagfile to integrate the CM3 common core defines. Markup ------ Each family has been given a group name that will allow subgrouping of API functions and defines in the documentation. The header and source files for each peripheral in each family must have a heading section in which an @defgroup defines the group name for the particular peripheral. This group name will be the same across all families as each one is documented separately. Thus for a peripheral xxx the header will have a group name xxx_defines and the source file will have xxx_file. This will allow the group to appear separately. An @ingroup must be provided to place the group as a subgroup of the appropriate family grouping. Note that @file is not used. The heading section must include the version number and date and authors names plus a license reference. Any documentation specific to the family can be included here. If there are common files included then their documentation will appear in a separate section. Common header and source files that are included into a number of families must have an @addgroup to include its documentation into the appropriate peripheral group. These headings may include authors and any specific descriptions but the date and version number must be omitted as it will be included from the family files. There must not be any reference to family groupings as these common files will be incorporated into multiple family groups. Each helper function must have a header with an @brief, and where appropriate additional description, @parameter and @return elements. These latter must describe the allowable parameter ranges preferably with reference to a suitable define in the corresponding header file. The Doxyfile for a family must include input files from the header and source subdirectories, as well as all needed common files. The common files can be added separately or as an entire directory with exclusions of inappropriate files. Doxyfiles --------- Doxyfile_common holds global settings. OUTPUT_DIRECTORY blank so that the output is placed in the current directory. RECURSIVE = NO EXTERNAL_GROUPS = NO Each Doxyfile_include for a processor family has: @INCLUDE = ../Doxyfile_common INPUT = specific directories needed, including /include/libopencm3/cm3 in top directory to set the top level page and GNU license. LAYOUT_FILE = DoxygenLayout_$processor.xml WARN_LOGFILE = doxygen_$processor.log TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = $processor.tag PREDEFINED = list of macro definitions For the top level Doxyfile INPUT = ../include/libopencm3/docmain.dox to add in the main page text LAYOUT_FILE = DoxygenLayout.xml WARN_LOGFILE = doxygen.log TAGFILES = cm3/cm3.tag=../cm3/html plus all families to be included. Generation of PDF ----------------- The needs for pdf documents differ from HTML so separate Doxyfile_latex files are provided. @INCLUDE = ../Doxyfile_common GENERATE_LATEX = YES GENERATE_HTML = NO hackrf-0.0~git20230104.cfc2f34/doc/Makefile000066400000000000000000000051661435536612600177060ustar00rootroot00000000000000# Makefile to build libopencm3 documentation # 14 September 2012 # (C) Ken Sarkies doc: html latex html: cm3 usb stm32l1 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 efm32g efm32gg efm32lg efm32tg lm3s lm4f lpc13 lpc17 lpc43 top cm3: cd cm3/; doxygen usb: cd usb/; doxygen lm3s: cd lm3s/; doxygen lm4f: cd lm4f/; doxygen efm32g: cd efm32g/; doxygen efm32gg: cd efm32gg/; doxygen efm32lg: cd efm32lg/; doxygen efm32tg: cd efm32tg/; doxygen lpc13: cd lpc13xx/; doxygen lpc17: cd lpc17xx/; doxygen lpc43: cd lpc43xx/; doxygen stm32f0: cd stm32f0/; doxygen stm32f1: cd stm32f1/; doxygen stm32f2: cd stm32f2/; doxygen stm32f3: cd stm32f3/; doxygen stm32f4: cd stm32f4/; doxygen stm32l1: cd stm32l1/; doxygen top: doxygen latex: stm32l1.pdf stm32f0.pdf stm32f1.pdf stm32f2.pdf stm32f3.pdf stm32f4.pdf lm3s.pdf lm4f.pdf lpc13.pdf lpc17.pdf lpc43.pdf efm32g.pdf efm32gg.pdf efm32lg.pdf efm32tg.pdf stm32l1.pdf: cd stm32l1/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32l1.pdf stm32f0.pdf: cd stm32f0/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f0.pdf stm32f1.pdf: cd stm32f1/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f1.pdf stm32f2.pdf: cd stm32f2/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f2.pdf stm32f3.pdf: cd stm32f3/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f3.pdf stm32f4.pdf: cd stm32f4/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f4.pdf lm3s.pdf: cd lm3s/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lm3s.pdf lm4f.pdf: cd lm4f/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lm4f.pdf lpc13.pdf: cd lpc13xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc13.pdf lpc17.pdf: cd lpc17xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc17.pdf lpc43.pdf: cd lpc43xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc43.pdf efm32g.pdf: cd efm32g/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32g.pdf efm32gg.pdf: cd efm32gg/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32gg.pdf efm32lg.pdf: cd efm32lg/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32lg.pdf efm32tg.pdf: cd efm32tg/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32tg.pdf clean: @rm -rf html/ */html/ */latex/ *.pdf */*.tag .PHONY: doc html cm3 usb lm3s lm4f lpc13 lpc17 lpc43 stm32l1 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 efm32g efm32gg efm32lg efm32tg top latex hackrf-0.0~git20230104.cfc2f34/doc/README000066400000000000000000000015221435536612600171160ustar00rootroot00000000000000libopencm3 Documentation 14 September 2012 (C) K Sarkies ------------------------------- To generate all documentation run 'make doc' in the doc directory, or for html documentation only run 'make html' (much faster). This runs doxygen for each of the processor families then integrates the whole. Alternatively run 'make doc' in the top directory to make html documentation. LaTeX and pdf documentation is currently very large in size. This requires doxygen v 1.8.2 or later. HTML, LaTeX, and pdf output can be produced. Generation of HTML ------------------ To view HTML, point a browser to libopencm3/doc/html/index.html. Generation of PDF ----------------- The pdf is generated via LaTeX. The pdf files are placed in the doc directory. Each file contains all documentation for the core and common features. The resulting files are huge. hackrf-0.0~git20230104.cfc2f34/doc/cm3/000077500000000000000000000000001435536612600167205ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/cm3/Doxyfile000066400000000000000000000013101435536612600204210ustar00rootroot00000000000000# HTML Documentation for CM3 Core features. # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_cm3.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/cm3/ LAYOUT_FILE = DoxygenLayout_cm3.xml GENERATE_TAGFILE = cm3.tag hackrf-0.0~git20230104.cfc2f34/doc/cm3/DoxygenLayout_cm3.xml000066400000000000000000000162221435536612600230220ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/efm32g/000077500000000000000000000000001435536612600173215ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/efm32g/Doxyfile000066400000000000000000000016041435536612600210300ustar00rootroot00000000000000# HTML Documentation for efm32 code level # 11 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32g.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32g \ ../../lib/efm32/efm32g EXCLUDE = LAYOUT_FILE = DoxygenLayout_efm32g.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html \ GENERATE_TAGFILE = efm32g.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/efm32g/Doxyfile_latex000066400000000000000000000017271435536612600222330ustar00rootroot00000000000000# LaTeX Documentation for efm32 code level # 12 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32g_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32g \ ../../lib/efm32/efm32g EXCLUDE = ../../include/libopencm3/efm32/doc-efm32g.h LAYOUT_FILE = DoxygenLayout_efm32g.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_efm32g.tex hackrf-0.0~git20230104.cfc2f34/doc/efm32g/DoxygenLayout_efm32g.xml000066400000000000000000000164761435536612600240370ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/efm32g/header_efm32g.tex000066400000000000000000000030621435536612600224370ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ EFM32 Gecko ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/efm32gg/000077500000000000000000000000001435536612600174705ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/efm32gg/Doxyfile000066400000000000000000000016111435536612600211750ustar00rootroot00000000000000# HTML Documentation for efm32 code level # 11 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32gg.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32gg \ ../../lib/efm32/efm32gg EXCLUDE = LAYOUT_FILE = DoxygenLayout_efm32gg.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html \ GENERATE_TAGFILE = efm32gg.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/efm32gg/Doxyfile_latex000066400000000000000000000017351435536612600224010ustar00rootroot00000000000000# LaTeX Documentation for efm32 code level # 12 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32gg_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32gg \ ../../lib/efm32/efm32gg EXCLUDE = ../../include/libopencm3/efm32/doc-efm32gg.h LAYOUT_FILE = DoxygenLayout_efm32gg.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_efm32gg.tex hackrf-0.0~git20230104.cfc2f34/doc/efm32gg/DoxygenLayout_efm32gg.xml000066400000000000000000000164751435536612600243540ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/efm32gg/header_efm32gg.tex000066400000000000000000000030701435536612600227540ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ EFM32 Giant Gecko ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/efm32lg/000077500000000000000000000000001435536612600174755ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/efm32lg/Doxyfile000066400000000000000000000016111435536612600212020ustar00rootroot00000000000000# HTML Documentation for efm32 code level # 11 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32lg.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32lg \ ../../lib/efm32/efm32lg EXCLUDE = LAYOUT_FILE = DoxygenLayout_efm32lg.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html \ GENERATE_TAGFILE = efm32lg.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/efm32lg/Doxyfile_latex000066400000000000000000000017351435536612600224060ustar00rootroot00000000000000# LaTeX Documentation for efm32 code level # 12 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32lg_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32lg \ ../../lib/efm32/efm32lg EXCLUDE = ../../include/libopencm3/efm32/doc-efm32lg.h LAYOUT_FILE = DoxygenLayout_efm32lg.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_efm32lg.tex hackrf-0.0~git20230104.cfc2f34/doc/efm32lg/DoxygenLayout_efm32lg.xml000066400000000000000000000164751435536612600243660ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/efm32lg/header_efm32lg.tex000066400000000000000000000030721435536612600227700ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ EFM32 Leopard Gecko ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/efm32tg/000077500000000000000000000000001435536612600175055ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/efm32tg/Doxyfile000066400000000000000000000016111435536612600212120ustar00rootroot00000000000000# HTML Documentation for efm32 code level # 11 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32tg.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32tg \ ../../lib/efm32/efm32tg EXCLUDE = LAYOUT_FILE = DoxygenLayout_efm32tg.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html \ GENERATE_TAGFILE = efm32tg.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/efm32tg/Doxyfile_latex000066400000000000000000000017351435536612600224160ustar00rootroot00000000000000# LaTeX Documentation for efm32 code level # 12 November 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_efm32tg_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/efm32/efm32tg \ ../../lib/efm32/efm32tg EXCLUDE = ../../include/libopencm3/efm32/doc-efm32tg.h LAYOUT_FILE = DoxygenLayout_efm32tg.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_efm32tg.tex hackrf-0.0~git20230104.cfc2f34/doc/efm32tg/DoxygenLayout_efm32tg.xml000066400000000000000000000164751435536612600244060ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/efm32tg/header_efm32tg.tex000066400000000000000000000030671435536612600230140ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ EFM32 Tiny Gecko ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/index.html000066400000000000000000000003131435536612600202300ustar00rootroot00000000000000 Documentation index

hackrf-0.0~git20230104.cfc2f34/doc/lm3s/000077500000000000000000000000001435536612600171145ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/lm3s/Doxyfile000066400000000000000000000015141435536612600206230ustar00rootroot00000000000000# HTML Documentation for LM3S code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lm3s.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/lm3s \ ../../lib/lm3s LAYOUT_FILE = DoxygenLayout_lm3s.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = lm3s.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/lm3s/Doxyfile_latex000066400000000000000000000016541435536612600220250ustar00rootroot00000000000000# LaTeX Documentation for LM3S code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lm3s_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/lm3s \ ../../lib/lm3s EXCLUDE = ../../include/libopencm3/lm3s/doc-lm3s.h LAYOUT_FILE = DoxygenLayout_lm3s.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_lm3s.tex hackrf-0.0~git20230104.cfc2f34/doc/lm3s/DoxygenLayout_lm3s.xml000066400000000000000000000165001435536612600234110ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/lm3s/header_lm3s.tex000066400000000000000000000030561435536612600220300ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ TI LM3S ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/lm4f/000077500000000000000000000000001435536612600171005ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/lm4f/Doxyfile000066400000000000000000000015141435536612600206070ustar00rootroot00000000000000# HTML Documentation for LM3S code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lm4f.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/lm4f \ ../../lib/lm4f LAYOUT_FILE = DoxygenLayout_lm4f.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = lm4f.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/lm4f/Doxyfile_latex000066400000000000000000000017641435536612600220130ustar00rootroot00000000000000# LaTeX Documentation for LM3S code level # 14 September 2012 # Copyright (C) Ken Sarkies # Copyright (C) 2012 Alexandru Gagniuc #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lm4f_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/lm4f \ ../../lib/lm4f EXCLUDE = ../../include/libopencm3/lm4f/doc-lm4f.h LAYOUT_FILE = DoxygenLayout_lm4f.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_lm4f.tex hackrf-0.0~git20230104.cfc2f34/doc/lm4f/DoxygenLayout_lm4f.xml000066400000000000000000000165001435536612600233610ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/lm4f/header_lm4f.tex000066400000000000000000000030561435536612600220000ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ TI LM4f ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/lpc13xx/000077500000000000000000000000001435536612600175405ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/lpc13xx/Doxyfile000066400000000000000000000015361435536612600212530ustar00rootroot00000000000000# HTML Documentation for LPC13xx code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lpc13xx.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/lpc13xx \ ../../lib/lpc13xx LAYOUT_FILE = DoxygenLayout_lpc13xx.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = lpc13xx.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/lpc13xx/Doxyfile_latex000066400000000000000000000017051435536612600224460ustar00rootroot00000000000000# LaTeX Documentation for LPC13xx code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lpc13xx_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/lpc13xx/ \ ../../lib/lpc13xx EXCLUDE = ../../include/libopencm3/lpc13xx/doc-lpc13xx.h LAYOUT_FILE = DoxygenLayout_lpc13xx.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_lpc13xx.tex hackrf-0.0~git20230104.cfc2f34/doc/lpc13xx/DoxygenLayout_lpc13xx.xml000066400000000000000000000163311435536612600244630ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/lpc13xx/header_lpc13xx.tex000066400000000000000000000030621435536612600230750ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ NXP LPC13xx ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/lpc17xx/000077500000000000000000000000001435536612600175445ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/lpc17xx/Doxyfile000066400000000000000000000015361435536612600212570ustar00rootroot00000000000000# HTML Documentation for LPC17xx code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lpc17xx.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/lpc17xx \ ../../lib/lpc17xx LAYOUT_FILE = DoxygenLayout_lpc17xx.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = lpc17xx.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/lpc17xx/Doxyfile_latex000066400000000000000000000017051435536612600224520ustar00rootroot00000000000000# LaTeX Documentation for LPC17xx code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lpc17xx_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/lpc17xx/ \ ../../lib/lpc17xx EXCLUDE = ../../include/libopencm3/lpc17xx/doc-lpc17xx.h LAYOUT_FILE = DoxygenLayout_lpc17xx.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_lpc17xx.tex hackrf-0.0~git20230104.cfc2f34/doc/lpc17xx/DoxygenLayout_lpc17xx.xml000066400000000000000000000163311435536612600244730ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/lpc17xx/header_lpc17xx.tex000066400000000000000000000030621435536612600231050ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ NXP LPC17xx ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/lpc43xx/000077500000000000000000000000001435536612600175435ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/lpc43xx/Doxyfile000066400000000000000000000015361435536612600212560ustar00rootroot00000000000000# HTML Documentation for LPC43xx code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lpc43xx.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/lpc43xx \ ../../lib/lpc43xx LAYOUT_FILE = DoxygenLayout_lpc43xx.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = lpc43xx.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/lpc43xx/Doxyfile_latex000066400000000000000000000017051435536612600224510ustar00rootroot00000000000000# LaTeX Documentation for LPC43xx code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_lpc43xx_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/lpc43xx/ \ ../../lib/lpc43xx EXCLUDE = ../../include/libopencm3/lpc43xx/doc-lpc43xx.h LAYOUT_FILE = DoxygenLayout_lpc43xx.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_lpc43xx.tex hackrf-0.0~git20230104.cfc2f34/doc/lpc43xx/DoxygenLayout_lpc43xx.xml000066400000000000000000000163311435536612600244710ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/lpc43xx/header_lpc43xx.tex000066400000000000000000000030621435536612600231030ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ NXP LPC43xx ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/stm32f0/000077500000000000000000000000001435536612600174345ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/stm32f0/Doxyfile000066400000000000000000000022461435536612600211460ustar00rootroot00000000000000# HTML Documentation for STM32F1 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f0.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f0 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f0 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f0/usb.h \ ../../include/libopencm3/stm32/f0/usb_desc.h EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c LAYOUT_FILE = DoxygenLayout_stm32f0.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = stm32f0.tag ENABLE_PREPROCESSING = YES hackrf-0.0~git20230104.cfc2f34/doc/stm32f0/Doxyfile_latex000066400000000000000000000024121435536612600223360ustar00rootroot00000000000000# LaTeX Documentation for STM32F1 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f0_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f0 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f0 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f0/doc-stm32f0.h \ ../../include/libopencm3/stm32/f0/usb.h \ ../../include/libopencm3/stm32/f0/usb_desc.h \ ../../include/libopencm3/stm32/f0/nvic_f0.h EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c LAYOUT_FILE = DoxygenLayout_stm32f0.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_stm32f0.tex hackrf-0.0~git20230104.cfc2f34/doc/stm32f0/DoxygenLayout_stm32f0.xml000066400000000000000000000164751435536612600242640ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/stm32f0/header_stm32f0.tex000066400000000000000000000030621435536612600226650ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ STM STM32F0 ARM Cortex M0 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/stm32f0/index.html000066400000000000000000000003131435536612600214260ustar00rootroot00000000000000 Documentation index

hackrf-0.0~git20230104.cfc2f34/doc/stm32f1/000077500000000000000000000000001435536612600174355ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/stm32f1/Doxyfile000066400000000000000000000022461435536612600211470ustar00rootroot00000000000000# HTML Documentation for STM32F1 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f1.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f1 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f1 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f1/usb.h \ ../../include/libopencm3/stm32/f1/usb_desc.h EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c LAYOUT_FILE = DoxygenLayout_stm32f1.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = stm32f1.tag ENABLE_PREPROCESSING = YES hackrf-0.0~git20230104.cfc2f34/doc/stm32f1/Doxyfile_latex000066400000000000000000000024121435536612600223370ustar00rootroot00000000000000# LaTeX Documentation for STM32F1 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f1_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f1 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f1 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f1/doc-stm32f1.h \ ../../include/libopencm3/stm32/f1/usb.h \ ../../include/libopencm3/stm32/f1/usb_desc.h \ ../../include/libopencm3/stm32/f1/nvic_f1.h EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c LAYOUT_FILE = DoxygenLayout_stm32f1.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_stm32f1.tex hackrf-0.0~git20230104.cfc2f34/doc/stm32f1/DoxygenLayout_stm32f1.xml000066400000000000000000000164751435536612600242660ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/stm32f1/header_stm32f1.tex000066400000000000000000000030621435536612600226670ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ STM STM32F1 ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/stm32f1/index.html000066400000000000000000000003131435536612600214270ustar00rootroot00000000000000 Documentation index

hackrf-0.0~git20230104.cfc2f34/doc/stm32f2/000077500000000000000000000000001435536612600174365ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/stm32f2/Doxyfile000066400000000000000000000020001435536612600211340ustar00rootroot00000000000000# HTML Documentation for STM32F2 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f2.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f2 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f2 \ ../../lib/stm32/common EXCLUDE = EXCLUDE_PATTERNS = *_common_f13.h *_common_f13.c LAYOUT_FILE = DoxygenLayout_stm32f2.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = stm32f2.tag ENABLE_PREPROCESSING = YES hackrf-0.0~git20230104.cfc2f34/doc/stm32f2/Doxyfile_latex000066400000000000000000000021011435536612600223330ustar00rootroot00000000000000# LaTeX Documentation for STM32F2 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f2_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f2 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f2 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f2/doc-stm32f2.h EXCLUDE_PATTERNS = LAYOUT_FILE = DoxygenLayout_stm32f2.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_stm32f2.tex hackrf-0.0~git20230104.cfc2f34/doc/stm32f2/DoxygenLayout_stm32f2.xml000066400000000000000000000164751435536612600242700ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/stm32f2/header_stm32f2.tex000066400000000000000000000030621435536612600226710ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ STM STM32F2 ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/stm32f2/index.html000066400000000000000000000003131435536612600214300ustar00rootroot00000000000000 Documentation index

hackrf-0.0~git20230104.cfc2f34/doc/stm32f3/000077500000000000000000000000001435536612600174375ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/stm32f3/Doxyfile000066400000000000000000000023331435536612600211460ustar00rootroot00000000000000# HTML Documentation for STM32F3 code level #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f3.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f3 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f3 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f3/usb.h \ ../../include/libopencm3/stm32/f3/usb_desc.h EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c EXCLUDE_PATTERNS += *_common_f124.h *_common_f124.c EXCLUDE_PATTERNS += *_common_l1f24.h *_common_l1f24.c EXCLUDE_PATTERNS += *_common_bcd.h *_common_bcd.c LAYOUT_FILE = DoxygenLayout_stm32f3.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = stm32f3.tag ENABLE_PREPROCESSING = YES hackrf-0.0~git20230104.cfc2f34/doc/stm32f3/Doxyfile_latex000066400000000000000000000024121435536612600223410ustar00rootroot00000000000000# LaTeX Documentation for STM32F3 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f3_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f3 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f3 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f3/doc-stm32f3.h \ ../../include/libopencm3/stm32/f3/usb.h \ ../../include/libopencm3/stm32/f3/usb_desc.h \ ../../include/libopencm3/stm32/f3/nvic_f3.h EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c LAYOUT_FILE = DoxygenLayout_stm32f1.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_stm32f3.tex hackrf-0.0~git20230104.cfc2f34/doc/stm32f3/DoxygenLayout_stm32f3.xml000066400000000000000000000164751435536612600242720ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/stm32f3/header_stm32f3.tex000066400000000000000000000030621435536612600226730ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ STM STM32F3 ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/stm32f3/index.html000066400000000000000000000003131435536612600214310ustar00rootroot00000000000000 Documentation index

hackrf-0.0~git20230104.cfc2f34/doc/stm32f4/000077500000000000000000000000001435536612600174405ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/stm32f4/Doxyfile000066400000000000000000000020001435536612600211360ustar00rootroot00000000000000# HTML Documentation for STM32F4 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f4.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f4 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f4 \ ../../lib/stm32/common EXCLUDE = EXCLUDE_PATTERNS = *_common_f13.h *_common_f13.c LAYOUT_FILE = DoxygenLayout_stm32f4.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = stm32f4.tag ENABLE_PREPROCESSING = YES hackrf-0.0~git20230104.cfc2f34/doc/stm32f4/Doxyfile_latex000066400000000000000000000021041435536612600223400ustar00rootroot00000000000000# LaTeX Documentation for STM32F4 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32f4_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/f4 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/f4 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/f4/doc-stm32f4.h EXCLUDE_PATTERNS = LAYOUT_FILE = DoxygenLayout_stm32f4.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_stm32f4.tex hackrf-0.0~git20230104.cfc2f34/doc/stm32f4/DoxygenLayout_stm32f4.xml000066400000000000000000000164751435536612600242740ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/stm32f4/header_stm32f4.tex000066400000000000000000000030621435536612600226750ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ STM STM32F4 ARM Cortex M4 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/stm32f4/index.html000066400000000000000000000003131435536612600214320ustar00rootroot00000000000000 Documentation index

hackrf-0.0~git20230104.cfc2f34/doc/stm32l1/000077500000000000000000000000001435536612600174435ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/stm32l1/Doxyfile000066400000000000000000000023751435536612600211600ustar00rootroot00000000000000# HTML Documentation for STM32L1 code level # 15 December 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32l1.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/l1 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/l1 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/common/gpio_common_f24.h \ ../../include/libopencm3/stm32/common/timer_common_f24.h EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c \ ../../lib/stm32/common/timer_common_f24.c EXCLUDE_PATTERNS = LAYOUT_FILE = DoxygenLayout_stm32l1.xml TAGFILES = ../cm3/cm3.tag=../../cm3/html GENERATE_TAGFILE = stm32l1.tag ENABLE_PREPROCESSING = YES hackrf-0.0~git20230104.cfc2f34/doc/stm32l1/Doxyfile_latex000066400000000000000000000023601435536612600223470ustar00rootroot00000000000000# LaTeX Documentation for STM32L1 code level # 14 September 2012 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_stm32l1_latex.log INPUT = ../../include/libopencm3/docmain.dox \ ../../include/libopencm3/license.dox \ ../../include/libopencm3/stm32/l1 \ ../../include/libopencm3/stm32/common INPUT += ../../lib/stm32/l1 \ ../../lib/stm32/common EXCLUDE = ../../include/libopencm3/stm32/l1/doc-stm32l1.h \ ../../include/libopencm3/stm32/common/gpio_common_f24.h EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c EXCLUDE_PATTERNS = LAYOUT_FILE = DoxygenLayout_stm32l1.xml GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_stm32l1.tex hackrf-0.0~git20230104.cfc2f34/doc/stm32l1/DoxygenLayout_stm32l1.xml000066400000000000000000000164751435536612600243020ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/stm32l1/header_stm32l1.tex000066400000000000000000000030621435536612600227030ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ STM STM32L1 ARM Cortex M3 Series}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu Sep 13 2012 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/doc/stm32l1/index.html000066400000000000000000000003131435536612600214350ustar00rootroot00000000000000 Documentation index

hackrf-0.0~git20230104.cfc2f34/doc/usb/000077500000000000000000000000001435536612600170275ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/doc/usb/Doxyfile000066400000000000000000000015041435536612600205350ustar00rootroot00000000000000# HTML Documentation for USB code level # 10 March 2013 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_usb.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/usb INPUT += ../../lib/usb EXCLUDE_PATTERNS = LAYOUT_FILE = DoxygenLayout_usb.xml TAGFILES = GENERATE_TAGFILE = usb.tag ENABLE_PREPROCESSING = NO hackrf-0.0~git20230104.cfc2f34/doc/usb/Doxyfile_latex000066400000000000000000000017171435536612600217400ustar00rootroot00000000000000# LaTeX Documentation for USB code level # 10 March 2013 # (C) Ken Sarkies #--------------------------------------------------------------------------- # Common Include File #--------------------------------------------------------------------------- @INCLUDE = ../Doxyfile_common #--------------------------------------------------------------------------- # Local settings #--------------------------------------------------------------------------- WARN_LOGFILE = doxygen_usb_latex.log WARN_LOGFILE = doxygen_usb.log INPUT = ../../include/libopencm3/license.dox \ ../../include/libopencm3/usb INPUT += ../../lib/usb EXCLUDE_PATTERNS = LAYOUT_FILE = DoxygenLayout_usb.xml TAGFILES = GENERATE_TAGFILE = usb.tag ENABLE_PREPROCESSING = NO GENERATE_HTML = NO GENERATE_LATEX = YES LATEX_HEADER = header_usb.tex hackrf-0.0~git20230104.cfc2f34/doc/usb/DoxygenLayout_usb.xml000066400000000000000000000165011435536612600232400ustar00rootroot00000000000000 hackrf-0.0~git20230104.cfc2f34/doc/usb/header_usb.tex000066400000000000000000000030511435536612600216510ustar00rootroot00000000000000\documentclass{book} \usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} \usepackage{makeidx} \usepackage{natbib} \usepackage{graphicx} \usepackage{multicol} \usepackage{float} \usepackage{listings} \usepackage{color} \usepackage{ifthen} \usepackage[table]{xcolor} \usepackage{textcomp} \usepackage{alltt} \usepackage{ifpdf} \ifpdf \usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \else \usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode ]{hyperref} \usepackage{pspicture} \fi \usepackage[utf8]{inputenc} \usepackage{mathptmx} \usepackage[scaled=.90]{helvet} \usepackage{courier} \usepackage{sectsty} \usepackage{amssymb} \usepackage[titles]{tocloft} \usepackage{doxygen} \lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } \makeindex \setcounter{tocdepth}{3} \renewcommand{\footrulewidth}{0.4pt} \renewcommand{\familydefault}{\sfdefault} \hfuzz=15pt \setlength{\emergencystretch}{15pt} \hbadness=750 \tolerance=750 \begin{document} \hypersetup{pageanchor=false,citecolor=blue} \begin{titlepage} \vspace*{7cm} \begin{center} {\Huge libopencm3: API Reference\\ Cortex M3 Generic USB}\\ \vspace*{1cm} {\large Generated by Doxygen 1.8.2}\\ \vspace*{0.5cm} {\small Thu 10 March 2013 23:26:45}\\ \end{center} \end{titlepage} \pagenumbering{arabic} \hypersetup{pageanchor=true,citecolor=blue} hackrf-0.0~git20230104.cfc2f34/include/000077500000000000000000000000001435536612600171145ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/000077500000000000000000000000001435536612600211475ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/000077500000000000000000000000001435536612600216315ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/assert.h000066400000000000000000000111051435536612600233010ustar00rootroot00000000000000/** @defgroup debugging Debugging @brief Macros and functions to aid in debugging @version 1.0.0 @date 25 September 2012 Two preprocessor defines control the behavior of assertion check macros in this module. They allow the choice between generated code size and ease of debugging. If NDEBUG is defined, all assertion checks are disabled and macros do not generate any code. If CM3_ASSERT_VERBOSE is defined, information regarding the position of assertion checks will be stored in the binary, allowing for more informative error messages, but also significantly increased code size. As default assertion checks do not use this information it is only useful if the application linked with libopencm3 defines its own cm3_assert_failed_verbose() implementation. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Tomaz Solc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LIBOPENCM3_CM3_ASSERT_H #define LIBOPENCM3_CM3_ASSERT_H #include #define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1)) #ifdef NDEBUG # define cm3_assert(expr) (void)0 # define cm3_assert_not_reached() do { } while (1) #else # ifdef CM3_ASSERT_VERBOSE # define cm3_assert(expr) do { \ if (CM3_LIKELY(expr)) { \ (void)0; \ } else { \ cm3_assert_failed_verbose( \ __FILE__, __LINE__, \ __func__, #expr); \ } \ } while (0) # define cm3_assert_not_reached() \ cm3_assert_failed_verbose( \ __FILE__, __LINE__, \ __func__, 0) # else /** @brief Check if assertion is true. * * If NDEBUG macro is defined, this macro generates no code. Otherwise * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion * is false. * * The purpose of this macro is to aid in debugging libopencm3 and * applications using it. It can be used for example to check if function * arguments are within expected ranges and stop execution in case an * unexpected state is reached. * * @param expr expression to check */ # define cm3_assert(expr) do { \ if (CM3_LIKELY(expr)) { \ (void)0; \ } else { \ cm3_assert_failed(); \ } \ } while (0) /** @brief Check if unreachable code is reached. * * If NDEBUG macro is defined, this macro generates code for an infinite loop. * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if * the macro is ever reached. * * The purpose of this macro is to aid in debugging libopencm3 and * applications using it. It can be used for example to stop execution if an * unreachable portion of code is reached. */ # define cm3_assert_not_reached() cm3_assert_failed() # endif #endif BEGIN_DECLS /** @brief Called on a failed assertion. * * Halts execution in an infinite loop. This function never returns. * * Defined as a weak symbol, so applications can define their own * implementation. Usually, a custom implementation of this function should * report an error in some way (print a message to a debug console, display, * LED, ...) and halt execution or reboot the device. */ void cm3_assert_failed(void) __attribute__((__noreturn__)); /** @brief Called on a failed assertion with verbose messages enabled. * * Halts execution in an infinite loop. This function never returns. * * Defined as a weak symbol, so applications can define their own * implementation. Usually, a custom implementation of this function should * report an error in some way (print a message to a debug console, display, * LED, ...) and halt execution or reboot the device. * * @param file File name where the failed assertion occurred * @param line Line number where the failed assertion occurred * @param func Name of the function where the failed assertion occurred * @param assert_expr Expression that evaluated to false (can be NULL) */ void cm3_assert_failed_verbose(const char *file, int line, const char *func, const char *assert_expr) __attribute__((__noreturn__)); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/common.h000066400000000000000000000051551435536612600233000ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM3_COMMON_H #define LIBOPENCM3_CM3_COMMON_H #include #include /* This must be placed around external function declaration for C++ * support. */ #ifdef __cplusplus # define BEGIN_DECLS extern "C" { # define END_DECLS } #else # define BEGIN_DECLS # define END_DECLS #endif /* Full-featured deprecation attribute with fallback for older compilers. */ #ifdef __GNUC__ # if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4) # define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x))) # else # define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated)) # endif #else # define LIBOPENCM3_DEPRECATED(x) #endif /* Generic memory-mapped I/O accessor functions */ #define MMIO8(addr) (*(volatile uint8_t *)(addr)) #define MMIO16(addr) (*(volatile uint16_t *)(addr)) #define MMIO32(addr) (*(volatile uint32_t *)(addr)) #define MMIO64(addr) (*(volatile uint64_t *)(addr)) /* Generic bit-band I/O accessor functions */ #define BBIO_SRAM(addr, bit) \ MMIO8(((addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4) #define BBIO_PERIPH(addr, bit) \ MMIO8(((addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4) /* Generic bit definition */ #define BIT0 (1<<0) #define BIT1 (1<<1) #define BIT2 (1<<2) #define BIT3 (1<<3) #define BIT4 (1<<4) #define BIT5 (1<<5) #define BIT6 (1<<6) #define BIT7 (1<<7) #define BIT8 (1<<8) #define BIT9 (1<<9) #define BIT10 (1<<10) #define BIT11 (1<<11) #define BIT12 (1<<12) #define BIT13 (1<<13) #define BIT14 (1<<14) #define BIT15 (1<<15) #define BIT16 (1<<16) #define BIT17 (1<<17) #define BIT18 (1<<18) #define BIT19 (1<<19) #define BIT20 (1<<20) #define BIT21 (1<<21) #define BIT22 (1<<22) #define BIT23 (1<<23) #define BIT24 (1<<24) #define BIT25 (1<<25) #define BIT26 (1<<26) #define BIT27 (1<<27) #define BIT28 (1<<28) #define BIT29 (1<<29) #define BIT30 (1<<30) #define BIT31 (1<<31) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/cortex.h000066400000000000000000000017611435536612600233130ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Ben Gamari * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CORTEX_H #define LIBOPENCM3_CORTEX_H static inline void cm_enable_interrupts(void) { __asm__("CPSIE I\n"); } static inline void cm_disable_interrupts(void) { __asm__("CPSID I\n"); } #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/doc-cm3.h000066400000000000000000000005361435536612600232330ustar00rootroot00000000000000/** @mainpage libopencm3 Core CM3 @version 1.0.0 @date 14 September 2012 API documentation for Cortex M3 core features. LGPL License Terms @ref lgpl_license */ /** @defgroup CM3_defines CM3 Defines @brief Defined Constants and Types for Cortex M3 core features @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/fpb.h000066400000000000000000000045171435536612600225600ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM3_FPB_H #define LIBOPENCM3_CM3_FPB_H /* Cortex-M3 Flash Patch and Breakpoint (FPB) unit */ /* Those defined only on ARMv7 and above */ #if !defined(__ARM_ARCH_7M__) || !defined(__ARM_ARCH_7EM__) #error "Flash Patch and Breakpoint not available in CM0" #endif /* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */ /* --- FPB registers ------------------------------------------------------- */ /* Flash Patch Control (FPB_CTRL) */ #define FPB_CTRL MMIO32(FPB_BASE + 0) /* Flash Patch Remap (FPB_REMAP) */ #define FPB_REMAP MMIO32(FPB_BASE + 4) /* Flash Patch Comparator (FPB_COMPx) */ #define FPB_COMP (&MMIO32(FPB_BASE + 8)) /* TODO: PID, CID */ /* --- FPB_CTRL values ----------------------------------------------------- */ /* Bits [31:15]: Reserved, read as zero, writes ignored */ #define FPB_CTRL_NUM_CODE2_MASK (0x7 << 12) #define FPB_CTRL_NUM_LIT_MASK (0xf << 8) #define FPB_CTRL_NUM_CODE1_MASK (0xf << 4) /* Bits [3:2]: Reserved */ #define FPB_CTRL_KEY (1 << 1) #define FPB_CTRL_ENABLE (1 << 0) /* --- FPB_REMAP values ---------------------------------------------------- */ /* TODO */ /* --- FPB_COMPx values ---------------------------------------------------- */ #define FPB_COMP_REPLACE_REMAP (0x0 << 30) #define FPB_COMP_REPLACE_BREAK_LOWER (0x1 << 30) #define FPB_COMP_REPLACE_BREAK_UPPER (0x2 << 30) #define FPB_COMP_REPLACE_BREAK_BOTH (0x3 << 30) #define FPB_COMP_REPLACE_MASK (0x3 << 30) /* Bit 29: Reserved */ /* TODO */ /* Bit 1: Reserved */ #define FPB_COMP_ENABLE (1 << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/itm.h000066400000000000000000000053231435536612600225760ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM3_ITM_H #define LIBOPENCM3_CM3_ITM_H /* Cortex-M3 Instrumentation Trace Macrocell (ITM) */ /* Those defined only on ARMv7 and above */ #if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) #error "Instrumentation Trace Macrocell not available in CM0" #endif /* --- ITM registers ------------------------------------------------------- */ /* Stimulus Port x (ITM_STIM[x]) */ #define ITM_STIM (&MMIO32(ITM_BASE)) /* Trace Enable ports (ITM_TER[x]) */ #define ITM_TER (&MMIO32(ITM_BASE + 0xE00)) /* Trace Privilege (ITM_TPR) */ #define ITM_TPR MMIO32(ITM_BASE + 0xE40) /* Trace Control (ITM_TCR) */ #define ITM_TCR MMIO32(ITM_BASE + 0xE80) /* TODO: PID, CID */ /* --- ITM_STIM values ----------------------------------------------------- */ /* Bits 31:0 - Write to port FIFO for forwarding as software event packet */ /* Bits 31:1 - RAZ */ #define ITM_STIM_FIFOREADY (1 << 0) /* --- ITM_TER values ------------------------------------------------------ */ /* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */ /* --- ITM_TPR values ------------------------------------------------------ */ /* * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7 * 0: User access allowed to stimulus ports * 1: Privileged access only to stimulus ports */ /* --- ITM_TCR values ------------------------------------------------------ */ /* Bits 31:24 - Reserved */ #define ITM_TCR_BUSY (1 << 23) #define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16) /* Bits 15:10 - Reserved */ #define ITM_TCR_TSPRESCALE_NONE (0 << 8) #define ITM_TCR_TSPRESCALE_DIV4 (1 << 8) #define ITM_TCR_TSPRESCALE_DIV16 (2 << 8) #define ITM_TCR_TSPRESCALE_DIV64 (3 << 8) #define ITM_TCR_TSPRESCALE_MASK (3 << 8) /* Bits 7:5 - Reserved */ #define ITM_TCR_SWOENA (1 << 4) #define ITM_TCR_TXENA (1 << 3) #define ITM_TCR_SYNCENA (1 << 2) #define ITM_TCR_TSENA (1 << 1) #define ITM_TCR_ITMENA (1 << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/memorymap.h000066400000000000000000000060741435536612600240170ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM3_MEMORYMAP_H #define LIBOPENCM3_CM3_MEMORYMAP_H /* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */ /* Private peripheral bus - Internal */ #define PPBI_BASE 0xE0000000 /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* ITM: Instrumentation Trace Macrocell */ #define ITM_BASE (PPBI_BASE + 0x0000) /* DWT: Data Watchpoint and Trace unit */ #define DWT_BASE (PPBI_BASE + 0x1000) /* FPB: Flash Patch and Breakpoint unit */ #define FPB_BASE (PPBI_BASE + 0x2000) #endif /* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */ #define SCS_BASE (PPBI_BASE + 0xE000) /* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */ /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #define TPIU_BASE (PPBI_BASE + 0x40000) #endif /* --- ITM: Instrumentation Trace Macrocell --- */ /* TODO */ /* --- DWT: Data Watchpoint and Trace unit --- */ /* TODO */ /* --- FPB: Flash Patch and Breakpoint unit --- */ /* TODO */ /* --- SCS: System Control Space --- */ /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* ITR: Interrupt Type Register */ #define ITR_BASE (SCS_BASE + 0x0000) #endif /* SYS_TICK: System Timer */ #define SYS_TICK_BASE (SCS_BASE + 0x0010) /* NVIC: Nested Vector Interrupt Controller */ #define NVIC_BASE (SCS_BASE + 0x0100) /* SCB: System Control Block */ #define SCB_BASE (SCS_BASE + 0x0D00) #ifdef CM0_PLUS /* MPU: Memory protection unit */ #define MPU_BASE (SCS_BASE + 0x0D90) #endif /* Those defined only on CM0*/ #if defined(__ARM_ARCH_6M__) /* DEBUG: Debug control and configuration */ #define DEBUG_BASE (SCS_BASE + 0x0DF0) #endif /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* STE: Software Trigger Interrupt Register */ #define STIR_BASE (SCS_BASE + 0x0F00) /* ID: ID space */ #define ID_BASE (SCS_BASE + 0x0FD0) #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/mpu.h000066400000000000000000000072111435536612600226040ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM0_MPU_H #define LIBOPENCM3_CM0_MPU_H #ifndef CM0_PLUS #error "mpu is supported only on CM0+ architecture" #else #include #include /* --- SCB: Registers ------------------------------------------------------ */ #define MPU_TYPE MMIO32(MPU_BASE + 0x00) #define MPU_CTRL MMIO32(MPU_BASE + 0x04) #define MPU_RNR MMIO32(MPU_BASE + 0x08) #define MPU_RBAR MMIO32(MPU_BASE + 0x0C) #define MPU_RASR MMIO32(MPU_BASE + 0x10) /* --- MPU values ---------------------------------------------------------- */ /* --- MPU_TYPE values ----------------------------------------------------- */ #define MPU_TYPE_IREGION_LSB 16 #define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB) #define MPU_TYPE_DREGION_LSB 8 #define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB) #define MPU_TYPE_SEPARATE (1<<0) /* --- MPU_CTRL values ----------------------------------------------------- */ #define MPU_CTRL_PRIVDEFENA (1<<2) #define MPU_CTRL_HFNMIENA (1<<1) #define MPU_CTRL_ENABLE (1<<0) /* --- MPU_RNR values ------------------------------------------------------ */ #define MPU_RNR_REGION_LSB 0 #define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB) /* --- MPU_RBAR values ----------------------------------------------------- */ #define MPU_RBAR_ADDR_LSB 8 #define MPU_RBAR_ADDR (0x00FFFFFF << MPU_RBAR_REGION_LSB) #define MPU_RBAR_VALID (1<<4) #define MPU_RBAR_REGION_LSB 0 #define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB) /* --- MPU_RASR values ----------------------------------------------------- */ #define MPU_RASR_ATTRS_LSB 16 #define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB) #define MPU_RASR_SRD_LSB 8 #define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB) #define MPU_RASR_SIZE_LSB 1 #define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB) #define MPU_RASR_ENABLE (1 << 0) #define MPU_RASR_ATTR_XN (1 << 28) #define MPU_RASR_ATTR_AP (7 << 24) #define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24) #define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24) #define MPU_RASR_ATTR_AP_PRW_URO (2 << 24) #define MPU_RASR_ATTR_AP_PRW_URW (3 << 24) #define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24) #define MPU_RASR_ATTR_AP_PRO_URO (6 << 24) #define MPU_RASR_ATTR_AP_PRO_URO (7 << 24) #define MPU_RASR_ATTR_TEX (7 << 19) #define MPU_RASR_ATTR_S (1 << 18) #define MPU_RASR_ATTR_C (1 << 17) #define MPU_RASR_ATTR_B (1 << 16) #define MPU_RASR_ATTR_SCB (7 << 16) #define MPU_RASR_ATTR_SCB_SH_STRONG (0 << 16) #define MPU_RASR_ATTR_SCB_SH_DEVICE (1 << 16) #define MPU_RASR_ATTR_SCB_NSH_WT (2 << 16) #define MPU_RASR_ATTR_SCB_NSH_WB (3 << 16) #define MPU_RASR_ATTR_SCB_SH_STRONG (4 << 16) #define MPU_RASR_ATTR_SCB_SH_DEVICE (5 << 16) #define MPU_RASR_ATTR_SCB_SH_WT (6 << 16) #define MPU_RASR_ATTR_SCB_SH_WB (7 << 16) /* --- MPU functions ------------------------------------------------------- */ BEGIN_DECLS END_DECLS #endif /* CM0_PLUS */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/nvic.h000066400000000000000000000121611435536612600227420ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @defgroup CM3_nvic_defines NVIC Defines * * @brief libopencm3 Cortex Nested Vectored Interrupt Controller * * @ingroup CM3_defines * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski * * @date 18 August 2012 * * LGPL License Terms @ref lgpl_license */ /**@{*/ #ifndef LIBOPENCM3_NVIC_H #define LIBOPENCM3_NVIC_H #include #include /* --- NVIC Registers ------------------------------------------------------ */ /* ISER: Interrupt Set Enable Registers */ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \ (iser_id * 4)) /* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ /* ICER: Interrupt Clear Enable Registers */ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \ (icer_id * 4)) /* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ /* ISPR: Interrupt Set Pending Registers */ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \ (ispr_id * 4)) /* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ /* ICPR: Interrupt Clear Pending Registers */ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \ (icpr_id * 4)) /* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* IABR: Interrupt Active Bit Register */ /* Note: 8 32bit Registers */ #define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \ (iabr_id * 4)) #endif /* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ /* IPR: Interrupt Priority Registers */ /* Note: 240 8bit Registers */ /* Note: 32 8bit Registers on CM0 */ #define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \ ipr_id) #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* STIR: Software Trigger Interrupt Register */ #define NVIC_STIR MMIO32(STIR_BASE) #endif /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M0, M3 and M4 System Interrupts */ /** @defgroup nvic_sysint Cortex M0/M3/M4 System Interrupts @ingroup CM3_nvic_defines IRQ numbers -3 and -6 to -9 are reserved @{*/ #define NVIC_NMI_IRQ -14 #define NVIC_HARD_FAULT_IRQ -13 /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #define NVIC_MEM_MANAGE_IRQ -12 #define NVIC_BUS_FAULT_IRQ -11 #define NVIC_USAGE_FAULT_IRQ -10 #endif /* irq numbers -6 to -9 are reserved */ #define NVIC_SV_CALL_IRQ -5 /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #define DEBUG_MONITOR_IRQ -4 #endif /* irq number -3 reserved */ #define NVIC_PENDSV_IRQ -2 #define NVIC_SYSTICK_IRQ -1 /**@}*/ /* Note: User interrupts are family specific and are defined in a family * specific header file in the corresponding subfolder. */ #define WEAK __attribute__((weak)) #include /* --- NVIC functions ------------------------------------------------------ */ BEGIN_DECLS void nvic_enable_irq(uint8_t irqn); void nvic_disable_irq(uint8_t irqn); uint8_t nvic_get_pending_irq(uint8_t irqn); void nvic_set_pending_irq(uint8_t irqn); void nvic_clear_pending_irq(uint8_t irqn); uint8_t nvic_get_irq_enabled(uint8_t irqn); void nvic_set_priority(uint8_t irqn, uint8_t priority); /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) uint8_t nvic_get_active_irq(uint8_t irqn); void nvic_generate_software_interrupt(uint16_t irqn); #endif void WEAK reset_handler(void); void WEAK nmi_handler(void); void WEAK hard_fault_handler(void); void WEAK sv_call_handler(void); void WEAK pend_sv_handler(void); void WEAK sys_tick_handler(void); /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) void WEAK mem_manage_handler(void); void WEAK bus_fault_handler(void); void WEAK usage_fault_handler(void); void WEAK debug_monitor_handler(void); #endif END_DECLS /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/scb.h000066400000000000000000000366041435536612600225620ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SCB_H #define LIBOPENCM3_SCB_H #include #include /* --- SCB: Registers ------------------------------------------------------ */ /* CPUID: CPUID base register */ #define SCB_CPUID MMIO32(SCB_BASE + 0x00) /* ICSR: Interrupt Control State Register */ #define SCB_ICSR MMIO32(SCB_BASE + 0x04) /* VTOR: Vector Table Offset Register */ #define SCB_VTOR MMIO32(SCB_BASE + 0x08) /* AIRCR: Application Interrupt and Reset Control Register */ #define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) /* SCR: System Control Register */ #define SCB_SCR MMIO32(SCB_BASE + 0x10) /* CCR: Configuration Control Register */ #define SCB_CCR MMIO32(SCB_BASE + 0x14) /* SHP: System Handler Priority Registers */ /* Note: 12 8bit registers */ #define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) #define SCB_SHPR1 MMIO32(SCB_BASE + 0x18) #define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C) #define SCB_SHPR3 MMIO32(SCB_BASE + 0x20) /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* SHCSR: System Handler Control and State Register */ #define SCB_SHCSR MMIO32(SCB_BASE + 0x24) /* CFSR: Configurable Fault Status Registers */ #define SCB_CFSR MMIO32(SCB_BASE + 0x28) /* HFSR: Hard Fault Status Register */ #define SCB_HFSR MMIO32(SCB_BASE + 0x2C) /* DFSR: Debug Fault Status Register */ #define SCB_DFSR MMIO32(SCB_BASE + 0x30) /* MMFAR: Memory Manage Fault Address Register */ #define SCB_MMFAR MMIO32(SCB_BASE + 0x34) /* BFAR: Bus Fault Address Register */ #define SCB_BFAR MMIO32(SCB_BASE + 0x38) /* AFSR: Auxiliary Fault Status Register */ #define SCB_AFSR MMIO32(SCB_BASE + 0x3C) /* ID_PFR0: Processor Feature Register 0 */ #define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) /* ID_PFR1: Processor Feature Register 1 */ #define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) /* ID_DFR0: Debug Features Register 0 */ #define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) /* ID_AFR0: Auxiliary Features Register 0 */ #define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) /* ID_MMFR0: Memory Model Feature Register 0 */ #define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) /* ID_MMFR1: Memory Model Feature Register 1 */ #define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) /* ID_MMFR2: Memory Model Feature Register 2 */ #define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) /* ID_MMFR3: Memory Model Feature Register 3 */ #define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) /* ID_ISAR0: Instruction Set Attributes Register 0 */ #define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) /* ID_ISAR1: Instruction Set Attributes Register 1 */ #define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) /* ID_ISAR2: Instruction Set Attributes Register 2 */ #define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) /* ID_ISAR3: Instruction Set Attributes Register 3 */ #define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) /* ID_ISAR4: Instruction Set Attributes Register 4 */ #define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) /* CPACR: Coprocessor Access Control Register */ #define SCB_CPACR MMIO32(SCB_BASE + 0x88) /* FPCCR: Floating-Point Context Control Register */ #define SCB_FPCCR MMIO32(SCB_BASE + 0x234) /* FPCAR: Floating-Point Context Address Register */ #define SCB_FPCAR MMIO32(SCB_BASE + 0x238) /* FPDSCR: Floating-Point Default Status Control Register */ #define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) /* MVFR0: Media and Floating-Point Feature Register 0 */ #define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) /* MVFR1: Media and Floating-Point Feature Register 1 */ #define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) #endif /* --- SCB values ---------------------------------------------------------- */ /* --- SCB_CPUID values ---------------------------------------------------- */ /* Implementer[31:24]: Implementer code */ #define SCB_CPUID_IMPLEMENTER_LSB 24 #define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB) /* Variant[23:20]: Variant number */ #define SCB_CPUID_VARIANT_LSB 20 #define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB) /* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */ /* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */ #define SCB_CPUID_CONSTANT_LSB 16 #define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB) #define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB) #define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB) /* PartNo[15:4]: Part number of the processor */ #define SCB_CPUID_PARTNO_LSB 4 #define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB) /* Revision[3:0]: Revision number */ #define SCB_CPUID_REVISION_LSB 0 #define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB) /* --- SCB_ICSR values ----------------------------------------------------- */ /* NMIPENDSET: NMI set-pending bit */ #define SCB_ICSR_NMIPENDSET (1 << 31) /* Bits [30:29]: reserved - must be kept cleared */ /* PENDSVSET: PendSV set-pending bit */ #define SCB_ICSR_PENDSVSET (1 << 28) /* PENDSVCLR: PendSV clear-pending bit */ #define SCB_ICSR_PENDSVCLR (1 << 27) /* PENDSTSET: SysTick exception set-pending bit */ #define SCB_ICSR_PENDSTSET (1 << 26) /* PENDSTCLR: SysTick exception clear-pending bit */ #define SCB_ICSR_PENDSTCLR (1 << 25) /* Bit 24: reserved - must be kept cleared */ /* Bit 23: reserved for debug - reads as 0 when not in debug mode */ #define SCB_ICSR_ISRPREEMPT (1 << 23) /* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ #define SCB_ICSR_ISRPENDING (1 << 22) /* VECTPENDING[21:12] Pending vector */ #define SCB_ICSR_VECTPENDING_LSB 12 #define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB) /* RETOBASE: Return to base level */ #define SCB_ICSR_RETOBASE (1 << 11) /* Bits [10:9]: reserved - must be kept cleared */ /* VECTACTIVE[8:0] Active vector */ #define SCB_ICSR_VECTACTIVE_LSB 0 #define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB) /* --- SCB_VTOR values ----------------------------------------------------- */ /* IMPLEMENTATION DEFINED */ #if defined(__ARM_ARCH_6M__) #define SCB_VTOR_TBLOFF_LSB 7 #define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB) #elif defined(CM1) /* VTOR not defined there */ #elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* Bits [31:30]: reserved - must be kept cleared */ /* TBLOFF[29:9]: Vector table base offset field */ /* inconsistent datasheet - LSB could be 11 */ /* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */ #define SCB_VTOR_TBLOFF_LSB 9 #define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB) #endif /* --- SCB_AIRCR values ---------------------------------------------------- */ /* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ #define SCB_AIRCR_VECTKEYSTAT_LSB 16 #define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB) #define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB) /* ENDIANESS Data endianness bit */ #define SCB_AIRCR_ENDIANESS (1 << 15) /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* Bits [14:11]: reserved - must be kept cleared */ /* PRIGROUP[10:8]: Interrupt priority grouping field */ #define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) #define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) #define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) #define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) #define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) #define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) #define SCB_AIRCR_PRIGROUP_SHIFT 8 /* Bits [7:3]: reserved - must be kept cleared */ #endif /* SYSRESETREQ System reset request */ #define SCB_AIRCR_SYSRESETREQ (1 << 2) /* VECTCLRACTIVE */ #define SCB_AIRCR_VECTCLRACTIVE (1 << 1) /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* VECTRESET */ #define SCB_AIRCR_VECTRESET (1 << 0) #endif /* --- SCB_SCR values ------------------------------------------------------ */ /* Bits [31:5]: reserved - must be kept cleared */ /* SEVEONPEND Send Event on Pending bit */ #define SCB_SCR_SEVEONPEND (1 << 4) /* Bit 3: reserved - must be kept cleared */ /* SLEEPDEEP */ #define SCB_SCR_SLEEPDEEP (1 << 2) /* SLEEPONEXIT */ #define SCB_SCR_SLEEPONEXIT (1 << 1) /* Bit 0: reserved - must be kept cleared */ /* --- SCB_CCR values ------------------------------------------------------ */ /* Bits [31:10]: reserved - must be kept cleared */ /* STKALIGN */ #define SCB_CCR_STKALIGN (1 << 9) /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* BFHFNMIGN */ #define SCB_CCR_BFHFNMIGN (1 << 8) /* Bits [7:5]: reserved - must be kept cleared */ /* DIV_0_TRP */ #define SCB_CCR_DIV_0_TRP (1 << 4) #endif /* UNALIGN_TRP */ #define SCB_CCR_UNALIGN_TRP (1 << 3) /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* Bit 2: reserved - must be kept cleared */ /* USERSETMPEND */ #define SCB_CCR_USERSETMPEND (1 << 1) /* NONBASETHRDENA */ #define SCB_CCR_NONBASETHRDENA (1 << 0) #endif /* These numbers are designed to be used with the SCB_SHPR() macro */ /* SCB_SHPR1 */ #define SCB_SHPR_PRI_4_MEMMANAGE 0 #define SCB_SHPR_PRI_5_BUSFAULT 1 #define SCB_SHPR_PRI_6_USAGEFAULT 2 #define SCB_SHPR_PRI_7_RESERVED 3 /* SCB_SHPR2 */ #define SCB_SHPR_PRI_8_RESERVED 4 #define SCB_SHPR_PRI_9_RESERVED 5 #define SCB_SHPR_PRI_10_RESERVED 6 #define SCB_SHPR_PRI_11_SVCALL 7 /* SCB_SHPR3 */ #define SCB_SHPR_PRI_12_RESERVED 8 #define SCB_SHPR_PRI_13_RESERVED 9 #define SCB_SHPR_PRI_14_PENDSV 10 #define SCB_SHPR_PRI_15_SYSTICK 11 /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* --- SCB_SHCSR values ---------------------------------------------------- */ /* Bits [31:19]: reserved - must be kept cleared */ /* USGFAULTENA: Usage fault enable */ #define SCB_SHCSR_USGFAULTENA (1 << 18) /* BUSFAULTENA: Bus fault enable */ #define SCB_SHCSR_BUSFAULTENA (1 << 17) /* MEMFAULTENA: Memory management fault enable */ #define SCB_SHCSR_MEMFAULTENA (1 << 16) /* SVCALLPENDED: SVC call pending */ #define SCB_SHCSR_SVCALLPENDED (1 << 15) /* BUSFAULTPENDED: Bus fault exception pending */ #define SCB_SHCSR_BUSFAULTPENDED (1 << 14) /* MEMFAULTPENDED: Memory management fault exception pending */ #define SCB_SHCSR_MEMFAULTPENDED (1 << 13) /* USGFAULTPENDED: Usage fault exception pending */ #define SCB_SHCSR_USGFAULTPENDED (1 << 12) /* SYSTICKACT: SysTick exception active */ #define SCB_SHCSR_SYSTICKACT (1 << 11) /* PENDSVACT: PendSV exception active */ #define SCB_SHCSR_PENDSVACT (1 << 10) /* Bit 9: reserved - must be kept cleared */ /* MONITORACT: Debug monitor active */ #define SCB_SHCSR_MONITORACT (1 << 8) /* SVCALLACT: SVC call active */ #define SCB_SHCSR_SVCALLACT (1 << 7) /* Bits [6:4]: reserved - must be kept cleared */ /* USGFAULTACT: Usage fault exception active */ #define SCB_SHCSR_USGFAULTACT (1 << 3) /* Bit 2: reserved - must be kept cleared */ /* BUSFAULTACT: Bus fault exception active */ #define SCB_SHCSR_BUSFAULTACT (1 << 1) /* MEMFAULTACT: Memory management fault exception active */ #define SCB_SHCSR_MEMFAULTACT (1 << 0) /* --- SCB_CFSR values ----------------------------------------------------- */ /* Bits [31:26]: reserved - must be kept cleared */ /* DIVBYZERO: Divide by zero usage fault */ #define SCB_CFSR_DIVBYZERO (1 << 25) /* UNALIGNED: Unaligned access usage fault */ #define SCB_CFSR_UNALIGNED (1 << 24) /* Bits [23:20]: reserved - must be kept cleared */ /* NOCP: No coprocessor usage fault */ #define SCB_CFSR_NOCP (1 << 19) /* INVPC: Invalid PC load usage fault */ #define SCB_CFSR_INVPC (1 << 18) /* INVSTATE: Invalid state usage fault */ #define SCB_CFSR_INVSTATE (1 << 17) /* UNDEFINSTR: Undefined instruction usage fault */ #define SCB_CFSR_UNDEFINSTR (1 << 16) /* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ #define SCB_CFSR_BFARVALID (1 << 15) /* Bits [14:13]: reserved - must be kept cleared */ /* STKERR: Bus fault on stacking for exception entry */ #define SCB_CFSR_STKERR (1 << 12) /* UNSTKERR: Bus fault on unstacking for a return from exception */ #define SCB_CFSR_UNSTKERR (1 << 11) /* IMPRECISERR: Imprecise data bus error */ #define SCB_CFSR_IMPRECISERR (1 << 10) /* PRECISERR: Precise data bus error */ #define SCB_CFSR_PRECISERR (1 << 9) /* IBUSERR: Instruction bus error */ #define SCB_CFSR_IBUSERR (1 << 8) /* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ #define SCB_CFSR_MMARVALID (1 << 7) /* Bits [6:5]: reserved - must be kept cleared */ /* MSTKERR: Memory manager fault on stacking for exception entry */ #define SCB_CFSR_MSTKERR (1 << 4) /* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ #define SCB_CFSR_MUNSTKERR (1 << 3) /* Bit 2: reserved - must be kept cleared */ /* DACCVIOL: Data access violation flag */ #define SCB_CFSR_DACCVIOL (1 << 1) /* IACCVIOL: Instruction access violation flag */ #define SCB_CFSR_IACCVIOL (1 << 0) /* --- SCB_HFSR values ----------------------------------------------------- */ /* DEBUG_VT: reserved for debug use */ #define SCB_HFSR_DEBUG_VT (1 << 31) /* FORCED: Forced hard fault */ #define SCB_HFSR_FORCED (1 << 30) /* Bits [29:2]: reserved - must be kept cleared */ /* VECTTBL: Vector table hard fault */ #define SCB_HFSR_VECTTBL (1 << 1) /* Bit 0: reserved - must be kept cleared */ /* --- SCB_MMFAR values ---------------------------------------------------- */ /* MMFAR [31:0]: Memory management fault address */ /* --- SCB_BFAR values ----------------------------------------------------- */ /* BFAR [31:0]: Bus fault address */ /* --- SCB_CPACR values ---------------------------------------------------- */ /* CPACR CPn: Access privileges values */ #define SCB_CPACR_NONE 0 /* Access denied */ #define SCB_CPACR_PRIV 1 /* Privileged access only */ #define SCB_CPACR_FULL 3 /* Full access */ /* CPACR [20:21]: Access privileges for coprocessor 10 */ #define SCB_CPACR_CP10 (1 << 20) /* CPACR [22:23]: Access privileges for coprocessor 11 */ #define SCB_CPACR_CP11 (1 << 22) #endif /* --- SCB functions ------------------------------------------------------- */ BEGIN_DECLS struct scb_exception_stack_frame { uint32_t r0; uint32_t r1; uint32_t r2; uint32_t r3; uint32_t r12; uint32_t lr; uint32_t pc; uint32_t xpsr; } __attribute__((packed)); #define SCB_GET_EXCEPTION_STACK_FRAME(f) \ do { \ asm volatile ("mov %[frameptr], sp" \ : [frameptr]"=r" (f)); \ } while (0) void scb_reset_system(void) __attribute__((noreturn, naked)); /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) void scb_reset_core(void) __attribute__((noreturn, naked)); void scb_set_priority_grouping(uint32_t prigroup); #endif END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/scs.h000066400000000000000000000310571435536612600226000ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM3_SCS_H #define LIBOPENCM3_CM3_SCS_H /* * All the definition hereafter are generic for CortexMx ARMv7-M * See ARM document "ARMv7-M Architecture Reference Manual" for more details. * See also ARM document "ARM Compiler toolchain Developing Software for ARM * Processors" for details on System Timer/SysTick. */ /* * The System Control Space (SCS) is a memory-mapped 4KB address space that * provides 32-bit registers for configuration, status reporting and control. * The SCS registers divide into the following groups: * - system control and identification * - the CPUID processor identification space * - system configuration and status * - fault reporting * - a system timer, SysTick * - a Nested Vectored Interrupt Controller (NVIC) * - a Protected Memory System Architecture (PMSA) * - system debug. */ /* System Handler Priority 8 bits Registers, SHPR1/2/3 */ /* Note: 12 8bit Registers */ #define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id) /* * Debug Halting Control and Status Register (DHCSR). * * Purpose Controls halting debug. * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when * the system is running with halting debug enabled is UNPREDICTABLE. * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running * when S_HALT is set to 0. * - When C_DEBUGEN is set to 0, the processor ignores the values of all other * bits in this register. * - For more information about the use of DHCSR see Debug stepping on page * C1-824. * Configurations Always implemented. */ /* SCS_DHCSR register */ #define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0) /* * Debug Core Register Selector Register (DCRSR). * * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core * registers, special-purpose registers, and Floating-point extension * registers. A write to DCRSR specifies the register to transfer, whether the * transfer is a read or a write, and starts the transfer. * Usage constraints: Only accessible in Debug state. * Configurations Always implemented. * */ /* SCS_DCRS register */ #define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4) /* * Debug Core Register Data Register (DCRDR) * * Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR * provides debug access to the ARM core registers, special-purpose registers, * and Floating-point extension registers. The DCRDR is the data register for * these accesses. * - Used on its own, the DCRDR provides a message passing resource between an * external debugger and a debug agent running on the processor. * Note: * The architecture does not define any handshaking mechanism for this use of * DCRDR. * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to * particular transfers using the DCRSR and DCRDR. * Configurations Always implemented. * */ /* SCS_DCRDR register */ #define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8) /* * Debug Exception and Monitor Control Register (DEMCR). * * Purpose Manages vector catch behavior and DebugMonitor handling when * debugging. * Usage constraints: * - Bits [23:16] provide DebugMonitor exception control. * - Bits [15:0] provide Debug state, halting debug, control. * Configurations Always implemented. * */ /* SCS_DEMCR register */ #define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC) /* Debug Halting Control and Status Register (DHCSR) */ #define SCS_DHCSR_DBGKEY 0xA05F0000 #define SCS_DHCSR_C_DEBUGEN 0x00000001 #define SCS_DHCSR_C_HALT 0x00000002 #define SCS_DHCSR_C_STEP 0x00000004 #define SCS_DHCSR_C_MASKINTS 0x00000008 #define SCS_DHCSR_C_SNAPSTALL 0x00000020 #define SCS_DHCSR_S_REGRDY 0x00010000 #define SCS_DHCSR_S_HALT 0x00020000 #define SCS_DHCSR_S_SLEEP 0x00040000 #define SCS_DHCSR_S_LOCKUP 0x00080000 #define SCS_DHCSR_S_RETIRE_ST 0x01000000 #define SCS_DHCSR_S_RESET_ST 0x02000000 /* Debug Core Register Selector Register (DCRSR) */ #define SCS_DCRSR_REGSEL_MASK 0x0000001F #define SCS_DCRSR_REGSEL_XPSR 0x00000010 #define SCS_DCRSR_REGSEL_MSP 0x00000011 #define SCS_DCRSR_REGSEL_PSP 0x00000012 /* Debug Exception and Monitor Control Register (DEMCR) */ /* Bits 31:25 - Reserved */ #define SCS_DEMCR_TRCENA (1 << 24) /* Bits 23:20 - Reserved */ #define SCS_DEMCR_MON_REQ (1 << 19) #define SCS_DEMCR_MON_STEP (1 << 18) #define SCS_DEMCR_VC_MON_PEND (1 << 17) #define SCS_DEMCR_VC_MON_EN (1 << 16) /* Bits 15:11 - Reserved */ #define SCS_DEMCR_VC_HARDERR (1 << 10) #define SCS_DEMCR_VC_INTERR (1 << 9) #define SCS_DEMCR_VC_BUSERR (1 << 8) #define SCS_DEMCR_VC_STATERR (1 << 7) #define SCS_DEMCR_VC_CHKERR (1 << 6) #define SCS_DEMCR_VC_NOCPERR (1 << 5) #define SCS_DEMCR_VC_MMERR (1 << 4) /* Bits 3:1 - Reserved */ #define SCS_DEMCR_VC_CORERESET (1 << 0) /* * System Control Space (SCS) => System timer register support in the SCS. * To configure SysTick, load the interval required between SysTick events to * the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in * the SysTick Control and Status register, is activated on the transition from * 1 to 0, therefore it activates every n+1 clock ticks. If you require a * period of 100, write 99 to the SysTick Reload Value register. The SysTick * Reload Value register supports values between 0x1 and 0x00FFFFFF. * * If you want to use SysTick to generate an event at a timed interval, for * example 1ms, you can use the SysTick Calibration Value Register to scale * your value for the Reload register. The SysTick Calibration Value Register * is a read-only register that contains the number of pulses for a period of * 10ms, in the TENMS field, bits[23:0]. * * This register also has a SKEW bit. Bit[30] == 1 indicates that the * calibration for 10ms in the TENMS section is not exactly 10ms due to clock * frequency. Bit[31] == 1 indicates that the reference clock is not provided. */ /* * SysTick Control and Status Register (CSR). * Purpose Controls the system timer and provides status data. * Usage constraints: There are no usage constraints. * Configurations Always implemented. */ #define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10) /* SysTick Reload Value Register (CVR). * Purpose Reads or clears the current counter value. * Usage constraints: * - Any write to the register clears the register to zero. * - The counter does not provide read-modify-write protection. * - Unsupported bits are read as zero * Configurations Always implemented. */ #define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14) /* SysTick Current Value Register (RVR). * Purpose Holds the reload value of the SYST_CVR. * Usage constraints There are no usage constraints. * Configurations Always implemented. */ #define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18) /* * SysTick Calibration value Register(Read Only) (CALIB) * Purpose Reads the calibration value and parameters for SysTick. * Usage constraints: There are no usage constraints. * Configurations Always implemented. */ #define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C) /* --- SCS_SYST_CSR values ----------------------------------------------- */ /* Counter is operating. */ #define SCS_SYST_CSR_ENABLE (BIT0) /* Count to 0 changes the SysTick exception status to pending. */ #define SCS_SYST_CSR_TICKINT (BIT1) /* SysTick uses the processor clock. */ #define SCS_SYST_CSR_CLKSOURCE (BIT2) /* * Indicates whether the counter has counted to 0 since the last read of this * register: * 0 = Timer has not counted to 0 * 1 = Timer has counted to 0. */ #define SCS_SYST_CSR_COUNTFLAG (BIT16) /* --- CM_SCS_SYST_RVR values ---------------------------------------------- */ /* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter * reaches 0. */ /* Bit 24 to 31 are Reserved */ /* --- CM_SCS_SYST_CVR values ---------------------------------------------- */ /* Bit0 to 31 => Reads or clears the current counter value. */ /* --- CM_SCS_SYST_CALIB values -------------------------------------------- */ /* * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms * (100Hz) timing, subject to system clock skew errors. If this field is zero, * the calibration value is not known. */ #define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1) /* * Bit30 => SKEW Indicates whether the 10ms calibration value is exact: * 0 = 10ms calibration value is exact. * 1 = 10ms calibration value is inexact, because of the clock frequency */ #define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30) /* * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock * is implemented: * 0 = The reference clock is implemented. * 1 = The reference clock is not implemented. * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to * 1 and cannot be cleared to 0. */ #define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31) /* * System Control Space (SCS) => Data Watchpoint and Trace (DWT). * See "ARMv7-M Architecture Reference Manual" * (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/ * ARMv7-M_ARM.pdf) * The DWT is an optional debug unit that provides watchpoints, data tracing, * and system profiling for the processor. */ /* * DWT Control register * Purpose Provides configuration and status information for the DWT block, and * used to control features of the block * Usage constraints: There are no usage constraints. * Configurations Always implemented. */ #define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00) /* * DWT_CYCCNT register * Cycle Count Register (Shows or sets the value of the processor cycle * counter, CYCCNT) * When enabled, CYCCNT increments on each processor clock cycle. On overflow, * CYCCNT wraps to zero. * * Purpose Shows or sets the value of the processor cycle counter, CYCCNT. * Usage constraints: The DWT unit suspends CYCCNT counting when the processor * is in Debug state. * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control * register, DWT_CTRL. * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this * register is UNK/SBZP. */ #define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04) /* DWT_CPICNT register * Purpose Counts additional cycles required to execute multi-cycle * instructions and instruction fetch stalls. * Usage constraints: The counter initializes to 0 when software enables its * counter overflow event by * setting the DWT_CTRL.CPIEVTENA bit to 1. * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control * register, DWT_CTRL. * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not * include the profiling counters, this register is UNK/SBZP. */ #define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08) /* DWT_EXCCNT register */ #define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) /* DWT_EXCCNT register */ #define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) /* DWT_EXCCNT register */ #define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14) /* DWT_EXCCNT register */ #define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) /* DWT_PCSR register */ #define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18) /* --- SCS_DWT_CTRL values ------------------------------------------------- */ /* * Enables CYCCNT: * 0 = Disabled, 1 = Enabled * This bit is UNK/SBZP if the NOCYCCNT bit is RAO. */ #define SCS_DWT_CTRL_CYCCNTENA (BIT0) /* TODO bit definition values for other DWT_XXX register */ /* Macro to be called at startup to enable SCS & Cycle Counter */ #define SCS_DWT_CYCLE_COUNTER_ENABLED() ((SCS_DEMCR |= SCS_DEMCR_TRCENA)\ (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA)) #define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR = 0) /* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not * enabled) */ #define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \ SCS_SYST_CSR_CLKSOURCE)) /* Macro to be called at startup to Enable CortexMx SysTick and IRQ */ #define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \ SCS_SYST_CSR_CLKSOURCE | \ SCS_SYST_CSR_TICKINT)) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/sync.h000066400000000000000000000032771435536612600227670ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM3_SYNC_H #define LIBOPENCM3_CM3_SYNC_H #include "common.h" #ifdef __cplusplus extern "C" { #endif void __dmb(void); /* Implements synchronisation primitives as discussed in the ARM document * DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M * Architecture Reference Manual. */ /* --- Exclusive load and store instructions ------------------------------- */ /* Those are defined only on CM3 or CM4 */ #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) uint32_t __ldrex(volatile uint32_t *addr); uint32_t __strex(uint32_t val, volatile uint32_t *addr); /* --- Convenience functions ----------------------------------------------- */ /* Here we implement some simple synchronisation primitives. */ typedef uint32_t mutex_t; #define MUTEX_UNLOCKED 0 #define MUTEX_LOCKED 1 void mutex_lock(mutex_t *m); void mutex_unlock(mutex_t *m); #endif #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/systick.h000066400000000000000000000105601435536612600234750ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @defgroup CM3_systick_defines SysTick Defines * * @brief libopencm3 Defined Constants and Types for the Cortex SysTick * * @ingroup CM3_defines * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2010 Thomas Otto * * @date 19 August 2012 * * LGPL License Terms @ref lgpl_license */ /** * @note this file has been not following the register naming scheme, the * correct names defined, and the old ones stay there for compatibility with * old software (will be deprecated in the future) */ /**@{*/ #ifndef LIBOPENCM3_SYSTICK_H #define LIBOPENCM3_SYSTICK_H #include #include /* --- SYSTICK registers --------------------------------------------------- */ /* Control and status register (STK_CTRL) */ #define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) #define STK_CSR MMIO32(SYS_TICK_BASE + 0x00) /* reload value register (STK_LOAD) */ #define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) #define STK_RVR MMIO32(SYS_TICK_BASE + 0x04) /* current value register (STK_VAL) */ #define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) #define STK_CVR MMIO32(SYS_TICK_BASE + 0x08) /* calibration value register (STK_CALIB) */ #define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) /* --- STK_CSR values ------------------------------------------------------ */ /* Bits [31:17] Reserved, must be kept cleared. */ /* COUNTFLAG: */ #define STK_CTRL_COUNTFLAG (1 << 16) #define STK_CSR_COUNTFLAG (1 << 16) /* Bits [15:3] Reserved, must be kept cleared. */ /* CLKSOURCE: Clock source selection */ #define STK_CTRL_CLKSOURCE_LSB 2 #define STK_CTRL_CLKSOURCE (1 << STK_CTRL_CLKSOURCE_LSB) #define STK_CSR_CLKSOURCE_LSB 2 #define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB) /** @defgroup systick_clksource Clock source selection @ingroup CM3_systick_defines @{*/ #if defined(__ARM_ARCH_6M__) #define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB) #define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) #else #define STK_CTRL_CLKSOURCE_AHB_DIV8 (0 << STK_CTRL_CLKSOURCE_LSB) #define STK_CTRL_CLKSOURCE_AHB (1 << STK_CTRL_CLKSOURCE_LSB) #endif /**@}*/ /* TICKINT: SysTick exception request enable */ #define STK_CTRL_TICKINT (1 << 1) #define STK_CSR_TICKINT (1 << 1) /* ENABLE: Counter enable */ #define STK_CTRL_ENABLE (1 << 0) #define STK_CSR_ENABLE (1 << 0) /* --- STK_RVR values ------------------------------------------------------ */ /* Bits [31:24] Reserved, must be kept cleared. */ /* RELOAD[23:0]: RELOAD value */ #define STK_RVR_RELOAD 0x00FFFFFF /* --- STK_CVR values ------------------------------------------------------ */ /* Bits [31:24] Reserved, must be kept cleared. */ /* CURRENT[23:0]: Current counter value */ #define STK_CVR_CURRENT 0x00FFFFFF /* --- STK_CALIB values ---------------------------------------------------- */ /* NOREF: NOREF flag */ #define STK_CALIB_NOREF (1 << 31) /* SKEW: SKEW flag */ #define STK_CALIB_SKEW (1 << 30) /* Bits [29:24] Reserved, must be kept cleared. */ /* TENMS[23:0]: Calibration value */ #define STK_CALIB_TENMS 0x00FFFFFF /* --- Function Prototypes ------------------------------------------------- */ BEGIN_DECLS void systick_set_reload(uint32_t value); uint32_t systick_get_reload(void); uint32_t systick_get_value(void); void systick_set_clocksource(uint8_t clocksource); void systick_interrupt_enable(void); void systick_interrupt_disable(void); void systick_counter_enable(void); void systick_counter_disable(void); uint8_t systick_get_countflag(void); uint32_t systick_get_calib(void); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/tpiu.h000066400000000000000000000071261435536612600227710ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CM3_TPIU_H #define LIBOPENCM3_CM3_TPIU_H /* Cortex-M3 Trace Port Interface Unit (TPIU) */ /* Those defined only on ARMv7 and above */ #if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) #error "Trace Port Interface Unit not available in CM0" #endif /* --- TPIU registers ------------------------------------------------------ */ /* Supported Synchronous Port Size (TPIU_SSPSR) */ #define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000) /* Current Synchronous Port Size (TPIU_CSPSR) */ #define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004) /* Asynchronous Clock Prescaler (TPIU_ACPR) */ #define TPIU_ACPR MMIO32(TPIU_BASE + 0x010) /* Selected Pin Protocol (TPIU_SPPR) */ #define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0) /* Formatter and Flush Status Register (TPIU_FFSR) */ #define TPIU_FFSR MMIO32(TPIU_BASE + 0x300) /* Formatter and Flush Control Register (TPIU_FFCR) */ #define TPIU_FFCR MMIO32(TPIU_BASE + 0x304) /* (TPIU_DEVID) */ #define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8) /* TODO: PID, CID */ /* --- TPIU_SSPSR values --------------------------------------------------- */ /* * bit[N] == 0, trace port width of (N+1) not supported * bit[N] == 1, trace port width of (N+1) supported */ #define TPIU_SSPSR_BYTE (1 << 0) #define TPIU_SSPSR_HALFWORD (1 << 1) #define TPIU_SSPSR_WORD (1 << 3) /* --- TPIU_SSPSR values --------------------------------------------------- */ /* Same format as TPIU_SSPSR, except only one is set */ #define TPIU_CSPSR_BYTE (1 << 0) #define TPIU_CSPSR_HALFWORD (1 << 1) #define TPIU_CSPSR_WORD (1 << 3) /* --- TPIU_ACPR values ---------------------------------------------------- */ /* Bits 31:16 - Reserved */ /* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */ /* --- TPIU_SPPR values ---------------------------------------------------- */ /* Bits 31:2 - Reserved */ #define TPIU_SPPR_SYNC (0x0) #define TPIU_SPPR_ASYNC_MANCHESTER (0x1) #define TPIU_SPPR_ASYNC_NRZ (0x2) /* --- TPIU_FFSR values ---------------------------------------------------- */ /* Bits 31:4 - Reserved */ #define TPIU_FFSR_FTNONSTOP (1 << 3) #define TPIU_FFSR_TCPRESENT (1 << 2) #define TPIU_FFSR_FTSTOPPED (1 << 1) #define TPIU_FFSR_FLINPROG (1 << 0) /* --- TPIU_FFCR values ---------------------------------------------------- */ /* Bits 31:9 - Reserved */ #define TPIU_FFCR_TRIGIN (1 << 8) /* Bits 7:2 - Reserved */ #define TPIU_FFCR_ENFCONT (1 << 1) /* Bit 0 - Reserved */ /* --- TPIU_DEVID values ---------------------------------------------------- */ /* Bits 31:16 - Reserved */ /* Bits 15:12 - Implementation defined */ #define TPUI_DEVID_NRZ_SUPPORTED (1 << 11) #define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10) /* Bit 9 - RAZ, indicated that trace data and clock are supported */ #define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6) /* Bits 5:0 - Implementation defined */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/cm3/vector.h000066400000000000000000000045251435536612600233120ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 chrysn * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @file * * Definitions for handling vector tables. * * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 * (from the EFM32 documentation at * http://www.energymicro.com/downloads/datasheets), and was seen analogously * in other ARM implementations' libopencm3 files. * * The structure of the vector table is implemented independently of the system * vector table starting at memory position 0x0, as it can be relocated to * other memory locations too. * * The exact size of a vector interrupt table depends on the number of * interrupts IRQ_COUNT, which is defined per family. */ #ifndef LIBOPENCM3_VECTOR_H #define LIBOPENCM3_VECTOR_H #include #include /** Type of an interrupt function. Only used to avoid hard-to-read function * pointers in the efm32_vector_table_t struct. */ typedef void (*vector_table_entry_t)(void); typedef struct { unsigned int *initial_sp_value; /**< Initial stack pointer value. */ vector_table_entry_t reset; vector_table_entry_t nmi; vector_table_entry_t hard_fault; vector_table_entry_t memory_manage_fault; /* not in CM0 */ vector_table_entry_t bus_fault; /* not in CM0 */ vector_table_entry_t usage_fault; /* not in CM0 */ vector_table_entry_t reserved_x001c[4]; vector_table_entry_t sv_call; vector_table_entry_t debug_monitor; /* not in CM0 */ vector_table_entry_t reserved_x0034; vector_table_entry_t pend_sv; vector_table_entry_t systick; vector_table_entry_t irq[NVIC_IRQ_COUNT]; } vector_table_t; extern vector_table_t vector_table; #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/dispatch/000077500000000000000000000000001435536612600227465ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/dispatch/nvic.h000066400000000000000000000023501435536612600240560ustar00rootroot00000000000000#if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #elif defined(EFM32TG) # include #elif defined(EFM32G) # include #elif defined(EFM32LG) # include #elif defined(EFM32GG) # include #elif defined(LPC13XX) # include #elif defined(LPC17XX) # include #elif defined(LPC43XX_M4) # include #elif defined(LPC43XX_M0) # include #elif defined(SAM3X) # include #elif defined(SAM3N) # include #elif defined(LM3S) || defined(LM4F) /* Yes, we use the same interrupt table for both LM3S and LM4F */ # include #else # warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0" #define NVIC_IRQ_COUNT 0 #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/docmain.dox000066400000000000000000000007701435536612600233010ustar00rootroot00000000000000/** @mainpage libopencm3 Developer Documentation @version 1.0.0 @date 7 September 2012 * The libopencm3 project (previously known as libopenstm32) aims to create * a free/libre/open-source (GPL v3, or later) firmware library for various * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03, * Atmel SAM3U, NXP LPC1000 and others. * * @par "" * * See the libopencm3 wiki for * more information. LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/000077500000000000000000000000001435536612600220635ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32g/000077500000000000000000000000001435536612600231465ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32g/doc-efm32g.h000066400000000000000000000010521435536612600251430ustar00rootroot00000000000000/** @mainpage libopencm3 EFM32 Gecko @version 1.0.0 @date 11 November 2012 API documentation for Energy Micro EFM32 Gecko Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32G EFM32 Gecko Libraries for Energy Micro EFM32 Gecko series. @version 1.0.0 @date 11 November 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32G_defines EFM32 Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Gecko series @version 1.0.0 @date 11 November 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32g/irq.yaml000066400000000000000000000010221435536612600246200ustar00rootroot00000000000000includeguard: LIBOPENCM3_EFM32G_NVIC_H partname_humanreadable: EFM32 Gecko series partname_doxygen: EFM32G # The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1. irqs: - dma - gpio_even - timer0 - usart0_rx - usart0_tx - acmp01 - adc0 - dac0 - i2c0 - gpio_odd - timer1 - timer2 - usart1_rx - usart1_tx - usart2_rx - usart2_tx - uart0_rx - uart0_tx - leuart0 - leuart1 - letimer0 - pcnt0 - pcnt1 - pcnt2 - rtc - cmu - vcmp - lcd - msc - aes hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32gg/000077500000000000000000000000001435536612600233155ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32gg/doc-efm32gg.h000066400000000000000000000011201435536612600254550ustar00rootroot00000000000000/** @mainpage libopencm3 EFM32 Giant Gecko @version 1.0.0 @date 11 November 2012 API documentation for Energy Micro EFM32 Giant Gecko Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32GG EFM32 Giant Gecko Libraries for Energy Micro EFM32 Giant Gecko series. @version 1.0.0 @date 11 November 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32GG_defines EFM32 Giant Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Giant Gecko series @version 1.0.0 @date 11 November 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32gg/irq.yaml000066400000000000000000000011571435536612600250000ustar00rootroot00000000000000includeguard: LIBOPENCM3_EFM32GG_NVIC_H partname_humanreadable: EFM32 Giant Gecko series partname_doxygen: EFM32GG # The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1. irqs: - dma - gpio_even - timer0 - usart0_rx - usart0_tx - usb - acmp01 - adc0 - dac0 - i2c0 - i2c1 - gpio_odd - timer1 - timer2 - timer3 - usart1_rx - usart1_tx - lesense - usart2_rx - usart2_tx - uart0_rx - uart0_tx - uart1_rx - uart1_tx - leuart0 - leuart1 - letimer0 - pcnt0 - pcnt1 - pcnt2 - rtc - burtc - cmu - vcmp - lcd - msc - aes - ebi hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32lg/000077500000000000000000000000001435536612600233225ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32lg/doc-efm32lg.h000066400000000000000000000011171435536612600254750ustar00rootroot00000000000000/** @mainpage libopencm3 EFM32 Leopard Gecko @version 1.0.0 @date 4 March 2013 API documentation for Energy Micro EFM32 Leopard Gecko Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32LG EFM32 LeopardGecko Libraries for Energy Micro EFM32 Leopard Gecko series. @version 1.0.0 @date 4 March 2013 LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32LG_defines EFM32 Leopard Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko series @version 1.0.0 @date 4 March 2013 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32lg/irq.yaml000066400000000000000000000011611435536612600250000ustar00rootroot00000000000000includeguard: LIBOPENCM3_EFM32LG_NVIC_H partname_humanreadable: EFM32 Leopard Gecko series partname_doxygen: EFM32LG # The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1. irqs: - dma - gpio_even - timer0 - usart0_rx - usart0_tx - usb - acmp01 - adc0 - dac0 - i2c0 - i2c1 - gpio_odd - timer1 - timer2 - timer3 - usart1_rx - usart1_tx - lesense - usart2_rx - usart2_tx - uart0_rx - uart0_tx - uart1_rx - uart1_tx - leuart0 - leuart1 - letimer0 - pcnt0 - pcnt1 - pcnt2 - rtc - burtc - cmu - vcmp - lcd - msc - aes - ebi hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32tg/000077500000000000000000000000001435536612600233325ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32tg/doc-efm32tg.h000066400000000000000000000010751435536612600255200ustar00rootroot00000000000000/** @mainpage libopencm3 EFM32 Tiny Gecko @version 1.0.0 @date 4 March 2013 API documentation for Energy Micro EFM32 Tiny Gecko Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32TG EFM32 TinyGecko Libraries for Energy Micro EFM32 Tiny Gecko series. @version 1.0.0 @date 4 March 2013 LGPL License Terms @ref lgpl_license */ /** @defgroup EFM32TG_defines EFM32 Tiny Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Tiny Gecko series @version 1.0.0 @date 4 March 2013 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32tg/irq.yaml000066400000000000000000000007051435536612600250130ustar00rootroot00000000000000includeguard: LIBOPENCM3_EFM32TG_NVIC_H partname_humanreadable: EFM32 Tiny Gecko series partname_doxygen: EFM32TG # The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. irqs: - dma - gpio_even - timer0 - usart0_rx - usart0_tx - acmp01 - adc0 - dac0 - i2c0 - gpio_odd - timer1 - usart1_rx - usart1_tx - lesense - leuart0 - letimer0 - pcnt0 - rtc - cmu - vcmp - lcd - msc - aes hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/efm32tg/memorymap.h000066400000000000000000000056421435536612600255200ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 chrysn * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @file * * Layout of the system address space of Tiny Gecko devices. * * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2. */ /* The common cortex-m3 definitions were verified from * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be * missing there. The details (everything based on SCS_BASE) was verified from * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but * there are discrepancies. */ #include #define CODE_BASE 0x00000000 #define SRAM_BASE 0x20000000 #define SRAM_BASE_BITBAND 0x22000000 #define PERIPH_BASE 0x40000000 #define PERIPH_BASE_BITBAND 0x42000000 /* Details of the "Code" section */ #define FLASH_BASE (CODE_BASE + 0x00000000) #define USERDATA_BASE (CODE_BASE + 0x0fe00000) #define LOCKBITS_BASE (CODE_BASE + 0x0fe04000) #define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000) #define CODESPACESRAM_BASE (CODE_BASE + 0x10000000) /* Tiny Gecko peripherial definitions */ #define VCMP_BASE (PERIPH_BASE + 0x00000000) #define ACMP0_BASE (PERIPH_BASE + 0x00001000) #define ACMP1_BASE (PERIPH_BASE + 0x00001400) #define ADC_BASE (PERIPH_BASE + 0x00002000) #define DAC0_BASE (PERIPH_BASE + 0x00004000) #define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */ #define I2C0_BASE (PERIPH_BASE + 0x0000a000) #define USART0_BASE (PERIPH_BASE + 0x0000c000) #define USART1_BASE (PERIPH_BASE + 0x0000c400) #define TIMER0_BASE (PERIPH_BASE + 0x00010000) #define TIMER1_BASE (PERIPH_BASE + 0x00010400) #define RTC_BASE (PERIPH_BASE + 0x00080000) #define LETIMER0_BASE (PERIPH_BASE + 0x00082000) #define LEUART0_BASE (PERIPH_BASE + 0x00084000) #define PCNT0_BASE (PERIPH_BASE + 0x00086000) #define WDOG_BASE (PERIPH_BASE + 0x00088000) #define LCD_BASE (PERIPH_BASE + 0x0008a000) #define LESENSE_BASE (PERIPH_BASE + 0x0008c000) #define MSC_BASE (PERIPH_BASE + 0x000c0000) #define DMA_BASE (PERIPH_BASE + 0x000c2000) #define EMU_BASE (PERIPH_BASE + 0x000c6000) #define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */ #define RMU_BASE (PERIPH_BASE + 0x000ca000) #define PRS_BASE (PERIPH_BASE + 0x000cc000) #define AES_BASE (PERIPH_BASE + 0x000e0000) hackrf-0.0~git20230104.cfc2f34/include/libopencm3/efm32/memorymap.h000066400000000000000000000021371435536612600242450ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 chrysn * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @file * * Dispatcher for the base address definitions, depending on the particular * Gecko family. * * @see tinygecko/memorymap.h */ #ifndef LIBOPENCM3_EFM32_MEMORYMAP_H #define LIBOPENCM3_EFM32_MEMORYMAP_H #ifdef TINYGECKO # include #else # error "efm32 family not defined." #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/license.dox000066400000000000000000000012451435536612600233070ustar00rootroot00000000000000/** @page lgpl_license libopencm3 License libopencm3 is free software: you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this program. If not, see . */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm3s/000077500000000000000000000000001435536612600220255ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm3s/doc-lm3s.h000066400000000000000000000007661435536612600236300ustar00rootroot00000000000000/** @mainpage libopencm3 LM3S @version 1.0.0 @date 14 September 2012 API documentation for TI Stellaris LM3S Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup LM3Sxx LM3S Libraries for TI Stellaris LM3S series. @version 1.0.0 @date 7 September 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup LM3Sxx_defines LM3S Defines @brief Defined Constants and Types for the LM3S series @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm3s/gpio.h000066400000000000000000000060121435536612600231330ustar00rootroot00000000000000/** @defgroup gpio_defines General Purpose I/O Defines @brief Defined Constants and Types for the LM3S General Purpose I/O @ingroup LM3Sxx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2011 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LM3S_GPIO_H #define LM3S_GPIO_H /**@{*/ #include #include /* --- Convenience macros -------------------------------------------------- */ /* GPIO port base addresses (for convenience) */ #define GPIOA GPIOA_APB_BASE #define GPIOB GPIOB_APB_BASE #define GPIOC GPIOC_APB_BASE #define GPIOD GPIOD_APB_BASE #define GPIOE GPIOE_APB_BASE #define GPIOF GPIOF_APB_BASE #define GPIOG GPIOG_APB_BASE #define GPIOH GPIOH_APB_BASE /* GPIO number definitions (for convenience) */ #define GPIO0 (1 << 0) #define GPIO1 (1 << 1) #define GPIO2 (1 << 2) #define GPIO3 (1 << 3) #define GPIO4 (1 << 4) #define GPIO5 (1 << 5) #define GPIO6 (1 << 6) #define GPIO7 (1 << 7) /* --- GPIO registers ------------------------------------------------------ */ #define GPIO_DATA(port) (&MMIO32(port + 0x000)) #define GPIO_DIR(port) MMIO32(port + 0x400) #define GPIO_IS(port) MMIO32(port + 0x404) #define GPIO_IBE(port) MMIO32(port + 0x408) #define GPIO_IEV(port) MMIO32(port + 0x40c) #define GPIO_IM(port) MMIO32(port + 0x410) #define GPIO_RIS(port) MMIO32(port + 0x414) #define GPIO_MIS(port) MMIO32(port + 0x418) #define GPIO_ICR(port) MMIO32(port + 0x41c) #define GPIO_AFSEL(port) MMIO32(port + 0x420) #define GPIO_DR2R(port) MMIO32(port + 0x500) #define GPIO_DR4R(port) MMIO32(port + 0x504) #define GPIO_DR8R(port) MMIO32(port + 0x508) #define GPIO_ODR(port) MMIO32(port + 0x50c) #define GPIO_PUR(port) MMIO32(port + 0x510) #define GPIO_PDR(port) MMIO32(port + 0x514) #define GPIO_SLR(port) MMIO32(port + 0x518) #define GPIO_DEN(port) MMIO32(port + 0x51c) #define GPIO_LOCK(port) MMIO32(port + 0x520) #define GPIO_CR(port) MMIO32(port + 0x524) #define GPIO_AMSEL(port) MMIO32(port + 0x528) BEGIN_DECLS void gpio_set(uint32_t gpioport, uint8_t gpios); void gpio_clear(uint32_t gpioport, uint8_t gpios); END_DECLS /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm3s/irq.yaml000066400000000000000000000040071435536612600235050ustar00rootroot00000000000000# Although this says LM3S, the interrupt table applies to the LM4F as well # Some interrupt vectores marked as reserved in LM3S are used in LM4F, and some # vectors in LM3S are marked reserved for LM4F. However, the common vectors are # identical, and we can safely use the same interrupt table. Reserved vectors # will never be triggered, so having them is perfectly safe. includeguard: LIBOPENCM3_LM3S_NVIC_H partname_humanreadable: LM3S series partname_doxygen: LM3S irqs: 0: GPIOA 1: GPIOB 2: GPIOC 3: GPIOD 4: GPIOE 5: UART0 6: UART1 7: SSI0 8: I2C0 9: PWM0_FAULT 10: PWM0_0 11: PWM0_1 12: PWM0_2 13: QEI0 14: ADC0SS0 15: ADC0SS1 16: ADC0SS2 17: ADC0SS3 18: WATCHDOG 19: TIMER0A 20: TIMER0B 21: TIMER1A 22: TIMER1B 23: TIMER2A 24: TIMER2B 25: COMP0 26: COMP1 27: COMP2 28: SYSCTL 29: FLASH 30: GPIOF 31: GPIOG 32: GPIOH 33: UART2 34: SSI1 35: TIMER3A 36: TIMER3B 37: I2C1 38: QEI1 39: CAN0 40: CAN1 41: CAN2 42: ETH 43: HIBERNATE 44: USB0 45: PWM0_3 46: UDMA 47: UDMAERR 48: ADC1SS0 49: ADC1SS1 50: ADC1SS2 51: ADC1SS3 52: I2S0 53: EPI0 54: GPIOJ 55: GPIOK 56: GPIOL 57: SSI2 58: SSI3 59: UART3 60: UART4 61: UART5 62: UART6 63: UART7 # undefined: slot 64 - 67 68: I2C2 69: I2C3 70: TIMER4A 71: TIMER4B # undefined: slot 72 - 91 92: TIMER5A 93: TIMER5B 94: WTIMER0A 95: WTIMER0B 96: WTIMER1A 97: WTIMER1B 98: WTIMER2A 99: WTIMER2B 100: WTIMER3A 101: WTIMER3B 102: WTIMER4A 103: WTIMER4B 104: WTIMER5A 105: WTIMER5B 106: SYSEXC 107: PECI0 108: LPC0 109: I2C4 110: I2C5 111: GPIOM 112: GPION # undefined: slot 113 114: FAN0 # undefined: slot 115 116: GPIOP0 117: GPIOP1 118: GPIOP2 119: GPIOP3 120: GPIOP4 121: GPIOP5 122: GPIOP6 123: GPIOP7 124: GPIOQ0 125: GPIOQ1 126: GPIOQ2 127: GPIOQ3 128: GPIOQ4 129: GPIOQ5 130: GPIOQ6 131: GPIOQ7 # undefined: slot 132 - 133 134: PWM1_0 135: PWM1_1 136: PWM1_2 137: PWM1_3 138: PWM1_FAULT hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm3s/memorymap.h000066400000000000000000000030621435536612600242050ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LM3S_MEMORYMAP_H #define LM3S_MEMORYMAP_H #include /* --- LM3S specific peripheral definitions ----------------------------- */ #define GPIOA_APB_BASE (0x40004000) #define GPIOB_APB_BASE (0x40005000) #define GPIOC_APB_BASE (0x40006000) #define GPIOD_APB_BASE (0x40007000) #define GPIOE_APB_BASE (0x40024000) #define GPIOF_APB_BASE (0x40025000) #define GPIOG_APB_BASE (0x40026000) #define GPIOH_APB_BASE (0x40027000) #define GPIOA_BASE (0x40058000) #define GPIOB_BASE (0x40059000) #define GPIOC_BASE (0x4005A000) #define GPIOD_BASE (0x4005B000) #define GPIOE_BASE (0x4005C000) #define GPIOF_BASE (0x4005D000) #define GPIOG_BASE (0x4005E000) #define GPIOH_BASE (0x4005F000) #define SYSTEMCONTROL_BASE (0x400FE000) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm3s/systemcontrol.h000066400000000000000000000065011435536612600251250ustar00rootroot00000000000000/** @defgroup systemcontrol_defines System Control @brief Defined Constants and Types for the LM3S System Control @ingroup LM3Sxx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2011 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LM3S_SYSTEMCONTROL_H #define LM3S_SYSTEMCONTROL_H /**@{*/ #include #define SYSTEMCONTROL_DID0 MMIO32(SYSTEMCONTROL_BASE + 0x000) #define SYSTEMCONTROL_DID1 MMIO32(SYSTEMCONTROL_BASE + 0x004) #define SYSTEMCONTROL_DC0 MMIO32(SYSTEMCONTROL_BASE + 0x008) #define SYSTEMCONTROL_DC1 MMIO32(SYSTEMCONTROL_BASE + 0x010) #define SYSTEMCONTROL_DC2 MMIO32(SYSTEMCONTROL_BASE + 0x014) #define SYSTEMCONTROL_DC3 MMIO32(SYSTEMCONTROL_BASE + 0x018) #define SYSTEMCONTROL_DC4 MMIO32(SYSTEMCONTROL_BASE + 0x01C) #define SYSTEMCONTROL_DC5 MMIO32(SYSTEMCONTROL_BASE + 0x020) #define SYSTEMCONTROL_DC6 MMIO32(SYSTEMCONTROL_BASE + 0x024) #define SYSTEMCONTROL_DC7 MMIO32(SYSTEMCONTROL_BASE + 0x028) #define SYSTEMCONTROL_PBORCTL MMIO32(SYSTEMCONTROL_BASE + 0x030) #define SYSTEMCONTROL_LDORCTL MMIO32(SYSTEMCONTROL_BASE + 0x034) #define SYSTEMCONTROL_SRCR0 MMIO32(SYSTEMCONTROL_BASE + 0x040) #define SYSTEMCONTROL_SRCR1 MMIO32(SYSTEMCONTROL_BASE + 0x044) #define SYSTEMCONTROL_SRCR2 MMIO32(SYSTEMCONTROL_BASE + 0x048) #define SYSTEMCONTROL_RIS MMIO32(SYSTEMCONTROL_BASE + 0x050) #define SYSTEMCONTROL_IMC MMIO32(SYSTEMCONTROL_BASE + 0x054) #define SYSTEMCONTROL_MISC MMIO32(SYSTEMCONTROL_BASE + 0x058) #define SYSTEMCONTROL_RESC MMIO32(SYSTEMCONTROL_BASE + 0x05C) #define SYSTEMCONTROL_RCC MMIO32(SYSTEMCONTROL_BASE + 0x060) #define SYSTEMCONTROL_PLLCFG MMIO32(SYSTEMCONTROL_BASE + 0x064) #define SYSTEMCONTROL_GPIOHBCTL MMIO32(SYSTEMCONTROL_BASE + 0x06C) #define SYSTEMCONTROL_RCC2 MMIO32(SYSTEMCONTROL_BASE + 0x070) #define SYSTEMCONTROL_MOSCCTL MMIO32(SYSTEMCONTROL_BASE + 0x07C) #define SYSTEMCONTROL_RCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x100) #define SYSTEMCONTROL_RCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x104) #define SYSTEMCONTROL_RCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x108) #define SYSTEMCONTROL_SCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x110) #define SYSTEMCONTROL_SCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x114) #define SYSTEMCONTROL_SCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x118) #define SYSTEMCONTROL_DCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x120) #define SYSTEMCONTROL_DCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x124) #define SYSTEMCONTROL_DCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x128) #define SYSTEMCONTROL_DSLPCLKCFG MMIO32(SYSTEMCONTROL_BASE + 0x144) /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/000077500000000000000000000000001435536612600220115ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/doc-lm4f.h000066400000000000000000000007651435536612600235770ustar00rootroot00000000000000/** @mainpage libopencm3 LM4F @version 1.0.0 @date 22 November 2012 API documentation for TI Stellaris LM4F Cortex M4F series. LGPL License Terms @ref lgpl_license */ /** @defgroup LM4Fxx LM4F Libraries for TI Stellaris LM4F series. @version 1.0.0 @date 22 November 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup LM4Fxx_defines LM4F Defines @brief Defined Constants and Types for the LM4F series @version 1.0.0 @date 22 November 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/gpio.h000066400000000000000000000273231435536612600231270ustar00rootroot00000000000000/** @defgroup gpio_defines General Purpose I/O Defines * * @brief Defined Constants and Types for the LM4F General Purpose I/O * * @ingroup LM4Fxx_defines * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2011 * Gareth McMullin * @author @htmlonly © @endhtmlonly 2013 * Alexandru Gagniuc * * @date 16 March 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * Copyright (C) 2013 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LM4F_GPIO_H #define LM4F_GPIO_H /**@{*/ #include #include /* ============================================================================= * Convenience macros * ---------------------------------------------------------------------------*/ /** @defgroup gpio_reg_base GPIO register base addresses * @{*/ #define GPIOA GPIOA_BASE #define GPIOB GPIOB_BASE #define GPIOC GPIOC_BASE #define GPIOD GPIOD_BASE #define GPIOE GPIOE_BASE #define GPIOF GPIOF_BASE #define GPIOG GPIOG_BASE #define GPIOH GPIOH_BASE #define GPIOJ GPIOJ_BASE #define GPIOK GPIOK_BASE #define GPIOL GPIOL_BASE #define GPIOM GPIOM_BASE #define GPION GPION_BASE #define GPIOP GPIOP_BASE #define GPIOQ GPIOQ_BASE /** @} */ /* ============================================================================= * GPIO number definitions (for convenience) * * These are usable across all GPIO registers, * except GPIO_LOCK and GPIO_PCTL * ---------------------------------------------------------------------------*/ /** @defgroup gpio_pin_id GPIO pin identifiers * @{*/ #define GPIO0 (1 << 0) #define GPIO1 (1 << 1) #define GPIO2 (1 << 2) #define GPIO3 (1 << 3) #define GPIO4 (1 << 4) #define GPIO5 (1 << 5) #define GPIO6 (1 << 6) #define GPIO7 (1 << 7) #define GPIO_ALL 0xff /** @} */ /* ============================================================================= * GPIO registers * ---------------------------------------------------------------------------*/ /* GPIO Data */ #define GPIO_DATA(port) (&MMIO32(port + 0x000)) /* GPIO Direction */ #define GPIO_DIR(port) MMIO32(port + 0x400) /* GPIO Interrupt Sense */ #define GPIO_IS(port) MMIO32(port + 0x404) /* GPIO Interrupt Both Edges */ #define GPIO_IBE(port) MMIO32(port + 0x408) /* GPIO Interrupt Event */ #define GPIO_IEV(port) MMIO32(port + 0x40c) /* GPIO Interrupt Mask */ #define GPIO_IM(port) MMIO32(port + 0x410) /* GPIO Raw Interrupt Status */ #define GPIO_RIS(port) MMIO32(port + 0x414) /* GPIO Masked Interrupt Status */ #define GPIO_MIS(port) MMIO32(port + 0x418) /* GPIO Interrupt Clear */ #define GPIO_ICR(port) MMIO32(port + 0x41c) /* GPIO Alternate Function Select */ #define GPIO_AFSEL(port) MMIO32(port + 0x420) /* GPIO 2-mA Drive Select */ #define GPIO_DR2R(port) MMIO32(port + 0x500) /* GPIO 4-mA Drive Select */ #define GPIO_DR4R(port) MMIO32(port + 0x504) /* GPIO 8-mA Drive Select */ #define GPIO_DR8R(port) MMIO32(port + 0x508) /* GPIO Open Drain Select */ #define GPIO_ODR(port) MMIO32(port + 0x50c) /* GPIO Pull-Up Select */ #define GPIO_PUR(port) MMIO32(port + 0x510) /* GPIO Pull-Down Select */ #define GPIO_PDR(port) MMIO32(port + 0x514) /* GPIO Slew Rate Control Select */ #define GPIO_SLR(port) MMIO32(port + 0x518) /* GPIO Digital Enable */ #define GPIO_DEN(port) MMIO32(port + 0x51c) /* GPIO Lock */ #define GPIO_LOCK(port) MMIO32(port + 0x520) /* GPIO Commit */ #define GPIO_CR(port) MMIO32(port + 0x524) /* GPIO Analog Mode Select */ #define GPIO_AMSEL(port) MMIO32(port + 0x528) /* GPIO Port Control */ #define GPIO_PCTL(port) MMIO32(port + 0x52C) /* GPIO ADC Control */ #define GPIO_ADCCTL(port) MMIO32(port + 0x530) /* GPIO DMA Control */ #define GPIO_DMACTL(port) MMIO32(port + 0x534) /* GPIO Peripheral Identification */ #define GPIO_PERIPH_ID4(port) MMIO32(port + 0xFD0) #define GPIO_PERIPH_ID5(port) MMIO32(port + 0xFD4) #define GPIO_PERIPH_ID6(port) MMIO32(port + 0xFD8) #define GPIO_PERIPH_ID7(port) MMIO32(port + 0xFDC) #define GPIO_PERIPH_ID0(port) MMIO32(port + 0xFE0) #define GPIO_PERIPH_ID1(port) MMIO32(port + 0xFE4) #define GPIO_PERIPH_ID2(port) MMIO32(port + 0xFE8) #define GPIO_PERIPH_ID3(port) MMIO32(port + 0xFEC) /* GPIO PrimeCell Identification */ #define GPIO_PCELL_ID0(port) MMIO32(port + 0xFF0) #define GPIO_PCELL_ID1(port) MMIO32(port + 0xFF4) #define GPIO_PCELL_ID2(port) MMIO32(port + 0xFF8) #define GPIO_PCELL_ID3(port) MMIO32(port + 0xFFC) /* ============================================================================= * Convenience enums * ---------------------------------------------------------------------------*/ enum gpio_mode { GPIO_MODE_OUTPUT, /**< Configure pin as output */ GPIO_MODE_INPUT, /**< Configure pin as input */ GPIO_MODE_ANALOG, /**< Configure pin as analog function */ }; enum gpio_pullup { GPIO_PUPD_NONE, /**< Do not pull the pin high or low */ GPIO_PUPD_PULLUP, /**< Pull the pin high */ GPIO_PUPD_PULLDOWN, /**< Pull the pin low */ }; enum gpio_output_type { GPIO_OTYPE_PP, /**< Push-pull configuration */ GPIO_OTYPE_OD, /**< Open drain configuration */ }; enum gpio_drive_strength { GPIO_DRIVE_2MA, /**< 2mA drive */ GPIO_DRIVE_4MA, /**< 4mA drive */ GPIO_DRIVE_8MA, /**< 8mA drive */ GPIO_DRIVE_8MA_SLEW_CTL,/**< 8mA drive with slew rate control */ }; enum gpio_trigger { GPIO_TRIG_LVL_LOW, /**< Level trigger, signal low */ GPIO_TRIG_LVL_HIGH, /**< Level trigger, signal high */ GPIO_TRIG_EDGE_FALL, /**< Falling edge trigger */ GPIO_TRIG_EDGE_RISE, /**< Rising edge trigger*/ GPIO_TRIG_EDGE_BOTH, /**< Falling and Rising edges trigger*/ }; /* ============================================================================= * Function prototypes * ---------------------------------------------------------------------------*/ BEGIN_DECLS void gpio_enable_ahb_aperture(void); void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, enum gpio_pullup pullup, uint8_t gpios); void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype, enum gpio_drive_strength drive, uint8_t gpios); void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios); void gpio_toggle(uint32_t gpioport, uint8_t gpios); void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios); /* Let's keep these ones inlined. GPIO control should be fast */ /** @ingroup gpio_control * @{ */ /** * \brief Get status of a Group of Pins (atomic) * * Reads the level of the given pins. Bit 0 of the returned data corresponds to * GPIO0 level, bit 1 to GPIO1 level. and so on. Bits corresponding to masked * pins (corresponding bit of gpios parameter set to zero) are returned as 0. * * This is an atomic operation. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together. * * @return The level of the GPIO port. The pins not specified in gpios are * masked to zero. */ static inline uint8_t gpio_read(uint32_t gpioport, uint8_t gpios) { return GPIO_DATA(gpioport)[gpios]; } /** * \brief Set level of a Group of Pins (atomic) * * Sets the level of the given pins. Bit 0 of the data parameter corresponds to * GPIO0, bit 1 to GPIO1. and so on. Maskedpins (corresponding bit of gpios * parameter set to zero) are returned not affected. * * This is an atomic operation. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together. * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit * 1 to GPIO1. and so on. */ static inline void gpio_write(uint32_t gpioport, uint8_t gpios, uint8_t data) { /* ipaddr[9:2] mask the bits to be set, hence the array index */ GPIO_DATA(gpioport)[gpios] = data; } /** * \brief Set a Group of Pins (atomic) * * Set one or more pins of the given GPIO port. This is an atomic operation. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together. */ static inline void gpio_set(uint32_t gpioport, uint8_t gpios) { gpio_write(gpioport, gpios, 0xff); } /** * \brief Clear a Group of Pins (atomic) * * Clear one or more pins of the given GPIO port. This is an atomic operation. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together. */ static inline void gpio_clear(uint32_t gpioport, uint8_t gpios) { gpio_write(gpioport, gpios, 0); } /** * \brief Read level of all pins from a port (atomic) * * Read the current value of the given GPIO port. This is an atomic operation. * * This is functionally identical to @ref gpio_read (gpioport, GPIO_ALL). * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * * @return The level of all the pins on the GPIO port. */ static inline uint8_t gpio_port_read(uint32_t gpioport) { return gpio_read(gpioport, GPIO_ALL); } /** * \brief Set level of of all pins from a port (atomic) * * Set the level of all pins on the given GPIO port. This is an atomic * operation. * * This is functionally identical to @ref gpio_write (gpioport, GPIO_ALL, data). * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together. * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit * 1 to GPIO1. and so on. */ static inline void gpio_port_write(uint32_t gpioport, uint8_t data) { gpio_write(gpioport, GPIO_ALL, data); } /** @} */ void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, uint8_t gpios); void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios); void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios); /* Let's keep these ones inlined. GPIO. They are designed to be used in ISRs */ /** @ingroup gpio_irq * @{ */ /** \brief Determine if interrupt is generated by the given pin * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] srcpins source pin or group of pins to check. */ static inline bool gpio_is_interrupt_source(uint32_t gpioport, uint8_t srcpins) { return GPIO_MIS(gpioport) & srcpins; } /** * \brief Mark interrupt as serviced * * After an interrupt is services, its flag must be cleared. If the flag is not * cleared, then execution will jump back to the start of the ISR after the ISR * returns. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together. */ static inline void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios) { GPIO_ICR(gpioport) |= gpios; } /** @} */ END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/memorymap.h000066400000000000000000000041621435536612600241730ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LM4F_MEMORYMAP_H #define LM4F_MEMORYMAP_H #include /* --- LM4F specific peripheral definitions ----------------------------- */ #define GPIOA_APB_BASE (0x40004000) #define GPIOB_APB_BASE (0x40005000) #define GPIOC_APB_BASE (0x40006000) #define GPIOD_APB_BASE (0x40007000) #define GPIOE_APB_BASE (0x40024000) #define GPIOF_APB_BASE (0x40025000) #define GPIOG_APB_BASE (0x40026000) #define GPIOH_APB_BASE (0x40027000) #define GPIOJ_APB_BASE (0x4003D000) #define GPIOA_BASE (0x40058000) #define GPIOB_BASE (0x40059000) #define GPIOC_BASE (0x4005A000) #define GPIOD_BASE (0x4005B000) #define GPIOE_BASE (0x4005C000) #define GPIOF_BASE (0x4005D000) #define GPIOG_BASE (0x4005E000) #define GPIOH_BASE (0x4005F000) #define GPIOJ_BASE (0x40060000) #define GPIOK_BASE (0x40061000) #define GPIOL_BASE (0x40062000) #define GPIOM_BASE (0x40063000) #define GPION_BASE (0x40064000) #define GPIOP_BASE (0x40065000) #define GPIOQ_BASE (0x40066000) #define UART0_BASE (0x4000C000) #define UART1_BASE (0x4000D000) #define UART2_BASE (0x4000E000) #define UART3_BASE (0x4000F000) #define UART4_BASE (0x40010000) #define UART5_BASE (0x40011000) #define UART6_BASE (0x40012000) #define UART7_BASE (0x40013000) #define USB_BASE (0x40050000) #define SYSCTL_BASE (0x400FE000) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/nvic.h000066400000000000000000000032621435536612600231240ustar00rootroot00000000000000/** @defgroup nvic_defines Nested Vectored Interrupt Controller @brief Defined Constants and Types for the LM4F Nested Vectored Interrupt Controller @ingroup LM4Fxx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_LM4F_NVIC_H #define LIBOPENCM3_LM4F_NVIC_H /**@{*/ #include /** @ingroup nvic_defines * The LM3S interrupt table applies to the LM4F as well. Some interrupt * vectors marked as reserved in LM3S are used in LM4F, and some vectors in * LM3S are marked reserved for LM4F. However, the common vectors are * identical, and we can safely use the same interrupt table. Reserved vectors * will never be triggered, so having them is perfectly safe. */ #include /**@}*/ #endif /* LIBOPENCM3_LM4F_NVIC_H */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/rcc.h000066400000000000000000000077221435536612600227410ustar00rootroot00000000000000/** @defgroup rcc_defines Reset and Clock Control @brief Defined Constants and Types for the LM4F Reset and Clock Control @ingroup LM4Fxx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LM4F_RCC_H #define LM4F_RCC_H /**@{*/ #include /** * \brief Oscillator source values * * Possible values of the oscillator source. */ enum osc_src { OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC, OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC, OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4, OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K, OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768, }; /** * \brief PWM clock divisor values * * Possible values of the binary divisor used to predivide the system clock down * for use as the timing reference for the PWM module. */ enum pwm_clkdiv { PWMDIV_2 = SYSCTL_RCC_PWMDIV_2, PWMDIV_4 = SYSCTL_RCC_PWMDIV_4, PWMDIV_8 = SYSCTL_RCC_PWMDIV_8, PWMDIV_16 = SYSCTL_RCC_PWMDIV_16, PWMDIV_32 = SYSCTL_RCC_PWMDIV_32, PWMDIV_64 = SYSCTL_RCC_PWMDIV_64, }; /** * \brief Predefined crystal values * * Predefined crystal values for the XTAL field in SYSCTL_RCC. * Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and * SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock * of 400MHz. */ enum xtal_t { XTAL_4M = SYSCTL_RCC_XTAL_4M, XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096, XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152, XTAL_5M = SYSCTL_RCC_XTAL_5M, XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12, XTAL_6M = SYSCTL_RCC_XTAL_6M, XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144, XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728, XTAL_8M = SYSCTL_RCC_XTAL_8M, XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192, XTAL_10M = SYSCTL_RCC_XTAL_10M, XTAL_12M = SYSCTL_RCC_XTAL_12M, XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288, XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56, XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818, XTAL_16M = SYSCTL_RCC_XTAL_16M, XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384, XTAL_18M = SYSCTL_RCC_XTAL_18M, XTAL_20M = SYSCTL_RCC_XTAL_20M, XTAL_24M = SYSCTL_RCC_XTAL_24M, XTAL_25M = SYSCTL_RCC_XTAL_25M, }; /* ============================================================================= * Function prototypes * ---------------------------------------------------------------------------*/ BEGIN_DECLS /* Low-level clock API */ void rcc_configure_xtal(enum xtal_t xtal); void rcc_disable_main_osc(void); void rcc_disable_interal_osc(void); void rcc_enable_main_osc(void); void rcc_enable_interal_osc(void); void rcc_enable_rcc2(void); void rcc_pll_off(void); void rcc_pll_on(void); void rcc_set_osc_source(enum osc_src src); void rcc_pll_bypass_disable(void); void rcc_pll_bypass_enable(void); void rcc_set_pll_divisor(uint8_t div400); void rcc_set_pwm_divisor(enum pwm_clkdiv div); void rcc_usb_pll_off(void); void rcc_usb_pll_on(void); void rcc_wait_for_pll_ready(void); /* High-level clock API */ void rcc_change_pll_divisor(uint8_t plldiv400); uint32_t rcc_get_system_clock_frequency(void); void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400); END_DECLS /**@}*/ #endif /* LM4F_RCC_H */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/systemcontrol.h000066400000000000000000000621061435536612600251140ustar00rootroot00000000000000/** @defgroup systemcontrol_defines System Control @brief Defined Constants and Types for the LM4F System Control @ingroup LM4Fxx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LM4F_SYSTEMCONTROL_H #define LM4F_SYSTEMCONTROL_H /**@{*/ #include #include #define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000) #define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004) #define SYSCTL_PBORCTL MMIO32(SYSCTL_BASE + 0x030) #define SYSCTL_LDORCTL MMIO32(SYSCTL_BASE + 0x034) #define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050) #define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054) #define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058) #define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C) #define SYSCTL_RCC MMIO32(SYSCTL_BASE + 0x060) #define SYSCTL_PLLCFG MMIO32(SYSCTL_BASE + 0x064) #define SYSCTL_GPIOHBCTL MMIO32(SYSCTL_BASE + 0x06C) #define SYSCTL_RCC2 MMIO32(SYSCTL_BASE + 0x070) #define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C) #define SYSCTL_DSLPCLKCFG MMIO32(SYSCTL_BASE + 0x144) #define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C) #define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150) #define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154) #define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160) #define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164) #define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168) /* Peripheral present */ #define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300) #define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304) #define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308) #define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C) #define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314) #define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318) #define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C) #define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320) #define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328) #define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334) #define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338) #define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C) #define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340) #define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344) #define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358) #define SYSCTL_PPWTIMER MMIO32(SYSCTL_BASE + 0x35C) /* Peripheral software reset */ #define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500) #define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504) #define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508) #define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C) #define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514) #define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518) #define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C) #define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520) #define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528) #define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534) #define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538) #define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C) #define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540) #define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544) #define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558) #define SYSCTL_SRWTIMER MMIO32(SYSCTL_BASE + 0x55C) /* Peripheral run mode clock gating control */ #define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600) #define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604) #define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608) #define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C) #define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614) #define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618) #define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C) #define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620) #define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628) #define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634) #define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638) #define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C) #define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640) #define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644) #define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658) #define SYSCTL_RCGCWTIMER MMIO32(SYSCTL_BASE + 0x65C) /* Peripheral sleep mode clock gating control */ #define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700) #define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704) #define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708) #define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C) #define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714) #define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718) #define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C) #define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720) #define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728) #define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734) #define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738) #define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C) #define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740) #define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744) #define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758) #define SYSCTL_SCGCWTIMER MMIO32(SYSCTL_BASE + 0x75C) /* Peripheral deep-sleep mode clock gating control */ #define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800) #define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804) #define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808) #define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C) #define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814) #define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818) #define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C) #define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820) #define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828) #define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834) #define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838) #define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C) #define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840) #define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844) #define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858) #define SYSCTL_DCGCWTIMER MMIO32(SYSCTL_BASE + 0x85C) /* Peripheral ready */ #define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00) #define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04) #define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08) #define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C) #define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14) #define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18) #define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C) #define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20) #define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28) #define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34) #define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38) #define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C) #define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40) #define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44) #define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58) #define SYSCTL_PRWTIMER MMIO32(SYSCTL_BASE + 0xA5C) /* ============================================================================= * System Control Legacy Registers * ---------------------------------------------------------------------------*/ #ifdef LM4F_LEGACY_SYSCTL #define SYSCTL_DC0 MMIO32(SYSCTL_BASE + 0x008) #define SYSCTL_DC1 MMIO32(SYSCTL_BASE + 0x010) #define SYSCTL_DC2 MMIO32(SYSCTL_BASE + 0x014) #define SYSCTL_DC3 MMIO32(SYSCTL_BASE + 0x018) #define SYSCTL_DC4 MMIO32(SYSCTL_BASE + 0x01C) #define SYSCTL_DC5 MMIO32(SYSCTL_BASE + 0x020) #define SYSCTL_DC6 MMIO32(SYSCTL_BASE + 0x024) #define SYSCTL_DC7 MMIO32(SYSCTL_BASE + 0x028) #define SYSCTL_DC8 MMIO32(SYSCTL_BASE + 0x02C) #define SYSCTL_SRCR0 MMIO32(SYSCTL_BASE + 0x040) #define SYSCTL_SRCR1 MMIO32(SYSCTL_BASE + 0x044) #define SYSCTL_SRCR2 MMIO32(SYSCTL_BASE + 0x048) #define SYSCTL_RCGC0 MMIO32(SYSCTL_BASE + 0x100) #define SYSCTL_RCGC1 MMIO32(SYSCTL_BASE + 0x104) #define SYSCTL_RCGC2 MMIO32(SYSCTL_BASE + 0x108) #define SYSCTL_SCGC0 MMIO32(SYSCTL_BASE + 0x110) #define SYSCTL_SCGC1 MMIO32(SYSCTL_BASE + 0x114) #define SYSCTL_SCGC2 MMIO32(SYSCTL_BASE + 0x118) #define SYSCTL_DCGC0 MMIO32(SYSCTL_BASE + 0x120) #define SYSCTL_DCGC1 MMIO32(SYSCTL_BASE + 0x124) #define SYSCTL_DCGC2 MMIO32(SYSCTL_BASE + 0x128) #define SYSCTL_DC9 MMIO32(SYSCTL_BASE + 0x190) #define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0) #endif /* LM4F_LEGACY_SYSCTL */ /* ============================================================================= * SYSCTL_DID0 values * ---------------------------------------------------------------------------*/ /** DID0 version */ #define SYSCTL_DID0_VER_MASK (7 << 28) /** Device class */ #define SYSCTL_DID0_CLASS_MASK (0xFF << 16) /** Major revision */ #define SYSCTL_DID0_MAJOR_MASK (0xFF << 8) /** Minor revision */ #define SYSCTL_DID0_MAJOR_MASK (0xFF << 8) /* ============================================================================= * SYSCTL_DID1 values * ---------------------------------------------------------------------------*/ /** DID1 version */ #define SYSCTL_DID1_VER_MASK (0xF << 28) /** Family */ #define SYSCTL_DID1_FAM_MASK (0xF << 24) /** Part number */ #define SYSCTL_DID1_PARTNO_MASK (0xFF << 16) /** Pin count */ #define SYSCTL_DID1_PINCOUNT_MASK (0x7 << 13) #define SYSCTL_DID1_PINCOUNT_28P (0x0 << 13) #define SYSCTL_DID1_PINCOUNT_48P (0x1 << 13) #define SYSCTL_DID1_PINCOUNT_100P (0x2 << 13) #define SYSCTL_DID1_PINCOUNT_64P (0x3 << 13) #define SYSCTL_DID1_PINCOUNT_144P (0x4 << 13) #define SYSCTL_DID1_PINCOUNT_157P (0x5 << 13) /** Temperature range */ #define SYSCTL_DID1_TEMP_MASK (0x7 << 5) #define SYSCTL_DID1_TEMP_0_70 (0x0 << 5) #define SYSCTL_DID1_TEMP_M40_85 (0x1 << 5) #define SYSCTL_DID1_TEMP_M40_105 (0x2 << 5) /** Package */ #define SYSCTL_DID1_PKG_MASK (0x3 << 5) #define SYSCTL_DID1_PKG_SOIC (0x0 << 5) #define SYSCTL_DID1_PKG_LQFP (0x1 << 5) #define SYSCTL_DID1_PKG_BGA (0x2 << 5) /** ROHS compliance */ #define SYSCTL_DID1_ROHS (1 << 2) /** Qualification status */ #define SYSCTL_DID1_QUAL_MASK (3 << 0) /* ============================================================================= * SYSCTL_PBORCTL values * ---------------------------------------------------------------------------*/ /** BOR interrupt or reset */ #define SYSCTL_PBORCTL_BORIOR (1 << 1) /* ============================================================================= * SYSCTL_RIS values * ---------------------------------------------------------------------------*/ /** MOSC Power Up Raw Interrupt Status */ #define SYSCTL_RIS_MOSCPUPRIS (1 << 8) /** USB PLL Lock Raw Interrupt Status */ #define SYSCTL_RIS_USBPLLLRIS (1 << 7) /** PLL Lock Raw Interrupt Status */ #define SYSCTL_RIS_PLLLRIS (1 << 6) /** Main Oscillator Failure Raw Interrupt Status */ #define SYSCTL_RIS_MOFRIS (1 << 3) /** Brown-Out Reset Raw Interrupt Status */ #define SYSCTL_RIS_BORRIS (1 << 1) /* ============================================================================= * SYSCTL_IMC values * ---------------------------------------------------------------------------*/ /** MOSC Power Up Raw Interrupt Status */ #define SYSCTL_IMC_MOSCPUPIM (1 << 8) /** USB PLL Lock Raw Interrupt Status */ #define SYSCTL_IMC_USBPLLLIM (1 << 7) /** PLL Lock Raw Interrupt Status */ #define SYSCTL_IMC_PLLLIM (1 << 6) /** Main Oscillator Failure Raw Interrupt Status */ #define SYSCTL_IMC_MOFIM (1 << 3) /** Brown-Out Reset Raw Interrupt Status */ #define SYSCTL_IMC_BORIM (1 << 1) /* ============================================================================= * SYSCTL_MISC values * ---------------------------------------------------------------------------*/ /** MOSC Power Up Raw Interrupt Status */ #define SYSCTL_MISC_MOSCPUPMIS (1 << 8) /** USB PLL Lock Raw Interrupt Status */ #define SYSCTL_MISC_USBPLLLMIS (1 << 7) /** PLL Lock Raw Interrupt Status */ #define SYSCTL_MISC_PLLLMIS (1 << 6) /** Main Oscillator Failure Raw Interrupt Status */ #define SYSCTL_MISC_MOFMIS (1 << 3) /** Brown-Out Reset Raw Interrupt Status */ #define SYSCTL_MISC_BORMIS (1 << 1) /* ============================================================================= * SYSCTL_RESC values * ---------------------------------------------------------------------------*/ /** MOSC Failure Reset */ #define SYSCTL_RESC_MOSCFAIL (1 << 18) /** Watchdog Timer 1 Reset */ #define SYSCTL_RESC_WDT1 (1 << 5) /** Software Reset */ #define SYSCTL_RESC_SW (1 << 4) /** Watchdog Timer 0 Reset */ #define SYSCTL_RESC_WDT0 (1 << 3) /** Brown-Out Reset */ #define SYSCTL_RESC_BOR (1 << 2) /** Power-On Reset */ #define SYSCTL_RESC_POR (1 << 1) /** External Reset */ #define SYSCTL_RESC_EXT (1 << 0) /* ============================================================================= * SYSCTL_RCC values * ---------------------------------------------------------------------------*/ /** Auto Clock Gating */ #define SYSCTL_RCC_ACG (1 << 27) /** System Clock Divisor */ #define SYSCTL_RCC_SYSDIV_MASK (0xF << 23) /** Enable System Clock Divider */ #define SYSCTL_RCC_USESYSDIV (1 << 22) /** Enable PWM Clock Divisor */ #define SYSCTL_RCC_USEPWMDIV (1 << 20) /** PWM Unit Clock Divisor */ #define SYSCTL_RCC_PWMDIV_MASK (0xF << 17) #define SYSCTL_RCC_PWMDIV_2 (0x0 << 17) #define SYSCTL_RCC_PWMDIV_4 (0x1 << 17) #define SYSCTL_RCC_PWMDIV_8 (0x2 << 17) #define SYSCTL_RCC_PWMDIV_16 (0x3 << 17) #define SYSCTL_RCC_PWMDIV_32 (0x4 << 17) #define SYSCTL_RCC_PWMDIV_64 (0x5 << 17) /** PLL Power Down */ #define SYSCTL_RCC_PWRDN (1 << 13) /** PLL Bypass */ #define SYSCTL_RCC_BYPASS (1 << 11) /** Crystal Value */ #define SYSCTL_RCC_XTAL_MASK (0x1F << 6) #define SYSCTL_RCC_XTAL_4M (0x06 << 6) #define SYSCTL_RCC_XTAL_4M_096 (0x07 << 6) #define SYSCTL_RCC_XTAL_4M_9152 (0x08 << 6) #define SYSCTL_RCC_XTAL_5M (0x09 << 6) #define SYSCTL_RCC_XTAL_5M_12 (0x0A << 6) #define SYSCTL_RCC_XTAL_6M (0x0B << 6) #define SYSCTL_RCC_XTAL_6M_144 (0x0C << 6) #define SYSCTL_RCC_XTAL_7M_3728 (0x0D << 6) #define SYSCTL_RCC_XTAL_8M (0x0E << 6) #define SYSCTL_RCC_XTAL_8M_192 (0x0F << 6) #define SYSCTL_RCC_XTAL_10M (0x10 << 6) #define SYSCTL_RCC_XTAL_12M (0x11 << 6) #define SYSCTL_RCC_XTAL_12M_288 (0x12 << 6) #define SYSCTL_RCC_XTAL_13M_56 (0x13 << 6) #define SYSCTL_RCC_XTAL_14M_31818 (0x14 << 6) #define SYSCTL_RCC_XTAL_16M (0x15 << 6) #define SYSCTL_RCC_XTAL_16M_384 (0x16 << 6) #define SYSCTL_RCC_XTAL_18M (0x17 << 6) #define SYSCTL_RCC_XTAL_20M (0x18 << 6) #define SYSCTL_RCC_XTAL_24M (0x19 << 6) #define SYSCTL_RCC_XTAL_25M (0x1A << 6) /** Oscillator Source */ #define SYSCTL_RCC_OSCSRC_MASK (0x3 << 4) #define SYSCTL_RCC_OSCSRC_MOSC (0x0 << 4) #define SYSCTL_RCC_OSCSRC_PIOSC (0x1 << 4) #define SYSCTL_RCC_OSCSRC_PIOSC_D4 (0x2 << 4) #define SYSCTL_RCC_OSCSRC_30K (0x3 << 4) /** Precision Internal Oscillator Disable */ #define SYSCTL_RCC_IOSCDIS (1 << 1) /** Main Oscillator Disable */ #define SYSCTL_RCC_MOSCDIS (1 << 0) /* ============================================================================= * SYSCTL_GPIOHBCTL values * ---------------------------------------------------------------------------*/ #define SYSCTL_GPIOHBCTL_PORTQ (1 << 14) #define SYSCTL_GPIOHBCTL_PORTP (1 << 13) #define SYSCTL_GPIOHBCTL_PORTN (1 << 12) #define SYSCTL_GPIOHBCTL_PORTM (1 << 11) #define SYSCTL_GPIOHBCTL_PORTL (1 << 10) #define SYSCTL_GPIOHBCTL_PORTK (1 << 9) #define SYSCTL_GPIOHBCTL_PORTJ (1 << 8) #define SYSCTL_GPIOHBCTL_PORTH (1 << 7) #define SYSCTL_GPIOHBCTL_PORTG (1 << 6) #define SYSCTL_GPIOHBCTL_PORTF (1 << 5) #define SYSCTL_GPIOHBCTL_PORTE (1 << 4) #define SYSCTL_GPIOHBCTL_PORTD (1 << 3) #define SYSCTL_GPIOHBCTL_PORTC (1 << 2) #define SYSCTL_GPIOHBCTL_PORTB (1 << 1) #define SYSCTL_GPIOHBCTL_PORTA (1 << 0) /* ============================================================================= * SYSCTL_RCC2 values * ---------------------------------------------------------------------------*/ /** RCC2 overides RCC */ #define SYSCTL_RCC2_USERCC2 (1 << 31) /** Divide PLL as 400 MHz vs. 200 MHz */ #define SYSCTL_RCC2_DIV400 (1 << 30) /** Auto Clock Gating */ #define SYSCTL_RCC2_ACG (1 << 27) /** System Clock Divisor 2 */ #define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23) /** Additional LSB for SYSDIV2 */ #define SYSCTL_RCC2_SYSDIV2LSB (1 << 22) /** System clock divisor mask when RCC2_DIV400 is set */ #define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22) /** Power-Down USB PLL */ #define SYSCTL_RCC2_USBPWRDN (1 << 14) /** PLL Power Down 2 */ #define SYSCTL_RCC2_PWRDN2 (1 << 13) /** PLL Bypass 2 */ #define SYSCTL_RCC2_BYPASS2 (1 << 11) /** Oscillator Source 2 */ #define SYSCTL_RCC2_OSCSRC2_MASK (0x7 << 4) #define SYSCTL_RCC2_OSCSRC2_MOSC (0x0 << 4) #define SYSCTL_RCC2_OSCSRC2_PIOSC (0x1 << 4) #define SYSCTL_RCC2_OSCSRC2_PIOSC_D4 (0x2 << 4) #define SYSCTL_RCC2_OSCSRC2_30K (0x3 << 4) #define SYSCTL_RCC2_OSCSRC2_32K768 (0x7 << 4) /* ============================================================================= * SYSCTL_MOSCCTL values * ---------------------------------------------------------------------------*/ /** No Crystal Connected */ #define SYSCTL_MOSCCTL_NOXTAL (1 << 2) /** MOSC Failure Action */ #define SYSCTL_MOSCCTL_MOSCIM (1 << 1) /** Clock Validation for MOSC */ #define SYSCTL_MOSCCTL_CVAL (1 << 0) /* ============================================================================= * SYSCTL_DSLPCLKCFG values * ---------------------------------------------------------------------------*/ /*TODO*/ /* ============================================================================= * SYSCTL_SYSPROP values * ---------------------------------------------------------------------------*/ /** FPU present */ #define SYSCTL_SYSPROP_FPU (1 << 0) /* ============================================================================= * SYSCTL_PIOSCCAL values * ---------------------------------------------------------------------------*/ /** Use User Trim Value */ #define SYSCTL_PIOSCCAL_UTEN (1 << 31) /** Start calibration */ #define SYSCTL_PIOSCCAL_CAL (1 << 9) /** Update trim */ #define SYSCTL_PIOSCCAL_UPDATE (1 << 8) /** User Trim Value */ #define SYSCTL_PIOSCCAL_UT_MASK (0x7F << 0) /* ============================================================================= * SYSCTL_PIOSCSTAT values * ---------------------------------------------------------------------------*/ /** Default Trim Value */ #define SYSCTL_PIOSCSTAT_DT_MASK (0x7F << 16) /** Calibration result */ #define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3 << 8) /** Calibration Trim Value */ #define SYSCTL_PIOSCSTAT_CT_MASK (0x7F << 0) /* ============================================================================= * SYSCTL_PLLFREQ0 values * ---------------------------------------------------------------------------*/ /** PLL M fractional value */ #define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF << 10) /** PLL M integer value */ #define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF << 0) /* ============================================================================= * SYSCTL_PLLFREQ1 values * ---------------------------------------------------------------------------*/ /** PLL Q value */ #define SYSCTL_PLLFREQ1_Q_MASK (0x1F << 8) /** PLL N value */ #define SYSCTL_PLLFREQ1_N_MASK (0x1F << 0) /* ============================================================================= * SYSCTL_PLLSTAT values * ---------------------------------------------------------------------------*/ /** PLL lock */ #define SYSCTL_PLLSTAT_LOCK (1 << 0) /* ============================================================================= * Convenience definitions for a readable API * ---------------------------------------------------------------------------*/ /** * \brief Clock enable definitions * * The definitions are specified in the form * 31:5 register offset from SYSCTL_BASE for the clock register * 4:0 bit offset for the given peripheral * * The names have the form [clock_type]_[periph_type]_[periph_number] * Where clock_type is * RCC for run clock * SCC for sleep clock * DCC for deep-sleep clock */ enum lm4f_clken { /* * Run clock control */ RCC_WD0 = ((uint32_t)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5, RCC_WD1, RCC_TIMER0 = ((uint32_t)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5, RCC_TIMER1, RCC_TIMER2, RCC_TIMER3, RCC_TIMER4, RCC_TIMER5, RCC_GPIOA = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5, RCC_GPIOB, RCC_GPIOC, RCC_GPIOD, RCC_GPIOE, RCC_GPIOF, RCC_GPIOG, RCC_GPIOH, RCC_GPIOJ, RCC_GPIOK, RCC_GPIOL, RCC_GPIOM, RCC_GPION, RCC_GPIOP, RCC_GPIOQ, RCC_DMA = ((uint32_t)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5, RCC_HIB = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5, RCC_UART0 = ((uint32_t)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5, RCC_UART1, RCC_UART2, RCC_UART3, RCC_UART4, RCC_UART5, RCC_UART6, RCC_UART7, RCC_SSI0 = ((uint32_t)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5, RCC_SSI1, RCC_SSI2, RCC_SSI3, RCC_I2C0 = ((uint32_t)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5, RCC_I2C1, RCC_I2C2, RCC_I2C3, RCC_I2C4, RCC_I2C5, RCC_USB0 = ((uint32_t)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5, RCC_CAN0 = ((uint32_t)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5, RCC_CAN1, RCC_ADC0 = ((uint32_t)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5, RCC_ADC1, RCC_ACMP0 = ((uint32_t)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5, RCC_PWM0 = ((uint32_t)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5, RCC_PWM1, RCC_QEI0 = ((uint32_t)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5, RCC_QEI1, RCC_EEPROM0 = ((uint32_t)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5, RCC_WTIMER0 = ((uint32_t)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5, RCC_WTIMER1, RCC_WTIMER2, RCC_WTIMER3, RCC_WTIMER4, RCC_WTIMER5, /* * Sleep clock control */ SCC_WD0 = ((uint32_t)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5, SCC_WD1, SCC_TIMER0 = ((uint32_t)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5, SCC_TIMER1, SCC_TIMER2, SCC_TIMER3, SCC_TIMER4, SCC_TIMER5, SCC_GPIOA = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5, SCC_GPIOB, SCC_GPIOC, SCC_GPIOD, SCC_GPIOE, SCC_GPIOF, SCC_GPIOG, SCC_GPIOH, SCC_GPIOJ, SCC_GPIOK, SCC_GPIOL, SCC_GPIOM, SCC_GPION, SCC_GPIOP, SCC_GPIOQ, SCC_DMA = ((uint32_t)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5, SCC_HIB = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5, SCC_UART0 = ((uint32_t)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5, SCC_UART1, SCC_UART2, SCC_UART3, SCC_UART4, SCC_UART5, SCC_UART6, SCC_UART7, SCC_SSI0 = ((uint32_t)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5, SCC_SSI1, SCC_SSI2, SCC_SSI3, SCC_I2C0 = ((uint32_t)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5, SCC_I2C1, SCC_I2C2, SCC_I2C3, SCC_I2C4, SCC_I2C5, SCC_USB0 = ((uint32_t)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5, SCC_CAN0 = ((uint32_t)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5, SCC_CAN1, SCC_ADC0 = ((uint32_t)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5, SCC_ADC1, SCC_ACMP0 = ((uint32_t)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5, SCC_PWM0 = ((uint32_t)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5, SCC_PWM1, SCC_QEI0 = ((uint32_t)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5, SCC_QEI1, SCC_EEPROM0 = ((uint32_t)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5, SCC_WTIMER0 = ((uint32_t)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5, SCC_WTIMER1, SCC_WTIMER2, SCC_WTIMER3, SCC_WTIMER4, SCC_WTIMER5, /* * Deep-sleep clock control */ DCC_WD0 = ((uint32_t)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5, DCC_WD1, DCC_TIMER0 = ((uint32_t)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5, DCC_TIMER1, DCC_TIMER2, DCC_TIMER3, DCC_TIMER4, DCC_TIMER5, DCC_GPIOA = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5, DCC_GPIOB, DCC_GPIOC, DCC_GPIOD, DCC_GPIOE, DCC_GPIOF, DCC_GPIOG, DCC_GPIOH, DCC_GPIOJ, DCC_GPIOK, DCC_GPIOL, DCC_GPIOM, DCC_GPION, DCC_GPIOP, DCC_GPIOQ, DCC_DMA = ((uint32_t)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5, DCC_HIB = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5, DCC_UART0 = ((uint32_t)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5, DCC_UART1, DCC_UART2, DCC_UART3, DCC_UART4, DCC_UART5, DCC_UART6, DCC_UART7, DCC_SSI0 = ((uint32_t)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5, DCC_SSI1, DCC_SSI2, DCC_SSI3, DCC_I2C0 = ((uint32_t)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5, DCC_I2C1, DCC_I2C2, DCC_I2C3, DCC_I2C4, DCC_I2C5, DCC_USB0 = ((uint32_t)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5, DCC_CAN0 = ((uint32_t)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5, DCC_CAN1, DCC_ADC0 = ((uint32_t)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5, DCC_ADC1, DCC_ACMP0 = ((uint32_t)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5, DCC_PWM0 = ((uint32_t)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5, DCC_PWM1, DCC_QEI0 = ((uint32_t)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5, DCC_QEI1, DCC_EEPROM0 = ((uint32_t)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5, DCC_WTIMER0 = ((uint32_t)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5, DCC_WTIMER1, DCC_WTIMER2, DCC_WTIMER3, DCC_WTIMER4, DCC_WTIMER5, }; /* ============================================================================ * Function prototypes * --------------------------------------------------------------------------*/ BEGIN_DECLS void periph_clock_enable(enum lm4f_clken periph); void periph_clock_disable(enum lm4f_clken periph); END_DECLS /**@}*/ #endif /* LM4F_SYSTEMCONTROL_H */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/uart.h000066400000000000000000000424331435536612600231430ustar00rootroot00000000000000/** @defgroup uart_defines UART Control * * @brief Defined Constants and Types for the LM4F UART Control * * @ingroup LM4Fxx_defines * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2013 * Alexandru Gagniuc * * @date 07 May 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_LM4F_UART_H #define LIBOPENCM3_LM4F_UART_H /**@{*/ #include #include /* ============================================================================= * Convenience macros * ---------------------------------------------------------------------------*/ /** @defgroup uart_reg_base UART register base addresses * @{*/ #define UART0 UART0_BASE #define UART1 UART1_BASE #define UART2 UART2_BASE #define UART3 UART3_BASE #define UART4 UART4_BASE #define UART5 UART5_BASE #define UART6 UART6_BASE #define UART7 UART7_BASE /** @} */ /* ============================================================================= * UART registers * ---------------------------------------------------------------------------*/ /* UART data register */ #define UART_DR(uart_base) MMIO32(uart_base + 0x00) /* UART Receive Status/Error Clear register */ #define UART_RSR(uart_base) MMIO32(uart_base + 0x04) #define UART_ECR(uart_base) MMIO32(uart_base + 0x04) /* UART Flag register */ #define UART_FR(uart_base) MMIO32(uart_base + 0x18) /* UART IrDA Low-Power register */ #define UART_ILPR(uart_base) MMIO32(uart_base + 0x20) /* UART Integer baudrate divisor */ #define UART_IBRD(uart_base) MMIO32(uart_base + 0x24) /* UART Fractional baudrate divisor */ #define UART_FBRD(uart_base) MMIO32(uart_base + 0x28) /* UART Line control */ #define UART_LCRH(uart_base) MMIO32(uart_base + 0x2C) /* UART Control */ #define UART_CTL(uart_base) MMIO32(uart_base + 0x30) /* UART Interrupt FIFO level select */ #define UART_IFLS(uart_base) MMIO32(uart_base + 0x34) /* UART Interrupt mask */ #define UART_IM(uart_base) MMIO32(uart_base + 0x38) /* UART Raw interrupt status */ #define UART_RIS(uart_base) MMIO32(uart_base + 0x3C) /* UART Masked Interrupt status */ #define UART_MIS(uart_base) MMIO32(uart_base + 0x40) /* UART Interrupt Clear */ #define UART_ICR(uart_base) MMIO32(uart_base + 0x44) /* UART DMA control */ #define UART_DMACTL(uart_base) MMIO32(uart_base + 0x48) /* UART LIN control */ #define UART_LCTL(uart_base) MMIO32(uart_base + 0x90) /* UART LIN snap shot */ #define UART_LSS(uart_base) MMIO32(uart_base + 0x94) /* UART LIN timer */ #define UART_LTIM(uart_base) MMIO32(uart_base + 0x98) /* UART 9-Bit self address */ #define UART_9BITADDR(uart_base) MMIO32(uart_base + 0xA4) /* UART 9-Bit self address mask */ #define UART_9BITAMASK(uart_base) MMIO32(uart_base + 0xA8) /* UART Peripheral properties */ #define UART_PP(uart_base) MMIO32(uart_base + 0xFC0) /* UART Clock configuration */ #define UART_CC(uart_base) MMIO32(uart_base + 0xFC8) /* UART Peripheral Identification 4 */ #define UART_PERIPH_ID4(uart_base) MMIO32(uart_base + 0xFD0) /* UART Peripheral Identification 5 */ #define UART_PERIPH_ID5(uart_base) MMIO32(uart_base + 0xFD4) /* UART Peripheral Identification 6 */ #define UART_PERIPH_ID6(uart_base) MMIO32(uart_base + 0xFD8) /* UART Peripheral Identification 7 */ #define UART_PERIPH_ID7(uart_base) MMIO32(uart_base + 0xFDC) /* UART Peripheral Identification 0 */ #define UART_PERIPH_ID0(uart_base) MMIO32(uart_base + 0xFE0) /* UART Peripheral Identification 1 */ #define UART_PERIPH_ID1(uart_base) MMIO32(uart_base + 0xFE4) /* UART Peripheral Identification 2 */ #define UART_PERIPH_ID2(uart_base) MMIO32(uart_base + 0xFE8) /* UART Peripheral Identification 3 */ #define UART_PERIPH_ID3(uart_base) MMIO32(uart_base + 0xFEC) /* UART PrimeCell Identification 0 */ #define UART_PCELL_ID0(uart_base) MMIO32(uart_base + 0xFF0) /* UART PrimeCell Identification 1 */ #define UART_PCELL_ID1(uart_base) MMIO32(uart_base + 0xFF4) /* UART PrimeCell Identification 2 */ #define UART_PCELL_ID2(uart_base) MMIO32(uart_base + 0xFF8) /* UART PrimeCell Identification 3 */ #define UART_PCELL_ID3(uart_base) MMIO32(uart_base + 0xFFC) /* ============================================================================= * UART_DR values * ---------------------------------------------------------------------------*/ /** Overrun Error */ #define UART_DR_OE (1 << 11) /** Break Error */ #define UART_DR_BE (1 << 10) /** Parity Error */ #define UART_DR_PE (1 << 9) /** Framing Error */ #define UART_DR_FE (1 << 8) /** Data transmitted or received */ #define UART_DR_DATA_MASK (0xFF << 0) /* ============================================================================= * Readonly UART_RSR values * ---------------------------------------------------------------------------*/ /** Overrun Error */ #define UART_RSR_OE (1 << 3) /** Break Error */ #define UART_RSR_BE (1 << 2) /** Parity Error */ #define UART_RSR_PE (1 << 1) /** Framing Error */ #define UART_RSR_FE (1 << 0) /* ============================================================================= * UART_FR values * ---------------------------------------------------------------------------*/ /** Tx FIFO empty */ #define UART_FR_TXFE (1 << 7) /** Rx FIFO full */ #define UART_FR_RXFF (1 << 6) /** Tx FIFO full */ #define UART_FR_TXFF (1 << 5) /** Rx FIFO empty */ #define UART_FR_RXFE (1 << 4) /** UART Busy */ #define UART_FR_BUSY (1 << 3) /** Clear To Send */ #define UART_FR_CTS (1 << 0) /* ============================================================================= * UART_LCRH values * ---------------------------------------------------------------------------*/ /** Stick parity select */ #define UART_LCRH_SPS (1 << 7) /** Word length */ #define UART_LCRH_WLEN_MASK (3 << 5) #define UART_LCRH_WLEN_5 (0 << 5) #define UART_LCRH_WLEN_6 (1 << 5) #define UART_LCRH_WLEN_7 (2 << 5) #define UART_LCRH_WLEN_8 (3 << 5) /** Enable FIFOs */ #define UART_LCRH_FEN (1 << 4) /** Two stop bits select */ #define UART_LCRH_STP2 (1 << 3) /** Even parity select */ #define UART_LCRH_EPS (1 << 2) /** Parity enable */ #define UART_LCRH_PEN (1 << 1) /** Send break */ #define UART_LCRH_BRK (1 << 0) /* ============================================================================= * UART_CTL values * ---------------------------------------------------------------------------*/ /** Enable Clear To Send */ #define UART_CTL_CTSEN (1 << 15) /** Enable Request To Send */ #define UART_CTL_RTSEN (1 << 14) /** Request To Send */ #define UART_CTL_RTS (1 << 11) /** Data terminal ready */ #define UART_CTL_DTR (1 << 10) /** Rx Enable */ #define UART_CTL_RXE (1 << 9) /** Tx Enable */ #define UART_CTL_TXE (1 << 8) /** Loop back enable */ #define UART_CTL_LBE (1 << 7) /** LIN mode enable */ #define UART_CTL_LIN (1 << 6) /** High speed Enable */ #define UART_CTL_HSE (1 << 5) /** End of transmission */ #define UART_CTL_EOT (1 << 4) /** ISO 7816 Smart Card support */ #define UART_CTL_SMART (1 << 3) /** SIR low-power mode */ #define UART_CTL_SIRLIP (1 << 2) /** SIR enable */ #define UART_CTL_SIREN (1 << 1) /** UART enable */ #define UART_CTL_UARTEN (1 << 0) /* ============================================================================= * UART_IFLS values * ---------------------------------------------------------------------------*/ /** UART Rx interrupt FIFO level select */ #define UART_IFLS_RXIFLSEL_MASK (7 << 3) #define UART_IFLS_RXIFLSEL_1_8 (0 << 3) #define UART_IFLS_RXIFLSEL_1_4 (1 << 3) #define UART_IFLS_RXIFLSEL_1_2 (2 << 3) #define UART_IFLS_RXIFLSEL_3_4 (3 << 3) #define UART_IFLS_RXIFLSEL_7_8 (4 << 3) /** UART Tx interrupt FIFO level select */ #define UART_IFLS_TXIFLSEL_MASK (7 << 0) #define UART_IFLS_TXIFLSEL_7_8 (0 << 0) #define UART_IFLS_TXIFLSEL_3_4 (1 << 0) #define UART_IFLS_TXIFLSEL_1_2 (2 << 0) #define UART_IFLS_TXIFLSEL_1_4 (3 << 0) #define UART_IFLS_TXIFLSEL_1_8 (4 << 0) /* ============================================================================= * UART interrupt mask values * * These are interchangeable across UART_IM, UART_RIS, UART_MIS, and UART_ICR * registers. * ---------------------------------------------------------------------------*/ /** LIN mode edge 5 interrupt mask */ #define UART_IM_LME5IM (1 << 15) /** LIN mode edge 1 interrupt mask */ #define UART_IM_LME1IM (1 << 14) /** LIN mode sync break interrupt mask */ #define UART_IM_LMSBIM (1 << 13) /** 9-bit mode interrupt mask */ #define UART_IM_9BITIM (1 << 12) /** Overrun error interrupt mask */ #define UART_IM_OEIM (1 << 10) /** Break error interrupt mask */ #define UART_IM_BEIM (1 << 9) /** Parity error interrupt mask */ #define UART_IM_PEIM (1 << 8) /** Framing error interrupt mask */ #define UART_IM_FEIM (1 << 7) /** Receive time-out interrupt mask */ #define UART_IM_RTIM (1 << 6) /** Transmit interrupt mask */ #define UART_IM_TXIM (1 << 5) /** Receive interrupt mask */ #define UART_IM_RXIM (1 << 4) /** Data Set Ready modem interrupt mask */ #define UART_IM_DSRIM (1 << 3) /** Data Carrier Detect modem interrupt mask */ #define UART_IM_DCDIM (1 << 2) /** Clear To Send modem interrupt mask */ #define UART_IM_CTSIM (1 << 1) /** Ring Indicator modem interrupt mask */ #define UART_IM_RIIM (1 << 0) /* ============================================================================= * UART_DMACTL values * ---------------------------------------------------------------------------*/ /** DMA on error */ #define UART_DMACTL_DMAERR (1 << 2) /** Transmit DMA enable */ #define UART_DMACTL_TXDMAE (1 << 1) /** Recieve DMA enable */ #define UART_DMACTL_RXDMAE (1 << 0) /* ============================================================================= * UART_LCTL values * ---------------------------------------------------------------------------*/ /** Sync break length */ #define UART_LCTL_BLEN_MASK (3 << 4) #define UART_LCTL_BLEN_16T (3 << 4) #define UART_LCTL_BLEN_15T (2 << 4) #define UART_LCTL_BLEN_14T (1 << 4) #define UART_LCTL_BLEN_13T (0 << 4) /** LIN master enable */ #define UART_LCTL_MASTER (1 << 0) /* ============================================================================= * UART_9BITADDR values * ---------------------------------------------------------------------------*/ /** Enable 9-bit mode */ #define UART_UART_9BITADDR_9BITEN (1 << 15) /** Self-address for 9-bit mode */ #define UART_UART_9BITADDR_ADDR_MASK (0xFF << 0) /* ============================================================================= * UART_PP values * ---------------------------------------------------------------------------*/ /** 9-bit support */ #define UART_UART_PP_NB (1 << 1) /** Smart Card support */ #define UART_UART_PP_SC (1 << 0) /* ============================================================================= * UART_CC values * ---------------------------------------------------------------------------*/ /** UART baud clock source */ #define UART_CC_CS_MASK (0xF << 0) #define UART_CC_CS_SYSCLK (0x0 << 0) #define UART_CC_CS_PIOSC (0x5 << 0) /* ============================================================================= * Convenience enums * ---------------------------------------------------------------------------*/ enum uart_parity { UART_PARITY_NONE, UART_PARITY_ODD, UART_PARITY_EVEN, UART_PARITY_STICK_0, UART_PARITY_STICK_1, }; enum uart_flowctl { UART_FLOWCTL_NONE, UART_FLOWCTL_RTS, UART_FLOWCTL_CTS, UART_FLOWCTL_RTS_CTS, }; /** * \brief UART interrupt masks * * These masks can be OR'ed together to specify more than one interrupt. For * example, (UART_INT_TXIM | UART_INT_TXIM) specifies both Rx and Tx Interrupt. */ enum uart_interrupt_flag { UART_INT_LME5 = UART_IM_LME5IM, UART_INT_LME1 = UART_IM_LME1IM, UART_INT_LMSB = UART_IM_LMSBIM, UART_INT_9BIT = UART_IM_9BITIM, UART_INT_OE = UART_IM_OEIM, UART_INT_BE = UART_IM_BEIM, UART_INT_PE = UART_IM_PEIM, UART_INT_FE = UART_IM_FEIM, UART_INT_RT = UART_IM_RTIM, UART_INT_TX = UART_IM_TXIM, UART_INT_RX = UART_IM_RXIM, UART_INT_DSR = UART_IM_DSRIM, UART_INT_DCD = UART_IM_DCDIM, UART_INT_CTS = UART_IM_CTSIM, UART_INT_RI = UART_IM_RIIM, }; /** * \brief UART RX FIFO interrupt trigger levels * * The levels indicate how full the FIFO should be before an interrupt is * generated. UART_FIFO_RX_TRIG_3_4 means that an interrupt is triggered when * the FIFO is 3/4 full. As the FIFO is 8 elements deep, 1/8 is equal to being * triggered by a single character. */ enum uart_fifo_rx_trigger_level { UART_FIFO_RX_TRIG_1_8 = UART_IFLS_RXIFLSEL_1_8, UART_FIFO_RX_TRIG_1_4 = UART_IFLS_RXIFLSEL_1_4, UART_FIFO_RX_TRIG_1_2 = UART_IFLS_RXIFLSEL_1_2, UART_FIFO_RX_TRIG_3_4 = UART_IFLS_RXIFLSEL_3_4, UART_FIFO_RX_TRIG_7_8 = UART_IFLS_RXIFLSEL_7_8 }; /** * \brief UART TX FIFO interrupt trigger levels * * The levels indicate how empty the FIFO should be before an interrupt is * generated. Note that this indicates the emptiness of the FIFO and not the * fullness. This is somewhat confusing, but it follows the wording of the * LM4F120H5QR datasheet. * * UART_FIFO_TX_TRIG_3_4 means that an interrupt is triggered when the FIFO is * 3/4 empty. As the FIFO is 8 elements deep, 7/8 is equal to being triggered * by a single character. */ enum uart_fifo_tx_trigger_level { UART_FIFO_TX_TRIG_7_8 = UART_IFLS_TXIFLSEL_7_8, UART_FIFO_TX_TRIG_3_4 = UART_IFLS_TXIFLSEL_3_4, UART_FIFO_TX_TRIG_1_2 = UART_IFLS_TXIFLSEL_1_2, UART_FIFO_TX_TRIG_1_4 = UART_IFLS_TXIFLSEL_1_4, UART_FIFO_TX_TRIG_1_8 = UART_IFLS_TXIFLSEL_1_8 }; /* ============================================================================= * Function prototypes * ---------------------------------------------------------------------------*/ BEGIN_DECLS void uart_set_baudrate(uint32_t uart, uint32_t baud); void uart_set_databits(uint32_t uart, uint8_t databits); void uart_set_stopbits(uint32_t uart, uint8_t stopbits); void uart_set_parity(uint32_t uart, enum uart_parity parity); void uart_set_mode(uint32_t uart, uint32_t mode); void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow); void uart_enable(uint32_t uart); void uart_disable(uint32_t uart); void uart_clock_from_piosc(uint32_t uart); void uart_clock_from_sysclk(uint32_t uart); void uart_send(uint32_t uart, uint16_t data); uint16_t uart_recv(uint32_t uart); void uart_wait_send_ready(uint32_t uart); void uart_wait_recv_ready(uint32_t uart); void uart_send_blocking(uint32_t uart, uint16_t data); uint16_t uart_recv_blocking(uint32_t uart); void uart_enable_rx_dma(uint32_t uart); void uart_disable_rx_dma(uint32_t uart); void uart_enable_tx_dma(uint32_t uart); void uart_disable_tx_dma(uint32_t uart); void uart_enable_fifo(uint32_t uart); void uart_disable_fifo(uint32_t uart); void uart_set_fifo_trigger_levels(uint32_t uart, enum uart_fifo_rx_trigger_level rx_level, enum uart_fifo_tx_trigger_level tx_level); /* We inline FIFO full/empty checks as they are intended to be called from ISRs * */ /** @ingroup uart_fifo * @{ * \brief Determine if the TX fifo is full * * @param[in] uart UART block register address base @ref uart_reg_base */ static inline bool uart_is_tx_fifo_full(uint32_t uart) { return UART_FR(uart) & UART_FR_TXFF; } /** * \brief Determine if the TX fifo is empty * * @param[in] uart UART block register address base @ref uart_reg_base */ static inline bool uart_is_tx_fifo_empty(uint32_t uart) { return UART_FR(uart) & UART_FR_TXFE; } /** * \brief Determine if the RX fifo is full * * @param[in] uart UART block register address base @ref uart_reg_base */ static inline bool uart_is_rx_fifo_full(uint32_t uart) { return UART_FR(uart) & UART_FR_RXFF; } /** * \brief Determine if the RX fifo is empty * * @param[in] uart UART block register address base @ref uart_reg_base */ static inline bool uart_is_rx_fifo_empty(uint32_t uart) { return UART_FR(uart) & UART_FR_RXFE; } /**@}*/ void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints); void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints); void uart_enable_rx_interrupt(uint32_t uart); void uart_disable_rx_interrupt(uint32_t uart); void uart_enable_tx_interrupt(uint32_t uart); void uart_disable_tx_interrupt(uint32_t uart); void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints); /* Let's keep this one inlined. It's designed to be used in ISRs */ /** @ingroup uart_irq * @{ * \brief Determine if interrupt is generated by the given source * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] source source to check. */ static inline bool uart_is_interrupt_source(uint32_t uart, enum uart_interrupt_flag source) { return UART_MIS(uart) & source; } /**@}*/ END_DECLS /**@}*/ #endif /* LIBOPENCM3_LM4F_UART_H */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lm4f/usb.h000066400000000000000000000332451435536612600227620ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @defgroup usb_defines USB Controller * * @brief Defined Constants and Types for the LM4F USB Controller * * @ingroup LM4Fxx_defines * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc * * @date 15 May 2013 * * LGPL License Terms @ref lgpl_license */ #ifndef LIBOPENCM3_LM4F_USB_H #define LIBOPENCM3_LM4F_USB_H /**@{*/ #include #include /* ============================================================================ * USB registers * --------------------------------------------------------------------------*/ /* USB Device Functional Address */ #define USB_FADDR MMIO8(USB_BASE + 0x00) /* USB Power */ #define USB_POWER MMIO8(USB_BASE + 0x01) /* USB Transmit Interrupt Status */ #define USB_TXIS MMIO16(USB_BASE + 0x02) /* USB Receive Interrupt Status */ #define USB_RXIS MMIO16(USB_BASE + 0x04) /* USB Transmit Interrupt Enable */ #define USB_TXIE MMIO16(USB_BASE + 0x06) /* USB Receive Interrupt Enable */ #define USB_RXIE MMIO16(USB_BASE + 0x08) /* USB General Interrupt Status */ #define USB_IS MMIO8(USB_BASE + 0x0A) /* USB Interrupt Enable */ #define USB_IE MMIO8(USB_BASE + 0x0B) /* USB Frame Value */ #define USB_FRAME MMIO16(USB_BASE + 0x0C) /* USB Endpoint Index */ #define USB_EPIDX MMIO8(USB_BASE + 0x0E) /* USB Test Mode */ #define USB_TEST MMIO8(USB_BASE + 0x0F) /* USB FIFO Endpoint [0-7] */ #define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04) #define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + n*0x04) #define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04) /* USB Transmit Dynamic FIFO Sizing */ #define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62) /* USB Receive Dynamic FIFO Sizing */ #define USB_RXFIFOSZ MMIO8(USB_BASE + 0x63) /* USB Transmit FIFO Start Address */ #define USB_TXFIFOADD MMIO16(USB_BASE + 0x64) /* USB Receive FIFO Start Address */ #define USB_RXFIFOADD MMIO16(USB_BASE + 0x66) /* USB Connect Timing */ #define USB_CONTIM MMIO8(USB_BASE + 0x7A) /* USB Full-Speed Last Transaction to End of Frame Timing */ #define USB_FSEOF MMIO8(USB_BASE + 0x7D) /* USB Low-Speed Last Transaction to End of Frame Timing */ #define USB_LSEOF MMIO8(USB_BASE + 0x7E) /* USB Control and Status Endpoint 0 Low */ #define USB_CSRL0 MMIO8(USB_BASE + 0x102) /* USB Control and Status Endpoint 0 High */ #define USB_CSRH0 MMIO8(USB_BASE + 0x103) /* USB Receive Byte Count Endpoint 0 */ #define USB_COUNT0 MMIO8(USB_BASE + 0x108) /* USB Maximum Transmit Data Endpoint [1-7] */ #define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10) /* USB Transmit Control and Status Endpoint [1-7] Low */ #define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + n*0x10) /* USB Transmit Control and Status Endpoint [1-7] High */ #define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + n*0x10) /* USB Maximum Receive Data Endpoint [1-7] */ #define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10) /* USB Receive Control and Status Endpoint [1-7] Low */ #define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + n*0x10) /* USB Receive Control and Status Endpoint [1-7] High */ #define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + n*0x10) /* USB Receive Byte Count Endpoint [1-7] */ #define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10) /* USB Receive Double Packet Buffer Disable */ #define USB_RXDPKTBUFDIS MMIO16(USB_BASE + 0x340) /* USB Transmit Double Packet Buffer Disable */ #define USB_TXDPKTBUFDIS MMIO16(USB_BASE + 0x342) /* USB Device RESUME Raw Interrupt Status */ #define USB_DRRIS MMIO32(USB_BASE + 0x410) /* USB Device RESUME Interrupt Mask */ #define USB_DRIM MMIO32(USB_BASE + 0x414) /* USB Device RESUME Interrupt Status and Clear */ #define USB_DRISC MMIO32(USB_BASE + 0x418) /* USB DMA Select */ #define USB_DMASEL MMIO32(USB_BASE + 0x450) /* USB Peripheral Properties */ #define USB_PP MMIO32(USB_BASE + 0xFC0) /* ============================================================================= * USB_FADDR values * ---------------------------------------------------------------------------*/ /** Function Address */ #define USB_FADDR_FUNCADDR_MASK (0x3f << 0) /* ============================================================================= * USB_POWER values * ---------------------------------------------------------------------------*/ /** Isochronous Update */ #define USB_POWER_ISOUP (1 << 7) /** Soft Connect/Disconnect */ #define USB_POWER_SOFTCONN (1 << 6) /** RESET signaling */ #define USB_POWER_RESET (1 << 3) /** RESUME signaling */ #define USB_POWER_RESUME (1 << 2) /** SUSPEND mode */ #define USB_POWER_SUSPEND (1 << 1) /** Power down PHY */ #define USB_POWER_PWRDNPHY (1 << 0) /* ============================================================================= * Endpoint bitmasks for interrupt status and control registers * Applies to USB_TXIS, USB_RXIS, USB_TXIE, USB_RXIE, USB_RXDPKTBUFDIS, * USB_TXDPKTBUFDIS * ---------------------------------------------------------------------------*/ #define USB_EP7 (1 << 7) #define USB_EP6 (1 << 6) #define USB_EP5 (1 << 5) #define USB_EP4 (1 << 4) #define USB_EP3 (1 << 3) #define USB_EP2 (1 << 2) #define USB_EP1 (1 << 1) #define USB_EP0 (1 << 0) /* ============================================================================= * USB interrupt mask values * * These are interchangeable across USB_IS, and USB_IE registers. * ---------------------------------------------------------------------------*/ /** USB disconnect interrupt */ #define USB_IM_DISCON (1 << 5) /** Start of frame */ #define USB_IM_SOF (1 << 3) /** RESET signaling detected */ #define USB_IM_RESET (1 << 2) /** RESUME signaling detected */ #define USB_IM_RESUME (1 << 1) /** SUSPEND signaling detected */ #define USB_IM_SUSPEND (1 << 0) /* ============================================================================= * USB_FRAME values * ---------------------------------------------------------------------------*/ /** Frame number */ #define USB_FRAME_MASK (0x03FF) /* ============================================================================= * USB_IDX values * ---------------------------------------------------------------------------*/ /** Endpoint Index */ #define USB_EPIDX_MASK (0x0F) /* ============================================================================= * USB_TEST values * ---------------------------------------------------------------------------*/ /** FIFO access */ #define USB_TEST_FIFOACC (1 << 6) /** Force full-speed mode */ #define USB_TEST_FORCEFS (1 << 5) /* ============================================================================= * USB_TXFIFOSZ and USB_RXFIFOSZ values * ---------------------------------------------------------------------------*/ /** Double packet buffer support */ #define USB_FIFOSZ_DPB (1 << 4) /* USB Transmit Dynamic FIFO Sizing */ #define USB_FIFOSZ_SIZE_MASK (0x0F << 0) #define USB_FIFOSZ_SIZE_8 (0x00 << 0) #define USB_FIFOSZ_SIZE_16 (0x01 << 0) #define USB_FIFOSZ_SIZE_32 (0x02 << 0) #define USB_FIFOSZ_SIZE_64 (0x03 << 0) #define USB_FIFOSZ_SIZE_128 (0x04 << 0) #define USB_FIFOSZ_SIZE_256 (0x05 << 0) #define USB_FIFOSZ_SIZE_512 (0x06 << 0) #define USB_FIFOSZ_SIZE_1024 (0x07 << 0) #define USB_FIFOSZ_SIZE_2048 (0x08 << 0) /* ============================================================================= * USB_CONTIM values * ---------------------------------------------------------------------------*/ /** Connect wait */ #define USB_CONTIM_WTCON_MASK (0x0F << 4) /** Wait ID */ #define USB_CONTIM_WTID_MASK (0x0F << 0) /* ============================================================================= * USB_CSRL0 values * ---------------------------------------------------------------------------*/ /** Setup End Clear */ #define USB_CSRL0_SETENDC (1 << 7) /** RXRDY Clear */ #define USB_CSRL0_RXRDYC (1 << 6) /** Send Stall */ #define USB_CSRL0_STALL (1 << 5) /** Setup End */ #define USB_CSRL0_SETEND (1 << 4) /** Data End */ #define USB_CSRL0_DATAEND (1 << 3) /** Endpoint Stalled */ #define USB_CSRL0_STALLED (1 << 2) /** Transmit Packet Ready */ #define USB_CSRL0_TXRDY (1 << 1) /** Receive Packet Ready */ #define USB_CSRL0_RXRDY (1 << 0) /* ============================================================================= * USB_CSRH0 values * ---------------------------------------------------------------------------*/ /** Flush FIFO */ #define USB_CSRH0_FLUSH (1 << 0) /* ============================================================================= * USB_TXCSRLx values * ---------------------------------------------------------------------------*/ /** Clear data toggle */ #define USB_TXCSRL_CLRDT (1 << 6) /** Endpoint Stalled */ #define USB_TXCSRL_STALLED (1 << 5) /** Send Stall */ #define USB_TXCSRL_STALL (1 << 4) /** Flush FIFO */ #define USB_TXCSRL_FLUSH (1 << 3) /** Underrun */ #define USB_TXCSRL_UNDRN (1 << 2) /** FIFO not empty */ #define USB_TXCSRL_FIFONE (1 << 1) /** Transmit Packet Ready */ #define USB_TXCSRL_TXRDY (1 << 0) /* ============================================================================= * USB_TXCSRHx values * ---------------------------------------------------------------------------*/ /** Auto set */ #define USB_TXCSRH_AUTOSET (1 << 7) /** Isochronous transfers */ #define USB_TXCSRH_ISO (1 << 6) /** Mode */ #define USB_TXCSRH_MODE (1 << 5) /** DMA request enable */ #define USB_TXCSRH_DMAEN (1 << 4) /** Force data toggle */ #define USB_TXCSRH_FDT (1 << 3) /** DMA request mode */ #define USB_TXCSRH_DMAMOD (1 << 2) /* ============================================================================= * USB_RXCSRLx values * ---------------------------------------------------------------------------*/ /** Clear data toggle */ #define USB_RXCSRL_CLRDT (1 << 7) /** Endpoint Stalled */ #define USB_RXCSRL_STALLED (1 << 6) /** Send Stall */ #define USB_RXCSRL_STALL (1 << 5) /** Flush FIFO */ #define USB_RXCSRL_FLUSH (1 << 4) /** Data error */ #define USB_RXCSRL_DATAERR (1 << 2) /** Overrun */ #define USB_RXCSRL_OVER (1 << 2) /** FIFO full */ #define USB_RXCSRL_FULL (1 << 1) /** Receive Packet Ready */ #define USB_RXCSRL_RXRDY (1 << 0) /* ============================================================================= * USB_RXCSRHx values * ---------------------------------------------------------------------------*/ /** Auto clear */ #define USB_RXCSRH_AUTOCL (1 << 7) /** Isochronous transfers */ #define USB_RXCSRH_ISO (1 << 6) /** DMA request enable */ #define USB_RXCSRH_DMAEN (1 << 5) /** Disable NYET / PID error */ #define USB_RXCSRH_PIDERR (1 << 4) /** DMA request mode */ #define USB_RXCSRH_DMAMOD (1 << 3) /* ============================================================================= * USB_DRRIS values * ---------------------------------------------------------------------------*/ /** RESUME interrupt status */ #define USB_DRRIS_RESUME (1 << 0) /* ============================================================================= * USB_DRIM values * ---------------------------------------------------------------------------*/ /** RESUME interrupt mask */ #define USB_DRIM_RESUME (1 << 0) /* ============================================================================= * USB_DRISC values * ---------------------------------------------------------------------------*/ /** RESUME interrupt status and clear */ #define USB_DRISC_RESUME (1 << 0) /* ============================================================================= * USB_PP values * ---------------------------------------------------------------------------*/ /** Endpoint count */ #define USB_PP_ECNT_MASK (0xFF << 8) /** USB capability */ #define USB_PP_USB_MASK (0x03 << 6) #define USB_PP_USB_NA (0x00 << 6) #define USB_PP_USB_DEVICE (0x01 << 6) #define USB_PP_USB_HOST (0x02 << 6) #define USB_PP_USB_OTG (0x03 << 6) /** PHY present */ #define USB_PP_PHY (1 << 4) /** Controller type */ #define USB_PP_TYPE_MASK (0x0F << 0) /* ============================================================================= * Convenience enums * ---------------------------------------------------------------------------*/ enum usb_interrupt { USB_INT_DISCON = USB_IM_DISCON, USB_INT_SOF = USB_IM_SOF, USB_INT_RESET = USB_IM_RESET, USB_INT_RESUME = USB_IM_RESUME, USB_INT_SUSPEND = USB_IM_SUSPEND, }; enum usb_ep_interrupt { USB_EP0_INT = USB_EP0, USB_EP1_INT = USB_EP1, USB_EP2_INT = USB_EP2, USB_EP3_INT = USB_EP3, USB_EP4_INT = USB_EP4, USB_EP5_INT = USB_EP5, USB_EP6_INT = USB_EP6, USB_EP7_INT = USB_EP7, }; /* ============================================================================= * Function prototypes * ---------------------------------------------------------------------------*/ BEGIN_DECLS void usb_enable_interrupts(enum usb_interrupt ints, enum usb_ep_interrupt rx_ints, enum usb_ep_interrupt tx_ints); void usb_disable_interrupts(enum usb_interrupt ints, enum usb_ep_interrupt rx_ints, enum usb_ep_interrupt tx_ints); END_DECLS /**@}*/ #endif /* LIBOPENCM3_LM4F_USB_H */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc13xx/000077500000000000000000000000001435536612600224515ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc13xx/doc-lpc13xx.h000066400000000000000000000010261435536612600246660ustar00rootroot00000000000000/** @mainpage libopencm3 LPC13xx @version 1.0.0 @date 14 September 2012 API documentation for NXP Semiconductors LPC13xx Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup LPC13xx LPC13xx Libraries for NXP Semiconductors LPC13xx series. @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup LPC13xx_defines LPC13xx Defines @brief Defined Constants and Types for the LPC13xx series @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc13xx/gpio.h000066400000000000000000000074041435536612600235650ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines @brief Defined Constants and Types for the LPC13xx General Purpose I/O @ingroup LPC13xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LPC13XX_GPIO_H #define LPC13XX_GPIO_H #include #include /* --- Convenience macros -------------------------------------------------- */ /* GPIO port base addresses (for convenience) */ #define GPIO0 GPIO_PIO0_BASE #define GPIO1 GPIO_PIO1_BASE #define GPIO2 GPIO_PIO2_BASE #define GPIO3 GPIO_PIO3_BASE /* --- GPIO registers ------------------------------------------------------ */ /* GPIO data register (GPIOn_DATA) */ #define GPIO_DATA(port) MMIO32(port + 0x3ffc) #define GPIO0_DATA GPIO_DATA(GPIO0) #define GPIO1_DATA GPIO_DATA(GPIO1) #define GPIO2_DATA GPIO_DATA(GPIO2) #define GPIO3_DATA GPIO_DATA(GPIO3) /* GPIO data direction register (GPIOn_DIR) */ #define GPIO_DIR(port) MMIO32(port + 0x00) #define GPIO0_DIR GPIO_DIR(GPIO0) #define GPIO1_DIR GPIO_DIR(GPIO1) #define GPIO2_DIR GPIO_DIR(GPIO2) #define GPIO3_DIR GPIO_DIR(GPIO3) /* GPIO interrupt sense register (GPIOn_IS) */ #define GPIO_IS(port) MMIO32(port + 0x04) #define GPIO0_IS GPIO_IS(GPIO0) #define GPIO1_IS GPIO_IS(GPIO1) #define GPIO2_IS GPIO_IS(GPIO2) #define GPIO3_IS GPIO_IS(GPIO3) /* GPIO interrupt both edges sense register (GPIOn_IBE) */ #define GPIO_IBE(port) MMIO32(port + 0x08) #define GPIO0_IBE GPIO_IBE(GPIO0) #define GPIO1_IBE GPIO_IBE(GPIO1) #define GPIO2_IBE GPIO_IBE(GPIO2) #define GPIO3_IBE GPIO_IBE(GPIO3) /* GPIO interrupt event register (GPIOn_IEV) */ #define GPIO_IEV(port) MMIO32(port + 0x0c) #define GPIO0_IEV GPIO_IEV(GPIO0) #define GPIO1_IEV GPIO_IEV(GPIO1) #define GPIO2_IEV GPIO_IEV(GPIO2) #define GPIO3_IEV GPIO_IEV(GPIO3) /* GPIO interrupt mask register (GPIOn_IE) */ #define GPIO_IE(port) MMIO16(port + 0x10) #define GPIO0_IE GPIO_IE(GPIO0) #define GPIO1_IE GPIO_IE(GPIO1) #define GPIO2_IE GPIO_IE(GPIO2) #define GPIO3_IE GPIO_IE(GPIO3) /* FIXME: IRS or RIS? Datasheet is not consistent here. */ /* GPIO raw interrupt status register (GPIOn_IRS) */ #define GPIO_IRS(port) MMIO16(port + 0x14) #define GPIO0_IRS GPIO_IRS(GPIO0) #define GPIO1_IRS GPIO_IRS(GPIO1) #define GPIO2_IRS GPIO_IRS(GPIO2) #define GPIO3_IRS GPIO_IRS(GPIO3) /* GPIO masked interrupt status register (GPIOn_MIS) */ #define GPIO_MIS(port) MMIO16(port + 0x18) #define GPIO0_MIS GPIO_MIS(GPIO0) #define GPIO1_MIS GPIO_MIS(GPIO1) #define GPIO2_MIS GPIO_MIS(GPIO2) #define GPIO3_MIS GPIO_MIS(GPIO3) /* GPIO interrupt clear register (GPIOn_IC) */ #define GPIO_IC(port) MMIO16(port + 0x1c) #define GPIO0_IC GPIO_IC(GPIO0) #define GPIO1_IC GPIO_IC(GPIO1) #define GPIO2_IC GPIO_IC(GPIO2) #define GPIO3_IC GPIO_IC(GPIO3) BEGIN_DECLS void gpio_set(uint32_t gpioport, uint16_t gpios); END_DECLS /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc13xx/irq.yaml000066400000000000000000000015051435536612600241310ustar00rootroot00000000000000includeguard: LIBOPENCM3_LPC13xx_NVIC_H partname_humanreadable: LPC 13xx series partname_doxygen: LPC13xx irqs: 0: pio0_0 1: pio0_1 2: pio0_2 3: pio0_3 4: pio0_4 5: pio0_5 6: pio0_6 7: pio0_7 8: pio0_8 9: pio0_9 10: pio0_10 11: pio0_11 12: pio1_0 13: pio1_1 14: pio1_2 15: pio1_3 16: pio1_4 17: pio1_5 18: pio1_6 19: pio1_7 20: pio1_8 21: pio1_9 22: pio1_10 23: pio1_11 24: pio2_0 25: pio2_1 26: pio2_2 27: pio2_3 28: pio2_4 29: pio2_5 30: pio2_6 31: pio2_7 32: pio2_8 33: pio2_9 34: pio2_10 35: pio2_11 36: pio3_0 37: pio3_1 38: pio3_2 39: pio3_3 40: i2c0 41: ct16b0 42: ct16b1 43: ct32b0 44: ct32b1 45: ssp0 46: uart 47: usb 48: usb_fiq 49: adc 50: wdt 51: bod # 52: reserved 53: pio3 54: pio2 55: pio1 56: pio0 56: ssp1 hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc13xx/memorymap.h000066400000000000000000000043151435536612600246330ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC13XX_MEMORYMAP_H #define LPC13XX_MEMORYMAP_H #include /* --- LPC13XX specific peripheral definitions ----------------------------- */ /* Memory map for all busses */ #define PERIPH_BASE_APB 0x40000000 #define PERIPH_BASE_AHB 0x50000000 /* Register boundary addresses */ /* APB */ #define I2C_BASE (PERIPH_BASE_APB + 0x00000) #define WDT_BASE (PERIPH_BASE_APB + 0x04000) #define UART_BASE (PERIPH_BASE_APB + 0x08000) #define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000) #define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000) #define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000) #define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000) #define ADC_BASE (PERIPH_BASE_APB + 0x1c000) #define USB_BASE (PERIPH_BASE_APB + 0x20000) /* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */ #define PMU_BASE (PERIPH_BASE_APB + 0x38000) #define FLASH_BASE (PERIPH_BASE_APB + 0x3c000) #define SSP_BASE (PERIPH_BASE_APB + 0x40000) #define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000) #define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000) /* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */ /* AHB */ #define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000) #define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000) #define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000) #define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000) /* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc17xx/000077500000000000000000000000001435536612600224555ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc17xx/doc-lpc17xx.h000066400000000000000000000010261435536612600246760ustar00rootroot00000000000000/** @mainpage libopencm3 LPC17xx @version 1.0.0 @date 14 September 2012 API documentation for NXP Semiconductors LPC17xx Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup LPC17xx LPC17xx Libraries for NXP Semiconductors LPC17xx series. @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup LPC17xx_defines LPC17xx Defines @brief Defined Constants and Types for the LPC17xx series @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc17xx/gpio.h000066400000000000000000000132451435536612600235710ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines @brief Defined Constants and Types for the LPC17xx General Purpose I/O @ingroup LPC17xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC17XX_GPIO_H #define LPC17XX_GPIO_H /**@{*/ #include #include /* --- Convenience macros -------------------------------------------------- */ /* GPIO port base addresses (for convenience) */ #define GPIO0 GPIO_PIO0_BASE #define GPIO1 GPIO_PIO1_BASE #define GPIO2 GPIO_PIO2_BASE #define GPIO3 GPIO_PIO3_BASE #define GPIO4 GPIO_PIO4_BASE /* GPIO number definitions (for convenience) */ #define GPIOPIN0 (1 << 0) #define GPIOPIN1 (1 << 1) #define GPIOPIN2 (1 << 2) #define GPIOPIN3 (1 << 3) #define GPIOPIN4 (1 << 4) #define GPIOPIN5 (1 << 5) #define GPIOPIN6 (1 << 6) #define GPIOPIN7 (1 << 7) #define GPIOPIN8 (1 << 8) #define GPIOPIN9 (1 << 9) #define GPIOPIN10 (1 << 10) #define GPIOPIN11 (1 << 11) #define GPIOPIN12 (1 << 12) #define GPIOPIN13 (1 << 13) #define GPIOPIN14 (1 << 14) #define GPIOPIN15 (1 << 15) #define GPIOPIN16 (1 << 16) #define GPIOPIN17 (1 << 17) #define GPIOPIN18 (1 << 18) #define GPIOPIN19 (1 << 19) #define GPIOPIN20 (1 << 20) #define GPIOPIN21 (1 << 21) #define GPIOPIN22 (1 << 22) #define GPIOPIN23 (1 << 23) #define GPIOPIN24 (1 << 24) #define GPIOPIN25 (1 << 25) #define GPIOPIN26 (1 << 26) #define GPIOPIN27 (1 << 27) #define GPIOPIN28 (1 << 28) #define GPIOPIN29 (1 << 29) #define GPIOPIN30 (1 << 30) #define GPIOPIN31 (1 << 31) /* --- GPIO registers ------------------------------------------------------ */ /* GPIO data direction register (GPIOn_DIR) */ #define GPIO_DIR(port) MMIO32(port + 0x00) #define GPIO0_DIR GPIO_DIR(GPIO0) #define GPIO1_DIR GPIO_DIR(GPIO1) #define GPIO2_DIR GPIO_DIR(GPIO2) #define GPIO3_DIR GPIO_DIR(GPIO3) #define GPIO4_DIR GPIO_DIR(GPIO4) /* GPIO fast mask register (GPIOn_DIR) */ #define GPIO_MASK(port) MMIO32(port + 0x10) #define GPIO0_MASK GPIO_MASK(GPIO0) #define GPIO1_MASK GPIO_MASK(GPIO1) #define GPIO2_MASK GPIO_MASK(GPIO2) #define GPIO3_MASK GPIO_MASK(GPIO3) #define GPIO4_MASK GPIO_MASK(GPIO4) /* GPIO port pin value register (GPIOn_PIN) */ #define GPIO_PIN(port) MMIO32(port + 0x14) #define GPIO0_PIN GPIO_PIN(GPIO0) #define GPIO1_PIN GPIO_PIN(GPIO1) #define GPIO2_PIN GPIO_PIN(GPIO2) #define GPIO3_PIN GPIO_PIN(GPIO3) #define GPIO4_PIN GPIO_PIN(GPIO4) /* GPIO port output set register (GPIOn_SET) */ #define GPIO_SET(port) MMIO32(port + 0x18) #define GPIO0_SET GPIO_SET(GPIO0) #define GPIO1_SET GPIO_SET(GPIO1) #define GPIO2_SET GPIO_SET(GPIO2) #define GPIO3_SET GPIO_SET(GPIO3) #define GPIO4_SET GPIO_SET(GPIO4) /* GPIO port output clear register (GPIOn_CLR) */ #define GPIO_CLR(port) MMIO32(port + 0x1C) #define GPIO0_CLR GPIO_CLR(GPIO0) #define GPIO1_CLR GPIO_CLR(GPIO1) #define GPIO2_CLR GPIO_CLR(GPIO2) #define GPIO3_CLR GPIO_CLR(GPIO3) #define GPIO4_CLR GPIO_CLR(GPIO4) /* GPIO interrupt register map */ /* Interrupt enable rising edge */ #define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90) #define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0) /* Interrupt enable falling edge */ #define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94) #define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4) /* Interrupt status rising edge */ #define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84) #define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4) /* Interrupt status falling edge */ #define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88) #define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8) /* Interrupt clear */ #define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C) #define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC) /* Overall interrupt status */ #define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80) BEGIN_DECLS void gpio_set(uint32_t gpioport, uint32_t gpios); void gpio_clear(uint32_t gpioport, uint32_t gpios); END_DECLS /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc17xx/irq.yaml000066400000000000000000000007741435536612600241440ustar00rootroot00000000000000includeguard: LIBOPENCM3_LPC17xx_NVIC_H partname_humanreadable: LPC 17xx series partname_doxygen: LPC17xx irqs: 0: wdt 1: timer0 2: timer1 3: timer2 4: timer3 5: uart0 6: uart1 7: uart2 8: uart3 9: pwm 10: i2c0 11: i2c1 12: i2c2 13: spi 14: ssp0 15: ssp1 16: pll0 17: rtc 18: eint0 19: eint1 20: eint2 21: eint3 22: adc 23: bod 24: usb 25: can 26: gpdma 27: i2s 28: ethernet 29: rit 30: motor_pwm 31: qei 32: pll1 33: usb_act 34: can_act hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc17xx/memorymap.h000066400000000000000000000050571435536612600246430ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC17XX_MEMORYMAP_H #define LPC17XX_MEMORYMAP_H #include /* --- LPC17XX specific peripheral definitions ----------------------------- */ /* Memory map for all busses */ #define PERIPH_BASE_APB0 0x40000000 #define PERIPH_BASE_APB1 0x40080000 #define PERIPH_BASE_AHB 0x20000000 /* Register boundary addresses */ /* APB0 */ #define WDT_BASE (PERIPH_BASE_APB0 + 0x00000) #define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) #define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000) #define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000) #define UART1_BASE (PERIPH_BASE_APB0 + 0x10000) /* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */ #define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000) #define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000) #define SPI_BASE (PERIPH_BASE_APB0 + 0x20000) #define RTC_BASE (PERIPH_BASE_APB0 + 0x24000) #define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000) #define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000) #define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000) #define ADC_BASE (PERIPH_BASE_APB0 + 0x34000) #define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000) #define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000) #define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000) #define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000) #define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000) /* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */ #define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000) /* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */ /* AHB */ #define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000) #define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020) #define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040) #define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060) #define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/000077500000000000000000000000001435536612600224545ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/adc.h000066400000000000000000000121001435536612600233460ustar00rootroot00000000000000/** @defgroup adc_defines ADC Defines @brief Defined Constants and Types for the LPC43xx A/D Converter @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_ADC_H #define LPC43XX_ADC_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* ADC port base addresses (for convenience) */ #define ADC0 ADC0_BASE #define ADC1 ADC1_BASE /* --- ADC registers ------------------------------------------------------- */ /* A/D Control Register */ #define ADC_CR(port) MMIO32(port + 0x000) #define ADC0_CR ADC_CR(ADC0) #define ADC1_CR ADC_CR(ADC1) #define ADC_CR_SEL_SHIFT (0) #define ADC_CR_SEL(x) ((x) << ADC_CR_SEL_SHIFT) #define ADC_CR_CLKDIV_SHIFT (8) #define ADC_CR_CLKDIV(x) ((x) << ADC_CR_CLKDIV_SHIFT) #define ADC_CR_BURST_SHIFT (16) #define ADC_CR_BURST (1 << ADC_CR_BURST_SHIFT) #define ADC_CR_CLKS_SHIFT (17) #define ADC_CR_CLKS(x) ((x) << ADC_CR_CLKS_SHIFT) #define ADC_CR_PDN_SHIFT (21) #define ADC_CR_PDN (1 << ADC_CR_PDN_SHIFT) #define ADC_CR_START_SHIFT (24) #define ADC_CR_START(x) ((x) << ADC_CR_START_SHIFT) #define ADC_CR_EDGE_SHIFT (27) #define ADC_CR_EDGE (1 << ADC_CR_EDGE_SHIFT) /* A/D Global Data Register */ #define ADC_GDR(port) MMIO32(port + 0x004) #define ADC0_GDR ADC_GDR(ADC0) #define ADC1_GDR ADC_GDR(ADC1) /* A/D Interrupt Enable Register */ #define ADC_INTEN(port) MMIO32(port + 0x00C) #define ADC0_INTEN ADC_INTEN(ADC0) #define ADC1_INTEN ADC_INTEN(ADC1) /* A/D Channel 0 Data Register */ #define ADC_DR0(port) MMIO32(port + 0x010) #define ADC0_DR0 ADC_DR0(ADC0) #define ADC1_DR0 ADC_DR0(ADC1) /* A/D Channel 1 Data Register */ #define ADC_DR1(port) MMIO32(port + 0x014) #define ADC0_DR1 ADC_DR1(ADC0) #define ADC1_DR1 ADC_DR1(ADC1) /* A/D Channel 2 Data Register */ #define ADC_DR2(port) MMIO32(port + 0x018) #define ADC0_DR2 ADC_DR2(ADC0) #define ADC1_DR2 ADC_DR2(ADC1) /* A/D Channel 3 Data Register */ #define ADC_DR3(port) MMIO32(port + 0x01C) #define ADC0_DR3 ADC_DR3(ADC0) #define ADC1_DR3 ADC_DR3(ADC1) /* A/D Channel 4 Data Register */ #define ADC_DR4(port) MMIO32(port + 0x020) #define ADC0_DR4 ADC_DR4(ADC0) #define ADC1_DR4 ADC_DR4(ADC1) /* A/D Channel 5 Data Register */ #define ADC_DR5(port) MMIO32(port + 0x024) #define ADC0_DR5 ADC_DR5(ADC0) #define ADC1_DR5 ADC_DR5(ADC1) /* A/D Channel 6 Data Register */ #define ADC_DR6(port) MMIO32(port + 0x028) #define ADC0_DR6 ADC_DR6(ADC0) #define ADC1_DR6 ADC_DR6(ADC1) /* A/D Channel 7 Data Register */ #define ADC_DR7(port) MMIO32(port + 0x02C) #define ADC0_DR7 ADC_DR7(ADC0) #define ADC1_DR7 ADC_DR7(ADC1) #define ADC_DR_VVREF_SHIFT (6) #define ADC_DR_VVREF (1 << ADC_DR_VVREF_SHIFT) #define ADC_DR_OVERRUN_SHIFT (30) #define ADC_DR_OVERRUN (1 << ADC_DR_OVERRUN_SHIFT) #define ADC_DR_DONE_SHIFT (31) #define ADC_DR_DONE (1 << ADC_DR_DONE_SHIFT) /* A/D Status Register */ #define ADC_STAT(port) MMIO32(port + 0x030) #define ADC0_STAT ADC_STAT(ADC0) #define ADC1_STAT ADC_STAT(ADC1) typedef enum { ADC0_NUM = 0x0, ADC1_NUM = 0x1 } adc_num_t; BEGIN_DECLS void adc_disable(adc_num_t adc_num); void adc_init(adc_num_t adc_num, uint8_t pins, uint8_t clkdiv, uint8_t clks); void adc_start(adc_num_t adc_num); void adc_read_to_buffer(adc_num_t adc_num, uint8_t pin, uint8_t *buf, uint16_t buf_len); END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/atimer.h000066400000000000000000000041571435536612600241150ustar00rootroot00000000000000/** @defgroup atimer_defines Alarm Timer Defines @brief Defined Constants and Types for the LPC43xx Alarm Timer @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_ATIMER_H #define LPC43XX_ATIMER_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Alarm Timer registers ----------------------------------------------- */ /* Downcounter register */ #define ATIMER_DOWNCOUNTER MMIO32(ATIMER_BASE + 0x000) /* Preset value register */ #define ATIMER_PRESET MMIO32(ATIMER_BASE + 0x004) /* Interrupt clear enable register */ #define ATIMER_CLR_EN MMIO32(ATIMER_BASE + 0xFD8) /* Interrupt set enable register */ #define ATIMER_SET_EN MMIO32(ATIMER_BASE + 0xFDC) /* Status register */ #define ATIMER_STATUS MMIO32(ATIMER_BASE + 0xFE0) /* Enable register */ #define ATIMER_ENABLE MMIO32(ATIMER_BASE + 0xFE4) /* Clear register */ #define ATIMER_CLR_STAT MMIO32(ATIMER_BASE + 0xFE8) /* Set register */ #define ATIMER_SET_STAT MMIO32(ATIMER_BASE + 0xFEC) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/ccu.h000066400000000000000000000331751435536612600234100ustar00rootroot00000000000000/** @defgroup ccu_defines Clock Control Unit Defines @brief Defined Constants and Types for the LPC43xx Clock Control Unit @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_CCU_H #define LPC43XX_CCU_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- CCU1 registers ------------------------------------------------------ */ /* CCU1 power mode register */ #define CCU1_PM MMIO32(CCU1_BASE + 0x000) /* CCU1 base clock status register */ #define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004) /* CLK_APB3_BUS clock configuration register */ #define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100) /* CLK_APB3_BUS clock status register */ #define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104) /* CLK_APB3_I2C1 configuration register */ #define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108) /* CLK_APB3_I2C1 status register */ #define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C) /* CLK_APB3_DAC configuration register */ #define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110) /* CLK_APB3_DAC status register */ #define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114) /* CLK_APB3_ADC0 configuration register */ #define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118) /* CLK_APB3_ADC0 status register */ #define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C) /* CLK_APB3_ADC1 configuration register */ #define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120) /* CLK_APB3_ADC1 status register */ #define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124) /* CLK_APB3_CAN0 configuration register */ #define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128) /* CLK_APB3_CAN0 status register */ #define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C) /* CLK_APB1_BUS configuration register */ #define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200) /* CLK_APB1_BUS status register */ #define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204) /* CLK_APB1_MOTOCON configuration register */ #define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208) /* CLK_APB1_MOTOCON status register */ #define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C) /* CLK_APB1_I2C0 configuration register */ #define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210) /* CLK_APB1_I2C0 status register */ #define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214) /* CLK_APB1_I2S configuration register */ #define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218) /* CLK_APB1_I2S status register */ #define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C) /* CLK_APB3_CAN1 configuration register */ #define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220) /* CLK_APB3_CAN1 status register */ #define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224) /* CLK_SPIFI configuration register */ #define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300) /* CLK_SPIFI status register */ #define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304) /* CLK_M4_BUS configuration register */ #define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400) /* CLK_M4_BUS status register */ #define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404) /* CLK_M4_SPIFI configuration register */ #define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408) /* CLK_M4_SPIFI status register */ #define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C) /* CLK_M4_GPIO configuration register */ #define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410) /* CLK_M4_GPIO status register */ #define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414) /* CLK_M4_LCD configuration register */ #define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418) /* CLK_M4_LCD status register */ #define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C) /* CLK_M4_ETHERNET configuration register */ #define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420) /* CLK_M4_ETHERNET status register */ #define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424) /* CLK_M4_USB0 configuration register */ #define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428) /* CLK_M4_USB0 status register */ #define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C) /* CLK_M4_EMC configuration register */ #define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430) /* CLK_M4_EMC status register */ #define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434) /* CLK_M4_SDIO configuration register */ #define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438) /* CLK_M4_SDIO status register */ #define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C) /* CLK_M4_DMA configuration register */ #define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440) /* CLK_M4_DMA status register */ #define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444) /* CLK_M4_M4CORE configuration register */ #define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448) /* CLK_M4_M4CORE status register */ #define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C) /* CLK_M4_SCT configuration register */ #define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468) /* CLK_M4_SCT status register */ #define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C) /* CLK_M4_USB1 configuration register */ #define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470) /* CLK_M4_USB1 status register */ #define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474) /* CLK_M4_EMCDIV configuration register */ #define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478) /* CLK_M4_EMCDIV status register */ #define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C) /* CLK_M4_M0_CFG configuration register */ #define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490) /* CLK_M4_M0_STAT status register */ #define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494) /* CLK_M4_VADC_CFG configuration register */ #define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498) /* CLK_M4_VADC_STAT configuration register */ #define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C) /* CLK_M4_WWDT configuration register */ #define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500) /* CLK_M4_WWDT status register */ #define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504) /* CLK_M4_UART0 configuration register */ #define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508) /* CLK_M4_UART0 status register */ #define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C) /* CLK_M4_UART1 configuration register */ #define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510) /* CLK_M4_UART1 status register */ #define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514) /* CLK_M4_SSP0 configuration register */ #define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518) /* CLK_M4_SSP0 status register */ #define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C) /* CLK_M4_TIMER0 configuration register */ #define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520) /* CLK_M4_TIMER0 status register */ #define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524) /* CLK_M4_TIMER1 configuration register */ #define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528) /* CLK_M4_TIMER1 status register */ #define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C) /* CLK_M4_SCU configuration register */ #define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530) /* CLK_M4_SCU status register */ #define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534) /* CLK_M4_CREG configuration register */ #define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538) /* CLK_M4_CREG status register */ #define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C) /* CLK_M4_RITIMER configuration register */ #define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600) /* CLK_M4_RITIMER status register */ #define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604) /* CLK_M4_UART2 configuration register */ #define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608) /* CLK_M4_UART2 status register */ #define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C) /* CLK_M4_UART3 configuration register */ #define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610) /* CLK_M4_UART3 status register */ #define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614) /* CLK_M4_TIMER2 configuration register */ #define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618) /* CLK_M4_TIMER2 status register */ #define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C) /* CLK_M4_TIMER3 configuration register */ #define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620) /* CLK_M4_TIMER3 status register */ #define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624) /* CLK_M4_SSP1 configuration register */ #define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628) /* CLK_M4_SSP1 status register */ #define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C) /* CLK_M4_QEI configuration register */ #define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630) /* CLK_M4_QEI status register */ #define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634) /* CLK_PERIPH_BUS configuration register */ #define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700) /* CLK_PERIPH_BUS status register */ #define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704) /* CLK_PERIPH_CORE configuration register */ #define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710) /* CLK_PERIPH_CORE status register */ #define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714) /* CLK_PERIPH_SGPIO configuration register */ #define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718) /* CLK_PERIPH_SGPIO status register */ #define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C) /* CLK_USB0 configuration register */ #define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800) /* CLK_USB0 status register */ #define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804) /* CLK_USB1 configuration register */ #define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900) /* CLK_USB1 status register */ #define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904) /* CLK_SPI configuration register */ #define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00) /* CLK_SPI status register */ #define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04) /* CLK_VADC configuration register */ #define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00) /* CLK_VADC status register */ #define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04) /* --- CCU2 registers ------------------------------------------------------ */ /* CCU2 power mode register */ #define CCU2_PM MMIO32(CCU2_BASE + 0x000) /* CCU2 base clocks status register */ #define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004) /* CLK_APLL configuration register */ #define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100) /* CLK_APLL status register */ #define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104) /* CLK_APB2_UART3 configuration register */ #define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200) /* CLK_APB2_UART3 status register */ #define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204) /* CLK_APB2_UART2 configuration register */ #define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300) /* CLK_APB2_UART2 status register */ #define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304) /* CLK_APB0_UART1 configuration register */ #define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400) /* CLK_APB0_UART1 status register */ #define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404) /* CLK_APB0_UART0 configuration register */ #define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500) /* CLK_APB0_UART0 status register */ #define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504) /* CLK_APB2_SSP1 configuration register */ #define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600) /* CLK_APB2_SSP1 status register */ #define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604) /* CLK_APB0_SSP0 configuration register */ #define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700) /* CLK_APB0_SSP0 status register */ #define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704) /* CLK_SDIO configuration register (for SD/MMC) */ #define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800) /* CLK_SDIO status register (for SD/MMC) */ #define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/cgu.h000066400000000000000000001260531435536612600234120ustar00rootroot00000000000000/** @defgroup cgu_defines Clock Generation Unit Defines * * @brief Defined Constants and Types for the LPC43xx Clock Generation * Unit * * @ingroup LPC43xx_defines * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann * * * @date 10 March 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_CGU_H #define CGU_LPC43XX_CGU_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- CGU registers ------------------------------------------------------- */ /* Frequency monitor register */ #define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014) /* Crystal oscillator control register */ #define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018) /* PLL0USB status register */ #define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C) /* PLL0USB control register */ #define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020) /* PLL0USB M-divider register */ #define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024) /* PLL0USB N/P-divider register */ #define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028) /* PLL0AUDIO status register */ #define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C) /* PLL0AUDIO control register */ #define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030) /* PLL0AUDIO M-divider register */ #define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034) /* PLL0AUDIO N/P-divider register */ #define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038) /* PLL0AUDIO fractional divider register */ #define CGU_PLL0AUDIO_FRAC MMIO32(CGU_BASE + 0x03C) /* PLL1 status register */ #define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040) /* PLL1 control register */ #define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044) /* Integer divider A control register */ #define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048) /* Integer divider B control register */ #define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C) /* Integer divider C control register */ #define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050) /* Integer divider D control register */ #define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054) /* Integer divider E control register */ #define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058) /* Output stage 0 control register */ #define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C) /* Output stage 1 control register for base clock */ #define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060) /* Output stage 2 control register for base clock */ #define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064) /* Output stage 3 control register for base clock */ #define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068) /* Output stage 4 control register for base clock */ #define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C) /* Output stage 5 control register for base clock */ #define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070) /* Output stage 6 control register for base clock */ #define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074) /* Output stage 7 control register for base clock */ #define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078) /* Output stage 8 control register for base clock */ #define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C) /* Output stage 9 control register for base clock */ #define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080) /* Output stage 10 control register for base clock */ #define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084) /* Output stage 11 control register for base clock */ #define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088) /* Output stage 12 control register for base clock */ #define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C) /* Output stage 13 control register for base clock */ #define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090) /* Output stage 14 control register for base clock */ #define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094) /* Output stage 15 control register for base clock */ #define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098) /* Output stage 16 control register for base clock */ #define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C) /* Output stage 17 control register for base clock */ #define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0) /* Output stage 18 control register for base clock */ #define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4) /* Output stage 19 control register for base clock */ #define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8) /* Output stage 20 control register for base clock */ #define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC) /* Reserved output stage */ #define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0) /* Reserved output stage */ #define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4) /* Reserved output stage */ #define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8) /* Reserved output stage */ #define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC) /* Output stage 25 control register for base clock */ #define CGU_BASE_AUDIO_CLK MMIO32(CGU_BASE + 0x0C0) /* Output stage 26 control CLK register for base clock */ #define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4) /* Output stage 27 control CLK register for base clock */ #define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) /* --- CGU_FREQ_MON values -------------------------------------- */ /* RCNT: 9-bit reference clock-counter value */ #define CGU_FREQ_MON_RCNT_SHIFT (0) #define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) #define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) /* FCNT: 14-bit selected clock-counter value */ #define CGU_FREQ_MON_FCNT_SHIFT (9) #define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) #define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) /* MEAS: Measure frequency */ #define CGU_FREQ_MON_MEAS_SHIFT (23) #define CGU_FREQ_MON_MEAS_MASK (0x1 << CGU_FREQ_MON_MEAS_SHIFT) #define CGU_FREQ_MON_MEAS(x) ((x) << CGU_FREQ_MON_MEAS_SHIFT) /* CLK_SEL: Clock-source selection for the clock to be measured */ #define CGU_FREQ_MON_CLK_SEL_SHIFT (24) #define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) #define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) /* --- CGU_XTAL_OSC_CTRL values --------------------------------- */ /* ENABLE: Oscillator-pad enable */ #define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) #define CGU_XTAL_OSC_CTRL_ENABLE_MASK (0x1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) #define CGU_XTAL_OSC_CTRL_ENABLE(x) ((x) << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) /* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */ #define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) #define CGU_XTAL_OSC_CTRL_BYPASS_MASK (0x1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) #define CGU_XTAL_OSC_CTRL_BYPASS(x) ((x) << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) /* HF: Select frequency range */ #define CGU_XTAL_OSC_CTRL_HF_SHIFT (2) #define CGU_XTAL_OSC_CTRL_HF_MASK (0x1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) #define CGU_XTAL_OSC_CTRL_HF(x) ((x) << CGU_XTAL_OSC_CTRL_HF_SHIFT) /* --- CGU_PLL0USB_STAT values ---------------------------------- */ /* LOCK: PLL0 lock indicator */ #define CGU_PLL0USB_STAT_LOCK_SHIFT (0) #define CGU_PLL0USB_STAT_LOCK_MASK (0x1 << CGU_PLL0USB_STAT_LOCK_SHIFT) #define CGU_PLL0USB_STAT_LOCK(x) ((x) << CGU_PLL0USB_STAT_LOCK_SHIFT) /* FR: PLL0 free running indicator */ #define CGU_PLL0USB_STAT_FR_SHIFT (1) #define CGU_PLL0USB_STAT_FR_MASK (0x1 << CGU_PLL0USB_STAT_FR_SHIFT) #define CGU_PLL0USB_STAT_FR(x) ((x) << CGU_PLL0USB_STAT_FR_SHIFT) /* --- CGU_PLL0USB_CTRL values ---------------------------------- */ /* PD: PLL0 power down */ #define CGU_PLL0USB_CTRL_PD_SHIFT (0) #define CGU_PLL0USB_CTRL_PD_MASK (0x1 << CGU_PLL0USB_CTRL_PD_SHIFT) #define CGU_PLL0USB_CTRL_PD(x) ((x) << CGU_PLL0USB_CTRL_PD_SHIFT) /* BYPASS: Input clock bypass control */ #define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) #define CGU_PLL0USB_CTRL_BYPASS_MASK (0x1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) #define CGU_PLL0USB_CTRL_BYPASS(x) ((x) << CGU_PLL0USB_CTRL_BYPASS_SHIFT) /* DIRECTI: PLL0 direct input */ #define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) #define CGU_PLL0USB_CTRL_DIRECTI_MASK (0x1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) #define CGU_PLL0USB_CTRL_DIRECTI(x) ((x) << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) /* DIRECTO: PLL0 direct output */ #define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) #define CGU_PLL0USB_CTRL_DIRECTO_MASK (0x1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) #define CGU_PLL0USB_CTRL_DIRECTO(x) ((x) << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) /* CLKEN: PLL0 clock enable */ #define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) #define CGU_PLL0USB_CTRL_CLKEN_MASK (0x1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) #define CGU_PLL0USB_CTRL_CLKEN(x) ((x) << CGU_PLL0USB_CTRL_CLKEN_SHIFT) /* FRM: Free running mode */ #define CGU_PLL0USB_CTRL_FRM_SHIFT (6) #define CGU_PLL0USB_CTRL_FRM_MASK (0x1 << CGU_PLL0USB_CTRL_FRM_SHIFT) #define CGU_PLL0USB_CTRL_FRM(x) ((x) << CGU_PLL0USB_CTRL_FRM_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_PLL0USB_CTRL_AUTOBLOCK_MASK (0x1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) #define CGU_PLL0USB_CTRL_AUTOBLOCK(x) ((x) << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) #define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) #define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) /* --- CGU_PLL0USB_MDIV values ---------------------------------- */ /* MDEC: Decoded M-divider coefficient value */ #define CGU_PLL0USB_MDIV_MDEC_SHIFT (0) #define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) #define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) /* SELP: Bandwidth select P value */ #define CGU_PLL0USB_MDIV_SELP_SHIFT (17) #define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) #define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) /* SELI: Bandwidth select I value */ #define CGU_PLL0USB_MDIV_SELI_SHIFT (22) #define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) #define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) /* SELR: Bandwidth select R value */ #define CGU_PLL0USB_MDIV_SELR_SHIFT (28) #define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) #define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) /* --- CGU_PLL0USB_NP_DIV values -------------------------------- */ /* PDEC: Decoded P-divider coefficient value */ #define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) #define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) #define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) /* NDEC: Decoded N-divider coefficient value */ #define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) #define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) #define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) /* --- CGU_PLL0AUDIO_STAT values -------------------------------- */ /* LOCK: PLL0 lock indicator */ #define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) #define CGU_PLL0AUDIO_STAT_LOCK_MASK (0x1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) #define CGU_PLL0AUDIO_STAT_LOCK(x) ((x) << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) /* FR: PLL0 free running indicator */ #define CGU_PLL0AUDIO_STAT_FR_SHIFT (1) #define CGU_PLL0AUDIO_STAT_FR_MASK (0x1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) #define CGU_PLL0AUDIO_STAT_FR(x) ((x) << CGU_PLL0AUDIO_STAT_FR_SHIFT) /* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */ /* PD: PLL0 power down */ #define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) #define CGU_PLL0AUDIO_CTRL_PD_MASK (0x1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) #define CGU_PLL0AUDIO_CTRL_PD(x) ((x) << CGU_PLL0AUDIO_CTRL_PD_SHIFT) /* BYPASS: Input clock bypass control */ #define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) #define CGU_PLL0AUDIO_CTRL_BYPASS_MASK (0x1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) #define CGU_PLL0AUDIO_CTRL_BYPASS(x) ((x) << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) /* DIRECTI: PLL0 direct input */ #define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2) #define CGU_PLL0AUDIO_CTRL_DIRECTI_MASK (0x1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) #define CGU_PLL0AUDIO_CTRL_DIRECTI(x) ((x) << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) /* DIRECTO: PLL0 direct output */ #define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3) #define CGU_PLL0AUDIO_CTRL_DIRECTO_MASK (0x1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) #define CGU_PLL0AUDIO_CTRL_DIRECTO(x) ((x) << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) /* CLKEN: PLL0 clock enable */ #define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) #define CGU_PLL0AUDIO_CTRL_CLKEN_MASK (0x1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) #define CGU_PLL0AUDIO_CTRL_CLKEN(x) ((x) << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) /* FRM: Free running mode */ #define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) #define CGU_PLL0AUDIO_CTRL_FRM_MASK (0x1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) #define CGU_PLL0AUDIO_CTRL_FRM(x) ((x) << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_MASK (0x1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) #define CGU_PLL0AUDIO_CTRL_AUTOBLOCK(x) ((x) << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) /* PLLFRACT_REQ: Fractional PLL word write request */ #define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12) #define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_MASK (0x1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) #define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ(x) ((x) << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) /* SEL_EXT: Select fractional divider */ #define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13) #define CGU_PLL0AUDIO_CTRL_SEL_EXT_MASK (0x1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) #define CGU_PLL0AUDIO_CTRL_SEL_EXT(x) ((x) << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) /* MOD_PD: Sigma-Delta modulator power-down */ #define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14) #define CGU_PLL0AUDIO_CTRL_MOD_PD_MASK (0x1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) #define CGU_PLL0AUDIO_CTRL_MOD_PD(x) ((x) << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24) #define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) #define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) /* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */ /* MDEC: Decoded M-divider coefficient value */ #define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) #define CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) #define CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) /* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */ /* PDEC: Decoded P-divider coefficient value */ #define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) #define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) #define CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) /* NDEC: Decoded N-divider coefficient value */ #define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) #define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) #define CGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) /* --- CGU_PLL0AUDIO_FRAC values -------------------------------- */ /* PLLFRACT_CTRL: PLL fractional divider control word */ #define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) #define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_SHIFT) #define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_SHIFT) /* --- CGU_PLL1_STAT values ------------------------------------- */ /* LOCK: PLL1 lock indicator */ #define CGU_PLL1_STAT_LOCK_SHIFT (0) #define CGU_PLL1_STAT_LOCK_MASK (0x1 << CGU_PLL1_STAT_LOCK_SHIFT) #define CGU_PLL1_STAT_LOCK(x) ((x) << CGU_PLL1_STAT_LOCK_SHIFT) /* --- CGU_PLL1_CTRL values ------------------------------------- */ /* PD: PLL1 power down */ #define CGU_PLL1_CTRL_PD_SHIFT (0) #define CGU_PLL1_CTRL_PD_MASK (0x1 << CGU_PLL1_CTRL_PD_SHIFT) #define CGU_PLL1_CTRL_PD(x) ((x) << CGU_PLL1_CTRL_PD_SHIFT) /* BYPASS: Input clock bypass control */ #define CGU_PLL1_CTRL_BYPASS_SHIFT (1) #define CGU_PLL1_CTRL_BYPASS_MASK (0x1 << CGU_PLL1_CTRL_BYPASS_SHIFT) #define CGU_PLL1_CTRL_BYPASS(x) ((x) << CGU_PLL1_CTRL_BYPASS_SHIFT) /* FBSEL: PLL feedback select */ #define CGU_PLL1_CTRL_FBSEL_SHIFT (6) #define CGU_PLL1_CTRL_FBSEL_MASK (0x1 << CGU_PLL1_CTRL_FBSEL_SHIFT) #define CGU_PLL1_CTRL_FBSEL(x) ((x) << CGU_PLL1_CTRL_FBSEL_SHIFT) /* DIRECT: PLL direct CCO output */ #define CGU_PLL1_CTRL_DIRECT_SHIFT (7) #define CGU_PLL1_CTRL_DIRECT_MASK (0x1 << CGU_PLL1_CTRL_DIRECT_SHIFT) #define CGU_PLL1_CTRL_DIRECT(x) ((x) << CGU_PLL1_CTRL_DIRECT_SHIFT) /* PSEL: Post-divider division ratio P */ #define CGU_PLL1_CTRL_PSEL_SHIFT (8) #define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) #define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_PLL1_CTRL_AUTOBLOCK_MASK (0x1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) #define CGU_PLL1_CTRL_AUTOBLOCK(x) ((x) << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) /* NSEL: Pre-divider division ratio N */ #define CGU_PLL1_CTRL_NSEL_SHIFT (12) #define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) #define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) /* MSEL: Feedback-divider division ratio (M) */ #define CGU_PLL1_CTRL_MSEL_SHIFT (16) #define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) #define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) /* CLK_SEL: Clock-source selection */ #define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) #define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) #define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVA_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ #define CGU_IDIVA_CTRL_PD_SHIFT (0) #define CGU_IDIVA_CTRL_PD_MASK (0x1 << CGU_IDIVA_CTRL_PD_SHIFT) #define CGU_IDIVA_CTRL_PD(x) ((x) << CGU_IDIVA_CTRL_PD_SHIFT) /* IDIV: Integer divider A divider value (1/(IDIV + 1)) */ #define CGU_IDIVA_CTRL_IDIV_SHIFT (2) #define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) #define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_IDIVA_CTRL_AUTOBLOCK_MASK (0x1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) #define CGU_IDIVA_CTRL_AUTOBLOCK(x) ((x) << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) #define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) #define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVB_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ #define CGU_IDIVB_CTRL_PD_SHIFT (0) #define CGU_IDIVB_CTRL_PD_MASK (0x1 << CGU_IDIVB_CTRL_PD_SHIFT) #define CGU_IDIVB_CTRL_PD(x) ((x) << CGU_IDIVB_CTRL_PD_SHIFT) /* IDIV: Integer divider B divider value (1/(IDIV + 1)) */ #define CGU_IDIVB_CTRL_IDIV_SHIFT (2) #define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) #define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_IDIVB_CTRL_AUTOBLOCK_MASK (0x1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) #define CGU_IDIVB_CTRL_AUTOBLOCK(x) ((x) << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) #define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) #define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVC_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ #define CGU_IDIVC_CTRL_PD_SHIFT (0) #define CGU_IDIVC_CTRL_PD_MASK (0x1 << CGU_IDIVC_CTRL_PD_SHIFT) #define CGU_IDIVC_CTRL_PD(x) ((x) << CGU_IDIVC_CTRL_PD_SHIFT) /* IDIV: Integer divider C divider value (1/(IDIV + 1)) */ #define CGU_IDIVC_CTRL_IDIV_SHIFT (2) #define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) #define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_IDIVC_CTRL_AUTOBLOCK_MASK (0x1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) #define CGU_IDIVC_CTRL_AUTOBLOCK(x) ((x) << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) #define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) #define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVD_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ #define CGU_IDIVD_CTRL_PD_SHIFT (0) #define CGU_IDIVD_CTRL_PD_MASK (0x1 << CGU_IDIVD_CTRL_PD_SHIFT) #define CGU_IDIVD_CTRL_PD(x) ((x) << CGU_IDIVD_CTRL_PD_SHIFT) /* IDIV: Integer divider D divider value (1/(IDIV + 1)) */ #define CGU_IDIVD_CTRL_IDIV_SHIFT (2) #define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) #define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_IDIVD_CTRL_AUTOBLOCK_MASK (0x1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) #define CGU_IDIVD_CTRL_AUTOBLOCK(x) ((x) << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) #define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) #define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVE_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ #define CGU_IDIVE_CTRL_PD_SHIFT (0) #define CGU_IDIVE_CTRL_PD_MASK (0x1 << CGU_IDIVE_CTRL_PD_SHIFT) #define CGU_IDIVE_CTRL_PD(x) ((x) << CGU_IDIVE_CTRL_PD_SHIFT) /* IDIV: Integer divider E divider value (1/(IDIV + 1)) */ #define CGU_IDIVE_CTRL_IDIV_SHIFT (2) #define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) #define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) #define CGU_IDIVE_CTRL_AUTOBLOCK_MASK (0x1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) #define CGU_IDIVE_CTRL_AUTOBLOCK(x) ((x) << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) #define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) #define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) /* --- CGU_BASE_SAFE_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_SAFE_CLK_PD_SHIFT (0) #define CGU_BASE_SAFE_CLK_PD_MASK (0x1 << CGU_BASE_SAFE_CLK_PD_SHIFT) #define CGU_BASE_SAFE_CLK_PD(x) ((x) << CGU_BASE_SAFE_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_SAFE_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_SAFE_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) #define CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_USB0_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_USB0_CLK_PD_SHIFT (0) #define CGU_BASE_USB0_CLK_PD_MASK (0x1 << CGU_BASE_USB0_CLK_PD_SHIFT) #define CGU_BASE_USB0_CLK_PD(x) ((x) << CGU_BASE_USB0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_USB0_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_USB0_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) #define CGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_PERIPH_CLK values ------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_PERIPH_CLK_PD_SHIFT (0) #define CGU_BASE_PERIPH_CLK_PD_MASK (0x1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) #define CGU_BASE_PERIPH_CLK_PD(x) ((x) << CGU_BASE_PERIPH_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_PERIPH_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_PERIPH_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) #define CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_USB1_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_USB1_CLK_PD_SHIFT (0) #define CGU_BASE_USB1_CLK_PD_MASK (0x1 << CGU_BASE_USB1_CLK_PD_SHIFT) #define CGU_BASE_USB1_CLK_PD(x) ((x) << CGU_BASE_USB1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_USB1_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_USB1_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) #define CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_M4_CLK values ----------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_M4_CLK_PD_SHIFT (0) #define CGU_BASE_M4_CLK_PD_MASK (0x1 << CGU_BASE_M4_CLK_PD_SHIFT) #define CGU_BASE_M4_CLK_PD(x) ((x) << CGU_BASE_M4_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_M4_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_M4_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) #define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SPIFI_CLK values -------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_SPIFI_CLK_PD_SHIFT (0) #define CGU_BASE_SPIFI_CLK_PD_MASK (0x1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) #define CGU_BASE_SPIFI_CLK_PD(x) ((x) << CGU_BASE_SPIFI_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_SPIFI_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_SPIFI_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) #define CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SPI_CLK values ---------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_SPI_CLK_PD_SHIFT (0) #define CGU_BASE_SPI_CLK_PD_MASK (0x1 << CGU_BASE_SPI_CLK_PD_SHIFT) #define CGU_BASE_SPI_CLK_PD(x) ((x) << CGU_BASE_SPI_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_SPI_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_SPI_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) #define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) #define CGU_BASE_PHY_RX_CLK_PD_MASK (0x1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) #define CGU_BASE_PHY_RX_CLK_PD(x) ((x) << CGU_BASE_PHY_RX_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_PHY_RX_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) #define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) #define CGU_BASE_PHY_TX_CLK_PD_MASK (0x1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) #define CGU_BASE_PHY_TX_CLK_PD(x) ((x) << CGU_BASE_PHY_TX_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_PHY_TX_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) #define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_APB1_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_APB1_CLK_PD_SHIFT (0) #define CGU_BASE_APB1_CLK_PD_MASK (0x1 << CGU_BASE_APB1_CLK_PD_SHIFT) #define CGU_BASE_APB1_CLK_PD(x) ((x) << CGU_BASE_APB1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_APB1_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_APB1_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) #define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_APB3_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_APB3_CLK_PD_SHIFT (0) #define CGU_BASE_APB3_CLK_PD_MASK (0x1 << CGU_BASE_APB3_CLK_PD_SHIFT) #define CGU_BASE_APB3_CLK_PD(x) ((x) << CGU_BASE_APB3_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_APB3_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_APB3_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) #define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_LCD_CLK values ---------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_LCD_CLK_PD_SHIFT (0) #define CGU_BASE_LCD_CLK_PD_MASK (0x1 << CGU_BASE_LCD_CLK_PD_SHIFT) #define CGU_BASE_LCD_CLK_PD(x) ((x) << CGU_BASE_LCD_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_LCD_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_LCD_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) #define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_VADC_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_VADC_CLK_PD_SHIFT (0) #define CGU_BASE_VADC_CLK_PD_MASK (0x1 << CGU_BASE_VADC_CLK_PD_SHIFT) #define CGU_BASE_VADC_CLK_PD(x) ((x) << CGU_BASE_VADC_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_VADC_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_VADC_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) #define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SDIO_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_SDIO_CLK_PD_SHIFT (0) #define CGU_BASE_SDIO_CLK_PD_MASK (0x1 << CGU_BASE_SDIO_CLK_PD_SHIFT) #define CGU_BASE_SDIO_CLK_PD(x) ((x) << CGU_BASE_SDIO_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_SDIO_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_SDIO_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) #define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SSP0_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_SSP0_CLK_PD_SHIFT (0) #define CGU_BASE_SSP0_CLK_PD_MASK (0x1 << CGU_BASE_SSP0_CLK_PD_SHIFT) #define CGU_BASE_SSP0_CLK_PD(x) ((x) << CGU_BASE_SSP0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_SSP0_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_SSP0_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) #define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SSP1_CLK values --------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_SSP1_CLK_PD_SHIFT (0) #define CGU_BASE_SSP1_CLK_PD_MASK (0x1 << CGU_BASE_SSP1_CLK_PD_SHIFT) #define CGU_BASE_SSP1_CLK_PD(x) ((x) << CGU_BASE_SSP1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_SSP1_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_SSP1_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) #define CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART0_CLK values -------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_UART0_CLK_PD_SHIFT (0) #define CGU_BASE_UART0_CLK_PD_MASK (0x1 << CGU_BASE_UART0_CLK_PD_SHIFT) #define CGU_BASE_UART0_CLK_PD(x) ((x) << CGU_BASE_UART0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_UART0_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_UART0_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) #define CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART1_CLK values -------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_UART1_CLK_PD_SHIFT (0) #define CGU_BASE_UART1_CLK_PD_MASK (0x1 << CGU_BASE_UART1_CLK_PD_SHIFT) #define CGU_BASE_UART1_CLK_PD(x) ((x) << CGU_BASE_UART1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_UART1_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_UART1_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) #define CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART2_CLK values -------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_UART2_CLK_PD_SHIFT (0) #define CGU_BASE_UART2_CLK_PD_MASK (0x1 << CGU_BASE_UART2_CLK_PD_SHIFT) #define CGU_BASE_UART2_CLK_PD(x) ((x) << CGU_BASE_UART2_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_UART2_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_UART2_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) #define CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART3_CLK values -------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_UART3_CLK_PD_SHIFT (0) #define CGU_BASE_UART3_CLK_PD_MASK (0x1 << CGU_BASE_UART3_CLK_PD_SHIFT) #define CGU_BASE_UART3_CLK_PD(x) ((x) << CGU_BASE_UART3_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_UART3_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_UART3_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) #define CGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_OUT_CLK values ---------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_OUT_CLK_PD_SHIFT (0) #define CGU_BASE_OUT_CLK_PD_MASK (0x1 << CGU_BASE_OUT_CLK_PD_SHIFT) #define CGU_BASE_OUT_CLK_PD(x) ((x) << CGU_BASE_OUT_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_OUT_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_OUT_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) #define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_AUDIO_CLK values -------------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_AUDIO_CLK_PD_SHIFT (0) #define CGU_BASE_AUDIO_CLK_PD_MASK (0x1 << CGU_BASE_AUDIO_CLK_PD_SHIFT) #define CGU_BASE_AUDIO_CLK_PD(x) ((x) << CGU_BASE_AUDIO_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_AUDIO_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_AUDIO_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_AUDIO_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_AUDIO_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_AUDIO_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_AUDIO_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_AUDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_AUDIO_CLK_CLK_SEL_SHIFT) #define CGU_BASE_AUDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_AUDIO_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) #define CGU_BASE_CGU_OUT0_CLK_PD_MASK (0x1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) #define CGU_BASE_CGU_OUT0_CLK_PD(x) ((x) << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) #define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */ /* PD: Output stage power down */ #define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) #define CGU_BASE_CGU_OUT1_CLK_PD_MASK (0x1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) #define CGU_BASE_CGU_OUT1_CLK_PD(x) ((x) << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11) #define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_MASK (0x1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) #define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK(x) ((x) << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24) #define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) #define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ #define CGU_SRC_32K 0x00 #define CGU_SRC_IRC 0x01 #define CGU_SRC_ENET_RX 0x02 #define CGU_SRC_ENET_TX 0x03 #define CGU_SRC_GP_CLKIN 0x04 #define CGU_SRC_XTAL 0x06 #define CGU_SRC_PLL0USB 0x07 #define CGU_SRC_PLL0AUDIO 0x08 #define CGU_SRC_PLL1 0x09 #define CGU_SRC_IDIVA 0x0C #define CGU_SRC_IDIVB 0x0D #define CGU_SRC_IDIVC 0x0E #define CGU_SRC_IDIVD 0x0F #define CGU_SRC_IDIVE 0x10 /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/creg.h000066400000000000000000000344341435536612600235550ustar00rootroot00000000000000/** @defgroup creg_defines Configuration Registers Defines @brief Defined Constants and Types for the LPC43xx Configuration Registers @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_CREG_H #define LPC43XX_CREG_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- CREG registers ----------------------------------------------------- */ /* * Chip configuration register 32 kHz oscillator output and BOD control * register */ #define CREG_CREG0 MMIO32(CREG_BASE + 0x004) /* ARM Cortex-M4 memory mapping */ #define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100) /* Chip configuration register 1 */ #define CREG_CREG1 MMIO32(CREG_BASE + 0x108) /* Chip configuration register 2 */ #define CREG_CREG2 MMIO32(CREG_BASE + 0x10C) /* Chip configuration register 3 */ #define CREG_CREG3 MMIO32(CREG_BASE + 0x110) /* Chip configuration register 4 */ #define CREG_CREG4 MMIO32(CREG_BASE + 0x114) /* Chip configuration register 5 */ #define CREG_CREG5 MMIO32(CREG_BASE + 0x118) /* DMA muxing control */ #define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C) /* Flash accelerator configuration register for flash bank A */ #define CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120) /* Flash accelerator configuration register for flash bank B */ #define CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124) /* ETB RAM configuration */ #define CREG_ETBCFG MMIO32(CREG_BASE + 0x128) /* * Chip configuration register 6. Controls multiple functions: Ethernet * interface, SCT output, I2S0/1 inputs, EMC clock. */ #define CREG_CREG6 MMIO32(CREG_BASE + 0x12C) /* Cortex-M4 TXEV event clear */ #define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130) /* Part ID (Boundary scan ID code, read-only) */ #define CREG_CHIPID MMIO32(CREG_BASE + 0x200) /* Cortex-M0 TXEV event clear */ #define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400) /* ARM Cortex-M0 memory mapping */ #define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404) /* USB0 frame length adjust register */ #define CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500) /* USB1 frame length adjust register */ #define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600) /* --- CREG_CREG0 values ---------------------------------------- */ /* EN1KHZ: Enable 1 kHz output */ #define CREG_CREG0_EN1KHZ_SHIFT (0) #define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT) /* EN32KHZ: Enable 32 kHz output */ #define CREG_CREG0_EN32KHZ_SHIFT (1) #define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT) /* RESET32KHZ: 32 kHz oscillator reset */ #define CREG_CREG0_RESET32KHZ_SHIFT (2) #define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT) /* PD32KHZ: 32 kHz power control */ #define CREG_CREG0_PD32KHZ_SHIFT (3) #define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT) /* USB0PHY: USB0 PHY power control */ #define CREG_CREG0_USB0PHY_SHIFT (5) #define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT) /* ALARMCTRL: RTC_ALARM pin output control */ #define CREG_CREG0_ALARMCTRL_SHIFT (6) #define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT) #define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT) /* BODLVL1: BOD trip level to generate an interrupt */ #define CREG_CREG0_BODLVL1_SHIFT (8) #define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT) #define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT) /* BODLVL2: BOD trip level to generate a reset */ #define CREG_CREG0_BODLVL2_SHIFT (10) #define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT) #define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT) /* SAMPLECTRL: SAMPLE pin input/output control */ #define CREG_CREG0_SAMPLECTRL_SHIFT (12) #define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT) #define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT) /* WAKEUP0CTRL: WAKEUP0 pin input/output control */ #define CREG_CREG0_WAKEUP0CTRL_SHIFT (14) #define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT) #define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT) /* WAKEUP1CTRL: WAKEUP1 pin input/output control */ #define CREG_CREG0_WAKEUP1CTRL_SHIFT (16) #define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT) #define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT) /* --- CREG_M4MEMMAP values ------------------------------------- */ /* M4MAP: Shadow address when accessing memory at address 0x00000000 */ #define CREG_M4MEMMAP_M4MAP_SHIFT (12) #define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT) #define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT) /* --- CREG_CREG5 values ---------------------------------------- */ /* M4TAPSEL: JTAG debug select for M4 core */ #define CREG_CREG5_M4TAPSEL_SHIFT (6) #define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT) /* M0APPTAPSEL: JTAG debug select for M0 co-processor */ #define CREG_CREG5_M0APPTAPSEL_SHIFT (9) #define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT) /* --- CREG_DMAMUX values --------------------------------------- */ /* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */ #define CREG_DMAMUX_DMAMUXPER0_SHIFT (0) #define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT) #define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT) /* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */ #define CREG_DMAMUX_DMAMUXPER1_SHIFT (2) #define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT) #define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT) /* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */ #define CREG_DMAMUX_DMAMUXPER2_SHIFT (4) #define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT) #define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT) /* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */ #define CREG_DMAMUX_DMAMUXPER3_SHIFT (6) #define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT) #define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT) /* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */ #define CREG_DMAMUX_DMAMUXPER4_SHIFT (8) #define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT) #define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT) /* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */ #define CREG_DMAMUX_DMAMUXPER5_SHIFT (10) #define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT) #define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT) /* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */ #define CREG_DMAMUX_DMAMUXPER6_SHIFT (12) #define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT) #define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT) /* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */ #define CREG_DMAMUX_DMAMUXPER7_SHIFT (14) #define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT) #define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT) /* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */ #define CREG_DMAMUX_DMAMUXPER8_SHIFT (16) #define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT) #define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT) /* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */ #define CREG_DMAMUX_DMAMUXPER9_SHIFT (18) #define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT) #define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT) /* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */ #define CREG_DMAMUX_DMAMUXPER10_SHIFT (20) #define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT) #define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT) /* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */ #define CREG_DMAMUX_DMAMUXPER11_SHIFT (22) #define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT) #define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT) /* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */ #define CREG_DMAMUX_DMAMUXPER12_SHIFT (24) #define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT) #define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT) /* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */ #define CREG_DMAMUX_DMAMUXPER13_SHIFT (26) #define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT) #define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT) /* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */ #define CREG_DMAMUX_DMAMUXPER14_SHIFT (28) #define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT) #define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT) /* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */ #define CREG_DMAMUX_DMAMUXPER15_SHIFT (30) #define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT) #define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT) /* --- CREG_FLASHCFGA values ------------------------------------ */ /* FLASHTIM: Flash access time. The value of this field plus 1 gives the number * of BASE_M4_CLK clocks used for a flash access */ #define CREG_FLASHCFGA_FLASHTIM_SHIFT (12) #define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT) #define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT) /* POW: Flash bank A power control */ #define CREG_FLASHCFGA_POW_SHIFT (31) #define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT) /* --- CREG_FLASHCFGB values ------------------------------------ */ /* FLASHTIM: Flash access time. The value of this field plus 1 gives the number * of BASE_M4_CLK clocks used for a flash access */ #define CREG_FLASHCFGB_FLASHTIM_SHIFT (12) #define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT) #define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT) /* POW: Flash bank B power control */ #define CREG_FLASHCFGB_POW_SHIFT (31) #define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT) /* --- CREG_ETBCFG values --------------------------------------- */ /* ETB: Select SRAM interface */ #define CREG_ETBCFG_ETB_SHIFT (0) #define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT) /* --- CREG_CREG6 values ---------------------------------------- */ /* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the * PHY interface */ #define CREG_CREG6_ETHMODE_SHIFT (0) #define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT) #define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT) /* CTOUTCTRL: Selects the functionality of the SCT outputs */ #define CREG_CREG6_CTOUTCTRL_SHIFT (4) #define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT) /* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */ #define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12) #define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT) /* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */ #define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13) #define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT) /* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */ #define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14) #define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT) /* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */ #define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15) #define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT) /* EMC_CLK_SEL: EMC_CLK divided clock select */ #define CREG_CREG6_EMC_CLK_SEL_SHIFT (16) #define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT) /* --- CREG_M4TXEVENT values ------------------------------------ */ /* TXEVCLR: Cortex-M4 TXEV event */ #define CREG_M4TXEVENT_TXEVCLR_SHIFT (0) #define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT) /* --- CREG_M0TXEVENT values ------------------------------------ */ /* TXEVCLR: Cortex-M0 TXEV event */ #define CREG_M0TXEVENT_TXEVCLR_SHIFT (0) #define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT) /* --- CREG_M0APPMEMMAP values ---------------------------------- */ /* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */ #define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12) #define CREG_M0APPMEMMAP_M0APPMAP_MASK \ (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) #define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) /* --- CREG_USB0FLADJ values ------------------------------------ */ /* FLTV: Frame length timing value */ #define CREG_USB0FLADJ_FLTV_SHIFT (0) #define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT) #define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT) /* --- CREG_USB1FLADJ values ------------------------------------ */ /* FLTV: Frame length timing value */ #define CREG_USB1FLADJ_FLTV_SHIFT (0) #define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT) #define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/doc-lpc43xx.h000066400000000000000000000010261435536612600246740ustar00rootroot00000000000000/** @mainpage libopencm3 LPC43xx @version 1.0.0 @date 14 September 2012 API documentation for NXP Semiconductors LPC43xx Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup LPC43xx LPC43xx Libraries for NXP Semiconductors LPC43xx series. @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup LPC43xx_defines LPC43xx Defines @brief Defined Constants and Types for the LPC43xx series @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/eventrouter.h000066400000000000000000000043131435536612600252100ustar00rootroot00000000000000/** @defgroup eventrouter_defines Event Router Defines @brief Defined Constants and Types for the LPC43xx Event Router @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_EVENTROUTER_H #define LPC43XX_EVENTROUTER_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Event Router registers ---------------------------------------------- */ /* Level configuration register */ #define EVENTROUTER_HILO MMIO32(EVENTROUTER_BASE + 0x000) /* Edge configuration */ #define EVENTROUTER_EDGE MMIO32(EVENTROUTER_BASE + 0x004) /* Clear event enable register */ #define EVENTROUTER_CLR_EN MMIO32(EVENTROUTER_BASE + 0xFD8) /* Set event enable register */ #define EVENTROUTER_SET_EN MMIO32(EVENTROUTER_BASE + 0xFDC) /* Event Status register */ #define EVENTROUTER_STATUS MMIO32(EVENTROUTER_BASE + 0xFE0) /* Event Enable register */ #define EVENTROUTER_ENABLE MMIO32(EVENTROUTER_BASE + 0xFE4) /* Clear event status register */ #define EVENTROUTER_CLR_STAT MMIO32(EVENTROUTER_BASE + 0xFE8) /* Set event status register */ #define EVENTROUTER_SET_STAT MMIO32(EVENTROUTER_BASE + 0xFEC) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/gima.h000066400000000000000000000122121435536612600235400ustar00rootroot00000000000000/** @defgroup gima_defines Global Input Multiplexer Array Defines @brief Defined Constants and Types for the LPC43xx Global Input Multiplexer Array @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_GIMA_H #define LPC43XX_GIMA_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- GIMA registers ----------------------------------------------------- */ /* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ #define GIMA_CAP0_0_IN MMIO32(GIMA_BASE + 0x000) /* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ #define GIMA_CAP0_1_IN MMIO32(GIMA_BASE + 0x004) /* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ #define GIMA_CAP0_2_IN MMIO32(GIMA_BASE + 0x008) /* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */ #define GIMA_CAP0_3_IN MMIO32(GIMA_BASE + 0x00C) /* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */ #define GIMA_CAP1_0_IN MMIO32(GIMA_BASE + 0x010) /* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */ #define GIMA_CAP1_1_IN MMIO32(GIMA_BASE + 0x014) /* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */ #define GIMA_CAP1_2_IN MMIO32(GIMA_BASE + 0x018) /* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */ #define GIMA_CAP1_3_IN MMIO32(GIMA_BASE + 0x01C) /* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */ #define GIMA_CAP2_0_IN MMIO32(GIMA_BASE + 0x020) /* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */ #define GIMA_CAP2_1_IN MMIO32(GIMA_BASE + 0x024) /* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */ #define GIMA_CAP2_2_IN MMIO32(GIMA_BASE + 0x028) /* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */ #define GIMA_CAP2_3_IN MMIO32(GIMA_BASE + 0x02C) /* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */ #define GIMA_CAP3_0_IN MMIO32(GIMA_BASE + 0x030) /* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */ #define GIMA_CAP3_1_IN MMIO32(GIMA_BASE + 0x034) /* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ #define GIMA_CAP3_2_IN MMIO32(GIMA_BASE + 0x038) /* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ #define GIMA_CAP3_3_IN MMIO32(GIMA_BASE + 0x03C) /* SCT CTIN_0 capture input multiplexer (GIMA output 16) */ #define GIMA_CTIN_0_IN MMIO32(GIMA_BASE + 0x040) /* SCT CTIN_1 capture input multiplexer (GIMA output 17) */ #define GIMA_CTIN_1_IN MMIO32(GIMA_BASE + 0x044) /* SCT CTIN_2 capture input multiplexer (GIMA output 18) */ #define GIMA_CTIN_2_IN MMIO32(GIMA_BASE + 0x048) /* SCT CTIN_3 capture input multiplexer (GIMA output 19) */ #define GIMA_CTIN_3_IN MMIO32(GIMA_BASE + 0x04C) /* SCT CTIN_4 capture input multiplexer (GIMA output 20) */ #define GIMA_CTIN_4_IN MMIO32(GIMA_BASE + 0x050) /* SCT CTIN_5 capture input multiplexer (GIMA output 21) */ #define GIMA_CTIN_5_IN MMIO32(GIMA_BASE + 0x054) /* SCT CTIN_6 capture input multiplexer (GIMA output 22) */ #define GIMA_CTIN_6_IN MMIO32(GIMA_BASE + 0x058) /* SCT CTIN_7 capture input multiplexer (GIMA output 23) */ #define GIMA_CTIN_7_IN MMIO32(GIMA_BASE + 0x05C) /* VADC trigger input multiplexer (GIMA output 24) */ #define GIMA_VADC_TRIGGER_IN MMIO32(GIMA_BASE + 0x060) /* Event router input 13 multiplexer (GIMA output 25) */ #define GIMA_EVENTROUTER_13_IN MMIO32(GIMA_BASE + 0x064) /* Event router input 14 multiplexer (GIMA output 26) */ #define GIMA_EVENTROUTER_14_IN MMIO32(GIMA_BASE + 0x068) /* Event router input 16 multiplexer (GIMA output 27) */ #define GIMA_EVENTROUTER_16_IN MMIO32(GIMA_BASE + 0x06C) /* ADC start0 input multiplexer (GIMA output 28) */ #define GIMA_ADCSTART0_IN MMIO32(GIMA_BASE + 0x070) /* ADC start1 input multiplexer (GIMA output 29) */ #define GIMA_ADCSTART1_IN MMIO32(GIMA_BASE + 0x074) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/gpdma.h000066400000000000000000000542041435536612600237220ustar00rootroot00000000000000/** @defgroup gpdma_defines General Purpose DMA Defines * * @brief Defined Constants and Types for the LPC43xx General Purpose DMA * * @ingroup LPC43xx_defines * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann * * @date 10 March 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_GPDMA_H #define LPC43XX_GPDMA_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif typedef struct gpdma_lli_t gpdma_lli_t; struct gpdma_lli_t { void* csrcaddr; void* cdestaddr; uint32_t clli; uint32_t ccontrol; }; /* --- GPDMA registers ----------------------------------------------------- */ /* General registers */ /* DMA Interrupt Status Register */ #define GPDMA_INTSTAT MMIO32(GPDMA_BASE + 0x000) /* DMA Interrupt Terminal Count Request Status Register */ #define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004) /* DMA Interrupt Terminal Count Request Clear Register */ #define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008) /* DMA Interrupt Error Status Register */ #define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C) /* DMA Interrupt Error Clear Register */ #define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010) /* DMA Raw Interrupt Terminal Count Status Register */ #define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014) /* DMA Raw Error Interrupt Status Register */ #define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018) /* DMA Enabled Channel Register */ #define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C) /* DMA Software Burst Request Register */ #define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020) /* DMA Software Single Request Register */ #define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024) /* DMA Software Last Burst Request Register */ #define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028) /* DMA Software Last Single Request Register */ #define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C) /* DMA Configuration Register */ #define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030) /* DMA Synchronization Register */ #define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034) /* Channel registers */ /* Source Address Register */ #define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + 0x100 + \ (channel * 0x20)) #define GPDMA_C0SRCADDR GPDMA_CSRCADDR(0) #define GPDMA_C1SRCADDR GPDMA_CSRCADDR(1) #define GPDMA_C2SRCADDR GPDMA_CSRCADDR(2) #define GPDMA_C3SRCADDR GPDMA_CSRCADDR(3) #define GPDMA_C4SRCADDR GPDMA_CSRCADDR(4) #define GPDMA_C5SRCADDR GPDMA_CSRCADDR(5) #define GPDMA_C6SRCADDR GPDMA_CSRCADDR(6) #define GPDMA_C7SRCADDR GPDMA_CSRCADDR(7) /* Destination Address Register */ #define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + 0x104 + \ (channel * 0x20)) #define GPDMA_C0DESTADDR GPDMA_CDESTADDR(0) #define GPDMA_C1DESTADDR GPDMA_CDESTADDR(1) #define GPDMA_C2DESTADDR GPDMA_CDESTADDR(2) #define GPDMA_C3DESTADDR GPDMA_CDESTADDR(3) #define GPDMA_C4DESTADDR GPDMA_CDESTADDR(4) #define GPDMA_C5DESTADDR GPDMA_CDESTADDR(5) #define GPDMA_C6DESTADDR GPDMA_CDESTADDR(6) #define GPDMA_C7DESTADDR GPDMA_CDESTADDR(7) /* Linked List Item Register */ #define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + 0x108 + \ (channel * 0x20)) #define GPDMA_C0LLI GPDMA_CLLI(0) #define GPDMA_C1LLI GPDMA_CLLI(1) #define GPDMA_C2LLI GPDMA_CLLI(2) #define GPDMA_C3LLI GPDMA_CLLI(3) #define GPDMA_C4LLI GPDMA_CLLI(4) #define GPDMA_C5LLI GPDMA_CLLI(5) #define GPDMA_C6LLI GPDMA_CLLI(6) #define GPDMA_C7LLI GPDMA_CLLI(7) /* Control Register */ #define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + 0x10C + \ (channel * 0x20)) #define GPDMA_C0CONTROL GPDMA_CCONTROL(0) #define GPDMA_C1CONTROL GPDMA_CCONTROL(1) #define GPDMA_C2CONTROL GPDMA_CCONTROL(2) #define GPDMA_C3CONTROL GPDMA_CCONTROL(3) #define GPDMA_C4CONTROL GPDMA_CCONTROL(4) #define GPDMA_C5CONTROL GPDMA_CCONTROL(5) #define GPDMA_C6CONTROL GPDMA_CCONTROL(6) #define GPDMA_C7CONTROL GPDMA_CCONTROL(7) /* Configuration Register */ #define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + 0x110 + \ (channel * 0x20)) #define GPDMA_C0CONFIG GPDMA_CCONFIG(0) #define GPDMA_C1CONFIG GPDMA_CCONFIG(1) #define GPDMA_C2CONFIG GPDMA_CCONFIG(2) #define GPDMA_C3CONFIG GPDMA_CCONFIG(3) #define GPDMA_C4CONFIG GPDMA_CCONFIG(4) #define GPDMA_C5CONFIG GPDMA_CCONFIG(5) #define GPDMA_C6CONFIG GPDMA_CCONFIG(6) #define GPDMA_C7CONFIG GPDMA_CCONFIG(7) /* --- Common fields -------------------------------------------- */ #define GPDMA_CSRCADDR_SRCADDR_SHIFT (0) #define GPDMA_CSRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_CSRCADDR_SRCADDR_SHIFT) #define GPDMA_CSRCADDR_SRCADDR(x) ((x) << GPDMA_CSRCADDR_SRCADDR_SHIFT) #define GPDMA_CDESTADDR_DESTADDR_SHIFT (0) #define GPDMA_CDESTADDR_DESTADDR_MASK \ (0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT) #define GPDMA_CDESTADDR_DESTADDR(x) ((x) << GPDMA_CDESTADDR_DESTADDR_SHIFT) #define GPDMA_CLLI_LM_SHIFT (0) #define GPDMA_CLLI_LM_MASK (0x1 << GPDMA_CLLI_LM_SHIFT) #define GPDMA_CLLI_LM(x) ((x) << GPDMA_CLLI_LM_SHIFT) #define GPDMA_CLLI_LLI_SHIFT (2) #define GPDMA_CLLI_LLI_MASK (0x3fffffff << GPDMA_CLLI_LLI_SHIFT) #define GPDMA_CLLI_LLI(x) ((x) << GPDMA_CLLI_LLI_SHIFT) #define GPDMA_CCONTROL_TRANSFERSIZE_SHIFT (0) #define GPDMA_CCONTROL_TRANSFERSIZE_MASK \ (0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) #define GPDMA_CCONTROL_TRANSFERSIZE(x) \ ((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) #define GPDMA_CCONTROL_SBSIZE_SHIFT (12) #define GPDMA_CCONTROL_SBSIZE_MASK (0x7 << GPDMA_CCONTROL_SBSIZE_SHIFT) #define GPDMA_CCONTROL_SBSIZE(x) ((x) << GPDMA_CCONTROL_SBSIZE_SHIFT) #define GPDMA_CCONTROL_DBSIZE_SHIFT (15) #define GPDMA_CCONTROL_DBSIZE_MASK (0x7 << GPDMA_CCONTROL_DBSIZE_SHIFT) #define GPDMA_CCONTROL_DBSIZE(x) ((x) << GPDMA_CCONTROL_DBSIZE_SHIFT) #define GPDMA_CCONTROL_SWIDTH_SHIFT (18) #define GPDMA_CCONTROL_SWIDTH_MASK (0x7 << GPDMA_CCONTROL_SWIDTH_SHIFT) #define GPDMA_CCONTROL_SWIDTH(x) ((x) << GPDMA_CCONTROL_SWIDTH_SHIFT) #define GPDMA_CCONTROL_DWIDTH_SHIFT (21) #define GPDMA_CCONTROL_DWIDTH_MASK (0x7 << GPDMA_CCONTROL_DWIDTH_SHIFT) #define GPDMA_CCONTROL_DWIDTH(x) ((x) << GPDMA_CCONTROL_DWIDTH_SHIFT) #define GPDMA_CCONTROL_S_SHIFT (24) #define GPDMA_CCONTROL_S_MASK (0x1 << GPDMA_CCONTROL_S_SHIFT) #define GPDMA_CCONTROL_S(x) ((x) << GPDMA_CCONTROL_S_SHIFT) #define GPDMA_CCONTROL_D_SHIFT (25) #define GPDMA_CCONTROL_D_MASK (0x1 << GPDMA_CCONTROL_D_SHIFT) #define GPDMA_CCONTROL_D(x) ((x) << GPDMA_CCONTROL_D_SHIFT) #define GPDMA_CCONTROL_SI_SHIFT (26) #define GPDMA_CCONTROL_SI_MASK (0x1 << GPDMA_CCONTROL_SI_SHIFT) #define GPDMA_CCONTROL_SI(x) ((x) << GPDMA_CCONTROL_SI_SHIFT) #define GPDMA_CCONTROL_DI_SHIFT (27) #define GPDMA_CCONTROL_DI_MASK (0x1 << GPDMA_CCONTROL_DI_SHIFT) #define GPDMA_CCONTROL_DI(x) ((x) << GPDMA_CCONTROL_DI_SHIFT) #define GPDMA_CCONTROL_PROT1_SHIFT (28) #define GPDMA_CCONTROL_PROT1_MASK (0x1 << GPDMA_CCONTROL_PROT1_SHIFT) #define GPDMA_CCONTROL_PROT1(x) ((x) << GPDMA_CCONTROL_PROT1_SHIFT) #define GPDMA_CCONTROL_PROT2_SHIFT (29) #define GPDMA_CCONTROL_PROT2_MASK (0x1 << GPDMA_CCONTROL_PROT2_SHIFT) #define GPDMA_CCONTROL_PROT2(x) ((x) << GPDMA_CCONTROL_PROT2_SHIFT) #define GPDMA_CCONTROL_PROT3_SHIFT (30) #define GPDMA_CCONTROL_PROT3_MASK (0x1 << GPDMA_CCONTROL_PROT3_SHIFT) #define GPDMA_CCONTROL_PROT3(x) ((x) << GPDMA_CCONTROL_PROT3_SHIFT) #define GPDMA_CCONTROL_I_SHIFT (31) #define GPDMA_CCONTROL_I_MASK (0x1 << GPDMA_CCONTROL_I_SHIFT) #define GPDMA_CCONTROL_I(x) ((x) << GPDMA_CCONTROL_I_SHIFT) #define GPDMA_CCONFIG_E_SHIFT (0) #define GPDMA_CCONFIG_E_MASK (0x1 << GPDMA_CCONFIG_E_SHIFT) #define GPDMA_CCONFIG_E(x) ((x) << GPDMA_CCONFIG_E_SHIFT) #define GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT (1) #define GPDMA_CCONFIG_SRCPERIPHERAL_MASK \ (0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) #define GPDMA_CCONFIG_SRCPERIPHERAL(x) \ ((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) #define GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT (6) #define GPDMA_CCONFIG_DESTPERIPHERAL_MASK \ (0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) #define GPDMA_CCONFIG_DESTPERIPHERAL(x) \ ((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) #define GPDMA_CCONFIG_FLOWCNTRL_SHIFT (11) #define GPDMA_CCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) #define GPDMA_CCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) #define GPDMA_CCONFIG_IE_SHIFT (14) #define GPDMA_CCONFIG_IE_MASK (0x1 << GPDMA_CCONFIG_IE_SHIFT) #define GPDMA_CCONFIG_IE(x) ((x) << GPDMA_CCONFIG_IE_SHIFT) #define GPDMA_CCONFIG_ITC_SHIFT (15) #define GPDMA_CCONFIG_ITC_MASK (0x1 << GPDMA_CCONFIG_ITC_SHIFT) #define GPDMA_CCONFIG_ITC(x) ((x) << GPDMA_CCONFIG_ITC_SHIFT) #define GPDMA_CCONFIG_L_SHIFT (16) #define GPDMA_CCONFIG_L_MASK (0x1 << GPDMA_CCONFIG_L_SHIFT) #define GPDMA_CCONFIG_L(x) ((x) << GPDMA_CCONFIG_L_SHIFT) #define GPDMA_CCONFIG_A_SHIFT (17) #define GPDMA_CCONFIG_A_MASK (0x1 << GPDMA_CCONFIG_A_SHIFT) #define GPDMA_CCONFIG_A(x) ((x) << GPDMA_CCONFIG_A_SHIFT) #define GPDMA_CCONFIG_H_SHIFT (18) #define GPDMA_CCONFIG_H_MASK (0x1 << GPDMA_CCONFIG_H_SHIFT) #define GPDMA_CCONFIG_H(x) ((x) << GPDMA_CCONFIG_H_SHIFT) /* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ /* --- GPDMA_NTSTAT values -------------------------------------- */ /* INTSTAT: Status of DMA channel interrupts after masking */ #define GPDMA_NTSTAT_INTSTAT_SHIFT (0) #define GPDMA_NTSTAT_INTSTAT_MASK (0xff << GPDMA_NTSTAT_INTSTAT_SHIFT) #define GPDMA_NTSTAT_INTSTAT(x) ((x) << GPDMA_NTSTAT_INTSTAT_SHIFT) /* --- GPDMA_INTTCSTAT values ----------------------------------- */ /* INTTCSTAT: Terminal count interrupt request status for DMA channels */ #define GPDMA_INTTCSTAT_INTTCSTAT_SHIFT (0) #define GPDMA_INTTCSTAT_INTTCSTAT_MASK (0xff << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) #define GPDMA_INTTCSTAT_INTTCSTAT(x) ((x) << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) /* --- GPDMA_INTTCCLEAR values ---------------------------------- */ /* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels */ #define GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT (0) #define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK \ (0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) #define GPDMA_INTTCCLEAR_INTTCCLEAR(x) \ ((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) /* --- GPDMA_INTERRSTAT values ---------------------------------- */ /* INTERRSTAT: Interrupt error status for DMA channels */ #define GPDMA_INTERRSTAT_INTERRSTAT_SHIFT (0) #define GPDMA_INTERRSTAT_INTERRSTAT_MASK \ (0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) #define GPDMA_INTERRSTAT_INTERRSTAT(x) \ ((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) /* --- GPDMA_INTERRCLR values ----------------------------------- */ /* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels */ #define GPDMA_INTERRCLR_INTERRCLR_SHIFT (0) #define GPDMA_INTERRCLR_INTERRCLR_MASK \ (0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT) #define GPDMA_INTERRCLR_INTERRCLR(x) \ ((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT) /* --- GPDMA_RAWINTTCSTAT values -------------------------------- */ /* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels prior to masking */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT (0) #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK \ (0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) \ ((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) /* --- GPDMA_RAWINTERRSTAT values ------------------------------- */ /* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to masking */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT (0) #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK \ (0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) \ ((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) /* --- GPDMA_ENBLDCHNS values ----------------------------------- */ /* ENABLEDCHANNELS: Enable status for DMA channels */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT (0) #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK \ (0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) \ ((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) /* --- GPDMA_SOFTBREQ values ------------------------------------ */ /* SOFTBREQ: Software burst request flags for each of 16 possible sources */ #define GPDMA_SOFTBREQ_SOFTBREQ_SHIFT (0) #define GPDMA_SOFTBREQ_SOFTBREQ_MASK (0xffff << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) #define GPDMA_SOFTBREQ_SOFTBREQ(x) ((x) << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) /* --- GPDMA_SOFTSREQ values ------------------------------------ */ /* SOFTSREQ: Software single transfer request flags for each of 16 possible sources */ #define GPDMA_SOFTSREQ_SOFTSREQ_SHIFT (0) #define GPDMA_SOFTSREQ_SOFTSREQ_MASK (0xffff << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) #define GPDMA_SOFTSREQ_SOFTSREQ(x) ((x) << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) /* --- GPDMA_SOFTLBREQ values ----------------------------------- */ /* SOFTLBREQ: Software last burst request flags for each of 16 possible sources */ #define GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT (0) #define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK \ (0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) #define GPDMA_SOFTLBREQ_SOFTLBREQ(x) \ ((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) /* --- GPDMA_SOFTLSREQ values ----------------------------------- */ /* SOFTLSREQ: Software last single transfer request flags for each of 16 possible sources */ #define GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT (0) #define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK \ (0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) #define GPDMA_SOFTLSREQ_SOFTLSREQ(x) \ ((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) /* --- GPDMA_CONFIG values -------------------------------------- */ /* E: DMA Controller enable */ #define GPDMA_CONFIG_E_SHIFT (0) #define GPDMA_CONFIG_E_MASK (0x1 << GPDMA_CONFIG_E_SHIFT) #define GPDMA_CONFIG_E(x) ((x) << GPDMA_CONFIG_E_SHIFT) /* M0: AHB Master 0 endianness configuration */ #define GPDMA_CONFIG_M0_SHIFT (1) #define GPDMA_CONFIG_M0_MASK (0x1 << GPDMA_CONFIG_M0_SHIFT) #define GPDMA_CONFIG_M0(x) ((x) << GPDMA_CONFIG_M0_SHIFT) /* M1: AHB Master 1 endianness configuration */ #define GPDMA_CONFIG_M1_SHIFT (2) #define GPDMA_CONFIG_M1_MASK (0x1 << GPDMA_CONFIG_M1_SHIFT) #define GPDMA_CONFIG_M1(x) ((x) << GPDMA_CONFIG_M1_SHIFT) /* --- GPDMA_SYNC values ---------------------------------------- */ /* DMACSYNC: Controls the synchronization logic for DMA request signals */ #define GPDMA_SYNC_DMACSYNC_SHIFT (0) #define GPDMA_SYNC_DMACSYNC_MASK (0xffff << GPDMA_SYNC_DMACSYNC_SHIFT) #define GPDMA_SYNC_DMACSYNC(x) ((x) << GPDMA_SYNC_DMACSYNC_SHIFT) /* --- GPDMA_C[0..7]SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_CxSRCADDR_SRCADDR_SHIFT (0) #define GPDMA_CxSRCADDR_SRCADDR_MASK \ (0xffffffff << GPDMA_CxSRCADDR_SRCADDR_SHIFT) #define GPDMA_CxSRCADDR_SRCADDR(x) ((x) << GPDMA_CxSRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C[0..7]DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_CxDESTADDR_DESTADDR_SHIFT (0) #define GPDMA_CxDESTADDR_DESTADDR_MASK \ (0xffffffff << GPDMA_CxDESTADDR_DESTADDR_SHIFT) #define GPDMA_CxDESTADDR_DESTADDR(x) ((x) << GPDMA_CxDESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C[0..7]LLI values --------------------------------------- */ /* LM: AHB master select for loading the next LLI */ #define GPDMA_CxLLI_LM_SHIFT (0) #define GPDMA_CxLLI_LM_MASK (0x1 << GPDMA_CxLLI_LM_SHIFT) #define GPDMA_CxLLI_LM(x) ((x) << GPDMA_CxLLI_LM_SHIFT) /* LLI: Linked list item */ #define GPDMA_CxLLI_LLI_SHIFT (2) #define GPDMA_CxLLI_LLI_MASK (0x3fffffff << GPDMA_CxLLI_LLI_SHIFT) #define GPDMA_CxLLI_LLI(x) ((x) << GPDMA_CxLLI_LLI_SHIFT) /* --- GPDMA_C[0..7]CONTROL values ----------------------------------- */ /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT (0) #define GPDMA_CxCONTROL_TRANSFERSIZE_MASK \ (0xfff << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) #define GPDMA_CxCONTROL_TRANSFERSIZE(x) \ ((x) << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_CxCONTROL_SBSIZE_SHIFT (12) #define GPDMA_CxCONTROL_SBSIZE_MASK (0x7 << GPDMA_CxCONTROL_SBSIZE_SHIFT) #define GPDMA_CxCONTROL_SBSIZE(x) ((x) << GPDMA_CxCONTROL_SBSIZE_SHIFT) /* DBSIZE: Destination burst size */ #define GPDMA_CxCONTROL_DBSIZE_SHIFT (15) #define GPDMA_CxCONTROL_DBSIZE_MASK (0x7 << GPDMA_CxCONTROL_DBSIZE_SHIFT) #define GPDMA_CxCONTROL_DBSIZE(x) ((x) << GPDMA_CxCONTROL_DBSIZE_SHIFT) /* SWIDTH: Source transfer width */ #define GPDMA_CxCONTROL_SWIDTH_SHIFT (18) #define GPDMA_CxCONTROL_SWIDTH_MASK (0x7 << GPDMA_CxCONTROL_SWIDTH_SHIFT) #define GPDMA_CxCONTROL_SWIDTH(x) ((x) << GPDMA_CxCONTROL_SWIDTH_SHIFT) /* DWIDTH: Destination transfer width */ #define GPDMA_CxCONTROL_DWIDTH_SHIFT (21) #define GPDMA_CxCONTROL_DWIDTH_MASK (0x7 << GPDMA_CxCONTROL_DWIDTH_SHIFT) #define GPDMA_CxCONTROL_DWIDTH(x) ((x) << GPDMA_CxCONTROL_DWIDTH_SHIFT) /* S: Source AHB master select */ #define GPDMA_CxCONTROL_S_SHIFT (24) #define GPDMA_CxCONTROL_S_MASK (0x1 << GPDMA_CxCONTROL_S_SHIFT) #define GPDMA_CxCONTROL_S(x) ((x) << GPDMA_CxCONTROL_S_SHIFT) /* D: Destination AHB master select */ #define GPDMA_CxCONTROL_D_SHIFT (25) #define GPDMA_CxCONTROL_D_MASK (0x1 << GPDMA_CxCONTROL_D_SHIFT) #define GPDMA_CxCONTROL_D(x) ((x) << GPDMA_CxCONTROL_D_SHIFT) /* SI: Source increment */ #define GPDMA_CxCONTROL_SI_SHIFT (26) #define GPDMA_CxCONTROL_SI_MASK (0x1 << GPDMA_CxCONTROL_SI_SHIFT) #define GPDMA_Cx0CONTROL_SI(x) ((x) << GPDMA_CxCONTROL_SI_SHIFT) /* DI: Destination increment */ #define GPDMA_CxCONTROL_DI_SHIFT (27) #define GPDMA_CxCONTROL_DI_MASK (0x1 << GPDMA_CxCONTROL_DI_SHIFT) #define GPDMA_CxCONTROL_DI(x) ((x) << GPDMA_CxCONTROL_DI_SHIFT) /* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ #define GPDMA_CxCONTROL_PROT1_SHIFT (28) #define GPDMA_CxCONTROL_PROT1_MASK (0x1 << GPDMA_CxCONTROL_PROT1_SHIFT) #define GPDMA_CxCONTROL_PROT1(x) ((x) << GPDMA_CxCONTROL_PROT1_SHIFT) /* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ #define GPDMA_CxCONTROL_PROT2_SHIFT (29) #define GPDMA_CxCONTROL_PROT2_MASK (0x1 << GPDMA_CxCONTROL_PROT2_SHIFT) #define GPDMA_CxCONTROL_PROT2(x) ((x) << GPDMA_CxCONTROL_PROT2_SHIFT) /* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ #define GPDMA_CxCONTROL_PROT3_SHIFT (30) #define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT) #define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT) /* I: Terminal count interrupt enable bit */ #define GPDMA_CxCONTROL_I_SHIFT (31) #define GPDMA_CxCONTROL_I_MASK (0x1 << GPDMA_CxCONTROL_I_SHIFT) #define GPDMA_CxCONTROL_I(x) ((x) << GPDMA_CxCONTROL_I_SHIFT) /* --- GPDMA_C[0..7]CONFIG values ------------------------------------ */ /* E: Channel enable */ #define GPDMA_CxCONFIG_E_SHIFT (0) #define GPDMA_CxCONFIG_E_MASK (0x1 << GPDMA_CxCONFIG_E_SHIFT) #define GPDMA_CxCONFIG_E(x) ((x) << GPDMA_CxCONFIG_E_SHIFT) /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT (1) #define GPDMA_CxCONFIG_SRCPERIPHERAL_MASK \ (0x1f << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) #define GPDMA_CxCONFIG_SRCPERIPHERAL(x) \ ((x) << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT (6) #define GPDMA_CxCONFIG_DESTPERIPHERAL_MASK \ (0x1f << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) #define GPDMA_CxCONFIG_DESTPERIPHERAL(x) \ ((x) << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_CxCONFIG_FLOWCNTRL_SHIFT (11) #define GPDMA_CxCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) #define GPDMA_CxCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) /* IE: Interrupt error mask */ #define GPDMA_CxCONFIG_IE_SHIFT (14) #define GPDMA_CxCONFIG_IE_MASK (0x1 << GPDMA_CxCONFIG_IE_SHIFT) #define GPDMA_CxCONFIG_IE(x) ((x) << GPDMA_CxCONFIG_IE_SHIFT) /* ITC: Terminal count interrupt mask */ #define GPDMA_CxCONFIG_ITC_SHIFT (15) #define GPDMA_CxCONFIG_ITC_MASK (0x1 << GPDMA_CxCONFIG_ITC_SHIFT) #define GPDMA_CxCONFIG_ITC(x) ((x) << GPDMA_CxCONFIG_ITC_SHIFT) /* L: Lock */ #define GPDMA_CxCONFIG_L_SHIFT (16) #define GPDMA_CxCONFIG_L_MASK (0x1 << GPDMA_CxCONFIG_L_SHIFT) #define GPDMA_CxCONFIG_L(x) ((x) << GPDMA_CxCONFIG_L_SHIFT) /* A: Active */ #define GPDMA_CxCONFIG_A_SHIFT (17) #define GPDMA_CxCONFIG_A_MASK (0x1 << GPDMA_CxCONFIG_A_SHIFT) #define GPDMA_CxCONFIG_A(x) ((x) << GPDMA_CxCONFIG_A_SHIFT) /* H: Halt */ #define GPDMA_CxCONFIG_H_SHIFT (18) #define GPDMA_CxCONFIG_H_MASK (0x1 << GPDMA_CxCONFIG_H_SHIFT) #define GPDMA_CxCONFIG_H(x) ((x) << GPDMA_CxCONFIG_H_SHIFT) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/gpio.h000066400000000000000000001276401435536612600235750ustar00rootroot00000000000000/** @defgroup gpio_defines General Purpose I/O Defines @brief Defined Constants and Types for the LPC43xx General Purpose I/O @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @author @htmlonly © @endhtmlonly 2014 Jared Boone @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2014 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_GPIO_H #define LPC43XX_GPIO_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* GPIO port base addresses (for convenience) */ #define GPIO0 (GPIO_PORT_BASE + 0x2000) #define GPIO1 (GPIO_PORT_BASE + 0x2004) #define GPIO2 (GPIO_PORT_BASE + 0x2008) #define GPIO3 (GPIO_PORT_BASE + 0x200C) #define GPIO4 (GPIO_PORT_BASE + 0x2010) #define GPIO5 (GPIO_PORT_BASE + 0x2014) #define GPIO6 (GPIO_PORT_BASE + 0x2018) #define GPIO7 (GPIO_PORT_BASE + 0x201C) /* GPIO number definitions (for convenience) */ #define GPIOPIN0 (1 << 0) #define GPIOPIN1 (1 << 1) #define GPIOPIN2 (1 << 2) #define GPIOPIN3 (1 << 3) #define GPIOPIN4 (1 << 4) #define GPIOPIN5 (1 << 5) #define GPIOPIN6 (1 << 6) #define GPIOPIN7 (1 << 7) #define GPIOPIN8 (1 << 8) #define GPIOPIN9 (1 << 9) #define GPIOPIN10 (1 << 10) #define GPIOPIN11 (1 << 11) #define GPIOPIN12 (1 << 12) #define GPIOPIN13 (1 << 13) #define GPIOPIN14 (1 << 14) #define GPIOPIN15 (1 << 15) #define GPIOPIN16 (1 << 16) #define GPIOPIN17 (1 << 17) #define GPIOPIN18 (1 << 18) #define GPIOPIN19 (1 << 19) #define GPIOPIN20 (1 << 20) #define GPIOPIN21 (1 << 21) #define GPIOPIN22 (1 << 22) #define GPIOPIN23 (1 << 23) #define GPIOPIN24 (1 << 24) #define GPIOPIN25 (1 << 25) #define GPIOPIN26 (1 << 26) #define GPIOPIN27 (1 << 27) #define GPIOPIN28 (1 << 28) #define GPIOPIN29 (1 << 29) #define GPIOPIN30 (1 << 30) #define GPIOPIN31 (1 << 31) /* --- GPIO registers ------------------------------------------------------ */ /* GPIO pin interrupts */ /* Pin Interrupt Mode register */ #define GPIO_PIN_INTERRUPT_ISEL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x000) /* Pin interrupt level (rising edge) interrupt enable register */ #define GPIO_PIN_INTERRUPT_IENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x004) /* Pin interrupt level (rising edge) interrupt set register */ #define GPIO_PIN_INTERRUPT_SIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x008) /* Pin interrupt level (rising edge interrupt) clear register */ #define GPIO_PIN_INTERRUPT_CIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x00C) /* Pin interrupt active level (falling edge) interrupt enable register */ #define GPIO_PIN_INTERRUPT_IENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x010) /* Pin interrupt active level (falling edge) interrupt set register */ #define GPIO_PIN_INTERRUPT_SIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x014) /* Pin interrupt active level (falling edge) interrupt clear register */ #define GPIO_PIN_INTERRUPT_CIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x018) /* Pin interrupt rising edge register */ #define GPIO_PIN_INTERRUPT_RISE MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x01C) /* Pin interrupt falling edge register */ #define GPIO_PIN_INTERRUPT_FALL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x020) /* Pin interrupt status register */ #define GPIO_PIN_INTERRUPT_IST MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x024) /* GPIO GROUP0 interrupt */ /* GPIO grouped interrupt control register */ #define GPIO_GROUP0_INTERRUPT_CTRL \ MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000) /* GPIO grouped interrupt port [0..7] polarity register */ #define GPIO_GROUP0_INTERRUPT_PORT_POL(x) \ MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4)) /* GPIO grouped interrupt port [0..7] enable register */ #define GPIO_GROUP0_INTERRUPT_PORT_ENA(x) \ MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4)) /* GPIO GROUP1 interrupt */ /* GPIO grouped interrupt control register */ #define GPIO_GROUP1_INTERRUPT_CTRL \ MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000) /* GPIO grouped interrupt port [0..7] polarity register */ #define GPIO_GROUP1_INTERRUPT_PORT_POL(x) \ MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4)) /* GPIO grouped interrupt port [0..7] enable register */ #define GPIO_GROUP1_INTERRUPT_PORT_ENA(x) \ MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4)) /* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */ #define GPIO_B0 (GPIO_PORT_BASE + 0x0000) #define GPIO_B1 (GPIO_PORT_BASE + 0x0001) #define GPIO_B2 (GPIO_PORT_BASE + 0x0002) #define GPIO_B3 (GPIO_PORT_BASE + 0x0003) #define GPIO_B4 (GPIO_PORT_BASE + 0x0004) #define GPIO_B5 (GPIO_PORT_BASE + 0x0005) #define GPIO_B6 (GPIO_PORT_BASE + 0x0006) #define GPIO_B7 (GPIO_PORT_BASE + 0x0007) #define GPIO_B8 (GPIO_PORT_BASE + 0x0008) #define GPIO_B9 (GPIO_PORT_BASE + 0x0009) #define GPIO_B10 (GPIO_PORT_BASE + 0x000A) #define GPIO_B11 (GPIO_PORT_BASE + 0x000B) #define GPIO_B12 (GPIO_PORT_BASE + 0x000C) #define GPIO_B13 (GPIO_PORT_BASE + 0x000D) #define GPIO_B14 (GPIO_PORT_BASE + 0x000E) #define GPIO_B15 (GPIO_PORT_BASE + 0x000F) #define GPIO_B16 (GPIO_PORT_BASE + 0x0010) #define GPIO_B17 (GPIO_PORT_BASE + 0x0011) #define GPIO_B18 (GPIO_PORT_BASE + 0x0012) #define GPIO_B19 (GPIO_PORT_BASE + 0x0013) #define GPIO_B20 (GPIO_PORT_BASE + 0x0014) #define GPIO_B21 (GPIO_PORT_BASE + 0x0015) #define GPIO_B22 (GPIO_PORT_BASE + 0x0016) #define GPIO_B23 (GPIO_PORT_BASE + 0x0017) #define GPIO_B24 (GPIO_PORT_BASE + 0x0018) #define GPIO_B25 (GPIO_PORT_BASE + 0x0019) #define GPIO_B26 (GPIO_PORT_BASE + 0x001A) #define GPIO_B27 (GPIO_PORT_BASE + 0x001B) #define GPIO_B28 (GPIO_PORT_BASE + 0x001C) #define GPIO_B29 (GPIO_PORT_BASE + 0x001D) #define GPIO_B30 (GPIO_PORT_BASE + 0x001E) #define GPIO_B31 (GPIO_PORT_BASE + 0x001F) /* Byte pin registers port 1 (R/W) */ #define GPIO_B32 (GPIO_PORT_BASE + 0x0020) #define GPIO_B33 (GPIO_PORT_BASE + 0x0021) #define GPIO_B34 (GPIO_PORT_BASE + 0x0022) #define GPIO_B35 (GPIO_PORT_BASE + 0x0023) #define GPIO_B36 (GPIO_PORT_BASE + 0x0024) #define GPIO_B37 (GPIO_PORT_BASE + 0x0025) #define GPIO_B38 (GPIO_PORT_BASE + 0x0026) #define GPIO_B39 (GPIO_PORT_BASE + 0x0027) #define GPIO_B40 (GPIO_PORT_BASE + 0x0028) #define GPIO_B41 (GPIO_PORT_BASE + 0x0029) #define GPIO_B42 (GPIO_PORT_BASE + 0x002A) #define GPIO_B43 (GPIO_PORT_BASE + 0x002B) #define GPIO_B44 (GPIO_PORT_BASE + 0x002C) #define GPIO_B45 (GPIO_PORT_BASE + 0x002D) #define GPIO_B46 (GPIO_PORT_BASE + 0x002E) #define GPIO_B47 (GPIO_PORT_BASE + 0x002F) #define GPIO_B48 (GPIO_PORT_BASE + 0x0030) #define GPIO_B49 (GPIO_PORT_BASE + 0x0031) #define GPIO_B50 (GPIO_PORT_BASE + 0x0032) #define GPIO_B51 (GPIO_PORT_BASE + 0x0033) #define GPIO_B52 (GPIO_PORT_BASE + 0x0034) #define GPIO_B53 (GPIO_PORT_BASE + 0x0035) #define GPIO_B54 (GPIO_PORT_BASE + 0x0036) #define GPIO_B55 (GPIO_PORT_BASE + 0x0037) #define GPIO_B56 (GPIO_PORT_BASE + 0x0038) #define GPIO_B57 (GPIO_PORT_BASE + 0x0039) #define GPIO_B58 (GPIO_PORT_BASE + 0x003A) #define GPIO_B59 (GPIO_PORT_BASE + 0x003B) #define GPIO_B60 (GPIO_PORT_BASE + 0x003C) #define GPIO_B61 (GPIO_PORT_BASE + 0x003D) #define GPIO_B62 (GPIO_PORT_BASE + 0x003E) #define GPIO_B63 (GPIO_PORT_BASE + 0x003F) /* Byte pin registers port 2 (R/W) */ #define GPIO_B64 (GPIO_PORT_BASE + 0x0040) #define GPIO_B65 (GPIO_PORT_BASE + 0x0041) #define GPIO_B66 (GPIO_PORT_BASE + 0x0042) #define GPIO_B67 (GPIO_PORT_BASE + 0x0043) #define GPIO_B68 (GPIO_PORT_BASE + 0x0044) #define GPIO_B69 (GPIO_PORT_BASE + 0x0045) #define GPIO_B70 (GPIO_PORT_BASE + 0x0046) #define GPIO_B71 (GPIO_PORT_BASE + 0x0047) #define GPIO_B72 (GPIO_PORT_BASE + 0x0048) #define GPIO_B73 (GPIO_PORT_BASE + 0x0049) #define GPIO_B74 (GPIO_PORT_BASE + 0x004A) #define GPIO_B75 (GPIO_PORT_BASE + 0x004B) #define GPIO_B76 (GPIO_PORT_BASE + 0x004C) #define GPIO_B77 (GPIO_PORT_BASE + 0x004D) #define GPIO_B78 (GPIO_PORT_BASE + 0x004E) #define GPIO_B79 (GPIO_PORT_BASE + 0x004F) #define GPIO_B80 (GPIO_PORT_BASE + 0x0050) #define GPIO_B81 (GPIO_PORT_BASE + 0x0051) #define GPIO_B82 (GPIO_PORT_BASE + 0x0052) #define GPIO_B83 (GPIO_PORT_BASE + 0x0053) #define GPIO_B84 (GPIO_PORT_BASE + 0x0054) #define GPIO_B85 (GPIO_PORT_BASE + 0x0055) #define GPIO_B86 (GPIO_PORT_BASE + 0x0056) #define GPIO_B87 (GPIO_PORT_BASE + 0x0057) #define GPIO_B88 (GPIO_PORT_BASE + 0x0058) #define GPIO_B89 (GPIO_PORT_BASE + 0x0059) #define GPIO_B90 (GPIO_PORT_BASE + 0x005A) #define GPIO_B91 (GPIO_PORT_BASE + 0x005B) #define GPIO_B92 (GPIO_PORT_BASE + 0x005C) #define GPIO_B93 (GPIO_PORT_BASE + 0x005D) #define GPIO_B94 (GPIO_PORT_BASE + 0x005E) #define GPIO_B95 (GPIO_PORT_BASE + 0x005F) /* Byte pin registers port 3 (R/W) */ #define GPIO_B96 (GPIO_PORT_BASE + 0x0060) #define GPIO_B97 (GPIO_PORT_BASE + 0x0061) #define GPIO_B98 (GPIO_PORT_BASE + 0x0062) #define GPIO_B99 (GPIO_PORT_BASE + 0x0063) #define GPIO_B100 (GPIO_PORT_BASE + 0x0064) #define GPIO_B101 (GPIO_PORT_BASE + 0x0065) #define GPIO_B102 (GPIO_PORT_BASE + 0x0066) #define GPIO_B103 (GPIO_PORT_BASE + 0x0067) #define GPIO_B104 (GPIO_PORT_BASE + 0x0068) #define GPIO_B105 (GPIO_PORT_BASE + 0x0069) #define GPIO_B106 (GPIO_PORT_BASE + 0x006A) #define GPIO_B107 (GPIO_PORT_BASE + 0x006B) #define GPIO_B108 (GPIO_PORT_BASE + 0x006C) #define GPIO_B109 (GPIO_PORT_BASE + 0x006D) #define GPIO_B110 (GPIO_PORT_BASE + 0x006E) #define GPIO_B111 (GPIO_PORT_BASE + 0x006F) #define GPIO_B112 (GPIO_PORT_BASE + 0x0070) #define GPIO_B113 (GPIO_PORT_BASE + 0x0071) #define GPIO_B114 (GPIO_PORT_BASE + 0x0072) #define GPIO_B115 (GPIO_PORT_BASE + 0x0073) #define GPIO_B116 (GPIO_PORT_BASE + 0x0074) #define GPIO_B117 (GPIO_PORT_BASE + 0x0075) #define GPIO_B118 (GPIO_PORT_BASE + 0x0076) #define GPIO_B119 (GPIO_PORT_BASE + 0x0077) #define GPIO_B120 (GPIO_PORT_BASE + 0x0078) #define GPIO_B121 (GPIO_PORT_BASE + 0x0079) #define GPIO_B122 (GPIO_PORT_BASE + 0x007A) #define GPIO_B123 (GPIO_PORT_BASE + 0x007B) #define GPIO_B124 (GPIO_PORT_BASE + 0x007C) #define GPIO_B125 (GPIO_PORT_BASE + 0x007D) #define GPIO_B126 (GPIO_PORT_BASE + 0x007E) #define GPIO_B127 (GPIO_PORT_BASE + 0x007F) /* Byte pin registers port 4 (R/W) */ #define GPIO_B128 (GPIO_PORT_BASE + 0x0080) #define GPIO_B129 (GPIO_PORT_BASE + 0x0081) #define GPIO_B130 (GPIO_PORT_BASE + 0x0082) #define GPIO_B131 (GPIO_PORT_BASE + 0x0083) #define GPIO_B132 (GPIO_PORT_BASE + 0x0084) #define GPIO_B133 (GPIO_PORT_BASE + 0x0085) #define GPIO_B134 (GPIO_PORT_BASE + 0x0086) #define GPIO_B135 (GPIO_PORT_BASE + 0x0087) #define GPIO_B136 (GPIO_PORT_BASE + 0x0088) #define GPIO_B137 (GPIO_PORT_BASE + 0x0089) #define GPIO_B138 (GPIO_PORT_BASE + 0x008A) #define GPIO_B139 (GPIO_PORT_BASE + 0x008B) #define GPIO_B140 (GPIO_PORT_BASE + 0x008C) #define GPIO_B141 (GPIO_PORT_BASE + 0x008D) #define GPIO_B142 (GPIO_PORT_BASE + 0x008E) #define GPIO_B143 (GPIO_PORT_BASE + 0x008F) #define GPIO_B144 (GPIO_PORT_BASE + 0x0090) #define GPIO_B145 (GPIO_PORT_BASE + 0x0091) #define GPIO_B146 (GPIO_PORT_BASE + 0x0092) #define GPIO_B147 (GPIO_PORT_BASE + 0x0093) #define GPIO_B148 (GPIO_PORT_BASE + 0x0094) #define GPIO_B149 (GPIO_PORT_BASE + 0x0095) #define GPIO_B150 (GPIO_PORT_BASE + 0x0096) #define GPIO_B151 (GPIO_PORT_BASE + 0x0097) #define GPIO_B152 (GPIO_PORT_BASE + 0x0098) #define GPIO_B153 (GPIO_PORT_BASE + 0x0099) #define GPIO_B154 (GPIO_PORT_BASE + 0x009A) #define GPIO_B155 (GPIO_PORT_BASE + 0x009B) #define GPIO_B156 (GPIO_PORT_BASE + 0x009C) #define GPIO_B157 (GPIO_PORT_BASE + 0x009D) #define GPIO_B158 (GPIO_PORT_BASE + 0x009E) #define GPIO_B159 (GPIO_PORT_BASE + 0x009F) /* Byte pin registers port 5 (R/W) */ #define GPIO_B160 (GPIO_PORT_BASE + 0x00A0) #define GPIO_B161 (GPIO_PORT_BASE + 0x00A1) #define GPIO_B162 (GPIO_PORT_BASE + 0x00A2) #define GPIO_B163 (GPIO_PORT_BASE + 0x00A3) #define GPIO_B164 (GPIO_PORT_BASE + 0x00A4) #define GPIO_B165 (GPIO_PORT_BASE + 0x00A5) #define GPIO_B166 (GPIO_PORT_BASE + 0x00A6) #define GPIO_B167 (GPIO_PORT_BASE + 0x00A7) #define GPIO_B168 (GPIO_PORT_BASE + 0x00A8) #define GPIO_B169 (GPIO_PORT_BASE + 0x00A9) #define GPIO_B170 (GPIO_PORT_BASE + 0x00AA) #define GPIO_B171 (GPIO_PORT_BASE + 0x00AB) #define GPIO_B172 (GPIO_PORT_BASE + 0x00AC) #define GPIO_B173 (GPIO_PORT_BASE + 0x00AD) #define GPIO_B174 (GPIO_PORT_BASE + 0x00AE) #define GPIO_B175 (GPIO_PORT_BASE + 0x00AF) #define GPIO_B176 (GPIO_PORT_BASE + 0x00B0) #define GPIO_B177 (GPIO_PORT_BASE + 0x00B1) #define GPIO_B178 (GPIO_PORT_BASE + 0x00B2) #define GPIO_B179 (GPIO_PORT_BASE + 0x00B3) #define GPIO_B180 (GPIO_PORT_BASE + 0x00B4) #define GPIO_B181 (GPIO_PORT_BASE + 0x00B5) #define GPIO_B182 (GPIO_PORT_BASE + 0x00B6) #define GPIO_B183 (GPIO_PORT_BASE + 0x00B7) #define GPIO_B184 (GPIO_PORT_BASE + 0x00B8) #define GPIO_B185 (GPIO_PORT_BASE + 0x00B9) #define GPIO_B186 (GPIO_PORT_BASE + 0x00BA) #define GPIO_B187 (GPIO_PORT_BASE + 0x00BB) #define GPIO_B188 (GPIO_PORT_BASE + 0x00BC) #define GPIO_B189 (GPIO_PORT_BASE + 0x00BD) #define GPIO_B190 (GPIO_PORT_BASE + 0x00BE) #define GPIO_B191 (GPIO_PORT_BASE + 0x00BF) /* Byte pin registers port 6 (R/W) */ #define GPIO_B192 (GPIO_PORT_BASE + 0x00C0) #define GPIO_B193 (GPIO_PORT_BASE + 0x00C1) #define GPIO_B194 (GPIO_PORT_BASE + 0x00C2) #define GPIO_B195 (GPIO_PORT_BASE + 0x00C3) #define GPIO_B196 (GPIO_PORT_BASE + 0x00C4) #define GPIO_B197 (GPIO_PORT_BASE + 0x00C5) #define GPIO_B198 (GPIO_PORT_BASE + 0x00C6) #define GPIO_B199 (GPIO_PORT_BASE + 0x00C7) #define GPIO_B200 (GPIO_PORT_BASE + 0x00C8) #define GPIO_B201 (GPIO_PORT_BASE + 0x00C9) #define GPIO_B202 (GPIO_PORT_BASE + 0x00CA) #define GPIO_B203 (GPIO_PORT_BASE + 0x00CB) #define GPIO_B204 (GPIO_PORT_BASE + 0x00CC) #define GPIO_B205 (GPIO_PORT_BASE + 0x00CD) #define GPIO_B206 (GPIO_PORT_BASE + 0x00CE) #define GPIO_B207 (GPIO_PORT_BASE + 0x00CF) #define GPIO_B208 (GPIO_PORT_BASE + 0x00D0) #define GPIO_B209 (GPIO_PORT_BASE + 0x00D1) #define GPIO_B210 (GPIO_PORT_BASE + 0x00D2) #define GPIO_B211 (GPIO_PORT_BASE + 0x00D3) #define GPIO_B212 (GPIO_PORT_BASE + 0x00D4) #define GPIO_B213 (GPIO_PORT_BASE + 0x00D5) #define GPIO_B214 (GPIO_PORT_BASE + 0x00D6) #define GPIO_B215 (GPIO_PORT_BASE + 0x00D7) #define GPIO_B216 (GPIO_PORT_BASE + 0x00D8) #define GPIO_B217 (GPIO_PORT_BASE + 0x00D9) #define GPIO_B218 (GPIO_PORT_BASE + 0x00DA) #define GPIO_B219 (GPIO_PORT_BASE + 0x00DB) #define GPIO_B220 (GPIO_PORT_BASE + 0x00DC) #define GPIO_B221 (GPIO_PORT_BASE + 0x00DD) #define GPIO_B222 (GPIO_PORT_BASE + 0x00DE) #define GPIO_B223 (GPIO_PORT_BASE + 0x00DF) /* Byte pin registers port 7 (R/W) */ #define GPIO_B224 (GPIO_PORT_BASE + 0x00E0) #define GPIO_B225 (GPIO_PORT_BASE + 0x00E1) #define GPIO_B226 (GPIO_PORT_BASE + 0x00E2) #define GPIO_B227 (GPIO_PORT_BASE + 0x00E3) #define GPIO_B228 (GPIO_PORT_BASE + 0x00E4) #define GPIO_B229 (GPIO_PORT_BASE + 0x00E5) #define GPIO_B230 (GPIO_PORT_BASE + 0x00E6) #define GPIO_B231 (GPIO_PORT_BASE + 0x00E7) #define GPIO_B232 (GPIO_PORT_BASE + 0x00E8) #define GPIO_B233 (GPIO_PORT_BASE + 0x00E9) #define GPIO_B234 (GPIO_PORT_BASE + 0x00EA) #define GPIO_B235 (GPIO_PORT_BASE + 0x00EB) #define GPIO_B236 (GPIO_PORT_BASE + 0x00EC) #define GPIO_B237 (GPIO_PORT_BASE + 0x00ED) #define GPIO_B238 (GPIO_PORT_BASE + 0x00EE) #define GPIO_B239 (GPIO_PORT_BASE + 0x00EF) #define GPIO_B240 (GPIO_PORT_BASE + 0x00F0) #define GPIO_B241 (GPIO_PORT_BASE + 0x00F1) #define GPIO_B242 (GPIO_PORT_BASE + 0x00F2) #define GPIO_B243 (GPIO_PORT_BASE + 0x00F3) #define GPIO_B244 (GPIO_PORT_BASE + 0x00F4) #define GPIO_B245 (GPIO_PORT_BASE + 0x00F5) #define GPIO_B246 (GPIO_PORT_BASE + 0x00F6) #define GPIO_B247 (GPIO_PORT_BASE + 0x00F7) #define GPIO_B248 (GPIO_PORT_BASE + 0x00F8) #define GPIO_B249 (GPIO_PORT_BASE + 0x00F9) #define GPIO_B250 (GPIO_PORT_BASE + 0x00FA) #define GPIO_B251 (GPIO_PORT_BASE + 0x00FB) #define GPIO_B252 (GPIO_PORT_BASE + 0x00FC) #define GPIO_B253 (GPIO_PORT_BASE + 0x00FD) #define GPIO_B254 (GPIO_PORT_BASE + 0x00FE) #define GPIO_B255 (GPIO_PORT_BASE + 0x00FF) /* Word pin registers port 0 (R/W) */ #define GPIO_W0 (GPIO_PORT_BASE + 0x1000) #define GPIO_W1 (GPIO_PORT_BASE + 0x1004) #define GPIO_W2 (GPIO_PORT_BASE + 0x1008) #define GPIO_W3 (GPIO_PORT_BASE + 0x100C) #define GPIO_W4 (GPIO_PORT_BASE + 0x1010) #define GPIO_W5 (GPIO_PORT_BASE + 0x1014) #define GPIO_W6 (GPIO_PORT_BASE + 0x1018) #define GPIO_W7 (GPIO_PORT_BASE + 0x101C) #define GPIO_W8 (GPIO_PORT_BASE + 0x1020) #define GPIO_W9 (GPIO_PORT_BASE + 0x1024) #define GPIO_W10 (GPIO_PORT_BASE + 0x1028) #define GPIO_W11 (GPIO_PORT_BASE + 0x102C) #define GPIO_W12 (GPIO_PORT_BASE + 0x1030) #define GPIO_W13 (GPIO_PORT_BASE + 0x1034) #define GPIO_W14 (GPIO_PORT_BASE + 0x1038) #define GPIO_W15 (GPIO_PORT_BASE + 0x103C) #define GPIO_W16 (GPIO_PORT_BASE + 0x1040) #define GPIO_W17 (GPIO_PORT_BASE + 0x1044) #define GPIO_W18 (GPIO_PORT_BASE + 0x1048) #define GPIO_W19 (GPIO_PORT_BASE + 0x104C) #define GPIO_W20 (GPIO_PORT_BASE + 0x1050) #define GPIO_W21 (GPIO_PORT_BASE + 0x1054) #define GPIO_W22 (GPIO_PORT_BASE + 0x1058) #define GPIO_W23 (GPIO_PORT_BASE + 0x105C) #define GPIO_W24 (GPIO_PORT_BASE + 0x1060) #define GPIO_W25 (GPIO_PORT_BASE + 0x1064) #define GPIO_W26 (GPIO_PORT_BASE + 0x1068) #define GPIO_W27 (GPIO_PORT_BASE + 0x106C) #define GPIO_W28 (GPIO_PORT_BASE + 0x1070) #define GPIO_W29 (GPIO_PORT_BASE + 0x1074) #define GPIO_W30 (GPIO_PORT_BASE + 0x1078) #define GPIO_W31 (GPIO_PORT_BASE + 0x107C) /* Word pin registers port 1 (R/W) */ #define GPIO_W32 (GPIO_PORT_BASE + 0x1080) #define GPIO_W33 (GPIO_PORT_BASE + 0x1084) #define GPIO_W34 (GPIO_PORT_BASE + 0x1088) #define GPIO_W35 (GPIO_PORT_BASE + 0x108C) #define GPIO_W36 (GPIO_PORT_BASE + 0x1090) #define GPIO_W37 (GPIO_PORT_BASE + 0x1094) #define GPIO_W38 (GPIO_PORT_BASE + 0x1098) #define GPIO_W39 (GPIO_PORT_BASE + 0x109C) #define GPIO_W40 (GPIO_PORT_BASE + 0x10A0) #define GPIO_W41 (GPIO_PORT_BASE + 0x10A4) #define GPIO_W42 (GPIO_PORT_BASE + 0x10A8) #define GPIO_W43 (GPIO_PORT_BASE + 0x10AC) #define GPIO_W44 (GPIO_PORT_BASE + 0x10B0) #define GPIO_W45 (GPIO_PORT_BASE + 0x10B4) #define GPIO_W46 (GPIO_PORT_BASE + 0x10B8) #define GPIO_W47 (GPIO_PORT_BASE + 0x10BC) #define GPIO_W48 (GPIO_PORT_BASE + 0x10C0) #define GPIO_W49 (GPIO_PORT_BASE + 0x10C4) #define GPIO_W50 (GPIO_PORT_BASE + 0x10C8) #define GPIO_W51 (GPIO_PORT_BASE + 0x10CC) #define GPIO_W52 (GPIO_PORT_BASE + 0x10D0) #define GPIO_W53 (GPIO_PORT_BASE + 0x10D4) #define GPIO_W54 (GPIO_PORT_BASE + 0x10D8) #define GPIO_W55 (GPIO_PORT_BASE + 0x10DC) #define GPIO_W56 (GPIO_PORT_BASE + 0x10E0) #define GPIO_W57 (GPIO_PORT_BASE + 0x10E4) #define GPIO_W58 (GPIO_PORT_BASE + 0x10E8) #define GPIO_W59 (GPIO_PORT_BASE + 0x10EC) #define GPIO_W60 (GPIO_PORT_BASE + 0x10F0) #define GPIO_W61 (GPIO_PORT_BASE + 0x10F4) #define GPIO_W62 (GPIO_PORT_BASE + 0x10F8) #define GPIO_W63 (GPIO_PORT_BASE + 0x10FC) /* Word pin registers port 2 (R/W) */ #define GPIO_W64 (GPIO_PORT_BASE + 0x1100) #define GPIO_W65 (GPIO_PORT_BASE + 0x1104) #define GPIO_W66 (GPIO_PORT_BASE + 0x1108) #define GPIO_W67 (GPIO_PORT_BASE + 0x110C) #define GPIO_W68 (GPIO_PORT_BASE + 0x1110) #define GPIO_W69 (GPIO_PORT_BASE + 0x1114) #define GPIO_W70 (GPIO_PORT_BASE + 0x1118) #define GPIO_W71 (GPIO_PORT_BASE + 0x111C) #define GPIO_W72 (GPIO_PORT_BASE + 0x1120) #define GPIO_W73 (GPIO_PORT_BASE + 0x1124) #define GPIO_W74 (GPIO_PORT_BASE + 0x1128) #define GPIO_W75 (GPIO_PORT_BASE + 0x112C) #define GPIO_W76 (GPIO_PORT_BASE + 0x1130) #define GPIO_W77 (GPIO_PORT_BASE + 0x1134) #define GPIO_W78 (GPIO_PORT_BASE + 0x1138) #define GPIO_W79 (GPIO_PORT_BASE + 0x113C) #define GPIO_W80 (GPIO_PORT_BASE + 0x1140) #define GPIO_W81 (GPIO_PORT_BASE + 0x1144) #define GPIO_W82 (GPIO_PORT_BASE + 0x1148) #define GPIO_W83 (GPIO_PORT_BASE + 0x114C) #define GPIO_W84 (GPIO_PORT_BASE + 0x1150) #define GPIO_W85 (GPIO_PORT_BASE + 0x1154) #define GPIO_W86 (GPIO_PORT_BASE + 0x1158) #define GPIO_W87 (GPIO_PORT_BASE + 0x115C) #define GPIO_W88 (GPIO_PORT_BASE + 0x1160) #define GPIO_W89 (GPIO_PORT_BASE + 0x1164) #define GPIO_W90 (GPIO_PORT_BASE + 0x1168) #define GPIO_W91 (GPIO_PORT_BASE + 0x116C) #define GPIO_W92 (GPIO_PORT_BASE + 0x1170) #define GPIO_W93 (GPIO_PORT_BASE + 0x1174) #define GPIO_W94 (GPIO_PORT_BASE + 0x1178) #define GPIO_W95 (GPIO_PORT_BASE + 0x117C) /* Word pin registers port 3 (R/W) */ #define GPIO_W96 (GPIO_PORT_BASE + 0x1180) #define GPIO_W97 (GPIO_PORT_BASE + 0x1184) #define GPIO_W98 (GPIO_PORT_BASE + 0x1188) #define GPIO_W99 (GPIO_PORT_BASE + 0x118C) #define GPIO_W100 (GPIO_PORT_BASE + 0x1190) #define GPIO_W101 (GPIO_PORT_BASE + 0x1194) #define GPIO_W102 (GPIO_PORT_BASE + 0x1198) #define GPIO_W103 (GPIO_PORT_BASE + 0x119C) #define GPIO_W104 (GPIO_PORT_BASE + 0x11A0) #define GPIO_W105 (GPIO_PORT_BASE + 0x11A4) #define GPIO_W106 (GPIO_PORT_BASE + 0x11A8) #define GPIO_W107 (GPIO_PORT_BASE + 0x11AC) #define GPIO_W108 (GPIO_PORT_BASE + 0x11B0) #define GPIO_W109 (GPIO_PORT_BASE + 0x11B4) #define GPIO_W110 (GPIO_PORT_BASE + 0x11B8) #define GPIO_W111 (GPIO_PORT_BASE + 0x11BC) #define GPIO_W112 (GPIO_PORT_BASE + 0x11C0) #define GPIO_W113 (GPIO_PORT_BASE + 0x11C4) #define GPIO_W114 (GPIO_PORT_BASE + 0x11C8) #define GPIO_W115 (GPIO_PORT_BASE + 0x11CC) #define GPIO_W116 (GPIO_PORT_BASE + 0x11D0) #define GPIO_W117 (GPIO_PORT_BASE + 0x11D4) #define GPIO_W118 (GPIO_PORT_BASE + 0x11D8) #define GPIO_W119 (GPIO_PORT_BASE + 0x11DC) #define GPIO_W120 (GPIO_PORT_BASE + 0x11E0) #define GPIO_W121 (GPIO_PORT_BASE + 0x11E4) #define GPIO_W122 (GPIO_PORT_BASE + 0x11E8) #define GPIO_W123 (GPIO_PORT_BASE + 0x11EC) #define GPIO_W124 (GPIO_PORT_BASE + 0x11F0) #define GPIO_W125 (GPIO_PORT_BASE + 0x11F4) #define GPIO_W126 (GPIO_PORT_BASE + 0x11F8) #define GPIO_W127 (GPIO_PORT_BASE + 0x11FC) /* Word pin registers port 4 (R/W) */ #define GPIO_W128 (GPIO_PORT_BASE + 0x1200) #define GPIO_W129 (GPIO_PORT_BASE + 0x1204) #define GPIO_W130 (GPIO_PORT_BASE + 0x1208) #define GPIO_W131 (GPIO_PORT_BASE + 0x120C) #define GPIO_W132 (GPIO_PORT_BASE + 0x1210) #define GPIO_W133 (GPIO_PORT_BASE + 0x1214) #define GPIO_W134 (GPIO_PORT_BASE + 0x1218) #define GPIO_W135 (GPIO_PORT_BASE + 0x121C) #define GPIO_W136 (GPIO_PORT_BASE + 0x1220) #define GPIO_W137 (GPIO_PORT_BASE + 0x1224) #define GPIO_W138 (GPIO_PORT_BASE + 0x1228) #define GPIO_W139 (GPIO_PORT_BASE + 0x122C) #define GPIO_W140 (GPIO_PORT_BASE + 0x1230) #define GPIO_W141 (GPIO_PORT_BASE + 0x1234) #define GPIO_W142 (GPIO_PORT_BASE + 0x1238) #define GPIO_W143 (GPIO_PORT_BASE + 0x123C) #define GPIO_W144 (GPIO_PORT_BASE + 0x1240) #define GPIO_W145 (GPIO_PORT_BASE + 0x1244) #define GPIO_W146 (GPIO_PORT_BASE + 0x1248) #define GPIO_W147 (GPIO_PORT_BASE + 0x124C) #define GPIO_W148 (GPIO_PORT_BASE + 0x1250) #define GPIO_W149 (GPIO_PORT_BASE + 0x1254) #define GPIO_W150 (GPIO_PORT_BASE + 0x1258) #define GPIO_W151 (GPIO_PORT_BASE + 0x125C) #define GPIO_W152 (GPIO_PORT_BASE + 0x1260) #define GPIO_W153 (GPIO_PORT_BASE + 0x1264) #define GPIO_W154 (GPIO_PORT_BASE + 0x1268) #define GPIO_W155 (GPIO_PORT_BASE + 0x126C) #define GPIO_W156 (GPIO_PORT_BASE + 0x1270) #define GPIO_W157 (GPIO_PORT_BASE + 0x1274) #define GPIO_W158 (GPIO_PORT_BASE + 0x1278) #define GPIO_W159 (GPIO_PORT_BASE + 0x127C) /* Word pin registers port 5 (R/W) */ #define GPIO_W160 (GPIO_PORT_BASE + 0x1280) #define GPIO_W161 (GPIO_PORT_BASE + 0x1284) #define GPIO_W162 (GPIO_PORT_BASE + 0x1288) #define GPIO_W163 (GPIO_PORT_BASE + 0x128C) #define GPIO_W164 (GPIO_PORT_BASE + 0x1290) #define GPIO_W165 (GPIO_PORT_BASE + 0x1294) #define GPIO_W166 (GPIO_PORT_BASE + 0x1298) #define GPIO_W167 (GPIO_PORT_BASE + 0x129C) #define GPIO_W168 (GPIO_PORT_BASE + 0x12A0) #define GPIO_W169 (GPIO_PORT_BASE + 0x12A4) #define GPIO_W170 (GPIO_PORT_BASE + 0x12A8) #define GPIO_W171 (GPIO_PORT_BASE + 0x12AC) #define GPIO_W172 (GPIO_PORT_BASE + 0x12B0) #define GPIO_W173 (GPIO_PORT_BASE + 0x12B4) #define GPIO_W174 (GPIO_PORT_BASE + 0x12B8) #define GPIO_W175 (GPIO_PORT_BASE + 0x12BC) #define GPIO_W176 (GPIO_PORT_BASE + 0x12C0) #define GPIO_W177 (GPIO_PORT_BASE + 0x12C4) #define GPIO_W178 (GPIO_PORT_BASE + 0x12C8) #define GPIO_W179 (GPIO_PORT_BASE + 0x12CC) #define GPIO_W180 (GPIO_PORT_BASE + 0x12D0) #define GPIO_W181 (GPIO_PORT_BASE + 0x12D4) #define GPIO_W182 (GPIO_PORT_BASE + 0x12D8) #define GPIO_W183 (GPIO_PORT_BASE + 0x12DC) #define GPIO_W184 (GPIO_PORT_BASE + 0x12E0) #define GPIO_W185 (GPIO_PORT_BASE + 0x12E4) #define GPIO_W186 (GPIO_PORT_BASE + 0x12E8) #define GPIO_W187 (GPIO_PORT_BASE + 0x12EC) #define GPIO_W188 (GPIO_PORT_BASE + 0x12F0) #define GPIO_W189 (GPIO_PORT_BASE + 0x12F4) #define GPIO_W190 (GPIO_PORT_BASE + 0x12F8) #define GPIO_W191 (GPIO_PORT_BASE + 0x12FC) /* Word pin registers port 6 (R/W) */ #define GPIO_W192 (GPIO_PORT_BASE + 0x1300) #define GPIO_W193 (GPIO_PORT_BASE + 0x1304) #define GPIO_W194 (GPIO_PORT_BASE + 0x1308) #define GPIO_W195 (GPIO_PORT_BASE + 0x130C) #define GPIO_W196 (GPIO_PORT_BASE + 0x1310) #define GPIO_W197 (GPIO_PORT_BASE + 0x1314) #define GPIO_W198 (GPIO_PORT_BASE + 0x1318) #define GPIO_W199 (GPIO_PORT_BASE + 0x131C) #define GPIO_W200 (GPIO_PORT_BASE + 0x1320) #define GPIO_W201 (GPIO_PORT_BASE + 0x1324) #define GPIO_W202 (GPIO_PORT_BASE + 0x1328) #define GPIO_W203 (GPIO_PORT_BASE + 0x132C) #define GPIO_W204 (GPIO_PORT_BASE + 0x1330) #define GPIO_W205 (GPIO_PORT_BASE + 0x1334) #define GPIO_W206 (GPIO_PORT_BASE + 0x1338) #define GPIO_W207 (GPIO_PORT_BASE + 0x133C) #define GPIO_W208 (GPIO_PORT_BASE + 0x1340) #define GPIO_W209 (GPIO_PORT_BASE + 0x1344) #define GPIO_W210 (GPIO_PORT_BASE + 0x1348) #define GPIO_W211 (GPIO_PORT_BASE + 0x134C) #define GPIO_W212 (GPIO_PORT_BASE + 0x1350) #define GPIO_W213 (GPIO_PORT_BASE + 0x1354) #define GPIO_W214 (GPIO_PORT_BASE + 0x1358) #define GPIO_W215 (GPIO_PORT_BASE + 0x135C) #define GPIO_W216 (GPIO_PORT_BASE + 0x1360) #define GPIO_W217 (GPIO_PORT_BASE + 0x1364) #define GPIO_W218 (GPIO_PORT_BASE + 0x1368) #define GPIO_W219 (GPIO_PORT_BASE + 0x136C) #define GPIO_W220 (GPIO_PORT_BASE + 0x1370) #define GPIO_W221 (GPIO_PORT_BASE + 0x1374) #define GPIO_W222 (GPIO_PORT_BASE + 0x1378) #define GPIO_W223 (GPIO_PORT_BASE + 0x137C) /* Word pin registers port 7 (R/W) */ #define GPIO_W224 (GPIO_PORT_BASE + 0x1380) #define GPIO_W225 (GPIO_PORT_BASE + 0x1384) #define GPIO_W226 (GPIO_PORT_BASE + 0x1388) #define GPIO_W227 (GPIO_PORT_BASE + 0x138C) #define GPIO_W228 (GPIO_PORT_BASE + 0x1390) #define GPIO_W229 (GPIO_PORT_BASE + 0x1394) #define GPIO_W230 (GPIO_PORT_BASE + 0x1398) #define GPIO_W231 (GPIO_PORT_BASE + 0x139C) #define GPIO_W232 (GPIO_PORT_BASE + 0x13A0) #define GPIO_W233 (GPIO_PORT_BASE + 0x13A4) #define GPIO_W234 (GPIO_PORT_BASE + 0x13A8) #define GPIO_W235 (GPIO_PORT_BASE + 0x13AC) #define GPIO_W236 (GPIO_PORT_BASE + 0x13B0) #define GPIO_W237 (GPIO_PORT_BASE + 0x13B4) #define GPIO_W238 (GPIO_PORT_BASE + 0x13B8) #define GPIO_W239 (GPIO_PORT_BASE + 0x13BC) #define GPIO_W240 (GPIO_PORT_BASE + 0x13C0) #define GPIO_W241 (GPIO_PORT_BASE + 0x13C4) #define GPIO_W242 (GPIO_PORT_BASE + 0x13C8) #define GPIO_W243 (GPIO_PORT_BASE + 0x13CC) #define GPIO_W244 (GPIO_PORT_BASE + 0x13D0) #define GPIO_W245 (GPIO_PORT_BASE + 0x13D4) #define GPIO_W246 (GPIO_PORT_BASE + 0x13D8) #define GPIO_W247 (GPIO_PORT_BASE + 0x13DC) #define GPIO_W248 (GPIO_PORT_BASE + 0x13E0) #define GPIO_W249 (GPIO_PORT_BASE + 0x13E4) #define GPIO_W250 (GPIO_PORT_BASE + 0x13E8) #define GPIO_W251 (GPIO_PORT_BASE + 0x13EC) #define GPIO_W252 (GPIO_PORT_BASE + 0x13F0) #define GPIO_W253 (GPIO_PORT_BASE + 0x13F4) #define GPIO_W254 (GPIO_PORT_BASE + 0x13F8) #define GPIO_W255 (GPIO_PORT_BASE + 0x13FC) #define GPIO_W(port, pin) MMIO32(GPIO_PORT_BASE + 0x1000 + (port * 0x80) + (pin * 4)) /* GPIO data direction register (GPIOn_DIR) */ #define GPIO_DIR(port) MMIO32(port + 0x00) #define GPIO0_DIR GPIO_DIR(GPIO0) #define GPIO1_DIR GPIO_DIR(GPIO1) #define GPIO2_DIR GPIO_DIR(GPIO2) #define GPIO3_DIR GPIO_DIR(GPIO3) #define GPIO4_DIR GPIO_DIR(GPIO4) #define GPIO5_DIR GPIO_DIR(GPIO5) #define GPIO6_DIR GPIO_DIR(GPIO6) #define GPIO7_DIR GPIO_DIR(GPIO7) /* GPIO fast mask register (GPIOn_MASK) */ #define GPIO_MASK(port) MMIO32(port + 0x80) #define GPIO0_MASK GPIO_MASK(GPIO0) #define GPIO1_MASK GPIO_MASK(GPIO1) #define GPIO2_MASK GPIO_MASK(GPIO2) #define GPIO3_MASK GPIO_MASK(GPIO3) #define GPIO4_MASK GPIO_MASK(GPIO4) #define GPIO5_MASK GPIO_MASK(GPIO5) #define GPIO6_MASK GPIO_MASK(GPIO6) #define GPIO7_MASK GPIO_MASK(GPIO7) /* GPIO port pin value register (GPIOn_PIN) */ #define GPIO_PIN(port) MMIO32(port + 0x100) #define GPIO0_PIN GPIO_PIN(GPIO0) #define GPIO1_PIN GPIO_PIN(GPIO1) #define GPIO2_PIN GPIO_PIN(GPIO2) #define GPIO3_PIN GPIO_PIN(GPIO3) #define GPIO4_PIN GPIO_PIN(GPIO4) #define GPIO5_PIN GPIO_PIN(GPIO5) #define GPIO6_PIN GPIO_PIN(GPIO6) #define GPIO7_PIN GPIO_PIN(GPIO7) /* GPIO port masked pin value register (GPIOn_MPIN) */ #define GPIO_MPIN(port) MMIO32(port + 0x180) #define GPIO0_MPIN GPIO_MPIN(GPIO0) #define GPIO1_MPIN GPIO_MPIN(GPIO1) #define GPIO2_MPIN GPIO_MPIN(GPIO2) #define GPIO3_MPIN GPIO_MPIN(GPIO3) #define GPIO4_MPIN GPIO_MPIN(GPIO4) #define GPIO5_MPIN GPIO_MPIN(GPIO5) #define GPIO6_MPIN GPIO_MPIN(GPIO6) #define GPIO7_MPIN GPIO_MPIN(GPIO7) /* GPIO port output set register (GPIOn_SET) */ #define GPIO_SET(port) MMIO32(port + 0x200) #define GPIO0_SET GPIO_SET(GPIO0) #define GPIO1_SET GPIO_SET(GPIO1) #define GPIO2_SET GPIO_SET(GPIO2) #define GPIO3_SET GPIO_SET(GPIO3) #define GPIO4_SET GPIO_SET(GPIO4) #define GPIO5_SET GPIO_SET(GPIO5) #define GPIO6_SET GPIO_SET(GPIO6) #define GPIO7_SET GPIO_SET(GPIO7) /* GPIO port output clear register (GPIOn_CLR) */ #define GPIO_CLR(port) MMIO32(port + 0x280) #define GPIO0_CLR GPIO_CLR(GPIO0) #define GPIO1_CLR GPIO_CLR(GPIO1) #define GPIO2_CLR GPIO_CLR(GPIO2) #define GPIO3_CLR GPIO_CLR(GPIO3) #define GPIO4_CLR GPIO_CLR(GPIO4) #define GPIO5_CLR GPIO_CLR(GPIO5) #define GPIO6_CLR GPIO_CLR(GPIO6) #define GPIO7_CLR GPIO_CLR(GPIO7) /* GPIO port toggle register (GPIOn_NOT) */ #define GPIO_NOT(port) MMIO32(port + 0x300) #define GPIO0_NOT GPIO_NOT(GPIO0) #define GPIO1_NOT GPIO_NOT(GPIO1) #define GPIO2_NOT GPIO_NOT(GPIO2) #define GPIO3_NOT GPIO_NOT(GPIO3) #define GPIO4_NOT GPIO_NOT(GPIO4) #define GPIO5_NOT GPIO_NOT(GPIO5) #define GPIO6_NOT GPIO_NOT(GPIO6) #define GPIO7_NOT GPIO_NOT(GPIO7) /* TODO interrupts */ BEGIN_DECLS void gpio_set(uint32_t gpioport, uint32_t gpios); void gpio_clear(uint32_t gpioport, uint32_t gpios); void gpio_toggle(uint32_t gpioport, uint32_t gpios); uint32_t gpio_get(uint32_t gpioport, uint32_t gpios); END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/i2c.h000066400000000000000000000152111435536612600233020ustar00rootroot00000000000000/** @defgroup i2c_defines I2C Defines @brief Defined Constants and Types for the LPC43xx I2C @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @author @htmlonly © @endhtmlonly 2013 Benjamin Vernoux @author @htmlonly © @endhtmlonly 2014 Jared Boone @date 19 December 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2013 Benjamin Vernoux * Copyright (C) 2014 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_I2C_H #define LPC43XX_I2C_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* I2C port base addresses (for convenience) */ #define I2C0 I2C0_BASE #define I2C1 I2C1_BASE /* --- I2C registers ------------------------------------------------------- */ /* I2C Control Set Register */ #define I2C_CONSET(port) MMIO32(port + 0x000) #define I2C0_CONSET I2C_CONSET(I2C0) #define I2C1_CONSET I2C_CONSET(I2C1) /* I2C Status Register */ #define I2C_STAT(port) MMIO32(port + 0x004) #define I2C0_STAT I2C_STAT(I2C0) #define I2C1_STAT I2C_STAT(I2C1) /* I2C Data Register */ #define I2C_DAT(port) MMIO32(port + 0x008) #define I2C0_DAT I2C_DAT(I2C0) #define I2C1_DAT I2C_DAT(I2C1) /* I2C Slave Address Register 0 */ #define I2C_ADR0(port) MMIO32(port + 0x00C) #define I2C0_ADR0 I2C_ADR0(I2C0) #define I2C1_ADR0 I2C_ADR0(I2C1) /* SCH Duty Cycle Register High Half Word */ #define I2C_SCLH(port) MMIO32(port + 0x010) #define I2C0_SCLH I2C_SCLH(I2C0) #define I2C1_SCLH I2C_SCLH(I2C1) /* SCL Duty Cycle Register Low Half Word */ #define I2C_SCLL(port) MMIO32(port + 0x014) #define I2C0_SCLL I2C_SCLL(I2C0) #define I2C1_SCLL I2C_SCLL(I2C1) /* I2C Control Clear Register */ #define I2C_CONCLR(port) MMIO32(port + 0x018) #define I2C0_CONCLR I2C_CONCLR(I2C0) #define I2C1_CONCLR I2C_CONCLR(I2C1) /* Monitor mode control register */ #define I2C_MMCTRL(port) MMIO32(port + 0x01C) #define I2C0_MMCTRL I2C_MMCTRL(I2C0) #define I2C1_MMCTRL I2C_MMCTRL(I2C1) /* I2C Slave Address Register 1 */ #define I2C_ADR1(port) MMIO32(port + 0x020) #define I2C0_ADR1 I2C_ADR1(I2C0) #define I2C1_ADR1 I2C_ADR1(I2C1) /* I2C Slave Address Register 2 */ #define I2C_ADR2(port) MMIO32(port + 0x024) #define I2C0_ADR2 I2C_ADR2(I2C0) #define I2C1_ADR2 I2C_ADR2(I2C1) /* I2C Slave Address Register 3 */ #define I2C_ADR3(port) MMIO32(port + 0x028) #define I2C0_ADR3 I2C_ADR3(I2C0) #define I2C1_ADR3 I2C_ADR3(I2C1) /* Data buffer register */ #define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C) #define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0) #define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1) /* I2C Slave address mask register 0 */ #define I2C_MASK0(port) MMIO32(port + 0x030) #define I2C0_MASK0 I2C_MASK0(I2C0) #define I2C1_MASK0 I2C_MASK0(I2C1) /* I2C Slave address mask register 1 */ #define I2C_MASK1(port) MMIO32(port + 0x034) #define I2C0_MASK1 I2C_MASK1(I2C0) #define I2C1_MASK1 I2C_MASK1(I2C1) /* I2C Slave address mask register 2 */ #define I2C_MASK2(port) MMIO32(port + 0x038) #define I2C0_MASK2 I2C_MASK2(I2C0) #define I2C1_MASK2 I2C_MASK2(I2C1) /* I2C Slave address mask register 3 */ #define I2C_MASK3(port) MMIO32(port + 0x03C) #define I2C0_MASK3 I2C_MASK3(I2C0) #define I2C1_MASK3 I2C_MASK3(I2C1) /* --- I2Cx_CONCLR values -------------------------------------------------- */ #define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ #define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ #define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ #define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ /* --- I2Cx_CONSET values -------------------------------------------------- */ #define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ #define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ #define I2C_CONSET_STO (1 << 4) /* STOP flag */ #define I2C_CONSET_STA (1 << 5) /* START flag */ #define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ /* --- I2C const definitions ----------------------------------------------- */ #define I2C_WRITE 0 #define I2C_READ 1 /* --- I2C function prototypes --------------------------------------------- */ BEGIN_DECLS typedef uint32_t i2c_port_t; void i2c_init(i2c_port_t port, const uint16_t duty_cycle_count); void i2c_disable(i2c_port_t port); void i2c_tx_start(i2c_port_t port); void i2c_tx_byte(i2c_port_t port, uint8_t byte); uint8_t i2c_rx_byte(i2c_port_t port, bool ack); void i2c_stop(i2c_port_t port); void i2c0_init(const uint16_t duty_cycle_count); void i2c0_tx_start(void); void i2c0_tx_byte(uint8_t byte); uint8_t i2c0_rx_byte(bool ack); void i2c0_stop(void); void i2c1_init(const uint16_t duty_cycle_count); void i2c1_tx_start(void); void i2c1_tx_byte(uint8_t byte); uint8_t i2c1_rx_byte(bool ack); void i2c1_stop(void); END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/i2s.h000066400000000000000000000663301435536612600233320ustar00rootroot00000000000000/** @defgroup i2s_defines I2S Defines @brief Defined Constants and Types for the LPC43xx I2S @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_I2S_H #define LPC43XX_I2S_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* I2S port base addresses (for convenience) */ #define I2S0 I2S0_BASE #define I2S1 I2S1_BASE /* --- I2S registers ------------------------------------------------------- */ /* I2S Digital Audio Output Register */ #define I2S_DAO(port) MMIO32(port + 0x000) #define I2S0_DAO I2S_DAO(I2S0) #define I2S1_DAO I2S_DAO(I2S1) /* I2S Digital Audio Input Register */ #define I2S_DAI(port) MMIO32(port + 0x004) #define I2S0_DAI I2S_DAI(I2S0) #define I2S1_DAI I2S_DAI(I2S1) /* I2S Transmit FIFO */ #define I2S_TXFIFO(port) MMIO32(port + 0x008) #define I2S0_TXFIFO I2S_TXFIFO(I2S0) #define I2S1_TXFIFO I2S_TXFIFO(I2S1) /* I2S Receive FIFO */ #define I2S_RXFIFO(port) MMIO32(port + 0x00C) #define I2S0_RXFIFO I2S_RXFIFO(I2S0) #define I2S1_RXFIFO I2S_RXFIFO(I2S1) /* I2S Status Feedback Register */ #define I2S_STATE(port) MMIO32(port + 0x010) #define I2S0_STATE I2S_STATE(I2S0) #define I2S1_STATE I2S_STATE(I2S1) /* I2S DMA Configuration Register 1 */ #define I2S_DMA1(port) MMIO32(port + 0x014) #define I2S0_DMA1 I2S_DMA1(I2S0) #define I2S1_DMA1 I2S_DMA1(I2S1) /* I2S DMA Configuration Register 2 */ #define I2S_DMA2(port) MMIO32(port + 0x018) #define I2S0_DMA2 I2S_DMA2(I2S0) #define I2S1_DMA2 I2S_DMA2(I2S1) /* I2S Interrupt Request Control Register */ #define I2S_IRQ(port) MMIO32(port + 0x01C) #define I2S0_IRQ I2S_IRQ(I2S0) #define I2S1_IRQ I2S_IRQ(I2S1) /* I2S Transmit MCLK divider */ #define I2S_TXRATE(port) MMIO32(port + 0x020) #define I2S0_TXRATE I2S_TXRATE(I2S0) #define I2S1_TXRATE I2S_TXRATE(I2S1) /* I2S Receive MCLK divider */ #define I2S_RXRATE(port) MMIO32(port + 0x024) #define I2S0_RXRATE I2S_RXRATE(I2S0) #define I2S1_RXRATE I2S_RXRATE(I2S1) /* I2S Transmit bit rate divider */ #define I2S_TXBITRATE(port) MMIO32(port + 0x028) #define I2S0_TXBITRATE I2S_TXBITRATE(I2S0) #define I2S1_TXBITRATE I2S_TXBITRATE(I2S1) /* I2S Receive bit rate divider */ #define I2S_RXBITRATE(port) MMIO32(port + 0x02C) #define I2S0_RXBITRATE I2S_RXBITRATE(I2S0) #define I2S1_RXBITRATE I2S_RXBITRATE(I2S1) /* I2S Transmit mode control */ #define I2S_TXMODE(port) MMIO32(port + 0x030) #define I2S0_TXMODE I2S_TXMODE(I2S0) #define I2S1_TXMODE I2S_TXMODE(I2S1) /* I2S Receive mode control */ #define I2S_RXMODE(port) MMIO32(port + 0x034) #define I2S0_RXMODE I2S_RXMODE(I2S0) #define I2S1_RXMODE I2S_RXMODE(I2S1) /* --- I2S0_DAO values ------------------------------------------ */ /* WORDWIDTH: Selects the number of bytes in data */ #define I2S0_DAO_WORDWIDTH_SHIFT (0) #define I2S0_DAO_WORDWIDTH_MASK (0x3 << I2S0_DAO_WORDWIDTH_SHIFT) #define I2S0_DAO_WORDWIDTH(x) ((x) << I2S0_DAO_WORDWIDTH_SHIFT) /* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */ #define I2S0_DAO_MONO_SHIFT (2) #define I2S0_DAO_MONO_MASK (0x1 << I2S0_DAO_MONO_SHIFT) #define I2S0_DAO_MONO(x) ((x) << I2S0_DAO_MONO_SHIFT) /* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */ #define I2S0_DAO_STOP_SHIFT (3) #define I2S0_DAO_STOP_MASK (0x1 << I2S0_DAO_STOP_SHIFT) #define I2S0_DAO_STOP(x) ((x) << I2S0_DAO_STOP_SHIFT) /* RESET: When 1, asynchronously resets the transmit channel and FIFO */ #define I2S0_DAO_RESET_SHIFT (4) #define I2S0_DAO_RESET_MASK (0x1 << I2S0_DAO_RESET_SHIFT) #define I2S0_DAO_RESET(x) ((x) << I2S0_DAO_RESET_SHIFT) /* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */ #define I2S0_DAO_WS_SEL_SHIFT (5) #define I2S0_DAO_WS_SEL_MASK (0x1 << I2S0_DAO_WS_SEL_SHIFT) #define I2S0_DAO_WS_SEL(x) ((x) << I2S0_DAO_WS_SEL_SHIFT) /* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */ #define I2S0_DAO_WS_HALFPERIOD_SHIFT (6) #define I2S0_DAO_WS_HALFPERIOD_MASK (0x1ff << I2S0_DAO_WS_HALFPERIOD_SHIFT) #define I2S0_DAO_WS_HALFPERIOD(x) ((x) << I2S0_DAO_WS_HALFPERIOD_SHIFT) /* MUTE: When 1, the transmit channel sends only zeroes */ #define I2S0_DAO_MUTE_SHIFT (15) #define I2S0_DAO_MUTE_MASK (0x1 << I2S0_DAO_MUTE_SHIFT) #define I2S0_DAO_MUTE(x) ((x) << I2S0_DAO_MUTE_SHIFT) /* --- I2S1_DAO values ------------------------------------------ */ /* WORDWIDTH: Selects the number of bytes in data */ #define I2S1_DAO_WORDWIDTH_SHIFT (0) #define I2S1_DAO_WORDWIDTH_MASK (0x3 << I2S1_DAO_WORDWIDTH_SHIFT) #define I2S1_DAO_WORDWIDTH(x) ((x) << I2S1_DAO_WORDWIDTH_SHIFT) /* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */ #define I2S1_DAO_MONO_SHIFT (2) #define I2S1_DAO_MONO_MASK (0x1 << I2S1_DAO_MONO_SHIFT) #define I2S1_DAO_MONO(x) ((x) << I2S1_DAO_MONO_SHIFT) /* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */ #define I2S1_DAO_STOP_SHIFT (3) #define I2S1_DAO_STOP_MASK (0x1 << I2S1_DAO_STOP_SHIFT) #define I2S1_DAO_STOP(x) ((x) << I2S1_DAO_STOP_SHIFT) /* RESET: When 1, asynchronously resets the transmit channel and FIFO */ #define I2S1_DAO_RESET_SHIFT (4) #define I2S1_DAO_RESET_MASK (0x1 << I2S1_DAO_RESET_SHIFT) #define I2S1_DAO_RESET(x) ((x) << I2S1_DAO_RESET_SHIFT) /* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */ #define I2S1_DAO_WS_SEL_SHIFT (5) #define I2S1_DAO_WS_SEL_MASK (0x1 << I2S1_DAO_WS_SEL_SHIFT) #define I2S1_DAO_WS_SEL(x) ((x) << I2S1_DAO_WS_SEL_SHIFT) /* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */ #define I2S1_DAO_WS_HALFPERIOD_SHIFT (6) #define I2S1_DAO_WS_HALFPERIOD_MASK (0x1ff << I2S1_DAO_WS_HALFPERIOD_SHIFT) #define I2S1_DAO_WS_HALFPERIOD(x) ((x) << I2S1_DAO_WS_HALFPERIOD_SHIFT) /* MUTE: When 1, the transmit channel sends only zeroes */ #define I2S1_DAO_MUTE_SHIFT (15) #define I2S1_DAO_MUTE_MASK (0x1 << I2S1_DAO_MUTE_SHIFT) #define I2S1_DAO_MUTE(x) ((x) << I2S1_DAO_MUTE_SHIFT) /* --- I2S0_DAI values ------------------------------------------ */ /* WORDWIDTH: Selects the number of bytes in data */ #define I2S0_DAI_WORDWIDTH_SHIFT (0) #define I2S0_DAI_WORDWIDTH_MASK (0x3 << I2S0_DAI_WORDWIDTH_SHIFT) #define I2S0_DAI_WORDWIDTH(x) ((x) << I2S0_DAI_WORDWIDTH_SHIFT) /* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */ #define I2S0_DAI_MONO_SHIFT (2) #define I2S0_DAI_MONO_MASK (0x1 << I2S0_DAI_MONO_SHIFT) #define I2S0_DAI_MONO(x) ((x) << I2S0_DAI_MONO_SHIFT) /* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */ #define I2S0_DAI_STOP_SHIFT (3) #define I2S0_DAI_STOP_MASK (0x1 << I2S0_DAI_STOP_SHIFT) #define I2S0_DAI_STOP(x) ((x) << I2S0_DAI_STOP_SHIFT) /* RESET: When 1, asynchronously resets the transmit channel and FIFO */ #define I2S0_DAI_RESET_SHIFT (4) #define I2S0_DAI_RESET_MASK (0x1 << I2S0_DAI_RESET_SHIFT) #define I2S0_DAI_RESET(x) ((x) << I2S0_DAI_RESET_SHIFT) /* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */ #define I2S0_DAI_WS_SEL_SHIFT (5) #define I2S0_DAI_WS_SEL_MASK (0x1 << I2S0_DAI_WS_SEL_SHIFT) #define I2S0_DAI_WS_SEL(x) ((x) << I2S0_DAI_WS_SEL_SHIFT) /* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */ #define I2S0_DAI_WS_HALFPERIOD_SHIFT (6) #define I2S0_DAI_WS_HALFPERIOD_MASK (0x1ff << I2S0_DAI_WS_HALFPERIOD_SHIFT) #define I2S0_DAI_WS_HALFPERIOD(x) ((x) << I2S0_DAI_WS_HALFPERIOD_SHIFT) /* --- I2S1_DAI values ------------------------------------------ */ /* WORDWIDTH: Selects the number of bytes in data */ #define I2S1_DAI_WORDWIDTH_SHIFT (0) #define I2S1_DAI_WORDWIDTH_MASK (0x3 << I2S1_DAI_WORDWIDTH_SHIFT) #define I2S1_DAI_WORDWIDTH(x) ((x) << I2S1_DAI_WORDWIDTH_SHIFT) /* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */ #define I2S1_DAI_MONO_SHIFT (2) #define I2S1_DAI_MONO_MASK (0x1 << I2S1_DAI_MONO_SHIFT) #define I2S1_DAI_MONO(x) ((x) << I2S1_DAI_MONO_SHIFT) /* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */ #define I2S1_DAI_STOP_SHIFT (3) #define I2S1_DAI_STOP_MASK (0x1 << I2S1_DAI_STOP_SHIFT) #define I2S1_DAI_STOP(x) ((x) << I2S1_DAI_STOP_SHIFT) /* RESET: When 1, asynchronously resets the transmit channel and FIFO */ #define I2S1_DAI_RESET_SHIFT (4) #define I2S1_DAI_RESET_MASK (0x1 << I2S1_DAI_RESET_SHIFT) #define I2S1_DAI_RESET(x) ((x) << I2S1_DAI_RESET_SHIFT) /* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */ #define I2S1_DAI_WS_SEL_SHIFT (5) #define I2S1_DAI_WS_SEL_MASK (0x1 << I2S1_DAI_WS_SEL_SHIFT) #define I2S1_DAI_WS_SEL(x) ((x) << I2S1_DAI_WS_SEL_SHIFT) /* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */ #define I2S1_DAI_WS_HALFPERIOD_SHIFT (6) #define I2S1_DAI_WS_HALFPERIOD_MASK (0x1ff << I2S1_DAI_WS_HALFPERIOD_SHIFT) #define I2S1_DAI_WS_HALFPERIOD(x) ((x) << I2S1_DAI_WS_HALFPERIOD_SHIFT) /* --- I2S0_TXFIFO values --------------------------------------- */ /* I2STXFIFO: 8 x 32-bit transmit FIFO */ #define I2S0_TXFIFO_I2STXFIFO_SHIFT (0) #define I2S0_TXFIFO_I2STXFIFO_MASK (0xffffffff << I2S0_TXFIFO_I2STXFIFO_SHIFT) #define I2S0_TXFIFO_I2STXFIFO(x) ((x) << I2S0_TXFIFO_I2STXFIFO_SHIFT) /* --- I2S1_TXFIFO values --------------------------------------- */ /* I2STXFIFO: 8 x 32-bit transmit FIFO */ #define I2S1_TXFIFO_I2STXFIFO_SHIFT (0) #define I2S1_TXFIFO_I2STXFIFO_MASK (0xffffffff << I2S1_TXFIFO_I2STXFIFO_SHIFT) #define I2S1_TXFIFO_I2STXFIFO(x) ((x) << I2S1_TXFIFO_I2STXFIFO_SHIFT) /* --- I2S0_RXFIFO values --------------------------------------- */ /* I2SRXFIFO: 8 x 32-bit receive FIFO */ #define I2S0_RXFIFO_I2SRXFIFO_SHIFT (0) #define I2S0_RXFIFO_I2SRXFIFO_MASK (0xffffffff << I2S0_RXFIFO_I2SRXFIFO_SHIFT) #define I2S0_RXFIFO_I2SRXFIFO(x) ((x) << I2S0_RXFIFO_I2SRXFIFO_SHIFT) /* --- I2S1_RXFIFO values --------------------------------------- */ /* I2SRXFIFO: 8 x 32-bit receive FIFO */ #define I2S1_RXFIFO_I2SRXFIFO_SHIFT (0) #define I2S1_RXFIFO_I2SRXFIFO_MASK (0xffffffff << I2S1_RXFIFO_I2SRXFIFO_SHIFT) #define I2S1_RXFIFO_I2SRXFIFO(x) ((x) << I2S1_RXFIFO_I2SRXFIFO_SHIFT) /* --- I2S0_STATE values ---------------------------------------- */ /* IRQ: This bit reflects the presence of Receive Interrupt or Transmit Interrupt */ #define I2S0_STATE_IRQ_SHIFT (0) #define I2S0_STATE_IRQ_MASK (0x1 << I2S0_STATE_IRQ_SHIFT) #define I2S0_STATE_IRQ(x) ((x) << I2S0_STATE_IRQ_SHIFT) /* DMAREQ1: This bit reflects the presence of Receive or Transmit DMA Request 1 */ #define I2S0_STATE_DMAREQ1_SHIFT (1) #define I2S0_STATE_DMAREQ1_MASK (0x1 << I2S0_STATE_DMAREQ1_SHIFT) #define I2S0_STATE_DMAREQ1(x) ((x) << I2S0_STATE_DMAREQ1_SHIFT) /* DMAREQ2: This bit reflects the presence of Receive or Transmit DMA Request 2 */ #define I2S0_STATE_DMAREQ2_SHIFT (2) #define I2S0_STATE_DMAREQ2_MASK (0x1 << I2S0_STATE_DMAREQ2_SHIFT) #define I2S0_STATE_DMAREQ2(x) ((x) << I2S0_STATE_DMAREQ2_SHIFT) /* RX_LEVEL: Reflects the current level of the Receive FIFO */ #define I2S0_STATE_RX_LEVEL_SHIFT (8) #define I2S0_STATE_RX_LEVEL_MASK (0xf << I2S0_STATE_RX_LEVEL_SHIFT) #define I2S0_STATE_RX_LEVEL(x) ((x) << I2S0_STATE_RX_LEVEL_SHIFT) /* TX_LEVEL: Reflects the current level of the Transmit FIFO */ #define I2S0_STATE_TX_LEVEL_SHIFT (16) #define I2S0_STATE_TX_LEVEL_MASK (0xf << I2S0_STATE_TX_LEVEL_SHIFT) #define I2S0_STATE_TX_LEVEL(x) ((x) << I2S0_STATE_TX_LEVEL_SHIFT) /* --- I2S1_STATE values ---------------------------------------- */ /* IRQ: This bit reflects the presence of Receive Interrupt or Transmit Interrupt */ #define I2S1_STATE_IRQ_SHIFT (0) #define I2S1_STATE_IRQ_MASK (0x1 << I2S1_STATE_IRQ_SHIFT) #define I2S1_STATE_IRQ(x) ((x) << I2S1_STATE_IRQ_SHIFT) /* DMAREQ1: This bit reflects the presence of Receive or Transmit DMA Request 1 */ #define I2S1_STATE_DMAREQ1_SHIFT (1) #define I2S1_STATE_DMAREQ1_MASK (0x1 << I2S1_STATE_DMAREQ1_SHIFT) #define I2S1_STATE_DMAREQ1(x) ((x) << I2S1_STATE_DMAREQ1_SHIFT) /* DMAREQ2: This bit reflects the presence of Receive or Transmit DMA Request 2 */ #define I2S1_STATE_DMAREQ2_SHIFT (2) #define I2S1_STATE_DMAREQ2_MASK (0x1 << I2S1_STATE_DMAREQ2_SHIFT) #define I2S1_STATE_DMAREQ2(x) ((x) << I2S1_STATE_DMAREQ2_SHIFT) /* RX_LEVEL: Reflects the current level of the Receive FIFO */ #define I2S1_STATE_RX_LEVEL_SHIFT (8) #define I2S1_STATE_RX_LEVEL_MASK (0xf << I2S1_STATE_RX_LEVEL_SHIFT) #define I2S1_STATE_RX_LEVEL(x) ((x) << I2S1_STATE_RX_LEVEL_SHIFT) /* TX_LEVEL: Reflects the current level of the Transmit FIFO */ #define I2S1_STATE_TX_LEVEL_SHIFT (16) #define I2S1_STATE_TX_LEVEL_MASK (0xf << I2S1_STATE_TX_LEVEL_SHIFT) #define I2S1_STATE_TX_LEVEL(x) ((x) << I2S1_STATE_TX_LEVEL_SHIFT) /* --- I2S0_DMA1 values ----------------------------------------- */ /* RX_DMA1_ENABLE: When 1, enables DMA1 for I2S receive */ #define I2S0_DMA1_RX_DMA1_ENABLE_SHIFT (0) #define I2S0_DMA1_RX_DMA1_ENABLE_MASK (0x1 << I2S0_DMA1_RX_DMA1_ENABLE_SHIFT) #define I2S0_DMA1_RX_DMA1_ENABLE(x) ((x) << I2S0_DMA1_RX_DMA1_ENABLE_SHIFT) /* TX_DMA1_ENABLE: When 1, enables DMA1 for I2S transmit */ #define I2S0_DMA1_TX_DMA1_ENABLE_SHIFT (1) #define I2S0_DMA1_TX_DMA1_ENABLE_MASK (0x1 << I2S0_DMA1_TX_DMA1_ENABLE_SHIFT) #define I2S0_DMA1_TX_DMA1_ENABLE(x) ((x) << I2S0_DMA1_TX_DMA1_ENABLE_SHIFT) /* RX_DEPTH_DMA1: Set the FIFO level that triggers a receive DMA request on DMA1 */ #define I2S0_DMA1_RX_DEPTH_DMA1_SHIFT (8) #define I2S0_DMA1_RX_DEPTH_DMA1_MASK (0xf << I2S0_DMA1_RX_DEPTH_DMA1_SHIFT) #define I2S0_DMA1_RX_DEPTH_DMA1(x) ((x) << I2S0_DMA1_RX_DEPTH_DMA1_SHIFT) /* TX_DEPTH_DMA1: Set the FIFO level that triggers a transmit DMA request on DMA1 */ #define I2S0_DMA1_TX_DEPTH_DMA1_SHIFT (16) #define I2S0_DMA1_TX_DEPTH_DMA1_MASK (0xf << I2S0_DMA1_TX_DEPTH_DMA1_SHIFT) #define I2S0_DMA1_TX_DEPTH_DMA1(x) ((x) << I2S0_DMA1_TX_DEPTH_DMA1_SHIFT) /* --- I2S1_DMA1 values ----------------------------------------- */ /* RX_DMA1_ENABLE: When 1, enables DMA1 for I2S receive */ #define I2S1_DMA1_RX_DMA1_ENABLE_SHIFT (0) #define I2S1_DMA1_RX_DMA1_ENABLE_MASK (0x1 << I2S1_DMA1_RX_DMA1_ENABLE_SHIFT) #define I2S1_DMA1_RX_DMA1_ENABLE(x) ((x) << I2S1_DMA1_RX_DMA1_ENABLE_SHIFT) /* TX_DMA1_ENABLE: When 1, enables DMA1 for I2S transmit */ #define I2S1_DMA1_TX_DMA1_ENABLE_SHIFT (1) #define I2S1_DMA1_TX_DMA1_ENABLE_MASK (0x1 << I2S1_DMA1_TX_DMA1_ENABLE_SHIFT) #define I2S1_DMA1_TX_DMA1_ENABLE(x) ((x) << I2S1_DMA1_TX_DMA1_ENABLE_SHIFT) /* RX_DEPTH_DMA1: Set the FIFO level that triggers a receive DMA request on DMA1 */ #define I2S1_DMA1_RX_DEPTH_DMA1_SHIFT (8) #define I2S1_DMA1_RX_DEPTH_DMA1_MASK (0xf << I2S1_DMA1_RX_DEPTH_DMA1_SHIFT) #define I2S1_DMA1_RX_DEPTH_DMA1(x) ((x) << I2S1_DMA1_RX_DEPTH_DMA1_SHIFT) /* TX_DEPTH_DMA1: Set the FIFO level that triggers a transmit DMA request on DMA1 */ #define I2S1_DMA1_TX_DEPTH_DMA1_SHIFT (16) #define I2S1_DMA1_TX_DEPTH_DMA1_MASK (0xf << I2S1_DMA1_TX_DEPTH_DMA1_SHIFT) #define I2S1_DMA1_TX_DEPTH_DMA1(x) ((x) << I2S1_DMA1_TX_DEPTH_DMA1_SHIFT) /* --- I2S0_DMA2 values ----------------------------------------- */ /* RX_DMA2_ENABLE: When 1, enables DMA2 for I2S receive */ #define I2S0_DMA2_RX_DMA2_ENABLE_SHIFT (0) #define I2S0_DMA2_RX_DMA2_ENABLE_MASK (0x1 << I2S0_DMA2_RX_DMA2_ENABLE_SHIFT) #define I2S0_DMA2_RX_DMA2_ENABLE(x) ((x) << I2S0_DMA2_RX_DMA2_ENABLE_SHIFT) /* TX_DMA2_ENABLE: When 1, enables DMA2 for I2S transmit */ #define I2S0_DMA2_TX_DMA2_ENABLE_SHIFT (1) #define I2S0_DMA2_TX_DMA2_ENABLE_MASK (0x1 << I2S0_DMA2_TX_DMA2_ENABLE_SHIFT) #define I2S0_DMA2_TX_DMA2_ENABLE(x) ((x) << I2S0_DMA2_TX_DMA2_ENABLE_SHIFT) /* RX_DEPTH_DMA2: Set the FIFO level that triggers a receive DMA request on DMA2 */ #define I2S0_DMA2_RX_DEPTH_DMA2_SHIFT (8) #define I2S0_DMA2_RX_DEPTH_DMA2_MASK (0xf << I2S0_DMA2_RX_DEPTH_DMA2_SHIFT) #define I2S0_DMA2_RX_DEPTH_DMA2(x) ((x) << I2S0_DMA2_RX_DEPTH_DMA2_SHIFT) /* TX_DEPTH_DMA2: Set the FIFO level that triggers a transmit DMA request on DMA2 */ #define I2S0_DMA2_TX_DEPTH_DMA2_SHIFT (16) #define I2S0_DMA2_TX_DEPTH_DMA2_MASK (0xf << I2S0_DMA2_TX_DEPTH_DMA2_SHIFT) #define I2S0_DMA2_TX_DEPTH_DMA2(x) ((x) << I2S0_DMA2_TX_DEPTH_DMA2_SHIFT) /* --- I2S1_DMA2 values ----------------------------------------- */ /* RX_DMA2_ENABLE: When 1, enables DMA2 for I2S receive */ #define I2S1_DMA2_RX_DMA2_ENABLE_SHIFT (0) #define I2S1_DMA2_RX_DMA2_ENABLE_MASK (0x1 << I2S1_DMA2_RX_DMA2_ENABLE_SHIFT) #define I2S1_DMA2_RX_DMA2_ENABLE(x) ((x) << I2S1_DMA2_RX_DMA2_ENABLE_SHIFT) /* TX_DMA2_ENABLE: When 1, enables DMA2 for I2S transmit */ #define I2S1_DMA2_TX_DMA2_ENABLE_SHIFT (1) #define I2S1_DMA2_TX_DMA2_ENABLE_MASK (0x1 << I2S1_DMA2_TX_DMA2_ENABLE_SHIFT) #define I2S1_DMA2_TX_DMA2_ENABLE(x) ((x) << I2S1_DMA2_TX_DMA2_ENABLE_SHIFT) /* RX_DEPTH_DMA2: Set the FIFO level that triggers a receive DMA request on DMA2 */ #define I2S1_DMA2_RX_DEPTH_DMA2_SHIFT (8) #define I2S1_DMA2_RX_DEPTH_DMA2_MASK (0xf << I2S1_DMA2_RX_DEPTH_DMA2_SHIFT) #define I2S1_DMA2_RX_DEPTH_DMA2(x) ((x) << I2S1_DMA2_RX_DEPTH_DMA2_SHIFT) /* TX_DEPTH_DMA2: Set the FIFO level that triggers a transmit DMA request on DMA2 */ #define I2S1_DMA2_TX_DEPTH_DMA2_SHIFT (16) #define I2S1_DMA2_TX_DEPTH_DMA2_MASK (0xf << I2S1_DMA2_TX_DEPTH_DMA2_SHIFT) #define I2S1_DMA2_TX_DEPTH_DMA2(x) ((x) << I2S1_DMA2_TX_DEPTH_DMA2_SHIFT) /* --- I2S0_IRQ values ------------------------------------------ */ /* RX_IRQ_ENABLE: When 1, enables I2S receive interrupt */ #define I2S0_IRQ_RX_IRQ_ENABLE_SHIFT (0) #define I2S0_IRQ_RX_IRQ_ENABLE_MASK (0x1 << I2S0_IRQ_RX_IRQ_ENABLE_SHIFT) #define I2S0_IRQ_RX_IRQ_ENABLE(x) ((x) << I2S0_IRQ_RX_IRQ_ENABLE_SHIFT) /* TX_IRQ_ENABLE: When 1, enables I2S transmit interrupt */ #define I2S0_IRQ_TX_IRQ_ENABLE_SHIFT (1) #define I2S0_IRQ_TX_IRQ_ENABLE_MASK (0x1 << I2S0_IRQ_TX_IRQ_ENABLE_SHIFT) #define I2S0_IRQ_TX_IRQ_ENABLE(x) ((x) << I2S0_IRQ_TX_IRQ_ENABLE_SHIFT) /* RX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */ #define I2S0_IRQ_RX_DEPTH_IRQ_SHIFT (8) #define I2S0_IRQ_RX_DEPTH_IRQ_MASK (0xf << I2S0_IRQ_RX_DEPTH_IRQ_SHIFT) #define I2S0_IRQ_RX_DEPTH_IRQ(x) ((x) << I2S0_IRQ_RX_DEPTH_IRQ_SHIFT) /* TX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */ #define I2S0_IRQ_TX_DEPTH_IRQ_SHIFT (16) #define I2S0_IRQ_TX_DEPTH_IRQ_MASK (0xf << I2S0_IRQ_TX_DEPTH_IRQ_SHIFT) #define I2S0_IRQ_TX_DEPTH_IRQ(x) ((x) << I2S0_IRQ_TX_DEPTH_IRQ_SHIFT) /* --- I2S1_IRQ values ------------------------------------------ */ /* RX_IRQ_ENABLE: When 1, enables I2S receive interrupt */ #define I2S1_IRQ_RX_IRQ_ENABLE_SHIFT (0) #define I2S1_IRQ_RX_IRQ_ENABLE_MASK (0x1 << I2S1_IRQ_RX_IRQ_ENABLE_SHIFT) #define I2S1_IRQ_RX_IRQ_ENABLE(x) ((x) << I2S1_IRQ_RX_IRQ_ENABLE_SHIFT) /* TX_IRQ_ENABLE: When 1, enables I2S transmit interrupt */ #define I2S1_IRQ_TX_IRQ_ENABLE_SHIFT (1) #define I2S1_IRQ_TX_IRQ_ENABLE_MASK (0x1 << I2S1_IRQ_TX_IRQ_ENABLE_SHIFT) #define I2S1_IRQ_TX_IRQ_ENABLE(x) ((x) << I2S1_IRQ_TX_IRQ_ENABLE_SHIFT) /* RX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */ #define I2S1_IRQ_RX_DEPTH_IRQ_SHIFT (8) #define I2S1_IRQ_RX_DEPTH_IRQ_MASK (0xf << I2S1_IRQ_RX_DEPTH_IRQ_SHIFT) #define I2S1_IRQ_RX_DEPTH_IRQ(x) ((x) << I2S1_IRQ_RX_DEPTH_IRQ_SHIFT) /* TX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */ #define I2S1_IRQ_TX_DEPTH_IRQ_SHIFT (16) #define I2S1_IRQ_TX_DEPTH_IRQ_MASK (0xf << I2S1_IRQ_TX_DEPTH_IRQ_SHIFT) #define I2S1_IRQ_TX_DEPTH_IRQ(x) ((x) << I2S1_IRQ_TX_DEPTH_IRQ_SHIFT) /* --- I2S0_TXRATE values --------------------------------------- */ /* Y_DIVIDER: I2S transmit MCLK rate denominator */ #define I2S0_TXRATE_Y_DIVIDER_SHIFT (0) #define I2S0_TXRATE_Y_DIVIDER_MASK (0xff << I2S0_TXRATE_Y_DIVIDER_SHIFT) #define I2S0_TXRATE_Y_DIVIDER(x) ((x) << I2S0_TXRATE_Y_DIVIDER_SHIFT) /* X_DIVIDER: I2S transmit MCLK rate numerator */ #define I2S0_TXRATE_X_DIVIDER_SHIFT (8) #define I2S0_TXRATE_X_DIVIDER_MASK (0xff << I2S0_TXRATE_X_DIVIDER_SHIFT) #define I2S0_TXRATE_X_DIVIDER(x) ((x) << I2S0_TXRATE_X_DIVIDER_SHIFT) /* --- I2S1_TXRATE values --------------------------------------- */ /* Y_DIVIDER: I2S transmit MCLK rate denominator */ #define I2S1_TXRATE_Y_DIVIDER_SHIFT (0) #define I2S1_TXRATE_Y_DIVIDER_MASK (0xff << I2S1_TXRATE_Y_DIVIDER_SHIFT) #define I2S1_TXRATE_Y_DIVIDER(x) ((x) << I2S1_TXRATE_Y_DIVIDER_SHIFT) /* X_DIVIDER: I2S transmit MCLK rate numerator */ #define I2S1_TXRATE_X_DIVIDER_SHIFT (8) #define I2S1_TXRATE_X_DIVIDER_MASK (0xff << I2S1_TXRATE_X_DIVIDER_SHIFT) #define I2S1_TXRATE_X_DIVIDER(x) ((x) << I2S1_TXRATE_X_DIVIDER_SHIFT) /* --- I2S0_RXRATE values --------------------------------------- */ /* Y_DIVIDER: I2S receive MCLK rate denominator */ #define I2S0_RXRATE_Y_DIVIDER_SHIFT (0) #define I2S0_RXRATE_Y_DIVIDER_MASK (0xff << I2S0_RXRATE_Y_DIVIDER_SHIFT) #define I2S0_RXRATE_Y_DIVIDER(x) ((x) << I2S0_RXRATE_Y_DIVIDER_SHIFT) /* X_DIVIDER: I2S receive MCLK rate numerator */ #define I2S0_RXRATE_X_DIVIDER_SHIFT (8) #define I2S0_RXRATE_X_DIVIDER_MASK (0xff << I2S0_RXRATE_X_DIVIDER_SHIFT) #define I2S0_RXRATE_X_DIVIDER(x) ((x) << I2S0_RXRATE_X_DIVIDER_SHIFT) /* --- I2S1_RXRATE values --------------------------------------- */ /* Y_DIVIDER: I2S receive MCLK rate denominator */ #define I2S1_RXRATE_Y_DIVIDER_SHIFT (0) #define I2S1_RXRATE_Y_DIVIDER_MASK (0xff << I2S1_RXRATE_Y_DIVIDER_SHIFT) #define I2S1_RXRATE_Y_DIVIDER(x) ((x) << I2S1_RXRATE_Y_DIVIDER_SHIFT) /* X_DIVIDER: I2S receive MCLK rate numerator */ #define I2S1_RXRATE_X_DIVIDER_SHIFT (8) #define I2S1_RXRATE_X_DIVIDER_MASK (0xff << I2S1_RXRATE_X_DIVIDER_SHIFT) #define I2S1_RXRATE_X_DIVIDER(x) ((x) << I2S1_RXRATE_X_DIVIDER_SHIFT) /* --- I2S0_TXBITRATE values ------------------------------------ */ /* TX_BITRATE: I2S transmit bit rate */ #define I2S0_TXBITRATE_TX_BITRATE_SHIFT (0) #define I2S0_TXBITRATE_TX_BITRATE_MASK (0x3f << I2S0_TXBITRATE_TX_BITRATE_SHIFT) #define I2S0_TXBITRATE_TX_BITRATE(x) ((x) << I2S0_TXBITRATE_TX_BITRATE_SHIFT) /* --- I2S1_TXBITRATE values ------------------------------------ */ /* TX_BITRATE: I2S transmit bit rate */ #define I2S1_TXBITRATE_TX_BITRATE_SHIFT (0) #define I2S1_TXBITRATE_TX_BITRATE_MASK (0x3f << I2S1_TXBITRATE_TX_BITRATE_SHIFT) #define I2S1_TXBITRATE_TX_BITRATE(x) ((x) << I2S1_TXBITRATE_TX_BITRATE_SHIFT) /* --- I2S0_RXBITRATE values ------------------------------------ */ /* RX_BITRATE: I2S receive bit rate */ #define I2S0_RXBITRATE_RX_BITRATE_SHIFT (0) #define I2S0_RXBITRATE_RX_BITRATE_MASK (0x3f << I2S0_RXBITRATE_RX_BITRATE_SHIFT) #define I2S0_RXBITRATE_RX_BITRATE(x) ((x) << I2S0_RXBITRATE_RX_BITRATE_SHIFT) /* --- I2S1_RXBITRATE values ------------------------------------ */ /* RX_BITRATE: I2S receive bit rate */ #define I2S1_RXBITRATE_RX_BITRATE_SHIFT (0) #define I2S1_RXBITRATE_RX_BITRATE_MASK (0x3f << I2S1_RXBITRATE_RX_BITRATE_SHIFT) #define I2S1_RXBITRATE_RX_BITRATE(x) ((x) << I2S1_RXBITRATE_RX_BITRATE_SHIFT) /* --- I2S0_TXMODE values --------------------------------------- */ /* TXCLKSEL: Clock source selection for the transmit bit clock divider */ #define I2S0_TXMODE_TXCLKSEL_SHIFT (0) #define I2S0_TXMODE_TXCLKSEL_MASK (0x3 << I2S0_TXMODE_TXCLKSEL_SHIFT) #define I2S0_TXMODE_TXCLKSEL(x) ((x) << I2S0_TXMODE_TXCLKSEL_SHIFT) /* TX4PIN: Transmit 4-pin mode selection */ #define I2S0_TXMODE_TX4PIN_SHIFT (2) #define I2S0_TXMODE_TX4PIN_MASK (0x1 << I2S0_TXMODE_TX4PIN_SHIFT) #define I2S0_TXMODE_TX4PIN(x) ((x) << I2S0_TXMODE_TX4PIN_SHIFT) /* TXMCENA: Enable for the TX_MCLK output */ #define I2S0_TXMODE_TXMCENA_SHIFT (3) #define I2S0_TXMODE_TXMCENA_MASK (0x1 << I2S0_TXMODE_TXMCENA_SHIFT) #define I2S0_TXMODE_TXMCENA(x) ((x) << I2S0_TXMODE_TXMCENA_SHIFT) /* --- I2S1_TXMODE values --------------------------------------- */ /* TXCLKSEL: Clock source selection for the transmit bit clock divider */ #define I2S1_TXMODE_TXCLKSEL_SHIFT (0) #define I2S1_TXMODE_TXCLKSEL_MASK (0x3 << I2S1_TXMODE_TXCLKSEL_SHIFT) #define I2S1_TXMODE_TXCLKSEL(x) ((x) << I2S1_TXMODE_TXCLKSEL_SHIFT) /* TX4PIN: Transmit 4-pin mode selection */ #define I2S1_TXMODE_TX4PIN_SHIFT (2) #define I2S1_TXMODE_TX4PIN_MASK (0x1 << I2S1_TXMODE_TX4PIN_SHIFT) #define I2S1_TXMODE_TX4PIN(x) ((x) << I2S1_TXMODE_TX4PIN_SHIFT) /* TXMCENA: Enable for the TX_MCLK output */ #define I2S1_TXMODE_TXMCENA_SHIFT (3) #define I2S1_TXMODE_TXMCENA_MASK (0x1 << I2S1_TXMODE_TXMCENA_SHIFT) #define I2S1_TXMODE_TXMCENA(x) ((x) << I2S1_TXMODE_TXMCENA_SHIFT) /* --- I2S0_RXMODE values --------------------------------------- */ /* RXCLKSEL: Clock source selection for the receive bit clock divider */ #define I2S0_RXMODE_RXCLKSEL_SHIFT (0) #define I2S0_RXMODE_RXCLKSEL_MASK (0x3 << I2S0_RXMODE_RXCLKSEL_SHIFT) #define I2S0_RXMODE_RXCLKSEL(x) ((x) << I2S0_RXMODE_RXCLKSEL_SHIFT) /* RX4PIN: Receive 4-pin mode selection */ #define I2S0_RXMODE_RX4PIN_SHIFT (2) #define I2S0_RXMODE_RX4PIN_MASK (0x1 << I2S0_RXMODE_RX4PIN_SHIFT) #define I2S0_RXMODE_RX4PIN(x) ((x) << I2S0_RXMODE_RX4PIN_SHIFT) /* RXMCENA: Enable for the RX_MCLK output */ #define I2S0_RXMODE_RXMCENA_SHIFT (3) #define I2S0_RXMODE_RXMCENA_MASK (0x1 << I2S0_RXMODE_RXMCENA_SHIFT) #define I2S0_RXMODE_RXMCENA(x) ((x) << I2S0_RXMODE_RXMCENA_SHIFT) /* --- I2S1_RXMODE values --------------------------------------- */ /* RXCLKSEL: Clock source selection for the receive bit clock divider */ #define I2S1_RXMODE_RXCLKSEL_SHIFT (0) #define I2S1_RXMODE_RXCLKSEL_MASK (0x3 << I2S1_RXMODE_RXCLKSEL_SHIFT) #define I2S1_RXMODE_RXCLKSEL(x) ((x) << I2S1_RXMODE_RXCLKSEL_SHIFT) /* RX4PIN: Receive 4-pin mode selection */ #define I2S1_RXMODE_RX4PIN_SHIFT (2) #define I2S1_RXMODE_RX4PIN_MASK (0x1 << I2S1_RXMODE_RX4PIN_SHIFT) #define I2S1_RXMODE_RX4PIN(x) ((x) << I2S1_RXMODE_RX4PIN_SHIFT) /* RXMCENA: Enable for the RX_MCLK output */ #define I2S1_RXMODE_RXMCENA_SHIFT (3) #define I2S1_RXMODE_RXMCENA_MASK (0x1 << I2S1_RXMODE_RXMCENA_SHIFT) #define I2S1_RXMODE_RXMCENA(x) ((x) << I2S1_RXMODE_RXMCENA_SHIFT) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/ipc.h000066400000000000000000000020631435536612600234010ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_IPC_H #define LPC43XX_IPC_H #include #include #ifdef __cplusplus extern "C" { #endif void ipc_halt_m0(void); void ipc_start_m0(uint32_t cm0_baseaddr); void ipc_m0apptxevent_clear(void); #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/m0/000077500000000000000000000000001435536612600227705ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/m0/irq.yaml000066400000000000000000000010341435536612600244450ustar00rootroot00000000000000includeguard: LIBOPENCM3_LPC43xx_M0_NVIC_H partname_humanreadable: LPC 43xx series M0 core partname_doxygen: LPC43xx (M0) irqs: 0: rtc 1: m4core 2: dma # reserved: 3 4: flasheepromat 5: ethernet 6: sdio 7: lcd 8: usb0 9: usb1 10: sct 11: ritimer_or_wwdt 12: timer0 13: gint1 14: pin_int4 15: timer3 16: mcpwm 17: adc0 18: i2c0_or_irc1 19: sgpio 20: spi_or_dac 21: adc1 22: ssp0_or_ssp1 23: eventrouter 24: usart0 25: uart1 26: usart2_or_c_can1 27: usart3 28: i2s0_or_i2s1 29: c_can0hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/m4/000077500000000000000000000000001435536612600227745ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/m4/irq.yaml000066400000000000000000000021561435536612600244570ustar00rootroot00000000000000includeguard: LIBOPENCM3_LPC43xx_M4_NVIC_H partname_humanreadable: LPC 43xx series M4 core partname_doxygen: LPC43xx (M4) irqs: 0: dac 1: m0core 2: dma # reserved: 3, 4 5: ethernet 6: sdio 7: lcd 8: usb0 9: usb1 10: sct 11: ritimer 12: timer0 13: timer1 14: timer2 15: timer3 16: mcpwm 17: adc0 18: i2c0 19: i2c1 20: spi 21: adc1 22: ssp0 23: ssp1 24: usart0 25: uart1 26: usart2 27: usart3 28: i2s0 29: i2s1 30: spifi 31: sgpio 32: pin_int0 33: pin_int1 34: pin_int2 35: pin_int3 36: pin_int4 37: pin_int5 38: pin_int6 39: pin_int7 40: gint0 41: gint1 42: eventrouter 43: c_can1 # reserved: 44, 45 46: atimer 47: rtc # reserved: 48 49: wwdt # reserved: 50 51: c_can0 52: qei hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/memorymap.h000066400000000000000000000137511435536612600246420ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_MEMORYMAP_H #define LPC43XX_MEMORYMAP_H #include #ifdef __cplusplus extern "C" { #endif /* --- LPC43XX specific peripheral definitions ----------------------------- */ /* local SRAM / external static memory banks (0x1000 0000 - 0x2000 0000) */ #define SPIFI_DATA_BASE 0x14000000 /* Memory map for all busses */ #define PERIPH_BASE_AHB 0x40000000 #define PERIPH_BASE_APB0 0x40080000 #define PERIPH_BASE_APB1 0x400A0000 #define PERIPH_BASE_APB2 0x400C0000 #define PERIPH_BASE_APB3 0x400E0000 /* Register boundary addresses */ /* AHB (0x4000 0000 - 0x4001 2000) */ #define SCT_BASE (PERIPH_BASE_AHB + 0x00000) /* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */ #define GPDMA_BASE (PERIPH_BASE_AHB + 0x02000) #define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000) #define SDIO_BASE (PERIPH_BASE_AHB + 0x04000) #define EMC_BASE (PERIPH_BASE_AHB + 0x05000) #define USB0_BASE (PERIPH_BASE_AHB + 0x06000) #define USB1_BASE (PERIPH_BASE_AHB + 0x07000) #define LCD_BASE (PERIPH_BASE_AHB + 0x08000) /* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */ #define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) /* 0x4001 2000 - 0x4003 FFFF Reserved */ /* RTC domain peripherals */ #define ATIMER_BASE 0x40040000 #define BACKUP_REG_BASE 0x40041000 #define PMC_BASE 0x40042000 #define CREG_BASE 0x40043000 #define EVENTROUTER_BASE 0x40044000 #define OTP_BASE 0x40045000 #define RTC_BASE 0x40046000 /* 0x4004 7000 - 0x4004 FFFF Reserved */ /* clocking/reset control peripherals */ #define CGU_BASE 0x40050000 #define CCU1_BASE 0x40051000 #define CCU2_BASE 0x40052000 #define RGU_BASE 0x40053000 /* 0x4005 4000 - 0x4005 FFFF Reserved */ /* 0x4006 0000 - 0x4007 FFFF Reserved */ /* APB0 ( 0x4008 0000 - 0x4008 FFFF) */ #define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000) #define USART0_BASE (PERIPH_BASE_APB0 + 0x01000) #define UART1_BASE (PERIPH_BASE_APB0 + 0x02000) #define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000) #define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) #define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000) #define SCU_BASE (PERIPH_BASE_APB0 + 0x06000) #define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000) #define GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000) #define GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000) /* 0x4008 A000 - 0x4008 FFFF Reserved */ /* 0x4009 0000 - 0x4009 FFFF Reserved */ /* APB1 (0x400A 0000 - 0x400A FFFF) */ #define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000) #define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000) #define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000) #define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000) #define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000) /* 0x400A 5000 - 0x400A FFFF Reserved */ /* 0x400B 0000 - 0x400B FFFF Reserved */ /* APB2 (0x400C 0000 - 0x400C FFFF) */ #define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000) #define USART2_BASE (PERIPH_BASE_APB2 + 0x01000) #define USART3_BASE (PERIPH_BASE_APB2 + 0x02000) #define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000) #define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000) #define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000) #define QEI_BASE (PERIPH_BASE_APB2 + 0x06000) #define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000) /* 0x400C 8000 - 0x400C FFFF Reserved */ /* 0x400D 0000 - 0x400D FFFF Reserved */ /* APB3 (0x400E 0000 - 0x400E FFFF) */ #define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000) #define DAC_BASE (PERIPH_BASE_APB3 + 0x01000) #define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000) #define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000) #define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000) /* 0x400E 5000 - 0x400E FFFF Reserved */ /* 0x400F 0000 - 0x400F 0FFF Reserved */ #define AES_BASE 0x400F1000 /* 0x400F 2000 - 0x400F 3FFF Reserved */ #define GPIO_PORT_BASE 0x400F4000 /* 0x400F 8000 - 0x400F FFFF Reserved */ #define SPI_PORT_BASE 0x40100000 #define SGPIO_PORT_BASE 0x40101000 /* 0x4010 2000 - 0x41FF FFFF Reserved */ /* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */ /* 0x4400 0000 - 0x5FFF FFFF Reserved */ /* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */ #define SPIFI_DATA_UNCACHED_BASE 0x80000000 #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/rgu.h000066400000000000000000001375271435536612600234410ustar00rootroot00000000000000/** @defgroup rgu_defines Reset Generation Unit Defines @brief Defined Constants and Types for the LPC43xx Reset Generation Unit @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_RGU_H #define LPC43XX_RGU_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- RGU registers ------------------------------------------------------- */ /* Reset control register 0 */ #define RESET_CTRL0 MMIO32(RGU_BASE + 0x100) /* Reset control register 1 */ #define RESET_CTRL1 MMIO32(RGU_BASE + 0x104) /* Reset status register 0 */ #define RESET_STATUS0 MMIO32(RGU_BASE + 0x110) /* Reset status register 1 */ #define RESET_STATUS1 MMIO32(RGU_BASE + 0x114) /* Reset status register 2 */ #define RESET_STATUS2 MMIO32(RGU_BASE + 0x118) /* Reset status register 3 */ #define RESET_STATUS3 MMIO32(RGU_BASE + 0x11C) /* Reset active status register 0 */ #define RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150) /* Reset active status register 1 */ #define RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154) /* Reset external status register 0 for CORE_RST */ #define RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400) /* Reset external status register 1 for PERIPH_RST */ #define RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404) /* Reset external status register 2 for MASTER_RST */ #define RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408) /* Reserved */ #define RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C) /* Reset external status register 4 for WWDT_RST */ #define RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410) /* Reset external status register 5 for CREG_RST */ #define RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414) /* Reserved */ #define RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418) /* Reserved */ #define RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C) /* Reset external status register 8 for BUS_RST */ #define RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420) /* Reset external status register 9 for SCU_RST */ #define RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424) /* Reserved */ #define RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428) /* Reserved */ #define RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C) /* Reserved */ #define RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430) /* Reset external status register 13 for M4_RST */ #define RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434) /* Reserved */ #define RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438) /* Reserved */ #define RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C) /* Reset external status register 16 for LCD_RST */ #define RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440) /* Reset external status register 17 for USB0_RST */ #define RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444) /* Reset external status register 18 for USB1_RST */ #define RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448) /* Reset external status register 19 for DMA_RST */ #define RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C) /* Reset external status register 20 for SDIO_RST */ #define RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450) /* Reset external status register 21 for EMC_RST */ #define RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454) /* Reset external status register 22 for ETHERNET_RST */ #define RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458) /* Reserved */ #define RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C) /* Reserved */ #define RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460) /* Reserved */ #define RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464) /* Reserved */ #define RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468) /* Reserved */ #define RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C) /* Reset external status register 28 for GPIO_RST */ #define RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470) /* Reserved */ #define RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474) /* Reserved */ #define RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478) /* Reserved */ #define RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C) /* Reset external status register 32 for TIMER0_RST */ #define RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480) /* Reset external status register 33 for TIMER1_RST */ #define RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484) /* Reset external status register 34 for TIMER2_RST */ #define RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488) /* Reset external status register 35 for TIMER3_RST */ #define RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C) /* Reset external status register 36 for RITIMER_RST */ #define RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490) /* Reset external status register 37 for SCT_RST */ #define RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494) /* Reset external status register 38 for MOTOCONPWM_RST */ #define RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498) /* Reset external status register 39 for QEI_RST */ #define RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C) /* Reset external status register 40 for ADC0_RST */ #define RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0) /* Reset external status register 41 for ADC1_RST */ #define RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4) /* Reset external status register 42 for DAC_RST */ #define RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8) /* Reserved */ #define RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC) /* Reset external status register 44 for UART0_RST */ #define RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0) /* Reset external status register 45 for UART1_RST */ #define RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4) /* Reset external status register 46 for UART2_RST */ #define RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8) /* Reset external status register 47 for UART3_RST */ #define RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC) /* Reset external status register 48 for I2C0_RST */ #define RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0) /* Reset external status register 49 for I2C1_RST */ #define RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4) /* Reset external status register 50 for SSP0_RST */ #define RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8) /* Reset external status register 51 for SSP1_RST */ #define RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC) /* Reset external status register 52 for I2S_RST */ #define RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0) /* Reset external status register 53 for SPIFI_RST */ #define RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4) /* Reset external status register 54 for CAN1_RST */ #define RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8) /* Reset external status register 55 for CAN0_RST */ #define RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC) /* Reset external status register 56 for M0APP_RST */ #define RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0) /* Reset external status register 57 for SGPIO_RST */ #define RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4) /* Reset external status register 58 for SPI_RST */ #define RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8) /* Reserved */ #define RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC) /* Reserved */ #define RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0) /* Reserved */ #define RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4) /* Reserved */ #define RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8) /* Reserved */ #define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC) /* --- RESET_CTRL0 values --------------------------------------- */ /* CORE_RST: Writing a one activates the reset */ #define RESET_CTRL0_CORE_RST_SHIFT (0) #define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT) /* PERIPH_RST: Writing a one activates the reset */ #define RESET_CTRL0_PERIPH_RST_SHIFT (1) #define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT) /* MASTER_RST: Writing a one activates the reset */ #define RESET_CTRL0_MASTER_RST_SHIFT (2) #define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT) /* WWDT_RST: Writing a one to this bit has no effect */ #define RESET_CTRL0_WWDT_RST_SHIFT (4) #define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT) /* CREG_RST: Writing a one to this bit has no effect */ #define RESET_CTRL0_CREG_RST_SHIFT (5) #define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT) /* BUS_RST: Writing a one activates the reset */ #define RESET_CTRL0_BUS_RST_SHIFT (8) #define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT) /* SCU_RST: Writing a one activates the reset */ #define RESET_CTRL0_SCU_RST_SHIFT (9) #define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT) /* M4_RST: Writing a one activates the reset */ #define RESET_CTRL0_M4_RST_SHIFT (13) #define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT) /* LCD_RST: Writing a one activates the reset */ #define RESET_CTRL0_LCD_RST_SHIFT (16) #define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT) /* USB0_RST: Writing a one activates the reset */ #define RESET_CTRL0_USB0_RST_SHIFT (17) #define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT) /* USB1_RST: Writing a one activates the reset */ #define RESET_CTRL0_USB1_RST_SHIFT (18) #define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT) /* DMA_RST: Writing a one activates the reset */ #define RESET_CTRL0_DMA_RST_SHIFT (19) #define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT) /* SDIO_RST: Writing a one activates the reset */ #define RESET_CTRL0_SDIO_RST_SHIFT (20) #define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT) /* EMC_RST: Writing a one activates the reset */ #define RESET_CTRL0_EMC_RST_SHIFT (21) #define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT) /* ETHERNET_RST: Writing a one activates the reset */ #define RESET_CTRL0_ETHERNET_RST_SHIFT (22) #define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT) /* FLASHA_RST: Writing a one activates the reset */ #define RESET_CTRL0_FLASHA_RST_SHIFT (25) #define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT) /* EEPROM_RST: Writing a one activates the reset */ #define RESET_CTRL0_EEPROM_RST_SHIFT (27) #define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT) /* GPIO_RST: Writing a one activates the reset */ #define RESET_CTRL0_GPIO_RST_SHIFT (28) #define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT) /* FLASHB_RST: Writing a one activates the reset */ #define RESET_CTRL0_FLASHB_RST_SHIFT (29) #define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT) /* --- RESET_CTRL1 values --------------------------------------- */ /* TIMER0_RST: Writing a one activates the reset */ #define RESET_CTRL1_TIMER0_RST_SHIFT (0) #define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT) /* TIMER1_RST: Writing a one activates the reset */ #define RESET_CTRL1_TIMER1_RST_SHIFT (1) #define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT) /* TIMER2_RST: Writing a one activates the reset */ #define RESET_CTRL1_TIMER2_RST_SHIFT (2) #define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT) /* TIMER3_RST: Writing a one activates the reset */ #define RESET_CTRL1_TIMER3_RST_SHIFT (3) #define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT) /* RTIMER_RST: Writing a one activates the reset */ #define RESET_CTRL1_RTIMER_RST_SHIFT (4) #define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT) /* SCT_RST: Writing a one activates the reset */ #define RESET_CTRL1_SCT_RST_SHIFT (5) #define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT) /* MOTOCONPWM_RST: Writing a one activates the reset */ #define RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6) #define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT) /* QEI_RST: Writing a one activates the reset */ #define RESET_CTRL1_QEI_RST_SHIFT (7) #define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT) /* ADC0_RST: Writing a one activates the reset */ #define RESET_CTRL1_ADC0_RST_SHIFT (8) #define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT) /* ADC1_RST: Writing a one activates the reset */ #define RESET_CTRL1_ADC1_RST_SHIFT (9) #define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT) /* DAC_RST: Writing a one activates the reset */ #define RESET_CTRL1_DAC_RST_SHIFT (10) #define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT) /* UART0_RST: Writing a one activates the reset */ #define RESET_CTRL1_UART0_RST_SHIFT (12) #define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT) /* UART1_RST: Writing a one activates the reset */ #define RESET_CTRL1_UART1_RST_SHIFT (13) #define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT) /* UART2_RST: Writing a one activates the reset */ #define RESET_CTRL1_UART2_RST_SHIFT (14) #define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT) /* UART3_RST: Writing a one activates the reset */ #define RESET_CTRL1_UART3_RST_SHIFT (15) #define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT) /* I2C0_RST: Writing a one activates the reset */ #define RESET_CTRL1_I2C0_RST_SHIFT (16) #define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT) /* I2C1_RST: Writing a one activates the reset */ #define RESET_CTRL1_I2C1_RST_SHIFT (17) #define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT) /* SSP0_RST: Writing a one activates the reset */ #define RESET_CTRL1_SSP0_RST_SHIFT (18) #define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT) /* SSP1_RST: Writing a one activates the reset */ #define RESET_CTRL1_SSP1_RST_SHIFT (19) #define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT) /* I2S_RST: Writing a one activates the reset */ #define RESET_CTRL1_I2S_RST_SHIFT (20) #define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT) /* SPIFI_RST: Writing a one activates the reset */ #define RESET_CTRL1_SPIFI_RST_SHIFT (21) #define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT) /* CAN1_RST: Writing a one activates the reset */ #define RESET_CTRL1_CAN1_RST_SHIFT (22) #define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT) /* CAN0_RST: Writing a one activates the reset */ #define RESET_CTRL1_CAN0_RST_SHIFT (23) #define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT) /* M0APP_RST: Writing a one activates the reset */ #define RESET_CTRL1_M0APP_RST_SHIFT (24) #define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT) /* SGPIO_RST: Writing a one activates the reset */ #define RESET_CTRL1_SGPIO_RST_SHIFT (25) #define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT) /* SPI_RST: Writing a one activates the reset */ #define RESET_CTRL1_SPI_RST_SHIFT (26) #define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT) /* --- RESET_STATUS0 values ------------------------------------- */ /* CORE_RST: Status of the CORE_RST reset generator output */ #define RESET_STATUS0_CORE_RST_SHIFT (0) #define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT) #define RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT) /* PERIPH_RST: Status of the PERIPH_RST reset generator output */ #define RESET_STATUS0_PERIPH_RST_SHIFT (2) #define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT) #define RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT) /* MASTER_RST: Status of the MASTER_RST reset generator output */ #define RESET_STATUS0_MASTER_RST_SHIFT (4) #define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT) #define RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT) /* WWDT_RST: Status of the WWDT_RST reset generator output */ #define RESET_STATUS0_WWDT_RST_SHIFT (8) #define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT) #define RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT) /* CREG_RST: Status of the CREG_RST reset generator output */ #define RESET_STATUS0_CREG_RST_SHIFT (10) #define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT) #define RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT) /* BUS_RST: Status of the BUS_RST reset generator output */ #define RESET_STATUS0_BUS_RST_SHIFT (16) #define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT) #define RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT) /* SCU_RST: Status of the SCU_RST reset generator output */ #define RESET_STATUS0_SCU_RST_SHIFT (18) #define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT) #define RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT) /* M4_RST: Status of the M4_RST reset generator output */ #define RESET_STATUS0_M4_RST_SHIFT (26) #define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT) #define RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT) /* --- RESET_STATUS1 values ------------------------------------- */ /* LCD_RST: Status of the LCD_RST reset generator output */ #define RESET_STATUS1_LCD_RST_SHIFT (0) #define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT) #define RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT) /* USB0_RST: Status of the USB0_RST reset generator output */ #define RESET_STATUS1_USB0_RST_SHIFT (2) #define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT) #define RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT) /* USB1_RST: Status of the USB1_RST reset generator output */ #define RESET_STATUS1_USB1_RST_SHIFT (4) #define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT) #define RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT) /* DMA_RST: Status of the DMA_RST reset generator output */ #define RESET_STATUS1_DMA_RST_SHIFT (6) #define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT) #define RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT) /* SDIO_RST: Status of the SDIO_RST reset generator output */ #define RESET_STATUS1_SDIO_RST_SHIFT (8) #define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT) #define RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT) /* EMC_RST: Status of the EMC_RST reset generator output */ #define RESET_STATUS1_EMC_RST_SHIFT (10) #define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT) #define RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT) /* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */ #define RESET_STATUS1_ETHERNET_RST_SHIFT (12) #define RESET_STATUS1_ETHERNET_RST_MASK \ (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) #define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) /* FLASHA_RST: Status of the FLASHA_RST reset generator output */ #define RESET_STATUS1_FLASHA_RST_SHIFT (18) #define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT) #define RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT) /* EEPROM_RST: Status of the EEPROM_RST reset generator output */ #define RESET_STATUS1_EEPROM_RST_SHIFT (22) #define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT) #define RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT) /* GPIO_RST: Status of the GPIO_RST reset generator output */ #define RESET_STATUS1_GPIO_RST_SHIFT (24) #define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT) #define RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT) /* FLASHB_RST: Status of the FLASHB_RST reset generator output */ #define RESET_STATUS1_FLASHB_RST_SHIFT (26) #define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT) #define RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT) /* --- RESET_STATUS2 values ------------------------------------- */ /* TIMER0_RST: Status of the TIMER0_RST reset generator output */ #define RESET_STATUS2_TIMER0_RST_SHIFT (0) #define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT) #define RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT) /* TIMER1_RST: Status of the TIMER1_RST reset generator output */ #define RESET_STATUS2_TIMER1_RST_SHIFT (2) #define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT) #define RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT) /* TIMER2_RST: Status of the TIMER2_RST reset generator output */ #define RESET_STATUS2_TIMER2_RST_SHIFT (4) #define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT) #define RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT) /* TIMER3_RST: Status of the TIMER3_RST reset generator output */ #define RESET_STATUS2_TIMER3_RST_SHIFT (6) #define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT) #define RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT) /* RITIMER_RST: Status of the RITIMER_RST reset generator output */ #define RESET_STATUS2_RITIMER_RST_SHIFT (8) #define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT) #define RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT) /* SCT_RST: Status of the SCT_RST reset generator output */ #define RESET_STATUS2_SCT_RST_SHIFT (10) #define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT) #define RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT) /* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */ #define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12) #define RESET_STATUS2_MOTOCONPWM_RST_MASK \ (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) #define RESET_STATUS2_MOTOCONPWM_RST(x) \ ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) /* QEI_RST: Status of the QEI_RST reset generator output */ #define RESET_STATUS2_QEI_RST_SHIFT (14) #define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT) #define RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT) /* ADC0_RST: Status of the ADC0_RST reset generator output */ #define RESET_STATUS2_ADC0_RST_SHIFT (16) #define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT) #define RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT) /* ADC1_RST: Status of the ADC1_RST reset generator output */ #define RESET_STATUS2_ADC1_RST_SHIFT (18) #define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT) #define RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT) /* DAC_RST: Status of the DAC_RST reset generator output */ #define RESET_STATUS2_DAC_RST_SHIFT (20) #define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT) #define RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT) /* UART0_RST: Status of the UART0_RST reset generator output */ #define RESET_STATUS2_UART0_RST_SHIFT (24) #define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT) #define RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT) /* UART1_RST: Status of the UART1_RST reset generator output */ #define RESET_STATUS2_UART1_RST_SHIFT (26) #define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT) #define RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT) /* UART2_RST: Status of the UART2_RST reset generator output */ #define RESET_STATUS2_UART2_RST_SHIFT (28) #define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT) #define RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT) /* UART3_RST: Status of the UART3_RST reset generator output */ #define RESET_STATUS2_UART3_RST_SHIFT (30) #define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT) #define RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT) /* --- RESET_STATUS3 values ------------------------------------- */ /* I2C0_RST: Status of the I2C0_RST reset generator output */ #define RESET_STATUS3_I2C0_RST_SHIFT (0) #define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT) #define RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT) /* I2C1_RST: Status of the I2C1_RST reset generator output */ #define RESET_STATUS3_I2C1_RST_SHIFT (2) #define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT) #define RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT) /* SSP0_RST: Status of the SSP0_RST reset generator output */ #define RESET_STATUS3_SSP0_RST_SHIFT (4) #define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT) #define RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT) /* SSP1_RST: Status of the SSP1_RST reset generator output */ #define RESET_STATUS3_SSP1_RST_SHIFT (6) #define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT) #define RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT) /* I2S_RST: Status of the I2S_RST reset generator output */ #define RESET_STATUS3_I2S_RST_SHIFT (8) #define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT) #define RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT) /* SPIFI_RST: Status of the SPIFI_RST reset generator output */ #define RESET_STATUS3_SPIFI_RST_SHIFT (10) #define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT) #define RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT) /* CAN1_RST: Status of the CAN1_RST reset generator output */ #define RESET_STATUS3_CAN1_RST_SHIFT (12) #define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT) #define RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT) /* CAN0_RST: Status of the CAN0_RST reset generator output */ #define RESET_STATUS3_CAN0_RST_SHIFT (14) #define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT) #define RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT) /* M0APP_RST: Status of the M0APP_RST reset generator output */ #define RESET_STATUS3_M0APP_RST_SHIFT (16) #define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT) #define RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT) /* SGPIO_RST: Status of the SGPIO_RST reset generator output */ #define RESET_STATUS3_SGPIO_RST_SHIFT (18) #define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT) #define RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT) /* SPI_RST: Status of the SPI_RST reset generator output */ #define RESET_STATUS3_SPI_RST_SHIFT (20) #define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT) #define RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT) /* --- RESET_ACTIVE_STATUS0 values ------------------------------ */ /* CORE_RST: Current status of the CORE_RST */ #define RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0) #define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT) /* PERIPH_RST: Current status of the PERIPH_RST */ #define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1) #define RESET_ACTIVE_STATUS0_PERIPH_RST \ (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) /* MASTER_RST: Current status of the MASTER_RST */ #define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2) #define RESET_ACTIVE_STATUS0_MASTER_RST \ (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) /* WWDT_RST: Current status of the WWDT_RST */ #define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4) #define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT) /* CREG_RST: Current status of the CREG_RST */ #define RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5) #define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT) /* BUS_RST: Current status of the BUS_RST */ #define RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8) #define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT) /* SCU_RST: Current status of the SCU_RST */ #define RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9) #define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT) /* M4_RST: Current status of the M4_RST */ #define RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13) #define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT) /* LCD_RST: Current status of the LCD_RST */ #define RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16) #define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT) /* USB0_RST: Current status of the USB0_RST */ #define RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17) #define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT) /* USB1_RST: Current status of the USB1_RST */ #define RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18) #define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT) /* DMA_RST: Current status of the DMA_RST */ #define RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19) #define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT) /* SDIO_RST: Current status of the SDIO_RST */ #define RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20) #define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT) /* EMC_RST: Current status of the EMC_RST */ #define RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21) #define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT) /* ETHERNET_RST: Current status of the ETHERNET_RST */ #define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22) #define RESET_ACTIVE_STATUS0_ETHERNET_RST \ (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) /* FLASHA_RST: Current status of the FLASHA_RST */ #define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25) #define RESET_ACTIVE_STATUS0_FLASHA_RST \ (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) /* EEPROM_RST: Current status of the EEPROM_RST */ #define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27) #define RESET_ACTIVE_STATUS0_EEPROM_RST \ (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) /* GPIO_RST: Current status of the GPIO_RST */ #define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28) #define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT) /* FLASHB_RST: Current status of the FLASHB_RST */ #define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29) #define RESET_ACTIVE_STATUS0_FLASHB_RST \ (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) /* --- RESET_ACTIVE_STATUS1 values ------------------------------ */ /* TIMER0_RST: Current status of the TIMER0_RST */ #define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0) #define RESET_ACTIVE_STATUS1_TIMER0_RST \ (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) /* TIMER1_RST: Current status of the TIMER1_RST */ #define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1) #define RESET_ACTIVE_STATUS1_TIMER1_RST \ (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) /* TIMER2_RST: Current status of the TIMER2_RST */ #define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2) #define RESET_ACTIVE_STATUS1_TIMER2_RST \ (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) /* TIMER3_RST: Current status of the TIMER3_RST */ #define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3) #define RESET_ACTIVE_STATUS1_TIMER3_RST \ (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) /* RITIMER_RST: Current status of the RITIMER_RST */ #define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4) #define RESET_ACTIVE_STATUS1_RITIMER_RST \ (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) /* SCT_RST: Current status of the SCT_RST */ #define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5) #define RESET_ACTIVE_STATUS1_SCT_RST \ (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) /* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */ #define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6) #define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST \ (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) /* QEI_RST: Current status of the QEI_RST */ #define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7) #define RESET_ACTIVE_STATUS1_QEI_RST \ (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) /* ADC0_RST: Current status of the ADC0_RST */ #define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8) #define RESET_ACTIVE_STATUS1_ADC0_RST \ (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) /* ADC1_RST: Current status of the ADC1_RST */ #define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9) #define RESET_ACTIVE_STATUS1_ADC1_RST \ (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) /* DAC_RST: Current status of the DAC_RST */ #define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10) #define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT) /* UART0_RST: Current status of the UART0_RST */ #define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12) #define RESET_ACTIVE_STATUS1_UART0_RST \ (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) /* UART1_RST: Current status of the UART1_RST */ #define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13) #define RESET_ACTIVE_STATUS1_UART1_RST \ (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) /* UART2_RST: Current status of the UART2_RST */ #define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14) #define RESET_ACTIVE_STATUS1_UART2_RST \ (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) /* UART3_RST: Current status of the UART3_RST */ #define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15) #define RESET_ACTIVE_STATUS1_UART3_RST \ (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) /* I2C0_RST: Current status of the I2C0_RST */ #define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16) #define RESET_ACTIVE_STATUS1_I2C0_RST \ (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) /* I2C1_RST: Current status of the I2C1_RST */ #define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17) #define RESET_ACTIVE_STATUS1_I2C1_RST \ (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) /* SSP0_RST: Current status of the SSP0_RST */ #define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18) #define RESET_ACTIVE_STATUS1_SSP0_RST \ (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) /* SSP1_RST: Current status of the SSP1_RST */ #define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19) #define RESET_ACTIVE_STATUS1_SSP1_RST \ (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) /* I2S_RST: Current status of the I2S_RST */ #define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20) #define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT) /* SPIFI_RST: Current status of the SPIFI_RST */ #define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21) #define RESET_ACTIVE_STATUS1_SPIFI_RST \ (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) /* CAN1_RST: Current status of the CAN1_RST */ #define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22) #define RESET_ACTIVE_STATUS1_CAN1_RST \ (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) /* CAN0_RST: Current status of the CAN0_RST */ #define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23) #define RESET_ACTIVE_STATUS1_CAN0_RST \ (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) /* M0APP_RST: Current status of the M0APP_RST */ #define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24) #define RESET_ACTIVE_STATUS1_M0APP_RST \ (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) /* SGPIO_RST: Current status of the SGPIO_RST */ #define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25) #define RESET_ACTIVE_STATUS1_SGPIO_RST \ (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) /* SPI_RST: Current status of the SPI_RST */ #define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26) #define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT) /* --- RESET_EXT_STAT0 values ----------------------------------- */ /* EXT_RESET: Reset activated by external reset from reset pin */ #define RESET_EXT_STAT0_EXT_RESET_SHIFT (0) #define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT) /* BOD_RESET: Reset activated by BOD reset */ #define RESET_EXT_STAT0_BOD_RESET_SHIFT (4) #define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT) /* WWDT_RESET: Reset activated by WWDT time-out */ #define RESET_EXT_STAT0_WWDT_RESET_SHIFT (5) #define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT) /* --- RESET_EXT_STAT1 values ----------------------------------- */ /* CORE_RESET: Reset activated by CORE_RST output */ #define RESET_EXT_STAT1_CORE_RESET_SHIFT (1) #define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT) /* --- RESET_EXT_STAT2 values ----------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT2_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT4 values ----------------------------------- */ /* CORE_RESET: Reset activated by CORE_RST output */ #define RESET_EXT_STAT4_CORE_RESET_SHIFT (1) #define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT) /* --- RESET_EXT_STAT5 values ----------------------------------- */ /* CORE_RESET: Reset activated by CORE_RST output */ #define RESET_EXT_STAT5_CORE_RESET_SHIFT (1) #define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT) /* --- RESET_EXT_STAT8 values ----------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT8_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT9 values ----------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT9_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT13 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT13_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT16 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT16_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT17 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT17_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT18 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT18_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT19 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT19_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT20 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT20_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT21 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT21_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT22 values ---------------------------------- */ /* MASTER_RESET: Reset activated by MASTER_RST output */ #define RESET_EXT_STAT22_MASTER_RESET_SHIFT (3) #define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT) /* --- RESET_EXT_STAT25 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT25_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT27 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT27_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT28 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT28_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT29 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT29_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT32 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT32_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT33 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT33_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT34 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT34_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT35 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT35_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT36 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT36_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT37 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT37_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT38 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT38_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT39 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT39_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT40 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT40_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT41 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT41_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT42 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT42_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT44 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT44_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT45 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT45_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT46 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT46_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT47 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT47_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT48 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT48_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT49 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT49_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT50 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT50_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT51 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT51_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT52 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT52_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT53 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT53_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT54 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT54_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT55 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT55_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT56 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT56_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT57 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT57_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT58 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2) #define RESET_EXT_STAT58_PERIPHERAL_RESET \ (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/ritimer.h000066400000000000000000000072121435536612600243020ustar00rootroot00000000000000/** @defgroup ritimer_defines Repetitive Interrupt Timer Defines @brief Defined Constants and Types for the LPC43xx Repetitive Interrupt Timer @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @author @htmlonly © @endhtmlonly 2014 Jared Boone @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2014 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_RITIMER_H #define LPC43XX_RITIMER_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Repetitive Interrupt Timer registers -------------------------------- */ /* Compare register */ #define RITIMER_COMPVAL MMIO32(RITIMER_BASE + 0x000) /* Mask register */ #define RITIMER_MASK MMIO32(RITIMER_BASE + 0x004) /* Control register */ #define RITIMER_CTRL MMIO32(RITIMER_BASE + 0x008) /* 32-bit counter */ #define RITIMER_COUNTER MMIO32(RITIMER_BASE + 0x00C) /* --- RITIMER_COMPVAL values ----------------------------------- */ /* RICOMP: Compare register */ #define RITIMER_COMPVAL_RICOMP_SHIFT (0) #define RITIMER_COMPVAL_RICOMP_MASK (0xffffffff << RITIMER_COMPVAL_RICOMP_SHIFT) #define RITIMER_COMPVAL_RICOMP(x) ((x) << RITIMER_COMPVAL_RICOMP_SHIFT) /* --- RITIMER_MASK values -------------------------------------- */ /* RIMASK: Mask register */ #define RITIMER_MASK_RIMASK_SHIFT (0) #define RITIMER_MASK_RIMASK_MASK (0xffffffff << RITIMER_MASK_RIMASK_SHIFT) #define RITIMER_MASK_RIMASK(x) ((x) << RITIMER_MASK_RIMASK_SHIFT) /* --- RITIMER_CTRL values -------------------------------------- */ /* RITINT: Interrupt flag */ #define RITIMER_CTRL_RITINT_SHIFT (0) #define RITIMER_CTRL_RITINT_MASK (0x1 << RITIMER_CTRL_RITINT_SHIFT) #define RITIMER_CTRL_RITINT(x) ((x) << RITIMER_CTRL_RITINT_SHIFT) /* RITENCLR: Timer enable clear */ #define RITIMER_CTRL_RITENCLR_SHIFT (1) #define RITIMER_CTRL_RITENCLR_MASK (0x1 << RITIMER_CTRL_RITENCLR_SHIFT) #define RITIMER_CTRL_RITENCLR(x) ((x) << RITIMER_CTRL_RITENCLR_SHIFT) /* RITENBR: Timer enable for debug */ #define RITIMER_CTRL_RITENBR_SHIFT (2) #define RITIMER_CTRL_RITENBR_MASK (0x1 << RITIMER_CTRL_RITENBR_SHIFT) #define RITIMER_CTRL_RITENBR(x) ((x) << RITIMER_CTRL_RITENBR_SHIFT) /* RITEN: Timer enable */ #define RITIMER_CTRL_RITEN_SHIFT (3) #define RITIMER_CTRL_RITEN_MASK (0x1 << RITIMER_CTRL_RITEN_SHIFT) #define RITIMER_CTRL_RITEN(x) ((x) << RITIMER_CTRL_RITEN_SHIFT) /* --- RITIMER_COUNTER values ----------------------------------- */ /* RICOUNTER: 32-bit up counter */ #define RITIMER_COUNTER_RICOUNTER_SHIFT (0) #define RITIMER_COUNTER_RICOUNTER_MASK (0xffffffff << RITIMER_COUNTER_RICOUNTER_SHIFT) #define RITIMER_COUNTER_RICOUNTER(x) ((x) << RITIMER_COUNTER_RICOUNTER_SHIFT) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/rtc.h000066400000000000000000000321331435536612600234170ustar00rootroot00000000000000/** @defgroup rtc_defines RTC Defines @brief Defined Constants and Types for the LPC43xx Real Time Clock (RTC) @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2014 Jared Boone @date 2 January 2014 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2014 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_RTC_H #define LPC43XX_RTC_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* RTC port base address (for convenience) */ #define RTC RTC_BASE /* --- RTC registers ------------------------------------------------------- */ #define RTC_ILR MMIO32(RTC_BASE + 0x000) #define RTC_CCR MMIO32(RTC_BASE + 0x008) #define RTC_CIIR MMIO32(RTC_BASE + 0x00c) #define RTC_AMR MMIO32(RTC_BASE + 0x010) #define RTC_CTIME0 MMIO32(RTC_BASE + 0x014) #define RTC_CTIME1 MMIO32(RTC_BASE + 0x018) #define RTC_CTIME2 MMIO32(RTC_BASE + 0x01c) #define RTC_SEC MMIO32(RTC_BASE + 0x020) #define RTC_MIN MMIO32(RTC_BASE + 0x024) #define RTC_HRS MMIO32(RTC_BASE + 0x028) #define RTC_DOM MMIO32(RTC_BASE + 0x02c) #define RTC_DOW MMIO32(RTC_BASE + 0x030) #define RTC_DOY MMIO32(RTC_BASE + 0x034) #define RTC_MONTH MMIO32(RTC_BASE + 0x038) #define RTC_YEAR MMIO32(RTC_BASE + 0x03c) #define RTC_CALIBRATION MMIO32(RTC_BASE + 0x040) #define RTC_ASEC MMIO32(RTC_BASE + 0x060) #define RTC_AMIN MMIO32(RTC_BASE + 0x064) #define RTC_AHRS MMIO32(RTC_BASE + 0x068) #define RTC_ADOM MMIO32(RTC_BASE + 0x06c) #define RTC_ADOW MMIO32(RTC_BASE + 0x070) #define RTC_ADOY MMIO32(RTC_BASE + 0x074) #define RTC_AMON MMIO32(RTC_BASE + 0x078) #define RTC_AYRS MMIO32(RTC_BASE + 0x07c) /* --- RTC_ILR values ------------------------------------------- */ /* RTCCIF: Counter increment interrupt block interrupted */ #define RTC_ILR_RTCCIF_SHIFT (0) #define RTC_ILR_RTCCIF_MASK (0x1 << RTC_ILR_RTCCIF_SHIFT) #define RTC_ILR_RTCCIF(x) ((x) << RTC_ILR_RTCCIF_SHIFT) /* RTCALF: Alarm interrupted */ #define RTC_ILR_RTCALF_SHIFT (1) #define RTC_ILR_RTCALF_MASK (0x1 << RTC_ILR_RTCALF_SHIFT) #define RTC_ILR_RTCALF(x) ((x) << RTC_ILR_RTCALF_SHIFT) /* --- RTC_CCR values ------------------------------------------- */ /* CLKEN: Clock enable */ #define RTC_CCR_CLKEN_SHIFT (0) #define RTC_CCR_CLKEN_MASK (0x1 << RTC_CCR_CLKEN_SHIFT) #define RTC_CCR_CLKEN(x) ((x) << RTC_CCR_CLKEN_SHIFT) /* CTCRST: CTC reset */ #define RTC_CCR_CTCRST_SHIFT (1) #define RTC_CCR_CTCRST_MASK (0x1 << RTC_CCR_CTCRST_SHIFT) #define RTC_CCR_CTCRST(x) ((x) << RTC_CCR_CTCRST_SHIFT) /* CCALEN: Calibration counter enable */ #define RTC_CCR_CCALEN_SHIFT (4) #define RTC_CCR_CCALEN_MASK (0x1 << RTC_CCR_CCALEN_SHIFT) #define RTC_CCR_CCALEN(x) ((x) << RTC_CCR_CCALEN_SHIFT) /* --- RTC_CIIR values ------------------------------------------ */ /* IMSEC: Second interrupt enable */ #define RTC_CIIR_IMSEC_SHIFT (0) #define RTC_CIIR_IMSEC_MASK (0x1 << RTC_CIIR_IMSEC_SHIFT) #define RTC_CIIR_IMSEC(x) ((x) << RTC_CIIR_IMSEC_SHIFT) /* IMMIN: Minute interrupt enable */ #define RTC_CIIR_IMMIN_SHIFT (1) #define RTC_CIIR_IMMIN_MASK (0x1 << RTC_CIIR_IMMIN_SHIFT) #define RTC_CIIR_IMMIN(x) ((x) << RTC_CIIR_IMMIN_SHIFT) /* IMHOUR: Hour interrupt enable */ #define RTC_CIIR_IMHOUR_SHIFT (2) #define RTC_CIIR_IMHOUR_MASK (0x1 << RTC_CIIR_IMHOUR_SHIFT) #define RTC_CIIR_IMHOUR(x) ((x) << RTC_CIIR_IMHOUR_SHIFT) /* IMDOM: Day of month interrupt enable */ #define RTC_CIIR_IMDOM_SHIFT (3) #define RTC_CIIR_IMDOM_MASK (0x1 << RTC_CIIR_IMDOM_SHIFT) #define RTC_CIIR_IMDOM(x) ((x) << RTC_CIIR_IMDOM_SHIFT) /* IMDOW: Day of week interrupt enable */ #define RTC_CIIR_IMDOW_SHIFT (4) #define RTC_CIIR_IMDOW_MASK (0x1 << RTC_CIIR_IMDOW_SHIFT) #define RTC_CIIR_IMDOW(x) ((x) << RTC_CIIR_IMDOW_SHIFT) /* IMDOY: Day of year interrupt enable */ #define RTC_CIIR_IMDOY_SHIFT (5) #define RTC_CIIR_IMDOY_MASK (0x1 << RTC_CIIR_IMDOY_SHIFT) #define RTC_CIIR_IMDOY(x) ((x) << RTC_CIIR_IMDOY_SHIFT) /* IMMON: Month interrupt enable */ #define RTC_CIIR_IMMON_SHIFT (6) #define RTC_CIIR_IMMON_MASK (0x1 << RTC_CIIR_IMMON_SHIFT) #define RTC_CIIR_IMMON(x) ((x) << RTC_CIIR_IMMON_SHIFT) /* IMYEAR: Year interrupt enable */ #define RTC_CIIR_IMYEAR_SHIFT (7) #define RTC_CIIR_IMYEAR_MASK (0x1 << RTC_CIIR_IMYEAR_SHIFT) #define RTC_CIIR_IMYEAR(x) ((x) << RTC_CIIR_IMYEAR_SHIFT) /* --- RTC_AMR values ------------------------------------------- */ /* AMRSEC: Second not compared for alarm */ #define RTC_AMR_AMRSEC_SHIFT (0) #define RTC_AMR_AMRSEC_MASK (0x1 << RTC_AMR_AMRSEC_SHIFT) #define RTC_AMR_AMRSEC(x) ((x) << RTC_AMR_AMRSEC_SHIFT) /* AMRMIN: Minute not compared for alarm */ #define RTC_AMR_AMRMIN_SHIFT (1) #define RTC_AMR_AMRMIN_MASK (0x1 << RTC_AMR_AMRMIN_SHIFT) #define RTC_AMR_AMRMIN(x) ((x) << RTC_AMR_AMRMIN_SHIFT) /* AMRHOUR: Hour not compared for alarm */ #define RTC_AMR_AMRHOUR_SHIFT (2) #define RTC_AMR_AMRHOUR_MASK (0x1 << RTC_AMR_AMRHOUR_SHIFT) #define RTC_AMR_AMRHOUR(x) ((x) << RTC_AMR_AMRHOUR_SHIFT) /* AMRDOM: Day of month not compared for alarm */ #define RTC_AMR_AMRDOM_SHIFT (3) #define RTC_AMR_AMRDOM_MASK (0x1 << RTC_AMR_AMRDOM_SHIFT) #define RTC_AMR_AMRDOM(x) ((x) << RTC_AMR_AMRDOM_SHIFT) /* AMRDOW: Day of week not compared for alarm */ #define RTC_AMR_AMRDOW_SHIFT (4) #define RTC_AMR_AMRDOW_MASK (0x1 << RTC_AMR_AMRDOW_SHIFT) #define RTC_AMR_AMRDOW(x) ((x) << RTC_AMR_AMRDOW_SHIFT) /* AMRDOY: Day of year not compared for alarm */ #define RTC_AMR_AMRDOY_SHIFT (5) #define RTC_AMR_AMRDOY_MASK (0x1 << RTC_AMR_AMRDOY_SHIFT) #define RTC_AMR_AMRDOY(x) ((x) << RTC_AMR_AMRDOY_SHIFT) /* AMRMON: Month not compared for alarm */ #define RTC_AMR_AMRMON_SHIFT (6) #define RTC_AMR_AMRMON_MASK (0x1 << RTC_AMR_AMRMON_SHIFT) #define RTC_AMR_AMRMON(x) ((x) << RTC_AMR_AMRMON_SHIFT) /* AMRYEAR: Year not compared for alarm */ #define RTC_AMR_AMRYEAR_SHIFT (7) #define RTC_AMR_AMRYEAR_MASK (0x1 << RTC_AMR_AMRYEAR_SHIFT) #define RTC_AMR_AMRYEAR(x) ((x) << RTC_AMR_AMRYEAR_SHIFT) /* --- RTC_CTIME0 values ---------------------------------------- */ /* SECONDS: Seconds */ #define RTC_CTIME0_SECONDS_SHIFT (0) #define RTC_CTIME0_SECONDS_MASK (0x3f << RTC_CTIME0_SECONDS_SHIFT) #define RTC_CTIME0_SECONDS(x) ((x) << RTC_CTIME0_SECONDS_SHIFT) /* MINUTES: Minutes */ #define RTC_CTIME0_MINUTES_SHIFT (8) #define RTC_CTIME0_MINUTES_MASK (0x3f << RTC_CTIME0_MINUTES_SHIFT) #define RTC_CTIME0_MINUTES(x) ((x) << RTC_CTIME0_MINUTES_SHIFT) /* HOURS: Hours */ #define RTC_CTIME0_HOURS_SHIFT (16) #define RTC_CTIME0_HOURS_MASK (0x1f << RTC_CTIME0_HOURS_SHIFT) #define RTC_CTIME0_HOURS(x) ((x) << RTC_CTIME0_HOURS_SHIFT) /* DOW: Day of week */ #define RTC_CTIME0_DOW_SHIFT (24) #define RTC_CTIME0_DOW_MASK (0x7 << RTC_CTIME0_DOW_SHIFT) #define RTC_CTIME0_DOW(x) ((x) << RTC_CTIME0_DOW_SHIFT) /* --- RTC_CTIME1 values ---------------------------------------- */ /* DOM: Day of month */ #define RTC_CTIME1_DOM_SHIFT (0) #define RTC_CTIME1_DOM_MASK (0x1f << RTC_CTIME1_DOM_SHIFT) #define RTC_CTIME1_DOM(x) ((x) << RTC_CTIME1_DOM_SHIFT) /* MONTH: Month */ #define RTC_CTIME1_MONTH_SHIFT (8) #define RTC_CTIME1_MONTH_MASK (0xf << RTC_CTIME1_MONTH_SHIFT) #define RTC_CTIME1_MONTH(x) ((x) << RTC_CTIME1_MONTH_SHIFT) /* YEAR: Year */ #define RTC_CTIME1_YEAR_SHIFT (16) #define RTC_CTIME1_YEAR_MASK (0xfff << RTC_CTIME1_YEAR_SHIFT) #define RTC_CTIME1_YEAR(x) ((x) << RTC_CTIME1_YEAR_SHIFT) /* --- RTC_CTIME2 values ---------------------------------------- */ /* DOY: Day of year */ #define RTC_CTIME2_DOY_SHIFT (0) #define RTC_CTIME2_DOY_MASK (0xfff << RTC_CTIME2_DOY_SHIFT) #define RTC_CTIME2_DOY(x) ((x) << RTC_CTIME2_DOY_SHIFT) /* --- RTC_SEC values ------------------------------------------- */ /* SECONDS: Seconds */ #define RTC_SEC_SECONDS_SHIFT (0) #define RTC_SEC_SECONDS_MASK (0x3f << RTC_SEC_SECONDS_SHIFT) #define RTC_SEC_SECONDS(x) ((x) << RTC_SEC_SECONDS_SHIFT) /* --- RTC_MIN values ------------------------------------------- */ /* MINUTES: Minutes */ #define RTC_MIN_MINUTES_SHIFT (0) #define RTC_MIN_MINUTES_MASK (0x3f << RTC_MIN_MINUTES_SHIFT) #define RTC_MIN_MINUTES(x) ((x) << RTC_MIN_MINUTES_SHIFT) /* --- RTC_HRS values ------------------------------------------- */ /* HOURS: Hours */ #define RTC_HRS_HOURS_SHIFT (0) #define RTC_HRS_HOURS_MASK (0x1f << RTC_HRS_HOURS_SHIFT) #define RTC_HRS_HOURS(x) ((x) << RTC_HRS_HOURS_SHIFT) /* --- RTC_DOM values ------------------------------------------- */ /* DOM: Day of month */ #define RTC_DOM_DOM_SHIFT (0) #define RTC_DOM_DOM_MASK (0x1f << RTC_DOM_DOM_SHIFT) #define RTC_DOM_DOM(x) ((x) << RTC_DOM_DOM_SHIFT) /* --- RTC_DOW values ------------------------------------------- */ /* DOW: Day of week */ #define RTC_DOW_DOW_SHIFT (0) #define RTC_DOW_DOW_MASK (0x7 << RTC_DOW_DOW_SHIFT) #define RTC_DOW_DOW(x) ((x) << RTC_DOW_DOW_SHIFT) /* --- RTC_DOY values ------------------------------------------- */ /* DOY: Day of year */ #define RTC_DOY_DOY_SHIFT (0) #define RTC_DOY_DOY_MASK (0x1ff << RTC_DOY_DOY_SHIFT) #define RTC_DOY_DOY(x) ((x) << RTC_DOY_DOY_SHIFT) /* --- RTC_MONTH values ----------------------------------------- */ /* MONTH: Month */ #define RTC_MONTH_MONTH_SHIFT (0) #define RTC_MONTH_MONTH_MASK (0xf << RTC_MONTH_MONTH_SHIFT) #define RTC_MONTH_MONTH(x) ((x) << RTC_MONTH_MONTH_SHIFT) /* --- RTC_YEAR values ------------------------------------------ */ /* YEAR: Year */ #define RTC_YEAR_YEAR_SHIFT (0) #define RTC_YEAR_YEAR_MASK (0xfff << RTC_YEAR_YEAR_SHIFT) #define RTC_YEAR_YEAR(x) ((x) << RTC_YEAR_YEAR_SHIFT) /* --- RTC_CALIBRATION values ----------------------------------- */ /* CALVAL: Calibration counter max */ #define RTC_CALIBRATION_CALVAL_SHIFT (0) #define RTC_CALIBRATION_CALVAL_MASK (0x1ffff << RTC_CALIBRATION_CALVAL_SHIFT) #define RTC_CALIBRATION_CALVAL(x) ((x) << RTC_CALIBRATION_CALVAL_SHIFT) /* CALDIR: Calibration counter direction */ #define RTC_CALIBRATION_CALDIR_SHIFT (17) #define RTC_CALIBRATION_CALDIR_MASK (0x1 << RTC_CALIBRATION_CALDIR_SHIFT) #define RTC_CALIBRATION_CALDIR(x) ((x) << RTC_CALIBRATION_CALDIR_SHIFT) /* --- RTC_ASEC values ------------------------------------------ */ /* SECONDS: Alarm seconds */ #define RTC_ASEC_SECONDS_SHIFT (0) #define RTC_ASEC_SECONDS_MASK (0x3f << RTC_ASEC_SECONDS_SHIFT) #define RTC_ASEC_SECONDS(x) ((x) << RTC_ASEC_SECONDS_SHIFT) /* --- RTC_AMIN values ------------------------------------------ */ /* MINUTES: Alarm minutes */ #define RTC_AMIN_MINUTES_SHIFT (0) #define RTC_AMIN_MINUTES_MASK (0x3f << RTC_AMIN_MINUTES_SHIFT) #define RTC_AMIN_MINUTES(x) ((x) << RTC_AMIN_MINUTES_SHIFT) /* --- RTC_AHRS values ------------------------------------------ */ /* HOURS: Alarm hours */ #define RTC_AHRS_HOURS_SHIFT (0) #define RTC_AHRS_HOURS_MASK (0x1f << RTC_AHRS_HOURS_SHIFT) #define RTC_AHRS_HOURS(x) ((x) << RTC_AHRS_HOURS_SHIFT) /* --- RTC_ADOM values ------------------------------------------ */ /* DOM: Alarm day of month */ #define RTC_ADOM_DOM_SHIFT (0) #define RTC_ADOM_DOM_MASK (0x1f << RTC_ADOM_DOM_SHIFT) #define RTC_ADOM_DOM(x) ((x) << RTC_ADOM_DOM_SHIFT) /* --- RTC_ADOW values ------------------------------------------ */ /* DOW: Alarm day of week */ #define RTC_ADOW_DOW_SHIFT (0) #define RTC_ADOW_DOW_MASK (0x7 << RTC_ADOW_DOW_SHIFT) #define RTC_ADOW_DOW(x) ((x) << RTC_ADOW_DOW_SHIFT) /* --- RTC_ADOY values ------------------------------------------ */ /* DOY: Alarm day of year */ #define RTC_ADOY_DOY_SHIFT (0) #define RTC_ADOY_DOY_MASK (0x1ff << RTC_ADOY_DOY_SHIFT) #define RTC_ADOY_DOY(x) ((x) << RTC_ADOY_DOY_SHIFT) /* --- RTC_AMON values ------------------------------------------ */ /* MONTH: Alarm month */ #define RTC_AMON_MONTH_SHIFT (0) #define RTC_AMON_MONTH_MASK (0xf << RTC_AMON_MONTH_SHIFT) #define RTC_AMON_MONTH(x) ((x) << RTC_AMON_MONTH_SHIFT) /* --- RTC_AYRS values ------------------------------------------ */ /* YEAR: Alarm year */ #define RTC_AYRS_YEAR_SHIFT (0) #define RTC_AYRS_YEAR_MASK (0xfff << RTC_AYRS_YEAR_SHIFT) #define RTC_AYRS_YEAR(x) ((x) << RTC_AYRS_YEAR_SHIFT) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/scu.h000066400000000000000000000674671435536612600234430ustar00rootroot00000000000000/** @defgroup scu_defines System Control Unit Defines @brief Defined Constants and Types for the LPC43xx System Control Unit @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_SCU_H #define LPC43XX_SCU_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* Pin group base addresses */ #define PIN_GROUP0 (SCU_BASE + 0x000) #define PIN_GROUP1 (SCU_BASE + 0x080) #define PIN_GROUP2 (SCU_BASE + 0x100) #define PIN_GROUP3 (SCU_BASE + 0x180) #define PIN_GROUP4 (SCU_BASE + 0x200) #define PIN_GROUP5 (SCU_BASE + 0x280) #define PIN_GROUP6 (SCU_BASE + 0x300) #define PIN_GROUP7 (SCU_BASE + 0x380) #define PIN_GROUP8 (SCU_BASE + 0x400) #define PIN_GROUP9 (SCU_BASE + 0x480) #define PIN_GROUPA (SCU_BASE + 0x500) #define PIN_GROUPB (SCU_BASE + 0x580) #define PIN_GROUPC (SCU_BASE + 0x600) #define PIN_GROUPD (SCU_BASE + 0x680) #define PIN_GROUPE (SCU_BASE + 0x700) #define PIN_GROUPF (SCU_BASE + 0x780) #define PIN0 0x000 #define PIN1 0x004 #define PIN2 0x008 #define PIN3 0x00C #define PIN4 0x010 #define PIN5 0x014 #define PIN6 0x018 #define PIN7 0x01C #define PIN8 0x020 #define PIN9 0x024 #define PIN10 0x028 #define PIN11 0x02C #define PIN12 0x030 #define PIN13 0x034 #define PIN14 0x038 #define PIN15 0x03C #define PIN16 0x040 #define PIN17 0x044 #define PIN18 0x048 #define PIN19 0x04C #define PIN20 0x050 /* --- SCU registers ------------------------------------------------------- */ /* Pin configuration registers */ #define SCU_SFS(group, pin) MMIO32(group + pin) /* Pins P0_n */ #define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) #define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) /* Pins P1_n */ #define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) #define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) #define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) #define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) #define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) #define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) #define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) #define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) #define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) #define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) #define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) #define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) #define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) #define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) #define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) #define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) #define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) #define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) #define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) #define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) #define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) /* Pins P2_n */ #define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) #define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) #define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) #define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) #define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) #define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) #define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) #define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) #define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) #define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) #define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) #define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) #define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) #define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) /* Pins P3_n */ #define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) #define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) #define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) #define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) #define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) #define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) #define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) #define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) #define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) /* Pins P4_n */ #define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) #define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) #define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) #define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) #define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) #define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) #define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) #define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) #define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) #define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) #define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) /* Pins P5_n */ #define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) #define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) #define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) #define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) #define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) #define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) #define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) #define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) /* Pins P6_n */ #define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) #define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) #define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) #define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) #define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) #define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) #define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) #define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) #define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) #define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) #define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) #define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) #define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) /* Pins P7_n */ #define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) #define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) #define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) #define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) #define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) #define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) #define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) #define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) /* Pins P8_n */ #define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) #define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) #define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) #define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) #define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) #define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) #define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) #define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) #define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) /* Pins P9_n */ #define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) #define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) #define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) #define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) #define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) #define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) #define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) /* Pins PA_n */ #define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) #define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) #define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) #define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) #define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) /* Pins PB_n */ #define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) #define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) #define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) #define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) #define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) #define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) #define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) /* Pins PC_n */ #define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) #define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) #define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) #define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) #define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) #define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) #define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) #define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) #define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) #define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) #define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) #define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) #define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) #define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) #define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) /* Pins PD_n */ #define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) #define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) #define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) #define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) #define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) #define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) #define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) #define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) #define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) #define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) #define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) #define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) #define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) #define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) #define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) #define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) #define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) /* Pins PE_n */ #define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) #define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) #define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) #define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) #define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) #define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) #define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) #define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) #define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) #define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) #define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) #define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) #define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) #define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) #define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) #define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) /* Pins PF_n */ #define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) #define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) #define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) #define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) #define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) #define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) #define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) #define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) #define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) #define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) #define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) #define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) /* CLKn pins */ #define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) #define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) #define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) #define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) /* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ #define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) #define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) /* ADC pin select registers */ /* ADC0 function select register */ #define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) /* ADC1 function select register */ #define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) /* Analog function select register */ #define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) /* EMC clock delay register */ #define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) /* Pin interrupt select registers */ /* Pin interrupt select register for pin interrupts 0 to 3 */ #define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) /* Pin interrupt select register for pin interrupts 4 to 7 */ #define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) /**************************/ /* SCU I2C0 Configuration */ /**************************/ /* * Select input glitch filter time constant for the SCL pin. * 0 = 50 ns glitch filter. * 1 = 3ns glitch filter. */ #define SCU_SCL_EFP (BIT0) /* BIT1 Reserved. Always write a 0 to this bit. */ /* * Select I2C mode for the SCL pin. * 0 = Standard/Fast mode transmit. * 1 = Fast-mode Plus transmit. */ #define SCU_SCL_EHD (BIT2) /* * Enable the input receiver for the SCL pin. * Always write a 1 to this bit when using the * I2C0. * 0 = Disabled. * 1 = Enabled. */ #define SCU_SCL_EZI_EN (BIT3) /* BIT4-6 Reserved. */ /* * Enable or disable input glitch filter for the * SCL pin. The filter time constant is * determined by bit EFP. * 0 = Enable input filter. * 1 = Disable input filter. */ #define SCU_SCL_ZIF_DIS (BIT7) /* * Select input glitch filter time constant for the SDA pin. * 0 = 50 ns glitch filter. * 1 = 3ns glitch filter. */ #define SCU_SDA_EFP (BIT8) /* BIT9 Reserved. Always write a 0 to this bit. */ /* * Select I2C mode for the SDA pin. * 0 = Standard/Fast mode transmit. * 1 = Fast-mode Plus transmit. */ #define SCU_SDA_EHD (BIT10) /* * Enable the input receiver for the SDA pin. * Always write a 1 to this bit when using the * I2C0. * 0 = Disabled. * 1 = Enabled. */ #define SCU_SDA_EZI_EN (BIT11) /* BIT 12-14 - Reserved */ /* * Enable or disable input glitch filter for the * SDA pin. The filter time constant is * determined by bit SDA_EFP. * 0 = Enable input filter. * 1 = Disable input filter. */ #define SCU_SDA_ZIF_DIS (BIT15) /* Standard mode for I2C SCL/SDA Standard/Fast mode */ #define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) /* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ #define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \ SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \ SCU_SDA_EZI_EN) /* * SCU PIN Normal Drive: * The configuration registers for normal-drive pins control the following pins: * - P0_0 and P0_1 * - P1_0 to P1_16 and P1_18 to P1_20 * - P2_0 to P2_2 and P2_6 to P2_13 * - P3_0 to P3_2 and P3_4 to P3_8 * - P4_0 to P4_10 * - P5_0 to P5_7 * - P6_0 to P6_12 * - P7_0 to P7_7 * - P8_3 to P8_8 * - P9_0 to P9_6 * - PA_0 and PA_4 * - PB_0 to PB_6 * - PC_0 to PC_14 * - PE_0 to PE_15 * - PF_0 to PF_11 * * Pin configuration registers for High-Drive pins. * The configuration registers for high-drive pins control the following pins: * - P1_17 * - P2_3 to P2_5 * - P8_0 to P8_2 * - PA_1 to PA_3 * * Pin configuration registers for High-Speed pins. * This register controls the following pins: * - P3_3 and pins CLK0 to CLK3. */ typedef enum { /* Group Port 0 */ P0_0 = (PIN_GROUP0+PIN0), P0_1 = (PIN_GROUP0+PIN1), /* Group Port 1 */ P1_0 = (PIN_GROUP1+PIN0), P1_1 = (PIN_GROUP1+PIN1), P1_2 = (PIN_GROUP1+PIN2), P1_3 = (PIN_GROUP1+PIN3), P1_4 = (PIN_GROUP1+PIN4), P1_5 = (PIN_GROUP1+PIN5), P1_6 = (PIN_GROUP1+PIN6), P1_7 = (PIN_GROUP1+PIN7), P1_8 = (PIN_GROUP1+PIN8), P1_9 = (PIN_GROUP1+PIN9), P1_10 = (PIN_GROUP1+PIN10), P1_11 = (PIN_GROUP1+PIN11), P1_12 = (PIN_GROUP1+PIN12), P1_13 = (PIN_GROUP1+PIN13), P1_14 = (PIN_GROUP1+PIN14), P1_15 = (PIN_GROUP1+PIN15), P1_16 = (PIN_GROUP1+PIN16), /* P1_17 is High-Drive pin */ P1_17 = (PIN_GROUP1+PIN17), P1_18 = (PIN_GROUP1+PIN18), P1_19 = (PIN_GROUP1+PIN19), P1_20 = (PIN_GROUP1+PIN20), /* Group Port 2 */ P2_0 = (PIN_GROUP2+PIN0), P2_1 = (PIN_GROUP2+PIN1), P2_2 = (PIN_GROUP2+PIN2), /* P2_3 to P2_5 are High-Drive pins */ P2_3 = (PIN_GROUP2+PIN3), P2_4 = (PIN_GROUP2+PIN4), P2_5 = (PIN_GROUP2+PIN5), P2_6 = (PIN_GROUP2+PIN6), P2_7 = (PIN_GROUP2+PIN7), P2_8 = (PIN_GROUP2+PIN8), P2_9 = (PIN_GROUP2+PIN9), P2_10 = (PIN_GROUP2+PIN10), P2_11 = (PIN_GROUP2+PIN11), P2_12 = (PIN_GROUP2+PIN12), P2_13 = (PIN_GROUP2+PIN13), /* Group Port 3 */ P3_0 = (PIN_GROUP3+PIN0), P3_1 = (PIN_GROUP3+PIN1), P3_2 = (PIN_GROUP3+PIN2), /* P3_3 is High-Speed pin */ P3_3 = (PIN_GROUP3+PIN3), P3_4 = (PIN_GROUP3+PIN4), P3_5 = (PIN_GROUP3+PIN5), P3_6 = (PIN_GROUP3+PIN6), P3_7 = (PIN_GROUP3+PIN7), P3_8 = (PIN_GROUP3+PIN8), /* Group Port 4 */ P4_0 = (PIN_GROUP4+PIN0), P4_1 = (PIN_GROUP4+PIN1), P4_2 = (PIN_GROUP4+PIN2), P4_3 = (PIN_GROUP4+PIN3), P4_4 = (PIN_GROUP4+PIN4), P4_5 = (PIN_GROUP4+PIN5), P4_6 = (PIN_GROUP4+PIN6), P4_7 = (PIN_GROUP4+PIN7), P4_8 = (PIN_GROUP4+PIN8), P4_9 = (PIN_GROUP4+PIN9), P4_10 = (PIN_GROUP4+PIN10), /* Group Port 5 */ P5_0 = (PIN_GROUP5+PIN0), P5_1 = (PIN_GROUP5+PIN1), P5_2 = (PIN_GROUP5+PIN2), P5_3 = (PIN_GROUP5+PIN3), P5_4 = (PIN_GROUP5+PIN4), P5_5 = (PIN_GROUP5+PIN5), P5_6 = (PIN_GROUP5+PIN6), P5_7 = (PIN_GROUP5+PIN7), /* Group Port 6 */ P6_0 = (PIN_GROUP6+PIN0), P6_1 = (PIN_GROUP6+PIN1), P6_2 = (PIN_GROUP6+PIN2), P6_3 = (PIN_GROUP6+PIN3), P6_4 = (PIN_GROUP6+PIN4), P6_5 = (PIN_GROUP6+PIN5), P6_6 = (PIN_GROUP6+PIN6), P6_7 = (PIN_GROUP6+PIN7), P6_8 = (PIN_GROUP6+PIN8), P6_9 = (PIN_GROUP6+PIN9), P6_10 = (PIN_GROUP6+PIN10), P6_11 = (PIN_GROUP6+PIN11), P6_12 = (PIN_GROUP6+PIN12), /* Group Port 7 */ P7_0 = (PIN_GROUP7+PIN0), P7_1 = (PIN_GROUP7+PIN1), P7_2 = (PIN_GROUP7+PIN2), P7_3 = (PIN_GROUP7+PIN3), P7_4 = (PIN_GROUP7+PIN4), P7_5 = (PIN_GROUP7+PIN5), P7_6 = (PIN_GROUP7+PIN6), P7_7 = (PIN_GROUP7+PIN7), /* Group Port 8 */ /* P8_0 to P8_2 are High-Drive pins */ P8_0 = (PIN_GROUP8+PIN0), P8_1 = (PIN_GROUP8+PIN1), P8_2 = (PIN_GROUP8+PIN2), P8_3 = (PIN_GROUP8+PIN3), P8_4 = (PIN_GROUP8+PIN4), P8_5 = (PIN_GROUP8+PIN5), P8_6 = (PIN_GROUP8+PIN6), P8_7 = (PIN_GROUP8+PIN7), P8_8 = (PIN_GROUP8+PIN8), /* Group Port 9 */ P9_0 = (PIN_GROUP9+PIN0), P9_1 = (PIN_GROUP9+PIN1), P9_2 = (PIN_GROUP9+PIN2), P9_3 = (PIN_GROUP9+PIN3), P9_4 = (PIN_GROUP9+PIN4), P9_5 = (PIN_GROUP9+PIN5), P9_6 = (PIN_GROUP9+PIN6), /* Group Port A */ PA_0 = (PIN_GROUPA+PIN0), /* PA_1 to PA_3 are Normal & High-Drive Pins */ PA_1 = (PIN_GROUPA+PIN1), PA_2 = (PIN_GROUPA+PIN2), PA_3 = (PIN_GROUPA+PIN3), PA_4 = (PIN_GROUPA+PIN4), /* Group Port B */ PB_0 = (PIN_GROUPB+PIN0), PB_1 = (PIN_GROUPB+PIN1), PB_2 = (PIN_GROUPB+PIN2), PB_3 = (PIN_GROUPB+PIN3), PB_4 = (PIN_GROUPB+PIN4), PB_5 = (PIN_GROUPB+PIN5), PB_6 = (PIN_GROUPB+PIN6), /* Group Port C */ PC_0 = (PIN_GROUPC+PIN0), PC_1 = (PIN_GROUPC+PIN1), PC_2 = (PIN_GROUPC+PIN2), PC_3 = (PIN_GROUPC+PIN3), PC_4 = (PIN_GROUPC+PIN4), PC_5 = (PIN_GROUPC+PIN5), PC_6 = (PIN_GROUPC+PIN6), PC_7 = (PIN_GROUPC+PIN7), PC_8 = (PIN_GROUPC+PIN8), PC_9 = (PIN_GROUPC+PIN9), PC_10 = (PIN_GROUPC+PIN10), PC_11 = (PIN_GROUPC+PIN11), PC_12 = (PIN_GROUPC+PIN12), PC_13 = (PIN_GROUPC+PIN13), PC_14 = (PIN_GROUPC+PIN14), /* Group Port D (seems not configurable through SCU, not defined in * UM10503.pdf Rev.1, keep it here) */ PD_0 = (PIN_GROUPD+PIN0), PD_1 = (PIN_GROUPD+PIN1), PD_2 = (PIN_GROUPD+PIN2), PD_3 = (PIN_GROUPD+PIN3), PD_4 = (PIN_GROUPD+PIN4), PD_5 = (PIN_GROUPD+PIN5), PD_6 = (PIN_GROUPD+PIN6), PD_7 = (PIN_GROUPD+PIN7), PD_8 = (PIN_GROUPD+PIN8), PD_9 = (PIN_GROUPD+PIN9), PD_10 = (PIN_GROUPD+PIN10), PD_11 = (PIN_GROUPD+PIN11), PD_12 = (PIN_GROUPD+PIN12), PD_13 = (PIN_GROUPD+PIN13), PD_14 = (PIN_GROUPD+PIN14), PD_15 = (PIN_GROUPD+PIN15), PD_16 = (PIN_GROUPD+PIN16), /* Group Port E */ PE_0 = (PIN_GROUPE+PIN0), PE_1 = (PIN_GROUPE+PIN1), PE_2 = (PIN_GROUPE+PIN2), PE_3 = (PIN_GROUPE+PIN3), PE_4 = (PIN_GROUPE+PIN4), PE_5 = (PIN_GROUPE+PIN5), PE_6 = (PIN_GROUPE+PIN6), PE_7 = (PIN_GROUPE+PIN7), PE_8 = (PIN_GROUPE+PIN8), PE_9 = (PIN_GROUPE+PIN9), PE_10 = (PIN_GROUPE+PIN10), PE_11 = (PIN_GROUPE+PIN11), PE_12 = (PIN_GROUPE+PIN12), PE_13 = (PIN_GROUPE+PIN13), PE_14 = (PIN_GROUPE+PIN14), PE_15 = (PIN_GROUPE+PIN15), /* Group Port F */ PF_0 = (PIN_GROUPF+PIN0), PF_1 = (PIN_GROUPF+PIN1), PF_2 = (PIN_GROUPF+PIN2), PF_3 = (PIN_GROUPF+PIN3), PF_4 = (PIN_GROUPF+PIN4), PF_5 = (PIN_GROUPF+PIN5), PF_6 = (PIN_GROUPF+PIN6), PF_7 = (PIN_GROUPF+PIN7), PF_8 = (PIN_GROUPF+PIN8), PF_9 = (PIN_GROUPF+PIN9), PF_10 = (PIN_GROUPF+PIN10), PF_11 = (PIN_GROUPF+PIN11), /* Group Clock 0 to 3 High-Speed pins */ CLK0 = (SCU_BASE + 0xC00), CLK1 = (SCU_BASE + 0xC04), CLK2 = (SCU_BASE + 0xC08), CLK3 = (SCU_BASE + 0xC0C) } scu_grp_pin_t; /* * Pin Configuration to be used for scu_pinmux() parameter scu_conf * For normal-drive pins, high-drive pins, high-speed pins */ /* * Function BIT0 to 2. * Common to normal-drive pins, high-drive pins, high-speed pins. */ #define SCU_CONF_FUNCTION0 (0x0) #define SCU_CONF_FUNCTION1 (0x1) #define SCU_CONF_FUNCTION2 (0x2) #define SCU_CONF_FUNCTION3 (0x3) #define SCU_CONF_FUNCTION4 (0x4) #define SCU_CONF_FUNCTION5 (0x5) #define SCU_CONF_FUNCTION6 (0x6) #define SCU_CONF_FUNCTION7 (0x7) /* * Enable pull-down resistor at pad * By default=0 Disable pull-down. * Available to normal-drive pins, high-drive pins, high-speed pins */ #define SCU_CONF_EPD_EN_PULLDOWN (BIT3) /* * Disable pull-up resistor at pad. * By default=0 the pull-up resistor is enabled at reset. * Available to normal-drive pins, high-drive pins, high-speed pins */ #define SCU_CONF_EPUN_DIS_PULLUP (BIT4) /* * Select Slew Rate. * By Default=0 Slow. * Available to normal-drive and high-speed pins, reserved for high-drive pins. */ #define SCU_CONF_EHS_FAST (BIT5) /* * Input buffer enable. * By Default=0 Disable Input Buffer. * The input buffer is disabled by default at reset and must be enabled for * receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer * to the pad(in high-drive pins). * Available to normal-drive pins, high-drive pins, high-speed pins. */ #define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) /* * Input glitch filter. Disable the input glitch filter for clocking signals * higher than 30 MHz. * Available to normal-drive pins, high-drive pins, high-speed pins. */ #define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) /* * Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). * Available to high-drive pins, reserved for others. */ #define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) #define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) #define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) /* BIT10 to 31 are Reserved */ /* Configuration for different I/O pins types */ #define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \ SCU_CONF_EHS_FAST | \ SCU_CONF_EZI_EN_IN_BUFFER | \ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \ SCU_CONF_EHS_FAST | \ SCU_CONF_EZI_EN_IN_BUFFER | \ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \ SCU_CONF_EHS_FAST | \ SCU_CONF_EZI_EN_IN_BUFFER | \ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \ SCU_CONF_EHS_FAST | \ SCU_CONF_EZI_EN_IN_BUFFER | \ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) #define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \ SCU_CONF_EPD_EN_PULLDOWN | \ SCU_CONF_EZI_EN_IN_BUFFER) #define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \ SCU_CONF_EZI_EN_IN_BUFFER) #define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \ SCU_CONF_EHS_FAST | \ SCU_CONF_EZI_EN_IN_BUFFER | \ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \ SCU_CONF_EPD_EN_PULLDOWN | \ SCU_CONF_EZI_EN_IN_BUFFER) #define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \ SCU_CONF_EHS_FAST | \ SCU_CONF_EZI_EN_IN_BUFFER | \ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) BEGIN_DECLS void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf); END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/sdio.h000066400000000000000000001162361435536612600235740ustar00rootroot00000000000000/** @defgroup sdio_defines SDIO @brief Defined Constants and Types for the LPC43xx SDIO @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @author @htmlonly © @endhtmlonly 2014 Jared Boone @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2014 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_SDIO_H #define LPC43XX_SDIO_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- SDIO registers ----------------------------------------------------- */ /* Control Register */ #define SDIO_CTRL MMIO32(SDIO_BASE + 0x000) /* Power Enable Register */ #define SDIO_PWREN MMIO32(SDIO_BASE + 0x004) /* Clock Divider Register */ #define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008) /* SD Clock Source Register */ #define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C) /* Clock Enable Register */ #define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010) /* Time-out Register */ #define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014) /* Card Type Register */ #define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018) /* Block Size Register */ #define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C) /* Byte Count Register */ #define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020) /* Interrupt Mask Register */ #define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024) /* Command Argument Register */ #define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028) /* Command Register */ #define SDIO_CMD MMIO32(SDIO_BASE + 0x02C) /* Response Register 0 */ #define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030) /* Response Register 1 */ #define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034) /* Response Register 2 */ #define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038) /* Response Register 3 */ #define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C) /* Masked Interrupt Status Register */ #define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040) /* Raw Interrupt Status Register */ #define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044) /* Status Register */ #define SDIO_STATUS MMIO32(SDIO_BASE + 0x048) /* FIFO Threshold Watermark Register */ #define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C) /* Card Detect Register */ #define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050) /* Write Protect Register */ #define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054) /* Transferred CIU Card Byte Count Register */ #define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C) /* Transferred Host to BIU-FIFO Byte Count Register */ #define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060) /* Debounce Count Register */ #define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064) /* Hardware Reset */ #define SDIO_RST_N MMIO32(SDIO_BASE + 0x078) /* Bus Mode Register */ #define SDIO_BMOD MMIO32(SDIO_BASE + 0x080) /* Poll Demand Register */ #define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084) /* Descriptor List Base Address Register */ #define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088) /* Internal DMAC Status Register */ #define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C) /* Internal DMAC Interrupt Enable Register */ #define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090) /* Current Host Descriptor Address Register */ #define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094) /* Current Buffer Descriptor Address Register */ #define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098) /* Data FIFO read/write */ #define SDIO_DATA MMIO32(SDIO_BASE + 0x100) /* --- SDIO_CTRL values ----------------------------------------- */ /* CONTROLLER_RESET: Controller reset */ #define SDIO_CTRL_CONTROLLER_RESET_SHIFT (0) #define SDIO_CTRL_CONTROLLER_RESET_MASK (0x1 << SDIO_CTRL_CONTROLLER_RESET_SHIFT) #define SDIO_CTRL_CONTROLLER_RESET(x) ((x) << SDIO_CTRL_CONTROLLER_RESET_SHIFT) /* FIFO_RESET: FIFO reset */ #define SDIO_CTRL_FIFO_RESET_SHIFT (1) #define SDIO_CTRL_FIFO_RESET_MASK (0x1 << SDIO_CTRL_FIFO_RESET_SHIFT) #define SDIO_CTRL_FIFO_RESET(x) ((x) << SDIO_CTRL_FIFO_RESET_SHIFT) /* DMA_RESET: DMA reset */ #define SDIO_CTRL_DMA_RESET_SHIFT (2) #define SDIO_CTRL_DMA_RESET_MASK (0x1 << SDIO_CTRL_DMA_RESET_SHIFT) #define SDIO_CTRL_DMA_RESET(x) ((x) << SDIO_CTRL_DMA_RESET_SHIFT) /* INT_ENABLE: Global interrupt enable/disable */ #define SDIO_CTRL_INT_ENABLE_SHIFT (4) #define SDIO_CTRL_INT_ENABLE_MASK (0x1 << SDIO_CTRL_INT_ENABLE_SHIFT) #define SDIO_CTRL_INT_ENABLE(x) ((x) << SDIO_CTRL_INT_ENABLE_SHIFT) /* READ_WAIT: Read/wait send */ #define SDIO_CTRL_READ_WAIT_SHIFT (6) #define SDIO_CTRL_READ_WAIT_MASK (0x1 << SDIO_CTRL_READ_WAIT_SHIFT) #define SDIO_CTRL_READ_WAIT(x) ((x) << SDIO_CTRL_READ_WAIT_SHIFT) /* SEND_IRQ_RESPONSE: Send IRQ response */ #define SDIO_CTRL_SEND_IRQ_RESPONSE_SHIFT (7) #define SDIO_CTRL_SEND_IRQ_RESPONSE_MASK (0x1 << SDIO_CTRL_SEND_IRQ_RESPONSE_SHIFT) #define SDIO_CTRL_SEND_IRQ_RESPONSE(x) ((x) << SDIO_CTRL_SEND_IRQ_RESPONSE_SHIFT) /* ABORT_READ_DATA: Abort read data */ #define SDIO_CTRL_ABORT_READ_DATA_SHIFT (8) #define SDIO_CTRL_ABORT_READ_DATA_MASK (0x1 << SDIO_CTRL_ABORT_READ_DATA_SHIFT) #define SDIO_CTRL_ABORT_READ_DATA(x) ((x) << SDIO_CTRL_ABORT_READ_DATA_SHIFT) /* SEND_CCSD: Send CCSD */ #define SDIO_CTRL_SEND_CCSD_SHIFT (9) #define SDIO_CTRL_SEND_CCSD_MASK (0x1 << SDIO_CTRL_SEND_CCSD_SHIFT) #define SDIO_CTRL_SEND_CCSD(x) ((x) << SDIO_CTRL_SEND_CCSD_SHIFT) /* SEND_AUTO_STOP_CCSD: Send auto stop CCSD */ #define SDIO_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10) #define SDIO_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x1 << SDIO_CTRL_SEND_AUTO_STOP_CCSD_SHIFT) #define SDIO_CTRL_SEND_AUTO_STOP_CCSD(x) ((x) << SDIO_CTRL_SEND_AUTO_STOP_CCSD_SHIFT) /* CEATA_DEVICE_INTERRUPT_STATUS: CEATA device interrupt status */ #define SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11) #define SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x1 << SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT) #define SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) ((x) << SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT) /* CARD_VOLTAGE_A0: SD_VOLT0 pin control */ #define SDIO_CTRL_CARD_VOLTAGE_A0_SHIFT (16) #define SDIO_CTRL_CARD_VOLTAGE_A0_MASK (0x1 << SDIO_CTRL_CARD_VOLTAGE_A0_SHIFT) #define SDIO_CTRL_CARD_VOLTAGE_A0(x) ((x) << SDIO_CTRL_CARD_VOLTAGE_A0_SHIFT) /* CARD_VOLTAGE_A1: SD_VOLT1 pin control */ #define SDIO_CTRL_CARD_VOLTAGE_A1_SHIFT (17) #define SDIO_CTRL_CARD_VOLTAGE_A1_MASK (0x1 << SDIO_CTRL_CARD_VOLTAGE_A1_SHIFT) #define SDIO_CTRL_CARD_VOLTAGE_A1(x) ((x) << SDIO_CTRL_CARD_VOLTAGE_A1_SHIFT) /* CARD_VOLTAGE_A2: SD_VOLT2 pin control */ #define SDIO_CTRL_CARD_VOLTAGE_A2_SHIFT (18) #define SDIO_CTRL_CARD_VOLTAGE_A2_MASK (0x1 << SDIO_CTRL_CARD_VOLTAGE_A2_SHIFT) #define SDIO_CTRL_CARD_VOLTAGE_A2(x) ((x) << SDIO_CTRL_CARD_VOLTAGE_A2_SHIFT) /* USE_INTERNAL_DMAC: SD/MMC DMA use */ #define SDIO_CTRL_USE_INTERNAL_DMAC_SHIFT (25) #define SDIO_CTRL_USE_INTERNAL_DMAC_MASK (0x1 << SDIO_CTRL_USE_INTERNAL_DMAC_SHIFT) #define SDIO_CTRL_USE_INTERNAL_DMAC(x) ((x) << SDIO_CTRL_USE_INTERNAL_DMAC_SHIFT) /* --- SDIO_PWREN values ---------------------------------------- */ /* POWER_ENABLE: Power on/off switch for card */ #define SDIO_PWREN_POWER_ENABLE_SHIFT (0) #define SDIO_PWREN_POWER_ENABLE_MASK (0x1 << SDIO_PWREN_POWER_ENABLE_SHIFT) #define SDIO_PWREN_POWER_ENABLE(x) ((x) << SDIO_PWREN_POWER_ENABLE_SHIFT) /* --- SDIO_CLKDIV values --------------------------------------- */ /* CLK_DIVIDER0: Clock divider-0 value */ #define SDIO_CLKDIV_CLK_DIVIDER0_SHIFT (0) #define SDIO_CLKDIV_CLK_DIVIDER0_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER0_SHIFT) #define SDIO_CLKDIV_CLK_DIVIDER0(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER0_SHIFT) /* CLK_DIVIDER1: Clock divider-1 value */ #define SDIO_CLKDIV_CLK_DIVIDER1_SHIFT (8) #define SDIO_CLKDIV_CLK_DIVIDER1_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER1_SHIFT) #define SDIO_CLKDIV_CLK_DIVIDER1(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER1_SHIFT) /* CLK_DIVIDER2: Clock divider-2 value */ #define SDIO_CLKDIV_CLK_DIVIDER2_SHIFT (16) #define SDIO_CLKDIV_CLK_DIVIDER2_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER2_SHIFT) #define SDIO_CLKDIV_CLK_DIVIDER2(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER2_SHIFT) /* CLK_DIVIDER3: Clock divider-3 value */ #define SDIO_CLKDIV_CLK_DIVIDER3_SHIFT (24) #define SDIO_CLKDIV_CLK_DIVIDER3_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER3_SHIFT) #define SDIO_CLKDIV_CLK_DIVIDER3(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER3_SHIFT) /* --- SDIO_CLKSRC values --------------------------------------- */ /* CLK_SOURCE: Clock divider source for SD card */ #define SDIO_CLKSRC_CLK_SOURCE_SHIFT (0) #define SDIO_CLKSRC_CLK_SOURCE_MASK (0x3 << SDIO_CLKSRC_CLK_SOURCE_SHIFT) #define SDIO_CLKSRC_CLK_SOURCE(x) ((x) << SDIO_CLKSRC_CLK_SOURCE_SHIFT) /* --- SDIO_CLKENA values --------------------------------------- */ /* CCLK_ENABLE: Clock-enable control for SD card clock */ #define SDIO_CLKENA_CCLK_ENABLE_SHIFT (0) #define SDIO_CLKENA_CCLK_ENABLE_MASK (0x1 << SDIO_CLKENA_CCLK_ENABLE_SHIFT) #define SDIO_CLKENA_CCLK_ENABLE(x) ((x) << SDIO_CLKENA_CCLK_ENABLE_SHIFT) /* CCLK_LOW_POWER: Low-power control for SD card clock */ #define SDIO_CLKENA_CCLK_LOW_POWER_SHIFT (16) #define SDIO_CLKENA_CCLK_LOW_POWER_MASK (0x1 << SDIO_CLKENA_CCLK_LOW_POWER_SHIFT) #define SDIO_CLKENA_CCLK_LOW_POWER(x) ((x) << SDIO_CLKENA_CCLK_LOW_POWER_SHIFT) /* --- SDIO_TMOUT values ---------------------------------------- */ /* RESPONSE_TIMEOUT: Response time-out value */ #define SDIO_TMOUT_RESPONSE_TIMEOUT_SHIFT (0) #define SDIO_TMOUT_RESPONSE_TIMEOUT_MASK (0xff << SDIO_TMOUT_RESPONSE_TIMEOUT_SHIFT) #define SDIO_TMOUT_RESPONSE_TIMEOUT(x) ((x) << SDIO_TMOUT_RESPONSE_TIMEOUT_SHIFT) /* DATA_TIMEOUT: Value for card data read time-out */ #define SDIO_TMOUT_DATA_TIMEOUT_SHIFT (8) #define SDIO_TMOUT_DATA_TIMEOUT_MASK (0xffffff << SDIO_TMOUT_DATA_TIMEOUT_SHIFT) #define SDIO_TMOUT_DATA_TIMEOUT(x) ((x) << SDIO_TMOUT_DATA_TIMEOUT_SHIFT) /* --- SDIO_CTYPE values ---------------------------------------- */ /* CARD_WIDTH0: Indicates if card is 1-bit or 4-bit */ #define SDIO_CTYPE_CARD_WIDTH0_SHIFT (0) #define SDIO_CTYPE_CARD_WIDTH0_MASK (0x1 << SDIO_CTYPE_CARD_WIDTH0_SHIFT) #define SDIO_CTYPE_CARD_WIDTH0(x) ((x) << SDIO_CTYPE_CARD_WIDTH0_SHIFT) /* CARD_WIDTH1: Indicates if card is 8-bit */ #define SDIO_CTYPE_CARD_WIDTH1_SHIFT (16) #define SDIO_CTYPE_CARD_WIDTH1_MASK (0x1 << SDIO_CTYPE_CARD_WIDTH1_SHIFT) #define SDIO_CTYPE_CARD_WIDTH1(x) ((x) << SDIO_CTYPE_CARD_WIDTH1_SHIFT) /* --- SDIO_BLKSIZ values --------------------------------------- */ /* BLOCK_SIZE: Block size */ #define SDIO_BLKSIZ_BLOCK_SIZE_SHIFT (0) #define SDIO_BLKSIZ_BLOCK_SIZE_MASK (0xffff << SDIO_BLKSIZ_BLOCK_SIZE_SHIFT) #define SDIO_BLKSIZ_BLOCK_SIZE(x) ((x) << SDIO_BLKSIZ_BLOCK_SIZE_SHIFT) /* --- SDIO_BYTCNT values --------------------------------------- */ /* BYTE_COUNT: Number of bytes to be transferred */ #define SDIO_BYTCNT_BYTE_COUNT_SHIFT (0) #define SDIO_BYTCNT_BYTE_COUNT_MASK (0xffffffff << SDIO_BYTCNT_BYTE_COUNT_SHIFT) #define SDIO_BYTCNT_BYTE_COUNT(x) ((x) << SDIO_BYTCNT_BYTE_COUNT_SHIFT) /* --- SDIO_INTMASK values -------------------------------------- */ /* CDET: Card detect */ #define SDIO_INTMASK_CDET_SHIFT (0) #define SDIO_INTMASK_CDET_MASK (0x1 << SDIO_INTMASK_CDET_SHIFT) #define SDIO_INTMASK_CDET(x) ((x) << SDIO_INTMASK_CDET_SHIFT) /* RE: Response error */ #define SDIO_INTMASK_RE_SHIFT (1) #define SDIO_INTMASK_RE_MASK (0x1 << SDIO_INTMASK_RE_SHIFT) #define SDIO_INTMASK_RE(x) ((x) << SDIO_INTMASK_RE_SHIFT) /* CDONE: Command done */ #define SDIO_INTMASK_CDONE_SHIFT (2) #define SDIO_INTMASK_CDONE_MASK (0x1 << SDIO_INTMASK_CDONE_SHIFT) #define SDIO_INTMASK_CDONE(x) ((x) << SDIO_INTMASK_CDONE_SHIFT) /* DTO: Data transfer over */ #define SDIO_INTMASK_DTO_SHIFT (3) #define SDIO_INTMASK_DTO_MASK (0x1 << SDIO_INTMASK_DTO_SHIFT) #define SDIO_INTMASK_DTO(x) ((x) << SDIO_INTMASK_DTO_SHIFT) /* TXDR: Transmit FIFO data request */ #define SDIO_INTMASK_TXDR_SHIFT (4) #define SDIO_INTMASK_TXDR_MASK (0x1 << SDIO_INTMASK_TXDR_SHIFT) #define SDIO_INTMASK_TXDR(x) ((x) << SDIO_INTMASK_TXDR_SHIFT) /* RXDR: Receive FIFO data request */ #define SDIO_INTMASK_RXDR_SHIFT (5) #define SDIO_INTMASK_RXDR_MASK (0x1 << SDIO_INTMASK_RXDR_SHIFT) #define SDIO_INTMASK_RXDR(x) ((x) << SDIO_INTMASK_RXDR_SHIFT) /* RCRC: Response CRC error */ #define SDIO_INTMASK_RCRC_SHIFT (6) #define SDIO_INTMASK_RCRC_MASK (0x1 << SDIO_INTMASK_RCRC_SHIFT) #define SDIO_INTMASK_RCRC(x) ((x) << SDIO_INTMASK_RCRC_SHIFT) /* DCRC: Data CRC error */ #define SDIO_INTMASK_DCRC_SHIFT (7) #define SDIO_INTMASK_DCRC_MASK (0x1 << SDIO_INTMASK_DCRC_SHIFT) #define SDIO_INTMASK_DCRC(x) ((x) << SDIO_INTMASK_DCRC_SHIFT) /* RTO: Response time-out */ #define SDIO_INTMASK_RTO_SHIFT (8) #define SDIO_INTMASK_RTO_MASK (0x1 << SDIO_INTMASK_RTO_SHIFT) #define SDIO_INTMASK_RTO(x) ((x) << SDIO_INTMASK_RTO_SHIFT) /* DRTO: Data read time-out */ #define SDIO_INTMASK_DRTO_SHIFT (9) #define SDIO_INTMASK_DRTO_MASK (0x1 << SDIO_INTMASK_DRTO_SHIFT) #define SDIO_INTMASK_DRTO(x) ((x) << SDIO_INTMASK_DRTO_SHIFT) /* HTO: Data starvation-by-host time-out/volt_switch_int */ #define SDIO_INTMASK_HTO_SHIFT (10) #define SDIO_INTMASK_HTO_MASK (0x1 << SDIO_INTMASK_HTO_SHIFT) #define SDIO_INTMASK_HTO(x) ((x) << SDIO_INTMASK_HTO_SHIFT) /* FRUN: FIFO underrun/overrun error */ #define SDIO_INTMASK_FRUN_SHIFT (11) #define SDIO_INTMASK_FRUN_MASK (0x1 << SDIO_INTMASK_FRUN_SHIFT) #define SDIO_INTMASK_FRUN(x) ((x) << SDIO_INTMASK_FRUN_SHIFT) /* HLE: Hardware locked write error */ #define SDIO_INTMASK_HLE_SHIFT (12) #define SDIO_INTMASK_HLE_MASK (0x1 << SDIO_INTMASK_HLE_SHIFT) #define SDIO_INTMASK_HLE(x) ((x) << SDIO_INTMASK_HLE_SHIFT) /* SBE: Start-bit error */ #define SDIO_INTMASK_SBE_SHIFT (13) #define SDIO_INTMASK_SBE_MASK (0x1 << SDIO_INTMASK_SBE_SHIFT) #define SDIO_INTMASK_SBE(x) ((x) << SDIO_INTMASK_SBE_SHIFT) /* ACD: Auto command done */ #define SDIO_INTMASK_ACD_SHIFT (14) #define SDIO_INTMASK_ACD_MASK (0x1 << SDIO_INTMASK_ACD_SHIFT) #define SDIO_INTMASK_ACD(x) ((x) << SDIO_INTMASK_ACD_SHIFT) /* EBE: End-bit error (read)/Write no CRC */ #define SDIO_INTMASK_EBE_SHIFT (15) #define SDIO_INTMASK_EBE_MASK (0x1 << SDIO_INTMASK_EBE_SHIFT) #define SDIO_INTMASK_EBE(x) ((x) << SDIO_INTMASK_EBE_SHIFT) /* SDIO_INT_MASK: Mask SDIO interrupt */ #define SDIO_INTMASK_SDIO_INT_MASK_SHIFT (16) #define SDIO_INTMASK_SDIO_INT_MASK_MASK (0x1 << SDIO_INTMASK_SDIO_INT_MASK_SHIFT) #define SDIO_INTMASK_SDIO_INT_MASK(x) ((x) << SDIO_INTMASK_SDIO_INT_MASK_SHIFT) /* --- SDIO_CMDARG values --------------------------------------- */ /* CMD_ARG: Value indicates command argument to be passed to card */ #define SDIO_CMDARG_CMD_ARG_SHIFT (0) #define SDIO_CMDARG_CMD_ARG_MASK (0xffffffff << SDIO_CMDARG_CMD_ARG_SHIFT) #define SDIO_CMDARG_CMD_ARG(x) ((x) << SDIO_CMDARG_CMD_ARG_SHIFT) /* --- SDIO_CMD values ------------------------------------------ */ /* CMD_INDEX: Command index */ #define SDIO_CMD_CMD_INDEX_SHIFT (0) #define SDIO_CMD_CMD_INDEX_MASK (0x3f << SDIO_CMD_CMD_INDEX_SHIFT) #define SDIO_CMD_CMD_INDEX(x) ((x) << SDIO_CMD_CMD_INDEX_SHIFT) /* RESPONSE_EXPECT: Response expect */ #define SDIO_CMD_RESPONSE_EXPECT_SHIFT (6) #define SDIO_CMD_RESPONSE_EXPECT_MASK (0x1 << SDIO_CMD_RESPONSE_EXPECT_SHIFT) #define SDIO_CMD_RESPONSE_EXPECT(x) ((x) << SDIO_CMD_RESPONSE_EXPECT_SHIFT) /* RESPONSE_LENGTH: Response length */ #define SDIO_CMD_RESPONSE_LENGTH_SHIFT (7) #define SDIO_CMD_RESPONSE_LENGTH_MASK (0x1 << SDIO_CMD_RESPONSE_LENGTH_SHIFT) #define SDIO_CMD_RESPONSE_LENGTH(x) ((x) << SDIO_CMD_RESPONSE_LENGTH_SHIFT) /* CHECK_RESPONSE_CRC: Check response CRC */ #define SDIO_CMD_CHECK_RESPONSE_CRC_SHIFT (8) #define SDIO_CMD_CHECK_RESPONSE_CRC_MASK (0x1 << SDIO_CMD_CHECK_RESPONSE_CRC_SHIFT) #define SDIO_CMD_CHECK_RESPONSE_CRC(x) ((x) << SDIO_CMD_CHECK_RESPONSE_CRC_SHIFT) /* DATA_EXPECTED: Data expected */ #define SDIO_CMD_DATA_EXPECTED_SHIFT (9) #define SDIO_CMD_DATA_EXPECTED_MASK (0x1 << SDIO_CMD_DATA_EXPECTED_SHIFT) #define SDIO_CMD_DATA_EXPECTED(x) ((x) << SDIO_CMD_DATA_EXPECTED_SHIFT) /* READ_WRITE: Read/write */ #define SDIO_CMD_READ_WRITE_SHIFT (10) #define SDIO_CMD_READ_WRITE_MASK (0x1 << SDIO_CMD_READ_WRITE_SHIFT) #define SDIO_CMD_READ_WRITE(x) ((x) << SDIO_CMD_READ_WRITE_SHIFT) /* TRANSFER_MODE: Transfer mode */ #define SDIO_CMD_TRANSFER_MODE_SHIFT (11) #define SDIO_CMD_TRANSFER_MODE_MASK (0x1 << SDIO_CMD_TRANSFER_MODE_SHIFT) #define SDIO_CMD_TRANSFER_MODE(x) ((x) << SDIO_CMD_TRANSFER_MODE_SHIFT) /* SEND_AUTO_STOP: Send auto stop */ #define SDIO_CMD_SEND_AUTO_STOP_SHIFT (12) #define SDIO_CMD_SEND_AUTO_STOP_MASK (0x1 << SDIO_CMD_SEND_AUTO_STOP_SHIFT) #define SDIO_CMD_SEND_AUTO_STOP(x) ((x) << SDIO_CMD_SEND_AUTO_STOP_SHIFT) /* WAIT_PRVDATA_COMPLETE: Wait prvdata complete */ #define SDIO_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13) #define SDIO_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x1 << SDIO_CMD_WAIT_PRVDATA_COMPLETE_SHIFT) #define SDIO_CMD_WAIT_PRVDATA_COMPLETE(x) ((x) << SDIO_CMD_WAIT_PRVDATA_COMPLETE_SHIFT) /* STOP_ABORT_CMD: Stop abort command */ #define SDIO_CMD_STOP_ABORT_CMD_SHIFT (14) #define SDIO_CMD_STOP_ABORT_CMD_MASK (0x1 << SDIO_CMD_STOP_ABORT_CMD_SHIFT) #define SDIO_CMD_STOP_ABORT_CMD(x) ((x) << SDIO_CMD_STOP_ABORT_CMD_SHIFT) /* SEND_INITIALIZATION: Send initialization */ #define SDIO_CMD_SEND_INITIALIZATION_SHIFT (15) #define SDIO_CMD_SEND_INITIALIZATION_MASK (0x1 << SDIO_CMD_SEND_INITIALIZATION_SHIFT) #define SDIO_CMD_SEND_INITIALIZATION(x) ((x) << SDIO_CMD_SEND_INITIALIZATION_SHIFT) /* UPDATE_CLOCK_REGISTERS_ONLY: Update clock registers only */ #define SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21) #define SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x1 << SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT) #define SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) ((x) << SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT) /* READ_CEATA_DEVICE: Read CEATA device */ #define SDIO_CMD_READ_CEATA_DEVICE_SHIFT (22) #define SDIO_CMD_READ_CEATA_DEVICE_MASK (0x1 << SDIO_CMD_READ_CEATA_DEVICE_SHIFT) #define SDIO_CMD_READ_CEATA_DEVICE(x) ((x) << SDIO_CMD_READ_CEATA_DEVICE_SHIFT) /* CCS_EXPECTED: CCS expected */ #define SDIO_CMD_CCS_EXPECTED_SHIFT (23) #define SDIO_CMD_CCS_EXPECTED_MASK (0x1 << SDIO_CMD_CCS_EXPECTED_SHIFT) #define SDIO_CMD_CCS_EXPECTED(x) ((x) << SDIO_CMD_CCS_EXPECTED_SHIFT) /* ENABLE_BOOT: Enable boot */ #define SDIO_CMD_ENABLE_BOOT_SHIFT (24) #define SDIO_CMD_ENABLE_BOOT_MASK (0x1 << SDIO_CMD_ENABLE_BOOT_SHIFT) #define SDIO_CMD_ENABLE_BOOT(x) ((x) << SDIO_CMD_ENABLE_BOOT_SHIFT) /* EXPECT_BOOT_ACK: Expect boot acknowledge */ #define SDIO_CMD_EXPECT_BOOT_ACK_SHIFT (25) #define SDIO_CMD_EXPECT_BOOT_ACK_MASK (0x1 << SDIO_CMD_EXPECT_BOOT_ACK_SHIFT) #define SDIO_CMD_EXPECT_BOOT_ACK(x) ((x) << SDIO_CMD_EXPECT_BOOT_ACK_SHIFT) /* DISABLE_BOOT: Disable boot */ #define SDIO_CMD_DISABLE_BOOT_SHIFT (26) #define SDIO_CMD_DISABLE_BOOT_MASK (0x1 << SDIO_CMD_DISABLE_BOOT_SHIFT) #define SDIO_CMD_DISABLE_BOOT(x) ((x) << SDIO_CMD_DISABLE_BOOT_SHIFT) /* BOOT_MODE: Boot mode */ #define SDIO_CMD_BOOT_MODE_SHIFT (27) #define SDIO_CMD_BOOT_MODE_MASK (0x1 << SDIO_CMD_BOOT_MODE_SHIFT) #define SDIO_CMD_BOOT_MODE(x) ((x) << SDIO_CMD_BOOT_MODE_SHIFT) /* VOLT_SWITCH: Voltage switch bit */ #define SDIO_CMD_VOLT_SWITCH_SHIFT (28) #define SDIO_CMD_VOLT_SWITCH_MASK (0x1 << SDIO_CMD_VOLT_SWITCH_SHIFT) #define SDIO_CMD_VOLT_SWITCH(x) ((x) << SDIO_CMD_VOLT_SWITCH_SHIFT) /* START_CMD: Start command */ #define SDIO_CMD_START_CMD_SHIFT (31) #define SDIO_CMD_START_CMD_MASK (0x1 << SDIO_CMD_START_CMD_SHIFT) #define SDIO_CMD_START_CMD(x) ((x) << SDIO_CMD_START_CMD_SHIFT) /* --- SDIO_RESP0 values ---------------------------------------- */ /* RESPONSE0: Bit[31:0] of response */ #define SDIO_RESP0_RESPONSE0_SHIFT (0) #define SDIO_RESP0_RESPONSE0_MASK (0xffffffff << SDIO_RESP0_RESPONSE0_SHIFT) #define SDIO_RESP0_RESPONSE0(x) ((x) << SDIO_RESP0_RESPONSE0_SHIFT) /* --- SDIO_RESP1 values ---------------------------------------- */ /* RESPONSE1: Bit[63:32] of long response */ #define SDIO_RESP1_RESPONSE1_SHIFT (0) #define SDIO_RESP1_RESPONSE1_MASK (0xffffffff << SDIO_RESP1_RESPONSE1_SHIFT) #define SDIO_RESP1_RESPONSE1(x) ((x) << SDIO_RESP1_RESPONSE1_SHIFT) /* --- SDIO_RESP2 values ---------------------------------------- */ /* RESPONSE2: Bit[95:64] of long response */ #define SDIO_RESP2_RESPONSE2_SHIFT (0) #define SDIO_RESP2_RESPONSE2_MASK (0xffffffff << SDIO_RESP2_RESPONSE2_SHIFT) #define SDIO_RESP2_RESPONSE2(x) ((x) << SDIO_RESP2_RESPONSE2_SHIFT) /* --- SDIO_RESP3 values ---------------------------------------- */ /* RESPONSE3: Bit[127:96] of long response */ #define SDIO_RESP3_RESPONSE3_SHIFT (0) #define SDIO_RESP3_RESPONSE3_MASK (0xffffffff << SDIO_RESP3_RESPONSE3_SHIFT) #define SDIO_RESP3_RESPONSE3(x) ((x) << SDIO_RESP3_RESPONSE3_SHIFT) /* --- SDIO_MINTSTS values -------------------------------------- */ /* CDET: Card detect */ #define SDIO_MINTSTS_CDET_SHIFT (0) #define SDIO_MINTSTS_CDET_MASK (0x1 << SDIO_MINTSTS_CDET_SHIFT) #define SDIO_MINTSTS_CDET(x) ((x) << SDIO_MINTSTS_CDET_SHIFT) /* RE: Response error */ #define SDIO_MINTSTS_RE_SHIFT (1) #define SDIO_MINTSTS_RE_MASK (0x1 << SDIO_MINTSTS_RE_SHIFT) #define SDIO_MINTSTS_RE(x) ((x) << SDIO_MINTSTS_RE_SHIFT) /* CDONE: Command done */ #define SDIO_MINTSTS_CDONE_SHIFT (2) #define SDIO_MINTSTS_CDONE_MASK (0x1 << SDIO_MINTSTS_CDONE_SHIFT) #define SDIO_MINTSTS_CDONE(x) ((x) << SDIO_MINTSTS_CDONE_SHIFT) /* DTO: Data transfer over */ #define SDIO_MINTSTS_DTO_SHIFT (3) #define SDIO_MINTSTS_DTO_MASK (0x1 << SDIO_MINTSTS_DTO_SHIFT) #define SDIO_MINTSTS_DTO(x) ((x) << SDIO_MINTSTS_DTO_SHIFT) /* TXDR: Transmit FIFO data request */ #define SDIO_MINTSTS_TXDR_SHIFT (4) #define SDIO_MINTSTS_TXDR_MASK (0x1 << SDIO_MINTSTS_TXDR_SHIFT) #define SDIO_MINTSTS_TXDR(x) ((x) << SDIO_MINTSTS_TXDR_SHIFT) /* RXDR: Receive FIFO data request */ #define SDIO_MINTSTS_RXDR_SHIFT (5) #define SDIO_MINTSTS_RXDR_MASK (0x1 << SDIO_MINTSTS_RXDR_SHIFT) #define SDIO_MINTSTS_RXDR(x) ((x) << SDIO_MINTSTS_RXDR_SHIFT) /* RCRC: Response CRC error */ #define SDIO_MINTSTS_RCRC_SHIFT (6) #define SDIO_MINTSTS_RCRC_MASK (0x1 << SDIO_MINTSTS_RCRC_SHIFT) #define SDIO_MINTSTS_RCRC(x) ((x) << SDIO_MINTSTS_RCRC_SHIFT) /* DCRC: Data CRC error */ #define SDIO_MINTSTS_DCRC_SHIFT (7) #define SDIO_MINTSTS_DCRC_MASK (0x1 << SDIO_MINTSTS_DCRC_SHIFT) #define SDIO_MINTSTS_DCRC(x) ((x) << SDIO_MINTSTS_DCRC_SHIFT) /* RTO: Response time-out */ #define SDIO_MINTSTS_RTO_SHIFT (8) #define SDIO_MINTSTS_RTO_MASK (0x1 << SDIO_MINTSTS_RTO_SHIFT) #define SDIO_MINTSTS_RTO(x) ((x) << SDIO_MINTSTS_RTO_SHIFT) /* DRTO: Data read time-out */ #define SDIO_MINTSTS_DRTO_SHIFT (9) #define SDIO_MINTSTS_DRTO_MASK (0x1 << SDIO_MINTSTS_DRTO_SHIFT) #define SDIO_MINTSTS_DRTO(x) ((x) << SDIO_MINTSTS_DRTO_SHIFT) /* HTO: Data starvation-by-host time-out */ #define SDIO_MINTSTS_HTO_SHIFT (10) #define SDIO_MINTSTS_HTO_MASK (0x1 << SDIO_MINTSTS_HTO_SHIFT) #define SDIO_MINTSTS_HTO(x) ((x) << SDIO_MINTSTS_HTO_SHIFT) /* FRUN: FIFO underrun/overrun error */ #define SDIO_MINTSTS_FRUN_SHIFT (11) #define SDIO_MINTSTS_FRUN_MASK (0x1 << SDIO_MINTSTS_FRUN_SHIFT) #define SDIO_MINTSTS_FRUN(x) ((x) << SDIO_MINTSTS_FRUN_SHIFT) /* HLE: Hardware locked write error */ #define SDIO_MINTSTS_HLE_SHIFT (12) #define SDIO_MINTSTS_HLE_MASK (0x1 << SDIO_MINTSTS_HLE_SHIFT) #define SDIO_MINTSTS_HLE(x) ((x) << SDIO_MINTSTS_HLE_SHIFT) /* SBE: Start-bit error */ #define SDIO_MINTSTS_SBE_SHIFT (13) #define SDIO_MINTSTS_SBE_MASK (0x1 << SDIO_MINTSTS_SBE_SHIFT) #define SDIO_MINTSTS_SBE(x) ((x) << SDIO_MINTSTS_SBE_SHIFT) /* ACD: Auto command done */ #define SDIO_MINTSTS_ACD_SHIFT (14) #define SDIO_MINTSTS_ACD_MASK (0x1 << SDIO_MINTSTS_ACD_SHIFT) #define SDIO_MINTSTS_ACD(x) ((x) << SDIO_MINTSTS_ACD_SHIFT) /* EBE: End-bit error (read)/write no CRC */ #define SDIO_MINTSTS_EBE_SHIFT (15) #define SDIO_MINTSTS_EBE_MASK (0x1 << SDIO_MINTSTS_EBE_SHIFT) #define SDIO_MINTSTS_EBE(x) ((x) << SDIO_MINTSTS_EBE_SHIFT) /* SDIO_INTERRUPT: Interrupt from SDIO card */ #define SDIO_MINTSTS_SDIO_INTERRUPT_SHIFT (16) #define SDIO_MINTSTS_SDIO_INTERRUPT_MASK (0x1 << SDIO_MINTSTS_SDIO_INTERRUPT_SHIFT) #define SDIO_MINTSTS_SDIO_INTERRUPT(x) ((x) << SDIO_MINTSTS_SDIO_INTERRUPT_SHIFT) /* --- SDIO_RINTSTS values -------------------------------------- */ /* CDET: Card detect */ #define SDIO_RINTSTS_CDET_SHIFT (0) #define SDIO_RINTSTS_CDET_MASK (0x1 << SDIO_RINTSTS_CDET_SHIFT) #define SDIO_RINTSTS_CDET(x) ((x) << SDIO_RINTSTS_CDET_SHIFT) /* RE: Response error */ #define SDIO_RINTSTS_RE_SHIFT (1) #define SDIO_RINTSTS_RE_MASK (0x1 << SDIO_RINTSTS_RE_SHIFT) #define SDIO_RINTSTS_RE(x) ((x) << SDIO_RINTSTS_RE_SHIFT) /* CDONE: Command done */ #define SDIO_RINTSTS_CDONE_SHIFT (2) #define SDIO_RINTSTS_CDONE_MASK (0x1 << SDIO_RINTSTS_CDONE_SHIFT) #define SDIO_RINTSTS_CDONE(x) ((x) << SDIO_RINTSTS_CDONE_SHIFT) /* DTO: Data transfer over */ #define SDIO_RINTSTS_DTO_SHIFT (3) #define SDIO_RINTSTS_DTO_MASK (0x1 << SDIO_RINTSTS_DTO_SHIFT) #define SDIO_RINTSTS_DTO(x) ((x) << SDIO_RINTSTS_DTO_SHIFT) /* TXDR: Transmit FIFO data request */ #define SDIO_RINTSTS_TXDR_SHIFT (4) #define SDIO_RINTSTS_TXDR_MASK (0x1 << SDIO_RINTSTS_TXDR_SHIFT) #define SDIO_RINTSTS_TXDR(x) ((x) << SDIO_RINTSTS_TXDR_SHIFT) /* RXDR: Receive FIFO data request */ #define SDIO_RINTSTS_RXDR_SHIFT (5) #define SDIO_RINTSTS_RXDR_MASK (0x1 << SDIO_RINTSTS_RXDR_SHIFT) #define SDIO_RINTSTS_RXDR(x) ((x) << SDIO_RINTSTS_RXDR_SHIFT) /* RCRC: Response CRC error */ #define SDIO_RINTSTS_RCRC_SHIFT (6) #define SDIO_RINTSTS_RCRC_MASK (0x1 << SDIO_RINTSTS_RCRC_SHIFT) #define SDIO_RINTSTS_RCRC(x) ((x) << SDIO_RINTSTS_RCRC_SHIFT) /* DCRC: Data CRC error */ #define SDIO_RINTSTS_DCRC_SHIFT (7) #define SDIO_RINTSTS_DCRC_MASK (0x1 << SDIO_RINTSTS_DCRC_SHIFT) #define SDIO_RINTSTS_DCRC(x) ((x) << SDIO_RINTSTS_DCRC_SHIFT) /* RTO_BAR: Response time-out (RTO)/boot ack received (BAR) */ #define SDIO_RINTSTS_RTO_BAR_SHIFT (8) #define SDIO_RINTSTS_RTO_BAR_MASK (0x1 << SDIO_RINTSTS_RTO_BAR_SHIFT) #define SDIO_RINTSTS_RTO_BAR(x) ((x) << SDIO_RINTSTS_RTO_BAR_SHIFT) /* DRTO_BDS: Data read time-out (DRTO)/boot data start (BDS) */ #define SDIO_RINTSTS_DRTO_BDS_SHIFT (9) #define SDIO_RINTSTS_DRTO_BDS_MASK (0x1 << SDIO_RINTSTS_DRTO_BDS_SHIFT) #define SDIO_RINTSTS_DRTO_BDS(x) ((x) << SDIO_RINTSTS_DRTO_BDS_SHIFT) /* HTO: Data starvation-by-host time-out */ #define SDIO_RINTSTS_HTO_SHIFT (10) #define SDIO_RINTSTS_HTO_MASK (0x1 << SDIO_RINTSTS_HTO_SHIFT) #define SDIO_RINTSTS_HTO(x) ((x) << SDIO_RINTSTS_HTO_SHIFT) /* FRUN: FIFO underrun/overrun error */ #define SDIO_RINTSTS_FRUN_SHIFT (11) #define SDIO_RINTSTS_FRUN_MASK (0x1 << SDIO_RINTSTS_FRUN_SHIFT) #define SDIO_RINTSTS_FRUN(x) ((x) << SDIO_RINTSTS_FRUN_SHIFT) /* HLE: Hardware locked write error */ #define SDIO_RINTSTS_HLE_SHIFT (12) #define SDIO_RINTSTS_HLE_MASK (0x1 << SDIO_RINTSTS_HLE_SHIFT) #define SDIO_RINTSTS_HLE(x) ((x) << SDIO_RINTSTS_HLE_SHIFT) /* SBE: Start-bit error */ #define SDIO_RINTSTS_SBE_SHIFT (13) #define SDIO_RINTSTS_SBE_MASK (0x1 << SDIO_RINTSTS_SBE_SHIFT) #define SDIO_RINTSTS_SBE(x) ((x) << SDIO_RINTSTS_SBE_SHIFT) /* ACD: Auto command done */ #define SDIO_RINTSTS_ACD_SHIFT (14) #define SDIO_RINTSTS_ACD_MASK (0x1 << SDIO_RINTSTS_ACD_SHIFT) #define SDIO_RINTSTS_ACD(x) ((x) << SDIO_RINTSTS_ACD_SHIFT) /* EBE: End-bit error (read)/write no CRC */ #define SDIO_RINTSTS_EBE_SHIFT (15) #define SDIO_RINTSTS_EBE_MASK (0x1 << SDIO_RINTSTS_EBE_SHIFT) #define SDIO_RINTSTS_EBE(x) ((x) << SDIO_RINTSTS_EBE_SHIFT) /* SDIO_INTERRUPT: Interrupt from SDIO card */ #define SDIO_RINTSTS_SDIO_INTERRUPT_SHIFT (16) #define SDIO_RINTSTS_SDIO_INTERRUPT_MASK (0x1 << SDIO_RINTSTS_SDIO_INTERRUPT_SHIFT) #define SDIO_RINTSTS_SDIO_INTERRUPT(x) ((x) << SDIO_RINTSTS_SDIO_INTERRUPT_SHIFT) /* --- SDIO_STATUS values --------------------------------------- */ /* FIFO_RX_WATERMARK: FIFO reached receive watermark level */ #define SDIO_STATUS_FIFO_RX_WATERMARK_SHIFT (0) #define SDIO_STATUS_FIFO_RX_WATERMARK_MASK (0x1 << SDIO_STATUS_FIFO_RX_WATERMARK_SHIFT) #define SDIO_STATUS_FIFO_RX_WATERMARK(x) ((x) << SDIO_STATUS_FIFO_RX_WATERMARK_SHIFT) /* FIFO_TX_WATERMARK: FIFO reached transmit watermark level */ #define SDIO_STATUS_FIFO_TX_WATERMARK_SHIFT (1) #define SDIO_STATUS_FIFO_TX_WATERMARK_MASK (0x1 << SDIO_STATUS_FIFO_TX_WATERMARK_SHIFT) #define SDIO_STATUS_FIFO_TX_WATERMARK(x) ((x) << SDIO_STATUS_FIFO_TX_WATERMARK_SHIFT) /* FIFO_EMPTY: FIFO is empty */ #define SDIO_STATUS_FIFO_EMPTY_SHIFT (2) #define SDIO_STATUS_FIFO_EMPTY_MASK (0x1 << SDIO_STATUS_FIFO_EMPTY_SHIFT) #define SDIO_STATUS_FIFO_EMPTY(x) ((x) << SDIO_STATUS_FIFO_EMPTY_SHIFT) /* FIFO_FULL: FIFO is full */ #define SDIO_STATUS_FIFO_FULL_SHIFT (3) #define SDIO_STATUS_FIFO_FULL_MASK (0x1 << SDIO_STATUS_FIFO_FULL_SHIFT) #define SDIO_STATUS_FIFO_FULL(x) ((x) << SDIO_STATUS_FIFO_FULL_SHIFT) /* CMDFSMSTATES: Command FSM states */ #define SDIO_STATUS_CMDFSMSTATES_SHIFT (4) #define SDIO_STATUS_CMDFSMSTATES_MASK (0xf << SDIO_STATUS_CMDFSMSTATES_SHIFT) #define SDIO_STATUS_CMDFSMSTATES(x) ((x) << SDIO_STATUS_CMDFSMSTATES_SHIFT) /* DATA_3_STATUS: Raw selected card_data[3] */ #define SDIO_STATUS_DATA_3_STATUS_SHIFT (8) #define SDIO_STATUS_DATA_3_STATUS_MASK (0x1 << SDIO_STATUS_DATA_3_STATUS_SHIFT) #define SDIO_STATUS_DATA_3_STATUS(x) ((x) << SDIO_STATUS_DATA_3_STATUS_SHIFT) /* DATA_BUSY: Inverted version of raw selected card_data[0] */ #define SDIO_STATUS_DATA_BUSY_SHIFT (9) #define SDIO_STATUS_DATA_BUSY_MASK (0x1 << SDIO_STATUS_DATA_BUSY_SHIFT) #define SDIO_STATUS_DATA_BUSY(x) ((x) << SDIO_STATUS_DATA_BUSY_SHIFT) /* DATA_STATE_MC_BUSY: Data transmit or receive state-machine is busy */ #define SDIO_STATUS_DATA_STATE_MC_BUSY_SHIFT (10) #define SDIO_STATUS_DATA_STATE_MC_BUSY_MASK (0x1 << SDIO_STATUS_DATA_STATE_MC_BUSY_SHIFT) #define SDIO_STATUS_DATA_STATE_MC_BUSY(x) ((x) << SDIO_STATUS_DATA_STATE_MC_BUSY_SHIFT) /* RESPONSE_INDEX: Index of previous response */ #define SDIO_STATUS_RESPONSE_INDEX_SHIFT (11) #define SDIO_STATUS_RESPONSE_INDEX_MASK (0x3f << SDIO_STATUS_RESPONSE_INDEX_SHIFT) #define SDIO_STATUS_RESPONSE_INDEX(x) ((x) << SDIO_STATUS_RESPONSE_INDEX_SHIFT) /* FIFO_COUNT: Number of filled locations in FIFO */ #define SDIO_STATUS_FIFO_COUNT_SHIFT (17) #define SDIO_STATUS_FIFO_COUNT_MASK (0x1fff << SDIO_STATUS_FIFO_COUNT_SHIFT) #define SDIO_STATUS_FIFO_COUNT(x) ((x) << SDIO_STATUS_FIFO_COUNT_SHIFT) /* DMA_ACK: DMA acknowledge signal */ #define SDIO_STATUS_DMA_ACK_SHIFT (30) #define SDIO_STATUS_DMA_ACK_MASK (0x1 << SDIO_STATUS_DMA_ACK_SHIFT) #define SDIO_STATUS_DMA_ACK(x) ((x) << SDIO_STATUS_DMA_ACK_SHIFT) /* DMA_REQ: DMA request signal */ #define SDIO_STATUS_DMA_REQ_SHIFT (31) #define SDIO_STATUS_DMA_REQ_MASK (0x1 << SDIO_STATUS_DMA_REQ_SHIFT) #define SDIO_STATUS_DMA_REQ(x) ((x) << SDIO_STATUS_DMA_REQ_SHIFT) /* --- SDIO_FIFOTH values --------------------------------------- */ /* TX_WMARK: FIFO threshold watermark level when transmitting data to card */ #define SDIO_FIFOTH_TX_WMARK_SHIFT (0) #define SDIO_FIFOTH_TX_WMARK_MASK (0xfff << SDIO_FIFOTH_TX_WMARK_SHIFT) #define SDIO_FIFOTH_TX_WMARK(x) ((x) << SDIO_FIFOTH_TX_WMARK_SHIFT) /* RX_WMARK: FIFO threshold watermark level when receiving data from card */ #define SDIO_FIFOTH_RX_WMARK_SHIFT (16) #define SDIO_FIFOTH_RX_WMARK_MASK (0xfff << SDIO_FIFOTH_RX_WMARK_SHIFT) #define SDIO_FIFOTH_RX_WMARK(x) ((x) << SDIO_FIFOTH_RX_WMARK_SHIFT) /* DMA_MTS: Burst size of multiple transaction */ #define SDIO_FIFOTH_DMA_MTS_SHIFT (28) #define SDIO_FIFOTH_DMA_MTS_MASK (0x7 << SDIO_FIFOTH_DMA_MTS_SHIFT) #define SDIO_FIFOTH_DMA_MTS(x) ((x) << SDIO_FIFOTH_DMA_MTS_SHIFT) /* --- SDIO_CDETECT values -------------------------------------- */ /* CARD_DETECT: Card detect - 0 represents presence of card */ #define SDIO_CDETECT_CARD_DETECT_SHIFT (0) #define SDIO_CDETECT_CARD_DETECT_MASK (0x1 << SDIO_CDETECT_CARD_DETECT_SHIFT) #define SDIO_CDETECT_CARD_DETECT(x) ((x) << SDIO_CDETECT_CARD_DETECT_SHIFT) /* --- SDIO_WRTPRT values --------------------------------------- */ /* WRITE_PROTECT: Write protect - 1 represents write protection */ #define SDIO_WRTPRT_WRITE_PROTECT_SHIFT (0) #define SDIO_WRTPRT_WRITE_PROTECT_MASK (0x1 << SDIO_WRTPRT_WRITE_PROTECT_SHIFT) #define SDIO_WRTPRT_WRITE_PROTECT(x) ((x) << SDIO_WRTPRT_WRITE_PROTECT_SHIFT) /* --- SDIO_TCBCNT values --------------------------------------- */ /* TRANS_CARD_BYTE_COUNT: Number of bytes transferred by CIU unit to card */ #define SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0) #define SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xffffffff << SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT) #define SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT(x) ((x) << SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT) /* --- SDIO_TBBCNT values --------------------------------------- */ /* TRANS_FIFO_BYTE_COUNT: Number of bytes transferred between host/DMA memory and BIU FIFO */ #define SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0) #define SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xffffffff << SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT) #define SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) ((x) << SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT) /* --- SDIO_DEBNCE values --------------------------------------- */ /* DEBOUNCE_COUNT: Number of host clocks used by debounce filter logic for card detect */ #define SDIO_DEBNCE_DEBOUNCE_COUNT_SHIFT (0) #define SDIO_DEBNCE_DEBOUNCE_COUNT_MASK (0xffffff << SDIO_DEBNCE_DEBOUNCE_COUNT_SHIFT) #define SDIO_DEBNCE_DEBOUNCE_COUNT(x) ((x) << SDIO_DEBNCE_DEBOUNCE_COUNT_SHIFT) /* --- SDIO_RST_N values ---------------------------------------- */ /* CARD_RESET: Hardware reset */ #define SDIO_RST_N_CARD_RESET_SHIFT (0) #define SDIO_RST_N_CARD_RESET_MASK (0x1 << SDIO_RST_N_CARD_RESET_SHIFT) #define SDIO_RST_N_CARD_RESET(x) ((x) << SDIO_RST_N_CARD_RESET_SHIFT) /* --- SDIO_BMOD values ----------------------------------------- */ /* SWR: Software reset */ #define SDIO_BMOD_SWR_SHIFT (0) #define SDIO_BMOD_SWR_MASK (0x1 << SDIO_BMOD_SWR_SHIFT) #define SDIO_BMOD_SWR(x) ((x) << SDIO_BMOD_SWR_SHIFT) /* FB: Fixed burst */ #define SDIO_BMOD_FB_SHIFT (1) #define SDIO_BMOD_FB_MASK (0x1 << SDIO_BMOD_FB_SHIFT) #define SDIO_BMOD_FB(x) ((x) << SDIO_BMOD_FB_SHIFT) /* DSL: Descriptor skip length */ #define SDIO_BMOD_DSL_SHIFT (2) #define SDIO_BMOD_DSL_MASK (0x1f << SDIO_BMOD_DSL_SHIFT) #define SDIO_BMOD_DSL(x) ((x) << SDIO_BMOD_DSL_SHIFT) /* DE: SD/MMC DMA enable */ #define SDIO_BMOD_DE_SHIFT (7) #define SDIO_BMOD_DE_MASK (0x1 << SDIO_BMOD_DE_SHIFT) #define SDIO_BMOD_DE(x) ((x) << SDIO_BMOD_DE_SHIFT) /* PBL: Programmable burst length */ #define SDIO_BMOD_PBL_SHIFT (8) #define SDIO_BMOD_PBL_MASK (0x7 << SDIO_BMOD_PBL_SHIFT) #define SDIO_BMOD_PBL(x) ((x) << SDIO_BMOD_PBL_SHIFT) /* --- SDIO_PLDMND values --------------------------------------- */ /* PD: Poll demand */ #define SDIO_PLDMND_PD_SHIFT (0) #define SDIO_PLDMND_PD_MASK (0xffffffff << SDIO_PLDMND_PD_SHIFT) #define SDIO_PLDMND_PD(x) ((x) << SDIO_PLDMND_PD_SHIFT) /* --- SDIO_DBADDR values --------------------------------------- */ /* SDL: Start of descriptor list */ #define SDIO_DBADDR_SDL_SHIFT (0) #define SDIO_DBADDR_SDL_MASK (0xffffffff << SDIO_DBADDR_SDL_SHIFT) #define SDIO_DBADDR_SDL(x) ((x) << SDIO_DBADDR_SDL_SHIFT) /* --- SDIO_IDSTS values ---------------------------------------- */ /* TI: Transmit interrupt */ #define SDIO_IDSTS_TI_SHIFT (0) #define SDIO_IDSTS_TI_MASK (0x1 << SDIO_IDSTS_TI_SHIFT) #define SDIO_IDSTS_TI(x) ((x) << SDIO_IDSTS_TI_SHIFT) /* RI: Receive interrupt */ #define SDIO_IDSTS_RI_SHIFT (1) #define SDIO_IDSTS_RI_MASK (0x1 << SDIO_IDSTS_RI_SHIFT) #define SDIO_IDSTS_RI(x) ((x) << SDIO_IDSTS_RI_SHIFT) /* FBE: Fatal bus error interrupt */ #define SDIO_IDSTS_FBE_SHIFT (2) #define SDIO_IDSTS_FBE_MASK (0x1 << SDIO_IDSTS_FBE_SHIFT) #define SDIO_IDSTS_FBE(x) ((x) << SDIO_IDSTS_FBE_SHIFT) /* DU: Descriptor unavailable interrupt */ #define SDIO_IDSTS_DU_SHIFT (4) #define SDIO_IDSTS_DU_MASK (0x1 << SDIO_IDSTS_DU_SHIFT) #define SDIO_IDSTS_DU(x) ((x) << SDIO_IDSTS_DU_SHIFT) /* CES: Card error summary */ #define SDIO_IDSTS_CES_SHIFT (5) #define SDIO_IDSTS_CES_MASK (0x1 << SDIO_IDSTS_CES_SHIFT) #define SDIO_IDSTS_CES(x) ((x) << SDIO_IDSTS_CES_SHIFT) /* NIS: Normal interrupt summary */ #define SDIO_IDSTS_NIS_SHIFT (8) #define SDIO_IDSTS_NIS_MASK (0x1 << SDIO_IDSTS_NIS_SHIFT) #define SDIO_IDSTS_NIS(x) ((x) << SDIO_IDSTS_NIS_SHIFT) /* AIS: Abnormal interrupt summary */ #define SDIO_IDSTS_AIS_SHIFT (9) #define SDIO_IDSTS_AIS_MASK (0x1 << SDIO_IDSTS_AIS_SHIFT) #define SDIO_IDSTS_AIS(x) ((x) << SDIO_IDSTS_AIS_SHIFT) /* EB: Error bits */ #define SDIO_IDSTS_EB_SHIFT (10) #define SDIO_IDSTS_EB_MASK (0x7 << SDIO_IDSTS_EB_SHIFT) #define SDIO_IDSTS_EB(x) ((x) << SDIO_IDSTS_EB_SHIFT) /* FSM: DMAC state machine present state */ #define SDIO_IDSTS_FSM_SHIFT (13) #define SDIO_IDSTS_FSM_MASK (0xf << SDIO_IDSTS_FSM_SHIFT) #define SDIO_IDSTS_FSM(x) ((x) << SDIO_IDSTS_FSM_SHIFT) /* --- SDIO_IDINTEN values -------------------------------------- */ /* TI: Transmit interrupt enable */ #define SDIO_IDINTEN_TI_SHIFT (0) #define SDIO_IDINTEN_TI_MASK (0x1 << SDIO_IDINTEN_TI_SHIFT) #define SDIO_IDINTEN_TI(x) ((x) << SDIO_IDINTEN_TI_SHIFT) /* RI: Receive interrupt enable */ #define SDIO_IDINTEN_RI_SHIFT (1) #define SDIO_IDINTEN_RI_MASK (0x1 << SDIO_IDINTEN_RI_SHIFT) #define SDIO_IDINTEN_RI(x) ((x) << SDIO_IDINTEN_RI_SHIFT) /* FBE: Fatal bus error enable */ #define SDIO_IDINTEN_FBE_SHIFT (2) #define SDIO_IDINTEN_FBE_MASK (0x1 << SDIO_IDINTEN_FBE_SHIFT) #define SDIO_IDINTEN_FBE(x) ((x) << SDIO_IDINTEN_FBE_SHIFT) /* DU: Descriptor unavailable interrupt */ #define SDIO_IDINTEN_DU_SHIFT (4) #define SDIO_IDINTEN_DU_MASK (0x1 << SDIO_IDINTEN_DU_SHIFT) #define SDIO_IDINTEN_DU(x) ((x) << SDIO_IDINTEN_DU_SHIFT) /* CES: Card error summary interrupt */ #define SDIO_IDINTEN_CES_SHIFT (5) #define SDIO_IDINTEN_CES_MASK (0x1 << SDIO_IDINTEN_CES_SHIFT) #define SDIO_IDINTEN_CES(x) ((x) << SDIO_IDINTEN_CES_SHIFT) /* NIS: Normal interrupt summary enable */ #define SDIO_IDINTEN_NIS_SHIFT (8) #define SDIO_IDINTEN_NIS_MASK (0x1 << SDIO_IDINTEN_NIS_SHIFT) #define SDIO_IDINTEN_NIS(x) ((x) << SDIO_IDINTEN_NIS_SHIFT) /* AIS: Abnormal interrupt summary enable */ #define SDIO_IDINTEN_AIS_SHIFT (9) #define SDIO_IDINTEN_AIS_MASK (0x1 << SDIO_IDINTEN_AIS_SHIFT) #define SDIO_IDINTEN_AIS(x) ((x) << SDIO_IDINTEN_AIS_SHIFT) /* --- SDIO_DSCADDR values -------------------------------------- */ /* HDA: Host descriptor address pointer */ #define SDIO_DSCADDR_HDA_SHIFT (0) #define SDIO_DSCADDR_HDA_MASK (0xffffffff << SDIO_DSCADDR_HDA_SHIFT) #define SDIO_DSCADDR_HDA(x) ((x) << SDIO_DSCADDR_HDA_SHIFT) /* --- SDIO_BUFADDR values -------------------------------------- */ /* HBA: Host buffer address pointer */ #define SDIO_BUFADDR_HBA_SHIFT (0) #define SDIO_BUFADDR_HBA_MASK (0xffffffff << SDIO_BUFADDR_HBA_SHIFT) #define SDIO_BUFADDR_HBA(x) ((x) << SDIO_BUFADDR_HBA_SHIFT) BEGIN_DECLS /*****/ END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/sgpio.h000066400000000000000000000732241435536612600237560ustar00rootroot00000000000000/** @defgroup sgpio_defines Serial General Purpose I/O @brief Defined Constants and Types for the LPC43xx Serial General Purpose I/O @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /** @defgroup sdio_defines SDIO @brief Defined Constants and Types for the LPC43xx SDIO @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2012 Jared Boone * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_SGPIO_H #define LPC43XX_SGPIO_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- SGPIO registers ----------------------------------------------------- */ /* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */ #define SGPIO_OUT_MUX_CFG(pin) MMIO32(SGPIO_PORT_BASE + (pin * 0x04)) #define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00) #define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04) #define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08) #define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C) #define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10) #define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14) #define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18) #define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C) #define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20) #define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24) #define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28) #define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C) #define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30) #define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34) #define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38) #define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C) /* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */ #define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \ (slice * 0x04)) #define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40) #define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44) #define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48) #define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C) #define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50) #define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54) #define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58) #define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C) #define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60) #define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64) #define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68) #define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C) #define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70) #define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74) #define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78) #define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C) /* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */ #define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \ (slice * 0x04)) #define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80) #define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84) #define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88) #define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C) #define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90) #define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94) #define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98) #define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C) #define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0) #define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4) #define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8) #define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC) #define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0) #define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4) #define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8) #define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC) /* Slice data registers (REG0 to 15) */ #define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \ (slice * 0x04)) #define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0) #define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4) #define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8) #define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC) #define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0) #define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4) #define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8) #define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC) #define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0) #define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4) #define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8) #define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC) #define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0) #define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4) #define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8) #define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC) /* Slice data shadow registers (REG_SS0 to 15) */ #define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \ (slice * 0x04)) #define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100) #define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104) #define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108) #define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C) #define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110) #define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114) #define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118) #define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C) #define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120) #define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124) #define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128) #define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C) #define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130) #define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134) #define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138) #define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C) /* Reload registers (PRESET0 to 15) */ #define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \ (slice * 0x04)) #define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140) #define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144) #define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148) #define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C) #define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150) #define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154) #define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158) #define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C) #define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160) #define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164) #define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168) #define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C) #define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170) #define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174) #define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178) #define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C) /* Down counter registers (COUNT0 to 15) */ #define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \ (slice * 0x04)) #define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180) #define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184) #define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188) #define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C) #define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190) #define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194) #define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198) #define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C) #define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0) #define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4) #define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8) #define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC) #define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0) #define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4) #define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8) #define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC) /* Position registers (POS0 to 15) */ #define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \ (slice * 0x04)) #define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0) #define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4) #define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8) #define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC) #define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0) #define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4) #define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8) #define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC) #define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0) #define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4) #define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8) #define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC) #define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0) #define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4) #define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8) #define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC) /* Slice name to slice index mapping */ #define SGPIO_SLICE_A 0 #define SGPIO_SLICE_B 1 #define SGPIO_SLICE_C 2 #define SGPIO_SLICE_D 3 #define SGPIO_SLICE_E 4 #define SGPIO_SLICE_F 5 #define SGPIO_SLICE_G 6 #define SGPIO_SLICE_H 7 #define SGPIO_SLICE_I 8 #define SGPIO_SLICE_J 9 #define SGPIO_SLICE_K 10 #define SGPIO_SLICE_L 11 #define SGPIO_SLICE_M 12 #define SGPIO_SLICE_N 13 #define SGPIO_SLICE_O 14 #define SGPIO_SLICE_P 15 /* Mask for pattern match function of slice A */ #define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200) /* Mask for pattern match function of slice H */ #define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204) /* Mask for pattern match function of slice I */ #define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208) /* Mask for pattern match function of slice P */ #define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C) /* GPIO input status register */ #define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210) /* GPIO output control register */ #define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214) /* GPIO OE control register */ #define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218) /* Enables the slice COUNT counter */ #define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C) /* Disables the slice COUNT counter */ #define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220) /* Shift clock interrupt clear mask */ #define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00) /* Shift clock interrupt set mask */ #define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04) /* Shift clock interrupt enable */ #define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08) /* Shift clock interrupt status */ #define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C) /* Shift clock interrupt clear status */ #define SGPIO_CLR_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF10) /* Shift clock interrupt set status */ #define SGPIO_SET_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF14) /* Exchange clock interrupt clear mask */ #define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20) /* Exchange clock interrupt set mask */ #define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24) /* Exchange clock interrupt enable */ #define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28) /* Exchange clock interrupt status */ #define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C) /* Exchange clock interrupt clear status */ #define SGPIO_CLR_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF30) /* Exchange clock interrupt set status */ #define SGPIO_SET_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF34) /* Pattern match interrupt clear mask */ #define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40) /* Pattern match interrupt set mask */ #define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44) /* Pattern match interrupt enable */ #define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48) /* Pattern match interrupt status */ #define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C) /* Pattern match interrupt clear status */ #define SGPIO_CLR_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF50) /* Pattern match interrupt set status */ #define SGPIO_SET_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF54) /* Input interrupt clear mask */ #define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60) /* Input bit match interrupt set mask */ #define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64) /* Input bit match interrupt enable */ #define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68) /* Input bit match interrupt status */ #define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C) /* Input bit match interrupt clear status */ #define SGPIO_CLR_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF70) /* Input bit match interrupt set status */ #define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74) /* --- Common register fields ----------------------------------- */ /* TODO: Generate this stuff with the gen.py script as well! */ #define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0) #define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK \ (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) #define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) \ ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) #define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4) #define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK \ (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) #define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) \ ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) #define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0) #define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK \ (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) #define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) \ ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) #define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1) #define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK \ (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) #define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) \ ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) #define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3) #define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK \ (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) #define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) \ ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) #define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5) #define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK \ (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) #define SGPIO_MUX_CFG_QUALIFIER_MODE(x) \ ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) #define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7) #define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK \ (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) #define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) \ ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) #define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9) #define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK \ (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) #define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) \ ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) #define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11) #define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK \ (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) #define SGPIO_MUX_CFG_CONCAT_ENABLE(x) \ ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) #define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12) #define SGPIO_MUX_CFG_CONCAT_ORDER_MASK \ (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) #define SGPIO_MUX_CFG_CONCAT_ORDER(x) \ ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) #define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0) #define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK \ (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) \ ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1) #define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK \ (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) \ ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2) #define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK \ (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) \ ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3) #define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK \ (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) #define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) \ ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) #define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4) #define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK \ (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) \ ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6) #define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK \ (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) \ ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8) #define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK \ (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) #define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) \ ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) #define SGPIO_POS_POS_SHIFT (0) #define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT) #define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT) #define SGPIO_POS_POS_RESET_SHIFT (8) #define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT) #define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT) /* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ /* --- SGPIO_OUT_MUX_CFG[0..15] values ------------------------------------ */ /* P_OUT_CFG: Output control of output SGPIOn */ #define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT (0) #define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_MASK \ (0xf << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) #define SGPIO_OUT_MUX_CFGx_P_OUT_CFG(x) \ ((x) << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ #define SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT (4) #define SGPIO_OUT_MUX_CFGx_P_OE_CFG_MASK \ (0x7 << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) #define SGPIO_OUT_MUX_CFGx_P_OE_CFG(x) \ ((x) << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) /* --- SGPIO_MUX_CFG[0..15] values ---------------------------------------- */ /* EXT_CLK_ENABLE: Select clock signal */ #define SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT (0) #define SGPIO_MUX_CFGx_EXT_CLK_ENABLE \ (1 << SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT) /* CLK_SOURCE_PIN_MODE: Select source clock pin */ #define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT (1) #define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_MASK \ (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) #define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE(x) \ ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) /* CLK_SOURCE_SLICE_MODE: Select clock source slice */ #define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3) #define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \ (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) #define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) \ ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ #define SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT (5) #define SGPIO_MUX_CFGx_QUALIFIER_MODE_MASK \ (0x3 << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) #define SGPIO_MUX_CFGx_QUALIFIER_MODE(x) \ ((x) << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) /* QUALIFIER_PIN_MODE: Select qualifier pin */ #define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT (7) #define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_MASK \ (0x3 << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) #define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE(x) \ ((x) << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) /* QUALIFIER_SLICE_MODE: Select qualifier slice */ #define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT (9) #define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_MASK \ (0x3 << SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT) #define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE(x) \ ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) /* CONCAT_ENABLE: Enable concatenation */ #define SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT (11) #define SGPIO_MUX_CFGx_CONCAT_ENABLE \ (1 << SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT) /* CONCAT_ORDER: Select concatenation order */ #define SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT (12) #define SGPIO_MUX_CFGx_CONCAT_ORDER_MASK \ (0x3 << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) #define SGPIO_MUX_CFGx_CONCAT_ORDER(x) \ ((x) << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) /* --- SGPIO_SLICE_MUX_CFG[0..15] values ---------------------------------- */ /* MATCH_MODE: Match mode */ #define SGPIO_SLICE_MUX_CFGx_MATCH_MODE_SHIFT (0) #define SGPIO_SLICE_MUX_CFGx_MATCH_MODE \ (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT) /* CLK_CAPTURE_MODE: Capture clock mode */ #define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT (1) #define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE \ (1 << SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT) /* CLKGEN_MODE: Clock generation mode */ #define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT (2) #define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE \ (1 << SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT) /* INV_OUT_CLK: Invert output clock */ #define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT (3) #define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK \ (1 << SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT) /* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ #define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT (4) #define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_MASK \ (0x3 << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE(x) \ ((x) << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) /* PARALLEL_MODE: Parallel mode */ #define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT (6) #define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_MASK \ (0x3 << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) #define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE(x) \ ((x) << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) /* INV_QUALIFIER: Inversion qualifier */ #define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT (8) #define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER \ (1 << SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT) /* --- SGPIO_POS[0..15] values -------------------------------------------- */ /* POS: Each time COUNT reaches 0x0 POS counts down */ #define SGPIO_POSx_POS_SHIFT (0) #define SGPIO_POSx_POS_MASK (0xff << SGPIO_POSx_POS_SHIFT) #define SGPIO_POSx_POS(x) ((x) << SGPIO_POSx_POS_SHIFT) /* POS_RESET: Reload value for POS after POS reaches 0x0 */ #define SGPIO_POSx_POS_RESET_SHIFT (8) #define SGPIO_POSx_POS_RESET_MASK (0xff << SGPIO_POSx_POS_RESET_SHIFT) #define SGPIO_POSx_POS_RESET(x) ((x) << SGPIO_POSx_POS_RESET_SHIFT) /* SGPIO structure for faster/better code generation (especially when optimized * with -O2/-O3) */ /* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3 * September 2012 */ typedef struct { /* Pin multiplexer configuration registers. RW */ volatile uint32_t OUT_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. RW */ volatile uint32_t SGPIO_MUX_CFG[16]; /* Slice multiplexer configuration registers. RW */ volatile uint32_t SLICE_MUX_CFG[16]; /* Slice data registers. RW */ volatile uint32_t REG[16]; /* Slice data shadow registers. Each time POS reaches 0x0 the contents * of REG_SS is exchanged with the content of REG. RW */ volatile uint32_t REG_SS[16]; /* Reload registers. Counter reload value; loaded when COUNT reaches * 0x0 RW */ volatile uint32_t PRESET[16]; /* Down counter registers, counts down each shift clock cycle. RW */ volatile uint32_t COUNT[16]; /* Position registers. POS Each time COUNT reaches 0x0 POS counts down. * POS_RESET Reload value for POS after POS reaches 0x0. RW */ volatile uint32_t POS[16]; /* Slice A mask register. Mask for pattern match function of slice A. * RW */ volatile uint32_t MASK_A; /* Slice H mask register. Mask for pattern match function of slice H. * RW */ volatile uint32_t MASK_H; /* Slice I mask register. Mask for pattern match function of slice I. * RW */ volatile uint32_t MASK_I; /* Slice P mask register. Mask for pattern match function of slice P. * RW */ volatile uint32_t MASK_P; /* GPIO input status register. R */ volatile uint32_t GPIO_INREG; /* GPIO output control register. RW */ volatile uint32_t GPIO_OUTREG; /* GPIO output enable register. RW */ volatile uint32_t GPIO_OENREG; /* Slice count enable register. RW */ volatile uint32_t CTRL_ENABLE; /* Slice count disable register. RW */ volatile uint32_t CTRL_DISABLE; volatile uint32_t RES0[823]; /* Shift clock interrupt clear mask register. W */ volatile uint32_t CLR_EN_0; /* Shift clock interrupt set mask register. W */ volatile uint32_t SET_EN_0; /* Shift clock interrupt enable register. R */ volatile uint32_t ENABLE_0; /* Shift clock interrupt status register. R */ volatile uint32_t STATUS_0; /* Shift clock interrupt clear status register. W */ volatile uint32_t CLR_STATUS_0; /* Shift clock interrupt set status register. W */ volatile uint32_t SET_STATUS_0; volatile uint32_t RES1[2]; /* Exchange clock interrupt clear mask register. W */ volatile uint32_t CLR_EN_1; /* Exchange clock interrupt set mask register. W */ volatile uint32_t SET_EN_1; /* Exchange clock interrupt enable. R */ volatile uint32_t ENABLE_1; /* Exchange clock interrupt status register. R */ volatile uint32_t STATUS_1; /* Exchange clock interrupt clear status register. W */ volatile uint32_t CLR_STATUS_1; /* Exchange clock interrupt set status register. W */ volatile uint32_t SET_STATUS_1; volatile uint32_t RES2[2]; /* Pattern match interrupt clear mask register. W */ volatile uint32_t CLR_EN_2; /* Pattern match interrupt set mask register. W */ volatile uint32_t SET_EN_2; /* Pattern match interrupt enable register. R */ volatile uint32_t ENABLE_2; /* Pattern match interrupt status register. R */ volatile uint32_t STATUS_2; /* Pattern match interrupt clear status register. W */ volatile uint32_t CLR_STATUS_2; /* Pattern match interrupt set status register. W */ volatile uint32_t SET_STATUS_2; volatile uint32_t RES3[2]; /* Input interrupt clear mask register. W */ volatile uint32_t CLR_EN_3; /* Input bit match interrupt set mask register. W */ volatile uint32_t SET_EN_3; /* Input bit match interrupt enable register. R */ volatile uint32_t ENABLE_3; /* Input bit match interrupt status register. R */ volatile uint32_t STATUS_3; /* Input bit match interrupt clear status register. W */ volatile uint32_t CLR_STATUS_3; /* Input bit match interrupt set status register. W */ volatile uint32_t SET_STATUS_3; } sgpio_t; /* Global access to SGPIO structure */ #define SGPIO ((sgpio_t*)SGPIO_PORT_BASE) /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/spi.h000066400000000000000000000137541435536612600234320ustar00rootroot00000000000000/** @defgroup spi_defines Serial Peripheral Interface Defines @brief Defined Constants and Types for the LPC43xx Serial Peripheral Interface @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2013 Jared Boone @date 15 November 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_SPI_H #define LPC43XX_SPI_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* SPI port base addresses (for convenience) */ #define SPI (SPI_PORT_BASE) /* --- SPI registers ----------------------------------------------------- */ /* Control Register */ #define SPI_CR MMIO32(SPI + 0x000) /* Status Register */ #define SPI_SR MMIO32(SPI + 0x004) /* Data Register */ #define SPI_DR MMIO32(SPI + 0x008) /* Clock Counter Register */ #define SPI_CCR MMIO32(SPI + 0x00C) /* Test Control Register */ #define SPI_TCR MMIO32(SPI + 0x010) /* Test Status Register */ #define SPI_TSR MMIO32(SPI + 0x014) /* Interrupt Flag */ #define SPI_INT MMIO32(SPI + 0x01C) /* --- SPI_CR values -------------------------------------------- */ /* BITENABLE: Bit length enable */ #define SPI_CR_BITENABLE_SHIFT (2) #define SPI_CR_BITENABLE_MASK (0x1 << SPI_CR_BITENABLE_SHIFT) #define SPI_CR_BITENABLE(x) ((x) << SPI_CR_BITENABLE_SHIFT) /* CPHA: Clock phase control */ #define SPI_CR_CPHA_SHIFT (3) #define SPI_CR_CPHA_MASK (0x1 << SPI_CR_CPHA_SHIFT) #define SPI_CR_CPHA(x) ((x) << SPI_CR_CPHA_SHIFT) /* CPOL: Clock polarity control */ #define SPI_CR_CPOL_SHIFT (4) #define SPI_CR_CPOL_MASK (0x1 << SPI_CR_CPOL_SHIFT) #define SPI_CR_CPOL(x) ((x) << SPI_CR_CPOL_SHIFT) /* MSTR: Master mode select */ #define SPI_CR_MSTR_SHIFT (5) #define SPI_CR_MSTR_MASK (0x1 << SPI_CR_MSTR_SHIFT) #define SPI_CR_MSTR(x) ((x) << SPI_CR_MSTR_SHIFT) /* LSBF: LSB first */ #define SPI_CR_LSBF_SHIFT (6) #define SPI_CR_LSBF_MASK (0x1 << SPI_CR_LSBF_SHIFT) #define SPI_CR_LSBF(x) ((x) << SPI_CR_LSBF_SHIFT) /* SPIE: Serial peripheral interrupt enable */ #define SPI_CR_SPIE_SHIFT (7) #define SPI_CR_SPIE_MASK (0x1 << SPI_CR_SPIE_SHIFT) #define SPI_CR_SPIE(x) ((x) << SPI_CR_SPIE_SHIFT) /* BITS: Bits per transfer */ #define SPI_CR_BITS_SHIFT (8) #define SPI_CR_BITS_MASK (0xf << SPI_CR_BITS_SHIFT) #define SPI_CR_BITS(x) ((x) << SPI_CR_BITS_SHIFT) /* SPIF: Interrupt */ #define SPI_CR_SPIF_SHIFT (0) #define SPI_CR_SPIF_MASK (0x1 << SPI_CR_SPIF_SHIFT) #define SPI_CR_SPIF(x) ((x) << SPI_CR_SPIF_SHIFT) /* --- SPI_SR values -------------------------------------------- */ /* ABRT: Slave abort */ #define SPI_SR_ABRT_SHIFT (3) #define SPI_SR_ABRT_MASK (0x1 << SPI_SR_ABRT_SHIFT) #define SPI_SR_ABRT(x) ((x) << SPI_SR_ABRT_SHIFT) /* MODF: Mode fault */ #define SPI_SR_MODF_SHIFT (4) #define SPI_SR_MODF_MASK (0x1 << SPI_SR_MODF_SHIFT) #define SPI_SR_MODF(x) ((x) << SPI_SR_MODF_SHIFT) /* ROVR: Read overrun */ #define SPI_SR_ROVR_SHIFT (5) #define SPI_SR_ROVR_MASK (0x1 << SPI_SR_ROVR_SHIFT) #define SPI_SR_ROVR(x) ((x) << SPI_SR_ROVR_SHIFT) /* WCOL: Write collision */ #define SPI_SR_WCOL_SHIFT (6) #define SPI_SR_WCOL_MASK (0x1 << SPI_SR_WCOL_SHIFT) #define SPI_SR_WCOL(x) ((x) << SPI_SR_WCOL_SHIFT) /* SPIF: Transfer complete */ #define SPI_SR_SPIF_SHIFT (7) #define SPI_SR_SPIF_MASK (0x1 << SPI_SR_SPIF_SHIFT) #define SPI_SR_SPIF(x) ((x) << SPI_SR_SPIF_SHIFT) /* --- SPI_DR values -------------------------------------------- */ /* DATA: Bi-directional data port */ #define SPI_DR_DATA_SHIFT (0) #define SPI_DR_DATA_MASK (0xffff << SPI_DR_DATA_SHIFT) #define SPI_DR_DATA(x) ((x) << SPI_DR_DATA_SHIFT) /* --- SPI_CCR values ------------------------------------------- */ /* COUNTER: Clock counter setting */ #define SPI_CCR_COUNTER_SHIFT (0) #define SPI_CCR_COUNTER_MASK (0xff << SPI_CCR_COUNTER_SHIFT) #define SPI_CCR_COUNTER(x) ((x) << SPI_CCR_COUNTER_SHIFT) /* --- SPI_TCR values ------------------------------------------- */ /* TEST: Test mode */ #define SPI_TCR_TEST_SHIFT (1) #define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) #define SPI_TCR_TEST(x) ((x) << SPI_TCR_TEST_SHIFT) /* --- SPI_TSR values ------------------------------------------- */ /* ABRT: Slave abort */ #define SPI_TSR_ABRT_SHIFT (3) #define SPI_TSR_ABRT_MASK (0x1 << SPI_TSR_ABRT_SHIFT) #define SPI_TSR_ABRT(x) ((x) << SPI_TSR_ABRT_SHIFT) /* MODF: Mode fault */ #define SPI_TSR_MODF_SHIFT (4) #define SPI_TSR_MODF_MASK (0x1 << SPI_TSR_MODF_SHIFT) #define SPI_TSR_MODF(x) ((x) << SPI_TSR_MODF_SHIFT) /* ROVR: Read overrun */ #define SPI_TSR_ROVR_SHIFT (5) #define SPI_TSR_ROVR_MASK (0x1 << SPI_TSR_ROVR_SHIFT) #define SPI_TSR_ROVR(x) ((x) << SPI_TSR_ROVR_SHIFT) /* WCOL: Write collision */ #define SPI_TSR_WCOL_SHIFT (6) #define SPI_TSR_WCOL_MASK (0x1 << SPI_TSR_WCOL_SHIFT) #define SPI_TSR_WCOL(x) ((x) << SPI_TSR_WCOL_SHIFT) /* SPIF: Transfer complete */ #define SPI_TSR_SPIF_SHIFT (7) #define SPI_TSR_SPIF_MASK (0x1 << SPI_TSR_SPIF_SHIFT) #define SPI_TSR_SPIF(x) ((x) << SPI_TSR_SPIF_SHIFT) BEGIN_DECLS /*****/ END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/spifi.h000066400000000000000000000224331435536612600237430ustar00rootroot00000000000000/** @defgroup spifi_defines SPI Flash Interface (SPIFI) Defines @brief Defined Constants and Types for the LPC43xx SPI Flash Interface (SPIFI) @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2014 Jared Boone @date 16 January 2014 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2014 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_SPIFI_H #define LPC43XX_SPIFI_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* SPIFI port base addresses (for convenience) */ #define SPIFI (SPIFI_BASE) /* --- SPIFI registers ----------------------------------------------------- */ /* Control Register */ #define SPIFI_CTRL MMIO32(SPIFI_BASE + 0x000) /* Command Register */ #define SPIFI_CMD MMIO32(SPIFI_BASE + 0x004) /* Address Register */ #define SPIFI_ADDR MMIO32(SPIFI_BASE + 0x008) /* Intermediate Data Register */ #define SPIFI_IDATA MMIO32(SPIFI_BASE + 0x00C) /* Cache Limit Register */ #define SPIFI_CLIMIT MMIO32(SPIFI_BASE + 0x010) /* Data Register */ #define SPIFI_DATA MMIO32(SPIFI_BASE + 0x014) #define SPIFI_DATA_BYTE MMIO8(SPIFI_BASE + 0x014) /* Memory Command Register */ #define SPIFI_MCMD MMIO32(SPIFI_BASE + 0x018) /* Status Register */ #define SPIFI_STAT MMIO32(SPIFI_BASE + 0x01C) /* --- SPIFI_CTRL values ---------------------------------------- */ /* TIMEOUT: Memory mode idle timeout */ #define SPIFI_CTRL_TIMEOUT_SHIFT (0) #define SPIFI_CTRL_TIMEOUT_MASK (0xffff << SPIFI_CTRL_TIMEOUT_SHIFT) #define SPIFI_CTRL_TIMEOUT(x) ((x) << SPIFI_CTRL_TIMEOUT_SHIFT) /* CSHIGH: Minimum CS# high time */ #define SPIFI_CTRL_CSHIGH_SHIFT (16) #define SPIFI_CTRL_CSHIGH_MASK (0xf << SPIFI_CTRL_CSHIGH_SHIFT) #define SPIFI_CTRL_CSHIGH(x) ((x) << SPIFI_CTRL_CSHIGH_SHIFT) /* D_PRFTCH_DIS: Disable speculative prefetch */ #define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21) #define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x1 << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT) #define SPIFI_CTRL_D_PRFTCH_DIS(x) ((x) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT) /* INTEN: Enable command end interrupt */ #define SPIFI_CTRL_INTEN_SHIFT (22) #define SPIFI_CTRL_INTEN_MASK (0x1 << SPIFI_CTRL_INTEN_SHIFT) #define SPIFI_CTRL_INTEN(x) ((x) << SPIFI_CTRL_INTEN_SHIFT) /* MODE3: SPI mode 3 select */ #define SPIFI_CTRL_MODE3_SHIFT (23) #define SPIFI_CTRL_MODE3_MASK (0x1 << SPIFI_CTRL_MODE3_SHIFT) #define SPIFI_CTRL_MODE3(x) ((x) << SPIFI_CTRL_MODE3_SHIFT) /* PRFTCH_DIS: Disable prefetching of cache lines */ #define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27) #define SPIFI_CTRL_PRFTCH_DIS_MASK (0x1 << SPIFI_CTRL_PRFTCH_DIS_SHIFT) #define SPIFI_CTRL_PRFTCH_DIS(x) ((x) << SPIFI_CTRL_PRFTCH_DIS_SHIFT) /* DUAL: Select dual protocol */ #define SPIFI_CTRL_DUAL_SHIFT (28) #define SPIFI_CTRL_DUAL_MASK (0x1 << SPIFI_CTRL_DUAL_SHIFT) #define SPIFI_CTRL_DUAL(x) ((x) << SPIFI_CTRL_DUAL_SHIFT) /* RFCLK: Read data on falling edge */ #define SPIFI_CTRL_RFCLK_SHIFT (29) #define SPIFI_CTRL_RFCLK_MASK (0x1 << SPIFI_CTRL_RFCLK_SHIFT) #define SPIFI_CTRL_RFCLK(x) ((x) << SPIFI_CTRL_RFCLK_SHIFT) /* FBCLK: Feedback clock select */ #define SPIFI_CTRL_FBCLK_SHIFT (30) #define SPIFI_CTRL_FBCLK_MASK (0x1 << SPIFI_CTRL_FBCLK_SHIFT) #define SPIFI_CTRL_FBCLK(x) ((x) << SPIFI_CTRL_FBCLK_SHIFT) /* DMAEN: DMA request output enable */ #define SPIFI_CTRL_DMAEN_SHIFT (31) #define SPIFI_CTRL_DMAEN_MASK (0x1 << SPIFI_CTRL_DMAEN_SHIFT) #define SPIFI_CTRL_DMAEN(x) ((x) << SPIFI_CTRL_DMAEN_SHIFT) /* --- SPIFI_CMD values ----------------------------------------- */ /* DATALEN: Data bytes in command */ #define SPIFI_CMD_DATALEN_SHIFT (0) #define SPIFI_CMD_DATALEN_MASK (0x3fff << SPIFI_CMD_DATALEN_SHIFT) #define SPIFI_CMD_DATALEN(x) ((x) << SPIFI_CMD_DATALEN_SHIFT) /* POLL: Poll at end of command */ #define SPIFI_CMD_POLL_SHIFT (14) #define SPIFI_CMD_POLL_MASK (0x1 << SPIFI_CMD_POLL_SHIFT) #define SPIFI_CMD_POLL(x) ((x) << SPIFI_CMD_POLL_SHIFT) /* DOUT: Data output to serial flash */ #define SPIFI_CMD_DOUT_SHIFT (15) #define SPIFI_CMD_DOUT_MASK (0x1 << SPIFI_CMD_DOUT_SHIFT) #define SPIFI_CMD_DOUT(x) ((x) << SPIFI_CMD_DOUT_SHIFT) /* INTLEN: Intermediate bytes before data */ #define SPIFI_CMD_INTLEN_SHIFT (16) #define SPIFI_CMD_INTLEN_MASK (0x7 << SPIFI_CMD_INTLEN_SHIFT) #define SPIFI_CMD_INTLEN(x) ((x) << SPIFI_CMD_INTLEN_SHIFT) /* FIELDFORM: Form of command fields */ #define SPIFI_CMD_FIELDFORM_SHIFT (19) #define SPIFI_CMD_FIELDFORM_MASK (0x3 << SPIFI_CMD_FIELDFORM_SHIFT) #define SPIFI_CMD_FIELDFORM(x) ((x) << SPIFI_CMD_FIELDFORM_SHIFT) /* FRAMEFORM: Form of the opcode/address fields */ #define SPIFI_CMD_FRAMEFORM_SHIFT (21) #define SPIFI_CMD_FRAMEFORM_MASK (0x7 << SPIFI_CMD_FRAMEFORM_SHIFT) #define SPIFI_CMD_FRAMEFORM(x) ((x) << SPIFI_CMD_FRAMEFORM_SHIFT) /* OPCODE: Command opcode */ #define SPIFI_CMD_OPCODE_SHIFT (24) #define SPIFI_CMD_OPCODE_MASK (0xff << SPIFI_CMD_OPCODE_SHIFT) #define SPIFI_CMD_OPCODE(x) ((x) << SPIFI_CMD_OPCODE_SHIFT) /* --- SPIFI_ADDR values ---------------------------------------- */ /* ADDRESS: Address field value */ #define SPIFI_ADDR_ADDRESS_SHIFT (0) #define SPIFI_ADDR_ADDRESS_MASK (0xffffffff << SPIFI_ADDR_ADDRESS_SHIFT) #define SPIFI_ADDR_ADDRESS(x) ((x) << SPIFI_ADDR_ADDRESS_SHIFT) /* --- SPIFI_IDATA values --------------------------------------- */ /* IDATA: Intermediate bytes value */ #define SPIFI_IDATA_IDATA_SHIFT (0) #define SPIFI_IDATA_IDATA_MASK (0xffffffff << SPIFI_IDATA_IDATA_SHIFT) #define SPIFI_IDATA_IDATA(x) ((x) << SPIFI_IDATA_IDATA_SHIFT) /* --- SPIFI_CLIMIT values -------------------------------------- */ /* CLIMIT: Upper limit of cacheable memory */ #define SPIFI_CLIMIT_CLIMIT_SHIFT (0) #define SPIFI_CLIMIT_CLIMIT_MASK (0xffffffff << SPIFI_CLIMIT_CLIMIT_SHIFT) #define SPIFI_CLIMIT_CLIMIT(x) ((x) << SPIFI_CLIMIT_CLIMIT_SHIFT) /* --- SPIFI_DATA values ---------------------------------------- */ /* DATA: Input or output data */ #define SPIFI_DATA_DATA_SHIFT (0) #define SPIFI_DATA_DATA_MASK (0xffffffff << SPIFI_DATA_DATA_SHIFT) #define SPIFI_DATA_DATA(x) ((x) << SPIFI_DATA_DATA_SHIFT) /* --- SPIFI_MCMD values ---------------------------------------- */ /* POLL: Must be zero */ #define SPIFI_MCMD_POLL_SHIFT (14) #define SPIFI_MCMD_POLL_MASK (0x1 << SPIFI_MCMD_POLL_SHIFT) #define SPIFI_MCMD_POLL(x) ((x) << SPIFI_MCMD_POLL_SHIFT) /* DOUT: Must be zero */ #define SPIFI_MCMD_DOUT_SHIFT (15) #define SPIFI_MCMD_DOUT_MASK (0x1 << SPIFI_MCMD_DOUT_SHIFT) #define SPIFI_MCMD_DOUT(x) ((x) << SPIFI_MCMD_DOUT_SHIFT) /* INTLEN: Intermediate bytes before data */ #define SPIFI_MCMD_INTLEN_SHIFT (16) #define SPIFI_MCMD_INTLEN_MASK (0x7 << SPIFI_MCMD_INTLEN_SHIFT) #define SPIFI_MCMD_INTLEN(x) ((x) << SPIFI_MCMD_INTLEN_SHIFT) /* FIELDFORM: Form of command fields */ #define SPIFI_MCMD_FIELDFORM_SHIFT (19) #define SPIFI_MCMD_FIELDFORM_MASK (0x3 << SPIFI_MCMD_FIELDFORM_SHIFT) #define SPIFI_MCMD_FIELDFORM(x) ((x) << SPIFI_MCMD_FIELDFORM_SHIFT) /* FRAMEFORM: Form of the opcode/address fields */ #define SPIFI_MCMD_FRAMEFORM_SHIFT (21) #define SPIFI_MCMD_FRAMEFORM_MASK (0x7 << SPIFI_MCMD_FRAMEFORM_SHIFT) #define SPIFI_MCMD_FRAMEFORM(x) ((x) << SPIFI_MCMD_FRAMEFORM_SHIFT) /* OPCODE: Command opcode */ #define SPIFI_MCMD_OPCODE_SHIFT (24) #define SPIFI_MCMD_OPCODE_MASK (0xff << SPIFI_MCMD_OPCODE_SHIFT) #define SPIFI_MCMD_OPCODE(x) ((x) << SPIFI_MCMD_OPCODE_SHIFT) /* --- SPIFI_STAT values ---------------------------------------- */ /* MCINIT: Memory command initialized */ #define SPIFI_STAT_MCINIT_SHIFT (0) #define SPIFI_STAT_MCINIT_MASK (0x1 << SPIFI_STAT_MCINIT_SHIFT) #define SPIFI_STAT_MCINIT(x) ((x) << SPIFI_STAT_MCINIT_SHIFT) /* CMD: Command active */ #define SPIFI_STAT_CMD_SHIFT (1) #define SPIFI_STAT_CMD_MASK (0x1 << SPIFI_STAT_CMD_SHIFT) #define SPIFI_STAT_CMD(x) ((x) << SPIFI_STAT_CMD_SHIFT) /* RESET: Abort current command/memory mode */ #define SPIFI_STAT_RESET_SHIFT (4) #define SPIFI_STAT_RESET_MASK (0x1 << SPIFI_STAT_RESET_SHIFT) #define SPIFI_STAT_RESET(x) ((x) << SPIFI_STAT_RESET_SHIFT) /* INTRQ: Interrupt request status */ #define SPIFI_STAT_INTRQ_SHIFT (5) #define SPIFI_STAT_INTRQ_MASK (0x1 << SPIFI_STAT_INTRQ_SHIFT) #define SPIFI_STAT_INTRQ(x) ((x) << SPIFI_STAT_INTRQ_SHIFT) /* VERSION: Peripheral hardware version */ #define SPIFI_STAT_VERSION_SHIFT (24) #define SPIFI_STAT_VERSION_MASK (0xff << SPIFI_STAT_VERSION_SHIFT) #define SPIFI_STAT_VERSION(x) ((x) << SPIFI_STAT_VERSION_SHIFT) BEGIN_DECLS END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/ssp.h000066400000000000000000000137121435536612600234360ustar00rootroot00000000000000/** @defgroup ssp_defines Synchronous Serial Port @brief Defined Constants and Types for the LPC43xx Synchronous Serial Port @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_SSP_H #define LPC43XX_SSP_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* SSP port base addresses (for convenience) */ #define SSP0 SSP0_BASE #define SSP1 SSP1_BASE /* --- SSP registers ------------------------------------------------------- */ /* Control Register 0 */ #define SSP_CR0(port) MMIO32(port + 0x000) #define SSP0_CR0 SSP_CR0(SSP0) #define SSP1_CR0 SSP_CR0(SSP1) /* Control Register 1 */ #define SSP_CR1(port) MMIO32(port + 0x004) #define SSP0_CR1 SSP_CR1(SSP0) #define SSP1_CR1 SSP_CR1(SSP1) /* Data Register */ #define SSP_DR(port) MMIO32(port + 0x008) #define SSP0_DR SSP_DR(SSP0) #define SSP1_DR SSP_DR(SSP1) /* Status Register */ #define SSP_SR(port) MMIO32(port + 0x00C) #define SSP0_SR SSP_SR(SSP0) #define SSP1_SR SSP_SR(SSP1) #define SSP_SR_TFE BIT0 #define SSP_SR_TNF BIT1 #define SSP_SR_RNE BIT2 #define SSP_SR_RFF BIT3 #define SSP_SR_BSY BIT4 /* Clock Prescale Register */ #define SSP_CPSR(port) MMIO32(port + 0x010) #define SSP0_CPSR SSP_CPSR(SSP0) #define SSP1_CPSR SSP_CPSR(SSP1) /* Interrupt Mask Set and Clear Register */ #define SSP_IMSC(port) MMIO32(port + 0x014) #define SSP0_IMSC SSP_IMSC(SSP0) #define SSP1_IMSC SSP_IMSC(SSP1) /* Raw Interrupt Status Register */ #define SSP_RIS(port) MMIO32(port + 0x018) #define SSP0_RIS SSP_RIS(SSP0) #define SSP1_RIS SSP_RIS(SSP1) /* Masked Interrupt Status Register */ #define SSP_MIS(port) MMIO32(port + 0x01C) #define SSP0_MIS SSP_MIS(SSP0) #define SSP1_MIS SSP_MIS(SSP1) /* SSPICR Interrupt Clear Register */ #define SSP_ICR(port) MMIO32(port + 0x020) #define SSP0_ICR SSP_ICR(SSP0) #define SSP1_ICR SSP_ICR(SSP1) /* SSP1 DMA control register */ #define SSP_DMACR(port) MMIO32(port + 0x024) #define SSP0_DMACR SSP_DMACR(SSP0) #define SSP1_DMACR SSP_DMACR(SSP1) /* RXDMAE: Receive DMA enable */ #define SSP_DMACR_RXDMAE 0x1 /* RXDMAE: Transmit DMA enable */ #define SSP_DMACR_TXDMAE 0x2 typedef enum { SSP0_NUM = 0x0, SSP1_NUM = 0x1 } ssp_num_t; /* * SSP Control Register 0 */ /* SSP Data Size Bits 0 to 3 */ typedef enum { SSP_DATA_4BITS = 0x3, SSP_DATA_5BITS = 0x4, SSP_DATA_6BITS = 0x5, SSP_DATA_7BITS = 0x6, SSP_DATA_8BITS = 0x7, SSP_DATA_9BITS = 0x8, SSP_DATA_10BITS = 0x9, SSP_DATA_11BITS = 0xA, SSP_DATA_12BITS = 0xB, SSP_DATA_13BITS = 0xC, SSP_DATA_14BITS = 0xD, SSP_DATA_15BITS = 0xE, SSP_DATA_16BITS = 0xF } ssp_datasize_t; /* SSP Frame Format/Type Bits 4 & 5 */ typedef enum { SSP_FRAME_SPI = 0x00, SSP_FRAME_TI = BIT4, SSP_FRAM_MICROWIRE = BIT5 } ssp_frame_format_t; /* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */ typedef enum { SSP_CPOL_0_CPHA_0 = 0x0, SSP_CPOL_1_CPHA_0 = BIT6, SSP_CPOL_0_CPHA_1 = BIT7, SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) } ssp_cpol_cpha_t; /* * SSP Control Register 1 */ /* SSP Mode Bit0 */ typedef enum { SSP_MODE_NORMAL = 0x0, SSP_MODE_LOOPBACK = BIT0 } ssp_mode_t; /* SSP Enable Bit1 */ #define SSP_ENABLE BIT1 /* SSP Master/Slave Mode Bit2 */ typedef enum { SSP_MASTER = 0x0, SSP_SLAVE = BIT2 } ssp_master_slave_t; /* * SSP Slave Output Disable Bit3 * Slave Output Disable. This bit is relevant only in slave mode * (MS = 1). If it is 1, this blocks this SSP controller from driving the * transmit data line (MISO). */ typedef enum { SSP_SLAVE_OUT_ENABLE = 0x0, SSP_SLAVE_OUT_DISABLE = BIT3 } ssp_slave_option_t; /* This option is relevant only in slave mode */ BEGIN_DECLS void ssp_disable(ssp_num_t ssp_num); /* * SSP Init * clk_prescale shall be in range 2 to 254 (even number only). * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, * SCR=serial_clock_rate */ void ssp_init(ssp_num_t ssp_num, ssp_datasize_t data_size, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, uint8_t serial_clock_rate, uint8_t clk_prescale, ssp_mode_t mode, ssp_master_slave_t master_slave, ssp_slave_option_t slave_option); uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data); END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/timer.h000066400000000000000000000260021435536612600237450ustar00rootroot00000000000000/** @defgroup timer_defines Timer @brief Defined Constants and Types for the LPC43xx timer @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_TIMER_H #define LPC43XX_TIMER_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* Timer base addresses */ #define TIMER0 TIMER0_BASE #define TIMER1 TIMER1_BASE #define TIMER2 TIMER2_BASE #define TIMER3 TIMER3_BASE /* --- Timer registers ----------------------------------------------------- */ /* Interrupt Register */ #define TIMER_IR(timer) MMIO32(timer + 0x000) #define TIMER0_IR TIMER_IR(TIMER0) #define TIMER1_IR TIMER_IR(TIMER1) #define TIMER2_IR TIMER_IR(TIMER2) #define TIMER3_IR TIMER_IR(TIMER3) /* Timer Control Register */ #define TIMER_TCR(timer) MMIO32(timer + 0x004) #define TIMER0_TCR TIMER_TCR(TIMER0) #define TIMER1_TCR TIMER_TCR(TIMER1) #define TIMER2_TCR TIMER_TCR(TIMER2) #define TIMER3_TCR TIMER_TCR(TIMER3) /* Timer Counter */ #define TIMER_TC(timer) MMIO32(timer + 0x008) #define TIMER0_TC TIMER_TC(TIMER0) #define TIMER1_TC TIMER_TC(TIMER1) #define TIMER2_TC TIMER_TC(TIMER2) #define TIMER3_TC TIMER_TC(TIMER3) /* Prescale Register */ #define TIMER_PR(timer) MMIO32(timer + 0x00C) #define TIMER0_PR TIMER_PR(TIMER0) #define TIMER1_PR TIMER_PR(TIMER1) #define TIMER2_PR TIMER_PR(TIMER2) #define TIMER3_PR TIMER_PR(TIMER3) /* Prescale Counter */ #define TIMER_PC(timer) MMIO32(timer + 0x010) #define TIMER0_PC TIMER_PC(TIMER0) #define TIMER1_PC TIMER_PC(TIMER1) #define TIMER2_PC TIMER_PC(TIMER2) #define TIMER3_PC TIMER_PC(TIMER3) /* Match Control Register */ #define TIMER_MCR(timer) MMIO32(timer + 0x014) #define TIMER0_MCR TIMER_MCR(TIMER0) #define TIMER1_MCR TIMER_MCR(TIMER1) #define TIMER2_MCR TIMER_MCR(TIMER2) #define TIMER3_MCR TIMER_MCR(TIMER3) /* Match Register 0 */ #define TIMER_MR0(timer) MMIO32(timer + 0x018) #define TIMER0_MR0 TIMER_MR0(TIMER0) #define TIMER1_MR0 TIMER_MR0(TIMER1) #define TIMER2_MR0 TIMER_MR0(TIMER2) #define TIMER3_MR0 TIMER_MR0(TIMER3) /* Match Register 1 */ #define TIMER_MR1(timer) MMIO32(timer + 0x01C) #define TIMER0_MR1 TIMER_MR1(TIMER0) #define TIMER1_MR1 TIMER_MR1(TIMER1) #define TIMER2_MR1 TIMER_MR1(TIMER2) #define TIMER3_MR1 TIMER_MR1(TIMER3) /* Match Register 2 */ #define TIMER_MR2(timer) MMIO32(timer + 0x020) #define TIMER0_MR2 TIMER_MR2(TIMER0) #define TIMER1_MR2 TIMER_MR2(TIMER1) #define TIMER2_MR2 TIMER_MR2(TIMER2) #define TIMER3_MR2 TIMER_MR2(TIMER3) /* Match Register 3 */ #define TIMER_MR3(timer) MMIO32(timer + 0x024) #define TIMER0_MR3 TIMER_MR3(TIMER0) #define TIMER1_MR3 TIMER_MR3(TIMER1) #define TIMER2_MR3 TIMER_MR3(TIMER2) #define TIMER3_MR3 TIMER_MR3(TIMER3) /* Capture Control Register */ #define TIMER_CCR(timer) MMIO32(timer + 0x028) #define TIMER0_CCR TIMER_CCR(TIMER0) #define TIMER1_CCR TIMER_CCR(TIMER1) #define TIMER2_CCR TIMER_CCR(TIMER2) #define TIMER3_CCR TIMER_CCR(TIMER3) /* Capture Register 0 */ #define TIMER_CR0(timer) MMIO32(timer + 0x02C) #define TIMER0_CR0 TIMER_CR0(TIMER0) #define TIMER1_CR0 TIMER_CR0(TIMER1) #define TIMER2_CR0 TIMER_CR0(TIMER2) #define TIMER3_CR0 TIMER_CR0(TIMER3) /* Capture Register 1 */ #define TIMER_CR1(timer) MMIO32(timer + 0x030) #define TIMER0_CR1 TIMER_CR1(TIMER0) #define TIMER1_CR1 TIMER_CR1(TIMER1) #define TIMER2_CR1 TIMER_CR1(TIMER2) #define TIMER3_CR1 TIMER_CR1(TIMER3) /* Capture Register 2 */ #define TIMER_CR2(timer) MMIO32(timer + 0x034) #define TIMER0_CR2 TIMER_CR2(TIMER0) #define TIMER1_CR2 TIMER_CR2(TIMER1) #define TIMER2_CR2 TIMER_CR2(TIMER2) #define TIMER3_CR2 TIMER_CR2(TIMER3) /* Capture Register 3 */ #define TIMER_CR3(timer) MMIO32(timer + 0x038) #define TIMER0_CR3 TIMER_CR3(TIMER0) #define TIMER1_CR3 TIMER_CR3(TIMER1) #define TIMER2_CR3 TIMER_CR3(TIMER2) #define TIMER3_CR3 TIMER_CR3(TIMER3) /* External Match Register */ #define TIMER_EMR(timer) MMIO32(timer + 0x03C) #define TIMER0_EMR TIMER_EMR(TIMER0) #define TIMER1_EMR TIMER_EMR(TIMER1) #define TIMER2_EMR TIMER_EMR(TIMER2) #define TIMER3_EMR TIMER_EMR(TIMER3) /* Count Control Register */ #define TIMER_CTCR(timer) MMIO32(timer + 0x070) #define TIMER0_CTCR TIMER_CTCR(TIMER0) #define TIMER1_CTCR TIMER_CTCR(TIMER1) #define TIMER2_CTCR TIMER_CTCR(TIMER2) #define TIMER3_CTCR TIMER_CTCR(TIMER3) /* --- TIMERx_IR values ----------------------------------------------------- */ #define TIMER_IR_MR0INT (1 << 0) #define TIMER_IR_MR1INT (1 << 1) #define TIMER_IR_MR2INT (1 << 2) #define TIMER_IR_MR3INT (1 << 3) #define TIMER_IR_CR0INT (1 << 4) #define TIMER_IR_CR1INT (1 << 5) #define TIMER_IR_CR2INT (1 << 6) #define TIMER_IR_CR3INT (1 << 7) /* --- TIMERx_TCR values --------------------------------------------------- */ #define TIMER_TCR_CEN (1 << 0) #define TIMER_TCR_CRST (1 << 1) /* --- TIMERx_MCR values --------------------------------------------------- */ #define TIMER_MCR_MR0I (1 << 0) #define TIMER_MCR_MR0R (1 << 1) #define TIMER_MCR_MR0S (1 << 2) #define TIMER_MCR_MR1I (1 << 3) #define TIMER_MCR_MR1R (1 << 4) #define TIMER_MCR_MR1S (1 << 5) #define TIMER_MCR_MR2I (1 << 6) #define TIMER_MCR_MR2R (1 << 7) #define TIMER_MCR_MR2S (1 << 8) #define TIMER_MCR_MR3I (1 << 9) #define TIMER_MCR_MR3R (1 << 10) #define TIMER_MCR_MR3S (1 << 11) /* --- TIMERx_MCR values --------------------------------------------------- */ #define TIMER_CCR_CAP0RE (1 << 0) #define TIMER_CCR_CAP0FE (1 << 1) #define TIMER_CCR_CAP0I (1 << 2) #define TIMER_CCR_CAP1RE (1 << 3) #define TIMER_CCR_CAP1FE (1 << 4) #define TIMER_CCR_CAP1I (1 << 5) #define TIMER_CCR_CAP2RE (1 << 6) #define TIMER_CCR_CAP2FE (1 << 7) #define TIMER_CCR_CAP2I (1 << 8) #define TIMER_CCR_CAP3RE (1 << 9) #define TIMER_CCR_CAP3FE (1 << 10) #define TIMER_CCR_CAP3I (1 << 11) /* --- TIMERx_EMR values --------------------------------------------------- */ #define TIMER_EMR_EM0 (1 << 0) #define TIMER_EMR_EM1 (1 << 1) #define TIMER_EMR_EM2 (1 << 2) #define TIMER_EMR_EM3 (1 << 3) #define TIMER_EMR_EMC0_SHIFT 4 #define TIMER_EMR_EMC0_MASK (0x3 << TIMER_EMR_EMC0_SHIFT) #define TIMER_EMR_EMC1_SHIFT 6 #define TIMER_EMR_EMC1_MASK (0x3 << TIMER_EMR_EMC1_SHIFT) #define TIMER_EMR_EMC2_SHIFT 8 #define TIMER_EMR_EMC2_MASK (0x3 << TIMER_EMR_EMC2_SHIFT) #define TIMER_EMR_EMC3_SHIFT 10 #define TIMER_EMR_EMC3_MASK (0x3 << TIMER_EMR_EMC3_SHIFT) #define TIMER_EMR_EMC_NOTHING 0x0 #define TIMER_EMR_EMC_CLEAR 0x1 #define TIMER_EMR_EMC_SET 0x2 #define TIMER_EMR_EMC_TOGGLE 0x3 /* --- TIMERx_CTCR values -------------------------------------------------- */ #define TIMER_CTCR_MODE_TIMER (0x0 << 0) #define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) #define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) #define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) #define TIMER_CTCR_MODE_MASK (0x3 << 0) #define TIMER_CTCR_CINSEL_CAPN_0 (0x0 << 2) #define TIMER_CTCR_CINSEL_CAPN_1 (0x1 << 2) #define TIMER_CTCR_CINSEL_CAPN_2 (0x2 << 2) #define TIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2) #define TIMER_CTCR_CINSEL_MASK (0x3 << 2) /* --- TIMER function prototypes ------------------------------------------- */ BEGIN_DECLS void timer_reset(uint32_t timer_peripheral); void timer_enable_counter(uint32_t timer_peripheral); void timer_disable_counter(uint32_t timer_peripheral); uint32_t timer_get_counter(uint32_t timer_peripheral); void timer_set_counter(uint32_t timer_peripheral, uint32_t count); uint32_t timer_get_prescaler(uint32_t timer_peripheral); void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); void timer_set_mode(uint32_t timer_peripheral, uint32_t mode); void timer_set_count_input(uint32_t timer_peripheral, uint32_t input); END_DECLS /**@}*/ #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/uart.h000066400000000000000000000430201435536612600235770ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_UART_H #define LPC43XX_UART_H #include #include #ifdef __cplusplus extern "C" { #endif /* --- Convenience macros -------------------------------------------------- */ /* UART port base addresses (for convenience) */ #define UART0 USART0_BASE /* APB0 */ #define UART1 UART1_BASE /* APB0 */ #define UART2 USART2_BASE /* APB2 */ #define UART3 USART3_BASE /* APB2 */ /* --- UART registers ------------------------------------------------------- */ /* Receiver Buffer Register (DLAB=0) Read Only */ #define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */ /* Transmitter Holding Register (DLAB=0) Write Only */ #define UART_THR(port) MMIO32(port + 0x000) /* 8bits */ /* Divisor Latch LSB Register (DLAB=1) */ #define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */ /* Divisor Latch MSB Register (DLAB=1) */ #define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */ /* Interrupt Enable Register (DLAB=0) */ #define UART_IER(port) MMIO32(port + 0x004) /* Interrupt ID Register Read Only */ #define UART_IIR(port) MMIO32(port + 0x008) /* FIFO Control Register Write Only */ #define UART_FCR(port) MMIO32(port + 0x008) /* Line Control Register */ #define UART_LCR(port) MMIO32(port + 0x00C) /* MCR only for UART1 */ /* Line Status Register */ #define UART_LSR(port) MMIO32(port + 0x014) /* Auto Baud Control Register */ #define UART_ACR(port) MMIO32(port + 0x020) /* IrDA Control Register only for UART0/2/3 */ #define UART_ICR(port) MMIO32(port + 0x024) /* Fractional Divider Register */ #define UART_FDR(port) MMIO32(port + 0x028) /* Oversampling Register only for UART0/2/3 */ #define UART_OSR(port) MMIO32(port + 0x02C) /* Half-Duplex enable Register only for UART0/2/3 */ #define UART_HDEN(port) MMIO32(port + 0x040) /* Smart card Interface Register Only for UART0/2/3 */ #define UART_SCICTRL(port) MMIO32(port + 0x048) /* RS-485/EIA-485 Control Register */ #define UART_RS485CTRL(port) MMIO32(port + 0x04C) /* RS-485/EIA-485 Address Match Register */ #define UART_RS485ADRMATCH(port) MMIO32(port + 0x050) /* RS-485/EIA-485 Direction Control Delay Register */ #define UART_RS485DLY(port) MMIO32(port + 0x054) /* Synchronous Mode Control Register only for UART0/2/3 */ #define UART_SYNCCTRL(port) MMIO32(port + 0x058) /* Transmit Enable Register */ #define UART_TER(port) MMIO32(port + 0x05C) /* --------------------- BIT DEFINITIONS ----------------------------------- */ /*********************************************************************** * Macro defines for Macro defines for UARTn Receiver Buffer Register **********************************************************************/ /* UART Received Buffer mask bit (8 bits) */ #define UART_RBR_MASKBIT ((uint8_t)0xFF) /*********************************************************************** * Macro defines for Macro defines for UARTn Transmit Holding Register **********************************************************************/ /* UART Transmit Holding mask bit (8 bits) */ #define UART_THR_MASKBIT ((uint8_t)0xFF) /*********************************************************************** * Macro defines for Macro defines for UARTn Divisor Latch LSB register **********************************************************************/ /* Macro for loading least significant halfs of divisors */ #define UART_LOAD_DLL(div) ((div) & 0xFF) /* Divisor latch LSB bit mask */ #define UART_DLL_MASKBIT ((uint8_t)0xFF) /*********************************************************************** * Macro defines for Macro defines for UARTn Divisor Latch MSB register **********************************************************************/ /* Divisor latch MSB bit mask */ #define UART_DLM_MASKBIT ((uint8_t)0xFF) /* Macro for loading most significant halfs of divisors */ #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*********************************************************************** * Macro defines for Macro defines for UART interrupt enable register **********************************************************************/ /* RBR Interrupt enable*/ #define UART_IER_RBRINT_EN (1 << 0) /* THR Interrupt enable*/ #define UART_IER_THREINT_EN (1 << 1) /* RX line status interrupt enable*/ #define UART_IER_RLSINT_EN (1 << 2) /* Modem status interrupt enable */ #define UART1_IER_MSINT_EN (1 << 3) /* CTS1 signal transition interrupt enable */ #define UART1_IER_CTSINT_EN (1 << 7) /* Enables the end of auto-baud interrupt */ #define UART_IER_ABEOINT_EN (1 << 8) /* Enables the auto-baud time-out interrupt */ #define UART_IER_ABTOINT_EN (1 << 9) /* UART interrupt enable register bit mask */ #define UART_IER_BITMASK ((uint32_t)(0x307)) /* UART1 interrupt enable register bit mask */ #define UART1_IER_BITMASK ((uint32_t)(0x38F)) /********************************************************************** * Macro defines for Macro defines for UART interrupt identification register **********************************************************************/ /* Interrupt Status - Active low */ #define UART_IIR_INTSTAT_PEND (1 << 0) /* Interrupt identification: Modem interrupt*/ #define UART1_IIR_INTID_MODEM (0 << 1) /* Interrupt identification: THRE interrupt*/ #define UART_IIR_INTID_THRE (1 << 1) /* Interrupt identification: Receive data available*/ #define UART_IIR_INTID_RDA (2 << 1) /* Interrupt identification: Receive line status*/ #define UART_IIR_INTID_RLS (3 << 1) /* Interrupt identification: Character time-out indicator*/ #define UART_IIR_INTID_CTI (6 << 1) /* Interrupt identification: Interrupt ID mask */ #define UART_IIR_INTID_MASK (7 << 1) /* These bits are equivalent to UnFCR[0] */ #define UART_IIR_FIFO_EN (3 << 6) /* End of auto-baud interrupt */ #define UART_IIR_ABEO_INT (1 << 8) /* Auto-baud time-out interrupt */ #define UART_IIR_ABTO_INT (1 << 9) /* UART interrupt identification register bit mask */ #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /********************************************************************** * Macro defines for Macro defines for UART FIFO control register **********************************************************************/ /* UART FIFO enable */ #define UART_FCR_FIFO_EN (1 << 0) /* UART FIFO RX reset */ #define UART_FCR_RX_RS (1 << 1) /* UART FIFO TX reset */ #define UART_FCR_TX_RS (1 << 2) /* UART DMA mode selection */ #define UART_FCR_DMAMODE_SEL (1 << 3) /* UART FIFO trigger level 0: 1 character */ #define UART_FCR_TRG_LEV0 (0 << 6) /* UART FIFO trigger level 1: 4 character */ #define UART_FCR_TRG_LEV1 (1 << 6) /* UART FIFO trigger level 2: 8 character */ #define UART_FCR_TRG_LEV2 (2 << 6) /* UART FIFO trigger level 3: 14 character */ #define UART_FCR_TRG_LEV3 (3 << 6) /* UART FIFO control bit mask */ #define UART_FCR_BITMASK ((uint8_t)(0xCF)) #define UART_TX_FIFO_SIZE (16) /********************************************************************** * Macro defines for Macro defines for UART line control register **********************************************************************/ /* UART 5 bit data mode */ #define UART_LCR_WLEN5 (0 << 0) /* UART 6 bit data mode */ #define UART_LCR_WLEN6 (1 << 0) /* UART 7 bit data mode */ #define UART_LCR_WLEN7 (2 << 0) /* UART 8 bit data mode */ #define UART_LCR_WLEN8 (3 << 0) /* UART One Stop Bits */ #define UART_LCR_ONE_STOPBIT (0 << 2) /* UART Two Stop Bits */ #define UART_LCR_TWO_STOPBIT (1 << 2) /* UART Parity Disabled / No Parity */ #define UART_LCR_NO_PARITY (0 << 3) /* UART Parity Enable */ #define UART_LCR_PARITY_EN (1 << 3) /* UART Odd Parity Select */ #define UART_LCR_PARITY_ODD (0 << 4) /* UART Even Parity Select */ #define UART_LCR_PARITY_EVEN (1 << 4) /* UART force 1 stick parity */ #define UART_LCR_PARITY_SP_1 (1 << 5) /* UART force 0 stick parity */ #define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4)) /* UART Transmission Break enable */ #define UART_LCR_BREAK_EN (1 << 6) /* UART Divisor Latches Access bit enable */ #define UART_LCR_DLAB_EN (1 << 7) /* UART line control bit mask */ #define UART_LCR_BITMASK ((uint8_t)(0xFF)) /********************************************************************** * Macro defines for Macro defines for UART line status register **********************************************************************/ /* Line status register: Receive data ready */ #define UART_LSR_RDR (1 << 0) /* Line status register: Overrun error */ #define UART_LSR_OE (1 << 1) /* Line status register: Parity error */ #define UART_LSR_PE (1 << 2) /* Line status register: Framing error */ #define UART_LSR_FE (1 << 3) /* Line status register: Break interrupt */ #define UART_LSR_BI (1 << 4) /* Line status register: Transmit holding register empty */ #define UART_LSR_THRE (1 << 5) /* Line status register: Transmitter empty */ #define UART_LSR_TEMT (1 << 6) /* Error in RX FIFO */ #define UART_LSR_RXFE (1 << 7) /* UART Line status bit mask */ #define UART_LSR_BITMASK ((uint8_t)(0xFF)) #define UART_LSR_ERROR_MASK \ (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE) /********************************************************************** * Macro defines for Macro defines for UART Scratch Pad Register **********************************************************************/ /* UART Scratch Pad bit mask */ #define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*********************************************************************** * Macro defines for Macro defines for UART Auto baudrate control register **********************************************************************/ /* UART Auto-baud start */ #define UART_ACR_START (1 << 0) /* UART Auto baudrate Mode 1 */ #define UART_ACR_MODE (1 << 1) /* UART Auto baudrate restart */ #define UART_ACR_AUTO_RESTART (1 << 2) /* UART End of auto-baud interrupt clear */ #define UART_ACR_ABEOINT_CLR (1 << 8) /* UART Auto-baud time-out interrupt clear */ #define UART_ACR_ABTOINT_CLR (1 << 9) /* UART Auto Baudrate register bit mask */ #define UART_ACR_BITMASK ((uint32_t)(0x307)) /********************************************************************* * Macro defines for Macro defines for UART IrDA control register **********************************************************************/ /* IrDA mode enable */ #define UART_ICR_IRDAEN (1 << 0) /* IrDA serial input inverted */ #define UART_ICR_IRDAINV (1 << 1) /* IrDA fixed pulse width mode */ #define UART_ICR_FIXPULSE_EN (1 << 2) /* PulseDiv - Configures the pulse when FixPulseEn = 1 */ #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /* UART IRDA bit mask */ #define UART_ICR_BITMASK ((uint32_t)(0x3F)) /********************************************************************** * Macro defines for Macro defines for UART half duplex register **********************************************************************/ /* enable half-duplex mode*/ #define UART_HDEN_HDEN (1 << 0) /********************************************************************** * Macro defines for Macro defines for UART smart card interface control register **********************************************************************/ /* enable asynchronous half-duplex smart card interface*/ #define UART_SCICTRL_SCIEN (1 << 0) /* NACK response is inhibited*/ #define UART_SCICTRL_NACKDIS (1 << 1) /* ISO7816-3 protocol T1 is selected*/ #define UART_SCICTRL_PROTSEL_T1 (1 << 2) /* number of retransmission*/ #define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /* Extra guard time*/ #define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /********************************************************************* * Macro defines for Macro defines for UART synchronous control register **********************************************************************/ /* enable synchronous mode*/ #define UART_SYNCCTRL_SYNC (1 << 0) /* synchronous master mode*/ #define UART_SYNCCTRL_CSRC_MASTER (1 << 1) /* sample on falling edge*/ #define UART_SYNCCTRL_FES (1 << 2) /* to be defined*/ #define UART_SYNCCTRL_TSBYPASS (1 << 3) /* continuous running clock enable (master mode only) */ #define UART_SYNCCTRL_CSCEN (1 << 4) /* Do not send start/stop bit */ #define UART_SYNCCTRL_NOSTARTSTOP (1 << 5) /* stop continuous clock */ #define UART_SYNCCTRL_CCCLR (1 << 6) /********************************************************************* * Macro defines for Macro defines for UART Fractional divider register **********************************************************************/ /* Baud-rate generation pre-scaler divisor */ #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /* Baud-rate pre-scaler multiplier value */ #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /* UART Fractional Divider register bit mask */ #define UART_FDR_BITMASK ((uint32_t)(0xFF)) /********************************************************************* * Macro defines for Macro defines for UART Tx Enable register **********************************************************************/ #define UART_TER_TXEN (1 << 0) /* Transmit enable bit */ /********************************************************************** * Macro defines for Macro defines for UART FIFO Level register **********************************************************************/ /* Reflects the current level of the UART receiver FIFO */ #define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F)) /* Reflects the current level of the UART transmitter FIFO */ #define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F)) /* UART FIFO Level Register bit mask */ #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /********************************************************************* * UART enum **********************************************************************/ /* * UART Databit type definitions */ typedef enum { UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */ UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */ UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */ UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */ } uart_databit_t; /* * UART Stop bit type definitions */ typedef enum { /* UART 1 Stop Bits Select */ UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT, /* UART 2 Stop Bits Select */ UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT } uart_stopbit_t; /* * UART Parity type definitions */ typedef enum { /* No parity */ UART_PARITY_NONE = UART_LCR_NO_PARITY, /* Odd parity */ UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN), /* Even parity */ UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN), /* Forced 1 stick parity */ UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN), /* Forced 0 stick parity */ UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN) } uart_parity_t; typedef enum { UART0_NUM = UART0, UART1_NUM = UART1, UART2_NUM = UART2, UART3_NUM = UART3 } uart_num_t; typedef enum { UART_NO_ERROR = 0, UART_TIMEOUT_ERROR = 1 } uart_error_t; typedef enum { UART_RX_NO_DATA = 0, UART_RX_DATA_READY = 1, UART_RX_DATA_ERROR = 2 } uart_rx_data_ready_t; /* function prototypes */ BEGIN_DECLS /* Init UART and set PLL1 as clock source (PCLK) */ void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, uart_stopbit_t data_nb_stop, uart_parity_t data_parity, uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval); uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num); uint8_t uart_read(uart_num_t uart_num); uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t *error); void uart_write(uart_num_t uart_num, uint8_t data); END_DECLS #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/usb.h000066400000000000000000002516411435536612600234270ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2015 Dominic Spill * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_USB_H #define LPC43XX_USB_H #include #include #ifdef __cplusplus extern "C" { #endif #define BIT_MASK(base_name) \ (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT) #define BIT_ARG(base_name, x) ((x) << base_name##_SHIFT) /* USB device data structures */ /* "The software must ensure that no interface data structure reachable * by the Device controller crosses a 4kB-page boundary." */ /* --- Endpoint Transfer Descriptor (dTD) ---------------------------------- */ typedef struct usb_transfer_descriptor_t usb_transfer_descriptor_t; struct usb_transfer_descriptor_t { volatile usb_transfer_descriptor_t *next_dtd_pointer; volatile uint32_t total_bytes; volatile uint32_t buffer_pointer_page[5]; volatile uint32_t _reserved; }; #define USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT (0) #define USB_TD_NEXT_DTD_POINTER_TERMINATE \ ((volatile usb_transfer_descriptor_t *) \ (1 << USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT)) #define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16) #define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15) #define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES) #define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, x) #define USB_TD_DTD_TOKEN_IOC_SHIFT (15) #define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT) #define USB_TD_DTD_TOKEN_MULTO_SHIFT (10) #define USB_TD_DTD_TOKEN_MULTO_WIDTH (2) #define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO) #define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, x) #define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7) #define USB_TD_DTD_TOKEN_STATUS_ACTIVE \ (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT) #define USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT (6) #define USB_TD_DTD_TOKEN_STATUS_HALTED \ (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT) #define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT (5) #define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR \ (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT) #define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT (3) #define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR \ (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT) /* --- Endpoint Queue Head (dQH) ------------------------------------------- */ /* - must be aligned on 64-byte boundaries. */ typedef struct { volatile uint32_t capabilities; volatile usb_transfer_descriptor_t *current_dtd_pointer; volatile usb_transfer_descriptor_t *next_dtd_pointer; volatile uint32_t total_bytes; volatile uint32_t buffer_pointer_page[5]; volatile uint32_t _reserved_0; volatile uint8_t setup[8]; volatile uint32_t _reserved_1[4]; } usb_queue_head_t; #define USB_QH_CAPABILITIES_IOS_SHIFT (15) #define USB_QH_CAPABILITIES_IOS (1 << USB_QH_CAPABILITIES_IOS_SHIFT) #define USB_QH_CAPABILITIES_MPL_SHIFT (16) #define USB_QH_CAPABILITIES_MPL_WIDTH (11) #define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL) #define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, x) #define USB_QH_CAPABILITIES_ZLT_SHIFT (29) #define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT) #define USB_QH_CAPABILITIES_MULT_SHIFT (30) #define USB_QH_CAPABILITIES_MULT_WIDTH (2) #define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT) #define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, x) /* --- USB0 registers ------------------------------------------------------ */ /* Device/host capability registers */ /* Capability register length */ #define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100) /* Host controller structural parameters */ #define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104) /* Host controller capability parameters */ #define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108) /* Device interface version number */ #define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120) /* Device controller capability parameters */ #define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124) /* Device/host operational registers */ /* USB command (device mode) */ #define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140) /* USB command (host mode) */ #define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140) /* USB status (device mode) */ #define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144) /* USB status (host mode) */ #define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144) /* USB interrupt enable (device mode) */ #define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148) /* USB interrupt enable (host mode) */ #define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148) /* USB frame index (device mode) */ #define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C) /* USB frame index (host mode) */ #define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C) /* USB device address (device mode) */ #define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154) /* Frame list base address (host mode) */ #define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154) /* Address of endpoint list in memory */ #define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158) /* Asynchronous list address */ #define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158) /* Asynchronous buffer status for embedded TT (host mode) */ #define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C) /* Programmable burst size */ #define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160) /* Host transmit pre-buffer packet tuning (host mode) */ #define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164) /* Length of virtual frame */ #define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174) /* Endpoint NAK (device mode) */ #define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178) /* Endpoint NAK Enable (device mode) */ #define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C) /* Port 1 status/control (device mode) */ #define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184) /* Port 1 status/control (host mode) */ #define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184) /* OTG status and control */ #define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4) /* USB device mode (device mode) */ #define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8) /* USB device mode (host mode) */ #define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8) /* Device endpoint registers */ /* Endpoint setup status */ #define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC) /* Endpoint initialization */ #define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0) /* Endpoint de-initialization */ #define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4) /* Endpoint status */ #define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8) /* Endpoint complete */ #define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC) /* Endpoint control */ #define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \ (logical_ep * 4)) /* Endpoint control 0 */ #define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) /* Endpoint control 1 */ #define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1) /* Endpoint control 2 */ #define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2) /* Endpoint control 3 */ #define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3) /* Endpoint control 4 */ #define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4) /* Endpoint control 5 */ #define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5) /* --- USB0_CAPLENGTH values ------------------------------------ */ /* CAPLENGTH: Indicates offset to add to the register base address at the beginning of the Operational Register */ #define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0) #define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT) #define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT) /* HCIVERSION: BCD encoding of the EHCI revision number supported by this host controller */ #define USB0_CAPLENGTH_HCIVERSION_SHIFT (8) #define USB0_CAPLENGTH_HCIVERSION_MASK \ (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) #define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT) /* --- USB0_HCSPARAMS values ------------------------------------ */ /* N_PORTS: Number of downstream ports */ #define USB0_HCSPARAMS_N_PORTS_SHIFT (0) #define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT) #define USB0_HCSPARAMS_N_PORTS(x) ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT) /* PPC: Port Power Control */ #define USB0_HCSPARAMS_PPC_SHIFT (4) #define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT) /* N_PCC: Number of Ports per Companion Controller */ #define USB0_HCSPARAMS_N_PCC_SHIFT (8) #define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT) #define USB0_HCSPARAMS_N_PCC(x) ((x) << USB0_HCSPARAMS_N_PCC_SHIFT) /* N_CC: Number of Companion Controller */ #define USB0_HCSPARAMS_N_CC_SHIFT (12) #define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT) #define USB0_HCSPARAMS_N_CC(x) ((x) << USB0_HCSPARAMS_N_CC_SHIFT) /* PI: Port indicators */ #define USB0_HCSPARAMS_PI_SHIFT (16) #define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT) /* N_PTT: Number of Ports per Transaction Translator */ #define USB0_HCSPARAMS_N_PTT_SHIFT (20) #define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT) #define USB0_HCSPARAMS_N_PTT(x) ((x) << USB0_HCSPARAMS_N_PTT_SHIFT) /* N_TT: Number of Transaction Translators */ #define USB0_HCSPARAMS_N_TT_SHIFT (24) #define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT) #define USB0_HCSPARAMS_N_TT(x) ((x) << USB0_HCSPARAMS_N_TT_SHIFT) /* --- USB0_HCCPARAMS values ------------------------------------ */ /* ADC: 64-bit Addressing Capability */ #define USB0_HCCPARAMS_ADC_SHIFT (0) #define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT) /* PFL: Programmable Frame List Flag */ #define USB0_HCCPARAMS_PFL_SHIFT (1) #define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT) /* ASP: Asynchronous Schedule Park Capability */ #define USB0_HCCPARAMS_ASP_SHIFT (2) #define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT) /* IST: Isochronous Scheduling Threshold */ #define USB0_HCCPARAMS_IST_SHIFT (4) #define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT) #define USB0_HCCPARAMS_IST(x) ((x) << USB0_HCCPARAMS_IST_SHIFT) /* EECP: EHCI Extended Capabilities Pointer */ #define USB0_HCCPARAMS_EECP_SHIFT (8) #define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT) #define USB0_HCCPARAMS_EECP(x) ((x) << USB0_HCCPARAMS_EECP_SHIFT) /* --- USB0_DCCPARAMS values ------------------------------------ */ /* DEN: Device Endpoint Number */ #define USB0_DCCPARAMS_DEN_SHIFT (0) #define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT) #define USB0_DCCPARAMS_DEN(x) ((x) << USB0_DCCPARAMS_DEN_SHIFT) /* DC: Device Capable */ #define USB0_DCCPARAMS_DC_SHIFT (7) #define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT) /* HC: Host Capable */ #define USB0_DCCPARAMS_HC_SHIFT (8) #define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT) /* --- USB0_USBCMD_D values ------------------------------------- */ /* RS: Run/Stop */ #define USB0_USBCMD_D_RS_SHIFT (0) #define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT) /* RST: Controller reset */ #define USB0_USBCMD_D_RST_SHIFT (1) #define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT) /* SUTW: Setup trip wire */ #define USB0_USBCMD_D_SUTW_SHIFT (13) #define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT) /* ATDTW: Add dTD trip wire */ #define USB0_USBCMD_D_ATDTW_SHIFT (14) #define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT) /* ITC: Interrupt threshold control */ #define USB0_USBCMD_D_ITC_SHIFT (16) #define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT) #define USB0_USBCMD_D_ITC(x) ((x) << USB0_USBCMD_D_ITC_SHIFT) /* --- USB0_USBCMD_H values ------------------------------------- */ /* RS: Run/Stop */ #define USB0_USBCMD_H_RS_SHIFT (0) #define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT) /* RST: Controller reset */ #define USB0_USBCMD_H_RST_SHIFT (1) #define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT) /* FS0: Bit 0 of the Frame List Size bits */ #define USB0_USBCMD_H_FS0_SHIFT (2) #define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT) /* FS1: Bit 1 of the Frame List Size bits */ #define USB0_USBCMD_H_FS1_SHIFT (3) #define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT) /* PSE: This bit controls whether the host controller skips processing the periodic schedule */ #define USB0_USBCMD_H_PSE_SHIFT (4) #define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT) /* ASE: This bit controls whether the host controller skips processing the asynchronous schedule */ #define USB0_USBCMD_H_ASE_SHIFT (5) #define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT) /* IAA: This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule */ #define USB0_USBCMD_H_IAA_SHIFT (6) #define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT) /* ASP1_0: Asynchronous schedule park mode */ #define USB0_USBCMD_H_ASP1_0_SHIFT (8) #define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT) #define USB0_USBCMD_H_ASP1_0(x) ((x) << USB0_USBCMD_H_ASP1_0_SHIFT) /* ASPE: Asynchronous Schedule Park Mode Enable */ #define USB0_USBCMD_H_ASPE_SHIFT (11) #define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT) /* FS2: Bit 2 of the Frame List Size bits */ #define USB0_USBCMD_H_FS2_SHIFT (15) #define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT) /* ITC: Interrupt threshold control */ #define USB0_USBCMD_H_ITC_SHIFT (16) #define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT) #define USB0_USBCMD_H_ITC(x) ((x) << USB0_USBCMD_H_ITC_SHIFT) /* --- USB0_USBSTS_D values ------------------------------------- */ /* UI: USB interrupt */ #define USB0_USBSTS_D_UI_SHIFT (0) #define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT) /* UEI: USB error interrupt */ #define USB0_USBSTS_D_UEI_SHIFT (1) #define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT) /* PCI: Port change detect */ #define USB0_USBSTS_D_PCI_SHIFT (2) #define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT) /* URI: USB reset received */ #define USB0_USBSTS_D_URI_SHIFT (6) #define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT) /* SRI: SOF received */ #define USB0_USBSTS_D_SRI_SHIFT (7) #define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT) /* SLI: DCSuspend */ #define USB0_USBSTS_D_SLI_SHIFT (8) #define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT) /* NAKI: NAK interrupt bit */ #define USB0_USBSTS_D_NAKI_SHIFT (16) #define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT) /* --- USB0_USBSTS_H values ------------------------------------- */ /* UI: USB interrupt */ #define USB0_USBSTS_H_UI_SHIFT (0) #define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT) /* UEI: USB error interrupt */ #define USB0_USBSTS_H_UEI_SHIFT (1) #define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT) /* PCI: Port change detect */ #define USB0_USBSTS_H_PCI_SHIFT (2) #define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT) /* FRI: Frame list roll-over */ #define USB0_USBSTS_H_FRI_SHIFT (3) #define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT) /* AAI: Interrupt on async advance */ #define USB0_USBSTS_H_AAI_SHIFT (5) #define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT) /* SRI: SOF received */ #define USB0_USBSTS_H_SRI_SHIFT (7) #define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT) /* HCH: HCHalted */ #define USB0_USBSTS_H_HCH_SHIFT (12) #define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT) /* RCL: Reclamation */ #define USB0_USBSTS_H_RCL_SHIFT (13) #define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT) /* PS: Periodic schedule status */ #define USB0_USBSTS_H_PS_SHIFT (14) #define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT) /* AS: Asynchronous schedule status */ #define USB0_USBSTS_H_AS_SHIFT (15) #define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT) /* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */ #define USB0_USBSTS_H_UAI_SHIFT (18) #define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT) /* UPI: USB host periodic interrupt (USBHSTPERINT) */ #define USB0_USBSTS_H_UPI_SHIFT (19) #define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT) /* --- USB0_USBINTR_D values ------------------------------------ */ /* UE: USB interrupt enable */ #define USB0_USBINTR_D_UE_SHIFT (0) #define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT) /* UEE: USB error interrupt enable */ #define USB0_USBINTR_D_UEE_SHIFT (1) #define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT) /* PCE: Port change detect enable */ #define USB0_USBINTR_D_PCE_SHIFT (2) #define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT) /* URE: USB reset enable */ #define USB0_USBINTR_D_URE_SHIFT (6) #define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT) /* SRE: SOF received enable */ #define USB0_USBINTR_D_SRE_SHIFT (7) #define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT) /* SLE: Sleep enable */ #define USB0_USBINTR_D_SLE_SHIFT (8) #define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT) /* NAKE: NAK interrupt enable */ #define USB0_USBINTR_D_NAKE_SHIFT (16) #define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT) /* --- USB0_USBINTR_H values ------------------------------------ */ /* UE: USB interrupt enable */ #define USB0_USBINTR_H_UE_SHIFT (0) #define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT) /* UEE: USB error interrupt enable */ #define USB0_USBINTR_H_UEE_SHIFT (1) #define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT) /* PCE: Port change detect enable */ #define USB0_USBINTR_H_PCE_SHIFT (2) #define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT) /* FRE: Frame list rollover enable */ #define USB0_USBINTR_H_FRE_SHIFT (3) #define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT) /* AAE: Interrupt on asynchronous advance enable */ #define USB0_USBINTR_H_AAE_SHIFT (5) #define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT) /* SRE: SOF received enable */ #define USB0_USBINTR_H_SRE_SHIFT (7) #define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT) /* UAIE: USB host asynchronous interrupt enable */ #define USB0_USBINTR_H_UAIE_SHIFT (18) #define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT) /* UPIA: USB host periodic interrupt enable */ #define USB0_USBINTR_H_UPIA_SHIFT (19) #define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT) /* --- USB0_FRINDEX_D values ------------------------------------ */ /* FRINDEX2_0: Current micro frame number */ #define USB0_FRINDEX_D_FRINDEX2_0_SHIFT (0) #define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) #define USB0_FRINDEX_D_FRINDEX2_0(x) ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) /* FRINDEX13_3: Current frame number of the last frame transmitted */ #define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3) #define USB0_FRINDEX_D_FRINDEX13_3_MASK \ (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) #define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) /* --- USB0_FRINDEX_H values ------------------------------------ */ /* FRINDEX2_0: Current micro frame number */ #define USB0_FRINDEX_H_FRINDEX2_0_SHIFT (0) #define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) #define USB0_FRINDEX_H_FRINDEX2_0(x) ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) /* FRINDEX12_3: Frame list current index */ #define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3) #define USB0_FRINDEX_H_FRINDEX12_3_MASK \ (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) #define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) /* --- USB0_DEVICEADDR values ----------------------------------- */ /* USBADRA: Device address advance */ #define USB0_DEVICEADDR_USBADRA_SHIFT (24) #define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT) /* USBADR: USB device address */ #define USB0_DEVICEADDR_USBADR_SHIFT (25) #define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT) #define USB0_DEVICEADDR_USBADR(x) ((x) << USB0_DEVICEADDR_USBADR_SHIFT) /* --- USB0_PERIODICLISTBASE values ----------------------------- */ /* PERBASE31_12: Base Address (Low) */ #define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12) #define USB0_PERIODICLISTBASE_PERBASE31_12_MASK \ (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) #define USB0_PERIODICLISTBASE_PERBASE31_12(x) \ ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) /* --- USB0_ENDPOINTLISTADDR values ----------------------------- */ /* EPBASE31_11: Endpoint list pointer (low) */ #define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11) #define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK \ (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) #define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) \ ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) /* --- USB0_ASYNCLISTADDR values -------------------------------- */ /* ASYBASE31_5: Link pointer (Low) LPL */ #define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5) #define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK \ (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) #define USB0_ASYNCLISTADDR_ASYBASE31_5(x) \ ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) /* --- USB0_TTCTRL values --------------------------------------- */ /* TTHA: Hub address when FS or LS device are connected directly */ #define USB0_TTCTRL_TTHA_SHIFT (24) #define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT) #define USB0_TTCTRL_TTHA(x) ((x) << USB0_TTCTRL_TTHA_SHIFT) /* --- USB0_BURSTSIZE values ------------------------------------ */ /* RXPBURST: Programmable RX burst length */ #define USB0_BURSTSIZE_RXPBURST_SHIFT (0) #define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT) #define USB0_BURSTSIZE_RXPBURST(x) ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT) /* TXPBURST: Programmable TX burst length */ #define USB0_BURSTSIZE_TXPBURST_SHIFT (8) #define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT) #define USB0_BURSTSIZE_TXPBURST(x) ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT) /* --- USB0_TXFILLTUNING values --------------------------------- */ /* TXSCHOH: FIFO burst threshold */ #define USB0_TXFILLTUNING_TXSCHOH_SHIFT (0) #define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT) #define USB0_TXFILLTUNING_TXSCHOH(x) ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT) /* TXSCHEATLTH: Scheduler health counter */ #define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8) #define USB0_TXFILLTUNING_TXSCHEATLTH_MASK \ (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) #define USB0_TXFILLTUNING_TXSCHEATLTH(x) \ ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) /* TXFIFOTHRES: Scheduler overhead */ #define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) #define USB0_TXFILLTUNING_TXFIFOTHRES_MASK \ (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) #define USB0_TXFILLTUNING_TXFIFOTHRES(x) \ ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) /* --- USB0_BINTERVAL values ------------------------------------ */ /* BINT: bInterval value */ #define USB0_BINTERVAL_BINT_SHIFT (0) #define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT) #define USB0_BINTERVAL_BINT(x) ((x) << USB0_BINTERVAL_BINT_SHIFT) /* --- USB0_ENDPTNAK values ------------------------------------- */ /* EPRN: Rx endpoint NAK */ #define USB0_ENDPTNAK_EPRN_SHIFT (0) #define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT) #define USB0_ENDPTNAK_EPRN(x) ((x) << USB0_ENDPTNAK_EPRN_SHIFT) /* EPTN: Tx endpoint NAK */ #define USB0_ENDPTNAK_EPTN_SHIFT (16) #define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT) #define USB0_ENDPTNAK_EPTN(x) ((x) << USB0_ENDPTNAK_EPTN_SHIFT) /* --- USB0_ENDPTNAKEN values ----------------------------------- */ /* EPRNE: Rx endpoint NAK enable */ #define USB0_ENDPTNAKEN_EPRNE_SHIFT (0) #define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT) #define USB0_ENDPTNAKEN_EPRNE(x) ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT) /* EPTNE: Tx endpoint NAK */ #define USB0_ENDPTNAKEN_EPTNE_SHIFT (16) #define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT) #define USB0_ENDPTNAKEN_EPTNE(x) ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT) /* --- USB0_PORTSC1_D values ------------------------------------ */ /* CCS: Current connect status */ #define USB0_PORTSC1_D_CCS_SHIFT (0) #define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT) /* PE: Port enable */ #define USB0_PORTSC1_D_PE_SHIFT (2) #define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT) /* PEC: Port enable/disable change */ #define USB0_PORTSC1_D_PEC_SHIFT (3) #define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT) /* FPR: Force port resume */ #define USB0_PORTSC1_D_FPR_SHIFT (6) #define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT) /* SUSP: Suspend */ #define USB0_PORTSC1_D_SUSP_SHIFT (7) #define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT) /* PR: Port reset */ #define USB0_PORTSC1_D_PR_SHIFT (8) #define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT) /* HSP: High-speed status */ #define USB0_PORTSC1_D_HSP_SHIFT (9) #define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT) /* PIC1_0: Port indicator control */ #define USB0_PORTSC1_D_PIC1_0_SHIFT (14) #define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT) #define USB0_PORTSC1_D_PIC1_0(x) ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT) /* PTC3_0: Port test control */ #define USB0_PORTSC1_D_PTC3_0_SHIFT (16) #define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT) #define USB0_PORTSC1_D_PTC3_0(x) ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT) /* PHCD: PHY low power suspend - clock disable (PLPSCD) */ #define USB0_PORTSC1_D_PHCD_SHIFT (23) #define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT) /* PFSC: Port force full speed connect */ #define USB0_PORTSC1_D_PFSC_SHIFT (24) #define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT) /* PSPD: Port speed */ #define USB0_PORTSC1_D_PSPD_SHIFT (26) #define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT) #define USB0_PORTSC1_D_PSPD(x) ((x) << USB0_PORTSC1_D_PSPD_SHIFT) /* --- USB0_PORTSC1_H values ------------------------------------ */ /* CCS: Current connect status */ #define USB0_PORTSC1_H_CCS_SHIFT (0) #define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT) /* CSC: Connect status change */ #define USB0_PORTSC1_H_CSC_SHIFT (1) #define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT) /* PE: Port enable */ #define USB0_PORTSC1_H_PE_SHIFT (2) #define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT) /* PEC: Port disable/enable change */ #define USB0_PORTSC1_H_PEC_SHIFT (3) #define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT) /* OCA: Over-current active */ #define USB0_PORTSC1_H_OCA_SHIFT (4) #define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT) /* OCC: Over-current change */ #define USB0_PORTSC1_H_OCC_SHIFT (5) #define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT) /* FPR: Force port resume */ #define USB0_PORTSC1_H_FPR_SHIFT (6) #define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT) /* SUSP: Suspend */ #define USB0_PORTSC1_H_SUSP_SHIFT (7) #define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT) /* PR: Port reset */ #define USB0_PORTSC1_H_PR_SHIFT (8) #define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT) /* HSP: High-speed status */ #define USB0_PORTSC1_H_HSP_SHIFT (9) #define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT) /* LS: Line status */ #define USB0_PORTSC1_H_LS_SHIFT (10) #define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT) #define USB0_PORTSC1_H_LS(x) ((x) << USB0_PORTSC1_H_LS_SHIFT) /* PP: Port power control */ #define USB0_PORTSC1_H_PP_SHIFT (12) #define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT) /* PIC1_0: Port indicator control */ #define USB0_PORTSC1_H_PIC1_0_SHIFT (14) #define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT) #define USB0_PORTSC1_H_PIC1_0(x) ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT) /* PTC3_0: Port test control */ #define USB0_PORTSC1_H_PTC3_0_SHIFT (16) #define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT) #define USB0_PORTSC1_H_PTC3_0(x) ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT) /* WKCN: Wake on connect enable (WKCNNT_E) */ #define USB0_PORTSC1_H_WKCN_SHIFT (20) #define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT) /* WKDC: Wake on disconnect enable (WKDSCNNT_E) */ #define USB0_PORTSC1_H_WKDC_SHIFT (21) #define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT) /* WKOC: Wake on over-current enable (WKOC_E) */ #define USB0_PORTSC1_H_WKOC_SHIFT (22) #define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT) /* PHCD: PHY low power suspend - clock disable (PLPSCD) */ #define USB0_PORTSC1_H_PHCD_SHIFT (23) #define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT) /* PFSC: Port force full speed connect */ #define USB0_PORTSC1_H_PFSC_SHIFT (24) #define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT) /* PSPD: Port speed */ #define USB0_PORTSC1_H_PSPD_SHIFT (26) #define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT) #define USB0_PORTSC1_H_PSPD(x) ((x) << USB0_PORTSC1_H_PSPD_SHIFT) /* --- USB0_OTGSC values ---------------------------------------- */ /* VD: VBUS_Discharge */ #define USB0_OTGSC_VD_SHIFT (0) #define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT) /* VC: VBUS_Charge */ #define USB0_OTGSC_VC_SHIFT (1) #define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT) /* HAAR: Hardware assist auto_reset */ #define USB0_OTGSC_HAAR_SHIFT (2) #define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT) /* OT: OTG termination */ #define USB0_OTGSC_OT_SHIFT (3) #define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT) /* DP: Data pulsing */ #define USB0_OTGSC_DP_SHIFT (4) #define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT) /* IDPU: ID pull-up */ #define USB0_OTGSC_IDPU_SHIFT (5) #define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT) /* HADP: Hardware assist data pulse */ #define USB0_OTGSC_HADP_SHIFT (6) #define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT) /* HABA: Hardware assist B-disconnect to A-connect */ #define USB0_OTGSC_HABA_SHIFT (7) #define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT) /* ID: USB ID */ #define USB0_OTGSC_ID_SHIFT (8) #define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT) /* AVV: A-VBUS valid */ #define USB0_OTGSC_AVV_SHIFT (9) #define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT) /* ASV: A-session valid */ #define USB0_OTGSC_ASV_SHIFT (10) #define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT) /* BSV: B-session valid */ #define USB0_OTGSC_BSV_SHIFT (11) #define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT) /* BSE: B-session end */ #define USB0_OTGSC_BSE_SHIFT (12) #define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT) /* MS1T: 1 millisecond timer toggle */ #define USB0_OTGSC_MS1T_SHIFT (13) #define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT) /* DPS: Data bus pulsing status */ #define USB0_OTGSC_DPS_SHIFT (14) #define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT) /* IDIS: USB ID interrupt status */ #define USB0_OTGSC_IDIS_SHIFT (16) #define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT) /* AVVIS: A-VBUS valid interrupt status */ #define USB0_OTGSC_AVVIS_SHIFT (17) #define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT) /* ASVIS: A-Session valid interrupt status */ #define USB0_OTGSC_ASVIS_SHIFT (18) #define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT) /* BSVIS: B-Session valid interrupt status */ #define USB0_OTGSC_BSVIS_SHIFT (19) #define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT) /* BSEIS: B-Session end interrupt status */ #define USB0_OTGSC_BSEIS_SHIFT (20) #define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT) /* MS1S: 1 millisecond timer interrupt status */ #define USB0_OTGSC_MS1S_SHIFT (21) #define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT) /* DPIS: Data pulse interrupt status */ #define USB0_OTGSC_DPIS_SHIFT (22) #define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT) /* IDIE: USB ID interrupt enable */ #define USB0_OTGSC_IDIE_SHIFT (24) #define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT) /* AVVIE: A-VBUS valid interrupt enable */ #define USB0_OTGSC_AVVIE_SHIFT (25) #define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT) /* ASVIE: A-session valid interrupt enable */ #define USB0_OTGSC_ASVIE_SHIFT (26) #define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT) /* BSVIE: B-session valid interrupt enable */ #define USB0_OTGSC_BSVIE_SHIFT (27) #define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT) /* BSEIE: B-session end interrupt enable */ #define USB0_OTGSC_BSEIE_SHIFT (28) #define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT) /* MS1E: 1 millisecond timer interrupt enable */ #define USB0_OTGSC_MS1E_SHIFT (29) #define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT) /* DPIE: Data pulse interrupt enable */ #define USB0_OTGSC_DPIE_SHIFT (30) #define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT) /* --- USB0_USBMODE_D values ------------------------------------ */ /* CM1_0: Controller mode */ #define USB0_USBMODE_D_CM1_0_SHIFT (0) #define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT) #define USB0_USBMODE_D_CM1_0(x) ((x) << USB0_USBMODE_D_CM1_0_SHIFT) /* ES: Endian select */ #define USB0_USBMODE_D_ES_SHIFT (2) #define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT) /* SLOM: Setup Lockout mode */ #define USB0_USBMODE_D_SLOM_SHIFT (3) #define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT) /* SDIS: Setup Lockout mode */ #define USB0_USBMODE_D_SDIS_SHIFT (4) #define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT) /* --- USB0_USBMODE_H values ------------------------------------ */ /* CM: Controller mode */ #define USB0_USBMODE_H_CM_SHIFT (0) #define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT) #define USB0_USBMODE_H_CM(x) ((x) << USB0_USBMODE_H_CM_SHIFT) /* ES: Endian select */ #define USB0_USBMODE_H_ES_SHIFT (2) #define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT) /* SDIS: Stream disable mode */ #define USB0_USBMODE_H_SDIS_SHIFT (4) #define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT) /* VBPS: VBUS power select */ #define USB0_USBMODE_H_VBPS_SHIFT (5) #define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT) /* --- USB0_ENDPTSETUPSTAT values ------------------------------- */ /* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0) #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK \ (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \ ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) /* --- USB0_ENDPTPRIME values ----------------------------------- */ /* PERB: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 */ #define USB0_ENDPTPRIME_PERB_SHIFT (0) #define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT) #define USB0_ENDPTPRIME_PERB(x) ((x) << USB0_ENDPTPRIME_PERB_SHIFT) /* PETB: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 */ #define USB0_ENDPTPRIME_PETB_SHIFT (16) #define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT) #define USB0_ENDPTPRIME_PETB(x) ((x) << USB0_ENDPTPRIME_PETB_SHIFT) /* --- USB0_ENDPTFLUSH values ----------------------------------- */ /* FERB: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 */ #define USB0_ENDPTFLUSH_FERB_SHIFT (0) #define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT) #define USB0_ENDPTFLUSH_FERB(x) ((x) << USB0_ENDPTFLUSH_FERB_SHIFT) /* FETB: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 */ #define USB0_ENDPTFLUSH_FETB_SHIFT (16) #define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT) #define USB0_ENDPTFLUSH_FETB(x) ((x) << USB0_ENDPTFLUSH_FETB_SHIFT) /* --- USB0_ENDPTSTAT values ------------------------------------ */ /* ERBR: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 */ #define USB0_ENDPTSTAT_ERBR_SHIFT (0) #define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT) #define USB0_ENDPTSTAT_ERBR(x) ((x) << USB0_ENDPTSTAT_ERBR_SHIFT) /* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */ #define USB0_ENDPTSTAT_ETBR_SHIFT (16) #define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT) #define USB0_ENDPTSTAT_ETBR(x) ((x) << USB0_ENDPTSTAT_ETBR_SHIFT) /* --- USB0_ENDPTCOMPLETE values -------------------------------- */ /* ERCE: Endpoint receive complete event for physical OUT endpoints 5 to 0 */ #define USB0_ENDPTCOMPLETE_ERCE_SHIFT (0) #define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT) #define USB0_ENDPTCOMPLETE_ERCE(x) ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT) /* ETCE: Endpoint transmit complete event for physical IN endpoints 5 to 0 */ #define USB0_ENDPTCOMPLETE_ETCE_SHIFT (16) #define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT) #define USB0_ENDPTCOMPLETE_ETCE(x) ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT) /* --- USB0_ENDPTCTRL0 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB0_ENDPTCTRL0_RXS_SHIFT (0) #define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT) /* RXT1_0: Endpoint type */ #define USB0_ENDPTCTRL0_RXT1_0_SHIFT (2) #define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT) #define USB0_ENDPTCTRL0_RXT1_0(x) ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT) /* RXE: Rx endpoint enable */ #define USB0_ENDPTCTRL0_RXE_SHIFT (7) #define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB0_ENDPTCTRL0_TXS_SHIFT (16) #define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT) /* TXT1_0: Endpoint type */ #define USB0_ENDPTCTRL0_TXT1_0_SHIFT (18) #define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT) #define USB0_ENDPTCTRL0_TXT1_0(x) ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT) /* TXE: Tx endpoint enable */ #define USB0_ENDPTCTRL0_TXE_SHIFT (23) #define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT) /* --- USB0_ENDPTCTRL1 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB0_ENDPTCTRL1_RXS_SHIFT (0) #define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT) /* RXT: Endpoint type */ #define USB0_ENDPTCTRL1_RXT_SHIFT (2) #define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT) #define USB0_ENDPTCTRL1_RXT(x) ((x) << USB0_ENDPTCTRL1_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB0_ENDPTCTRL1_RXI_SHIFT (5) #define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB0_ENDPTCTRL1_RXR_SHIFT (6) #define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB0_ENDPTCTRL1_RXE_SHIFT (7) #define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB0_ENDPTCTRL1_TXS_SHIFT (16) #define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB0_ENDPTCTRL1_TXT1_0_SHIFT (18) #define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT) #define USB0_ENDPTCTRL1_TXT1_0(x) ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB0_ENDPTCTRL1_TXI_SHIFT (21) #define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB0_ENDPTCTRL1_TXR_SHIFT (22) #define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB0_ENDPTCTRL1_TXE_SHIFT (23) #define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT) /* --- USB0_ENDPTCTRL2 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB0_ENDPTCTRL2_RXS_SHIFT (0) #define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT) /* RXT: Endpoint type */ #define USB0_ENDPTCTRL2_RXT_SHIFT (2) #define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT) #define USB0_ENDPTCTRL2_RXT(x) ((x) << USB0_ENDPTCTRL2_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB0_ENDPTCTRL2_RXI_SHIFT (5) #define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB0_ENDPTCTRL2_RXR_SHIFT (6) #define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB0_ENDPTCTRL2_RXE_SHIFT (7) #define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB0_ENDPTCTRL2_TXS_SHIFT (16) #define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB0_ENDPTCTRL2_TXT1_0_SHIFT (18) #define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT) #define USB0_ENDPTCTRL2_TXT1_0(x) ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB0_ENDPTCTRL2_TXI_SHIFT (21) #define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB0_ENDPTCTRL2_TXR_SHIFT (22) #define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB0_ENDPTCTRL2_TXE_SHIFT (23) #define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT) /* --- USB0_ENDPTCTRL3 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB0_ENDPTCTRL3_RXS_SHIFT (0) #define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT) /* RXT: Endpoint type */ #define USB0_ENDPTCTRL3_RXT_SHIFT (2) #define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT) #define USB0_ENDPTCTRL3_RXT(x) ((x) << USB0_ENDPTCTRL3_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB0_ENDPTCTRL3_RXI_SHIFT (5) #define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB0_ENDPTCTRL3_RXR_SHIFT (6) #define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB0_ENDPTCTRL3_RXE_SHIFT (7) #define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB0_ENDPTCTRL3_TXS_SHIFT (16) #define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB0_ENDPTCTRL3_TXT1_0_SHIFT (18) #define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT) #define USB0_ENDPTCTRL3_TXT1_0(x) ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB0_ENDPTCTRL3_TXI_SHIFT (21) #define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB0_ENDPTCTRL3_TXR_SHIFT (22) #define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB0_ENDPTCTRL3_TXE_SHIFT (23) #define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT) /* --- USB0_ENDPTCTRL4 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB0_ENDPTCTRL4_RXS_SHIFT (0) #define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT) /* RXT: Endpoint type */ #define USB0_ENDPTCTRL4_RXT_SHIFT (2) #define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT) #define USB0_ENDPTCTRL4_RXT(x) ((x) << USB0_ENDPTCTRL4_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB0_ENDPTCTRL4_RXI_SHIFT (5) #define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB0_ENDPTCTRL4_RXR_SHIFT (6) #define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB0_ENDPTCTRL4_RXE_SHIFT (7) #define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB0_ENDPTCTRL4_TXS_SHIFT (16) #define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB0_ENDPTCTRL4_TXT1_0_SHIFT (18) #define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT) #define USB0_ENDPTCTRL4_TXT1_0(x) ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB0_ENDPTCTRL4_TXI_SHIFT (21) #define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB0_ENDPTCTRL4_TXR_SHIFT (22) #define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB0_ENDPTCTRL4_TXE_SHIFT (23) #define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT) /* --- USB0_ENDPTCTRL5 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB0_ENDPTCTRL5_RXS_SHIFT (0) #define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT) /* RXT: Endpoint type */ #define USB0_ENDPTCTRL5_RXT_SHIFT (2) #define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT) #define USB0_ENDPTCTRL5_RXT(x) ((x) << USB0_ENDPTCTRL5_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB0_ENDPTCTRL5_RXI_SHIFT (5) #define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB0_ENDPTCTRL5_RXR_SHIFT (6) #define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB0_ENDPTCTRL5_RXE_SHIFT (7) #define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB0_ENDPTCTRL5_TXS_SHIFT (16) #define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB0_ENDPTCTRL5_TXT1_0_SHIFT (18) #define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT) #define USB0_ENDPTCTRL5_TXT1_0(x) ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB0_ENDPTCTRL5_TXI_SHIFT (21) #define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB0_ENDPTCTRL5_TXR_SHIFT (22) #define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB0_ENDPTCTRL5_TXE_SHIFT (23) #define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT) /* -------------------------------------------------------------- */ /* --- USB0_ENDPTCTRL common values ----------------------------- */ /* RXS: Rx endpoint stall */ #define USB0_ENDPTCTRL_RXS_SHIFT (0) #define USB0_ENDPTCTRL_RXS (1 << USB0_ENDPTCTRL_RXS_SHIFT) /* RXT: Endpoint type */ #define USB0_ENDPTCTRL_RXT_SHIFT (2) #define USB0_ENDPTCTRL_RXT_MASK (0x3 << USB0_ENDPTCTRL_RXT_SHIFT) #define USB0_ENDPTCTRL_RXT(x) ((x) << USB0_ENDPTCTRL_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB0_ENDPTCTRL_RXI_SHIFT (5) #define USB0_ENDPTCTRL_RXI (1 << USB0_ENDPTCTRL_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB0_ENDPTCTRL_RXR_SHIFT (6) #define USB0_ENDPTCTRL_RXR (1 << USB0_ENDPTCTRL_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB0_ENDPTCTRL_RXE_SHIFT (7) #define USB0_ENDPTCTRL_RXE (1 << USB0_ENDPTCTRL_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB0_ENDPTCTRL_TXS_SHIFT (16) #define USB0_ENDPTCTRL_TXS (1 << USB0_ENDPTCTRL_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB0_ENDPTCTRL_TXT1_0_SHIFT (18) #define USB0_ENDPTCTRL_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL_TXT1_0_SHIFT) #define USB0_ENDPTCTRL_TXT1_0(x) ((x) << USB0_ENDPTCTRL_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB0_ENDPTCTRL_TXI_SHIFT (21) #define USB0_ENDPTCTRL_TXI (1 << USB0_ENDPTCTRL_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB0_ENDPTCTRL_TXR_SHIFT (22) #define USB0_ENDPTCTRL_TXR (1 << USB0_ENDPTCTRL_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB0_ENDPTCTRL_TXE_SHIFT (23) #define USB0_ENDPTCTRL_TXE (1 << USB0_ENDPTCTRL_TXE_SHIFT) /* --- USB1 registers ------------------------------------------------------ */ /* Device/host capability registers */ /* Capability register length */ #define USB1_CAPLENGTH MMIO32(USB1_BASE + 0x100) /* Host controller structural parameters */ #define USB1_HCSPARAMS MMIO32(USB1_BASE + 0x104) /* Host controller capability parameters */ #define USB1_HCCPARAMS MMIO32(USB1_BASE + 0x108) /* Device interface version number */ #define USB1_DCIVERSION MMIO32(USB1_BASE + 0x120) /* Device controller capability parameters */ #define USB1_DCCPARAMS MMIO32(USB1_BASE + 0x124) /* Device/host operational registers */ /* USB command (device mode) */ #define USB1_USBCMD_D MMIO32(USB1_BASE + 0x140) /* USB command (host mode) */ #define USB1_USBCMD_H MMIO32(USB1_BASE + 0x140) /* USB status (device mode) */ #define USB1_USBSTS_D MMIO32(USB1_BASE + 0x144) /* USB status (host mode) */ #define USB1_USBSTS_H MMIO32(USB1_BASE + 0x144) /* USB interrupt enable (device mode) */ #define USB1_USBINTR_D MMIO32(USB1_BASE + 0x148) /* USB interrupt enable (host mode) */ #define USB1_USBINTR_H MMIO32(USB1_BASE + 0x148) /* USB frame index (device mode) */ #define USB1_FRINDEX_D MMIO32(USB1_BASE + 0x14C) /* USB frame index (host mode) */ #define USB1_FRINDEX_H MMIO32(USB1_BASE + 0x14C) /* USB device address (device mode) */ #define USB1_DEVICEADDR MMIO32(USB1_BASE + 0x154) /* Frame list base address (host mode) */ #define USB1_PERIODICLISTBASE MMIO32(USB1_BASE + 0x154) /* Address of endpoint list in memory */ #define USB1_ENDPOINTLISTADDR MMIO32(USB1_BASE + 0x158) /* Asynchronous list address */ #define USB1_ASYNCLISTADDR MMIO32(USB1_BASE + 0x158) /* Asynchronous buffer status for embedded TT (host mode) */ #define USB1_TTCTRL MMIO32(USB1_BASE + 0x15C) /* Programmable burst size */ #define USB1_BURSTSIZE MMIO32(USB1_BASE + 0x160) /* Host transmit pre-buffer packet tuning (host mode) */ #define USB1_TXFILLTUNING MMIO32(USB1_BASE + 0x164) /* Indirect access to the ULPI PHY registers */ #define USB1_ULPIVIEWPORT MMIO32(USB1_BASE + 0x170) /* Length of virtual frame */ #define USB1_BINTERVAL MMIO32(USB1_BASE + 0x174) /* Endpoint NAK (device mode) */ #define USB1_ENDPTNAK MMIO32(USB1_BASE + 0x178) /* Endpoint NAK Enable (device mode) */ #define USB1_ENDPTNAKEN MMIO32(USB1_BASE + 0x17C) /* Port 1 status/control (device mode) */ #define USB1_PORTSC1_D MMIO32(USB1_BASE + 0x184) /* Port 1 status/control (host mode) */ #define USB1_PORTSC1_H MMIO32(USB1_BASE + 0x184) /* USB device mode (device mode) */ #define USB1_USBMODE_D MMIO32(USB1_BASE + 0x1A8) /* USB device mode (host mode) */ #define USB1_USBMODE_H MMIO32(USB1_BASE + 0x1A8) /* Device endpoint registers */ /* Endpoint setup status */ #define USB1_ENDPTSETUPSTAT MMIO32(USB1_BASE + 0x1AC) /* Endpoint initialization */ #define USB1_ENDPTPRIME MMIO32(USB1_BASE + 0x1B0) /* Endpoint de-initialization */ #define USB1_ENDPTFLUSH MMIO32(USB1_BASE + 0x1B4) /* Endpoint status */ #define USB1_ENDPTSTAT MMIO32(USB1_BASE + 0x1B8) /* Endpoint complete */ #define USB1_ENDPTCOMPLETE MMIO32(USB1_BASE + 0x1BC) /* Endpoint control */ #define USB1_ENDPTCTRL(logical_ep) MMIO32(USB1_BASE + 0x1C0 + \ (logical_ep * 4)) /* Endpoint control 0 */ #define USB1_ENDPTCTRL0 USB1_ENDPTCTRL(0) /* Endpoint control 1 */ #define USB1_ENDPTCTRL1 USB1_ENDPTCTRL(1) /* Endpoint control 2 */ #define USB1_ENDPTCTRL2 USB1_ENDPTCTRL(2) /* Endpoint control 3 */ #define USB1_ENDPTCTRL3 USB1_ENDPTCTRL(3) /* --- USB1_CAPLENGTH values ------------------------------------ */ /* CAPLENGTH: Indicates offset to add to the register base address at the beginning of the Operational Register */ #define USB1_CAPLENGTH_CAPLENGTH_SHIFT (0) #define USB1_CAPLENGTH_CAPLENGTH_MASK (0xff << USB1_CAPLENGTH_CAPLENGTH_SHIFT) #define USB1_CAPLENGTH_CAPLENGTH(x) ((x) << USB1_CAPLENGTH_CAPLENGTH_SHIFT) /* HCIVERSION: BCD encoding of the EHCI revision number supported by this host controller */ #define USB1_CAPLENGTH_HCIVERSION_SHIFT (8) #define USB1_CAPLENGTH_HCIVERSION_MASK \ (0xffff << USB1_CAPLENGTH_HCIVERSION_SHIFT) #define USB1_CAPLENGTH_HCIVERSION(x) ((x) << USB1_CAPLENGTH_HCIVERSION_SHIFT) /* --- USB1_HCSPARAMS values ------------------------------------ */ /* N_PORTS: Number of downstream ports */ #define USB1_HCSPARAMS_N_PORTS_SHIFT (0) #define USB1_HCSPARAMS_N_PORTS_MASK (0xf << USB1_HCSPARAMS_N_PORTS_SHIFT) #define USB1_HCSPARAMS_N_PORTS(x) ((x) << USB1_HCSPARAMS_N_PORTS_SHIFT) /* PPC: Port Power Control */ #define USB1_HCSPARAMS_PPC_SHIFT (4) #define USB1_HCSPARAMS_PPC (1 << USB1_HCSPARAMS_PPC_SHIFT) /* N_PCC: Number of Ports per Companion Controller */ #define USB1_HCSPARAMS_N_PCC_SHIFT (8) #define USB1_HCSPARAMS_N_PCC_MASK (0xf << USB1_HCSPARAMS_N_PCC_SHIFT) #define USB1_HCSPARAMS_N_PCC(x) ((x) << USB1_HCSPARAMS_N_PCC_SHIFT) /* N_CC: Number of Companion Controller */ #define USB1_HCSPARAMS_N_CC_SHIFT (12) #define USB1_HCSPARAMS_N_CC_MASK (0xf << USB1_HCSPARAMS_N_CC_SHIFT) #define USB1_HCSPARAMS_N_CC(x) ((x) << USB1_HCSPARAMS_N_CC_SHIFT) /* PI: Port indicators */ #define USB1_HCSPARAMS_PI_SHIFT (16) #define USB1_HCSPARAMS_PI (1 << USB1_HCSPARAMS_PI_SHIFT) /* N_PTT: Number of Ports per Transaction Translator */ #define USB1_HCSPARAMS_N_PTT_SHIFT (20) #define USB1_HCSPARAMS_N_PTT_MASK (0xf << USB1_HCSPARAMS_N_PTT_SHIFT) #define USB1_HCSPARAMS_N_PTT(x) ((x) << USB1_HCSPARAMS_N_PTT_SHIFT) /* N_TT: Number of Transaction Translators */ #define USB1_HCSPARAMS_N_TT_SHIFT (24) #define USB1_HCSPARAMS_N_TT_MASK (0xf << USB1_HCSPARAMS_N_TT_SHIFT) #define USB1_HCSPARAMS_N_TT(x) ((x) << USB1_HCSPARAMS_N_TT_SHIFT) /* --- USB1_HCCPARAMS values ------------------------------------ */ /* ADC: 64-bit Addressing Capability */ #define USB1_HCCPARAMS_ADC_SHIFT (0) #define USB1_HCCPARAMS_ADC (1 << USB1_HCCPARAMS_ADC_SHIFT) /* PFL: Programmable Frame List Flag */ #define USB1_HCCPARAMS_PFL_SHIFT (1) #define USB1_HCCPARAMS_PFL (1 << USB1_HCCPARAMS_PFL_SHIFT) /* ASP: Asynchronous Schedule Park Capability */ #define USB1_HCCPARAMS_ASP_SHIFT (2) #define USB1_HCCPARAMS_ASP (1 << USB1_HCCPARAMS_ASP_SHIFT) /* IST: Isochronous Scheduling Threshold */ #define USB1_HCCPARAMS_IST_SHIFT (4) #define USB1_HCCPARAMS_IST_MASK (0xf << USB1_HCCPARAMS_IST_SHIFT) #define USB1_HCCPARAMS_IST(x) ((x) << USB1_HCCPARAMS_IST_SHIFT) /* EECP: EHCI Extended Capabilities Pointer */ #define USB1_HCCPARAMS_EECP_SHIFT (8) #define USB1_HCCPARAMS_EECP_MASK (0xf << USB1_HCCPARAMS_EECP_SHIFT) #define USB1_HCCPARAMS_EECP(x) ((x) << USB1_HCCPARAMS_EECP_SHIFT) /* --- USB1_DCCPARAMS values ------------------------------------ */ /* DEN: Device Endpoint Number */ #define USB1_DCCPARAMS_DEN_SHIFT (0) #define USB1_DCCPARAMS_DEN_MASK (0x1f << USB1_DCCPARAMS_DEN_SHIFT) #define USB1_DCCPARAMS_DEN(x) ((x) << USB1_DCCPARAMS_DEN_SHIFT) /* DC: Device Capable */ #define USB1_DCCPARAMS_DC_SHIFT (7) #define USB1_DCCPARAMS_DC (1 << USB1_DCCPARAMS_DC_SHIFT) /* HC: Host Capable */ #define USB1_DCCPARAMS_HC_SHIFT (8) #define USB1_DCCPARAMS_HC (1 << USB1_DCCPARAMS_HC_SHIFT) /* --- USB1_USBCMD_D values ------------------------------------- */ /* RS: Run/Stop */ #define USB1_USBCMD_D_RS_SHIFT (0) #define USB1_USBCMD_D_RS (1 << USB1_USBCMD_D_RS_SHIFT) /* RST: Controller reset */ #define USB1_USBCMD_D_RST_SHIFT (1) #define USB1_USBCMD_D_RST (1 << USB1_USBCMD_D_RST_SHIFT) /* SUTW: Setup trip wire */ #define USB1_USBCMD_D_SUTW_SHIFT (13) #define USB1_USBCMD_D_SUTW (1 << USB1_USBCMD_D_SUTW_SHIFT) /* ATDTW: Add dTD trip wire */ #define USB1_USBCMD_D_ATDTW_SHIFT (14) #define USB1_USBCMD_D_ATDTW (1 << USB1_USBCMD_D_ATDTW_SHIFT) /* ITC: Interrupt threshold control */ #define USB1_USBCMD_D_ITC_SHIFT (16) #define USB1_USBCMD_D_ITC_MASK (0xff << USB1_USBCMD_D_ITC_SHIFT) #define USB1_USBCMD_D_ITC(x) ((x) << USB1_USBCMD_D_ITC_SHIFT) /* --- USB1_USBCMD_H values ------------------------------------- */ /* RS: Run/Stop */ #define USB1_USBCMD_H_RS_SHIFT (0) #define USB1_USBCMD_H_RS (1 << USB1_USBCMD_H_RS_SHIFT) /* RST: Controller reset */ #define USB1_USBCMD_H_RST_SHIFT (1) #define USB1_USBCMD_H_RST (1 << USB1_USBCMD_H_RST_SHIFT) /* FS0: Bit 0 of the Frame List Size bits */ #define USB1_USBCMD_H_FS0_SHIFT (2) #define USB1_USBCMD_H_FS0 (1 << USB1_USBCMD_H_FS0_SHIFT) /* FS1: Bit 1 of the Frame List Size bits */ #define USB1_USBCMD_H_FS1_SHIFT (3) #define USB1_USBCMD_H_FS1 (1 << USB1_USBCMD_H_FS1_SHIFT) /* PSE: This bit controls whether the host controller skips processing the periodic schedule */ #define USB1_USBCMD_H_PSE_SHIFT (4) #define USB1_USBCMD_H_PSE (1 << USB1_USBCMD_H_PSE_SHIFT) /* ASE: This bit controls whether the host controller skips processing the asynchronous schedule */ #define USB1_USBCMD_H_ASE_SHIFT (5) #define USB1_USBCMD_H_ASE (1 << USB1_USBCMD_H_ASE_SHIFT) /* IAA: This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule */ #define USB1_USBCMD_H_IAA_SHIFT (6) #define USB1_USBCMD_H_IAA (1 << USB1_USBCMD_H_IAA_SHIFT) /* ASP1_0: Asynchronous schedule park mode */ #define USB1_USBCMD_H_ASP1_0_SHIFT (8) #define USB1_USBCMD_H_ASP1_0_MASK (0x3 << USB1_USBCMD_H_ASP1_0_SHIFT) #define USB1_USBCMD_H_ASP1_0(x) ((x) << USB1_USBCMD_H_ASP1_0_SHIFT) /* ASPE: Asynchronous Schedule Park Mode Enable */ #define USB1_USBCMD_H_ASPE_SHIFT (11) #define USB1_USBCMD_H_ASPE (1 << USB1_USBCMD_H_ASPE_SHIFT) /* FS2: Bit 2 of the Frame List Size bits */ #define USB1_USBCMD_H_FS2_SHIFT (15) #define USB1_USBCMD_H_FS2 (1 << USB1_USBCMD_H_FS2_SHIFT) /* ITC: Interrupt threshold control */ #define USB1_USBCMD_H_ITC_SHIFT (16) #define USB1_USBCMD_H_ITC_MASK (0xff << USB1_USBCMD_H_ITC_SHIFT) #define USB1_USBCMD_H_ITC(x) ((x) << USB1_USBCMD_H_ITC_SHIFT) /* --- USB1_USBSTS_D values ------------------------------------- */ /* UI: USB interrupt */ #define USB1_USBSTS_D_UI_SHIFT (0) #define USB1_USBSTS_D_UI (1 << USB1_USBSTS_D_UI_SHIFT) /* UEI: USB error interrupt */ #define USB1_USBSTS_D_UEI_SHIFT (1) #define USB1_USBSTS_D_UEI (1 << USB1_USBSTS_D_UEI_SHIFT) /* PCI: Port change detect */ #define USB1_USBSTS_D_PCI_SHIFT (2) #define USB1_USBSTS_D_PCI (1 << USB1_USBSTS_D_PCI_SHIFT) /* URI: USB reset received */ #define USB1_USBSTS_D_URI_SHIFT (6) #define USB1_USBSTS_D_URI (1 << USB1_USBSTS_D_URI_SHIFT) /* SRI: SOF received */ #define USB1_USBSTS_D_SRI_SHIFT (7) #define USB1_USBSTS_D_SRI (1 << USB1_USBSTS_D_SRI_SHIFT) /* SLI: DCSuspend */ #define USB1_USBSTS_D_SLI_SHIFT (8) #define USB1_USBSTS_D_SLI (1 << USB1_USBSTS_D_SLI_SHIFT) /* NAKI: NAK interrupt bit */ #define USB1_USBSTS_D_NAKI_SHIFT (16) #define USB1_USBSTS_D_NAKI (1 << USB1_USBSTS_D_NAKI_SHIFT) /* --- USB1_USBSTS_H values ------------------------------------- */ /* UI: USB interrupt */ #define USB1_USBSTS_H_UI_SHIFT (0) #define USB1_USBSTS_H_UI (1 << USB1_USBSTS_H_UI_SHIFT) /* UEI: USB error interrupt */ #define USB1_USBSTS_H_UEI_SHIFT (1) #define USB1_USBSTS_H_UEI (1 << USB1_USBSTS_H_UEI_SHIFT) /* PCI: Port change detect */ #define USB1_USBSTS_H_PCI_SHIFT (2) #define USB1_USBSTS_H_PCI (1 << USB1_USBSTS_H_PCI_SHIFT) /* FRI: Frame list roll-over */ #define USB1_USBSTS_H_FRI_SHIFT (3) #define USB1_USBSTS_H_FRI (1 << USB1_USBSTS_H_FRI_SHIFT) /* AAI: Interrupt on async advance */ #define USB1_USBSTS_H_AAI_SHIFT (5) #define USB1_USBSTS_H_AAI (1 << USB1_USBSTS_H_AAI_SHIFT) /* SRI: SOF received */ #define USB1_USBSTS_H_SRI_SHIFT (7) #define USB1_USBSTS_H_SRI (1 << USB1_USBSTS_H_SRI_SHIFT) /* HCH: HCHalted */ #define USB1_USBSTS_H_HCH_SHIFT (12) #define USB1_USBSTS_H_HCH (1 << USB1_USBSTS_H_HCH_SHIFT) /* RCL: Reclamation */ #define USB1_USBSTS_H_RCL_SHIFT (13) #define USB1_USBSTS_H_RCL (1 << USB1_USBSTS_H_RCL_SHIFT) /* PS: Periodic schedule status */ #define USB1_USBSTS_H_PS_SHIFT (14) #define USB1_USBSTS_H_PS (1 << USB1_USBSTS_H_PS_SHIFT) /* AS: Asynchronous schedule status */ #define USB1_USBSTS_H_AS_SHIFT (15) #define USB1_USBSTS_H_AS (1 << USB1_USBSTS_H_AS_SHIFT) /* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */ #define USB1_USBSTS_H_UAI_SHIFT (18) #define USB1_USBSTS_H_UAI (1 << USB1_USBSTS_H_UAI_SHIFT) /* UPI: USB host periodic interrupt (USBHSTPERINT) */ #define USB1_USBSTS_H_UPI_SHIFT (19) #define USB1_USBSTS_H_UPI (1 << USB1_USBSTS_H_UPI_SHIFT) /* --- USB1_USBINTR_D values ------------------------------------ */ /* UE: USB interrupt enable */ #define USB1_USBINTR_D_UE_SHIFT (0) #define USB1_USBINTR_D_UE (1 << USB1_USBINTR_D_UE_SHIFT) /* UEE: USB error interrupt enable */ #define USB1_USBINTR_D_UEE_SHIFT (1) #define USB1_USBINTR_D_UEE (1 << USB1_USBINTR_D_UEE_SHIFT) /* PCE: Port change detect enable */ #define USB1_USBINTR_D_PCE_SHIFT (2) #define USB1_USBINTR_D_PCE (1 << USB1_USBINTR_D_PCE_SHIFT) /* URE: USB reset enable */ #define USB1_USBINTR_D_URE_SHIFT (6) #define USB1_USBINTR_D_URE (1 << USB1_USBINTR_D_URE_SHIFT) /* SRE: SOF received enable */ #define USB1_USBINTR_D_SRE_SHIFT (7) #define USB1_USBINTR_D_SRE (1 << USB1_USBINTR_D_SRE_SHIFT) /* SLE: Sleep enable */ #define USB1_USBINTR_D_SLE_SHIFT (8) #define USB1_USBINTR_D_SLE (1 << USB1_USBINTR_D_SLE_SHIFT) /* NAKE: NAK interrupt enable */ #define USB1_USBINTR_D_NAKE_SHIFT (16) #define USB1_USBINTR_D_NAKE (1 << USB1_USBINTR_D_NAKE_SHIFT) /* --- USB1_USBINTR_H values ------------------------------------ */ /* UE: USB interrupt enable */ #define USB1_USBINTR_H_UE_SHIFT (0) #define USB1_USBINTR_H_UE (1 << USB1_USBINTR_H_UE_SHIFT) /* UEE: USB error interrupt enable */ #define USB1_USBINTR_H_UEE_SHIFT (1) #define USB1_USBINTR_H_UEE (1 << USB1_USBINTR_H_UEE_SHIFT) /* PCE: Port change detect enable */ #define USB1_USBINTR_H_PCE_SHIFT (2) #define USB1_USBINTR_H_PCE (1 << USB1_USBINTR_H_PCE_SHIFT) /* FRE: Frame list rollover enable */ #define USB1_USBINTR_H_FRE_SHIFT (3) #define USB1_USBINTR_H_FRE (1 << USB1_USBINTR_H_FRE_SHIFT) /* AAE: Interrupt on asynchronous advance enable */ #define USB1_USBINTR_H_AAE_SHIFT (5) #define USB1_USBINTR_H_AAE (1 << USB1_USBINTR_H_AAE_SHIFT) /* SRE: SOF received enable */ #define USB1_USBINTR_H_SRE_SHIFT (7) #define USB1_USBINTR_H_SRE (1 << USB1_USBINTR_H_SRE_SHIFT) /* UAIE: USB host asynchronous interrupt enable */ #define USB1_USBINTR_H_UAIE_SHIFT (18) #define USB1_USBINTR_H_UAIE (1 << USB1_USBINTR_H_UAIE_SHIFT) /* UPIA: USB host periodic interrupt enable */ #define USB1_USBINTR_H_UPIA_SHIFT (19) #define USB1_USBINTR_H_UPIA (1 << USB1_USBINTR_H_UPIA_SHIFT) /* --- USB1_FRINDEX_D values ------------------------------------ */ /* FRINDEX2_0: Current micro frame number */ #define USB1_FRINDEX_D_FRINDEX2_0_SHIFT (0) #define USB1_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB1_FRINDEX_D_FRINDEX2_0_SHIFT) #define USB1_FRINDEX_D_FRINDEX2_0(x) ((x) << USB1_FRINDEX_D_FRINDEX2_0_SHIFT) /* FRINDEX13_3: Current frame number of the last frame transmitted */ #define USB1_FRINDEX_D_FRINDEX13_3_SHIFT (3) #define USB1_FRINDEX_D_FRINDEX13_3_MASK \ (0x7ff << USB1_FRINDEX_D_FRINDEX13_3_SHIFT) #define USB1_FRINDEX_D_FRINDEX13_3(x) ((x) << USB1_FRINDEX_D_FRINDEX13_3_SHIFT) /* --- USB1_FRINDEX_H values ------------------------------------ */ /* FRINDEX2_0: Current micro frame number */ #define USB1_FRINDEX_H_FRINDEX2_0_SHIFT (0) #define USB1_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB1_FRINDEX_H_FRINDEX2_0_SHIFT) #define USB1_FRINDEX_H_FRINDEX2_0(x) ((x) << USB1_FRINDEX_H_FRINDEX2_0_SHIFT) /* FRINDEX12_3: Frame list current index */ #define USB1_FRINDEX_H_FRINDEX12_3_SHIFT (3) #define USB1_FRINDEX_H_FRINDEX12_3_MASK \ (0x3ff << USB1_FRINDEX_H_FRINDEX12_3_SHIFT) #define USB1_FRINDEX_H_FRINDEX12_3(x) ((x) << USB1_FRINDEX_H_FRINDEX12_3_SHIFT) /* --- USB1_DEVICEADDR values ----------------------------------- */ /* USBADRA: Device address advance */ #define USB1_DEVICEADDR_USBADRA_SHIFT (24) #define USB1_DEVICEADDR_USBADRA (1 << USB1_DEVICEADDR_USBADRA_SHIFT) /* USBADR: USB device address */ #define USB1_DEVICEADDR_USBADR_SHIFT (25) #define USB1_DEVICEADDR_USBADR_MASK (0x7f << USB1_DEVICEADDR_USBADR_SHIFT) #define USB1_DEVICEADDR_USBADR(x) ((x) << USB1_DEVICEADDR_USBADR_SHIFT) /* --- USB1_PERIODICLISTBASE values ----------------------------- */ /* PERBASE31_12: Base Address (Low) */ #define USB1_PERIODICLISTBASE_PERBASE31_12_SHIFT (12) #define USB1_PERIODICLISTBASE_PERBASE31_12_MASK \ (0xfffff << USB1_PERIODICLISTBASE_PERBASE31_12_SHIFT) #define USB1_PERIODICLISTBASE_PERBASE31_12(x) \ ((x) << USB1_PERIODICLISTBASE_PERBASE31_12_SHIFT) /* --- USB1_ENDPOINTLISTADDR values ----------------------------- */ /* EPBASE31_11: Endpoint list pointer (low) */ #define USB1_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11) #define USB1_ENDPOINTLISTADDR_EPBASE31_11_MASK \ (0x1fffff << USB1_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) #define USB1_ENDPOINTLISTADDR_EPBASE31_11(x) \ ((x) << USB1_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) /* --- USB1_ASYNCLISTADDR values -------------------------------- */ /* ASYBASE31_5: Link pointer (Low) LPL */ #define USB1_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5) #define USB1_ASYNCLISTADDR_ASYBASE31_5_MASK \ (0x7ffffff << USB1_ASYNCLISTADDR_ASYBASE31_5_SHIFT) #define USB1_ASYNCLISTADDR_ASYBASE31_5(x) \ ((x) << USB1_ASYNCLISTADDR_ASYBASE31_5_SHIFT) /* --- USB1_TTCTRL values --------------------------------------- */ /* TTHA: Hub address when FS or LS device are connected directly */ #define USB1_TTCTRL_TTHA_SHIFT (24) #define USB1_TTCTRL_TTHA_MASK (0x7f << USB1_TTCTRL_TTHA_SHIFT) #define USB1_TTCTRL_TTHA(x) ((x) << USB1_TTCTRL_TTHA_SHIFT) /* --- USB1_BURSTSIZE values ------------------------------------ */ /* RXPBURST: Programmable RX burst length */ #define USB1_BURSTSIZE_RXPBURST_SHIFT (0) #define USB1_BURSTSIZE_RXPBURST_MASK (0xff << USB1_BURSTSIZE_RXPBURST_SHIFT) #define USB1_BURSTSIZE_RXPBURST(x) ((x) << USB1_BURSTSIZE_RXPBURST_SHIFT) /* TXPBURST: Programmable TX burst length */ #define USB1_BURSTSIZE_TXPBURST_SHIFT (8) #define USB1_BURSTSIZE_TXPBURST_MASK (0xff << USB1_BURSTSIZE_TXPBURST_SHIFT) #define USB1_BURSTSIZE_TXPBURST(x) ((x) << USB1_BURSTSIZE_TXPBURST_SHIFT) /* --- USB1_TXFILLTUNING values --------------------------------- */ /* TXSCHOH: FIFO burst threshold */ #define USB1_TXFILLTUNING_TXSCHOH_SHIFT (0) #define USB1_TXFILLTUNING_TXSCHOH_MASK (0xff << USB1_TXFILLTUNING_TXSCHOH_SHIFT) #define USB1_TXFILLTUNING_TXSCHOH(x) ((x) << USB1_TXFILLTUNING_TXSCHOH_SHIFT) /* TXSCHEATLTH: Scheduler health counter */ #define USB1_TXFILLTUNING_TXSCHEATLTH_SHIFT (8) #define USB1_TXFILLTUNING_TXSCHEATLTH_MASK \ (0x1f << USB1_TXFILLTUNING_TXSCHEATLTH_SHIFT) #define USB1_TXFILLTUNING_TXSCHEATLTH(x) \ ((x) << USB1_TXFILLTUNING_TXSCHEATLTH_SHIFT) /* TXFIFOTHRES: Scheduler overhead */ #define USB1_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) #define USB1_TXFILLTUNING_TXFIFOTHRES_MASK \ (0x3f << USB1_TXFILLTUNING_TXFIFOTHRES_SHIFT) #define USB1_TXFILLTUNING_TXFIFOTHRES(x) \ ((x) << USB1_TXFILLTUNING_TXFIFOTHRES_SHIFT) /* --- USB1_ULPIVIEWPORT values --------------------------------- */ /* ULPIDATWR: ULPI data write */ #define USB1_ULPIVIEWPORT_ULPIDATWR_SHIFT (0) #define USB1_ULPIVIEWPORT_ULPIDATWR_MASK \ (0xff << USB1_ULPIVIEWPORT_ULPIDATWR_SHIFT) #define USB1_ULPIVIEWPORT_ULPIDATWR(x) \ ((x) << USB1_ULPIVIEWPORT_ULPIDATWR_SHIFT) /* ULPIDATRD: ULPI data read */ #define USB1_ULPIVIEWPORT_ULPIDATRD_SHIFT (8) #define USB1_ULPIVIEWPORT_ULPIDATRD_MASK \ (0xff << USB1_ULPIVIEWPORT_ULPIDATRD_SHIFT) #define USB1_ULPIVIEWPORT_ULPIDATRD(x) \ ((x) << USB1_ULPIVIEWPORT_ULPIDATRD_SHIFT) /* ULPIADDR: ULPI read/write address */ #define USB1_ULPIVIEWPORT_ULPIADDR_SHIFT (16) #define USB1_ULPIVIEWPORT_ULPIADDR_MASK \ (0xff << USB1_ULPIVIEWPORT_ULPIADDR_SHIFT) #define USB1_ULPIVIEWPORT_ULPIADDR(x) \ ((x) << USB1_ULPIVIEWPORT_ULPIADDR_SHIFT) /* ULPIPORT: ULPI port - must be written as 0 */ #define USB1_ULPIVIEWPORT_ULPIPORT_SHIFT (24) #define USB1_ULPIVIEWPORT_ULPIPORT_MASK \ (0x7 << USB1_ULPIVIEWPORT_ULPIPORT_SHIFT) #define USB1_ULPIVIEWPORT_ULPIPORT(x) \ ((x) << USB1_ULPIVIEWPORT_ULPIPORT_SHIFT) /* ULPISS: ULPI sync state */ #define USB1_ULPIVIEWPORT_ULPISS_SHIFT (27) #define USB1_ULPIVIEWPORT_ULPISS_MASK \ (0x1 << USB1_ULPIVIEWPORT_ULPISS_SHIFT) #define USB1_ULPIVIEWPORT_ULPISS(x) \ ((x) << USB1_ULPIVIEWPORT_ULPISS_SHIFT) /* ULPIRW: ULPI read/write */ #define USB1_ULPIVIEWPORT_ULPIRW_SHIFT (29) #define USB1_ULPIVIEWPORT_ULPIRW_MASK \ (0x1 << USB1_ULPIVIEWPORT_ULPIRW_SHIFT) #define USB1_ULPIVIEWPORT_ULPIRW(x) \ ((x) << USB1_ULPIVIEWPORT_ULPIRW_SHIFT) /* ULPIRUN: ULPI read/write run */ #define USB1_ULPIVIEWPORT_ULPIRUN_SHIFT (30) #define USB1_ULPIVIEWPORT_ULPIRUN_MASK \ (0x1 << USB1_ULPIVIEWPORT_ULPIRUN_SHIFT) #define USB1_ULPIVIEWPORT_ULPIRUN(x) \ ((x) << USB1_ULPIVIEWPORT_ULPIRUN_SHIFT) /* ULPIWU: ULPI wake-up */ #define USB1_ULPIVIEWPORT_ULPIWU_SHIFT (31) #define USB1_ULPIVIEWPORT_ULPIWU_MASK \ (0x1 << USB1_ULPIVIEWPORT_ULPIWU_SHIFT) #define USB1_ULPIVIEWPORT_ULPIWU(x) \ ((x) << USB1_ULPIVIEWPORT_ULPIWU_SHIFT) /* --- USB1_BINTERVAL values ------------------------------------ */ /* BINT: bInterval value */ #define USB1_BINTERVAL_BINT_SHIFT (0) #define USB1_BINTERVAL_BINT_MASK (0xf << USB1_BINTERVAL_BINT_SHIFT) #define USB1_BINTERVAL_BINT(x) ((x) << USB1_BINTERVAL_BINT_SHIFT) /* --- USB1_ENDPTNAK values ------------------------------------- */ /* EPRN: Rx endpoint NAK */ #define USB1_ENDPTNAK_EPRN_SHIFT (0) #define USB1_ENDPTNAK_EPRN_MASK (0xf << USB1_ENDPTNAK_EPRN_SHIFT) #define USB1_ENDPTNAK_EPRN(x) ((x) << USB1_ENDPTNAK_EPRN_SHIFT) /* EPTN: Tx endpoint NAK */ #define USB1_ENDPTNAK_EPTN_SHIFT (16) #define USB1_ENDPTNAK_EPTN_MASK (0xf << USB1_ENDPTNAK_EPTN_SHIFT) #define USB1_ENDPTNAK_EPTN(x) ((x) << USB1_ENDPTNAK_EPTN_SHIFT) /* --- USB1_ENDPTNAKEN values ----------------------------------- */ /* EPRNE: Rx endpoint NAK enable */ #define USB1_ENDPTNAKEN_EPRNE_SHIFT (0) #define USB1_ENDPTNAKEN_EPRNE_MASK (0xf << USB1_ENDPTNAKEN_EPRNE_SHIFT) #define USB1_ENDPTNAKEN_EPRNE(x) ((x) << USB1_ENDPTNAKEN_EPRNE_SHIFT) /* EPTNE: Tx endpoint NAK */ #define USB1_ENDPTNAKEN_EPTNE_SHIFT (16) #define USB1_ENDPTNAKEN_EPTNE_MASK (0xf << USB1_ENDPTNAKEN_EPTNE_SHIFT) #define USB1_ENDPTNAKEN_EPTNE(x) ((x) << USB1_ENDPTNAKEN_EPTNE_SHIFT) /* --- USB1_PORTSC1_D values ------------------------------------ */ /* CCS: Current connect status */ #define USB1_PORTSC1_D_CCS_SHIFT (0) #define USB1_PORTSC1_D_CCS (1 << USB1_PORTSC1_D_CCS_SHIFT) /* PE: Port enable */ #define USB1_PORTSC1_D_PE_SHIFT (2) #define USB1_PORTSC1_D_PE (1 << USB1_PORTSC1_D_PE_SHIFT) /* PEC: Port enable/disable change */ #define USB1_PORTSC1_D_PEC_SHIFT (3) #define USB1_PORTSC1_D_PEC (1 << USB1_PORTSC1_D_PEC_SHIFT) /* FPR: Force port resume */ #define USB1_PORTSC1_D_FPR_SHIFT (6) #define USB1_PORTSC1_D_FPR (1 << USB1_PORTSC1_D_FPR_SHIFT) /* SUSP: Suspend */ #define USB1_PORTSC1_D_SUSP_SHIFT (7) #define USB1_PORTSC1_D_SUSP (1 << USB1_PORTSC1_D_SUSP_SHIFT) /* PR: Port reset */ #define USB1_PORTSC1_D_PR_SHIFT (8) #define USB1_PORTSC1_D_PR (1 << USB1_PORTSC1_D_PR_SHIFT) /* HSP: High-speed status */ #define USB1_PORTSC1_D_HSP_SHIFT (9) #define USB1_PORTSC1_D_HSP (1 << USB1_PORTSC1_D_HSP_SHIFT) /* PIC1_0: Port indicator control */ #define USB1_PORTSC1_D_PIC1_0_SHIFT (14) #define USB1_PORTSC1_D_PIC1_0_MASK (0x3 << USB1_PORTSC1_D_PIC1_0_SHIFT) #define USB1_PORTSC1_D_PIC1_0(x) ((x) << USB1_PORTSC1_D_PIC1_0_SHIFT) /* PTC3_0: Port test control */ #define USB1_PORTSC1_D_PTC3_0_SHIFT (16) #define USB1_PORTSC1_D_PTC3_0_MASK (0xf << USB1_PORTSC1_D_PTC3_0_SHIFT) #define USB1_PORTSC1_D_PTC3_0(x) ((x) << USB1_PORTSC1_D_PTC3_0_SHIFT) /* PHCD: PHY low power suspend - clock disable (PLPSCD) */ #define USB1_PORTSC1_D_PHCD_SHIFT (23) #define USB1_PORTSC1_D_PHCD (1 << USB1_PORTSC1_D_PHCD_SHIFT) /* PFSC: Port force full speed connect */ #define USB1_PORTSC1_D_PFSC_SHIFT (24) #define USB1_PORTSC1_D_PFSC (1 << USB1_PORTSC1_D_PFSC_SHIFT) /* PSPD: Port speed */ #define USB1_PORTSC1_D_PSPD_SHIFT (26) #define USB1_PORTSC1_D_PSPD_MASK (0x3 << USB1_PORTSC1_D_PSPD_SHIFT) #define USB1_PORTSC1_D_PSPD(x) ((x) << USB1_PORTSC1_D_PSPD_SHIFT) /* --- USB1_PORTSC1_H values ------------------------------------ */ /* CCS: Current connect status */ #define USB1_PORTSC1_H_CCS_SHIFT (0) #define USB1_PORTSC1_H_CCS (1 << USB1_PORTSC1_H_CCS_SHIFT) /* CSC: Connect status change */ #define USB1_PORTSC1_H_CSC_SHIFT (1) #define USB1_PORTSC1_H_CSC (1 << USB1_PORTSC1_H_CSC_SHIFT) /* PE: Port enable */ #define USB1_PORTSC1_H_PE_SHIFT (2) #define USB1_PORTSC1_H_PE (1 << USB1_PORTSC1_H_PE_SHIFT) /* PEC: Port disable/enable change */ #define USB1_PORTSC1_H_PEC_SHIFT (3) #define USB1_PORTSC1_H_PEC (1 << USB1_PORTSC1_H_PEC_SHIFT) /* OCA: Over-current active */ #define USB1_PORTSC1_H_OCA_SHIFT (4) #define USB1_PORTSC1_H_OCA (1 << USB1_PORTSC1_H_OCA_SHIFT) /* OCC: Over-current change */ #define USB1_PORTSC1_H_OCC_SHIFT (5) #define USB1_PORTSC1_H_OCC (1 << USB1_PORTSC1_H_OCC_SHIFT) /* FPR: Force port resume */ #define USB1_PORTSC1_H_FPR_SHIFT (6) #define USB1_PORTSC1_H_FPR (1 << USB1_PORTSC1_H_FPR_SHIFT) /* SUSP: Suspend */ #define USB1_PORTSC1_H_SUSP_SHIFT (7) #define USB1_PORTSC1_H_SUSP (1 << USB1_PORTSC1_H_SUSP_SHIFT) /* PR: Port reset */ #define USB1_PORTSC1_H_PR_SHIFT (8) #define USB1_PORTSC1_H_PR (1 << USB1_PORTSC1_H_PR_SHIFT) /* HSP: High-speed status */ #define USB1_PORTSC1_H_HSP_SHIFT (9) #define USB1_PORTSC1_H_HSP (1 << USB1_PORTSC1_H_HSP_SHIFT) /* LS: Line status */ #define USB1_PORTSC1_H_LS_SHIFT (10) #define USB1_PORTSC1_H_LS_MASK (0x3 << USB1_PORTSC1_H_LS_SHIFT) #define USB1_PORTSC1_H_LS(x) ((x) << USB1_PORTSC1_H_LS_SHIFT) /* PP: Port power control */ #define USB1_PORTSC1_H_PP_SHIFT (12) #define USB1_PORTSC1_H_PP (1 << USB1_PORTSC1_H_PP_SHIFT) /* PIC1_0: Port indicator control */ #define USB1_PORTSC1_H_PIC1_0_SHIFT (14) #define USB1_PORTSC1_H_PIC1_0_MASK (0x3 << USB1_PORTSC1_H_PIC1_0_SHIFT) #define USB1_PORTSC1_H_PIC1_0(x) ((x) << USB1_PORTSC1_H_PIC1_0_SHIFT) /* PTC3_0: Port test control */ #define USB1_PORTSC1_H_PTC3_0_SHIFT (16) #define USB1_PORTSC1_H_PTC3_0_MASK (0xf << USB1_PORTSC1_H_PTC3_0_SHIFT) #define USB1_PORTSC1_H_PTC3_0(x) ((x) << USB1_PORTSC1_H_PTC3_0_SHIFT) /* WKCN: Wake on connect enable (WKCNNT_E) */ #define USB1_PORTSC1_H_WKCN_SHIFT (20) #define USB1_PORTSC1_H_WKCN (1 << USB1_PORTSC1_H_WKCN_SHIFT) /* WKDC: Wake on disconnect enable (WKDSCNNT_E) */ #define USB1_PORTSC1_H_WKDC_SHIFT (21) #define USB1_PORTSC1_H_WKDC (1 << USB1_PORTSC1_H_WKDC_SHIFT) /* WKOC: Wake on over-current enable (WKOC_E) */ #define USB1_PORTSC1_H_WKOC_SHIFT (22) #define USB1_PORTSC1_H_WKOC (1 << USB1_PORTSC1_H_WKOC_SHIFT) /* PHCD: PHY low power suspend - clock disable (PLPSCD) */ #define USB1_PORTSC1_H_PHCD_SHIFT (23) #define USB1_PORTSC1_H_PHCD (1 << USB1_PORTSC1_H_PHCD_SHIFT) /* PFSC: Port force full speed connect */ #define USB1_PORTSC1_H_PFSC_SHIFT (24) #define USB1_PORTSC1_H_PFSC (1 << USB1_PORTSC1_H_PFSC_SHIFT) /* PSPD: Port speed */ #define USB1_PORTSC1_H_PSPD_SHIFT (26) #define USB1_PORTSC1_H_PSPD_MASK (0x3 << USB1_PORTSC1_H_PSPD_SHIFT) #define USB1_PORTSC1_H_PSPD(x) ((x) << USB1_PORTSC1_H_PSPD_SHIFT) /* --- USB1_USBMODE_D values ------------------------------------ */ /* CM1_0: Controller mode */ #define USB1_USBMODE_D_CM1_0_SHIFT (0) #define USB1_USBMODE_D_CM1_0_MASK (0x3 << USB1_USBMODE_D_CM1_0_SHIFT) #define USB1_USBMODE_D_CM1_0(x) ((x) << USB1_USBMODE_D_CM1_0_SHIFT) /* ES: Endian select */ #define USB1_USBMODE_D_ES_SHIFT (2) #define USB1_USBMODE_D_ES (1 << USB1_USBMODE_D_ES_SHIFT) /* SLOM: Setup Lockout mode */ #define USB1_USBMODE_D_SLOM_SHIFT (3) #define USB1_USBMODE_D_SLOM (1 << USB1_USBMODE_D_SLOM_SHIFT) /* SDIS: Setup Lockout mode */ #define USB1_USBMODE_D_SDIS_SHIFT (4) #define USB1_USBMODE_D_SDIS (1 << USB1_USBMODE_D_SDIS_SHIFT) /* --- USB1_USBMODE_H values ------------------------------------ */ /* CM: Controller mode */ #define USB1_USBMODE_H_CM_SHIFT (0) #define USB1_USBMODE_H_CM_MASK (0x3 << USB1_USBMODE_H_CM_SHIFT) #define USB1_USBMODE_H_CM(x) ((x) << USB1_USBMODE_H_CM_SHIFT) /* ES: Endian select */ #define USB1_USBMODE_H_ES_SHIFT (2) #define USB1_USBMODE_H_ES (1 << USB1_USBMODE_H_ES_SHIFT) /* SDIS: Stream disable mode */ #define USB1_USBMODE_H_SDIS_SHIFT (4) #define USB1_USBMODE_H_SDIS (1 << USB1_USBMODE_H_SDIS_SHIFT) /* VBPS: VBUS power select */ #define USB1_USBMODE_H_VBPS_SHIFT (5) #define USB1_USBMODE_H_VBPS (1 << USB1_USBMODE_H_VBPS_SHIFT) /* --- USB1_ENDPTSETUPSTAT values ------------------------------- */ /* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 3 */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0) #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK \ (0xf << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \ ((x) << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) /* --- USB1_ENDPTPRIME values ----------------------------------- */ /* PERB: Prime endpoint receive buffer for physical OUT endpoints 3 to 0 */ #define USB1_ENDPTPRIME_PERB_SHIFT (0) #define USB1_ENDPTPRIME_PERB_MASK (0xf << USB1_ENDPTPRIME_PERB_SHIFT) #define USB1_ENDPTPRIME_PERB(x) ((x) << USB1_ENDPTPRIME_PERB_SHIFT) /* PETB: Prime endpoint transmit buffer for physical IN endpoints 3 to 0 */ #define USB1_ENDPTPRIME_PETB_SHIFT (16) #define USB1_ENDPTPRIME_PETB_MASK (0xf << USB1_ENDPTPRIME_PETB_SHIFT) #define USB1_ENDPTPRIME_PETB(x) ((x) << USB1_ENDPTPRIME_PETB_SHIFT) /* --- USB1_ENDPTFLUSH values ----------------------------------- */ /* FERB: Flush endpoint receive buffer for physical OUT endpoints 3 to 0 */ #define USB1_ENDPTFLUSH_FERB_SHIFT (0) #define USB1_ENDPTFLUSH_FERB_MASK (0xf << USB1_ENDPTFLUSH_FERB_SHIFT) #define USB1_ENDPTFLUSH_FERB(x) ((x) << USB1_ENDPTFLUSH_FERB_SHIFT) /* FETB: Flush endpoint transmit buffer for physical IN endpoints 3 to 0 */ #define USB1_ENDPTFLUSH_FETB_SHIFT (16) #define USB1_ENDPTFLUSH_FETB_MASK (0xf << USB1_ENDPTFLUSH_FETB_SHIFT) #define USB1_ENDPTFLUSH_FETB(x) ((x) << USB1_ENDPTFLUSH_FETB_SHIFT) /* --- USB1_ENDPTSTAT values ------------------------------------ */ /* ERBR: Endpoint receive buffer ready for physical OUT endpoints 3 to 0 */ #define USB1_ENDPTSTAT_ERBR_SHIFT (0) #define USB1_ENDPTSTAT_ERBR_MASK (0xf << USB1_ENDPTSTAT_ERBR_SHIFT) #define USB1_ENDPTSTAT_ERBR(x) ((x) << USB1_ENDPTSTAT_ERBR_SHIFT) /* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */ #define USB1_ENDPTSTAT_ETBR_SHIFT (16) #define USB1_ENDPTSTAT_ETBR_MASK (0xf << USB1_ENDPTSTAT_ETBR_SHIFT) #define USB1_ENDPTSTAT_ETBR(x) ((x) << USB1_ENDPTSTAT_ETBR_SHIFT) /* --- USB1_ENDPTCOMPLETE values -------------------------------- */ /* ERCE: Endpoint receive complete event for physical OUT endpoints 3 to 0 */ #define USB1_ENDPTCOMPLETE_ERCE_SHIFT (0) #define USB1_ENDPTCOMPLETE_ERCE_MASK (0xf << USB1_ENDPTCOMPLETE_ERCE_SHIFT) #define USB1_ENDPTCOMPLETE_ERCE(x) ((x) << USB1_ENDPTCOMPLETE_ERCE_SHIFT) /* ETCE: Endpoint transmit complete event for physical IN endpoints 3 to 0 */ #define USB1_ENDPTCOMPLETE_ETCE_SHIFT (16) #define USB1_ENDPTCOMPLETE_ETCE_MASK (0xf << USB1_ENDPTCOMPLETE_ETCE_SHIFT) #define USB1_ENDPTCOMPLETE_ETCE(x) ((x) << USB1_ENDPTCOMPLETE_ETCE_SHIFT) /* --- USB1_ENDPTCTRL0 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB1_ENDPTCTRL0_RXS_SHIFT (0) #define USB1_ENDPTCTRL0_RXS (1 << USB1_ENDPTCTRL0_RXS_SHIFT) /* RXT1_0: Endpoint type */ #define USB1_ENDPTCTRL0_RXT1_0_SHIFT (2) #define USB1_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB1_ENDPTCTRL0_RXT1_0_SHIFT) #define USB1_ENDPTCTRL0_RXT1_0(x) ((x) << USB1_ENDPTCTRL0_RXT1_0_SHIFT) /* RXE: Rx endpoint enable */ #define USB1_ENDPTCTRL0_RXE_SHIFT (7) #define USB1_ENDPTCTRL0_RXE (1 << USB1_ENDPTCTRL0_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB1_ENDPTCTRL0_TXS_SHIFT (16) #define USB1_ENDPTCTRL0_TXS (1 << USB1_ENDPTCTRL0_TXS_SHIFT) /* TXT1_0: Endpoint type */ #define USB1_ENDPTCTRL0_TXT1_0_SHIFT (18) #define USB1_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB1_ENDPTCTRL0_TXT1_0_SHIFT) #define USB1_ENDPTCTRL0_TXT1_0(x) ((x) << USB1_ENDPTCTRL0_TXT1_0_SHIFT) /* TXE: Tx endpoint enable */ #define USB1_ENDPTCTRL0_TXE_SHIFT (23) #define USB1_ENDPTCTRL0_TXE (1 << USB1_ENDPTCTRL0_TXE_SHIFT) /* --- USB1_ENDPTCTRL1 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB1_ENDPTCTRL1_RXS_SHIFT (0) #define USB1_ENDPTCTRL1_RXS (1 << USB1_ENDPTCTRL1_RXS_SHIFT) /* RXT: Endpoint type */ #define USB1_ENDPTCTRL1_RXT_SHIFT (2) #define USB1_ENDPTCTRL1_RXT_MASK (0x3 << USB1_ENDPTCTRL1_RXT_SHIFT) #define USB1_ENDPTCTRL1_RXT(x) ((x) << USB1_ENDPTCTRL1_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB1_ENDPTCTRL1_RXI_SHIFT (5) #define USB1_ENDPTCTRL1_RXI (1 << USB1_ENDPTCTRL1_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB1_ENDPTCTRL1_RXR_SHIFT (6) #define USB1_ENDPTCTRL1_RXR (1 << USB1_ENDPTCTRL1_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB1_ENDPTCTRL1_RXE_SHIFT (7) #define USB1_ENDPTCTRL1_RXE (1 << USB1_ENDPTCTRL1_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB1_ENDPTCTRL1_TXS_SHIFT (16) #define USB1_ENDPTCTRL1_TXS (1 << USB1_ENDPTCTRL1_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB1_ENDPTCTRL1_TXT1_0_SHIFT (18) #define USB1_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB1_ENDPTCTRL1_TXT1_0_SHIFT) #define USB1_ENDPTCTRL1_TXT1_0(x) ((x) << USB1_ENDPTCTRL1_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB1_ENDPTCTRL1_TXI_SHIFT (21) #define USB1_ENDPTCTRL1_TXI (1 << USB1_ENDPTCTRL1_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB1_ENDPTCTRL1_TXR_SHIFT (22) #define USB1_ENDPTCTRL1_TXR (1 << USB1_ENDPTCTRL1_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB1_ENDPTCTRL1_TXE_SHIFT (23) #define USB1_ENDPTCTRL1_TXE (1 << USB1_ENDPTCTRL1_TXE_SHIFT) /* --- USB1_ENDPTCTRL2 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB1_ENDPTCTRL2_RXS_SHIFT (0) #define USB1_ENDPTCTRL2_RXS (1 << USB1_ENDPTCTRL2_RXS_SHIFT) /* RXT: Endpoint type */ #define USB1_ENDPTCTRL2_RXT_SHIFT (2) #define USB1_ENDPTCTRL2_RXT_MASK (0x3 << USB1_ENDPTCTRL2_RXT_SHIFT) #define USB1_ENDPTCTRL2_RXT(x) ((x) << USB1_ENDPTCTRL2_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB1_ENDPTCTRL2_RXI_SHIFT (5) #define USB1_ENDPTCTRL2_RXI (1 << USB1_ENDPTCTRL2_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB1_ENDPTCTRL2_RXR_SHIFT (6) #define USB1_ENDPTCTRL2_RXR (1 << USB1_ENDPTCTRL2_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB1_ENDPTCTRL2_RXE_SHIFT (7) #define USB1_ENDPTCTRL2_RXE (1 << USB1_ENDPTCTRL2_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB1_ENDPTCTRL2_TXS_SHIFT (16) #define USB1_ENDPTCTRL2_TXS (1 << USB1_ENDPTCTRL2_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB1_ENDPTCTRL2_TXT1_0_SHIFT (18) #define USB1_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB1_ENDPTCTRL2_TXT1_0_SHIFT) #define USB1_ENDPTCTRL2_TXT1_0(x) ((x) << USB1_ENDPTCTRL2_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB1_ENDPTCTRL2_TXI_SHIFT (21) #define USB1_ENDPTCTRL2_TXI (1 << USB1_ENDPTCTRL2_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB1_ENDPTCTRL2_TXR_SHIFT (22) #define USB1_ENDPTCTRL2_TXR (1 << USB1_ENDPTCTRL2_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB1_ENDPTCTRL2_TXE_SHIFT (23) #define USB1_ENDPTCTRL2_TXE (1 << USB1_ENDPTCTRL2_TXE_SHIFT) /* --- USB1_ENDPTCTRL3 values ----------------------------------- */ /* RXS: Rx endpoint stall */ #define USB1_ENDPTCTRL3_RXS_SHIFT (0) #define USB1_ENDPTCTRL3_RXS (1 << USB1_ENDPTCTRL3_RXS_SHIFT) /* RXT: Endpoint type */ #define USB1_ENDPTCTRL3_RXT_SHIFT (2) #define USB1_ENDPTCTRL3_RXT_MASK (0x3 << USB1_ENDPTCTRL3_RXT_SHIFT) #define USB1_ENDPTCTRL3_RXT(x) ((x) << USB1_ENDPTCTRL3_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB1_ENDPTCTRL3_RXI_SHIFT (5) #define USB1_ENDPTCTRL3_RXI (1 << USB1_ENDPTCTRL3_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB1_ENDPTCTRL3_RXR_SHIFT (6) #define USB1_ENDPTCTRL3_RXR (1 << USB1_ENDPTCTRL3_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB1_ENDPTCTRL3_RXE_SHIFT (7) #define USB1_ENDPTCTRL3_RXE (1 << USB1_ENDPTCTRL3_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB1_ENDPTCTRL3_TXS_SHIFT (16) #define USB1_ENDPTCTRL3_TXS (1 << USB1_ENDPTCTRL3_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB1_ENDPTCTRL3_TXT1_0_SHIFT (18) #define USB1_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB1_ENDPTCTRL3_TXT1_0_SHIFT) #define USB1_ENDPTCTRL3_TXT1_0(x) ((x) << USB1_ENDPTCTRL3_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB1_ENDPTCTRL3_TXI_SHIFT (21) #define USB1_ENDPTCTRL3_TXI (1 << USB1_ENDPTCTRL3_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB1_ENDPTCTRL3_TXR_SHIFT (22) #define USB1_ENDPTCTRL3_TXR (1 << USB1_ENDPTCTRL3_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB1_ENDPTCTRL3_TXE_SHIFT (23) #define USB1_ENDPTCTRL3_TXE (1 << USB1_ENDPTCTRL3_TXE_SHIFT) /* -------------------------------------------------------------- */ /* --- USB1_ENDPTCTRL common values ----------------------------- */ /* RXS: Rx endpoint stall */ #define USB1_ENDPTCTRL_RXS_SHIFT (0) #define USB1_ENDPTCTRL_RXS (1 << USB1_ENDPTCTRL_RXS_SHIFT) /* RXT: Endpoint type */ #define USB1_ENDPTCTRL_RXT_SHIFT (2) #define USB1_ENDPTCTRL_RXT_MASK (0x3 << USB1_ENDPTCTRL_RXT_SHIFT) #define USB1_ENDPTCTRL_RXT(x) ((x) << USB1_ENDPTCTRL_RXT_SHIFT) /* RXI: Rx data toggle inhibit */ #define USB1_ENDPTCTRL_RXI_SHIFT (5) #define USB1_ENDPTCTRL_RXI (1 << USB1_ENDPTCTRL_RXI_SHIFT) /* RXR: Rx data toggle reset */ #define USB1_ENDPTCTRL_RXR_SHIFT (6) #define USB1_ENDPTCTRL_RXR (1 << USB1_ENDPTCTRL_RXR_SHIFT) /* RXE: Rx endpoint enable */ #define USB1_ENDPTCTRL_RXE_SHIFT (7) #define USB1_ENDPTCTRL_RXE (1 << USB1_ENDPTCTRL_RXE_SHIFT) /* TXS: Tx endpoint stall */ #define USB1_ENDPTCTRL_TXS_SHIFT (16) #define USB1_ENDPTCTRL_TXS (1 << USB1_ENDPTCTRL_TXS_SHIFT) /* TXT1_0: Tx Endpoint type */ #define USB1_ENDPTCTRL_TXT1_0_SHIFT (18) #define USB1_ENDPTCTRL_TXT1_0_MASK (0x3 << USB1_ENDPTCTRL_TXT1_0_SHIFT) #define USB1_ENDPTCTRL_TXT1_0(x) ((x) << USB1_ENDPTCTRL_TXT1_0_SHIFT) /* TXI: Tx data toggle inhibit */ #define USB1_ENDPTCTRL_TXI_SHIFT (21) #define USB1_ENDPTCTRL_TXI (1 << USB1_ENDPTCTRL_TXI_SHIFT) /* TXR: Tx data toggle reset */ #define USB1_ENDPTCTRL_TXR_SHIFT (22) #define USB1_ENDPTCTRL_TXR (1 << USB1_ENDPTCTRL_TXR_SHIFT) /* TXE: Tx endpoint enable */ #define USB1_ENDPTCTRL_TXE_SHIFT (23) #define USB1_ENDPTCTRL_TXE (1 << USB1_ENDPTCTRL_TXE_SHIFT) #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/lpc43xx/wwdt.h000066400000000000000000000044711435536612600236200ustar00rootroot00000000000000/** @defgroup wwdt_defines Windowed Watchdog Timer @brief Defined Constants and Types for the LPC43xx Windowed Watchdog Timer @ingroup LPC43xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LPC43XX_WWDT_H #define LPC43XX_WWDT_H /**@{*/ #include #include #ifdef __cplusplus extern "C" { #endif /* --- Windowed Watchdog Timer (WWDT) registers ---------------------------- */ /* Watchdog mode register */ #define WWDT_MOD MMIO32(WWDT_BASE + 0x000) #define WWDT_MOD_WDEN (1<<0) #define WWDT_MOD_WDRESET (1<<1) #define WWDT_MOD_WDTOF (1<<2) #define WWDT_MOD_WDINT (1<<3) #define WWDT_MOD_WDPROTECT (1<<4) /* Watchdog timer constant register */ #define WWDT_TC MMIO32(WWDT_BASE + 0x004) /* Watchdog feed sequence register */ #define WWDT_FEED MMIO32(WWDT_BASE + 0x008) #define WWDT_FEED_SEQUENCE WWDT_FEED = 0xAA; WWDT_FEED = 0x55 /* Watchdog timer value register */ #define WWDT_TV MMIO32(WWDT_BASE + 0x00C) /* Watchdog warning interrupt register */ #define WWDT_WARNINT MMIO32(WWDT_BASE + 0x014) /* Watchdog timer window register */ #define WWDT_WINDOW MMIO32(WWDT_BASE + 0x018) /**@}*/ /* Reset LPC4330 in timeout*4 clock cycles (min 256, max 2^24) */ void wwdt_reset(uint32_t timeout); #ifdef __cplusplus } #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/000077500000000000000000000000001435536612600217275ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/3n/000077500000000000000000000000001435536612600222475ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/3n/irq.yaml000066400000000000000000000006471435536612600237350ustar00rootroot00000000000000includeguard: LIBOPENCM3_SAM3N_NVIC_H partname_humanreadable: Atmel SAM3N series partname_doxygen: SAM3N irqs: - supc - rstc - rtc - rtt - wdg - pmc - eefc0 - reserved0 - uart0 - uart1 - reserved1 - pioa - piob - pioc - usart0 - usart1 - reserved2 - reserved3 - reserved4 - twi0 - twi1 - spi - reserved5 - tc0 - tc1 - tc2 - tc3 - tc4 - tc5 - adc - dacc - pwm hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/3n/memorymap.h000066400000000000000000000037631435536612600244370ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3N_MEMORYMAP_H #define SAM3N_MEMORYMAP_H #include /* --- SAM3N peripheral space -------------------------------------------- */ #define SPI_BASE (0x40008000) #define TC0_BASE (0x40010000) #define TC1_BASE (0x40010040) #define TC2_BASE (0x40010080) #define TC3_BASE (0x40014000) #define TC4_BASE (0x40014040) #define TC5_BASE (0x40014080) #define TWI0_BASE (0x40018000) #define TWI1_BASE (0x4001C000) #define PWM_BASE (0x40020000) #define USART0_BASE (0x40024000) #define USART1_BASE (0x40028000) #define ADC_BASE (0x40038000) #define DACC_BASE (0x4003C000) /* --- SAM3N system controller space ------------------------------------- */ #define SMC_BASE (0x400E0000) #define MATRIX_BASE (0x400E0200) #define PMC_BASE (0x400E0400) #define UART0_BASE (0x400E0600) #define CHIPID_BASE (0x400E0740) #define UART1_BASE (0x400E0800) #define EEFC_BASE (0x400E0A00) #define PIOA_BASE (0x400E0E00) #define PIOB_BASE (0x400E1000) #define PIOC_BASE (0x400E1200) #define RSTC_BASE (0x400E1400) #define SUPC_BASE (0x400E1410) #define RTT_BASE (0x400E1430) #define WDT_BASE (0x400E1450) #define RTC_BASE (0x400E1460) #define GPBR_BASE (0x400E1490) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/3x/000077500000000000000000000000001435536612600222615ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/3x/irq.yaml000066400000000000000000000010111435536612600237310ustar00rootroot00000000000000includeguard: LIBOPENCM3_SAM3X_NVIC_H partname_humanreadable: Atmel SAM3X series partname_doxygen: SAM3X irqs: - supc - rstc - rtc - rtt - wdg - pmc - eefc0 - eefc1 - uart - smc_sdramc - sdramc - pioa - piob - pioc - piod - pioe - piof - usart0 - usart1 - usart2 - usart3 - hsmci - twi0 - twi1 - spi0 - spi1 - ssc - tc0 - tc1 - tc2 - tc3 - tc4 - tc5 - tc6 - tc7 - tc8 - pwm - adc - dacc - dmac - uotghs - trng - emac - can0 - can1 hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/3x/memorymap.h000066400000000000000000000051111435536612600244360ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_MEMORYMAP_H #define SAM3X_MEMORYMAP_H #include /* --- SAM3X peripheral space -------------------------------------------- */ #define HSMCI_BASE (0x40000000) #define SSC_BASE (0x40004000) #define SPI0_BASE (0x40008000) #define SPI1_BASE (0x4000C000) #define TC0_BASE (0x40080000) #define TC1_BASE (0x40080040) #define TC2_BASE (0x40080080) #define TC3_BASE (0x40084000) #define TC4_BASE (0x40084040) #define TC5_BASE (0x40084080) #define TC6_BASE (0x40088000) #define TC7_BASE (0x40088040) #define TC8_BASE (0x40088080) #define TWI0_BASE (0x4008C000) #define TWI1_BASE (0x40090000) #define PWM_BASE (0x40094000) #define USART0_BASE (0x40098000) #define USART1_BASE (0x4009C000) #define USART2_BASE (0x400A0000) #define USART3_BASE (0x400A4000) #define UOTGHS_BASE (0x400AC000) #define EMAC_BASE (0x400B0000) #define CAN0_BASE (0x400B4000) #define CAN1_BASE (0x400B8000) #define TRNG_BASE (0x400BC000) #define ADC_BASE (0x400C0000) #define DMAC_BASE (0x400C4000) /* --- SAM3X system controller space ------------------------------------- */ #define SMC_BASE (0x400E0000) #define SDRAM_BASE (0x400E0200) #define MATRIX_BASE (0x400E0400) #define PMC_BASE (0x400E0600) #define UART_BASE (0x400E0800) #define CHIPID_BASE (0x400E0940) #define EEFC0_BASE (0x400E0A00) #define EEFC1_BASE (0x400E0C00) #define PIOA_BASE (0x400E0E00) #define PIOB_BASE (0x400E1000) #define PIOC_BASE (0x400E1200) #define PIOD_BASE (0x400E1400) #define PIOE_BASE (0x400E1600) #define PIOF_BASE (0x400E1800) #define RSTC_BASE (0x400E1A00) #define SUPC_BASE (0x400E1A10) #define RTT_BASE (0x400E1A30) #define WDT_BASE (0x400E1A50) #define RTC_BASE (0x400E1A60) #define GPBR_BASE (0x400E1A90) #define RTC_BASE (0x400E1A60) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/eefc.h000066400000000000000000000054161435536612600230100ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_EEFC_H #define SAM3X_EEFC_H #include #include /* --- Convenience macros ------------------------------------------------ */ #define EEFC EEFC_BASE #define EEFC0 EEFC0_BASE #define EEFC1 EEFC1_BASE /* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */ #define EEFC_FMR(port) MMIO32((port) + 0x00) #define EEFC_FCR(port) MMIO32((port) + 0x04) #define EEFC_FSR(port) MMIO32((port) + 0x08) #define EEFC_FRR(port) MMIO32((port) + 0x0C) /* 0x0010 - Reserved */ /* EEFC Flash Mode Register (EEFC_FMR) */ /* Bit [31:25] - Reserved */ #define EEFC_FMR_FAM (0x01 << 24) /* Bit [23:12] - Reserved */ #define EEFC_FMR_FWS_MASK (0x0F << 8) /* Bit [7:1] - Reserved */ #define EEFC_FMR_FRDY (0x01 << 0) /* EEFC Flash Command Register (EEFC_FCR) */ #define EEFC_FCR_FKEY (0x5A << 24) #define EEFC_FCR_FARG_MASK (0xFFFF << 8) #define EEFC_FCR_FCMD_MASK (0xFF << 0) #define EEFC_FCR_FCMD_GETD (0x00 << 0) #define EEFC_FCR_FCMD_WP (0x01 << 0) #define EEFC_FCR_FCMD_WPL (0x02 << 0) #define EEFC_FCR_FCMD_EWP (0x03 << 0) #define EEFC_FCR_FCMD_EWPL (0x04 << 0) #define EEFC_FCR_FCMD_EA (0x05 << 0) #define EEFC_FCR_FCMD_SLB (0x08 << 0) #define EEFC_FCR_FCMD_CLB (0x09 << 0) #define EEFC_FCR_FCMD_GLB (0x0A << 0) #define EEFC_FCR_FCMD_SGPB (0x0B << 0) #define EEFC_FCR_FCMD_CGPB (0x0C << 0) #define EEFC_FCR_FCMD_GGPB (0x0D << 0) #define EEFC_FCR_FCMD_STUI (0x0E << 0) #define EEFC_FCR_FCMD_SPUI (0x0F << 0) /* EEFC Flash Status Register (EEFC_FSR) */ /* Bit [31:3] - Reserved */ #define EEFC_FSR_FLOCKE (0x01 << 2) #define EEFC_FSR_FCMDE (0x01 << 1) #define EEFC_FSR_FRDY (0x01 << 0) static inline void eefc_set_latency(uint8_t wait) { #if defined(SAM3X) EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8); EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8); #elif defined(SAM3N) EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8); #endif } #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/gpio.h000066400000000000000000000026671435536612600230510ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_GPIO_H #define SAM3X_GPIO_H #include /* flags may be or'd together, but only contain one of * GPOUTPUT, PERIPHA and PERIPHB */ enum gpio_flags { GPIO_FLAG_GPINPUT = 0, GPIO_FLAG_GPOUTPUT = 1, GPIO_FLAG_PERIPHA = 2, GPIO_FLAG_PERIPHB = 3, GPIO_FLAG_OPEN_DRAIN = 4, GPIO_FLAG_PULL_UP = 8, }; void gpio_init(uint32_t gpioport, uint32_t pins, enum gpio_flags flags); static inline void gpio_set(uint32_t gpioport, uint32_t gpios) { PIO_SODR(gpioport) = gpios; } static inline void gpio_clear(uint32_t gpioport, uint32_t gpios) { PIO_CODR(gpioport) = gpios; } void gpio_toggle(uint32_t gpioport, uint32_t gpios); #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/memorymap.h000066400000000000000000000020051435536612600241030ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM_MEMORYMAP_H #define SAM_MEMORYMAP_H #if defined(SAM3X) # include #elif defined(SAM3N) # include #else # error "Processor family not defined." #endif #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/pio.h000066400000000000000000000072371435536612600227000ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM_PIO_H #define SAM_PIO_H #include #include /* --- Convenience macros ------------------------------------------------ */ /* GPIO port base addresses (for convenience) */ #define PIOA PIOA_BASE #define PIOB PIOB_BASE #define PIOC PIOC_BASE #define PIOD PIOD_BASE #define PIOE PIOE_BASE #define PIOF PIOF_BASE #define PIOG PIOG_BASE #define PIOH PIOH_BASE /* --- PIO registers ----------------------------------------------------- */ #define PIO_PER(port) MMIO32((port) + 0x0000) #define PIO_PDR(port) MMIO32((port) + 0x0004) #define PIO_PSR(port) MMIO32((port) + 0x0008) /* 0x000C - Reserved */ #define PIO_OER(port) MMIO32((port) + 0x0010) #define PIO_ODR(port) MMIO32((port) + 0x0014) #define PIO_OSR(port) MMIO32((port) + 0x0018) /* 0x001C - Reserved */ #define PIO_IFER(port) MMIO32((port) + 0x0020) #define PIO_IFDR(port) MMIO32((port) + 0x0024) #define PIO_IFSR(port) MMIO32((port) + 0x0028) /* 0x002C - Reserved */ #define PIO_SODR(port) MMIO32((port) + 0x0030) #define PIO_CODR(port) MMIO32((port) + 0x0034) #define PIO_ODSR(port) MMIO32((port) + 0x0038) #define PIO_PDSR(port) MMIO32((port) + 0x003C) #define PIO_IER(port) MMIO32((port) + 0x0040) #define PIO_IDR(port) MMIO32((port) + 0x0044) #define PIO_IMR(port) MMIO32((port) + 0x0048) #define PIO_ISR(port) MMIO32((port) + 0x004C) #define PIO_MDER(port) MMIO32((port) + 0x0050) #define PIO_MDDR(port) MMIO32((port) + 0x0054) #define PIO_MDSR(port) MMIO32((port) + 0x0058) /* 0x005C - Reserved */ #define PIO_PUDR(port) MMIO32((port) + 0x0060) #define PIO_PUER(port) MMIO32((port) + 0x0064) #define PIO_PUSR(port) MMIO32((port) + 0x0068) /* 0x006C - Reserved */ #define PIO_ABSR(port) MMIO32((port) + 0x0070) /* 0x0074-0x007C - Reserved */ #define PIO_SCIFSR(port) MMIO32((port) + 0x0080) #define PIO_DIFSR(port) MMIO32((port) + 0x0084) #define PIO_IFDGSR(port) MMIO32((port) + 0x0088) #define PIO_SCDR(port) MMIO32((port) + 0x008C) /* 0x0090-0x009C - Reserved */ #define PIO_OWER(port) MMIO32((port) + 0x00A0) #define PIO_OWDR(port) MMIO32((port) + 0x00A4) #define PIO_OWSR(port) MMIO32((port) + 0x00A8) /* 0x00AC - Reserved */ #define PIO_AIMER(port) MMIO32((port) + 0x00B0) #define PIO_AIMDR(port) MMIO32((port) + 0x00B4) #define PIO_AIMMR(port) MMIO32((port) + 0x00B8) /* 0x00BC - Reserved */ #define PIO_ESR(port) MMIO32((port) + 0x00C0) #define PIO_LSR(port) MMIO32((port) + 0x00C4) #define PIO_ELSR(port) MMIO32((port) + 0x00C8) /* 0x00CC - Reserved */ #define PIO_FELLSR(port) MMIO32((port) + 0x00D0) #define PIO_REHLSR(port) MMIO32((port) + 0x00D4) #define PIO_FRLHSR(port) MMIO32((port) + 0x00D8) /* 0x00DC - Reserved */ #define PIO_LOCKSR(port) MMIO32((port) + 0x00E0) #define PIO_WPMR(port) MMIO32((port) + 0x00E4) #define PIO_WPSR(port) MMIO32((port) + 0x00E8) /* 0x00EC-0x0144 - Reserved */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/pmc.h000066400000000000000000000117401435536612600226620ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_PMC_H #define SAM3X_PMC_H #include #include /* --- Power Management Controller (PMC) registers ----------------------- */ #define PMC_SCER MMIO32(PMC_BASE + 0x0000) #define PMC_SCDR MMIO32(PMC_BASE + 0x0004) #define PMC_SCSR MMIO32(PMC_BASE + 0x0008) /* 0x000C - Reserved */ #define PMC_PCER0 MMIO32(PMC_BASE + 0x0010) #define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014) #define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018) #define CKGR_UCKR MMIO32(PMC_BASE + 0x001C) #define CKGR_MOR MMIO32(PMC_BASE + 0x0020) #define CKGR_MCFR MMIO32(PMC_BASE + 0x0024) #define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028) /* 0x002C - Reserved */ #define PMC_MCKR MMIO32(PMC_BASE + 0x0030) /* 0x0034 - Reserved */ #define PMC_USB MMIO32(PMC_BASE + 0x0038) /* 0x003C - Reserved */ #define PMC_PCK0 MMIO32(PMC_BASE + 0x0040) #define PMC_PCK1 MMIO32(PMC_BASE + 0x0044) #define PMC_PCK2 MMIO32(PMC_BASE + 0x0048) /* 0x004C-0x005C - Reserved */ #define PMC_IER MMIO32(PMC_BASE + 0x0060) #define PMC_IDR MMIO32(PMC_BASE + 0x0064) #define PMC_SR MMIO32(PMC_BASE + 0x0068) #define PMC_IMR MMIO32(PMC_BASE + 0x006C) #define PMC_FSMR MMIO32(PMC_BASE + 0x0070) #define PMC_FSPR MMIO32(PMC_BASE + 0x0074) #define PMC_FOCR MMIO32(PMC_BASE + 0x0078) /* 0x007C-0x00E0 - Reserved */ #define PMC_WPMR MMIO32(PMC_BASE + 0x00E4) #define PMC_WPSR MMIO32(PMC_BASE + 0x00E8) /* 0x00EC-0x00FC - Reserved */ #define PMC_PCER1 MMIO32(PMC_BASE + 0x0100) #define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104) #define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108) #define PMC_PCR MMIO32(PMC_BASE + 0x010C) /* PMC UTMI Clock Configuration Register (CKGR_UCKR) */ /* Bit [31:22] - Reserved */ #define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20) /* Bit [19:17] - Reserved */ #define CKGR_CKGR_UPLLEN (0x01 << 16) /* Bit [15:0] - Reserved */ /* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */ /* Bit [31:26] - Reserved */ #define CKGR_MOR_CFDEN (0x01 << 25) #define CKGR_MOR_MOSCSEL (0x01 << 24) #define CKGR_MOR_KEY (0x37 << 16) #define CKGR_MOR_MOSCXTST_MASK (0xFF << 8) /* Bit 7 - Reserved */ #define CKGR_MOR_MOSCRCF_MASK (0x07 << 4) #define CKGR_MOR_MOSCRCEN (0x01 << 3) /* Bit 2 - Reserved */ #define CKGR_MOR_MOSCXTBY (0x01 << 1) #define CKGR_MOR_MOSCXTEN (0x01 << 0) /* PMC Clock Generator PLLA Register (CKGR_PLLAR) */ #define CKGR_PLLAR_ONE (0x01 << 29) #define CKGR_PLLAR_MULA_MASK (0x7FF << 16) #define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8) #define CKGR_PLLAR_DIVA_MASK (0xFF << 0) /* PMC Master Clock Register (PMC_MCKR) */ /* Bit [31:14] - Reserved */ #define PMC_MCKR_UPLLDIV2 (0x01 << 13) #define PMC_MCKR_PLLADIV2 (0x01 << 12) /* Bit [11:7] - Reserved */ #define PMC_MCKR_PRES_MASK (0x07 << 4) /* Bit [3:2] - Reserved */ #define PMC_MCKR_CSS_MASK (0x03 << 0) #define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0) #define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0) #define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0) #define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0) /* PMC USB Clock Register (PMC_USB) */ /* Bit [31:12] - Reserved */ #define PMC_USB_USBDIV_MASK (0x0F << 8) /* Bit [7:1] - Reserved */ #define PMC_USB_USBS (0x01 << 0) /* PMC Status Register (PMC_SR) */ /* Bits [31:21] - Reserved */ #define PMC_SR_FOS (0x01 << 20) #define PMC_SR_CFDS (0x01 << 19) #define PMC_SR_CFDEV (0x01 << 18) #define PMC_SR_MOSCRCS (0x01 << 17) #define PMC_SR_MOSCSELS (0x01 << 16) /* Bits [15:11] - Reserved */ #define PMC_SR_PCKRDY2 (0x01 << 10) #define PMC_SR_PCKRDY1 (0x01 << 9) #define PMC_SR_PCKRDY0 (0x01 << 8) #define PMC_SR_OSCSELS (0x01 << 7) #define PMC_SR_LOCKU (0x01 << 6) /* Bits [5:4] - Reserved */ #define PMC_SR_MCKRDY (0x01 << 3) /* Bit [2] - Reserved */ #define PMC_SR_LOCKA (0x01 << 1) #define PMC_SR_MOSCXTS (0x01 << 0) extern uint32_t pmc_mck_frequency; enum mck_src { MCK_SRC_SLOW = 0, MCK_SRC_MAIN = 1, MCK_SRC_PLLA = 2, MCK_SRC_UPLL = 3, }; void pmc_mck_set_source(enum mck_src src); void pmc_xtal_enable(bool en, uint8_t startup_time); void pmc_plla_config(uint8_t mul, uint8_t div); void pmc_peripheral_clock_enable(uint8_t pid); void pmc_peripheral_clock_disable(uint8_t pid); void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void); void pmc_clock_setup_in_rc_4mhz_out_84mhz(void); #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/pwm.h000066400000000000000000000076121435536612600227110ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_PWM_H #define SAM3X_PWM_H #include #include /* --- Pulse Width Modulation (PWM) registers ----------------------- */ #define PWM_CLK MMIO32(PWM_BASE + 0x0000) #define PWM_ENA MMIO32(PWM_BASE + 0x0004) #define PWM_DIS MMIO32(PWM_BASE + 0x0008) #define PWM_SR MMIO32(PWM_BASE + 0x000C) #define PWM_IER1 MMIO32(PWM_BASE + 0x0010) #define PWM_IDR1 MMIO32(PWM_BASE + 0x0014) #define PWM_IMR1 MMIO32(PWM_BASE + 0x0018) #define PWM_ISR1 MMIO32(PWM_BASE + 0x001C) #define PWM_SCM MMIO32(PWM_BASE + 0x0020) /* 0x0024 - Reserved */ #define PWM_SCUC MMIO32(PWM_BASE + 0x0028) #define PWM_SCUP MMIO32(PWM_BASE + 0x002C) #define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030) #define PWM_IER2 MMIO32(PWM_BASE + 0x0034) #define PWM_IDR2 MMIO32(PWM_BASE + 0x0038) #define PWM_IMR2 MMIO32(PWM_BASE + 0x003C) #define PWM_ISR2 MMIO32(PWM_BASE + 0x0040) #define PWM_OOV MMIO32(PWM_BASE + 0x0044) #define PWM_OS MMIO32(PWM_BASE + 0x0048) #define PWM_OSS MMIO32(PWM_BASE + 0x004C) #define PWM_OSC MMIO32(PWM_BASE + 0x0050) #define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054) #define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058) #define PWM_FMR MMIO32(PWM_BASE + 0x005C) #define PWM_FSR MMIO32(PWM_BASE + 0x0060) #define PWM_FCR MMIO32(PWM_BASE + 0x0064) #define PWM_FPV MMIO32(PWM_BASE + 0x0068) #define PWM_FPE1 MMIO32(PWM_BASE + 0x006C) #define PWM_FPE2 MMIO32(PWM_BASE + 0x0070) /* 0x0074:0x0078 - Reserved */ #define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C) #define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080) /* 0x0084:0x00AC - Reserved */ #define PWM_SMMR MMIO32(PWM_BASE + 0x00B0) /* 0x00B4:0x00E0 - Reserved */ #define PWM_WPCR MMIO32(PWM_BASE + 0x00E4) #define PWM_WPSR MMIO32(PWM_BASE + 0x00E8) /* 0x00EC:0x00FC - Reserved */ /* 0x0100:0x012C - Reserved */ #define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x)) #define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x)) #define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x)) #define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x)) /* 0x01B0:0x01FC - Reserved */ #define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x)) #define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x)) #if defined(SAM3X) # define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) # define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) # define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) # define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x)) # define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x)) # define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x)) #elif defined(SAM3N) # define PWM_CPRD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) # define PWM_CCNT(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) # define PWM_CUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) #else # error "Processor family not defined." #endif static inline void pwm_set_period(int ch, uint32_t period) { PWM_CPRD(ch) = period; } static inline void pwm_set_duty(int ch, uint32_t duty) { PWM_CDTY(ch) = duty; } static inline void pwm_enable(int ch) { PWM_ENA = 1 << ch; } static inline void pwm_disable(int ch) { PWM_DIS = 1 << ch; } #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/tc.h000066400000000000000000000040001435536612600225000ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_TC_H #define SAM3X_TC_H #include #include /* --- Timer Counter (TC) registers -------------------------------------- */ #define TC_CCR(x) MMIO32(TC_BASE + 0x00 + 0x40*(x)) #define TC_CMR(x) MMIO32(TC_BASE + 0x04 + 0x40*(x)) #define TC_SMMR(x) MMIO32(TC_BASE + 0x08 + 0x40*(x)) /* 0x0C + 0x40*channel - Reserved */ #define TC_CV(x) MMIO32(TC_BASE + 0x10 + 0x40*(x)) #define TC_RA(x) MMIO32(TC_BASE + 0x14 + 0x40*(x)) #define TC_RB(x) MMIO32(TC_BASE + 0x18 + 0x40*(x)) #define TC_RC(x) MMIO32(TC_BASE + 0x1C + 0x40*(x)) #define TC_SR(x) MMIO32(TC_BASE + 0x20 + 0x40*(x)) #define TC_IER(x) MMIO32(TC_BASE + 0x24 + 0x40*(x)) #define TC_IDR(x) MMIO32(TC_BASE + 0x28 + 0x40*(x)) #define TC_IMR(x) MMIO32(TC_BASE + 0x2C + 0x40*(x)) #define TC_BCR MMIO32(TC_BASE + 0xC0) #define TC_BMR MMIO32(TC_BASE + 0xC4) #define TC_QIER MMIO32(TC_BASE + 0xC8) #define TC_QIDR MMIO32(TC_BASE + 0xCC) #define TC_QIMR MMIO32(TC_BASE + 0xD0) #define TC_QISR MMIO32(TC_BASE + 0xD4) #define TC_FMR MMIO32(TC_BASE + 0xD8) /* 0x00DC:0x00E0 - Undocumented */ #define TC_WPMR MMIO32(TC_BASE + 0xE4) /* 0x00E8:0x00F8 - Undocumented */ /* 0x00FC - Reserved */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/uart.h000066400000000000000000000056051435536612600230610ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_UART_H #define SAM3X_UART_H #include #include /* --- Universal Asynchronous Receiver Transmitter (UART) registers ------- */ #define UART_CR MMIO32(UART_BASE + 0x0000) #define UART_MR MMIO32(UART_BASE + 0x0004) #define UART_IER MMIO32(UART_BASE + 0x0008) #define UART_IDR MMIO32(UART_BASE + 0x000C) #define UART_IMR MMIO32(UART_BASE + 0x0010) #define UART_SR MMIO32(UART_BASE + 0x0014) #define UART_RHR MMIO32(UART_BASE + 0x0018) #define UART_THR MMIO32(UART_BASE + 0x001C) #define UART_BRGR MMIO32(UART_BASE + 0x0020) /* 0x0024:0x003C - Reserved */ /* 0x004C:0x00FC - Reserved */ /* 0x0100:0x0124 - PDC Area */ /* UART Control Register (UART_CR) */ /* Bits [31:9] - Reserved */ #define UART_CR_RSTSTA (0x01 << 8) #define UART_CR_TXDIS (0x01 << 7) #define UART_CR_TXEN (0x01 << 6) #define UART_CR_RXDIS (0x01 << 5) #define UART_CR_RXEN (0x01 << 4) #define UART_CR_RSTTX (0x01 << 3) #define UART_CR_RSTRX (0x01 << 2) /* Bit [1:0] - Reserved */ /* UART Mode Register (UART_MR) */ /* Bits [31:16] - Reserved */ #define UART_MR_CHMODE_MASK (0x03 << 14) #define UART_MR_CHMODE_NORMAL (0x00 << 14) #define UART_MR_CHMODE_AUTOMATIC (0x01 << 14) #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) /* Bits [13:12] - Reserved */ #define UART_MR_PAR_MASK (0x07 << 9) #define UART_MR_PAR_EVEN (0x00 << 9) #define UART_MR_PAR_ODD (0x01 << 9) #define UART_MR_PAR_SPACE (0x02 << 9) #define UART_MR_PAR_MARK (0x03 << 9) #define UART_MR_PAR_NO (0x04 << 9) /* Bits [8:0] - Reserved */ /* UART Status Register (UART_SR) */ /* Bits [31:13] - Reserved */ #define UART_SR_RXBUFF (0x01 << 12) #define UART_SR_TXBUFF (0x01 << 11) /* Bit [10] - Reserved */ #define UART_SR_TXEMPTY (0x01 << 9) /* Bit [8] - Reserved */ #define UART_SR_PARE (0x01 << 7) #define UART_SR_FRAME (0x01 << 6) #define UART_SR_OVRE (0x01 << 5) #define UART_SR_ENDTX (0x01 << 4) #define UART_SR_ENDRX (0x01 << 3) /* Bit [2] - Reserved */ #define UART_SR_TXRDY (0x01 << 1) #define UART_SR_RXRDY (0x01 << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/usart.h000066400000000000000000000166721435536612600232520ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_USART_H #define SAM3X_USART_H #include #include #define USART0 USART0_BASE #define USART1 USART1_BASE #define USART2 USART2_BASE #define USART3 USART3_BASE /* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */ #define USART_CR(x) MMIO32((x) + 0x0000) #define USART_MR(x) MMIO32((x) + 0x0004) #define USART_IER(x) MMIO32((x) + 0x0008) #define USART_IDR(x) MMIO32((x) + 0x000C) #define USART_IMR(x) MMIO32((x) + 0x0010) #define USART_CSR(x) MMIO32((x) + 0x0014) #define USART_RHR(x) MMIO32((x) + 0x0018) #define USART_THR(x) MMIO32((x) + 0x001C) #define USART_BRGR(x) MMIO32((x) + 0x0020) #define USART_RTOR(x) MMIO32((x) + 0x0024) #define USART_TTGR(x) MMIO32((x) + 0x0028) /* 0x002C:0x003C - Reserved */ #define USART_FIDI(x) MMIO32((x) + 0x0040) #define USART_NER(x) MMIO32((x) + 0x0044) #define USART_NER(x) MMIO32((x) + 0x0044) /* 0x0048 - Reserved */ #define USART_IF(x) MMIO32((x) + 0x004C) #define USART_MAN(x) MMIO32((x) + 0x0050) #define USART_LINMR(x) MMIO32((x) + 0x0054) #define USART_LINIR(x) MMIO32((x) + 0x0058) /* 0x005C:0x00E0 - Reserved */ #define USART_WPMR(x) MMIO32((x) + 0x00E4) #define USART_WPSR(x) MMIO32((x) + 0x00E8) /* 0x00EC:0x00F8 - Reserved */ #define USART_VERSION(x) MMIO32((x) + 0x00FC) /* 0x0100:0x0124 - PDC Area */ /* USART Control Register (USART_CR) */ /* Bits [31:22] - Reserved */ #define USART_CR_LINWKUP (0x01 << 21) #define USART_CR_LINABT (0x01 << 20) #define USART_CR_RTSDIS (0x01 << 19) #define USART_CR_RCS (0x01 << 19) #define USART_CR_RTSEN (0x01 << 18) #define USART_CR_FCS (0x01 << 18) /* Bits [17:16] - Reserved */ #define USART_CR_RETTO (0x01 << 15) #define USART_CR_RSTNACK (0x01 << 14) #define USART_CR_RSTIT (0x01 << 13) #define USART_CR_SENDA (0x01 << 12) #define USART_CR_STTTO (0x01 << 11) #define USART_CR_STPBRK (0x01 << 10) #define USART_CR_STTBRK (0x01 << 9) #define USART_CR_RSTSTA (0x01 << 8) #define USART_CR_TXDIS (0x01 << 7) #define USART_CR_TXEN (0x01 << 6) #define USART_CR_RXDIS (0x01 << 5) #define USART_CR_RXEN (0x01 << 4) #define USART_CR_RSTTX (0x01 << 3) #define USART_CR_RSTRX (0x01 << 2) /* Bits [1:0] - Reserved */ /* USART Mode Register (USART_MR) */ #define USART_MR_ONEBIT (0x01 << 31) #define USART_MR_MODSYNC (0x01 << 30) #define USART_MR_MAN (0x01 << 29) #define USART_MR_FILTER (0x01 << 28) /* Bit [27] - Reserved */ #define USART_MR_MAX_ITERATION_MASK (0x07 << 24) #define USART_MR_INVDATA (0x01 << 23) #define USART_MR_VAR_SYNC (0x01 << 22) #define USART_MR_DSNACK (0x01 << 21) #define USART_MR_INACK (0x01 << 20) #define USART_MR_OVER (0x01 << 19) #define USART_MR_CLKO (0x01 << 18) #define USART_MR_MODE9 (0x01 << 17) #define USART_MR_MSBF (0x01 << 16) #define USART_MR_CPOL (0x01 << 16) #define USART_MR_CHMODE_MASK (0x03 << 14) #define USART_MR_CHMODE_NORMAL (0x00 << 14) #define USART_MR_CHMODE_AUTOMATIC (0x01 << 14) #define USART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) #define USART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) #define USART_MR_NBSTOP_MASK (0x03 << 12) #define USART_MR_NBSTOP_1_BIT (0x00 << 12) #define USART_MR_NBSTOP_1_5_BIT (0x01 << 12) #define USART_MR_NBSTOP_2_BIT (0x02 << 12) /* Bits [13:12] - Reserved */ #define USART_MR_PAR_MASK (0x07 << 9) #define USART_MR_PAR_EVEN (0x00 << 9) #define USART_MR_PAR_ODD (0x01 << 9) #define USART_MR_PAR_SPACE (0x02 << 9) #define USART_MR_PAR_MARK (0x03 << 9) #define USART_MR_PAR_NO (0x04 << 9) /* Bits [8:0] - Reserved */ #define USART_MR_SYNC (0x01 << 8) #define USART_MR_CPHA (0x01 << 8) #define USART_MR_CHRL_MASK (0x03 << 6) #define USART_MR_CHRL_5BIT (0x00 << 6) #define USART_MR_CHRL_6BIT (0x01 << 6) #define USART_MR_CHRL_7BIT (0x02 << 6) #define USART_MR_CHRL_8BIT (0x03 << 6) #define USART_MR_USCLKS_MASK (0x03 << 4) #define USART_MR_USCLKS_MCK (0x00 << 4) #define USART_MR_USCLKS_DIV (0x01 << 4) #define USART_MR_USCLKS_SCK (0x03 << 4) #define USART_MR_MODE_MASK (0x0F << 0) #define USART_MR_MODE_NORMAL (0x00 << 0) #define USART_MR_MODE_RS485 (0x01 << 0) #define USART_MR_MODE_HW_HANDSHAKING (0x02 << 0) #define USART_MR_MODE_ISO7816_T_0 (0x03 << 0) #define USART_MR_MODE_ISO7816_T_1 (0x04 << 0) #define USART_MR_MODE_IRDA (0x06 << 0) #define USART_MR_MODE_LIN_MASTER (0x0A << 0) #define USART_MR_MODE_LIN_SLAVE (0x0B << 0) #define USART_MR_MODE_SPI_MASTER (0x0E << 0) #define USART_MR_MODE_SPI_SLAVE (0x0F << 0) /* USART Status Register (USART_CSR) */ /* Bits [31:30] - Reserved */ #define USART_CSR_LINSNRE (0x01 << 29) #define USART_CSR_LINCE (0x01 << 28) #define USART_CSR_LINIPE (0x01 << 27) #define USART_CSR_LINSFE (0x01 << 26) #define USART_CSR_LINBE (0x01 << 25) #define USART_CSR_MANERR (0x01 << 24) #define USART_CSR_CTS (0x01 << 23) #define USART_CSR_LINBLS (0x01 << 23) /* Bits [22:20] - Reserved */ #define USART_CSR_CTSIC (0x01 << 19) /* Bits [18:16] - Reserved */ #define USART_CSR_LINTC (0x01 << 15) #define USART_CSR_LINID (0x01 << 14) #define USART_CSR_NACK (0x01 << 13) #define USART_CSR_LINBK (0x01 << 13) #define USART_CSR_RXBUFF (0x01 << 12) #define USART_CSR_TXBUFE (0x01 << 11) /* Bit [10] - Reserved */ #define USART_CSR_TXEMPTY (0x01 << 9) /* Bit [8] - Reserved */ #define USART_CSR_PARE (0x01 << 7) #define USART_CSR_FRAME (0x01 << 6) #define USART_CSR_OVRE (0x01 << 5) #define USART_CSR_ENDTX (0x01 << 4) #define USART_CSR_ENDRX (0x01 << 3) /* Bit [2] - Reserved */ #define USART_CSR_TXRDY (0x01 << 1) #define USART_CSR_RXRDY (0x01 << 0) enum usart_stopbits { USART_STOPBITS_1, USART_STOPBITS_1_5, USART_STOPBITS_2, }; enum usart_parity { USART_PARITY_EVEN, USART_PARITY_ODD, USART_PARITY_SPACE, USART_PARITY_MARK, USART_PARITY_NONE, USART_PARITY_MULTIDROP, }; enum usart_mode { USART_MODE_DISABLED, USART_MODE_RX, USART_MODE_TX, USART_MODE_TX_RX, }; enum usart_flowcontrol { USART_FLOWCONTROL_NONE, USART_FLOWCONTROL_RTS_CTS, }; void usart_set_baudrate(uint32_t usart, uint32_t baud); void usart_set_databits(uint32_t usart, int bits); void usart_set_stopbits(uint32_t usart, enum usart_stopbits); void usart_set_parity(uint32_t usart, enum usart_parity); void usart_set_mode(uint32_t usart, enum usart_mode); void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol); void usart_enable(uint32_t usart); void usart_disable(uint32_t usart); void usart_send(uint32_t usart, uint16_t data); uint16_t usart_recv(uint32_t usart); void usart_wait_send_ready(uint32_t usart); void usart_wait_recv_ready(uint32_t usart); void usart_send_blocking(uint32_t usart, uint16_t data); uint16_t usart_recv_blocking(uint32_t usart); void usart_enable_rx_interrupt(uint32_t usart); void usart_disable_rx_interrupt(uint32_t usart); #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/sam/wdt.h000066400000000000000000000035211435536612600226770ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef SAM3X_WDT_H #define SAM3X_WDT_H #include #include /* --- WDT registers ----------------------------------------------------- */ #define WDT_CR MMIO32(WDT_BASE + 0x00) #define WDT_MR MMIO32(WDT_BASE + 0x04) #define WDT_SR MMIO32(WDT_BASE + 0x08) /* --- WDT_CR values ------------------------------------------------------ */ #define WDT_CR_KEY (0xA5 << 24) /* Bits [23:1]: Reserved. */ #define WDT_CR_WDRSTT (1 << 0) /* --- WDT_MR values ------------------------------------------------------ */ /* Bits [31:32]: Reserved. */ #define WDT_MR_WDIDLEHLT (1 << 29) #define WDT_MR_WDDBGHLT (1 << 28) #define WDT_MR_WDD_MASK (0xFFF << 16) #define WDT_MR_WDDIS (1 << 15) #define WDT_MR_WDRPROC (1 << 14) #define WDT_MR_WDRSTEN (1 << 13) #define WDT_MR_WDFIEN (1 << 12) #define WDT_MR_WDV_MASK (0xFFF << 0) /* --- WDT_SR values ------------------------------------------------------ */ /* Bits [31:2]: Reserved. */ #define WDT_SR_WDERR (1 << 1) #define WDT_SR_WDUNF (1 << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/000077500000000000000000000000001435536612600221175ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/adc.h000066400000000000000000000021311435536612600230140ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/can.h000066400000000000000000000477421435536612600230470ustar00rootroot00000000000000/** @defgroup can_defines CAN defines @ingroup STM32F_defines @brief libopencm3 Defined Constants and Types for STM32 CAN @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski @date 12 November 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CAN_H #define LIBOPENCM3_CAN_H #include #include /**@{*/ /* --- Convenience macros -------------------------------------------------- */ /* CAN register base addresses (for convenience) */ /*****************************************************************************/ /** @defgroup can_reg_base CAN register base address @ingroup can_defines @{*/ #define CAN1 BX_CAN1_BASE #define CAN2 BX_CAN2_BASE /**@}*/ /* --- CAN registers ------------------------------------------------------- */ /* CAN master control register (CAN_MCR) */ #define CAN_MCR(can_base) MMIO32(can_base + 0x000) /* CAN master status register (CAN_MSR) */ #define CAN_MSR(can_base) MMIO32(can_base + 0x004) /* CAN transmit status register (CAN_TSR) */ #define CAN_TSR(can_base) MMIO32(can_base + 0x008) /* CAN receive FIFO 0 register (CAN_RF0R) */ #define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) /* CAN receive FIFO 1 register (CAN_RF1R) */ #define CAN_RF1R(can_base) MMIO32(can_base + 0x010) /* CAN interrupt enable register (CAN_IER) */ #define CAN_IER(can_base) MMIO32(can_base + 0x014) /* CAN error status register (CAN_ESR) */ #define CAN_ESR(can_base) MMIO32(can_base + 0x018) /* CAN bit timing register (CAN_BTR) */ #define CAN_BTR(can_base) MMIO32(can_base + 0x01C) /* Registers in the offset range 0x020 to 0x17F are reserved. */ /* --- CAN mailbox registers ----------------------------------------------- */ /* CAN mailbox / FIFO register offsets */ #define CAN_MBOX0 0x180 #define CAN_MBOX1 0x190 #define CAN_MBOX2 0x1A0 #define CAN_FIFO0 0x1B0 #define CAN_FIFO1 0x1C0 /* CAN TX mailbox identifier register (CAN_TIxR) */ #define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) #define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) #define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) #define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) /* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ #define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) #define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) #define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) #define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) /* CAN mailbox data low register (CAN_TDLxR) */ #define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) #define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) #define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) #define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) /* CAN mailbox data high register (CAN_TDHxR) */ #define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) #define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) #define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) #define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) /* CAN RX FIFO identifier register (CAN_RIxR) */ #define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) #define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) #define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) /* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ #define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) #define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) #define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) /* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ #define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) #define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) #define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) /* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ #define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) #define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) #define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) /* --- CAN filter registers ------------------------------------------------ */ /* CAN filter master register (CAN_FMR) */ #define CAN_FMR(can_base) MMIO32(can_base + 0x200) /* CAN filter mode register (CAN_FM1R) */ #define CAN_FM1R(can_base) MMIO32(can_base + 0x204) /* Register offset 0x208 is reserved. */ /* CAN filter scale register (CAN_FS1R) */ #define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) /* Register offset 0x210 is reserved. */ /* CAN filter FIFO assignement register (CAN_FFA1R) */ #define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) /* Register offset 0x218 is reserved. */ /* CAN filter activation register (CAN_FA1R) */ #define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) /* Register offset 0x220 is reserved. */ /* Registers with offset 0x224 to 0x23F are reserved. */ /* CAN filter bank registers (CAN_FiRx) */ /* * Connectivity line devices have 28 banks so the bank ID spans 0..27 * all other devices have 14 banks so the bank ID spans 0..13. */ #define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \ (bank * 0x8) + 0x0) #define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \ (bank * 0x8) + 0x4) /* --- CAN_MCR values ------------------------------------------------------ */ /* 31:17 Reserved, forced by hardware to 0 */ /* DBF: Debug freeze */ #define CAN_MCR_DBF (1 << 16) /* RESET: bxCAN software master reset */ #define CAN_MCR_RESET (1 << 15) /* 14:8 Reserved, forced by hardware to 0 */ /* TTCM: Time triggered communication mode */ #define CAN_MCR_TTCM (1 << 7) /* ABOM: Automatic bus-off management */ #define CAN_MCR_ABOM (1 << 6) /* AWUM: Automatic wakeup mode */ #define CAN_MCR_AWUM (1 << 5) /* NART: No automatic retransmission */ #define CAN_MCR_NART (1 << 4) /* RFLM: Receive FIFO locked mode */ #define CAN_MCR_RFLM (1 << 3) /* TXFP: Transmit FIFO priority */ #define CAN_MCR_TXFP (1 << 2) /* SLEEP: Sleep mode request */ #define CAN_MCR_SLEEP (1 << 1) /* INRQ: Initialization request */ #define CAN_MCR_INRQ (1 << 0) /* --- CAN_MSR values ------------------------------------------------------ */ /* 31:12 Reserved, forced by hardware to 0 */ /* RX: CAN Rx signal */ #define CAN_MSR_RX (1 << 11) /* SAMP: Last sample point */ #define CAN_MSR_SAMP (1 << 10) /* RXM: Receive mode */ #define CAN_MSR_RXM (1 << 9) /* TXM: Transmit mode */ #define CAN_MSR_TXM (1 << 8) /* 7:5 Reserved, forced by hardware to 0 */ /* SLAKI: Sleep acknowledge interrupt */ #define CAN_MSR_SLAKI (1 << 4) /* WKUI: Wakeup interrupt */ #define CAN_MSR_WKUI (1 << 3) /* ERRI: Error interrupt */ #define CAN_MSR_ERRI (1 << 2) /* SLAK: Sleep acknowledge */ #define CAN_MSR_SLAK (1 << 1) /* INAK: Initialization acknowledge */ #define CAN_MSR_INAK (1 << 0) /* --- CAN_TSR values ------------------------------------------------------ */ /* LOW2: Lowest priority flag for mailbox 2 */ #define CAN_TSR_LOW2 (1 << 31) /* LOW1: Lowest priority flag for mailbox 1 */ #define CAN_TSR_LOW1 (1 << 30) /* LOW0: Lowest priority flag for mailbox 0 */ #define CAN_TSR_LOW0 (1 << 29) /* TME2: Transmit mailbox 2 empty */ #define CAN_TSR_TME2 (1 << 28) /* TME1: Transmit mailbox 1 empty */ #define CAN_TSR_TME1 (1 << 27) /* TME0: Transmit mailbox 0 empty */ #define CAN_TSR_TME0 (1 << 26) /* CODE[1:0]: Mailbox code */ #define CAN_TSR_CODE_MASK (0x3 << 24) /* ABRQ2: Abort request for mailbox 2 */ #define CAN_TSR_TABRQ2 (1 << 23) /* 22:20 Reserved, forced by hardware to 0 */ /* TERR2: Transmission error for mailbox 2 */ #define CAN_TSR_TERR2 (1 << 19) /* ALST2: Arbitration lost for mailbox 2 */ #define CAN_TSR_ALST2 (1 << 18) /* TXOK2: Transmission OK for mailbox 2 */ #define CAN_TSR_TXOK2 (1 << 17) /* RQCP2: Request completed mailbox 2 */ #define CAN_TSR_RQCP2 (1 << 16) /* ABRQ1: Abort request for mailbox 1 */ #define CAN_TSR_ABRQ1 (1 << 15) /* 14:12 Reserved, forced by hardware to 0 */ /* TERR1: Transmission error for mailbox 1 */ #define CAN_TSR_TERR1 (1 << 11) /* ALST1: Arbitration lost for mailbox 1 */ #define CAN_TSR_ALST1 (1 << 10) /* TXOK1: Transmission OK for mailbox 1 */ #define CAN_TSR_TXOK1 (1 << 9) /* RQCP1: Request completed mailbox 1 */ #define CAN_TSR_RQCP1 (1 << 8) /* ABRQ0: Abort request for mailbox 0 */ #define CAN_TSR_ABRQ0 (1 << 7) /* 6:4 Reserved, forced by hardware to 0 */ /* TERR0: Transmission error for mailbox 0 */ #define CAN_TSR_TERR0 (1 << 3) /* ALST0: Arbitration lost for mailbox 0 */ #define CAN_TSR_ALST0 (1 << 2) /* TXOK0: Transmission OK for mailbox 0 */ #define CAN_TSR_TXOK0 (1 << 1) /* RQCP0: Request completed mailbox 0 */ #define CAN_TSR_RQCP0 (1 << 0) /* --- CAN_RF0R values ----------------------------------------------------- */ /* 31:6 Reserved, forced by hardware to 0 */ /* RFOM0: Release FIFO 0 output mailbox */ #define CAN_RF0R_RFOM0 (1 << 5) /* FOVR0: FIFO 0 overrun */ #define CAN_RF0R_FAVR0 (1 << 4) /* FULL0: FIFO 0 full */ #define CAN_RF0R_FULL0 (1 << 3) /* 2 Reserved, forced by hardware to 0 */ /* FMP0[1:0]: FIFO 0 message pending */ #define CAN_RF0R_FMP0_MASK (0x3 << 0) /* --- CAN_RF1R values ----------------------------------------------------- */ /* 31:6 Reserved, forced by hardware to 0 */ /* RFOM1: Release FIFO 1 output mailbox */ #define CAN_RF1R_RFOM1 (1 << 5) /* FOVR1: FIFO 1 overrun */ #define CAN_RF1R_FAVR1 (1 << 4) /* FULL1: FIFO 1 full */ #define CAN_RF1R_FULL1 (1 << 3) /* 2 Reserved, forced by hardware to 0 */ /* FMP1[1:0]: FIFO 1 message pending */ #define CAN_RF1R_FMP1_MASK (0x3 << 0) /* --- CAN_IER values ------------------------------------------------------ */ /* 32:18 Reserved, forced by hardware to 0 */ /* SLKIE: Sleep interrupt enable */ #define CAN_IER_SLKIE (1 << 17) /* WKUIE: Wakeup interrupt enable */ #define CAN_IER_WKUIE (1 << 16) /* ERRIE: Error interrupt enable */ #define CAN_IER_ERRIE (1 << 15) /* 14:12 Reserved, forced by hardware to 0 */ /* LECIE: Last error code interrupt enable */ #define CAN_IER_LECIE (1 << 11) /* BOFIE: Bus-off interrupt enable */ #define CAN_IER_BOFIE (1 << 10) /* EPVIE: Error passive interrupt enable */ #define CAN_IER_EPVIE (1 << 9) /* EWGIE: Error warning interrupt enable */ #define CAN_IER_EWGIE (1 << 8) /* 7 Reserved, forced by hardware to 0 */ /* FOVIE1: FIFO overrun interrupt enable */ #define CAN_IER_FOVIE1 (1 << 6) /* FFIE1: FIFO full interrupt enable */ #define CAN_IER_FFIE1 (1 << 5) /* FMPIE1: FIFO message pending interrupt enable */ #define CAN_IER_FMPIE1 (1 << 4) /* FOVIE0: FIFO overrun interrupt enable */ #define CAN_IER_FOVIE0 (1 << 3) /* FFIE0: FIFO full interrupt enable */ #define CAN_IER_FFIE0 (1 << 2) /* FMPIE0: FIFO message pending interrupt enable */ #define CAN_IER_FMPIE0 (1 << 1) /* TMEIE: Transmit mailbox empty interrupt enable */ #define CAN_IER_TMEIE (1 << 0) /* --- CAN_ESR values ------------------------------------------------------ */ /* REC[7:0]: Receive error counter */ #define CAN_ESR_REC_MASK (0xF << 24) /* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ #define CAN_ESR_TEC_MASK (0xF << 16) /* 15:7 Reserved, forced by hardware to 0 */ /* LEC[2:0]: Last error code */ #define CAN_ESR_LEC_NO_ERROR (0x0 << 4) #define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) #define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) #define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) #define CAN_ESR_LEC_REC_ERROR (0x4 << 4) #define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) #define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) #define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) #define CAN_ESR_LEC_MASK (0x7 << 4) /* 3 Reserved, forced by hardware to 0 */ /* BOFF: Bus-off flag */ #define CAN_ESR_BOFF (1 << 2) /* EPVF: Error passive flag */ #define CAN_ESR_EPVF (1 << 1) /* EWGF: Error warning flag */ #define CAN_ESR_EWGF (1 << 0) /* --- CAN_BTR values ------------------------------------------------------ */ /* SILM: Silent mode (debug) */ #define CAN_BTR_SILM (1 << 31) /* LBKM: Loop back mode (debug) */ #define CAN_BTR_LBKM (1 << 30) /* 29:26 Reserved, forced by hardware to 0 */ /* SJW[1:0]: Resynchronization jump width */ #define CAN_BTR_SJW_1TQ (0x0 << 24) #define CAN_BTR_SJW_2TQ (0x1 << 24) #define CAN_BTR_SJW_3TQ (0x2 << 24) #define CAN_BTR_SJW_4TQ (0x3 << 24) #define CAN_BTR_SJW_MASK (0x3 << 24) #define CAN_BTR_SJW_SHIFT 24 /* 23 Reserved, forced by hardware to 0 */ /* TS2[2:0]: Time segment 2 */ #define CAN_BTR_TS2_1TQ (0x0 << 20) #define CAN_BTR_TS2_2TQ (0x1 << 20) #define CAN_BTR_TS2_3TQ (0x2 << 20) #define CAN_BTR_TS2_4TQ (0x3 << 20) #define CAN_BTR_TS2_5TQ (0x4 << 20) #define CAN_BTR_TS2_6TQ (0x5 << 20) #define CAN_BTR_TS2_7TQ (0x6 << 20) #define CAN_BTR_TS2_8TQ (0x7 << 20) #define CAN_BTR_TS2_MASK (0x7 << 20) #define CAN_BTR_TS2_SHIFT 20 /* TS1[3:0]: Time segment 1 */ #define CAN_BTR_TS1_1TQ (0x0 << 16) #define CAN_BTR_TS1_2TQ (0x1 << 16) #define CAN_BTR_TS1_3TQ (0x2 << 16) #define CAN_BTR_TS1_4TQ (0x3 << 16) #define CAN_BTR_TS1_5TQ (0x4 << 16) #define CAN_BTR_TS1_6TQ (0x5 << 16) #define CAN_BTR_TS1_7TQ (0x6 << 16) #define CAN_BTR_TS1_8TQ (0x7 << 16) #define CAN_BTR_TS1_9TQ (0x8 << 16) #define CAN_BTR_TS1_10TQ (0x9 << 16) #define CAN_BTR_TS1_11TQ (0xA << 16) #define CAN_BTR_TS1_12TQ (0xB << 16) #define CAN_BTR_TS1_13TQ (0xC << 16) #define CAN_BTR_TS1_14TQ (0xD << 16) #define CAN_BTR_TS1_15TQ (0xE << 16) #define CAN_BTR_TS1_16TQ (0xF << 16) #define CAN_BTR_TS1_MASK (0xF << 16) #define CAN_BTR_TS1_SHIFT 16 /* 15:10 Reserved, forced by hardware to 0 */ /* BRP[9:0]: Baud rate prescaler */ #define CAN_BTR_BRP_MASK (0x1FFUL << 0) /* --- CAN_TIxR values ------------------------------------------------------ */ /* STID[10:0]: Standard identifier */ #define CAN_TIxR_STID_MASK (0x7FF << 21) #define CAN_TIxR_STID_SHIFT 21 /* EXID[15:0]: Extended identifier */ #define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) #define CAN_TIxR_EXID_SHIFT 3 /* IDE: Identifier extension */ #define CAN_TIxR_IDE (1 << 2) /* RTR: Remote transmission request */ #define CAN_TIxR_RTR (1 << 1) /* TXRQ: Transmit mailbox request */ #define CAN_TIxR_TXRQ (1 << 0) /* --- CAN_TDTxR values ----------------------------------------------------- */ /* TIME[15:0]: Message time stamp */ #define CAN_TDTxR_TIME_MASK (0xFFFF << 15) #define CAN_TDTxR_TIME_SHIFT 15 /* 15:6 Reserved, forced by hardware to 0 */ /* TGT: Transmit global time */ #define CAN_TDTxR_TGT (1 << 5) /* 7:4 Reserved, forced by hardware to 0 */ /* DLC[3:0]: Data length code */ #define CAN_TDTxR_DLC_MASK (0xF << 0) #define CAN_TDTxR_DLC_SHIFT 0 /* --- CAN_TDLxR values ----------------------------------------------------- */ /* DATA3[7:0]: Data byte 3 */ /* DATA2[7:0]: Data byte 2 */ /* DATA1[7:0]: Data byte 1 */ /* DATA0[7:0]: Data byte 0 */ /* --- CAN_TDHxR values ----------------------------------------------------- */ /* DATA7[7:0]: Data byte 7 */ /* DATA6[7:0]: Data byte 6 */ /* DATA5[7:0]: Data byte 5 */ /* DATA4[7:0]: Data byte 4 */ /* --- CAN_RIxR values ------------------------------------------------------ */ /* STID[10:0]: Standard identifier */ #define CAN_RIxR_STID_MASK (0x7FF) #define CAN_RIxR_STID_SHIFT 21 /* EXID[15:0]: Extended identifier */ #define CAN_RIxR_EXID_MASK (0x1FFFFFFF) #define CAN_RIxR_EXID_SHIFT 3 /* IDE: Identifier extension */ #define CAN_RIxR_IDE (1 << 2) /* RTR: Remote transmission request */ #define CAN_RIxR_RTR (1 << 1) /* 0 Reserved */ /* --- CAN_RDTxR values ----------------------------------------------------- */ /* TIME[15:0]: Message time stamp */ #define CAN_RDTxR_TIME_MASK (0xFFFF << 15) #define CAN_RDTxR_TIME_SHIFT 15 /* FMI[7:0]: Filter match index */ #define CAN_RDTxR_FMI_MASK (0xFF << 8) #define CAN_RDTxR_FMI_SHIFT 8 /* 7:4 Reserved, forced by hardware to 0 */ /* DLC[3:0]: Data length code */ #define CAN_RDTxR_DLC_MASK (0xF << 0) #define CAN_RDTxR_DLC_SHIFT 0 /* --- CAN_RDLxR values ----------------------------------------------------- */ /* DATA3[7:0]: Data byte 3 */ /* DATA2[7:0]: Data byte 2 */ /* DATA1[7:0]: Data byte 1 */ /* DATA0[7:0]: Data byte 0 */ /* --- CAN_RDHxR values ----------------------------------------------------- */ /* DATA7[7:0]: Data byte 7 */ /* DATA6[7:0]: Data byte 6 */ /* DATA5[7:0]: Data byte 5 */ /* DATA4[7:0]: Data byte 4 */ /* --- CAN_FMR values ------------------------------------------------------- */ /* 31:14 Reserved, forced to reset value */ /* * CAN2SB[5:0]: CAN2 start bank * (only on connectivity line devices otherwise reserved) */ #define CAN_FMR_CAN2SB_MASK (0x3F << 8) #define CAN_FMR_CAN2SB_SHIFT 15 /* 7:1 Reserved, forced to reset value */ /* FINIT: Filter init mode */ #define CAN_FMR_FINIT (1 << 0) /* --- CAN_FM1R values ------------------------------------------------------ */ /* 31:28 Reserved, forced by hardware to 0 */ /* * FBMx: Filter mode * x is 0..27 should be calculated by a helper function making so many macros * seems like an overkill? */ /* --- CAN_FS1R values ------------------------------------------------------ */ /* 31:28 Reserved, forced by hardware to 0 */ /* * FSCx: Filter scale configuration * x is 0..27 should be calculated by a helper function making so many macros * seems like an overkill? */ /* --- CAN_FFA1R values ----------------------------------------------------- */ /* 31:28 Reserved, forced by hardware to 0 */ /* * FFAx: Filter scale configuration * x is 0..27 should be calculated by a helper function making so many macros * seems like an overkill? */ /* --- CAN_FA1R values ------------------------------------------------------ */ /* 31:28 Reserved, forced by hardware to 0 */ /* * FACTx: Filter active * x is 0..27 should be calculated by a helper function making so many macros * seems like an overkill? */ /* --- CAN_FiRx values ------------------------------------------------------ */ /* FB[31:0]: Filter bits */ /* --- CAN functions -------------------------------------------------------- */ BEGIN_DECLS void can_reset(uint32_t canport); int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp, bool loopback, bool silent); void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode, uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable); void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1, uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable); void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask, uint32_t fifo, bool enable); void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t id4, uint32_t fifo, bool enable); void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2, uint32_t fifo, bool enable); void can_enable_irq(uint32_t canport, uint32_t irq); void can_disable_irq(uint32_t canport, uint32_t irq); int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data); void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext, bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data); void can_fifo_release(uint32_t canport, uint8_t fifo); bool can_available_mailbox(uint32_t canport); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/cec.h000066400000000000000000000016201435536612600230210ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/000077500000000000000000000000001435536612600234075ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/crc_common_all.h000066400000000000000000000054401435536612600265320ustar00rootroot00000000000000/** @addtogroup crc_defines @author @htmlonly © @endhtmlonly 2010 Thomas Otto */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H The order of header inclusion is important. crc.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_CRC_H /** @endcond */ #ifndef LIBOPENCM3_CRC_COMMON_ALL_H #define LIBOPENCM3_CRC_COMMON_ALL_H /**@{*/ #include /* --- CRC registers ------------------------------------------------------- */ /* Data register (CRC_DR) */ #define CRC_DR MMIO32(CRC_BASE + 0x00) /* Independent data register (CRC_IDR) */ #define CRC_IDR MMIO32(CRC_BASE + 0x04) /* Control register (CRC_CR) */ #define CRC_CR MMIO32(CRC_BASE + 0x08) /* --- CRC_DR values ------------------------------------------------------- */ /* Bits [31:0]: Data register */ /* --- CRC_IDR values ------------------------------------------------------ */ /* Bits [31:8]: Reserved */ /* Bits [7:0]: General-purpose 8-bit data register bits */ /* --- CRC_CR values ------------------------------------------------------- */ /* Bits [31:1]: Reserved */ /* RESET bit */ #define CRC_CR_RESET (1 << 0) /* --- CRC function prototypes --------------------------------------------- */ BEGIN_DECLS /* TODO */ /** * Reset the CRC calculator to initial values. */ void crc_reset(void); /** * Add a word to the CRC calculator and return the result. * @param data new word to add to the CRC calculator * @return final CRC calculator value */ uint32_t crc_calculate(uint32_t data); /** * Add a block of data to the CRC calculator and return the final result * @param datap pointer to the start of a block of 32bit data words * @param size length of data, in 32bit increments * @return final CRC calculator value */ uint32_t crc_calculate_block(uint32_t *datap, int size); END_DECLS /**@}*/ #endif /** @cond */ #else #warning "crc_common_all.h should not be included explicitly, only via crc.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/crypto_common_f24.h000066400000000000000000000211701435536612600271240ustar00rootroot00000000000000/** @addtogroup crypto_defines * * @warning The CRYP subsystem is present only in a limited set of devices, * see next section for list of supported devices. * * @section crypto_api_supported Supported devices * * - STM32F205 * - STM32F207 * - STM32F215 * - STM32F217 * - STM32F405 * - STM32F407 * - STM32F415 * - STM32F417 (tested) * - STM32F427 * - STM32F437 * * @section crypto_api_theory Theory of operation * * * * @section crypto_api_basic Basic handling API * * * @b Example @b 1: Blocking mode * * @code * //[enable-clocks] * crypto_set_key(CRYPTO_KEY_128BIT,key); * crypto_set_iv(iv); // only in CBC or CTR mode * crypto_set_datatype(CRYPTO_DATA_16BIT); * crypto_set_algorithm(ENCRYPT_AES_ECB); * crypto_start(); * foreach(block in blocks) * crypto_process_block(plaintext,ciphertext,blocksize); * crypto_stop(); * @endcode * * @section crypto_api_interrupt Interrupt supported handling API * * @warning This operation mode is currently not supported. * * @b Example @b 2: Interrupt mode * * @code * //[enable-clocks] * crypto_set_key(CRYPTO_KEY_128BIT,key); * crypto_set_iv(iv); // only in CBC or CTR mode * crypto_set_datatype(CRYPTO_DATA_16BIT); * crypto_set_algorithm(ENCRYPT_AES_ECB); * crypto_start(); * [... API to be described later ...] * crypto_stop(); * @endcode * * @section crypto_api_dma DMA handling API * * @warning This operation mode is currently not supported. * * @b Example @b 3: DMA mode * * @code * //[enable-clocks] * crypto_set_key(CRYPTO_KEY_128BIT,key); * crypto_set_iv(iv); // only in CBC or CTR mode * crypto_set_datatype(CRYPTO_DATA_16BIT); * crypto_set_algorithm(ENCRYPT_AES_ECB); * crypto_start(); * [... API to be described later ...] * crypto_stop(); * @endcode */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRYP.H The order of header inclusion is important. cryp.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_CRYPTO_H /** @endcond */ #ifndef LIBOPENCM3_CRYPTO_COMMON_F24_H #define LIBOPENCM3_CRYPTO_COMMON_F24_H #include /**@{*/ /* --- CRYP registers ------------------------------------------------------ */ /** @defgroup crypto_registers_gen Registers (Generic) * * @brief Register access to the CRYP controller. (All chips) * * @ingroup crypto_defines */ /**@{*/ #define CRYP CRYP_BASE /* CRYP Control Register (CRYP_CR) */ #define CRYP_CR MMIO32(CRYP_BASE + 0x00) /* CRYP Status Register (CRYP_SR) */ #define CRYP_SR MMIO32(CRYP_BASE + 0x04) /* CRYP Data Input Register (CRYP_DIN) */ #define CRYP_DIN MMIO32(CRYP_BASE + 0x08) /** CRYP Data Output Register (CRYP_DOUT) @see blablabla */ #define CRYP_DOUT MMIO32(CRYP_BASE + 0x0C) /* CRYP DMA Control Register (CRYP_DMACR) */ #define CRYP_DMACR MMIO32(CRYP_BASE + 0x10) /* CRYP Interrupt mask set/clear register (CRYP_IMSCR) */ #define CRYP_IMSCR MMIO32(CRYP_BASE + 0x14) /* CRYP Raw Interrupt status register (CRYP_RISR) */ #define CRYP_RISR MMIO32(CRYP_BASE + 0x18) /* CRYP Masked Interrupt status register (CRYP_MISR) */ #define CRYP_MISR MMIO32(CRYP_BASE + 0x1C) /* CRYP Key registers (CRYP_KxLR) x=0..3 */ #define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8) /* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */ #define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8) /* --- CRYP_CR values ------------------------------------------------------ */ /* ALGODIR: Algorithm direction */ #define CRYP_CR_ALGODIR (1 << 2) /* ALGOMODE: Algorithm mode */ #define CRYP_CR_ALGOMODE_SHIFT 3 #define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_DES_CBC (3 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_AES_ECB (4 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_AES_CBC (5 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_AES_CTR (6 << CRYP_CR_ALGOMODE_SHIFT) #define CRYP_CR_ALGOMODE_AES_PREP (7 << CRYP_CR_ALGOMODE_SHIFT) /* DATATYPE: Data type selection */ #define CRYP_CR_DATATYPE_SHIFT 6 #define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT) #define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT) #define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT) #define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT) #define CRYP_CR_DATATYPE_BIT (3 << CRYP_CR_DATATYPE_SHIFT) /* KEYSIZE: Key size selection (AES mode only)*/ #define CRYP_CR_KEYSIZE_SHIFT 8 #define CRYP_CR_KEYSIZE (3 << CRYP_CR_KEYSIZE_SHIFT) #define CRYP_CR_KEYSIZE_128 (0 << CRYP_CR_KEYSIZE_SHIFT) #define CRYP_CR_KEYSIZE_192 (1 << CRYP_CR_KEYSIZE_SHIFT) #define CRYP_CR_KEYSIZE_256 (2 << CRYP_CR_KEYSIZE_SHIFT) /* FFLUSH: FIFO Flush */ #define CRYP_CR_FFLUSH (1 << 14) /* CRYPEN: Cryptographic processor enable*/ #define CRYP_CR_CRYPEN (1 << 15) /* --- CRYP_SR values ------------------------------------------------------ */ /* IFEM: Input FIFO empty */ #define CRYP_SR_IFEM (1 << 0) /* IFNF: Input FIFO not full */ #define CRYP_SR_IFNF (1 << 1) /* OFNE: Output FIFO not empty */ #define CRYP_SR_OFNE (1 << 2) /* OFFU: Output FIFO full */ #define CRYP_SR_OFFU (1 << 3) /* BUSY: Busy bit */ #define CRYP_SR_BUSY (1 << 4) /* --- CRYP_DMACR values --------------------------------------------------- */ /* DIEN: DMA input enable */ #define CRYP_DMACR_DIEN (1 << 0) /* DOEN: DMA output enable */ #define CRYP_DMACR_DOEN (1 << 1) /* --- CRYP_IMSCR values --------------------------------------------------- */ /* INIM: Input FIFO service interrupt mask */ #define CRYP_IMSCR_INIM (1 << 0) /* OUTIM: Output FIFO service interrupt mask */ #define CRYP_IMSCR_OUTIM (1 << 1) /* --- CRYP_RISR values ---------------------------------------------------- */ /* INRIS: Input FIFO service raw interrupt status */ #define CRYP_RISR_INRIS (1 << 0) /* OUTRIS: Output FIFO service raw data */ #define CRYP_RISR_OUTRIS (1 << 0) /* --- CRYP_MISR values ---------------------------------------------------- */ /* INMIS: Input FIFO service masked interrupt status */ #define CRYP_MISR_INMIS (1 << 0) /* OUTMIS: Output FIFO service masked interrupt status */ #define CRYP_MISR_OUTMIS (1 << 0) /**@}*/ /** @defgroup crypto_api_gen API (Generic) * * @brief API for the CRYP controller * * @ingroup crypto_defines */ /**@{*/ enum crypto_mode { ENCRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB, ENCRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC, ENCRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB, ENCRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC, ENCRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB, ENCRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC, ENCRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR, DECRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGODIR, DECRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGODIR, DECRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB | CRYP_CR_ALGODIR, DECRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC | CRYP_CR_ALGODIR, DECRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR, DECRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR, DECRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,/* XOR is same ENC as DEC */ }; enum crypto_keysize { CRYPTO_KEY_128BIT = 0, CRYPTO_KEY_192BIT, CRYPTO_KEY_256BIT, }; enum crypto_datatype { CRYPTO_DATA_32BIT = 0, CRYPTO_DATA_16BIT, CRYPTO_DATA_8BIT, CRYPTO_DATA_BIT, }; BEGIN_DECLS void crypto_wait_busy(void); void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]); void crypto_set_iv(uint64_t iv[]); void crypto_set_datatype(enum crypto_datatype datatype); void crypto_set_algorithm(enum crypto_mode mode); void crypto_start(void); void crypto_stop(void); uint32_t crypto_process_block(uint32_t *inp, uint32_t *outp, uint32_t length); END_DECLS /**@}*/ /**@}*/ #endif /** @cond */ #else #warning "crypto_common_f24.h should not be included explicitly, " "only via crypto.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/dac_common_all.h000066400000000000000000000342241435536612600265140ustar00rootroot00000000000000/** @addtogroup dac_defines @author @htmlonly © @endhtmlonly 2012 Felix Held */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Felix Held * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H The order of header inclusion is important. dac.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_DAC_H /** @endcond */ #ifndef LIBOPENCM3_DAC_COMMON_ALL_H #define LIBOPENCM3_DAC_COMMON_ALL_H #include /* --- DAC registers ------------------------------------------------------- */ /* DAC control register (DAC_CR) */ #define DAC_CR MMIO32(DAC_BASE + 0x00) /* DAC software trigger register (DAC_SWTRIGR) */ #define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) /* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ #define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) /* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ #define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) /* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ #define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) /* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ #define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) /* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ #define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) /* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ #define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) /* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ #define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) /* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ #define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) /* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ #define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) /* DAC channel1 data output register (DAC_DOR1) */ #define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) /* DAC channel2 data output register (DAC_DOR2) */ #define DAC_DOR2 MMIO32(DAC_BASE + 0x30) /* --- DAC_CR values ------------------------------------------------------- */ /* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ /* doesn't exist in most members of the STM32F1 family */ #define DAC_CR_DMAUDRIE2 (1 << 29) /* DMAEN2: DAC channel2 DMA enable */ #define DAC_CR_DMAEN2 (1 << 28) /* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ /* DAC_CR_MAMP2_n: * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 */ #define DAC_CR_MAMP2_SHIFT 24 /** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values @ingroup dac_defines Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 @{*/ #define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) #define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) /**@}*/ /* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ /* Legend: * DIS: wave generation disabled * NOISE: Noise wave generation enabled * TRI: Triangle wave generation enabled * * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) */ #define DAC_CR_WAVE2_SHIFT 22 #define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) /** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable @ingroup dac_defines @li NOISE: Noise wave generation enabled @li TRI: Triangle wave generation enabled @note: only used if bit TEN2 is set (DAC channel2 trigger enabled) @{*/ #define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) #define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) /**@}*/ /* TSEL2[2:0]: DAC channel2 trigger selection */ /* Legend: * * T6: Timer 6 TRGO event * T3: Timer 3 TRGO event * T8: Timer 8 TRGO event * T7: Timer 7 TRGO event * T5: Timer 5 TRGO event * T15: Timer 15 TRGO event * T2: Timer 2 TRGO event * T4: Timer 4 TRGO event * E9: External line9 * SW: Software trigger * * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) * Note: T3 == T8; T5 == T15; not both present on one device * Note: this is *not* valid for the STM32L1 family */ #define DAC_CR_TSEL2_SHIFT 19 /** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection @ingroup dac_defines @li T6: Timer 6 TRGO event @li T3: Timer 3 TRGO event @li T8: Timer 8 TRGO event @li T7: Timer 7 TRGO event @li T5: Timer 5 TRGO event @li T15: Timer 15 TRGO event @li T2: Timer 2 TRGO event @li T4: Timer 4 TRGO event @li E9: External line9 @li SW: Software trigger @note: Refer to the timer documentation for details of the TRGO event. @note: T3 replaced by T8 and T5 replaced by T15 in some devices. @note: this is not valid for the STM32L1 family. @note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) @{*/ #define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) #define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) /**@}*/ /* TEN2: DAC channel2 trigger enable */ #define DAC_CR_TEN2 (1 << 18) /* BOFF2: DAC channel2 output buffer disable */ #define DAC_CR_BOFF2 (1 << 17) /* EN2: DAC channel2 enable */ #define DAC_CR_EN2 (1 << 16) /* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ /* doesn't exist in most members of the STM32F1 family */ #define DAC_CR_DMAUDRIE1 (1 << 13) /* DMAEN1: DAC channel1 DMA enable */ #define DAC_CR_DMAEN1 (1 << 12) /* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ /* DAC_CR_MAMP1_n: * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 */ #define DAC_CR_MAMP1_SHIFT 8 /** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values @ingroup dac_defines Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 @{*/ #define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) #define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) /**@}*/ /* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ /* Legend: * DIS: wave generation disabled * NOISE: Noise wave generation enabled * TRI: Triangle wave generation enabled * * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) */ #define DAC_CR_WAVE1_SHIFT 6 #define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) /** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable @ingroup dac_defines @li DIS: wave generation disabled @li NOISE: Noise wave generation enabled @li TRI: Triangle wave generation enabled @note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) @{*/ #define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) #define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) /**@}*/ /* TSEL1[2:0]: DAC channel1 trigger selection */ /* Legend: * * T6: Timer 6 TRGO event * T3: Timer 3 TRGO event in connectivity line devices * T8: Timer 8 TRGO event in high-density and XL-density devices * T7: Timer 7 TRGO event * T5: Timer 5 TRGO event * T15: Timer 15 TRGO event * T2: Timer 2 TRGO event * T4: Timer 4 TRGO event * E9: External line9 * SW: Software trigger * * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) * Note: T3 == T8; T5 == T15; not both present on one device * Note: this is *not* valid for the STM32L1 family */ #define DAC_CR_TSEL1_SHIFT 3 /** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection @ingroup dac_defines @li T6: Timer 6 TRGO event @li T3: Timer 3 TRGO event @li T8: Timer 8 TRGO event @li T7: Timer 7 TRGO event @li T5: Timer 5 TRGO event @li T15: Timer 15 TRGO event @li T2: Timer 2 TRGO event @li T4: Timer 4 TRGO event @li E9: External line 9 @li SW: Software trigger @note: Refer to the timer documentation for details of the TRGO event. @note: T3 replaced by T8 and T5 replaced by T15 in some devices. @note: this is not valid for the STM32L1 family. @note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). @{*/ #define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) /**@}*/ /* TEN1: DAC channel1 trigger enable */ #define DAC_CR_TEN1 (1 << 2) /* BOFF1: DAC channel1 output buffer disable */ #define DAC_CR_BOFF1 (1 << 1) /* EN1: DAC channel1 enable */ #define DAC_CR_EN1 (1 << 0) /* --- DAC_SWTRIGR values -------------------------------------------------- */ /* SWTRIG2: DAC channel2 software trigger */ #define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* SWTRIG1: DAC channel1 software trigger */ #define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* --- DAC_DHR12R1 values -------------------------------------------------- */ #define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) #define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) /* --- DAC_DHR12L1 values -------------------------------------------------- */ #define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) #define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) /* --- DAC_DHR8R1 values --------------------------------------------------- */ #define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) #define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) /* --- DAC_DHR12R2 values -------------------------------------------------- */ #define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) #define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) /* --- DAC_DHR12L2 values -------------------------------------------------- */ #define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) #define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) /* --- DAC_DHR8R2 values --------------------------------------------------- */ #define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) #define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) /* --- DAC_DHR12RD values -------------------------------------------------- */ #define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) #define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) #define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) #define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) /* --- DAC_DHR12LD values -------------------------------------------------- */ #define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) #define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) #define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) #define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) /* --- DAC_DHR8RD values --------------------------------------------------- */ #define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) #define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) #define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) #define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) /* --- DAC_DOR1 values ----------------------------------------------------- */ #define DAC_DOR1_DACC1DOR_LSB (1 << 0) #define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) /* --- DAC_DOR2 values ----------------------------------------------------- */ #define DAC_DOR2_DACC2DOR_LSB (1 << 0) #define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) /** DAC channel identifier */ typedef enum { CHANNEL_1, CHANNEL_2, CHANNEL_D } data_channel; /** DAC data size (8/12 bits), alignment (right/left) */ typedef enum { RIGHT8, RIGHT12, LEFT12 } data_align; /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void dac_enable(data_channel dac_channel); void dac_disable(data_channel dac_channel); void dac_buffer_enable(data_channel dac_channel); void dac_buffer_disable(data_channel dac_channel); void dac_dma_enable(data_channel dac_channel); void dac_dma_disable(data_channel dac_channel); void dac_trigger_enable(data_channel dac_channel); void dac_trigger_disable(data_channel dac_channel); void dac_set_trigger_source(uint32_t dac_trig_src); void dac_set_waveform_generation(uint32_t dac_wave_ens); void dac_disable_waveform_generation(data_channel dac_channel); void dac_set_waveform_characteristics(uint32_t dac_mamp); void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, data_channel dac_channel); void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, data_align dac_data_format); void dac_software_trigger(data_channel dac_channel); END_DECLS #endif /** @cond */ #else #warning "dac_common_all.h should not be included explicitly, only via dac.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/dma_common_f24.h000066400000000000000000000511121435536612600263440ustar00rootroot00000000000000/** @addtogroup dma_defines @author @htmlonly © @endhtmlonly 2011 Fergus Noble @author @htmlonly © @endhtmlonly 2012 Ken Sarkies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H The order of header inclusion is important. dma.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_DMA_H /** @endcond */ #ifndef LIBOPENCM3_DMA_COMMON_F24_H #define LIBOPENCM3_DMA_COMMON_F24_H /**@{*/ #include /* --- Convenience macros -------------------------------------------------- */ /* DMA controller base addresses (for convenience) */ #define DMA1 DMA1_BASE #define DMA2 DMA2_BASE /* DMA stream base addresses (for API parameters) */ /** @defgroup dma_st_number DMA Stream Number @ingroup STM32F4xx_dma_defines @{*/ #define DMA_STREAM0 0 #define DMA_STREAM1 1 #define DMA_STREAM2 2 #define DMA_STREAM3 3 #define DMA_STREAM4 4 #define DMA_STREAM5 5 #define DMA_STREAM6 6 #define DMA_STREAM7 7 /**@}*/ #define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n))) #define DMA1_STREAM(n) DMA_STREAM(DMA1, n) #define DMA2_STREAM(n) DMA_STREAM(DMA2, n) #define DMA1_STREAM0 DMA1_STREAM(0) #define DMA1_STREAM1 DMA1_STREAM(1) #define DMA1_STREAM2 DMA1_STREAM(2) #define DMA1_STREAM3 DMA1_STREAM(3) #define DMA1_STREAM4 DMA1_STREAM(4) #define DMA1_STREAM5 DMA1_STREAM(5) #define DMA1_STREAM6 DMA1_STREAM(6) #define DMA1_STREAM7 DMA1_STREAM(7) #define DMA2_STREAM0 DMA2_STREAM(0) #define DMA2_STREAM1 DMA2_STREAM(1) #define DMA2_STREAM2 DMA2_STREAM(2) #define DMA2_STREAM3 DMA2_STREAM(3) #define DMA2_STREAM4 DMA2_STREAM(4) #define DMA2_STREAM5 DMA2_STREAM(5) #define DMA2_STREAM6 DMA2_STREAM(6) #define DMA2_STREAM7 DMA2_STREAM(7) /* --- DMA controller registers -------------------------------------------- */ /* DMA low interrupt status register (DMAx_LISR) */ #define DMA_LISR(port) MMIO32(port + 0x00) #define DMA1_LISR DMA_LISR(DMA1) #define DMA2_LISR DMA_LISR(DMA2) /* DMA high interrupt status register (DMAx_HISR) */ #define DMA_HISR(port) MMIO32(port + 0x04) #define DMA1_HISR DMA_HISR(DMA1) #define DMA2_HISR DMA_HISR(DMA2) /* DMA low interrupt flag clear register (DMAx_LIFCR) */ #define DMA_LIFCR(port) MMIO32(port + 0x08) #define DMA1_LIFCR DMA_LIFCR(DMA1) #define DMA2_LIFCR DMA_LIFCR(DMA2) /* DMA high interrupt flag clear register (DMAx_HIFCR) */ #define DMA_HIFCR(port) MMIO32(port + 0x0C) #define DMA1_HIFCR DMA_HIFCR(DMA1) #define DMA2_HIFCR DMA_HIFCR(DMA2) /* --- DMA stream registers ------------------------------------------------ */ /* DMA Stream x configuration register (DMA_SxCR) */ #define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00) #define DMA1_SCR(n) DMA_SCR(DMA1, n) #define DMA2_SCR(n) DMA_SCR(DMA2, n) #define DMA1_S0CR DMA1_SCR(0) #define DMA1_S1CR DMA1_SCR(1) #define DMA1_S2CR DMA1_SCR(2) #define DMA1_S3CR DMA1_SCR(3) #define DMA1_S4CR DMA1_SCR(4) #define DMA1_S5CR DMA1_SCR(5) #define DMA1_S6CR DMA1_SCR(6) #define DMA1_S7CR DMA1_SCR(7) #define DMA2_S0CR DMA2_SCR(0) #define DMA2_S1CR DMA2_SCR(1) #define DMA2_S2CR DMA2_SCR(2) #define DMA2_S3CR DMA2_SCR(3) #define DMA2_S4CR DMA2_SCR(4) #define DMA2_S5CR DMA2_SCR(5) #define DMA2_S6CR DMA2_SCR(6) #define DMA2_S7CR DMA2_SCR(7) /* DMA Stream x number of data register (DMA_SxNDTR) */ #define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04) #define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n) #define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n) #define DMA1_S0NDTR DMA1_SNDTR(0) #define DMA1_S1NDTR DMA1_SNDTR(1) #define DMA1_S2NDTR DMA1_SNDTR(2) #define DMA1_S3NDTR DMA1_SNDTR(3) #define DMA1_S4NDTR DMA1_SNDTR(4) #define DMA1_S5NDTR DMA1_SNDTR(5) #define DMA1_S6NDTR DMA1_SNDTR(6) #define DMA1_S7NDTR DMA1_SNDTR(7) #define DMA2_S0NDTR DMA2_SNDTR(0) #define DMA2_S1NDTR DMA2_SNDTR(1) #define DMA2_S2NDTR DMA2_SNDTR(2) #define DMA2_S3NDTR DMA2_SNDTR(3) #define DMA2_S4NDTR DMA2_SNDTR(4) #define DMA2_S5NDTR DMA2_SNDTR(5) #define DMA2_S6NDTR DMA2_SNDTR(6) #define DMA2_S7NDTR DMA2_SNDTR(7) /* DMA Stream x peripheral address register (DMA_SxPAR) */ #define DMA_SPAR(port, n) (*(volatile void **)\ (DMA_STREAM(port, n) + 0x08)) #define DMA1_SPAR(n) DMA_SPAR(DMA1, n) #define DMA2_SPAR(n) DMA_SPAR(DMA2, n) #define DMA1_S0PAR DMA1_SPAR(0) #define DMA1_S1PAR DMA1_SPAR(1) #define DMA1_S2PAR DMA1_SPAR(2) #define DMA1_S3PAR DMA1_SPAR(3) #define DMA1_S4PAR DMA1_SPAR(4) #define DMA1_S5PAR DMA1_SPAR(5) #define DMA1_S6PAR DMA1_SPAR(6) #define DMA1_S7PAR DMA1_SPAR(7) #define DMA2_S0PAR DMA2_SPAR(0) #define DMA2_S1PAR DMA2_SPAR(1) #define DMA2_S2PAR DMA2_SPAR(2) #define DMA2_S3PAR DMA2_SPAR(3) #define DMA2_S4PAR DMA2_SPAR(4) #define DMA2_S5PAR DMA2_SPAR(5) #define DMA2_S6PAR DMA2_SPAR(6) #define DMA2_S7PAR DMA2_SPAR(7) /* DMA Stream x memory address 0 register (DMA_SxM0AR) */ #define DMA_SM0AR(port, n) (*(volatile void **) \ (DMA_STREAM(port, n) + 0x0c)) #define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n) #define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n) #define DMA1_S0M0AR DMA1_SM0AR(0) #define DMA1_S1M0AR DMA1_SM0AR(1) #define DMA1_S2M0AR DMA1_SM0AR(2) #define DMA1_S3M0AR DMA1_SM0AR(3) #define DMA1_S4M0AR DMA1_SM0AR(4) #define DMA1_S5M0AR DMA1_SM0AR(5) #define DMA1_S6M0AR DMA1_SM0AR(6) #define DMA1_S7M0AR DMA1_SM0AR(7) #define DMA2_S0M0AR DMA2_SM0AR(0) #define DMA2_S1M0AR DMA2_SM0AR(1) #define DMA2_S2M0AR DMA2_SM0AR(2) #define DMA2_S3M0AR DMA2_SM0AR(3) #define DMA2_S4M0AR DMA2_SM0AR(4) #define DMA2_S5M0AR DMA2_SM0AR(5) #define DMA2_S6M0AR DMA2_SM0AR(6) #define DMA2_S7M0AR DMA2_SM0AR(7) /* DMA Stream x memory address 1 register (DMA_SxM1AR) */ #define DMA_SM1AR(port, n) (*(volatile void **)\ (DMA_STREAM(port, n) + 0x10)) #define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n) #define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n) #define DMA1_S0M1AR DMA1_SM1AR(0) #define DMA1_S1M1AR DMA1_SM1AR(1) #define DMA1_S2M1AR DMA1_SM1AR(2) #define DMA1_S3M1AR DMA1_SM1AR(3) #define DMA1_S4M1AR DMA1_SM1AR(4) #define DMA1_S5M1AR DMA1_SM1AR(5) #define DMA1_S6M1AR DMA1_SM1AR(6) #define DMA1_S7M1AR DMA1_SM1AR(7) #define DMA2_S0M1AR DMA2_SM1AR(0) #define DMA2_S1M1AR DMA2_SM1AR(1) #define DMA2_S2M1AR DMA2_SM1AR(2) #define DMA2_S3M1AR DMA2_SM1AR(3) #define DMA2_S4M1AR DMA2_SM1AR(4) #define DMA2_S5M1AR DMA2_SM1AR(5) #define DMA2_S6M1AR DMA2_SM1AR(6) #define DMA2_S7M1AR DMA2_SM1AR(7) /* DMA Stream x FIFO control register (DMA_SxFCR) */ #define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14) #define DMA1_SFCR(n) DMA_SFCR(DMA1, n) #define DMA2_SFCR(n) DMA_SFCR(DMA2, n) #define DMA1_S0FCR DMA1_SFCR(0) #define DMA1_S1FCR DMA1_SFCR(1) #define DMA1_S2FCR DMA1_SFCR(2) #define DMA1_S3FCR DMA1_SFCR(3) #define DMA1_S4FCR DMA1_SFCR(4) #define DMA1_S5FCR DMA1_SFCR(5) #define DMA1_S6FCR DMA1_SFCR(6) #define DMA1_S7FCR DMA1_SFCR(7) #define DMA2_S0FCR DMA2_SFCR(0) #define DMA2_S1FCR DMA2_SFCR(1) #define DMA2_S2FCR DMA2_SFCR(2) #define DMA2_S3FCR DMA2_SFCR(3) #define DMA2_S4FCR DMA2_SFCR(4) #define DMA2_S5FCR DMA2_SFCR(5) #define DMA2_S6FCR DMA2_SFCR(6) #define DMA2_S7FCR DMA2_SFCR(7) /* --- DMA Interrupt Flag offset values ------------------------------------- */ /* For API parameters. These are based on every interrupt flag and flag clear being at the same relative location */ /** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group. @ingroup dma_defines @{*/ /** Transfer Complete Interrupt Flag */ #define DMA_TCIF (1 << 5) /** Half Transfer Interrupt Flag */ #define DMA_HTIF (1 << 4) /** Transfer Error Interrupt Flag */ #define DMA_TEIF (1 << 3) /** Direct Mode Error Interrupt Flag */ #define DMA_DMEIF (1 << 2) /** FIFO Error Interrupt Flag */ #define DMA_FEIF (1 << 0) /**@}*/ /* Offset within interrupt status register to start of stream interrupt flag * field */ #define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) #define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \ DMA_FEIF) #define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)) /* --- DMA_LISR values ----------------------------------------------------- */ #define DMA_LISR_FEIF0 (1 << 0) #define DMA_LISR_DMEIF0 (1 << 2) #define DMA_LISR_TEIF0 (1 << 3) #define DMA_LISR_HTIF0 (1 << 4) #define DMA_LISR_TCIF0 (1 << 5) #define DMA_LISR_FEIF1 (1 << 6) #define DMA_LISR_DMEIF1 (1 << 8) #define DMA_LISR_TEIF1 (1 << 9) #define DMA_LISR_HTIF1 (1 << 10) #define DMA_LISR_TCIF1 (1 << 11) #define DMA_LISR_FEIF2 (1 << 16) #define DMA_LISR_DMEIF2 (1 << 18) #define DMA_LISR_TEIF2 (1 << 19) #define DMA_LISR_HTIF2 (1 << 20) #define DMA_LISR_TCIF2 (1 << 21) #define DMA_LISR_FEIF3 (1 << 22) #define DMA_LISR_DMEIF3 (1 << 24) #define DMA_LISR_TEIF3 (1 << 25) #define DMA_LISR_HTIF3 (1 << 26) #define DMA_LISR_TCIF3 (1 << 27) /* --- DMA_HISR values ----------------------------------------------------- */ #define DMA_HISR_FEIF4 (1 << 0) #define DMA_HISR_DMEIF4 (1 << 2) #define DMA_HISR_TEIF4 (1 << 3) #define DMA_HISR_HTIF4 (1 << 4) #define DMA_HISR_TCIF4 (1 << 5) #define DMA_HISR_FEIF5 (1 << 6) #define DMA_HISR_DMEIF5 (1 << 8) #define DMA_HISR_TEIF5 (1 << 9) #define DMA_HISR_HTIF5 (1 << 10) #define DMA_HISR_TCIF5 (1 << 11) #define DMA_HISR_FEIF6 (1 << 16) #define DMA_HISR_DMEIF6 (1 << 18) #define DMA_HISR_TEIF6 (1 << 19) #define DMA_HISR_HTIF6 (1 << 20) #define DMA_HISR_TCIF6 (1 << 21) #define DMA_HISR_FEIF7 (1 << 22) #define DMA_HISR_DMEIF7 (1 << 24) #define DMA_HISR_TEIF7 (1 << 25) #define DMA_HISR_HTIF7 (1 << 26) #define DMA_HISR_TCIF7 (1 << 27) /* --- DMA_LIFCR values ----------------------------------------------------- */ #define DMA_LIFCR_CFEIF0 (1 << 0) #define DMA_LIFCR_CDMEIF0 (1 << 2) #define DMA_LIFCR_CTEIF0 (1 << 3) #define DMA_LIFCR_CHTIF0 (1 << 4) #define DMA_LIFCR_CTCIF0 (1 << 5) #define DMA_LIFCR_CFEIF1 (1 << 6) #define DMA_LIFCR_CDMEIF1 (1 << 8) #define DMA_LIFCR_CTEIF1 (1 << 9) #define DMA_LIFCR_CHTIF1 (1 << 10) #define DMA_LIFCR_CTCIF1 (1 << 11) #define DMA_LIFCR_CFEIF2 (1 << 16) #define DMA_LIFCR_CDMEIF2 (1 << 18) #define DMA_LIFCR_CTEIF2 (1 << 19) #define DMA_LIFCR_CHTIF2 (1 << 20) #define DMA_LIFCR_CTCIF2 (1 << 21) #define DMA_LIFCR_CFEIF3 (1 << 22) #define DMA_LIFCR_CDMEIF3 (1 << 24) #define DMA_LIFCR_CTEIF3 (1 << 25) #define DMA_LIFCR_CHTIF3 (1 << 26) #define DMA_LIFCR_CTCIF3 (1 << 27) /* --- DMA_HIFCR values ----------------------------------------------------- */ #define DMA_HIFCR_CFEIF4 (1 << 0) #define DMA_HIFCR_CDMEIF4 (1 << 2) #define DMA_HIFCR_CTEIF4 (1 << 3) #define DMA_HIFCR_CHTIF4 (1 << 4) #define DMA_HIFCR_CTCIF4 (1 << 5) #define DMA_HIFCR_CFEIF5 (1 << 6) #define DMA_HIFCR_CDMEIF5 (1 << 8) #define DMA_HIFCR_CTEIF5 (1 << 9) #define DMA_HIFCR_CHTIF5 (1 << 10) #define DMA_HIFCR_CTCIF5 (1 << 11) #define DMA_HIFCR_CFEIF6 (1 << 16) #define DMA_HIFCR_CDMEIF6 (1 << 18) #define DMA_HIFCR_CTEIF6 (1 << 19) #define DMA_HIFCR_CHTIF6 (1 << 20) #define DMA_HIFCR_CTCIF6 (1 << 21) #define DMA_HIFCR_CFEIF7 (1 << 22) #define DMA_HIFCR_CDMEIF7 (1 << 24) #define DMA_HIFCR_CTEIF7 (1 << 25) #define DMA_HIFCR_CHTIF7 (1 << 26) #define DMA_HIFCR_CTCIF7 (1 << 27) /* --- DMA_SxCR values ----------------------------------------------------- */ /* EN: Stream enable */ #define DMA_SxCR_EN (1 << 0) /* DMEIE: Direct Mode error interrupt enable */ #define DMA_SxCR_DMEIE (1 << 1) /* TEIE: Transfer error interrupt enable */ #define DMA_SxCR_TEIE (1 << 2) /* HTIE: Half transfer interrupt enable */ #define DMA_SxCR_HTIE (1 << 3) /* TCIE: Transfer complete interrupt enable */ #define DMA_SxCR_TCIE (1 << 4) /* PFCTRL: Peripheral Flow Controller */ #define DMA_SxCR_PFCTRL (1 << 5) /* DIR[7:6]: Data transfer direction */ /** @defgroup dma_st_dir DMA Stream Data transfer direction @ingroup dma_defines @{*/ #define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6) #define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6) #define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6) /**@}*/ #define DMA_SxCR_DIR_SHIFT 6 #define DMA_SxCR_DIR_MASK (3 << 6) /* CIRC: Circular mode */ #define DMA_SxCR_CIRC (1 << 8) /* PINC: Peripheral increment mode */ #define DMA_SxCR_PINC (1 << 9) /* MINC: Memory increment mode */ #define DMA_SxCR_MINC (1 << 10) /* PSIZE[12:11]: Peripheral size */ /** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width @ingroup STM32F4xx_dma_defines @{*/ #define DMA_SxCR_PSIZE_8BIT (0 << 11) #define DMA_SxCR_PSIZE_16BIT (1 << 11) #define DMA_SxCR_PSIZE_32BIT (2 << 11) /**@}*/ #define DMA_SxCR_PSIZE_SHIFT 11 #define DMA_SxCR_PSIZE_MASK (3 << 11) /* MSIZE[14:13]: Memory size */ /** @defgroup dma_st_memwidth DMA Stream Memory Word Width @ingroup STM32F4xx_dma_defines @{*/ #define DMA_SxCR_MSIZE_8BIT (0 << 13) #define DMA_SxCR_MSIZE_16BIT (1 << 13) #define DMA_SxCR_MSIZE_32BIT (2 << 13) /**@}*/ #define DMA_SxCR_MSIZE_SHIFT 13 #define DMA_SxCR_MSIZE_MASK (3 << 13) /* PINCOS: Peripheral increment offset size */ #define DMA_SxCR_PINCOS (1 << 15) /* PL[17:16]: Stream priority level */ /** @defgroup dma_st_pri DMA Stream Priority Levels @ingroup dma_defines @{*/ #define DMA_SxCR_PL_LOW (0 << 16) #define DMA_SxCR_PL_MEDIUM (1 << 16) #define DMA_SxCR_PL_HIGH (2 << 16) #define DMA_SxCR_PL_VERY_HIGH (3 << 16) /**@}*/ #define DMA_SxCR_PL_SHIFT 16 #define DMA_SxCR_PL_MASK (3 << 16) /* DBM: Double buffered mode */ #define DMA_SxCR_DBM (1 << 18) /* CT: Current target (in double buffered mode) */ #define DMA_SxCR_CT (1 << 19) /* Bit 20 reserved */ /* PBURST[13:12]: Peripheral Burst Configuration */ /** @defgroup dma_pburst DMA Peripheral Burst Length @ingroup dma_defines @{*/ #define DMA_SxCR_PBURST_SINGLE (0 << 21) #define DMA_SxCR_PBURST_INCR4 (1 << 21) #define DMA_SxCR_PBURST_INCR8 (2 << 21) #define DMA_SxCR_PBURST_INCR16 (3 << 21) /**@}*/ #define DMA_SxCR_PBURST_SHIFT 21 #define DMA_SxCR_PBURST_MASK (3 << 21) /* MBURST[13:12]: Memory Burst Configuration */ /** @defgroup dma_mburst DMA Memory Burst Length @ingroup STM32F4xx_dma_defines @{*/ #define DMA_SxCR_MBURST_SINGLE (0 << 23) #define DMA_SxCR_MBURST_INCR4 (1 << 23) #define DMA_SxCR_MBURST_INCR8 (2 << 23) #define DMA_SxCR_MBURST_INCR16 (3 << 23) /**@}*/ #define DMA_SxCR_MBURST_SHIFT 23 #define DMA_SxCR_MBURST_MASK (3 << 23) /* CHSEL[25:27]: Channel Select */ /** @defgroup dma_ch_sel DMA Channel Select @ingroup dma_defines @{*/ #define DMA_SxCR_CHSEL_0 (0 << DMA_SxCR_CHSEL_SHIFT) #define DMA_SxCR_CHSEL_1 (1 << DMA_SxCR_CHSEL_SHIFT) #define DMA_SxCR_CHSEL_2 (2 << DMA_SxCR_CHSEL_SHIFT) #define DMA_SxCR_CHSEL_3 (3 << DMA_SxCR_CHSEL_SHIFT) #define DMA_SxCR_CHSEL_4 (4 << DMA_SxCR_CHSEL_SHIFT) #define DMA_SxCR_CHSEL_5 (5 << DMA_SxCR_CHSEL_SHIFT) #define DMA_SxCR_CHSEL_6 (6 << DMA_SxCR_CHSEL_SHIFT) #define DMA_SxCR_CHSEL_7 (7 << DMA_SxCR_CHSEL_SHIFT) /**@}*/ #define DMA_SxCR_CHSEL_SHIFT 25 #define DMA_SxCR_CHSEL_MASK (7 << 25) #define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT) /* Reserved [31:28] */ /* --- DMA_SxNDTR values --------------------------------------------------- */ /* DMA_SxNDTR[15:0]: Number of data register. */ /* --- DMA_SxPAR values ---------------------------------------------------- */ /* DMA_SxPAR[31:0]: Peripheral address register. */ /* --- DMA_SxM0AR values --------------------------------------------------- */ /* DMA_SxM0AR[31:0]: Memory 0 address register. */ /* --- DMA_SxM1AR values --------------------------------------------------- */ /* DMA_SxM1AR[31:0]: Memory 1 address register. */ /* --- DMA_SxFCR values ---------------------------------------------------- */ /* FTH[1:0]: FIFO Threshold selection */ /** @defgroup dma_fifo_thresh FIFO Threshold selection @ingroup STM32F4xx_dma_defines @{*/ #define DMA_SxFCR_FTH_1_4_FULL (0 << 0) #define DMA_SxFCR_FTH_2_4_FULL (1 << 0) #define DMA_SxFCR_FTH_3_4_FULL (2 << 0) #define DMA_SxFCR_FTH_4_4_FULL (3 << 0) /**@}*/ #define DMA_SxFCR_FTH_SHIFT 0 #define DMA_SxFCR_FTH_MASK (3 << 0) /* DMDIS: Direct Mode disable */ #define DMA_SxFCR_DMDIS (1 << 2) /* FS[5:3]: FIFO Status */ /** @defgroup dma_fifo_status FIFO Status @ingroup STM32F4xx_dma_defines @{*/ #define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0) #define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0) #define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0) #define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0) #define DMA_SxFCR_FS_FULL (4 << 3) #define DMA_SxFCR_FS_EMPTY (5 << 3) /**@}*/ #define DMA_SxFCR_FS_SHIFT 3 #define DMA_SxFCR_FS_MASK (7 << 3) /* [6]: reserved */ /* FEIE[7]: FIFO error interrupt enable */ #define DMA_SxFCR_FEIE (1 << 7) /* [31:8]: Reserved */ /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS /* * Note: The F2 and F4 series have a completely new DMA peripheral with * different configuration options. */ void dma_stream_reset(uint32_t dma, uint8_t stream); void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts); bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt); void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction); void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio); void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size); void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size); void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream); void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel); void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream); void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel); void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream); void dma_enable_circular_mode(uint32_t dma, uint8_t stream); void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel); void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst); void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst); void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory); uint8_t dma_get_target(uint32_t dma, uint8_t stream); void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream); void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream); void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream); void dma_set_dma_flow_control(uint32_t dma, uint8_t stream); void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream); void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream); void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream); void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream); void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); uint32_t dma_fifo_status(uint32_t dma, uint8_t stream); void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream); void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream); void dma_enable_direct_mode(uint32_t dma, uint8_t stream); void dma_enable_fifo_mode(uint32_t dma, uint8_t stream); void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold); void dma_enable_stream(uint32_t dma, uint8_t stream); void dma_disable_stream(uint32_t dma, uint8_t stream); void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address); void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address); void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address); void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number); END_DECLS /**@}*/ #endif /** @cond */ #else #warning "dma_common_f24.h should not be included explicitly, only via dma.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/dma_common_l1f013.h000066400000000000000000000360601435536612600266640ustar00rootroot00000000000000/** @addtogroup dma_defines @author @htmlonly © @endhtmlonly 2010 Thomas Otto @author @htmlonly © @endhtmlonly 2012 Piotr Esden-Tempski */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H The order of header inclusion is important. dma.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_DMA_H /** @endcond */ #ifndef LIBOPENCM3_DMA_COMMON_F13_H #define LIBOPENCM3_DMA_COMMON_F13_H #include /* --- Convenience macros -------------------------------------------------- */ /* DMA register base adresses (for convenience) */ #define DMA1 DMA1_BASE #define DMA2 DMA2_BASE /* --- DMA registers ------------------------------------------------------- */ /* DMA interrupt status register (DMAx_ISR) */ #define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) #define DMA1_ISR DMA_ISR(DMA1) #define DMA2_ISR DMA_ISR(DMA2) /* DMA interrupt flag clear register (DMAx_IFCR) */ #define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) #define DMA1_IFCR DMA_IFCR(DMA1) #define DMA2_IFCR DMA_IFCR(DMA2) /* DMA channel configuration register (DMAx_CCRy) */ #define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ (0x14 * ((channel) - 1))) #define DMA1_CCR(channel) DMA_CCR(DMA1, channel) #define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1) #define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2) #define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3) #define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4) #define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5) #define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6) #define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7) #define DMA2_CCR(channel) DMA_CCR(DMA2, channel) #define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1) #define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2) #define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3) #define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4) #define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) /* DMA number of data register (DMAx_CNDTRy) */ #define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ (0x14 * ((channel) - 1))) #define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) #define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1) #define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2) #define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3) #define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4) #define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5) #define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6) #define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7) #define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel) #define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1) #define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2) #define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3) #define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4) #define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) /* DMA peripheral address register (DMAx_CPARy) */ #define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ (0x14 * ((channel) - 1))) #define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) #define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1) #define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2) #define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3) #define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4) #define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5) #define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6) #define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7) #define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel) #define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1) #define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2) #define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3) #define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4) #define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5) /* DMA memory address register (DMAx_CMARy) */ #define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ (0x14 * ((channel) - 1))) #define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) #define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1) #define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2) #define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3) #define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4) #define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5) #define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6) #define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7) #define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel) #define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1) #define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2) #define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3) #define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4) #define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5) /* --- DMA_ISR values ------------------------------------------------------ */ /* --- DMA Interrupt Flag offset values ------------------------------------- */ /* These are based on every interrupt flag and flag clear being at the same * relative location */ /** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag group. @ingroup dma_defines @{*/ /** Transfer Error Interrupt Flag */ #define DMA_TEIF (1 << 3) /** Half Transfer Interrupt Flag */ #define DMA_HTIF (1 << 2) /** Transfer Complete Interrupt Flag */ #define DMA_TCIF (1 << 1) /** Global Interrupt Flag */ #define DMA_GIF (1 << 0) /**@}*/ /* Offset within interrupt status register to start of channel interrupt flag * field */ #define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) #define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \ DMA_GIF) #define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel)) /* TEIF: Transfer error interrupt flag */ #define DMA_ISR_TEIF_BIT DMA_TEIF #define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) #define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) #define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3) #define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4) #define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5) #define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6) #define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) /* HTIF: Half transfer interrupt flag */ #define DMA_ISR_HTIF_BIT DMA_HTIF #define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) #define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) #define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3) #define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4) #define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5) #define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6) #define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) /* TCIF: Transfer complete interrupt flag */ #define DMA_ISR_TCIF_BIT DMA_TCIF #define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) #define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) #define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3) #define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4) #define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5) #define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6) #define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) /* GIF: Global interrupt flag */ #define DMA_ISR_GIF_BIT DMA_GIF #define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) #define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) #define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3) #define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4) #define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5) #define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6) #define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7) /* --- DMA_IFCR values ----------------------------------------------------- */ /* CTEIF: Transfer error clear */ #define DMA_IFCR_CTEIF_BIT DMA_TEIF #define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3) #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4) #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5) #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6) #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) /* CHTIF: Half transfer clear */ #define DMA_IFCR_CHTIF_BIT DMA_HTIF #define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3) #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4) #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5) #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6) #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) /* CTCIF: Transfer complete clear */ #define DMA_IFCR_CTCIF_BIT DMA_TCIF #define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3) #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4) #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5) #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6) #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) /* CGIF: Global interrupt clear */ #define DMA_IFCR_CGIF_BIT DMA_GIF #define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3) #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4) #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5) #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6) #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) /* Clear interrupts mask */ #define DMA_IFCR_CIF_BIT 0xF #define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \ (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) #define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) #define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3) #define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4) #define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5) #define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6) #define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7) /* --- DMA_CCRx generic values --------------------------------------------- */ /* MEM2MEM: Memory to memory mode */ #define DMA_CCR_MEM2MEM (1 << 14) /* PL[13:12]: Channel priority level */ /** @defgroup dma_ch_pri DMA Channel Priority Levels @ingroup dma_defines @{*/ #define DMA_CCR_PL_LOW (0x0 << 12) #define DMA_CCR_PL_MEDIUM (0x1 << 12) #define DMA_CCR_PL_HIGH (0x2 << 12) #define DMA_CCR_PL_VERY_HIGH (0x3 << 12) /**@}*/ #define DMA_CCR_PL_MASK (0x3 << 12) #define DMA_CCR_PL_SHIFT 12 /* MSIZE[11:10]: Memory size */ /** @defgroup dma_ch_memwidth DMA Channel Memory Word Width @ingroup dma_defines @{*/ #define DMA_CCR_MSIZE_8BIT (0x0 << 10) #define DMA_CCR_MSIZE_16BIT (0x1 << 10) #define DMA_CCR_MSIZE_32BIT (0x2 << 10) /**@}*/ #define DMA_CCR_MSIZE_MASK (0x3 << 10) #define DMA_CCR_MSIZE_SHIFT 10 /* PSIZE[9:8]: Peripheral size */ /** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width @ingroup dma_defines @{*/ #define DMA_CCR_PSIZE_8BIT (0x0 << 8) #define DMA_CCR_PSIZE_16BIT (0x1 << 8) #define DMA_CCR_PSIZE_32BIT (0x2 << 8) /**@}*/ #define DMA_CCR_PSIZE_MASK (0x3 << 8) #define DMA_CCR_PSIZE_SHIFT 8 /* MINC: Memory increment mode */ #define DMA_CCR_MINC (1 << 7) /* PINC: Peripheral increment mode */ #define DMA_CCR_PINC (1 << 6) /* CIRC: Circular mode */ #define DMA_CCR_CIRC (1 << 5) /* DIR: Data transfer direction */ #define DMA_CCR_DIR (1 << 4) /* TEIE: Transfer error interrupt enable */ #define DMA_CCR_TEIE (1 << 3) /* HTIE: Half transfer interrupt enable */ #define DMA_CCR_HTIE (1 << 2) /* TCIE: Transfer complete interrupt enable */ #define DMA_CCR_TCIE (1 << 1) /* EN: Channel enable */ #define DMA_CCR_EN (1 << 0) /* --- DMA_CNDTRx values --------------------------------------------------- */ /* NDT[15:0]: Number of data to transfer */ /* --- DMA_CPARx values ---------------------------------------------------- */ /* PA[31:0]: Peripheral address */ /* --- DMA_CMARx values ---------------------------------------------------- */ /* MA[31:0]: Memory address */ /* --- Generic values ------------------------------------------------------ */ /** @defgroup dma_ch DMA Channel Number @ingroup dma_defines @{*/ #define DMA_CHANNEL1 1 #define DMA_CHANNEL2 2 #define DMA_CHANNEL3 3 #define DMA_CHANNEL4 4 #define DMA_CHANNEL5 5 #define DMA_CHANNEL6 6 #define DMA_CHANNEL7 7 /**@}*/ /* --- function prototypes ------------------------------------------------- */ BEGIN_DECLS void dma_channel_reset(uint32_t dma, uint8_t channel); void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts); bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts); void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel); void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio); void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size); void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size); void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel); void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel); void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel); void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel); void dma_enable_circular_mode(uint32_t dma, uint8_t channel); void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel); void dma_set_read_from_memory(uint32_t dma, uint8_t channel); void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel); void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel); void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel); void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel); void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); void dma_enable_channel(uint32_t dma, uint8_t channel); void dma_disable_channel(uint32_t dma, uint8_t channel); void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address); void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address); void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number); END_DECLS #endif /** @cond */ #else #warning "dma_common_f13.h should not be included explicitly, only via dma.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/exti_common_all.h000066400000000000000000000046721435536612600267420ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @cond */ #if defined(LIBOPENCM3_EXTI_H) /** @endcond */ #ifndef LIBOPENCM3_EXTI_COMMON_ALL_H #define LIBOPENCM3_EXTI_COMMON_ALL_H #include #include /* --- EXTI registers ------------------------------------------------------ */ #define EXTI_IMR MMIO32(EXTI_BASE + 0x00) #define EXTI_EMR MMIO32(EXTI_BASE + 0x04) #define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) #define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) #define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) #define EXTI_PR MMIO32(EXTI_BASE + 0x14) /* EXTI number definitions */ #define EXTI0 (1 << 0) #define EXTI1 (1 << 1) #define EXTI2 (1 << 2) #define EXTI3 (1 << 3) #define EXTI4 (1 << 4) #define EXTI5 (1 << 5) #define EXTI6 (1 << 6) #define EXTI7 (1 << 7) #define EXTI8 (1 << 8) #define EXTI9 (1 << 9) #define EXTI10 (1 << 10) #define EXTI11 (1 << 11) #define EXTI12 (1 << 12) #define EXTI13 (1 << 13) #define EXTI14 (1 << 14) #define EXTI15 (1 << 15) #define EXTI16 (1 << 16) #define EXTI17 (1 << 17) #define EXTI18 (1 << 18) #define EXTI19 (1 << 19) /* Trigger types */ enum exti_trigger_type { EXTI_TRIGGER_RISING, EXTI_TRIGGER_FALLING, EXTI_TRIGGER_BOTH, }; BEGIN_DECLS void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig); void exti_enable_request(uint32_t extis); void exti_disable_request(uint32_t extis); void exti_reset_request(uint32_t extis); void exti_select_source(uint32_t exti, uint32_t gpioport); uint32_t exti_get_flag_status(uint32_t exti); END_DECLS #endif /** @cond */ #else #warning "exti_common_all.h should not be included directly, only via exti.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/exti_common_l1f24.h000066400000000000000000000024231435536612600270120ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @cond */ #if defined(LIBOPENCM3_EXTI_H) /** @endcond */ #ifndef LIBOPENCM3_EXTI_COMMON_F24_H #define LIBOPENCM3_EXTI_COMMON_F24_H #include #include #include /* EXTI number definitions */ #define EXTI20 (1 << 20) #define EXTI21 (1 << 21) #define EXTI22 (1 << 22) #endif /** @cond */ #else #warning "exti_common_f24.h should not be included directly, only via exti.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/flash_common_f234.h000066400000000000000000000054461435536612600267740ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * For details see: * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming * September 2011, Doc ID 018520 Rev 1 * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf */ /** @cond */ #ifdef LIBOPENCM3_FLASH_H /** @endcond */ #ifndef LIBOPENCM3_FLASH_COMMON_F234_H #define LIBOPENCM3_FLASH_COMMON_F234_H #include /* --- FLASH registers ----------------------------------------------------- */ #define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) #define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) #define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) #define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) #define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) /* --- FLASH_ACR values ---------------------------------------------------- */ #define FLASH_ACR_LATENCY_0WS 0x00 #define FLASH_ACR_LATENCY_1WS 0x01 #define FLASH_ACR_LATENCY_2WS 0x02 #define FLASH_ACR_LATENCY_3WS 0x03 #define FLASH_ACR_LATENCY_4WS 0x04 #define FLASH_ACR_LATENCY_5WS 0x05 #define FLASH_ACR_LATENCY_6WS 0x06 #define FLASH_ACR_LATENCY_7WS 0x07 /* --- FLASH_SR values ----------------------------------------------------- */ /* --- FLASH_CR values ----------------------------------------------------- */ /* --- FLASH Keys -----------------------------------------------------------*/ #define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) #define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void flash_set_ws(uint32_t ws); void flash_unlock(void); void flash_lock(void); void flash_clear_pgperr_flag(void); void flash_clear_eop_flag(void); void flash_clear_bsy_flag(void); void flash_clear_status_flags(void); void flash_wait_for_last_operation(void); END_DECLS #endif /** @cond */ #else #warning "flash_common_f234.h should not be included direcitly," #warning "only via flash.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/flash_common_f24.h000066400000000000000000000113421435536612600267010ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * For details see: * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming * September 2011, Doc ID 018520 Rev 1 * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf */ /** @cond */ #ifdef LIBOPENCM3_FLASH_H /** @endcond */ #ifndef LIBOPENCM3_FLASH_COMMON_F24_H #define LIBOPENCM3_FLASH_COMMON_F24_H #include #include /* --- FLASH registers ----------------------------------------------------- */ #define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) /* --- FLASH_ACR values ---------------------------------------------------- */ #define FLASH_ACR_DCRST (1 << 12) #define FLASH_ACR_ICRST (1 << 11) #define FLASH_ACR_DCE (1 << 10) #define FLASH_ACR_ICE (1 << 9) #define FLASH_ACR_PRFTEN (1 << 8) /* --- FLASH_SR values ----------------------------------------------------- */ #define FLASH_SR_BSY (1 << 16) #define FLASH_SR_PGSERR (1 << 7) #define FLASH_SR_PGPERR (1 << 6) #define FLASH_SR_PGAERR (1 << 5) #define FLASH_SR_WRPERR (1 << 4) #define FLASH_SR_OPERR (1 << 1) #define FLASH_SR_EOP (1 << 0) /* --- FLASH_CR values ----------------------------------------------------- */ #define FLASH_CR_LOCK (1 << 31) #define FLASH_CR_ERRIE (1 << 25) #define FLASH_CR_EOPIE (1 << 24) #define FLASH_CR_STRT (1 << 16) #define FLASH_CR_MER (1 << 2) #define FLASH_CR_SER (1 << 1) #define FLASH_CR_PG (1 << 0) #define FLASH_CR_SECTOR_0 (0x00 << 3) #define FLASH_CR_SECTOR_1 (0x01 << 3) #define FLASH_CR_SECTOR_2 (0x02 << 3) #define FLASH_CR_SECTOR_3 (0x03 << 3) #define FLASH_CR_SECTOR_4 (0x04 << 3) #define FLASH_CR_SECTOR_5 (0x05 << 3) #define FLASH_CR_SECTOR_6 (0x06 << 3) #define FLASH_CR_SECTOR_7 (0x07 << 3) #define FLASH_CR_SECTOR_8 (0x08 << 3) #define FLASH_CR_SECTOR_9 (0x09 << 3) #define FLASH_CR_SECTOR_10 (0x0a << 3) #define FLASH_CR_SECTOR_11 (0x0b << 3) #define FLASH_CR_PROGRAM_X8 (0x00 << 8) #define FLASH_CR_PROGRAM_X16 (0x01 << 8) #define FLASH_CR_PROGRAM_X32 (0x02 << 8) #define FLASH_CR_PROGRAM_X64 (0x03 << 8) /* --- FLASH_OPTCR values -------------------------------------------------- */ /* FLASH_OPTCR[27:16]: nWRP */ /* FLASH_OBR[15:8]: RDP */ #define FLASH_OPTCR_NRST_STDBY (1 << 7) #define FLASH_OPTCR_NRST_STOP (1 << 6) #define FLASH_OPTCR_WDG_SW (1 << 5) #define FLASH_OPTCR_OPTSTRT (1 << 1) #define FLASH_OPTCR_OPTLOCK (1 << 0) #define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2) #define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2) #define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2) #define FLASH_OPTCR_BOR_OFF (0x03 << 2) /* --- FLASH Keys -----------------------------------------------------------*/ #define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) #define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void flash_unlock_option_bytes(void); void flash_lock_option_bytes(void); void flash_clear_pgserr_flag(void); void flash_clear_wrperr_flag(void); void flash_clear_pgaerr_flag(void); void flash_dcache_enable(void); void flash_dcache_disable(void); void flash_icache_enable(void); void flash_icache_disable(void); void flash_prefetch_enable(void); void flash_prefetch_disable(void); void flash_dcache_reset(void); void flash_icache_reset(void); void flash_erase_all_sectors(uint32_t program_size); void flash_erase_sector(uint8_t sector, uint32_t program_size); void flash_program_double_word(uint32_t address, uint64_t data); void flash_program_word(uint32_t address, uint32_t data); void flash_program_half_word(uint32_t address, uint16_t data); void flash_program_byte(uint32_t address, uint8_t data); void flash_program(uint32_t address, uint8_t *data, uint32_t len); void flash_program_option_bytes(uint32_t data); END_DECLS #endif /** @cond */ #else #warning "flash_common_f24.h should not be included direcitly," #warning "only via flash.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/gpio_common_all.h000066400000000000000000000054351435536612600267250ustar00rootroot00000000000000/** @addtogroup gpio_defines @author @htmlonly © @endhtmlonly 2011 Fergus Noble @author @htmlonly © @endhtmlonly 2012 Ken Sarkies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H The order of header inclusion is important. gpio.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_GPIO_COMMON_ALL_H #define LIBOPENCM3_GPIO_COMMON_ALL_H /**@{*/ #include /* --- Convenience macros -------------------------------------------------- */ /* --- GPIO_LCKR values ---------------------------------------------------- */ #define GPIO_LCKK (1 << 16) /* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ /* GPIO number definitions (for convenience) */ /** @defgroup gpio_pin_id GPIO Pin Identifiers @ingroup gpio_defines @{*/ #define GPIO0 (1 << 0) #define GPIO1 (1 << 1) #define GPIO2 (1 << 2) #define GPIO3 (1 << 3) #define GPIO4 (1 << 4) #define GPIO5 (1 << 5) #define GPIO6 (1 << 6) #define GPIO7 (1 << 7) #define GPIO8 (1 << 8) #define GPIO9 (1 << 9) #define GPIO10 (1 << 10) #define GPIO11 (1 << 11) #define GPIO12 (1 << 12) #define GPIO13 (1 << 13) #define GPIO14 (1 << 14) #define GPIO15 (1 << 15) #define GPIO_ALL 0xffff /**@}*/ BEGIN_DECLS void gpio_set(uint32_t gpioport, uint16_t gpios); void gpio_clear(uint32_t gpioport, uint16_t gpios); uint16_t gpio_get(uint32_t gpioport, uint16_t gpios); void gpio_toggle(uint32_t gpioport, uint16_t gpios); uint16_t gpio_port_read(uint32_t gpioport); void gpio_port_write(uint32_t gpioport, uint16_t data); void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios); END_DECLS /**@}*/ #endif /** @cond */ #else #warning "gpio_common_all.h should not be included explicitly, only via gpio.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/gpio_common_f234.h000066400000000000000000000213571435536612600266340ustar00rootroot00000000000000/** @addtogroup gpio_defines @author @htmlonly © @endhtmlonly 2011 Fergus Noble @author @htmlonly © @endhtmlonly 2012 Ken Sarkies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H The order of header inclusion is important. gpio.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_GPIO_H /** @endcond */ #ifndef LIBOPENCM3_GPIO_COMMON_F234_H #define LIBOPENCM3_GPIO_COMMON_F234_H /**@{*/ #include /* GPIO port base addresses (for convenience) */ /** @defgroup gpio_port_id GPIO Port IDs @ingroup gpio_defines @{*/ #define GPIOA GPIO_PORT_A_BASE #define GPIOB GPIO_PORT_B_BASE #define GPIOC GPIO_PORT_C_BASE #define GPIOD GPIO_PORT_D_BASE #define GPIOE GPIO_PORT_E_BASE #define GPIOF GPIO_PORT_F_BASE /**@}*/ /* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ /* Port mode register (GPIOx_MODER) */ #define GPIO_MODER(port) MMIO32(port + 0x00) #define GPIOA_MODER GPIO_MODER(GPIOA) #define GPIOB_MODER GPIO_MODER(GPIOB) #define GPIOC_MODER GPIO_MODER(GPIOC) #define GPIOD_MODER GPIO_MODER(GPIOD) #define GPIOE_MODER GPIO_MODER(GPIOE) #define GPIOF_MODER GPIO_MODER(GPIOF) /* Port output type register (GPIOx_OTYPER) */ #define GPIO_OTYPER(port) MMIO32(port + 0x04) #define GPIOA_OTYPER GPIO_OTYPER(GPIOA) #define GPIOB_OTYPER GPIO_OTYPER(GPIOB) #define GPIOC_OTYPER GPIO_OTYPER(GPIOC) #define GPIOD_OTYPER GPIO_OTYPER(GPIOD) #define GPIOE_OTYPER GPIO_OTYPER(GPIOE) #define GPIOF_OTYPER GPIO_OTYPER(GPIOF) /* Port output speed register (GPIOx_OSPEEDR) */ #define GPIO_OSPEEDR(port) MMIO32(port + 0x08) #define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) #define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) #define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) #define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) #define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) #define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) /* Port pull-up/pull-down register (GPIOx_PUPDR) */ #define GPIO_PUPDR(port) MMIO32(port + 0x0c) #define GPIOA_PUPDR GPIO_PUPDR(GPIOA) #define GPIOB_PUPDR GPIO_PUPDR(GPIOB) #define GPIOC_PUPDR GPIO_PUPDR(GPIOC) #define GPIOD_PUPDR GPIO_PUPDR(GPIOD) #define GPIOE_PUPDR GPIO_PUPDR(GPIOE) #define GPIOF_PUPDR GPIO_PUPDR(GPIOF) /* Port input data register (GPIOx_IDR) */ #define GPIO_IDR(port) MMIO32(port + 0x10) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) #define GPIOD_IDR GPIO_IDR(GPIOD) #define GPIOE_IDR GPIO_IDR(GPIOE) #define GPIOF_IDR GPIO_IDR(GPIOF) /* Port output data register (GPIOx_ODR) */ #define GPIO_ODR(port) MMIO32(port + 0x14) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) #define GPIOD_ODR GPIO_ODR(GPIOD) #define GPIOE_ODR GPIO_ODR(GPIOE) #define GPIOF_ODR GPIO_ODR(GPIOF) /* Port bit set/reset register (GPIOx_BSRR) */ #define GPIO_BSRR(port) MMIO32(port + 0x18) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) #define GPIOD_BSRR GPIO_BSRR(GPIOD) #define GPIOE_BSRR GPIO_BSRR(GPIOE) #define GPIOF_BSRR GPIO_BSRR(GPIOF) /* Port configuration lock register (GPIOx_LCKR) */ #define GPIO_LCKR(port) MMIO32(port + 0x1c) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) #define GPIOD_LCKR GPIO_LCKR(GPIOD) #define GPIOE_LCKR GPIO_LCKR(GPIOE) #define GPIOF_LCKR GPIO_LCKR(GPIOF) /* Alternate function low register (GPIOx_AFRL) */ #define GPIO_AFRL(port) MMIO32(port + 0x20) #define GPIOA_AFRL GPIO_AFRL(GPIOA) #define GPIOB_AFRL GPIO_AFRL(GPIOB) #define GPIOC_AFRL GPIO_AFRL(GPIOC) #define GPIOD_AFRL GPIO_AFRL(GPIOD) #define GPIOE_AFRL GPIO_AFRL(GPIOE) #define GPIOF_AFRL GPIO_AFRL(GPIOF) /* Alternate function high register (GPIOx_AFRH) */ #define GPIO_AFRH(port) MMIO32(port + 0x24) #define GPIOA_AFRH GPIO_AFRH(GPIOA) #define GPIOB_AFRH GPIO_AFRH(GPIOB) #define GPIOC_AFRH GPIO_AFRH(GPIOC) #define GPIOD_AFRH GPIO_AFRH(GPIOD) #define GPIOE_AFRH GPIO_AFRH(GPIOE) #define GPIOF_AFRH GPIO_AFRH(GPIOF) /* --- GPIOx_MODER values -------------------------------------------------- */ #define GPIO_MODE(n, mode) (mode << (2 * (n))) #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode @ingroup gpio_defines @{*/ #define GPIO_MODE_INPUT 0x0 #define GPIO_MODE_OUTPUT 0x1 #define GPIO_MODE_AF 0x2 #define GPIO_MODE_ANALOG 0x3 /**@}*/ /* --- GPIOx_OTYPER values ------------------------------------------------- */ /** @defgroup gpio_output_type GPIO Output Pin Driver Type @ingroup gpio_defines @list Push Pull @list Open Drain @{*/ #define GPIO_OTYPE_PP 0x0 #define GPIO_OTYPE_OD 0x1 /**@}*/ /* --- GPIOx_OSPEEDR values ------------------------------------------------ */ #define GPIO_OSPEED(n, speed) (speed << (2 * (n))) #define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_speed GPIO Output Pin Speed @ingroup gpio_defines @{*/ #define GPIO_OSPEED_2MHZ 0x0 #define GPIO_OSPEED_25MHZ 0x1 #define GPIO_OSPEED_50MHZ 0x2 #define GPIO_OSPEED_100MHZ 0x3 /**@}*/ /* --- GPIOx_PUPDR values -------------------------------------------------- */ #define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) #define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_pup GPIO Output Pin Pullup @ingroup gpio_defines @{*/ #define GPIO_PUPD_NONE 0x0 #define GPIO_PUPD_PULLUP 0x1 #define GPIO_PUPD_PULLDOWN 0x2 /**@}*/ /* --- GPIOx_IDR values ---------------------------------------------------- */ /* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ /* --- GPIOx_ODR values ---------------------------------------------------- */ /* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ /* --- GPIOx_BSRR values --------------------------------------------------- */ /* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ /* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ /* --- GPIOx_LCKR values --------------------------------------------------- */ #define GPIO_LCKK (1 << 16) /* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ /* --- GPIOx_AFRL/H values ------------------------------------------------- */ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See datasheet table 6 (pg. 48) for alternate function mappings. */ #define GPIO_AFR(n, af) (af << ((n) * 4)) #define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) /** @defgroup gpio_af_num Alternate Function Pin Selection @ingroup gpio_defines @{*/ #define GPIO_AF0 0x0 #define GPIO_AF1 0x1 #define GPIO_AF2 0x2 #define GPIO_AF3 0x3 #define GPIO_AF4 0x4 #define GPIO_AF5 0x5 #define GPIO_AF6 0x6 #define GPIO_AF7 0x7 #define GPIO_AF8 0x8 #define GPIO_AF9 0x9 #define GPIO_AF10 0xa #define GPIO_AF11 0xb #define GPIO_AF12 0xc #define GPIO_AF13 0xd #define GPIO_AF14 0xe #define GPIO_AF15 0xf /**@}*/ /* Note: EXTI source selection is now in the SYSCFG peripheral. */ /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS /* * Note: The F2 and F4 series have a completely new GPIO peripheral with * different configuration options. Here we implement a different API partly to * more closely match the peripheral capabilities and also to deliberately * break compatibility with old F1 code so there is no confusion with similar * sounding functions that have very different functionality. */ void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios); void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios); void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios); END_DECLS /**@}*/ #endif /** @cond */ #else #warning "gpio_common_f234.h should not be included explicitly, only via gpio.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/gpio_common_f24.h000066400000000000000000000070071435536612600265450ustar00rootroot00000000000000/** @addtogroup gpio_defines @author @htmlonly © @endhtmlonly 2011 Fergus Noble @author @htmlonly © @endhtmlonly 2012 Ken Sarkies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H The order of header inclusion is important. gpio.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_GPIO_H /** @endcond */ #ifndef LIBOPENCM3_GPIO_COMMON_F24_H #define LIBOPENCM3_GPIO_COMMON_F24_H /**@{*/ #include #include /* GPIO port base addresses (for convenience) */ /** @defgroup gpio_port_id GPIO Port IDs @ingroup gpio_defines @{*/ #define GPIOG GPIO_PORT_G_BASE #define GPIOH GPIO_PORT_H_BASE #define GPIOI GPIO_PORT_I_BASE /**@}*/ /* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ /* Port mode register (GPIOx_MODER) */ #define GPIOG_MODER GPIO_MODER(GPIOG) #define GPIOH_MODER GPIO_MODER(GPIOH) #define GPIOI_MODER GPIO_MODER(GPIOI) /* Port output type register (GPIOx_OTYPER) */ #define GPIOG_OTYPER GPIO_OTYPER(GPIOG) #define GPIOH_OTYPER GPIO_OTYPER(GPIOH) #define GPIOI_OTYPER GPIO_OTYPER(GPIOI) /* Port output speed register (GPIOx_OSPEEDR) */ #define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG) #define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) #define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI) /* Port pull-up/pull-down register (GPIOx_PUPDR) */ #define GPIOG_PUPDR GPIO_PUPDR(GPIOG) #define GPIOH_PUPDR GPIO_PUPDR(GPIOH) #define GPIOI_PUPDR GPIO_PUPDR(GPIOI) /* Port input data register (GPIOx_IDR) */ #define GPIOG_IDR GPIO_IDR(GPIOG) #define GPIOH_IDR GPIO_IDR(GPIOH) #define GPIOI_IDR GPIO_IDR(GPIOI) /* Port output data register (GPIOx_ODR) */ #define GPIOG_ODR GPIO_ODR(GPIOG) #define GPIOH_ODR GPIO_ODR(GPIOH) #define GPIOI_ODR GPIO_ODR(GPIOI) /* Port bit set/reset register (GPIOx_BSRR) */ #define GPIOG_BSRR GPIO_BSRR(GPIOG) #define GPIOH_BSRR GPIO_BSRR(GPIOH) #define GPIOI_BSRR GPIO_BSRR(GPIOI) /* Port configuration lock register (GPIOx_LCKR) */ #define GPIOG_LCKR GPIO_LCKR(GPIOG) #define GPIOH_LCKR GPIO_LCKR(GPIOH) #define GPIOI_LCKR GPIO_LCKR(GPIOI) /* Alternate function low register (GPIOx_AFRL) */ #define GPIOG_AFRL GPIO_AFRL(GPIOG) #define GPIOH_AFRL GPIO_AFRL(GPIOH) #define GPIOI_AFRL GPIO_AFRL(GPIOI) /* Alternate function high register (GPIOx_AFRH) */ #define GPIOG_AFRH GPIO_AFRH(GPIOG) #define GPIOH_AFRH GPIO_AFRH(GPIOH) #define GPIOI_AFRH GPIO_AFRH(GPIOI) #endif /** @cond */ #else #warning "gpio_common_f24.h should not be included explicitly, only via gpio.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/hash_common_f24.h000066400000000000000000000117241435536612600265330ustar00rootroot00000000000000/** @addtogroup hash_defines @author @htmlonly © @endhtmlonly 2013 Mikhail Avkhimenia */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Mikhail Avkhimenia * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifdef LIBOPENCM3_HASH_H #ifndef LIBOPENCM3_HASH_COMMON_F24_H #define LIBOPENCM3_HASH_COMMON_F24_H #include /* --- Convenience macros -------------------------------------------------- */ /****************************************************************************/ /** @defgroup hash_reg_base HASH register base addresses @ingroup STM32F_hash_defines @{*/ #define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) #define HASH HASH_BASE /**@}*/ /* --- HASH registers ------------------------------------------------------ */ /* HASH control register (HASH_CR) */ #define HASH_CR MMIO32(HASH + 0x00) /* HASH data input register (HASH_DIR) */ #define HASH_DIN MMIO32(HASH + 0x04) /* HASH start register (HASH_STR) */ #define HASH_STR MMIO32(HASH + 0x08) /* HASH digest registers (HASH_HR[5]) */ #define HASH_HR (&MMIO32(HASH + 0x0C)) /* x5 */ /* HASH interrupt enable register (HASH_IMR) */ #define HASH_IMR MMIO32(HASH + 0x20) /* HASH status register (HASH_SR) */ #define HASH_SR MMIO32(HASH + 0x28) /* HASH context swap registers (HASH_CSR[51]) */ #define HASH_CSR (&MMIO32(HASH + 0xF8)) /* x51 */ /* --- HASH_CR values ------------------------------------------------------ */ /* INIT: Initialize message digest calculation */ #define HASH_CR_INIT (1 << 2) /* DMAE: DMA enable */ #define HASH_CR_DMAE (1 << 3) /* DATATYPE: Data type selection */ /****************************************************************************/ /** @defgroup hash_data_type HASH Data Type @ingroup hash_defines @{*/ #define HASH_DATA_32BIT (0 << 4) #define HASH_DATA_16BIT (1 << 4) #define HASH_DATA_8BIT (2 << 4) #define HASH_DATA_BITSTRING (3 << 4) /**@}*/ #define HASH_CR_DATATYPE (3 << 4) /* MODE: Mode selection */ /****************************************************************************/ /** @defgroup hash_mode HASH Mode @ingroup hash_defines @{*/ #define HASH_MODE_HASH (0 << 6) #define HASH_MODE_HMAC (1 << 6) /**@}*/ #define HASH_CR_MODE (1 << 6) /* ALGO: Algorithm selection */ /****************************************************************************/ /** @defgroup hash_algorithm HASH Algorithm @ingroup hash_defines @{*/ #define HASH_ALGO_SHA1 (0 << 7) #define HASH_ALGO_MD5 (1 << 7) /**@}*/ #define HASH_CR_ALGO (1 << 7) /* NBW: Number of words already pushed */ #define HASH_CR_NBW (15 << 8) /* DINNE: DIN(Data input register) not empty */ #define HASH_CR_DINNE (1 << 12) /* LKEY: Long key selection */ /****************************************************************************/ /** @defgroup hash_key_length HASH Key length @ingroup hash_defines @{*/ #define HASH_KEY_SHORT (0 << 16) #define HASH_KEY_LONG (1 << 16) /**@}*/ #define HASH_CR_LKEY (1 << 16) /* --- HASH_STR values ----------------------------------------------------- */ /* NBLW: Number of valid bits in the last word of the message in the bit string */ #define HASH_STR_NBW (31 << 0) /* DCAL: Digest calculation */ #define HASH_STR_DCAL (1 << 8) /* --- HASH_IMR values ----------------------------------------------------- */ /* DINIE: Data input interrupt enable */ #define HASH_IMR_DINIE (1 << 0) /* DCIE: Digest calculation completion interrupt enable */ #define HASH_IMR_DCIE (1 << 1) /* --- HASH_SR values ------------------------------------------------------ */ /* DINIS: Data input interrupt status */ #define HASH_SR_DINIS (1 << 0) /* DCIS: Digest calculation completion interrupt status */ #define HASH_SR_DCIS (1 << 1) /* DMAS: DMA Status */ #define HASH_SR_DMAS (1 << 2) /* BUSY: Busy bit */ #define HASH_SR_BUSY (1 << 3) /* --- HASH function prototypes -------------------------------------------- */ BEGIN_DECLS void hash_set_mode(uint8_t mode); void hash_set_algorithm(uint8_t algorithm); void hash_set_data_type(uint8_t datatype); void hash_set_key_length(uint8_t keylength); void hash_set_last_word_valid_bits(uint8_t validbits); void hash_init(void); void hash_add_data(uint32_t data); void hash_digest(void); void hash_get_result(uint32_t *data); END_DECLS /**@}*/ #endif #else #warning "hash_common_f24.h should not be included explicitly, only via hash.h" #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/i2c_common_all.h000066400000000000000000000265411435536612600264450ustar00rootroot00000000000000/** @addtogroup i2c_defines @author @htmlonly © @endhtmlonly 2010 Thomas Otto */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H The order of header inclusion is important. i2c.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #if defined(LIBOPENCM3_I2C_H) || defined(LIBOPENCM3_I2C_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_I2C_COMMON_ALL_H #define LIBOPENCM3_I2C_COMMON_ALL_H #include /**@{*/ /* --- Convenience macros -------------------------------------------------- */ /* I2C register base addresses (for convenience) */ /****************************************************************************/ /** @defgroup i2c_reg_base I2C register base address @ingroup i2c_defines @{*/ #define I2C1 I2C1_BASE #define I2C2 I2C2_BASE /**@}*/ /* --- I2C registers ------------------------------------------------------- */ /* Control register 1 (I2Cx_CR1) */ #define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) #define I2C1_CR1 I2C_CR1(I2C1) #define I2C2_CR1 I2C_CR1(I2C2) /* Control register 2 (I2Cx_CR2) */ #define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) #define I2C1_CR2 I2C_CR2(I2C1) #define I2C2_CR2 I2C_CR2(I2C2) /* Own address register 1 (I2Cx_OAR1) */ #define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) #define I2C1_OAR1 I2C_OAR1(I2C1) #define I2C2_OAR1 I2C_OAR1(I2C2) /* Own address register 2 (I2Cx_OAR2) */ #define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) #define I2C1_OAR2 I2C_OAR2(I2C1) #define I2C2_OAR2 I2C_OAR2(I2C2) /* Data register (I2Cx_DR) */ #define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) #define I2C1_DR I2C_DR(I2C1) #define I2C2_DR I2C_DR(I2C2) /* Status register 1 (I2Cx_SR1) */ #define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) #define I2C1_SR1 I2C_SR1(I2C1) #define I2C2_SR1 I2C_SR1(I2C2) /* Status register 2 (I2Cx_SR2) */ #define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) #define I2C1_SR2 I2C_SR2(I2C1) #define I2C2_SR2 I2C_SR2(I2C2) /* Clock control register (I2Cx_CCR) */ #define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) #define I2C1_CCR I2C_CCR(I2C1) #define I2C2_CCR I2C_CCR(I2C2) /* TRISE register (I2Cx_CCR) */ #define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) #define I2C1_TRISE I2C_TRISE(I2C1) #define I2C2_TRISE I2C_TRISE(I2C2) /* --- I2Cx_CR1 values ----------------------------------------------------- */ /* SWRST: Software reset */ #define I2C_CR1_SWRST (1 << 15) /* Note: Bit 14 is reserved, and forced to 0 by hardware. */ /* ALERT: SMBus alert */ #define I2C_CR1_ALERT (1 << 13) /* PEC: Packet error checking */ #define I2C_CR1_PEC (1 << 12) /* POS: Acknowledge / PEC position */ #define I2C_CR1_POS (1 << 11) /* ACK: Acknowledge enable */ #define I2C_CR1_ACK (1 << 10) /* STOP: STOP generation */ #define I2C_CR1_STOP (1 << 9) /* START: START generation */ #define I2C_CR1_START (1 << 8) /* NOSTRETCH: Clock stretching disable (slave mode) */ #define I2C_CR1_NOSTRETCH (1 << 7) /* ENGC: General call enable */ #define I2C_CR1_ENGC (1 << 6) /* ENPEC: Enable PEC */ #define I2C_CR1_ENPEC (1 << 5) /* ENARP: ARP enable */ #define I2C_CR1_ENARP (1 << 4) /* SMBTYPE: SMBus type */ #define I2C_CR1_SMBTYPE (1 << 3) /* Note: Bit 2 is reserved, and forced to 0 by hardware. */ /* SMBUS: SMBus mode */ #define I2C_CR1_SMBUS (1 << 1) /* PE: Peripheral enable */ #define I2C_CR1_PE (1 << 0) /* --- I2Cx_CR2 values ----------------------------------------------------- */ /* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ /* LAST: DMA last transfer */ #define I2C_CR2_LAST (1 << 12) /* DMAEN: DMA requests enable */ #define I2C_CR2_DMAEN (1 << 11) /* ITBUFEN: Buffer interrupt enable */ #define I2C_CR2_ITBUFEN (1 << 10) /* ITEVTEN: Event interrupt enable */ #define I2C_CR2_ITEVTEN (1 << 9) /* ITERREN: Error interrupt enable */ #define I2C_CR2_ITERREN (1 << 8) /* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ /* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ /****************************************************************************/ /** @defgroup i2c_clock I2C clock frequency settings @ingroup i2c_defines @{*/ #define I2C_CR2_FREQ_2MHZ 0x02 #define I2C_CR2_FREQ_3MHZ 0x03 #define I2C_CR2_FREQ_4MHZ 0x04 #define I2C_CR2_FREQ_5MHZ 0x05 #define I2C_CR2_FREQ_6MHZ 0x06 #define I2C_CR2_FREQ_7MHZ 0x07 #define I2C_CR2_FREQ_8MHZ 0x08 #define I2C_CR2_FREQ_9MHZ 0x09 #define I2C_CR2_FREQ_10MHZ 0x0a #define I2C_CR2_FREQ_11MHZ 0x0b #define I2C_CR2_FREQ_12MHZ 0x0c #define I2C_CR2_FREQ_13MHZ 0x0d #define I2C_CR2_FREQ_14MHZ 0x0e #define I2C_CR2_FREQ_15MHZ 0x0f #define I2C_CR2_FREQ_16MHZ 0x10 #define I2C_CR2_FREQ_17MHZ 0x11 #define I2C_CR2_FREQ_18MHZ 0x12 #define I2C_CR2_FREQ_19MHZ 0x13 #define I2C_CR2_FREQ_20MHZ 0x14 #define I2C_CR2_FREQ_21MHZ 0x15 #define I2C_CR2_FREQ_22MHZ 0x16 #define I2C_CR2_FREQ_23MHZ 0x17 #define I2C_CR2_FREQ_24MHZ 0x18 #define I2C_CR2_FREQ_25MHZ 0x19 #define I2C_CR2_FREQ_26MHZ 0x1a #define I2C_CR2_FREQ_27MHZ 0x1b #define I2C_CR2_FREQ_28MHZ 0x1c #define I2C_CR2_FREQ_29MHZ 0x1d #define I2C_CR2_FREQ_30MHZ 0x1e #define I2C_CR2_FREQ_31MHZ 0x1f #define I2C_CR2_FREQ_32MHZ 0x20 #define I2C_CR2_FREQ_33MHZ 0x21 #define I2C_CR2_FREQ_34MHZ 0x22 #define I2C_CR2_FREQ_35MHZ 0x23 #define I2C_CR2_FREQ_36MHZ 0x24 /**@}*/ /* --- I2Cx_OAR1 values ---------------------------------------------------- */ /* ADDMODE: Addressing mode (slave mode) */ #define I2C_OAR1_ADDMODE (1 << 15) #define I2C_OAR1_ADDMODE_7BIT 0 #define I2C_OAR1_ADDMODE_10BIT 1 /* Note: Bit 14 should always be kept at 1 by software! */ /* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ /* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ /* --- I2Cx_OAR2 values ---------------------------------------------------- */ /* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ /* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ /* ENDUAL: Dual addressing mode enable */ #define I2C_OAR2_ENDUAL (1 << 0) /* --- I2Cx_DR values ------------------------------------------------------ */ /* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ /* DR[7:0] 8-bit data register */ /* --- I2Cx_SR1 values ----------------------------------------------------- */ /* SMBALERT: SMBus alert */ #define I2C_SR1_SMBALERT (1 << 15) /* TIMEOUT: Timeout or Tlow Error */ #define I2C_SR1_TIMEOUT (1 << 14) /* Note: Bit 13 is reserved, and forced to 0 by hardware. */ /* PECERR: PEC Error in reception */ #define I2C_SR1_PECERR (1 << 12) /* OVR: Overrun/Underrun */ #define I2C_SR1_OVR (1 << 11) /* AF: Acknowledge failure */ #define I2C_SR1_AF (1 << 10) /* ARLO: Arbitration lost (master mode) */ #define I2C_SR1_ARLO (1 << 9) /* BERR: Bus error */ #define I2C_SR1_BERR (1 << 8) /* TxE: Data register empty (transmitters) */ #define I2C_SR1_TxE (1 << 7) /* RxNE: Data register not empty (receivers) */ #define I2C_SR1_RxNE (1 << 6) /* Note: Bit 5 is reserved, and forced to 0 by hardware. */ /* STOPF: STOP detection (slave mode) */ #define I2C_SR1_STOPF (1 << 4) /* ADD10: 10-bit header sent (master mode) */ #define I2C_SR1_ADD10 (1 << 3) /* BTF: Byte transfer finished */ #define I2C_SR1_BTF (1 << 2) /* ADDR: Address sent (master mode) / address matched (slave mode) */ #define I2C_SR1_ADDR (1 << 1) /* SB: Start bit (master mode) */ #define I2C_SR1_SB (1 << 0) /* --- I2Cx_SR2 values ----------------------------------------------------- */ /* Bits [15:8]: PEC[7:0]: Packet error checking register */ /* DUALF: Dual flag (slave mode) */ #define I2C_SR2_DUALF (1 << 7) /* SMBHOST: SMBus host header (slave mode) */ #define I2C_SR2_SMBHOST (1 << 6) /* SMBDEFAULT: SMBus device default address (slave mode) */ #define I2C_SR2_SMBDEFAULT (1 << 5) /* GENCALL: General call address (slave mode) */ #define I2C_SR2_GENCALL (1 << 4) /* Note: Bit 3 is reserved, and forced to 0 by hardware. */ /* TRA: Transmitter / receiver */ #define I2C_SR2_TRA (1 << 2) /* BUSY: Bus busy */ #define I2C_SR2_BUSY (1 << 1) /* MSL: Master / slave */ #define I2C_SR2_MSL (1 << 0) /* --- I2Cx_CCR values ----------------------------------------------------- */ /* F/S: I2C Master mode selection (fast / standard) */ #define I2C_CCR_FS (1 << 15) /* DUTY: Fast Mode Duty Cycle */ /** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles @ingroup i2c_defines @{*/ #define I2C_CCR_DUTY (1 << 14) #define I2C_CCR_DUTY_DIV2 0 #define I2C_CCR_DUTY_16_DIV_9 1 /**@}*/ /* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ /* * Bits [11:0]: * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) */ /* --- I2Cx_TRISE values --------------------------------------------------- */ /* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ /* * Bits [5:0]: * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) */ /* --- I2C constant definitions -------------------------------------------- */ /****************************************************************************/ /** @defgroup i2c_rw I2C Read/Write bit @ingroup i2c_defines @{*/ #define I2C_WRITE 0 #define I2C_READ 1 /**@}*/ /* --- I2C function prototypes---------------------------------------------- */ BEGIN_DECLS void i2c_reset(uint32_t i2c); void i2c_peripheral_enable(uint32_t i2c); void i2c_peripheral_disable(uint32_t i2c); void i2c_send_start(uint32_t i2c); void i2c_send_stop(uint32_t i2c); void i2c_clear_stop(uint32_t i2c); void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); void i2c_send_data(uint32_t i2c, uint8_t data); void i2c_set_fast_mode(uint32_t i2c); void i2c_set_standard_mode(uint32_t i2c); void i2c_set_ccr(uint32_t i2c, uint16_t freq); void i2c_set_trise(uint32_t i2c, uint16_t trise); void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite); uint8_t i2c_get_data(uint32_t i2c); void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); void i2c_enable_ack(uint32_t i2c); void i2c_disable_ack(uint32_t i2c); void i2c_nack_next(uint32_t i2c); void i2c_nack_current(uint32_t i2c); void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle); void i2c_enable_dma(uint32_t i2c); void i2c_disable_dma(uint32_t i2c); void i2c_set_dma_last_transfer(uint32_t i2c); void i2c_clear_dma_last_transfer(uint32_t i2c); END_DECLS #endif /** @cond */ #else #warning "i2c_common_all.h should not be included explicitly, only via i2c.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/i2c_common_f24.h000066400000000000000000000026651435536612600262710ustar00rootroot00000000000000/** @addtogroup i2c_defines @author @htmlonly © @endhtmlonly 2012 Ken Sarkies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H The order of header inclusion is important. i2c.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_I2C_H /** @endcond */ #ifndef LIBOPENCM3_I2C_COMMON_F24_H #define LIBOPENCM3_I2C_COMMON_F24_H #include /**@{*/ #define I2C3 I2C3_BASE /**@}*/ #endif /** @cond */ #else #warning "i2c_common_f24.h should not be included explicitly, only via i2c.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/iwdg_common_all.h000066400000000000000000000064761435536612600267270ustar00rootroot00000000000000/** @addtogroup iwdg_defines @author @htmlonly © @endhtmlonly 2010 Thomas Otto */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H The order of header inclusion is important. iwdg.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_IWDG_H /** @endcond */ #ifndef LIBOPENCM3_IWDG_COMMON_ALL_H #define LIBOPENCM3_IWDG_COMMON_ALL_H #include /**@{*/ /* --- IWDG registers ------------------------------------------------------ */ /* Key Register (IWDG_KR) */ #define IWDG_KR MMIO32(IWDG_BASE + 0x00) /* Prescaler register (IWDG_PR) */ #define IWDG_PR MMIO32(IWDG_BASE + 0x04) /* Reload register (IWDG_RLR) */ #define IWDG_RLR MMIO32(IWDG_BASE + 0x08) /* Status register (IWDG_SR) */ #define IWDG_SR MMIO32(IWDG_BASE + 0x0c) /* --- IWDG_KR values ------------------------------------------------------ */ /* Bits [31:16]: Reserved. */ /* KEY[15:0]: Key value (write-only, reads as 0x0000) */ /** @defgroup iwdg_key IWDG Key Values @ingroup STM32F_iwdg_defines @{*/ #define IWDG_KR_RESET 0xaaaa #define IWDG_KR_UNLOCK 0x5555 #define IWDG_KR_START 0xcccc /**@}*/ /* --- IWDG_PR values ------------------------------------------------------ */ /* Bits [31:3]: Reserved. */ /* PR[2:0]: Prescaler divider */ #define IWDG_PR_LSB 0 /** @defgroup iwdg_prediv IWDG prescaler divider @ingroup STM32F_iwdg_defines @{*/ #define IWDG_PR_DIV4 0x0 #define IWDG_PR_DIV8 0x1 #define IWDG_PR_DIV16 0x2 #define IWDG_PR_DIV32 0x3 #define IWDG_PR_DIV64 0x4 #define IWDG_PR_DIV128 0x5 #define IWDG_PR_DIV256 0x6 /**@}*/ /* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ /* #define IWDG_PR_DIV256 0x7 */ /* --- IWDG_RLR values ----------------------------------------------------- */ /* Bits [31:12]: Reserved. */ /* RL[11:0]: Watchdog counter reload value */ /* --- IWDG_SR values ------------------------------------------------------ */ /* Bits [31:2]: Reserved. */ /* RVU: Watchdog counter reload value update */ #define IWDG_SR_RVU (1 << 1) /* PVU: Watchdog prescaler value update */ #define IWDG_SR_PVU (1 << 0) /* --- IWDG function prototypes---------------------------------------------- */ BEGIN_DECLS void iwdg_start(void); void iwdg_set_period_ms(uint32_t period); bool iwdg_reload_busy(void); bool iwdg_prescaler_busy(void); void iwdg_reset(void); END_DECLS #endif /** @cond */ #else #warning "iwdg_common_all.h should not be included explicitly, only via iwdg.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/pwr_common_all.h000066400000000000000000000075431435536612600266010ustar00rootroot00000000000000/** @addtogroup pwr_defines @author @htmlonly © @endhtmlonly 2010 Thomas Otto */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H The order of header inclusion is important. pwr.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_PWR_H /** @endcond */ #ifndef LIBOPENCM3_PWR_COMMON_ALL_H #define LIBOPENCM3_PWR_COMMON_ALL_H /**@{*/ #include /* --- PWR registers ------------------------------------------------------- */ /* Power control register (PWR_CR) */ #define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) /* Power control/status register (PWR_CSR) */ #define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) /* --- PWR_CR values ------------------------------------------------------- */ /* Bits [31:9]: Reserved, must be kept at reset value. */ /* DBP: Disable backup domain write protection */ #define PWR_CR_DBP (1 << 8) /* PLS[7:5]: PVD level selection */ #define PWR_CR_PLS_LSB 5 /** @defgroup pwr_pls PVD level selection @ingroup STM32F_pwr_defines @{*/ #define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB) /**@}*/ #define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) /* PVDE: Power voltage detector enable */ #define PWR_CR_PVDE (1 << 4) /* CSBF: Clear standby flag */ #define PWR_CR_CSBF (1 << 3) /* CWUF: Clear wakeup flag */ #define PWR_CR_CWUF (1 << 2) /* PDDS: Power down deepsleep */ #define PWR_CR_PDDS (1 << 1) /* LPDS: Low-power deepsleep */ #define PWR_CR_LPDS (1 << 0) /* --- PWR_CSR values ------------------------------------------------------ */ /* Bits [31:9]: Reserved, must be kept at reset value. */ /* EWUP: Enable WKUP pin */ #define PWR_CSR_EWUP (1 << 8) /* Bits [7:3]: Reserved, must be kept at reset value. */ /* PVDO: PVD output */ #define PWR_CSR_PVDO (1 << 2) /* SBF: Standby flag */ #define PWR_CSR_SBF (1 << 1) /* WUF: Wakeup flag */ #define PWR_CSR_WUF (1 << 0) /* --- PWR function prototypes ------------------------------------------- */ BEGIN_DECLS void pwr_disable_backup_domain_write_protect(void); void pwr_enable_backup_domain_write_protect(void); void pwr_enable_power_voltage_detect(uint32_t pvd_level); void pwr_disable_power_voltage_detect(void); void pwr_clear_standby_flag(void); void pwr_clear_wakeup_flag(void); void pwr_set_standby_mode(void); void pwr_set_stop_mode(void); void pwr_voltage_regulator_on_in_stop(void); void pwr_voltage_regulator_low_power_in_stop(void); void pwr_enable_wakeup_pin(void); void pwr_disable_wakeup_pin(void); bool pwr_voltage_high(void); bool pwr_get_standby_flag(void); bool pwr_get_wakeup_flag(void); END_DECLS /**@}*/ #endif /** @cond */ #else #warning "pwr_common_all.h should not be included explicitly, only via pwr.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/rng_common_f24.h000066400000000000000000000040721435536612600263740ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H The order of header inclusion is important. rng.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_RNG_H /** @endcond */ #ifndef LIBOPENCM3_RNG_COMMON_F24_H #define LIBOPENCM3_RNG_COMMON_F24_H #include #include /* --- Random number generator registers ----------------------------------- */ /* Control register */ #define RNG_CR MMIO32(RNG_BASE + 0x00) /* Status register */ #define RNG_SR MMIO32(RNG_BASE + 0x04) /* Data register */ #define RNG_DR MMIO32(RNG_BASE + 0x08) /* --- RNG_CR values ------------------------------------------------------- */ /* RNG ENABLE */ #define RNG_CR_RNGEN (1 << 2) /* RNG interrupt enable */ #define RNG_CR_IE (1 << 3) /* --- RNG_SR values ------------------------------------------------------- */ /* Data ready */ #define RNG_SR_DRDY (1 << 0) /* Clock error current status */ #define RNG_SR_CECS (1 << 1) /* Seed error current status */ #define RNG_SR_SECS (1 << 2) /* Clock error interrupt status */ #define RNG_SR_CEIS (1 << 5) /* Seed error interrupt status */ #define RNG_SR_SEIS (1 << 6) #endif /** @cond */ #else #warning "rng_common_f24.h should not be included explicitly, only via rng.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/rtc_common_l1f024.h000066400000000000000000000345241435536612600267200ustar00rootroot00000000000000/** @addtogroup rtc_defines @author @htmlonly © @endhtmlonly 2012 Karl Palsson */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * This covers the "version 2" RTC peripheral. This is completely different * to the v1 RTC periph on the F1 series devices. It has BCD counters, with * automatic leapyear corrections and daylight savings support. * This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some * only support a subset. */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H The order of header inclusion is important. rtc.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_RTC_H /** @endcond */ #ifndef LIBOPENCM3_RTC2_H #define LIBOPENCM3_RTC2_H /**@{*/ #include #include /* RTC time register (RTC_TR) */ #define RTC_TR MMIO32(RTC_BASE + 0x00) /* RTC date register (RTC_DR) */ #define RTC_DR MMIO32(RTC_BASE + 0x04) /* RTC control register (RTC_CR) */ #define RTC_CR MMIO32(RTC_BASE + 0x08) /* RTC initialization and status register (RTC_ISR) */ #define RTC_ISR MMIO32(RTC_BASE + 0x0c) /* RTC prescaler register (RTC_PRER) */ #define RTC_PRER MMIO32(RTC_BASE + 0x10) /* RTC wakeup timer register (RTC_WUTR) */ #define RTC_WUTR MMIO32(RTC_BASE + 0x14) /* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */ #define RTC_CALIBR MMIO32(RTC_BASE + 0x18) /* RTC alarm X register (RTC_ALRMxR) */ #define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c) #define RTC_ALRMBR MMIO32(RTC_BASE + 0x20) /* RTC write protection register (RTC_WPR)*/ #define RTC_WPR MMIO32(RTC_BASE + 0x24) /* RTC sub second register (RTC_SSR) (high and med+ only) */ #define RTC_SSR MMIO32(RTC_BASE + 0x28) /* RTC shift control register (RTC_SHIFTR) (high and med+ only) */ #define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c) /* RTC time stamp time register (RTC_TSTR) */ #define RTC_TSTR MMIO32(RTC_BASE + 0x30) /* RTC time stamp date register (RTC_TSDR) */ #define RTC_TSDR MMIO32(RTC_BASE + 0x34) /* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */ #define RTC_TSSSR MMIO32(RTC_BASE + 0x38) /* RTC calibration register (RTC_CALR) (high and med+ only) */ #define RTC_CALR MMIO32(RTC_BASE + 0x3c) /* RTC tamper and alternate function configuration register (RTC_TAFCR) */ #define RTC_TAFCR MMIO32(RTC_BASE + 0x40) /* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */ #define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44) #define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48) /* RTC backup registers (RTC_BKPxR) */ #define RTC_BKP_BASE (RTC_BASE + 0x50) #define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg)) /* RTC time register (RTC_TR) ----------------------------------- */ /* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. */ #define RTC_TR_PM (1 << 22) /* AM/PM notation */ #define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */ #define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */ #define RTC_TR_HU_SHIFT (16) /* Hour units in BCD format shift */ #define RTC_TR_HU_MASK (0xf) /* Hour units in BCD format mask */ #define RTC_TR_MNT_SHIFT (12) /* Minute tens in BCD format shift */ #define RTC_TR_MNT_MASK (0x7) /* Minute tens in BCD format mask */ #define RTC_TR_MNU_SHIFT (8) /* Minute units in BCD format shift */ #define RTC_TR_MNU_MASK (0xf) /* Minute units in BCD format mask */ #define RTC_TR_ST_SHIFT (4) /* Second tens in BCD format shift */ #define RTC_TR_ST_MASK (0x7) /* Second tens in BCD format mask */ #define RTC_TR_SU_SHIFT (0) /* Second units in BCD format shift */ #define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */ /* RTC date register (RTC_DR) ----------------------------------- */ /* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. */ #define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */ #define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */ #define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */ #define RTC_DR_YU_MASK (0xf) /* Year units in BCD format mask */ #define RTC_DR_WDU_SHIFT (13) /* Weekday units shift */ #define RTC_DR_WDU_MASK (0x7) /* Weekday units mask */ #define RTC_DR_MT (1<<12) /* Month tens in BCD format shift */ #define RTC_DR_MT_SHIFT (12) /* Month tens in BCD format mask */ #define RTC_DR_MU_SHIFT (8) /* Month units in BCD format shift */ #define RTC_DR_MU_MASK (0xf) /* Month units in BCD format mask */ #define RTC_DR_DT_SHIFT (4) /* Date tens in BCD format shift */ #define RTC_DR_DT_MASK (0x3) /* Date tens in BCD format mask */ #define RTC_DR_DU_SHIFT (0) /* Date units in BCD format shift */ #define RTC_DR_DU_MASK (0xf) /* Date units in BCD format mask */ /* RTC control register (RTC_CR) -------------------------------- */ /* Note: Bits [31:24] are reserved, and must be kept at reset value. */ /* Note: Bits 7, 6 and 4 of this register can be written in initialization mode * only (RTC_ISR/INITF = 1). */ /* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit * = 0 and RTC_ISR WUTWF bit = 1. */ #define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */ /* RTC_CR_OSEL: Output selection values */ /* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC * output */ #define RTC_CR_OSEL_SHIFT 21 #define RTC_CR_OSEL_MASK (0x3) #define RTC_CR_OSEL_DISABLED (0x0) #define RTC_CR_OSEL_ALARMA (0x1) #define RTC_CR_OSEL_ALARMB (0x2) #define RTC_CR_OSEL_WAKEUP (0x3) #define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */ #define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output selection */ #define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */ #define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour (winter time change) */ #define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer time change) */ #define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt enable */ #define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer interrupt enable */ #define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt enable */ #define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt enable */ #define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */ #define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */ #define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */ #define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */ #define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital calibration enable */ #define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */ #define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow registers */ #define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock detection enable */ #define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event active edge */ /* RTC_CR_WUCKSEL: Wakeup clock selection */ #define RTC_CR_WUCLKSEL_SHIFT (0) #define RTC_CR_WUCLKSEL_MASK (0x7) #define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0) #define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1) #define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2) #define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3) #define RTC_CR_WUCLKSEL_SPRE (0x4) #define RTC_CR_WUCLKSEL_SPRE_216 (0x6) /* RTC initialization and status register (RTC_ISR) ------------- */ /* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */ /* Note: This register is write protected (except for RTC_ISR[13:8] bits). */ #define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */ #define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag (not on F4)*/ #define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */ #define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */ #define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */ #define RTC_ISR_TSF (1<<11) /* TSF: Timestamp flag */ #define RTC_ISR_WUTF (1<<10) /* WUTF: Wakeup timer flag */ #define RTC_ISR_ALRBF (1<<9) /* ALRBF: Alarm B flag */ #define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */ #define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */ #define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */ #define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */ #define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */ #define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */ #define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */ #define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */ #define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */ /* RTC prescaler register (RTC_PRER) ---------------------------- */ #define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */ #define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */ #define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */ #define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */ /* RTC calibration register (RTC_CALIBR) ------------------------ */ /* FIXME - TODO */ /* RTC Alarm register ------------------------------------------- */ /* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */ #define RTC_ALRMXR_MSK4 (1<<31) #define RTC_ALRMXR_WDSEL (1<<30) #define RTC_ALRMXR_DT_SHIFT (28) #define RTC_ALRMXR_DT_MASK (0x3) #define RTC_ALRMXR_DU_SHIFT (24) #define RTC_ALRMXR_DU_MASK (0xf) #define RTC_ALRMXR_MSK3 (1<<23) #define RTC_ALRMXR_PM (1<<22) #define RTC_ALRMXR_HT_SHIFT (20) #define RTC_ALRMXR_HT_MASK (0x3) #define RTC_ALRMXR_HU_SHIFT (16) #define RTC_ALRMXR_HU_MASK (0xf) #define RTC_ALRMXR_MSK2 (1<<15) #define RTC_ALRMXR_MNT_SHIFT (12) #define RTC_ALRMXR_MNT_MASK (0x7) #define RTC_ALRMXR_MNU_SHIFT (8) #define RTC_ALRMXR_MNU_MASK (0xf) #define RTC_ALRMXR_MSK1 (1<<7) #define RTC_ALRMXR_ST_SHIFT (4) #define RTC_ALRMXR_ST_MASK (0x7) #define RTC_ALRMXR_SU_SHIFT (0) #define RTC_ALRMXR_SU_MASK (0xf) /* RTC shift control register (RTC_SHIFTR) */ /* FIXME - TODO */ /* RTC time stamp time register (RTC_TSTR) ---------------------- */ #define RTC_TSTR_PM (1<<22) #define RTC_TSTR_HT_SHIFT (20) #define RTC_TSTR_HT_MASK (0x3) #define RTC_TSTR_HU_SHIFT (16) #define RTC_TSTR_HU_MASK (0xf) #define RTC_TSTR_MNT_SHIFT (12) #define RTC_TSTR_MNT_MASK (0x7) #define RTC_TSTR_MNU_SHIFT (8) #define RTC_TSTR_MNU_MASK (0xf) #define RTC_TSTR_ST_SHIFT (4) #define RTC_TSTR_ST_MASK (0x7) #define RTC_TSTR_SU_SHIFT (0) #define RTC_TSTR_SU_MASK (0xf) /* RTC time stamp date register (RTC_TSDR) ---------------------- */ #define RTC_TSDR_WDU_SHIFT (13) #define RTC_TSDR_WDU_MASK (0x7) #define RTC_TSDR_MT (1<<12) #define RTC_TSDR_MU_SHIFT (8) #define RTC_TSDR_MU_MASK (0xf) #define RTC_TSDR_DT_SHIFT (4) #define RTC_TSDR_DT_MASK (0x3) #define RTC_TSDR_DU_SHIFT (0) #define RTC_TSDR_DU_MASK (0xf) /* RTC calibration register (RTC_CALR) -------------------------- */ /* FIXME - TODO */ /* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */ #define RTC_TAFCR_ALARMOUTTYPE (1<<18) #define RTC_TAFCR_TAMPPUDIS (1<<15) #define RTC_TAFCR_TAMPPRCH_SHIFT (13) #define RTC_TAFCR_TAMPPRCH_MASK (0x3) #define RTC_TAFCR_TAMPPRCH_1RTC (0x0) #define RTC_TAFCR_TAMPPRCH_2RTC (0x1) #define RTC_TAFCR_TAMPPRCH_4RTC (0x2) #define RTC_TAFCR_TAMPPRCH_8RTC (0x3) #define RTC_TAFCR_TAMPFLT_SHIFT (11) #define RTC_TAFCR_TAMPFLT_MASK (0x3) #define RTC_TAFCR_TAMPFLT_EDGE1 (0x0) #define RTC_TAFCR_TAMPFLT_EDGE2 (0x1) #define RTC_TAFCR_TAMPFLT_EDGE4 (0x2) #define RTC_TAFCR_TAMPFLT_EDGE8 (0x3) #define RTC_TAFCR_TAMPFREQ_SHIFT (8) #define RTC_TAFCR_TAMPFREQ_MASK (0x7) #define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0) #define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1) #define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2) #define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3) #define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4) #define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5) #define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6) #define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7) #define RTC_TAFCR_TAMPTS (1<<7) #define RTC_TAFCR_TAMP3TRG (1<<6) #define RTC_TAFCR_TAMP3E (1<<5) #define RTC_TAFCR_TAMP2TRG (1<<4) #define RTC_TAFCR_TAMP2E (1<<3) #define RTC_TAFCR_TAMPIE (1<<2) #define RTC_TAFCR_TAMP1TRG (1<<1) #define RTC_TAFCR_TAMP1E (1<<0) /* RTC alarm X sub second register */ /* FIXME - TODO */ BEGIN_DECLS void rtc_set_prescaler(uint32_t sync, uint32_t async); void rtc_wait_for_synchro(void); void rtc_lock(void); void rtc_unlock(void); void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel); void rtc_clear_wakeup_flag(void); END_DECLS /**@}*/ #endif /* RTC2_H */ /** @cond */ #else #warning "rtc_common_bcd.h should not be included explicitly, only via rtc.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/spi_common_all.h000066400000000000000000000311421435536612600265540ustar00rootroot00000000000000/** @addtogroup spi_defines @author @htmlonly © @endhtmlonly 2009 Uwe Hermann */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H The order of header inclusion is important. spi.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #if defined(LIBOPENCM3_SPI_H) || defined(LIBOPENCM3_SPI_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_SPI_COMMON_ALL_H #define LIBOPENCM3_SPI_COMMON_ALL_H #include /**@{*/ /* Registers can be accessed as 16bit or 32bit values. */ /* --- Convenience macros -------------------------------------------------- */ /****************************************************************************/ /** @defgroup spi_reg_base SPI Register base address @ingroup spi_defines @{*/ #define SPI1 SPI1_BASE #define SPI2 SPI2_I2S_BASE #define SPI3 SPI3_I2S_BASE /**@}*/ /* --- SPI registers ------------------------------------------------------- */ /* Control register 1 (SPIx_CR1) */ /* Note: Not used in I2S mode. */ #define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) #define SPI1_CR1 SPI_CR1(SPI1_BASE) #define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) #define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) /* Control register 2 (SPIx_CR2) */ #define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) #define SPI1_CR2 SPI_CR2(SPI1_BASE) #define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) #define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) /* Status register (SPIx_SR) */ #define SPI_SR(spi_base) MMIO32(spi_base + 0x08) #define SPI1_SR SPI_SR(SPI1_BASE) #define SPI2_SR SPI_SR(SPI2_I2S_BASE) #define SPI3_SR SPI_SR(SPI3_I2S_BASE) /* Data register (SPIx_DR) */ #define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) #define SPI1_DR SPI_DR(SPI1_BASE) #define SPI2_DR SPI_DR(SPI2_I2S_BASE) #define SPI3_DR SPI_DR(SPI3_I2S_BASE) /* CRC polynomial register (SPIx_CRCPR) */ /* Note: Not used in I2S mode. */ #define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) #define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) #define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) #define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) /* RX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ #define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) #define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) #define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) #define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) /* TX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ #define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) #define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) #define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) #define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) /* I2S configuration register (SPIx_I2SCFGR) */ #define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) #define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) #define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) #define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) /* I2S prescaler register (SPIx_I2SPR) */ #define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) #define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) #define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) #define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) /* --- SPI_CR1 values ------------------------------------------------------ */ /* Note: None of the CR1 bits are used in I2S mode. */ /* BIDIMODE: Bidirectional data mode enable */ #define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) #define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) #define SPI_CR1_BIDIMODE (1 << 15) /* BIDIOE: Output enable in bidirectional mode */ #define SPI_CR1_BIDIOE (1 << 14) /* CRCEN: Hardware CRC calculation enable */ #define SPI_CR1_CRCEN (1 << 13) /* CRCNEXT: Transmit CRC next */ #define SPI_CR1_CRCNEXT (1 << 12) /* RXONLY: Receive only */ #define SPI_CR1_RXONLY (1 << 10) /* SSM: Software slave management */ #define SPI_CR1_SSM (1 << 9) /* SSI: Internal slave select */ #define SPI_CR1_SSI (1 << 8) /* LSBFIRST: Frame format */ /****************************************************************************/ /** @defgroup spi_lsbfirst SPI lsb/msb first @ingroup spi_defines @{*/ #define SPI_CR1_MSBFIRST (0 << 7) #define SPI_CR1_LSBFIRST (1 << 7) /**@}*/ /* SPE: SPI enable */ #define SPI_CR1_SPE (1 << 6) /* BR[2:0]: Baud rate control */ /****************************************************************************/ /** @defgroup spi_baudrate SPI peripheral baud rates @ingroup spi_defines @{*/ #define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) /**@}*/ /****************************************************************************/ /** @defgroup spi_br_pre SPI peripheral baud rate prescale values @ingroup spi_defines @{*/ #define SPI_CR1_BR_FPCLK_DIV_2 0x0 #define SPI_CR1_BR_FPCLK_DIV_4 0x1 #define SPI_CR1_BR_FPCLK_DIV_8 0x2 #define SPI_CR1_BR_FPCLK_DIV_16 0x3 #define SPI_CR1_BR_FPCLK_DIV_32 0x4 #define SPI_CR1_BR_FPCLK_DIV_64 0x5 #define SPI_CR1_BR_FPCLK_DIV_128 0x6 #define SPI_CR1_BR_FPCLK_DIV_256 0x7 /**@}*/ /* MSTR: Master selection */ #define SPI_CR1_MSTR (1 << 2) /* CPOL: Clock polarity */ /****************************************************************************/ /** @defgroup spi_cpol SPI clock polarity @ingroup spi_defines @{*/ #define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) #define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) /**@}*/ #define SPI_CR1_CPOL (1 << 1) /* CPHA: Clock phase */ /****************************************************************************/ /** @defgroup spi_cpha SPI clock phase @ingroup spi_defines @{*/ #define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) #define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) /**@}*/ #define SPI_CR1_CPHA (1 << 0) /* --- SPI_CR2 values ------------------------------------------------------ */ /* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ /* TXEIE: Tx buffer empty interrupt enable */ #define SPI_CR2_TXEIE (1 << 7) /* RXNEIE: Rx buffer not empty interrupt enable */ #define SPI_CR2_RXNEIE (1 << 6) /* ERRIE: Error interrupt enable */ #define SPI_CR2_ERRIE (1 << 5) /* Bits [4:3]: Reserved. Forced to 0 by hardware. */ /* SSOE: SS output enable */ /* Note: Not used in I2S mode. */ #define SPI_CR2_SSOE (1 << 2) /* TXDMAEN: Tx buffer DMA enable */ #define SPI_CR2_TXDMAEN (1 << 1) /* RXDMAEN: Rx buffer DMA enable */ #define SPI_CR2_RXDMAEN (1 << 0) /* --- SPI_SR values ------------------------------------------------------- */ /* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ /* BSY: Busy flag */ #define SPI_SR_BSY (1 << 7) /* OVR: Overrun flag */ #define SPI_SR_OVR (1 << 6) /* MODF: Mode fault */ /* Note: Not used in I2S mode. */ #define SPI_SR_MODF (1 << 5) /* CRCERR: CRC error flag */ /* Note: Not used in I2S mode. */ #define SPI_SR_CRCERR (1 << 4) /* UDR: Underrun flag */ /* Note: Not used in SPI mode. */ #define SPI_SR_UDR (1 << 3) /* CHSIDE: Channel side */ /* Note: Not used in SPI mode. No meaning in PCM mode. */ #define SPI_SR_CHSIDE (1 << 2) /* TXE: Transmit buffer empty */ #define SPI_SR_TXE (1 << 1) /* RXNE: Receive buffer not empty */ #define SPI_SR_RXNE (1 << 0) /* --- SPI_DR values ------------------------------------------------------- */ /* SPI_DR[15:0]: Data Register. */ /* --- SPI_CRCPR values ---------------------------------------------------- */ /* Note: Not used in I2S mode. */ /* SPI_CRCPR [15:0]: CRC Polynomial Register. */ /* --- SPI_RXCRCR values --------------------------------------------------- */ /* Note: Not used in I2S mode. */ /* SPI_RXCRCR [15:0]: RX CRC Register. */ /* --- SPI_TXCRCR values --------------------------------------------------- */ /* Note: Not used in I2S mode. */ /* SPI_TXCRCR [15:0]: TX CRC Register. */ /* --- SPI_I2SCFGR values -------------------------------------------------- */ /* Note: None of these bits are used in SPI mode. */ /* Bits [15:12]: Reserved. Forced to 0 by hardware. */ /* I2SMOD: I2S mode selection */ #define SPI_I2SCFGR_I2SMOD (1 << 11) /* I2SE: I2S enable */ #define SPI_I2SCFGR_I2SE (1 << 10) /* I2SCFG[9:8]: I2S configuration mode */ #define SPI_I2SCFGR_I2SCFG_LSB 8 #define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 #define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 #define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 #define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 /* PCMSYNC: PCM frame synchronization */ #define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 6: Reserved. Forced to 0 by hardware. */ /* I2SSTD[5:4]: I2S standard selection */ #define SPI_I2SCFGR_I2SSTD_LSB 4 #define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 #define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 #define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 #define SPI_I2SCFGR_I2SSTD_PCM 0x3 /* CKPOL: Steady state clock polarity */ #define SPI_I2SCFGR_CKPOL (1 << 3) /* DATLEN[2:1]: Data length to be transferred */ #define SPI_I2SCFGR_DATLEN_LSB 1 #define SPI_I2SCFGR_DATLEN_16BIT 0x0 #define SPI_I2SCFGR_DATLEN_24BIT 0x1 #define SPI_I2SCFGR_DATLEN_32BIT 0x2 /* CHLEN: Channel length */ #define SPI_I2SCFGR_CHLEN (1 << 0) /* --- SPI_I2SPR values ---------------------------------------------------- */ /* Note: None of these bits are used in SPI mode. */ /* Bits [15:10]: Reserved. Forced to 0 by hardware. */ /* MCKOE: Master clock output enable */ #define SPI_I2SPR_MCKOE (1 << 9) /* ODD: Odd factor for the prescaler */ #define SPI_I2SPR_ODD (1 << 8) /* I2SDIV[7:0]: I2S linear prescaler */ /* 0 and 1 are forbidden values */ /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void spi_reset(uint32_t spi_peripheral); int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst); void spi_enable(uint32_t spi); void spi_disable(uint32_t spi); uint16_t spi_clean_disable(uint32_t spi); void spi_write(uint32_t spi, uint16_t data); void spi_send(uint32_t spi, uint16_t data); uint16_t spi_read(uint32_t spi); uint16_t spi_xfer(uint32_t spi, uint16_t data); void spi_set_bidirectional_mode(uint32_t spi); void spi_set_unidirectional_mode(uint32_t spi); void spi_set_bidirectional_receive_only_mode(uint32_t spi); void spi_set_bidirectional_transmit_only_mode(uint32_t spi); void spi_enable_crc(uint32_t spi); void spi_disable_crc(uint32_t spi); void spi_set_next_tx_from_buffer(uint32_t spi); void spi_set_next_tx_from_crc(uint32_t spi); void spi_set_dff_8bit(uint32_t spi); void spi_set_dff_16bit(uint32_t spi); void spi_set_full_duplex_mode(uint32_t spi); void spi_set_receive_only_mode(uint32_t spi); void spi_disable_software_slave_management(uint32_t spi); void spi_enable_software_slave_management(uint32_t spi); void spi_set_nss_high(uint32_t spi); void spi_set_nss_low(uint32_t spi); void spi_send_lsb_first(uint32_t spi); void spi_send_msb_first(uint32_t spi); void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate); void spi_set_master_mode(uint32_t spi); void spi_set_slave_mode(uint32_t spi); void spi_set_clock_polarity_1(uint32_t spi); void spi_set_clock_polarity_0(uint32_t spi); void spi_set_clock_phase_1(uint32_t spi); void spi_set_clock_phase_0(uint32_t spi); void spi_enable_tx_buffer_empty_interrupt(uint32_t spi); void spi_disable_tx_buffer_empty_interrupt(uint32_t spi); void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi); void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi); void spi_enable_error_interrupt(uint32_t spi); void spi_disable_error_interrupt(uint32_t spi); void spi_enable_ss_output(uint32_t spi); void spi_disable_ss_output(uint32_t spi); void spi_enable_tx_dma(uint32_t spi); void spi_disable_tx_dma(uint32_t spi); void spi_enable_rx_dma(uint32_t spi); void spi_disable_rx_dma(uint32_t spi); END_DECLS /**@}*/ #endif /** @cond */ #else #warning "spi_common_all.h should not be included explicitly, only via spi.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/spi_common_f124.h000066400000000000000000000035211435536612600264600ustar00rootroot00000000000000/** @addtogroup spi_defines @author @htmlonly © @endhtmlonly 2011 Fergus Noble */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H The order of header inclusion is important. spi.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_SPI_H /** @endcond */ #ifndef LIBOPENCM3_SPI_COMMON_F0124_H #define LIBOPENCM3_SPI_COMMON_F0124_H /**@{*/ #include /* * This file extends the common STM32 version with definitions only * applicable to the STM32F0/1/2/4 series of devices. */ /* DFF: Data frame format */ /****************************************************************************/ /** @defgroup spi_dff SPI data frame format @ingroup spi_defines @{*/ #define SPI_CR1_DFF_8BIT (0 << 11) #define SPI_CR1_DFF_16BIT (1 << 11) /**@}*/ #define SPI_CR1_DFF (1 << 11) #endif /** @cond */ #else #warning "spi_common_f24.h should not be included explicitly, only via spi.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/spi_common_f24.h000066400000000000000000000036441435536612600264050ustar00rootroot00000000000000/** @addtogroup spi_defines @author @htmlonly © @endhtmlonly 2011 Fergus Noble */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H The order of header inclusion is important. spi.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_SPI_H /** @endcond */ #ifndef LIBOPENCM3_SPI_COMMON_F24_H #define LIBOPENCM3_SPI_COMMON_F24_H /**@{*/ #include /* * This file extends the common STM32 version with definitions only * applicable to the STM32F2/4 series of devices. */ /* --- SPI_CR2 values ------------------------------------------------------ */ /* FRF: Frame format */ /* Note: Not used in I2S mode. */ #define SPI_CR2_FRF (1 << 4) #define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) #define SPI_CR2_FRF_TI_MODE (1 << 4) /* --- SPI_SR values ------------------------------------------------------- */ /* TIFRFE: TI frame format error */ #define SPI_SR_TIFRFE (1 << 8) #endif /** @cond */ #else #warning "spi_common_f24.h should not be included explicitly, only via spi.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/syscfg_common_l1f234.h000066400000000000000000000035131435536612600274230ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H The order of header inclusion is important. spi.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #if defined(LIBOPENCM3_SYSCFG_H) /** @endcond */ #ifndef LIBOPENCM3_SYSCFG_COMMON_L1F234_H #define LIBOPENCM3_SYSCFG_COMMON_L1F234_H #include /* --- SYSCFG registers ---------------------------------------------------- */ #define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) #define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) /* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */ #define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) #define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) #define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) #define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) #define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) #define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) #endif /** @cond */ #else #warning "syscfg_common_l1f234.h should not be included explicitly," #warning "only via syscfg.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/timer_common_all.h000066400000000000000000001121531435536612600271030ustar00rootroot00000000000000/** @addtogroup timer_defines @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H The order of header inclusion is important. timer.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #if defined(LIBOPENCM3_TIMER_H) || defined(LIBOPENCM3_TIMER_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_TIMER_COMMON_H #define LIBOPENCM3_TIMER_COMMON_H #include #include /* --- Convenience macros -------------------------------------------------- */ /* Timer register base addresses (for convenience) */ /****************************************************************************/ /** @defgroup tim_reg_base Timer register base addresses @ingroup timer_defines @{*/ #define TIM1 TIM1_BASE #define TIM2 TIM2_BASE #define TIM3 TIM3_BASE #define TIM4 TIM4_BASE #define TIM5 TIM5_BASE #define TIM6 TIM6_BASE #define TIM7 TIM7_BASE #define TIM8 TIM8_BASE /**@}*/ /* --- Timer registers ----------------------------------------------------- */ /* Control register 1 (TIMx_CR1) */ #define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) #define TIM1_CR1 TIM_CR1(TIM1) #define TIM2_CR1 TIM_CR1(TIM2) #define TIM3_CR1 TIM_CR1(TIM3) #define TIM4_CR1 TIM_CR1(TIM4) #define TIM5_CR1 TIM_CR1(TIM5) #define TIM6_CR1 TIM_CR1(TIM6) #define TIM7_CR1 TIM_CR1(TIM7) #define TIM8_CR1 TIM_CR1(TIM8) /* Control register 2 (TIMx_CR2) */ #define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) #define TIM1_CR2 TIM_CR2(TIM1) #define TIM2_CR2 TIM_CR2(TIM2) #define TIM3_CR2 TIM_CR2(TIM3) #define TIM4_CR2 TIM_CR2(TIM4) #define TIM5_CR2 TIM_CR2(TIM5) #define TIM6_CR2 TIM_CR2(TIM6) #define TIM7_CR2 TIM_CR2(TIM7) #define TIM8_CR2 TIM_CR2(TIM8) /* Slave mode control register (TIMx_SMCR) */ #define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) #define TIM1_SMCR TIM_SMCR(TIM1) #define TIM2_SMCR TIM_SMCR(TIM2) #define TIM3_SMCR TIM_SMCR(TIM3) #define TIM4_SMCR TIM_SMCR(TIM4) #define TIM5_SMCR TIM_SMCR(TIM5) #define TIM8_SMCR TIM_SMCR(TIM8) /* DMA/Interrupt enable register (TIMx_DIER) */ #define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) #define TIM1_DIER TIM_DIER(TIM1) #define TIM2_DIER TIM_DIER(TIM2) #define TIM3_DIER TIM_DIER(TIM3) #define TIM4_DIER TIM_DIER(TIM4) #define TIM5_DIER TIM_DIER(TIM5) #define TIM6_DIER TIM_DIER(TIM6) #define TIM7_DIER TIM_DIER(TIM7) #define TIM8_DIER TIM_DIER(TIM8) /* Status register (TIMx_SR) */ #define TIM_SR(tim_base) MMIO32(tim_base + 0x10) #define TIM1_SR TIM_SR(TIM1) #define TIM2_SR TIM_SR(TIM2) #define TIM3_SR TIM_SR(TIM3) #define TIM4_SR TIM_SR(TIM4) #define TIM5_SR TIM_SR(TIM5) #define TIM6_SR TIM_SR(TIM6) #define TIM7_SR TIM_SR(TIM7) #define TIM8_SR TIM_SR(TIM8) /* Event generation register (TIMx_EGR) */ #define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) #define TIM1_EGR TIM_EGR(TIM1) #define TIM2_EGR TIM_EGR(TIM2) #define TIM3_EGR TIM_EGR(TIM3) #define TIM4_EGR TIM_EGR(TIM4) #define TIM5_EGR TIM_EGR(TIM5) #define TIM6_EGR TIM_EGR(TIM6) #define TIM7_EGR TIM_EGR(TIM7) #define TIM8_EGR TIM_EGR(TIM8) /* Capture/compare mode register 1 (TIMx_CCMR1) */ #define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) #define TIM1_CCMR1 TIM_CCMR1(TIM1) #define TIM2_CCMR1 TIM_CCMR1(TIM2) #define TIM3_CCMR1 TIM_CCMR1(TIM3) #define TIM4_CCMR1 TIM_CCMR1(TIM4) #define TIM5_CCMR1 TIM_CCMR1(TIM5) #define TIM8_CCMR1 TIM_CCMR1(TIM8) /* Capture/compare mode register 2 (TIMx_CCMR2) */ #define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) #define TIM1_CCMR2 TIM_CCMR2(TIM1) #define TIM2_CCMR2 TIM_CCMR2(TIM2) #define TIM3_CCMR2 TIM_CCMR2(TIM3) #define TIM4_CCMR2 TIM_CCMR2(TIM4) #define TIM5_CCMR2 TIM_CCMR2(TIM5) #define TIM8_CCMR2 TIM_CCMR2(TIM8) /* Capture/compare enable register (TIMx_CCER) */ #define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) #define TIM1_CCER TIM_CCER(TIM1) #define TIM2_CCER TIM_CCER(TIM2) #define TIM3_CCER TIM_CCER(TIM3) #define TIM4_CCER TIM_CCER(TIM4) #define TIM5_CCER TIM_CCER(TIM5) #define TIM8_CCER TIM_CCER(TIM8) /* Counter (TIMx_CNT) */ #define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) #define TIM1_CNT TIM_CNT(TIM1) #define TIM2_CNT TIM_CNT(TIM2) #define TIM3_CNT TIM_CNT(TIM3) #define TIM4_CNT TIM_CNT(TIM4) #define TIM5_CNT TIM_CNT(TIM5) #define TIM6_CNT TIM_CNT(TIM6) #define TIM7_CNT TIM_CNT(TIM7) #define TIM8_CNT TIM_CNT(TIM8) /* Prescaler (TIMx_PSC) */ #define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) #define TIM1_PSC TIM_PSC(TIM1) #define TIM2_PSC TIM_PSC(TIM2) #define TIM3_PSC TIM_PSC(TIM3) #define TIM4_PSC TIM_PSC(TIM4) #define TIM5_PSC TIM_PSC(TIM5) #define TIM6_PSC TIM_PSC(TIM6) #define TIM7_PSC TIM_PSC(TIM7) #define TIM8_PSC TIM_PSC(TIM8) /* Auto-reload register (TIMx_ARR) */ #define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) #define TIM1_ARR TIM_ARR(TIM1) #define TIM2_ARR TIM_ARR(TIM2) #define TIM3_ARR TIM_ARR(TIM3) #define TIM4_ARR TIM_ARR(TIM4) #define TIM5_ARR TIM_ARR(TIM5) #define TIM6_ARR TIM_ARR(TIM6) #define TIM7_ARR TIM_ARR(TIM7) #define TIM8_ARR TIM_ARR(TIM8) /* Repetition counter register (TIMx_RCR) */ #define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) #define TIM1_RCR TIM_RCR(TIM1) #define TIM8_RCR TIM_RCR(TIM8) /* Capture/compare register 1 (TIMx_CCR1) */ #define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) #define TIM1_CCR1 TIM_CCR1(TIM1) #define TIM2_CCR1 TIM_CCR1(TIM2) #define TIM3_CCR1 TIM_CCR1(TIM3) #define TIM4_CCR1 TIM_CCR1(TIM4) #define TIM5_CCR1 TIM_CCR1(TIM5) #define TIM8_CCR1 TIM_CCR1(TIM8) /* Capture/compare register 2 (TIMx_CCR2) */ #define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) #define TIM1_CCR2 TIM_CCR2(TIM1) #define TIM2_CCR2 TIM_CCR2(TIM2) #define TIM3_CCR2 TIM_CCR2(TIM3) #define TIM4_CCR2 TIM_CCR2(TIM4) #define TIM5_CCR2 TIM_CCR2(TIM5) #define TIM8_CCR2 TIM_CCR2(TIM8) /* Capture/compare register 3 (TIMx_CCR3) */ #define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) #define TIM1_CCR3 TIM_CCR3(TIM1) #define TIM2_CCR3 TIM_CCR3(TIM2) #define TIM3_CCR3 TIM_CCR3(TIM3) #define TIM4_CCR3 TIM_CCR3(TIM4) #define TIM5_CCR3 TIM_CCR3(TIM5) #define TIM8_CCR3 TIM_CCR3(TIM8) /* Capture/compare register 4 (TIMx_CCR4) */ #define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) #define TIM1_CCR4 TIM_CCR4(TIM1) #define TIM2_CCR4 TIM_CCR4(TIM2) #define TIM3_CCR4 TIM_CCR4(TIM3) #define TIM4_CCR4 TIM_CCR4(TIM4) #define TIM5_CCR4 TIM_CCR4(TIM5) #define TIM8_CCR4 TIM_CCR4(TIM8) /* Break and dead-time register (TIMx_BDTR) */ #define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) #define TIM1_BDTR TIM_BDTR(TIM1) #define TIM8_BDTR TIM_BDTR(TIM8) /* DMA control register (TIMx_DCR) */ #define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) #define TIM1_DCR TIM_DCR(TIM1) #define TIM2_DCR TIM_DCR(TIM2) #define TIM3_DCR TIM_DCR(TIM3) #define TIM4_DCR TIM_DCR(TIM4) #define TIM5_DCR TIM_DCR(TIM5) #define TIM8_DCR TIM_DCR(TIM8) /* DMA address for full transfer (TIMx_DMAR) */ #define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) #define TIM1_DMAR TIM_DMAR(TIM1) #define TIM2_DMAR TIM_DMAR(TIM2) #define TIM3_DMAR TIM_DMAR(TIM3) #define TIM4_DMAR TIM_DMAR(TIM4) #define TIM5_DMAR TIM_DMAR(TIM5) #define TIM8_DMAR TIM_DMAR(TIM8) /* --- TIMx_CR1 values ----------------------------------------------------- */ /****************************************************************************/ /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio @ingroup timer_defines @{*/ /* CKD[1:0]: Clock division */ #define TIM_CR1_CKD_CK_INT (0x0 << 8) #define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) #define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) #define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) /**@}*/ /* ARPE: Auto-reload preload enable */ #define TIM_CR1_ARPE (1 << 7) /* CMS[1:0]: Center-aligned mode selection */ /****************************************************************************/ /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection @ingroup timer_defines @{*/ #define TIM_CR1_CMS_EDGE (0x0 << 5) #define TIM_CR1_CMS_CENTER_1 (0x1 << 5) #define TIM_CR1_CMS_CENTER_2 (0x2 << 5) #define TIM_CR1_CMS_CENTER_3 (0x3 << 5) #define TIM_CR1_CMS_MASK (0x3 << 5) /**@}*/ /* DIR: Direction */ /****************************************************************************/ /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction @ingroup timer_defines @{*/ #define TIM_CR1_DIR_UP (0 << 4) #define TIM_CR1_DIR_DOWN (1 << 4) /**@}*/ /* OPM: One pulse mode */ #define TIM_CR1_OPM (1 << 3) /* URS: Update request source */ #define TIM_CR1_URS (1 << 2) /* UDIS: Update disable */ #define TIM_CR1_UDIS (1 << 1) /* CEN: Counter enable */ #define TIM_CR1_CEN (1 << 0) /* --- TIMx_CR2 values ----------------------------------------------------- */ /****************************************************************************/ /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values @ingroup timer_defines @{*/ /* OIS4:*//** Output idle state 4 (OC4 output) */ #define TIM_CR2_OIS4 (1 << 14) /* OIS3N:*//** Output idle state 3 (OC3N output) */ #define TIM_CR2_OIS3N (1 << 13) /* OIS3:*//** Output idle state 3 (OC3 output) */ #define TIM_CR2_OIS3 (1 << 12) /* OIS2N:*//** Output idle state 2 (OC2N output) */ #define TIM_CR2_OIS2N (1 << 11) /* OIS2:*//** Output idle state 2 (OC2 output) */ #define TIM_CR2_OIS2 (1 << 10) /* OIS1N:*//** Output idle state 1 (OC1N output) */ #define TIM_CR2_OIS1N (1 << 9) /* OIS1:*//** Output idle state 1 (OC1 output) */ #define TIM_CR2_OIS1 (1 << 8) #define TIM_CR2_OIS_MASK (0x7f << 8) /**@}*/ /* TI1S: TI1 selection */ #define TIM_CR2_TI1S (1 << 7) /* MMS[2:0]: Master mode selection */ /****************************************************************************/ /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection @ingroup timer_defines @{*/ #define TIM_CR2_MMS_RESET (0x0 << 4) #define TIM_CR2_MMS_ENABLE (0x1 << 4) #define TIM_CR2_MMS_UPDATE (0x2 << 4) #define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) #define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) #define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) #define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) #define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) #define TIM_CR2_MMS_MASK (0x7 << 4) /**@}*/ /* CCDS: Capture/compare DMA selection */ #define TIM_CR2_CCDS (1 << 3) /* CCUS: Capture/compare control update selection */ #define TIM_CR2_CCUS (1 << 2) /* CCPC: Capture/compare preload control */ #define TIM_CR2_CCPC (1 << 0) /* --- TIMx_SMCR values ---------------------------------------------------- */ /* ETP: External trigger polarity */ #define TIM_SMCR_ETP (1 << 15) /* ECE: External clock enable */ #define TIM_SMCR_ECE (1 << 14) /* ETPS[1:0]: External trigger prescaler */ #define TIM_SMCR_ETPS_OFF (0x0 << 12) #define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) #define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) #define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) #define TIM_SMCR_ETPS_MASK (0X3 << 12) /* ETF[3:0]: External trigger filter */ #define TIM_SMCR_ETF_OFF (0x0 << 8) #define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) #define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) #define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) #define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) #define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) #define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) #define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) #define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) #define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) #define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) #define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) #define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) #define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) #define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) #define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) #define TIM_SMCR_ETF_MASK (0xF << 8) /* MSM: Master/slave mode */ #define TIM_SMCR_MSM (1 << 7) /* TS[2:0]: Trigger selection */ /** @defgroup tim_ts TS Trigger selection @ingroup timer_defines @{*/ /** Internal Trigger 0 (ITR0) */ #define TIM_SMCR_TS_ITR0 (0x0 << 4) /** Internal Trigger 1 (ITR1) */ #define TIM_SMCR_TS_ITR1 (0x1 << 4) /** Internal Trigger 2 (ITR2) */ #define TIM_SMCR_TS_ITR2 (0x2 << 4) /** Internal Trigger 3 (ITR3) */ #define TIM_SMCR_TS_ITR3 (0x3 << 4) /** TI1 Edge Detector (TI1F_ED) */ #define TIM_SMCR_TS_IT1F_ED (0x4 << 4) /** Filtered Timer Input 1 (TI1FP1) */ #define TIM_SMCR_TS_IT1FP1 (0x5 << 4) /** Filtered Timer Input 2 (TI1FP2) */ #define TIM_SMCR_TS_IT1FP2 (0x6 << 4) /** External Trigger input (ETRF) */ #define TIM_SMCR_TS_ETRF (0x7 << 4) #define TIM_SMCR_TS_MASK (0x7 << 4) /**@}*/ /* SMS[2:0]: Slave mode selection */ /** @defgroup tim_sms SMS Slave mode selection @ingroup timer_defines @{*/ /** Slave mode disabled */ #define TIM_SMCR_SMS_OFF (0x0 << 0) /** Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. */ #define TIM_SMCR_SMS_EM1 (0x1 << 0) /** Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. */ #define TIM_SMCR_SMS_EM2 (0x2 << 0) /** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the complementary input. */ #define TIM_SMCR_SMS_EM3 (0x3 << 0) /** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes * the counter and generates an update of the registers. */ #define TIM_SMCR_SMS_RM (0x4 << 0) /** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is * high. */ #define TIM_SMCR_SMS_GM (0x5 << 0) /** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */ #define TIM_SMCR_SMS_TM (0x6 << 0) /** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock * the counter. */ #define TIM_SMCR_SMS_ECM1 (0x7 << 0) #define TIM_SMCR_SMS_MASK (0x7 << 0) /**@}*/ /* --- TIMx_DIER values ---------------------------------------------------- */ /****************************************************************************/ /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values @ingroup timer_defines @{*/ /* TDE:*//** Trigger DMA request enable */ #define TIM_DIER_TDE (1 << 14) /* COMDE:*//** COM DMA request enable */ #define TIM_DIER_COMDE (1 << 13) /* CC4DE:*//** Capture/Compare 4 DMA request enable */ #define TIM_DIER_CC4DE (1 << 12) /* CC3DE:*//** Capture/Compare 3 DMA request enable */ #define TIM_DIER_CC3DE (1 << 11) /* CC2DE:*//** Capture/Compare 2 DMA request enable */ #define TIM_DIER_CC2DE (1 << 10) /* CC1DE:*//** Capture/Compare 1 DMA request enable */ #define TIM_DIER_CC1DE (1 << 9) /* UDE*//**: Update DMA request enable */ #define TIM_DIER_UDE (1 << 8) /* BIE:*//** Break interrupt enable */ #define TIM_DIER_BIE (1 << 7) /* TIE:*//** Trigger interrupt enable */ #define TIM_DIER_TIE (1 << 6) /* COMIE:*//** COM interrupt enable */ #define TIM_DIER_COMIE (1 << 5) /* CC4IE:*//** Capture/compare 4 interrupt enable */ #define TIM_DIER_CC4IE (1 << 4) /* CC3IE:*//** Capture/compare 3 interrupt enable */ #define TIM_DIER_CC3IE (1 << 3) /* CC2IE:*//** Capture/compare 2 interrupt enable */ #define TIM_DIER_CC2IE (1 << 2) /* CC1IE:*//** Capture/compare 1 interrupt enable */ #define TIM_DIER_CC1IE (1 << 1) /* UIE:*//** Update interrupt enable */ #define TIM_DIER_UIE (1 << 0) /**@}*/ /* --- TIMx_SR values ------------------------------------------------------ */ /****************************************************************************/ /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags @ingroup timer_defines @{*/ /* CC4OF:*//** Capture/compare 4 overcapture flag */ #define TIM_SR_CC4OF (1 << 12) /* CC3OF:*//** Capture/compare 3 overcapture flag */ #define TIM_SR_CC3OF (1 << 11) /* CC2OF:*//** Capture/compare 2 overcapture flag */ #define TIM_SR_CC2OF (1 << 10) /* CC1OF:*//** Capture/compare 1 overcapture flag */ #define TIM_SR_CC1OF (1 << 9) /* BIF:*//** Break interrupt flag */ #define TIM_SR_BIF (1 << 7) /* TIF:*//** Trigger interrupt flag */ #define TIM_SR_TIF (1 << 6) /* COMIF:*//** COM interrupt flag */ #define TIM_SR_COMIF (1 << 5) /* CC4IF:*//** Capture/compare 4 interrupt flag */ #define TIM_SR_CC4IF (1 << 4) /* CC3IF:*//** Capture/compare 3 interrupt flag */ #define TIM_SR_CC3IF (1 << 3) /* CC2IF:*//** Capture/compare 2 interrupt flag */ #define TIM_SR_CC2IF (1 << 2) /* CC1IF:*//** Capture/compare 1 interrupt flag */ #define TIM_SR_CC1IF (1 << 1) /* UIF:*//** Update interrupt flag */ #define TIM_SR_UIF (1 << 0) /**@}*/ /* --- TIMx_EGR values ----------------------------------------------------- */ /****************************************************************************/ /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values @ingroup timer_defines @{*/ /* BG:*//** Break generation */ #define TIM_EGR_BG (1 << 7) /* TG:*//** Trigger generation */ #define TIM_EGR_TG (1 << 6) /* COMG:*//** Capture/compare control update generation */ #define TIM_EGR_COMG (1 << 5) /* CC4G:*//** Capture/compare 4 generation */ #define TIM_EGR_CC4G (1 << 4) /* CC3G:*//** Capture/compare 3 generation */ #define TIM_EGR_CC3G (1 << 3) /* CC2G:*//** Capture/compare 2 generation */ #define TIM_EGR_CC2G (1 << 2) /* CC1G:*//** Capture/compare 1 generation */ #define TIM_EGR_CC1G (1 << 1) /* UG:*//** Update generation */ #define TIM_EGR_UG (1 << 0) /**@}*/ /* --- TIMx_CCMR1 values --------------------------------------------------- */ /* --- Output compare mode --- */ /* OC2CE: Output compare 2 clear enable */ #define TIM_CCMR1_OC2CE (1 << 15) /* OC2M[2:0]: Output compare 2 mode */ #define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) #define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) #define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) #define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) #define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) #define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) #define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) #define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) #define TIM_CCMR1_OC2M_MASK (0x7 << 12) /* OC2PE: Output compare 2 preload enable */ #define TIM_CCMR1_OC2PE (1 << 11) /* OC2FE: Output compare 2 fast enable */ #define TIM_CCMR1_OC2FE (1 << 10) /* CC2S[1:0]: Capture/compare 2 selection */ /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in * TIMx_CCER). */ #define TIM_CCMR1_CC2S_OUT (0x0 << 8) #define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) #define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) #define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) #define TIM_CCMR1_CC2S_MASK (0x3 << 8) /* OC1CE: Output compare 1 clear enable */ #define TIM_CCMR1_OC1CE (1 << 7) /* OC1M[2:0]: Output compare 1 mode */ #define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) #define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) #define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) #define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) #define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) #define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) #define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) #define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) #define TIM_CCMR1_OC1M_MASK (0x7 << 4) /* OC1PE: Output compare 1 preload enable */ #define TIM_CCMR1_OC1PE (1 << 3) /* OC1FE: Output compare 1 fast enable */ #define TIM_CCMR1_OC1FE (1 << 2) /* CC1S[1:0]: Capture/compare 1 selection */ /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in * TIMx_CCER). */ #define TIM_CCMR1_CC1S_OUT (0x0 << 0) #define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0) #define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0) #define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) #define TIM_CCMR1_CC1S_MASK (0x3 << 0) /* --- Input capture mode --- */ /* IC2F[3:0]: Input capture 2 filter */ #define TIM_CCMR1_IC2F_OFF (0x0 << 12) #define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) #define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) #define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) #define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) #define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) #define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) #define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) #define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) #define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) #define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) #define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) #define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) #define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) #define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) #define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) #define TIM_CCMR1_IC2F_MASK (0xF << 12) /* IC2PSC[1:0]: Input capture 2 prescaler */ #define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) #define TIM_CCMR1_IC2PSC_2 (0x1 << 10) #define TIM_CCMR1_IC2PSC_4 (0x2 << 10) #define TIM_CCMR1_IC2PSC_8 (0x3 << 10) #define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) /* IC1F[3:0]: Input capture 1 filter */ #define TIM_CCMR1_IC1F_OFF (0x0 << 4) #define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) #define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) #define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) #define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) #define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) #define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) #define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) #define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) #define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) #define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) #define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) #define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) #define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) #define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) #define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) #define TIM_CCMR1_IC1F_MASK (0xF << 4) /* IC1PSC[1:0]: Input capture 1 prescaler */ #define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) #define TIM_CCMR1_IC1PSC_2 (0x1 << 2) #define TIM_CCMR1_IC1PSC_4 (0x2 << 2) #define TIM_CCMR1_IC1PSC_8 (0x3 << 2) #define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) /* --- TIMx_CCMR2 values --------------------------------------------------- */ /* --- Output compare mode --- */ /* OC4CE: Output compare 4 clear enable */ #define TIM_CCMR2_OC4CE (1 << 15) /* OC4M[2:0]: Output compare 4 mode */ #define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) #define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) #define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) #define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) #define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) #define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) #define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) #define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) #define TIM_CCMR2_OC4M_MASK (0x7 << 12) /* OC4PE: Output compare 4 preload enable */ #define TIM_CCMR2_OC4PE (1 << 11) /* OC4FE: Output compare 4 fast enable */ #define TIM_CCMR2_OC4FE (1 << 10) /* CC4S[1:0]: Capture/compare 4 selection */ /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in * TIMx_CCER). */ #define TIM_CCMR2_CC4S_OUT (0x0 << 8) #define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) #define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) #define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) #define TIM_CCMR2_CC4S_MASK (0x3 << 8) /* OC3CE: Output compare 3 clear enable */ #define TIM_CCMR2_OC3CE (1 << 7) /* OC3M[2:0]: Output compare 3 mode */ #define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) #define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) #define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) #define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) #define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) #define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) #define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) #define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) #define TIM_CCMR2_OC3M_MASK (0x7 << 4) /* OC3PE: Output compare 3 preload enable */ #define TIM_CCMR2_OC3PE (1 << 3) /* OC3FE: Output compare 3 fast enable */ #define TIM_CCMR2_OC3FE (1 << 2) /* CC3S[1:0]: Capture/compare 3 selection */ /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in * TIMx_CCER). */ #define TIM_CCMR2_CC3S_OUT (0x0 << 0) #define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) #define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) #define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) #define TIM_CCMR2_CC3S_MASK (0x3 << 0) /* --- Input capture mode --- */ /* IC4F[3:0]: Input capture 4 filter */ #define TIM_CCMR2_IC4F_OFF (0x0 << 12) #define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) #define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) #define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) #define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) #define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) #define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) #define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) #define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) #define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) #define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) #define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) #define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) #define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) #define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) #define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) #define TIM_CCMR2_IC4F_MASK (0xF << 12) /* IC4PSC[1:0]: Input capture 4 prescaler */ #define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) #define TIM_CCMR2_IC4PSC_2 (0x1 << 10) #define TIM_CCMR2_IC4PSC_4 (0x2 << 10) #define TIM_CCMR2_IC4PSC_8 (0x3 << 10) #define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) /* IC3F[3:0]: Input capture 3 filter */ #define TIM_CCMR2_IC3F_OFF (0x0 << 4) #define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) #define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) #define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) #define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) #define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) #define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) #define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) #define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) #define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) #define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) #define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) #define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) #define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) #define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) #define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) #define TIM_CCMR2_IC3F_MASK (0xF << 4) /* IC3PSC[1:0]: Input capture 3 prescaler */ #define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) #define TIM_CCMR2_IC3PSC_2 (0x1 << 2) #define TIM_CCMR2_IC3PSC_4 (0x2 << 2) #define TIM_CCMR2_IC3PSC_8 (0x3 << 2) #define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) /* --- TIMx_CCER values ---------------------------------------------------- */ /* CC4P: Capture/compare 4 output polarity */ #define TIM_CCER_CC4P (1 << 13) /* CC4E: Capture/compare 4 output enable */ #define TIM_CCER_CC4E (1 << 12) /* CC3NP: Capture/compare 3 complementary output polarity */ #define TIM_CCER_CC3NP (1 << 11) /* CC3NE: Capture/compare 3 complementary output enable */ #define TIM_CCER_CC3NE (1 << 10) /* CC3P: Capture/compare 3 output polarity */ #define TIM_CCER_CC3P (1 << 9) /* CC3E: Capture/compare 3 output enable */ #define TIM_CCER_CC3E (1 << 8) /* CC2NP: Capture/compare 2 complementary output polarity */ #define TIM_CCER_CC2NP (1 << 7) /* CC2NE: Capture/compare 2 complementary output enable */ #define TIM_CCER_CC2NE (1 << 6) /* CC2P: Capture/compare 2 output polarity */ #define TIM_CCER_CC2P (1 << 5) /* CC2E: Capture/compare 2 output enable */ #define TIM_CCER_CC2E (1 << 4) /* CC1NP: Capture/compare 1 complementary output polarity */ #define TIM_CCER_CC1NP (1 << 3) /* CC1NE: Capture/compare 1 complementary output enable */ #define TIM_CCER_CC1NE (1 << 2) /* CC1P: Capture/compare 1 output polarity */ #define TIM_CCER_CC1P (1 << 1) /* CC1E: Capture/compare 1 output enable */ #define TIM_CCER_CC1E (1 << 0) /* --- TIMx_CNT values ----------------------------------------------------- */ /* CNT[15:0]: Counter value */ /* --- TIMx_PSC values ----------------------------------------------------- */ /* PSC[15:0]: Prescaler value */ /* --- TIMx_ARR values ----------------------------------------------------- */ /* ARR[15:0]: Prescaler value */ /* --- TIMx_RCR values ----------------------------------------------------- */ /* REP[15:0]: Repetition counter value */ /* --- TIMx_CCR1 values ---------------------------------------------------- */ /* CCR1[15:0]: Capture/compare 1 value */ /* --- TIMx_CCR2 values ---------------------------------------------------- */ /* CCR2[15:0]: Capture/compare 2 value */ /* --- TIMx_CCR3 values ---------------------------------------------------- */ /* CCR3[15:0]: Capture/compare 3 value */ /* --- TIMx_CCR4 values ---------------------------------------------------- */ /* CCR4[15:0]: Capture/compare 4 value */ /* --- TIMx_BDTR values ---------------------------------------------------- */ /* MOE: Main output enable */ #define TIM_BDTR_MOE (1 << 15) /* AOE: Automatic output enable */ #define TIM_BDTR_AOE (1 << 14) /* BKP: Break polarity */ #define TIM_BDTR_BKP (1 << 13) /* BKE: Break enable */ #define TIM_BDTR_BKE (1 << 12) /* OSSR: Off-state selection of run mode */ #define TIM_BDTR_OSSR (1 << 11) /* OSSI: Off-state selection of idle mode */ #define TIM_BDTR_OSSI (1 << 10) /* LOCK[1:0]: Lock configuration */ /****************************************************************************/ /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values @ingroup timer_defines @{*/ #define TIM_BDTR_LOCK_OFF (0x0 << 8) #define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) #define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) #define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) #define TIM_BDTR_LOCK_MASK (0x3 << 8) /**@}*/ /* DTG[7:0]: Dead-time generator set-up */ #define TIM_BDTR_DTG_MASK 0x00FF /* --- TIMx_DCR values ----------------------------------------------------- */ /* DBL[4:0]: DMA burst length */ #define TIM_BDTR_DBL_MASK (0x1F << 8) /* DBA[4:0]: DMA base address */ #define TIM_BDTR_DBA_MASK (0x1F << 0) /* --- TIMx_DMAR values ---------------------------------------------------- */ /* DMAB[15:0]: DMA register for burst accesses */ /* --- TIMx convenience defines -------------------------------------------- */ /** Output Compare channel designators */ enum tim_oc_id { TIM_OC1 = 0, TIM_OC1N, TIM_OC2, TIM_OC2N, TIM_OC3, TIM_OC3N, TIM_OC4, }; /** Output Compare mode designators */ enum tim_oc_mode { TIM_OCM_FROZEN, TIM_OCM_ACTIVE, TIM_OCM_INACTIVE, TIM_OCM_TOGGLE, TIM_OCM_FORCE_LOW, TIM_OCM_FORCE_HIGH, TIM_OCM_PWM1, TIM_OCM_PWM2, }; /** Input Capture channel designators */ enum tim_ic_id { TIM_IC1, TIM_IC2, TIM_IC3, TIM_IC4, }; /** Input Capture input filter. The frequency used to sample the input and the number of events needed to validate an output transition. TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency (DTF), filter length x TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x */ enum tim_ic_filter { TIM_IC_OFF, TIM_IC_CK_INT_N_2, TIM_IC_CK_INT_N_4, TIM_IC_CK_INT_N_8, TIM_IC_DTF_DIV_2_N_6, TIM_IC_DTF_DIV_2_N_8, TIM_IC_DTF_DIV_4_N_6, TIM_IC_DTF_DIV_4_N_8, TIM_IC_DTF_DIV_8_N_6, TIM_IC_DTF_DIV_8_N_8, TIM_IC_DTF_DIV_16_N_5, TIM_IC_DTF_DIV_16_N_6, TIM_IC_DTF_DIV_16_N_8, TIM_IC_DTF_DIV_32_N_5, TIM_IC_DTF_DIV_32_N_6, TIM_IC_DTF_DIV_32_N_8, }; /** Input Capture input prescaler. TIM_IC_PSC_x Input capture is done every x events*/ enum tim_ic_psc { TIM_IC_PSC_OFF, TIM_IC_PSC_2, TIM_IC_PSC_4, TIM_IC_PSC_8, }; /** Input Capture input source. The direction of the channel (input/output) as well as the input used. */ enum tim_ic_input { TIM_IC_OUT = 0, TIM_IC_IN_TI1 = 1, TIM_IC_IN_TI2 = 2, TIM_IC_IN_TRC = 3, TIM_IC_IN_TI3 = 5, TIM_IC_IN_TI4 = 6, }; /** Slave external trigger polarity */ enum tim_et_pol { TIM_ET_RISING, TIM_ET_FALLING, }; /* --- TIM function prototypes --------------------------------------------- */ BEGIN_DECLS void timer_reset(uint32_t timer_peripheral); void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq); void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq); bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag); bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag); void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag); void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div, uint32_t alignment, uint32_t direction); void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div); void timer_enable_preload(uint32_t timer_peripheral); void timer_disable_preload(uint32_t timer_peripheral); void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment); void timer_direction_up(uint32_t timer_peripheral); void timer_direction_down(uint32_t timer_peripheral); void timer_one_shot_mode(uint32_t timer_peripheral); void timer_continuous_mode(uint32_t timer_peripheral); void timer_update_on_any(uint32_t timer_peripheral); void timer_update_on_overflow(uint32_t timer_peripheral); void timer_enable_update_event(uint32_t timer_peripheral); void timer_disable_update_event(uint32_t timer_peripheral); void timer_enable_counter(uint32_t timer_peripheral); void timer_disable_counter(uint32_t timer_peripheral); void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); void timer_set_ti1_ch123_xor(uint32_t timer_peripheral); void timer_set_ti1_ch1(uint32_t timer_peripheral); void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode); void timer_set_dma_on_compare_event(uint32_t timer_peripheral); void timer_set_dma_on_update_event(uint32_t timer_peripheral); void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral); void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral); void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral); void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral); void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value); void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value); void timer_set_period(uint32_t timer_peripheral, uint32_t period); void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value); void timer_enable_break_main_output(uint32_t timer_peripheral); void timer_disable_break_main_output(uint32_t timer_peripheral); void timer_enable_break_automatic_output(uint32_t timer_peripheral); void timer_disable_break_automatic_output(uint32_t timer_peripheral); void timer_set_break_polarity_high(uint32_t timer_peripheral); void timer_set_break_polarity_low(uint32_t timer_peripheral); void timer_enable_break(uint32_t timer_peripheral); void timer_disable_break(uint32_t timer_peripheral); void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral); void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral); void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral); void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral); void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock); void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime); void timer_generate_event(uint32_t timer_peripheral, uint32_t event); uint32_t timer_get_counter(uint32_t timer_peripheral); void timer_set_counter(uint32_t timer_peripheral, uint32_t count); void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, enum tim_ic_filter flt); void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, enum tim_ic_psc psc); void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, enum tim_ic_input in); void timer_ic_enable(uint32_t timer, enum tim_ic_id ic); void timer_ic_disable(uint32_t timer, enum tim_ic_id ic); void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt); void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc); void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol); void timer_slave_set_mode(uint32_t timer, uint8_t mode); void timer_slave_set_trigger(uint32_t timer, uint8_t trigger); END_DECLS #endif /** @cond */ #else #warning "timer_common_all.h should not be included directly, only via timer.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/timer_common_f24.h000066400000000000000000000070731435536612600267320ustar00rootroot00000000000000/** @addtogroup timer_defines @author @htmlonly © @endhtmlonly 2011 Fergus Noble */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H The order of header inclusion is important. timer.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_TIMER_H /** @endcond */ #ifndef LIBOPENCM3_TIMER_COMMON_F24_H #define LIBOPENCM3_TIMER_COMMON_F24_H #include /* * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: * CNT, ARR, CCR1, CCR2, CCR3, CCR4 */ /* Timer 2/5 option register (TIMx_OR) */ #define TIM_OR(tim_base) MMIO32(tim_base + 0x50) #define TIM2_OR TIM_OR(TIM2) #define TIM5_OR TIM_OR(TIM5) /* --- TIM2_OR values ---------------------------------------------------- */ /* ITR1_RMP */ /****************************************************************************/ /** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap Only available in F2 and F4 series. @ingroup timer_defines @{*/ /** Internal Trigger 1 remapped to timer 8 trigger out */ #define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10) /** Internal Trigger 1 remapped to PTP trigger out */ #define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) /** Internal Trigger 1 remapped to USB OTG FS SOF */ #define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) /** Internal Trigger 1 remapped to USB OTG HS SOF */ #define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) /**@}*/ #define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) /* --- TIM5_OR values ---------------------------------------------------- */ /* ITR4_RMP */ /****************************************************************************/ /** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap Only available in F2 and F4 series. @ingroup timer_defines @{*/ /** Internal Trigger 4 remapped to GPIO (see reference manual) */ #define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) /** Internal Trigger 4 remapped to LSI internal clock */ #define TIM5_OR_TI4_RMP_LSI (0x1 << 6) /** Internal Trigger 4 remapped to LSE internal clock */ #define TIM5_OR_TI4_RMP_LSE (0x2 << 6) /** Internal Trigger 4 remapped to RTC output event */ #define TIM5_OR_TI4_RMP_RTC (0x3 << 6) /**@}*/ #define TIM5_OR_TI4_RMP_MASK (0x3 << 6) /** Input Capture input polarity */ enum tim_ic_pol { TIM_IC_RISING, TIM_IC_FALLING, TIM_IC_BOTH, }; /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void timer_set_option(uint32_t timer_peripheral, uint32_t option); void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol); END_DECLS #endif /** @cond */ #else #warning "timer_common_f24.h should not be included directly, only via timer.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/usart_common_all.h000066400000000000000000000117731435536612600271270ustar00rootroot00000000000000/** @addtogroup usart_defines @author @htmlonly © @endhtmlonly 2009 Uwe Hermann */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H The order of header inclusion is important. usart.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #if defined(LIBOPENCM3_USART_H) /** @endcond */ #ifndef LIBOPENCM3_USART_COMMON_ALL_H #define LIBOPENCM3_USART_COMMON_ALL_H #include /* --- Convenience macros -------------------------------------------------- */ /****************************************************************************/ /** @defgroup usart_reg_base USART register base addresses @ingroup STM32F_usart_defines @{*/ #define USART1 USART1_BASE #define USART2 USART2_BASE #define USART3 USART3_BASE /**@}*/ #define UART4 UART4_BASE #define UART5 UART5_BASE /* --- Convenience defines ------------------------------------------------- */ /* CR1_PCE / CR1_PS combined values */ /****************************************************************************/ /** @defgroup usart_cr1_parity USART Parity Selection @ingroup STM32F_usart_defines @{*/ #define USART_PARITY_NONE 0x00 #define USART_PARITY_EVEN USART_CR1_PCE #define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) /**@}*/ #define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) /* CR1_TE/CR1_RE combined values */ /****************************************************************************/ /** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection @ingroup STM32F_usart_defines @{*/ #define USART_MODE_RX USART_CR1_RE #define USART_MODE_TX USART_CR1_TE #define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) /**@}*/ #define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) /****************************************************************************/ /** @defgroup usart_cr2_stopbits USART Stop Bit Selection @ingroup STM32F_usart_defines @{*/ #define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ #define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */ #define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ #define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/ /**@}*/ /* CR3_CTSE/CR3_RTSE combined values */ /****************************************************************************/ /** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection @ingroup STM32F_usart_defines @{*/ #define USART_FLOWCONTROL_NONE 0x00 #define USART_FLOWCONTROL_RTS USART_CR3_RTSE #define USART_FLOWCONTROL_CTS USART_CR3_CTSE #define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /**@}*/ #define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void usart_set_baudrate(uint32_t usart, uint32_t baud); void usart_set_databits(uint32_t usart, uint32_t bits); void usart_set_stopbits(uint32_t usart, uint32_t stopbits); void usart_set_parity(uint32_t usart, uint32_t parity); void usart_set_mode(uint32_t usart, uint32_t mode); void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol); void usart_enable(uint32_t usart); void usart_disable(uint32_t usart); void usart_send(uint32_t usart, uint16_t data); uint16_t usart_recv(uint32_t usart); void usart_wait_send_ready(uint32_t usart); void usart_wait_recv_ready(uint32_t usart); void usart_send_blocking(uint32_t usart, uint16_t data); uint16_t usart_recv_blocking(uint32_t usart); void usart_enable_rx_dma(uint32_t usart); void usart_disable_rx_dma(uint32_t usart); void usart_enable_tx_dma(uint32_t usart); void usart_disable_tx_dma(uint32_t usart); void usart_enable_rx_interrupt(uint32_t usart); void usart_disable_rx_interrupt(uint32_t usart); void usart_enable_tx_interrupt(uint32_t usart); void usart_disable_tx_interrupt(uint32_t usart); void usart_enable_error_interrupt(uint32_t usart); void usart_disable_error_interrupt(uint32_t usart); bool usart_get_flag(uint32_t usart, uint32_t flag); bool usart_get_interrupt_source(uint32_t usart, uint32_t flag); END_DECLS #endif /** @cond */ #else #warning "usart_common_all.h should not be included directly, only via usart.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/usart_common_f124.h000066400000000000000000000205231435536612600270240ustar00rootroot00000000000000/** @addtogroup usart_defines @author @htmlonly © @endhtmlonly 2009 Uwe Hermann */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H The order of header inclusion is important. usart.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #if defined(LIBOPENCM3_USART_H) /** @endcond */ #ifndef LIBOPENCM3_USART_COMMON_F124_H #define LIBOPENCM3_USART_COMMON_F124_H #include #include /* --- USART registers ----------------------------------------------------- */ /* Status register (USARTx_SR) */ #define USART_SR(usart_base) MMIO32(usart_base + 0x00) #define USART1_SR USART_SR(USART1_BASE) #define USART2_SR USART_SR(USART2_BASE) #define USART3_SR USART_SR(USART3_BASE) #define UART4_SR USART_SR(UART4_BASE) #define UART5_SR USART_SR(UART5_BASE) /* Data register (USARTx_DR) */ #define USART_DR(usart_base) MMIO32(usart_base + 0x04) #define USART1_DR USART_DR(USART1_BASE) #define USART2_DR USART_DR(USART2_BASE) #define USART3_DR USART_DR(USART3_BASE) #define UART4_DR USART_DR(UART4_BASE) #define UART5_DR USART_DR(UART5_BASE) /* Baud rate register (USARTx_BRR) */ #define USART_BRR(usart_base) MMIO32(usart_base + 0x08) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) #define UART4_BRR USART_BRR(UART4_BASE) #define UART5_BRR USART_BRR(UART5_BASE) /* Control register 1 (USARTx_CR1) */ #define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) #define UART4_CR1 USART_CR1(UART4_BASE) #define UART5_CR1 USART_CR1(UART5_BASE) /* Control register 2 (USARTx_CR2) */ #define USART_CR2(usart_base) MMIO32(usart_base + 0x10) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) #define UART4_CR2 USART_CR2(UART4_BASE) #define UART5_CR2 USART_CR2(UART5_BASE) /* Control register 3 (USARTx_CR3) */ #define USART_CR3(usart_base) MMIO32(usart_base + 0x14) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) #define UART4_CR3 USART_CR3(UART4_BASE) #define UART5_CR3 USART_CR3(UART5_BASE) /* Guard time and prescaler register (USARTx_GTPR) */ #define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) #define UART4_GTPR USART_GTPR(UART4_BASE) #define UART5_GTPR USART_GTPR(UART5_BASE) /* --- USART_SR values ----------------------------------------------------- */ /****************************************************************************/ /** @defgroup usart_sr_flags USART Status register Flags @ingroup STM32F_usart_defines @{*/ /** CTS: CTS flag */ /** @note: undefined on UART4 and UART5 */ #define USART_SR_CTS (1 << 9) /** LBD: LIN break detection flag */ #define USART_SR_LBD (1 << 8) /** TXE: Transmit data buffer empty */ #define USART_SR_TXE (1 << 7) /** TC: Transmission complete */ #define USART_SR_TC (1 << 6) /** RXNE: Read data register not empty */ #define USART_SR_RXNE (1 << 5) /** IDLE: Idle line detected */ #define USART_SR_IDLE (1 << 4) /** ORE: Overrun error */ #define USART_SR_ORE (1 << 3) /** NE: Noise error flag */ #define USART_SR_NE (1 << 2) /** FE: Framing error */ #define USART_SR_FE (1 << 1) /** PE: Parity error */ #define USART_SR_PE (1 << 0) /**@}*/ /* --- USART_DR values ----------------------------------------------------- */ /* USART_DR[8:0]: DR[8:0]: Data value */ #define USART_DR_MASK 0x1FF /* --- USART_BRR values ---------------------------------------------------- */ /* DIV_Mantissa[11:0]: mantissa of USARTDIV */ #define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) /* DIV_Fraction[3:0]: fraction of USARTDIV */ #define USART_BRR_DIV_FRACTION_MASK 0xF /* --- USART_CR1 values ---------------------------------------------------- */ /* UE: USART enable */ #define USART_CR1_UE (1 << 13) /* M: Word length */ #define USART_CR1_M (1 << 12) /* WAKE: Wakeup method */ #define USART_CR1_WAKE (1 << 11) /* PCE: Parity control enable */ #define USART_CR1_PCE (1 << 10) /* PS: Parity selection */ #define USART_CR1_PS (1 << 9) /* PEIE: PE interrupt enable */ #define USART_CR1_PEIE (1 << 8) /* TXEIE: TXE interrupt enable */ #define USART_CR1_TXEIE (1 << 7) /* TCIE: Transmission complete interrupt enable */ #define USART_CR1_TCIE (1 << 6) /* RXNEIE: RXNE interrupt enable */ #define USART_CR1_RXNEIE (1 << 5) /* IDLEIE: IDLE interrupt enable */ #define USART_CR1_IDLEIE (1 << 4) /* TE: Transmitter enable */ #define USART_CR1_TE (1 << 3) /* RE: Receiver enable */ #define USART_CR1_RE (1 << 2) /* RWU: Receiver wakeup */ #define USART_CR1_RWU (1 << 1) /* SBK: Send break */ #define USART_CR1_SBK (1 << 0) /* --- USART_CR2 values ---------------------------------------------------- */ /* LINEN: LIN mode enable */ #define USART_CR2_LINEN (1 << 14) /* STOP[13:12]: STOP bits */ #define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ #define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ #define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ #define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ #define USART_CR2_STOPBITS_MASK (0x03 << 12) #define USART_CR2_STOPBITS_SHIFT 12 /* CLKEN: Clock enable */ #define USART_CR2_CLKEN (1 << 11) /* CPOL: Clock polarity */ #define USART_CR2_CPOL (1 << 10) /* CPHA: Clock phase */ #define USART_CR2_CPHA (1 << 9) /* LBCL: Last bit clock pulse */ #define USART_CR2_LBCL (1 << 8) /* LBDIE: LIN break detection interrupt enable */ #define USART_CR2_LBDIE (1 << 6) /* LBDL: LIN break detection length */ #define USART_CR2_LBDL (1 << 5) /* ADD[3:0]: Address of the usart node */ #define USART_CR2_ADD_MASK 0xF /* --- USART_CR3 values ---------------------------------------------------- */ /* CTSIE: CTS interrupt enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_CTSIE (1 << 10) /* CTSE: CTS enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_CTSE (1 << 9) /* RTSE: RTS enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_RTSE (1 << 8) /* DMAT: DMA enable transmitter */ /* Note: N/A on UART5 */ #define USART_CR3_DMAT (1 << 7) /* DMAR: DMA enable receiver */ /* Note: N/A on UART5 */ #define USART_CR3_DMAR (1 << 6) /* SCEN: Smartcard mode enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_SCEN (1 << 5) /* NACK: Smartcard NACK enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_NACK (1 << 4) /* HDSEL: Half-duplex selection */ #define USART_CR3_HDSEL (1 << 3) /* IRLP: IrDA low-power */ #define USART_CR3_IRLP (1 << 2) /* IREN: IrDA mode enable */ #define USART_CR3_IREN (1 << 1) /* EIE: Error interrupt enable */ #define USART_CR3_EIE (1 << 0) /* --- USART_GTPR values --------------------------------------------------- */ /* GT[7:0]: Guard time value */ /* Note: N/A on UART4 & UART5 */ #define USART_GTPR_GT_MASK (0xFF << 8) /* PSC[7:0]: Prescaler value */ /* Note: N/A on UART4/5 */ #define USART_GTPR_PSC_MASK 0xFF /* TODO */ /* Note to Uwe: what needs to be done here? */ #endif /** @cond */ #else #warning "usart_common_all.h should not be included directly, only via usart.h" #endif /** @endcond */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/common/usart_common_f24.h000066400000000000000000000051271435536612600267460ustar00rootroot00000000000000/** @addtogroup usart_defines @author @htmlonly © @endhtmlonly 2011 Uwe Hermann @author @htmlonly © @endhtmlonly 2011 Stephen Caudle */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H The order of header inclusion is important. usart.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ #ifdef LIBOPENCM3_USART_H /** @endcond */ #ifndef LIBOPENCM3_USART_COMMON_F24_H #define LIBOPENCM3_USART_COMMON_F24_H #include /* --- Convenience macros -------------------------------------------------- */ #define USART6 USART6_BASE /* --- USART registers ----------------------------------------------------- */ /* Status register (USARTx_SR) */ #define USART6_SR USART_SR(USART6_BASE) /* Data register (USARTx_DR) */ #define USART6_DR USART_DR(USART6_BASE) /* Baud rate register (USARTx_BRR) */ #define USART6_BRR USART_BRR(USART6_BASE) /* Control register 1 (USARTx_CR1) */ #define USART6_CR1 USART_CR1(USART6_BASE) /* Control register 2 (USARTx_CR2) */ #define USART6_CR2 USART_CR2(USART6_BASE) /* Control register 3 (USARTx_CR3) */ #define USART6_CR3 USART_CR3(USART6_BASE) /* Guard time and prescaler register (USARTx_GTPR) */ #define USART6_GTPR USART_GTPR(USART6_BASE) /* --- USART_CR1 values ---------------------------------------------------- */ /* OVER8: Oversampling mode */ #define USART_CR1_OVER8 (1 << 15) /* --- USART_CR3 values ---------------------------------------------------- */ /* ONEBIT: One sample bit method enable */ #define USART_CR3_ONEBIT (1 << 11) #endif /** @cond */ #else #warning "usart_common_f24.h should not be included directly, only via usart.h" #endif /** @endcond */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/comparator.h000066400000000000000000000016271435536612600244450ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/crc.h000066400000000000000000000023371435536612600230440ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/crypto.h000066400000000000000000000020421435536612600236060ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F2) # include #elif defined(STM32F4) # include #else # error "CRYPTO processor is supported only" \ "in stm32f2xx, stm32f41xx, stm32f42xx and stm32f43xx family." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/dac.h000066400000000000000000000023361435536612600230230ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/dbgmcu.h000066400000000000000000000050341435536612600235330ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_STM32_DBGMCU_H #define LIBOPENCM3_STM32_DBGMCU_H #include #include /* --- DBGMCU registers ---------------------------------------------------- */ /* Debug MCU IDCODE register (DBGMCU_IDCODE) */ #define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) /* Debug MCU configuration register (DBGMCU_CR) */ /* Note: Only 32bit access supported. */ #define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) /* --- DBGMCU_IDCODE values ------------------------------------------------ */ #define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff #define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 /* --- DBGMCU_CR values ---------------------------------------------------- */ /* Bit 31: Reserved. */ /* Bits [24:22]: Reserved, must be kept cleared. */ /* Bits [4:3]: Reserved. */ #define DBGMCU_CR_SLEEP 0x00000001 #define DBGMCU_CR_STOP 0x00000002 #define DBGMCU_CR_STANDBY 0x00000004 #define DBGMCU_CR_TRACE_IOEN 0x00000020 #define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 #define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 #define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 #define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 #define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 #define DBGMCU_CR_IWDG_STOP 0x00000100 #define DBGMCU_CR_WWDG_STOP 0x00000200 #define DBGMCU_CR_TIM1_STOP 0x00000400 #define DBGMCU_CR_TIM2_STOP 0x00000800 #define DBGMCU_CR_TIM3_STOP 0x00001000 #define DBGMCU_CR_TIM4_STOP 0x00002000 #define DBGMCU_CR_CAN1_STOP 0x00004000 #define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 #define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 #define DBGMCU_CR_TIM8_STOP 0x00020000 #define DBGMCU_CR_TIM5_STOP 0x00040000 #define DBGMCU_CR_TIM6_STOP 0x00080000 #define DBGMCU_CR_TIM7_STOP 0x00100000 #define DBGMCU_CR_CAN2_STOP 0x00200000 #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/desig.h000066400000000000000000000041541435536612600233670ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DESIG_H #define LIBOPENCM3_DESIG_H #include #include /* --- Device Electronic Signature -------------------------------- */ /* Flash size register */ #define DESIG_FLASH_SIZE MMIO16(DESIG_FLASH_SIZE_BASE + 0x00) /* Unique ID register (96 bits) */ /* Note: ST says these may be accessed in any width if you choose */ #define DESIG_UID_15_0 MMIO16(DESIG_UNIQUE_ID_BASE + 0x00) /* Listed as "This field value is also reserved for a future feature" WTH?! */ #define DESIG_UID_31_16 MMIO16(DESIG_UNIQUE_ID_BASE + 0x02) #define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04) #define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08) BEGIN_DECLS /** * Read the on board flash size * @return flash size in KB */ uint16_t desig_get_flash_size(void); /** * Read the full 96 bit unique identifier * Note: ST specifies that bits 31..16 are _also_ reserved for future use * @param result pointer to at least 3xuint32_ts (96 bits) */ void desig_get_unique_id(uint32_t result[]); /** * Read the full 96 bit unique identifier and return it as a * zero-terminated string * @param string memory region to write the result to 8 @param string_len the size of string in bytes */ void desig_get_unique_id_as_string(char *string, unsigned int string_len); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/dma.h000066400000000000000000000023371435536612600230360ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/exti.h000066400000000000000000000024441435536612600232450ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/000077500000000000000000000000001435536612600224245ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/adc.h000066400000000000000000000271641435536612600233360ustar00rootroot00000000000000/** @defgroup adc_defines ADC Defines * * @brief Defined Constants and Types for the STM32F0xx Analog to Digital * Converter * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /** @defgroup adc_reg_base ADC register base addresses * @ingroup adc_defines * *@{*/ #define ADC ADC_BASE #define ADC1 ADC_BASE/* for API compatibility */ /**@}*/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ /* ADC interrupt and status register */ #define ADC_ISR(base) MMIO32(base + 0x00) #define ADC1_ISR ADC_ISR(ADC) /* Interrupt Enable Register */ #define ADC_IER(base) MMIO32(base + 0x04) #define ADC1_IER ADC_IER(ADC) /* Control Register */ #define ADC_CR(base) MMIO32(base + 0x08) #define ADC1_CR ADC_CR(ADC) /* Configuration Register 1 */ #define ADC_CFGR1(base) MMIO32(base + 0x0C) #define ADC1_CFGR1 ADC_CFGR1(ADC) /* Configuration Register 2 */ #define ADC_CFGR2(base) MMIO32(base + 0x10) #define ADC1_CFGR2 ADC_CFGR2(ADC) /* Sample Time Register 1 */ #define ADC_SMPR(base) MMIO32(base + 0x14) #define ADC1_SMPR ADC_SMPR(ADC) /* Watchdog Threshold Register */ #define ADC_TR(base) MMIO32(base + 0x20) #define ADC1_TR ADC_TR(ADC) /* Channel Select Register */ #define ADC_CHSELR(base) MMIO32(base + 0x28) #define ADC1_CHSELR ADC_CHSELR(ADC) /* Regular Data Register */ #define ADC_DR(base) MMIO32(base + 0x40) #define ADC1_DR ADC_DR(ADC) /* Regular Data Register */ #define ADC_CCR MMIO32(ADC_BASE + 0x308) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* ADC_ISR Values -----------------------------------------------------------*/ #define ADC_ISR_AWD (1 << 7) #define ADC_ISR_OVR (1 << 4) #define ADC_ISR_EOSEQ (1 << 3) #define ADC_ISR_EOC (1 << 2) #define ADC_ISR_EOSMP (1 << 1) #define ADC_ISR_ADRDY (1 << 0) /* ADC_IER Values -----------------------------------------------------------*/ #define ADC_IER_AWDIE (1 << 7) #define ADC_IER_OVRIE (1 << 4) #define ADC_IER_EOSEQIE (1 << 3) #define ADC_IER_EOCIE (1 << 2) #define ADC_IER_EOSMPIE (1 << 1) #define ADC_IER_ADRDYIE (1 << 0) /* ADC_CR Values ------------------------------------------------------------*/ #define ADC_CR_ADCAL (1 << 31) #define ADC_CR_ADSTP (1 << 4) #define ADC_CR_ADSTART (1 << 2) #define ADC_CR_ADDIS (1 << 1) #define ADC_CR_ADEN (1 << 0) /* ADC_CFGR1 Values ---------------------------------------------------------*/ #define ADC_CFGR1_AWDCH_SHIFT 26 #define ADC_CFGR1_AWDCH (0x1F << ADC_CFGR1_AWDCH_SHIFT) #define ADC_CFGR1_AWDCH_VAL(x) ((x) << ADC_CFGR1_AWDCH_SHIFT) #define ADC_CFGR1_AWDEN (1 << 23) #define ADC_CFGR1_AWDSGL (1 << 22) #define ADC_CFGR1_DISCEN (1 << 16) #define ADC_CFGR1_AUTOFF (1 << 15) #define ADC_CFGR1_WAIT (1 << 14) #define ADC_CFGR1_CONT (1 << 13) #define ADC_CFGR1_OVRMOD (1 << 12) #define ADC_CFGR1_EXTEN_SHIFT 10 #define ADC_CFGR1_EXTEN (3 << ADC_CFGR1_EXTEN_SHIFT) #define ADC_CFGR1_EXTEN_DISABLE (0 << ADC_CFGR1_EXTEN_SHIFT) #define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) #define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) #define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) #define ADC_CFGR1_EXTSEL_SHIFT 6 #define ADC_CFGR1_EXTSEL (7 << ADC_CFGR1_EXTSEL_SHIFT) #define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) #define ADC_CFGR1_ALIGN (1 << 5) #define ADC_CFGR1_RES_SHIFT 3 #define ADC_CFGR1_RES (3 << ADC_CFGR1_RES_SHIFT) #define ADC_CFGR1_RES_12_BIT (0 << ADC_CFGR1_RES_SHIFT) #define ADC_CFGR1_RES_10_BIT (1 << ADC_CFGR1_RES_SHIFT) #define ADC_CFGR1_RES_8_BIT (2 << ADC_CFGR1_RES_SHIFT) #define ADC_CFGR1_RES_6_BIT (3 << ADC_CFGR1_RES_SHIFT) #define ADC_CFGR1_SCANDIR (1 << 2) #define ADC_CFGR1_DMACFG (1 << 1) #define ADC_CFGR1_DMAEN (1 << 0) /* ADC_CFGR2 Values ---------------------------------------------------------*/ #define ADC_CFGR2_CKMODE_SHIFT 30 #define ADC_CFGR2_CKMODE (3 << ADC_CFGR2_CKMODE_SHIFT) #define ADC_CFGR2_CKMODE_CK_ADC (0 << ADC_CFGR2_CKMODE_SHIFT) #define ADC_CFGR2_CKMODE_PCLK_DIV2 (1 << ADC_CFGR2_CKMODE_SHIFT) #define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT) /* ADC_SMPR Values ----------------------------------------------------------*/ #define ADC_SMPR_SMP_SHIFT 0 #define ADC_SMPR_SMP (7 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_001DOT5 (0 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_007DOT5 (1 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_013DOT5 (2 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_028DOT5 (3 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_041DOT5 (4 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_055DOT5 (5 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_071DOT5 (6 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_239DOT5 (7 << ADC_SMPR_SMP_SHIFT) /* ADC_TR Values ------------------------------------------------------------*/ #define ADC_TR_LT_SHIFT 0 #define ADC_TR_LT (0xFFF << ADC_TR_LT_SHIFT) #define ADC_TR_LT_VAL(x) ((x) << ADC_TR_LT_SHIFT) #define ADC_TR_HT_SHIFT 16 #define ADC_TR_HT (0xFFF << ADC_TR_HT_SHIFT) #define ADC_TR_HT_VAL(x) ((x) << ADC_TR_HT_SHIFT) /* ADC_CHSELR Values --------------------------------------------------------*/ #define ADC_CHSELR_CHSEL(x) (1 << (x)) /* ADC_DR Values ------------------------------------------------------------*/ #define ADC_DR_DATA 0xFFFF /* ADC_CCR Values -----------------------------------------------------------*/ #define ADC_CCR_VBATEN (1 << 24) #define ADC_CCR_TSEN (1 << 23) #define ADC_CCR_VREFEN (1 << 22) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /** @defgroup adc_api_res ADC resolutions * @ingroup adc_defines * *@{*/ #define ADC_RESOLUTION_12BIT ADC_CFGR1_RES_12_BIT #define ADC_RESOLUTION_10BIT ADC_CFGR1_RES_10_BIT #define ADC_RESOLUTION_8BIT ADC_CFGR1_RES_8_BIT #define ADC_RESOLUTION_6BIT ADC_CFGR1_RES_6_BIT /**@}*/ /** @defgroup adc_api_smptime ADC sampling time * @ingroup adc_defines * *@{*/ #define ADC_SMPTIME_001DOT5 ADC_SMPR_SMP_001DOT5 #define ADC_SMPTIME_007DOT5 ADC_SMPR_SMP_007DOT5 #define ADC_SMPTIME_013DOT5 ADC_SMPR_SMP_013DOT5 #define ADC_SMPTIME_028DOT5 ADC_SMPR_SMP_028DOT5 #define ADC_SMPTIME_041DOT5 ADC_SMPR_SMP_041DOT5 #define ADC_SMPTIME_055DOT5 ADC_SMPR_SMP_055DOT5 #define ADC_SMPTIME_071DOT5 ADC_SMPR_SMP_071DOT5 #define ADC_SMPTIME_239DOT5 ADC_SMPR_SMP_239DOT5 /**@}*/ /** @defgroup adc_api_clksource ADC clock source * @ingroup adc_defines * *@{*/ #define ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_CK_ADC #define ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2 #define ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4 /**@}*/ /** @defgroup adc_channel ADC Channel Numbers * @ingroup adc_defines * *@{*/ #define ADC_CHANNEL0 0x00 #define ADC_CHANNEL1 0x01 #define ADC_CHANNEL2 0x02 #define ADC_CHANNEL3 0x03 #define ADC_CHANNEL4 0x04 #define ADC_CHANNEL5 0x05 #define ADC_CHANNEL6 0x06 #define ADC_CHANNEL7 0x07 #define ADC_CHANNEL8 0x08 #define ADC_CHANNEL9 0x09 #define ADC_CHANNEL10 0x0A #define ADC_CHANNEL11 0x0B #define ADC_CHANNEL12 0x0C #define ADC_CHANNEL13 0x0D #define ADC_CHANNEL14 0x0E #define ADC_CHANNEL15 0x0F #define ADC_CHANNEL_TEMP 0x10 #define ADC_CHANNEL_VREF 0x11 #define ADC_CHANNEL_VBAT 0x12 /**@}*/ /** @defgroup adc_api_opmode ADC Operation Modes * @ingroup adc_defines * *@{*/ enum adc_opmode { ADC_MODE_SEQUENTIAL, ADC_MODE_SCAN, ADC_MODE_SCAN_INFINITE, }; /**@}*/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS /* Operation mode API */ void adc_set_continuous_conversion_mode(uint32_t adc); void adc_set_single_conversion_mode(uint32_t adc); void adc_enable_discontinuous_mode(uint32_t adc); void adc_disable_discontinuous_mode(uint32_t adc); void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode); /* Trigger API */ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity); void adc_disable_external_trigger_regular(uint32_t adc); /* Conversion API */ void adc_start_conversion_regular(uint32_t adc); bool adc_eoc(uint32_t adc); uint32_t adc_read_regular(uint32_t adc); /* Interrupt configuration */ void adc_enable_watchdog_interrupt(uint32_t adc); void adc_disable_watchdog_interrupt(uint32_t adc); bool adc_get_watchdog_flag(uint32_t adc); void adc_clear_watchdog_flag(uint32_t adc); void adc_enable_overrun_interrupt(uint32_t adc); void adc_disable_overrun_interrupt(uint32_t adc); bool adc_get_overrun_flag(uint32_t adc); void adc_clear_overrun_flag(uint32_t adc); void adc_enable_eoc_sequence_interrupt(uint32_t adc); void adc_disable_eoc_sequence_interrupt(uint32_t adc); bool adc_get_eoc_sequence_flag(uint32_t adc); void adc_enable_eoc_interrupt(uint32_t adc); void adc_disable_eoc_interrupt(uint32_t adc); /* Basic configuration */ void adc_power_off(uint32_t adc); void adc_power_on(uint32_t adc); void adc_set_clk_source(uint32_t adc, uint32_t source); void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); void adc_set_resolution(uint32_t adc, uint16_t resolution); void adc_set_left_aligned(uint32_t adc); void adc_set_right_aligned(uint32_t adc); void adc_enable_dma(uint32_t adc); void adc_disable_dma(uint32_t adc); void adc_enable_temperature_sensor(void); void adc_disable_temperature_sensor(void); void adc_enable_vref_sensor(void); void adc_disable_vref_sensor(void); void adc_enable_vbat_sensor(void); void adc_disable_vbat_sensor(void); void adc_calibrate_start(uint32_t adc); void adc_calibrate_wait_finish(uint32_t adc); /* Analog Watchdog */ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan); void adc_disable_analog_watchdog(uint32_t adc); void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold); void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/cec.h000066400000000000000000000104441435536612600233320ustar00rootroot00000000000000/** @defgroup CEC_defines CEC Defines * * @brief Defined Constants and Types for the STM32F0xx HDMI-CEC * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CEC_H #define LIBOPENCM3_CEC_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ #define CEC CEC_BASE /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define CEC_CR MMIO32(CEC_BASE + 0x00) #define CEC_CFGR MMIO32(CEC_BASE + 0x04) #define CEC_TXDR MMIO32(CEC_BASE + 0x08) #define CEC_RXDR MMIO32(CEC_BASE + 0x0c) #define CEC_ISR MMIO32(CEC_BASE + 0x10) #define CEC_IER MMIO32(CEC_BASE + 0x14) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* CEC_CR Values ------------------------------------------------------------*/ #define CEC_CR_TXEOM (1 << 2) #define CEC_CR_TXSOM (1 << 1) #define CEC_CR_CECEN (1 << 0) /* CEC_CFGR Values ----------------------------------------------------------*/ #define CEC_CFGR_LSTN (1 << 31) #define CEC_CFGR_OAR_SHIFT 16 #define CEC_CFGR_OAR (0x3FFF << CEC_CFGR_OAR_SHIFT) #define CEC_CFGR_SFTOPT (1 << 8) #define CEC_CFGR_BRDNOGEN (1 << 7) #define CEC_CFGR_LBPEGEN (1 << 6) #define CEC_CFGR_BREGEN (1 << 5) #define CEC_CFGR_BRESTP (1 << 4) #define CEC_CFGR_RXTOL (1 << 3) #define CEC_CFGR_SFT_SHIFT 0 #define CEC_CFGR_SFT (7 >> CEC_CFGR_SFT_SHIFT) /* CEC_ISR Values -----------------------------------------------------------*/ #define CEC_ISR_TXACKE (1 << 12) #define CEC_ISR_TXERR (1 << 11) #define CEC_ISR_TXUDR (1 << 10) #define CEC_ISR_TXEND (1 << 9) #define CEC_ISR_TXBR (1 << 8) #define CEC_ISR_ARBLST (1 << 7) #define CEC_ISR_RXACKE (1 << 6) #define CEC_ISR_LBPE (1 << 5) #define CEC_ISR_SBPE (1 << 4) #define CEC_ISR_BRE (1 << 3) #define CEC_ISR_RXOVR (1 << 2) #define CEC_ISR_RXEND (1 << 1) #define CEC_ISR_RXBR (1 << 0) /* CEC_IER Values -----------------------------------------------------------*/ #define CEC_IER_TXACKIE (1 << 12) #define CEC_IER_TXERRIE (1 << 11) #define CEC_IER_TXUDRIE (1 << 10) #define CEC_IER_TXENDIE (1 << 9) #define CEC_IER_TXBRIE (1 << 8) #define CEC_IER_ARBLSTIE (1 << 7) #define CEC_IER_RXACKIE (1 << 6) #define CEC_IER_LBPEIE (1 << 5) #define CEC_IER_SBPEIE (1 << 4) #define CEC_IER_BREIE (1 << 3) #define CEC_IER_RXOVRIE (1 << 2) #define CEC_IER_RXENDIE (1 << 1) #define CEC_IER_RXBRIE (1 << 0) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/comparator.h000066400000000000000000000114571435536612600247540ustar00rootroot00000000000000/** @defgroup comp_defines COMP Defines * * @brief libopencm3 Defined Constants and Types for the STM32F0xx * Comparator module * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 29 Jun 2013 * *LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_COMP_H #define LIBOPENCM3_COMP_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ #define COMP1 0 #define COMP2 1 /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define COMP_CSR(i) MMIO16(SYSCFG_COMP_BASE + 0x1c + (i)*2) #define COMP_CSR1 COMP_CSR(COMP1) #define COMP_CSR2 COMP_CSR(COMP2) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* COMP_CSR Values ----------------------------------------------------------*/ #define COMP_CSR_LOCK (1 << 15) #define COMP_CSR_OUT (1 << 14) #define COMP_CSR_HYST_SHIFT 12 #define COMP_CSR_HYST (3 << COMP_CSR_HYST_SHIFT) #define COMP_CSR_HYST_NO (0 << COMP_CSR_HYST_SHIFT) #define COMP_CSR_HYST_LOW (1 << COMP_CSR_HYST_SHIFT) #define COMP_CSR_HYST_MED (2 << COMP_CSR_HYST_SHIFT) #define COMP_CSR_HYST_HIGH (3 << COMP_CSR_HYST_SHIFT) #define COMP_CSR_POL (1 << 11) #define COMP_CSR_OUTSEL_SHIFT 8 #define COMP_CSR_OUTSEL (7 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_NONE (0 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_TIM1_BRK (1 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_TIM1_IC1 (2 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_TIM1_OCRCLR (3 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_TIM2_IC4 (4 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_TIM2_OCRCLR (5 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_TIM3_IC1 (6 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_OUTSEL_TIM3_OCRCLR (7 << COMP_CSR_OUTSEL_SHIFT) #define COMP_CSR_WINDWEN (1 << 23) #define COMP_CSR_INSEL_SHIFT 4 #define COMP_CSR_INSEL (7 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_1_4_VREFINT (0 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_2_4_VREFINT (1 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_3_4_VREFINT (2 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_4_4_VREFINT (3 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_VREFINT (3 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_INM4 (4 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_INM5 (5 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_INSEL_INM6 (6 << COMP_CSR_INSEL_SHIFT) #define COMP_CSR_SPEED_SHIFT 2 #define COMP_CSR_SPEED (3 << COMP_CSR_SPEED_SHIFT) #define COMP_CSR_SPEED_HIGH (0 << COMP_CSR_SPEED_SHIFT) #define COMP_CSR_SPEED_MED (1 << COMP_CSR_SPEED_SHIFT) #define COMP_CSR_SPEED_LOW (2 << COMP_CSR_SPEED_SHIFT) #define COMP_CSR_SPEED_VERYLOW (3 << COMP_CSR_SPEED_SHIFT) #define COMP_CSR_SW1 (1 << 1) #define COMP_CSR_EN (1 << 0) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS void comp_enable(uint8_t id); void comp_disable(uint8_t id); void comp_select_input(uint8_t id, uint32_t input); void comp_select_output(uint8_t id, uint32_t output); void comp_select_hyst(uint8_t id, uint32_t hyst); void comp_select_speed(uint8_t id, uint32_t speed); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/crc.h000066400000000000000000000053051435536612600233470ustar00rootroot00000000000000/** @defgroup crc_defines CRC Defines * * @brief libopencm3 Defined Constants and Types for the STM32F1xx CRC * Generator * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 29 Jun 2013 * *LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRC_H #define LIBOPENCM3_CRC_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register values */ /*****************************************************************************/ #define CRC_CR_REV_OUT (1 << 7) #define CRC_CR_REV_IN_SHIFT 5 #define CRC_CR_REV_IN (3 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_NONE (0 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_BYTE (1 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_HALF (2 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_WORD (3 << CRC_CR_REV_IN_SHIFT) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/dac.h000066400000000000000000000102211435536612600233200ustar00rootroot00000000000000/** @defgroup dac_defines DAC Defines * * @brief Defined Constants and Types for the STM32F0xx Digital to Analog * Converter * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DAC_H #define LIBOPENCM3_DAC_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ #define DAC DAC_BASE /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define DAC_CR MMIO32(DAC_BASE + 0x00) #define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) #define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) #define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) #define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) #define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) #define DAC_SR MMIO32(DAC_BASE + 0x34) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* DAC_CR Values ------------------------------------------------------------*/ #define DAC_CR_DMAUDRIE1 (1 << 13) #define DAC_CR_DMAEN1 (1 << 12) #define DAC_CR_TSEL1_SHIFT 3 #define DAC_CR_TSEL1 (7 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_TIM6_TRGO (0 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_TIM8_TRGO (1 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_TIM7_TRGO (2 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_TIM5_TRGO (3 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_TIM2_TRGO (4 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_TIM4_TRGO (5 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_EXT_9 (6 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TSEL1_SWTRG (7 << DAC_CR_TSEL1_SHIFT) #define DAC_CR_TEN1 (1 << 2) #define DAC_CR_BOFF1 (1 << 1) #define DAC_CR_EN1 (1 << 0) /* DAC_SWTRIGR Values -------------------------------------------------------*/ #define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* DAC_DHR12R1 Values -------------------------------------------------------*/ #define DAC_DHR12R1_DACC1DHR 0xFFF /* DAC_DHR12L1 Values -------------------------------------------------------*/ #define DAC_DHR12L1_DACC1DHR (0xFFF << 4) /* DAC_DHR8R1 Values --------------------------------------------------------*/ #define DAC_DHR8R1_DACC1DHR 0xFF /* DAC_DOR1 Values ----------------------------------------------------------*/ #define DAC_DOR1_DACC1DOR 0xFFF /* DAC_SR Values ------------------------------------------------------------*/ #define DAC_SR_DMAUDR1 (1 << 13) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/dma.h000066400000000000000000000021401435536612600233330ustar00rootroot00000000000000/** @defgroup dma_defines DMA Defines * * @ingroup STM32F0xx_defines * * @brief Defined Constants and Types for the STM32F0xx DMA Controller * * @version 1.0.0 * * @date 10 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DMA_H #define LIBOPENCM3_DMA_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/doc-stm32f0.h000066400000000000000000000011211435536612600245310ustar00rootroot00000000000000/** @mainpage libopencm3 STM32F0 * * @version 1.0.0 * * @date 11 July 2013 * * API documentation for ST Microelectronics STM32F0 Cortex M0 series. * * LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F0xx STM32F0xx * Libraries for ST Microelectronics STM32F0xx series. * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F0xx_defines STM32F0xx Defines * * @brief Defined Constants and Types for the STM32F0xx series * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/exti.h000066400000000000000000000022551435536612600235520ustar00rootroot00000000000000/** @defgroup exti_defines EXTI Defines * * @brief Defined Constants and Types for the STM32F0xx External Interrupts * * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_EXTI_H #define LIBOPENCM3_EXTI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/flash.h000066400000000000000000000122461435536612600236770ustar00rootroot00000000000000/** @defgroup flash_defines FLASH Defines * * @brief Defined Constants and Types for the STM32F0xx Flash memory * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_FLASH_H #define LIBOPENCM3_FLASH_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) #define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) #define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) #define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) #define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) #define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) #define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) #define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* --- FLASH_ACR values ---------------------------------------------------- */ #define FLASH_ACR_PRFTBS (1 << 5) #define FLASH_ACR_PRFTBE (1 << 4) #define FLASH_ACR_LATENCY_SHIFT 0 #define FLASH_ACR_LATENCY 7 #define FLASH_ACR_LATENCY_000_024MHZ 0 #define FLASH_ACR_LATENCY_024_048MHZ 1 #define FLASH_ACR_LATENCY_0WS 0 #define FLASH_ACR_LATENCY_1WS 1 /* --- FLASH_SR values ----------------------------------------------------- */ #define FLASH_SR_EOP (1 << 5) #define FLASH_SR_WRPRTERR (1 << 4) #define FLASH_SR_PGERR (1 << 2) #define FLASH_SR_BSY (1 << 0) /* --- FLASH_CR values ----------------------------------------------------- */ #define FLASH_CR_OBL_LAUNCH (1 << 13) #define FLASH_CR_EOPIE (1 << 12) #define FLASH_CR_ERRIE (1 << 10) #define FLASH_CR_OPTWRE (1 << 9) #define FLASH_CR_LOCK (1 << 7) #define FLASH_CR_STRT (1 << 6) #define FLASH_CR_OPTER (1 << 5) #define FLASH_CR_OPTPG (1 << 4) #define FLASH_CR_MER (1 << 2) #define FLASH_CR_PER (1 << 1) #define FLASH_CR_PG (1 << 0) /* --- FLASH_OBR values ---------------------------------------------------- */ #define FLASH_OBR_DATA1_SHIFT 24 #define FLASH_OBR_DATA1 (0xFF << FLASH_OBR_DATA1_SHIFT) #define FLASH_OBR_DATA0_SHIFT 16 #define FLASH_OBR_DATA0 (0xFF << FLASH_OBR_DATA0_SHIFT) #define FLASH_OBR_RAM_PARITY_CHECK (1 << 14) #define FLASH_OBR_VDDA_MONITOR (1 << 13) #define FLASH_OBR_NBOOT1 (1 << 12) #define FLASH_OBR_NRST_STDBY (1 << 10) #define FLASH_OBR_NRST_STOP (1 << 9) #define FLASH_OBR_WDG_SW (1 << 8) #define FLASH_OBR_RDPRT_SHIFT 1 #define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT) #define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT) #define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT) #define FLASH_OBR_RDPRT_L2 (2 << FLASH_OBR_RDPRT_SHIFT) #define FLASH_OBR_OPTERR (1 << 0) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ #define FLASH_RDP_L0 ((uint8_t)0xaa) #define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */ #define FLASH_RDP_L2 ((uint8_t)0xcc) #define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) #define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS void flash_prefetch_buffer_enable(void); void flash_prefetch_buffer_disable(void); void flash_set_ws(uint32_t ws); void flash_wait_busy(void); void flash_program_u32(uint32_t address, uint32_t data); void flash_program_u16(uint32_t address, uint16_t data); void flash_erase_page(uint32_t page_address); void flash_erase_all_pages(void); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/gpio.h000066400000000000000000000053051435536612600235360ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines * * @brief Defined Constants and Types for the STM32F0xx General Purpose I/O * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 1 July 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_GPIO_H #define LIBOPENCM3_GPIO_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define GPIO_BRR(port) MMIO32(port + 0x24) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) #define GPIOD_BRR GPIO_BRR(GPIOD) #define GPIOF_BRR GPIO_BRR(GPIOF) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /** @defgroup gpio_speed GPIO Output Pin Speed @ingroup gpio_defines @{*/ #define GPIO_OSPEED_LOW 0x0 #define GPIO_OSPEED_MED 0x1 #define GPIO_OSPEED_HIGH 0x3 /**@}*/ /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/i2c.h000066400000000000000000000216631435536612600232620ustar00rootroot00000000000000/** @defgroup i2c_defines I2C Defines * * @brief Defined Constants and Types for the STM32F0xx I2C * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_I2C_H #define LIBOPENCM3_I2C_H #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ #define I2C1 I2C1_BASE #define I2C2 I2C2_BASE /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) #define I2C1_CR1 I2C_CR1(I2C1) #define I2C2_CR1 I2C_CR1(I2C2) #define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) #define I2C1_CR2 I2C_CR2(I2C1) #define I2C2_CR2 I2C_CR2(I2C2) #define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) #define I2C1_OAR1 I2C_OAR1(I2C1) #define I2C2_OAR1 I2C_OAR1(I2C2) #define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) #define I2C1_OAR2 I2C_OAR2(I2C1) #define I2C2_OAR2 I2C_OAR2(I2C2) #define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10) #define I2C1_TIMINGR I2C_TIMINGR(I2C1) #define I2C2_TIMINGR I2C_TIMINGR(I2C2) #define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14) #define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) #define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) #define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18) #define I2C1_ISR I2C_ISR(I2C1) #define I2C2_ISR I2C_ISR(I2C2) #define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C) #define I2C1_ICR I2C_ICR(I2C1) #define I2C2_ICR I2C_ICR(I2C2) #define I2C_PECR(i2c_base) MMIO8(i2c_base + 0x20) #define I2C1_PECR I2C_PECR(I2C1) #define I2C2_PECR I2C_PECR(I2C2) #define I2C_RXDR(i2c_base) MMIO8(i2c_base + 0x24) #define I2C1_RXDR I2C_RXDR(I2C1) #define I2C2_RXDR I2C_RXDR(I2C2) #define I2C_TXDR(i2c_base) MMIO8(i2c_base + 0x28) #define I2C1_TXDR I2C_TXDR(I2C1) #define I2C2_TXDR I2C_TXDR(I2C2) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* I2C_CR1 values ---------------------------------------------------------- */ #define I2C_CR1_PECEN (1 << 23) #define I2C_CR1_ALERTEN (1 << 22) #define I2C_CR1_SMBDEN (1 << 21) #define I2C_CR1_SMBHEN (1 << 20) #define I2C_CR1_GCEN (1 << 19) #define I2C_CR1_WUPEN (1 << 18) #define I2C_CR1_NOSTRETCH (1 << 17) #define I2C_CR1_SBC (1 << 16) #define I2C_CR1_RXDMAEN (1 << 15) #define I2C_CR1_TXDMAEN (1 << 14) #define I2C_CR1_ANFOFF (1 << 12) #define I2C_CR1_DNF_SHIFT 8 #define I2C_CR1_DNF (0x0F << I2C_CR1_DNF_SHIFT) #define I2C_CR1_DNF_VAL(x) ((x) << I2C_CR1_DNF_SHIFT) #define I2C_CR1_ERRIE (1 << 7) #define I2C_CR1_TCIE (1 << 6) #define I2C_CR1_STOPIE (1 << 5) #define I2C_CR1_NACKIE (1 << 4) #define I2C_CR1_ADDRIE (1 << 3) #define I2C_CR1_RXIE (1 << 2) #define I2C_CR1_TXIE (1 << 1) #define I2C_CR1_PE (1 << 0) /* I2C_CR2 values ---------------------------------------------------------- */ #define I2C_CR2_PECBYTE (1 << 26) #define I2C_CR2_AUTOEND (1 << 25) #define I2C_CR2_RELOAD (1 << 24) #define I2C_CR2_NBYTES_SHIFT 16 #define I2C_CR2_NBYTES (0xFF << I2C_CR2_NBYTES_SHIFT) #define I2C_CR2_NBYTES_VAL(x) ((x) << I2C_CR2_NBYTES_SHIFT) #define I2C_CR2_NACK (1 << 15) #define I2C_CR2_STOP (1 << 14) #define I2C_CR2_START (1 << 13) #define I2C_CR2_HEAD10R (1 << 12) #define I2C_CR2_ADD10 (1 << 11) #define I2C_CR2_RD_WRN (1 << 10) #define I2C_CR2_SADD_SHIFT 0 #define I2C_CR2_SADD (0x3FF << I2C_CR2_SADD_SHIFT) #define I2C_CR2_SADD_VAL(x) ((x) << I2C_CR2_SADD_SHIFT) /* I2C_OAR1 values --------------------------------------------------------- */ #define I2C_OAR1_OA1EN (1 << 15) #define I2C_OAR1_OA1MODE (1 << 10) #define I2C_OAR1_OA1_SHIFT 0 #define I2C_OAR1_OA1 (0x3FF << I2C_OAR1_OA1_SHIFT) #define I2C_OAR1_OA1_VAL(x) ((x) << I2C_OAR1_OA1_SHIFT) /* I2C_OAR2 values --------------------------------------------------------- */ #define I2C_OAR2_OA1EN (1 << 15) #define I2C_OAR2_OA2MSK_SHIFT 8 #define I2C_OAR2_OA2MSK (7 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_NOMASK (0 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_1_BIT (1 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_2_BIT (2 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_3_BIT (3 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_4_BIT (4 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_5_BIT (5 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_6_BIT (6 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) #define I2C_OAR2_OA2_SHIFT 1 #define I2C_OAR2_OA2 (0x7F << I2C_OAR2_OA2_SHIFT) #define I2C_OAR2_OA2_VAL(x) ((x) << I2C_OAR2_OA2_SHIFT) /* I2C_TIMINGR values ------------------------------------------------------ */ #define I2C_TIMINGR_PRESC_SHIFT 28 #define I2C_TIMINGR_PRESC (0x0F << I2C_TIMINGR_PRESC_SHIFT) #define I2C_TIMINGR_PRESC_VAL(x) ((x) << I2C_TIMINGR_PRESC_SHIFT) #define I2C_TIMINGR_SCLDEL_SHIFT 20 #define I2C_TIMINGR_SCLDEL (0x0F << I2C_TIMINGR_SCLDEL_SHIFT) #define I2C_TIMINGR_SCLDEL_VAL(x) ((x) << I2C_TIMINGR_SCLDEL_SHIFT) #define I2C_TIMINGR_SDADEL_SHIFT 16 #define I2C_TIMINGR_SDADEL (0x0F << I2C_TIMINGR_SDADEL_SHIFT) #define I2C_TIMINGR_SDADEL_VAL(x) ((x) << I2C_TIMINGR_SDADEL_SHIFT) #define I2C_TIMINGR_SCLH_SHIFT 8 #define I2C_TIMINGR_SCLH (0xFF << I2C_TIMINGR_SCLH_SHIFT) #define I2C_TIMINGR_SCLH_VAL(x) ((x) << I2C_TIMINGR_SCLH_SHIFT) #define I2C_TIMINGR_SCLL_SHIFT 0 #define I2C_TIMINGR_SCLL (0xFF << I2C_TIMINGR_SCLL_SHIFT) #define I2C_TIMINGR_SCLL_VAL(x) ((x) << I2C_TIMINGR_SCLL_SHIFT) /* I2C_TIMEOUTR values ----------------------------------------------------- */ #define I2C_TIMEOUTR_TETXEN (1 << 31) #define I2C_TIMEOUTR_TIMEOUTB_SHIFT 16 #define I2C_TIMEOUTR_TIMEOUTB (0xFFF << I2C_TIMEOUTR_TIMEOUTB_SHIFT) #define I2C_TIMEOUTR_TIMEOUTB_VAL(x) ((x) << I2C_TIMEOUTR_TIMEOUTB_SHIFT) #define I2C_TIMEOUTR_TIMOUTEN (1 << 15) #define I2C_TIMEOUTR_TIDLE (1 << 12) #define I2C_TIMEOUTR_TIMEOUTA_SHIFT 0 #define I2C_TIMEOUTR_TIMEOUTA (0xFFF << I2C_TIMEOUTR_TIMEOUTA_SHIFT) #define I2C_TIMEOUTR_TIMEOUTA_VAL(x) ((x) << I2C_TIMEOUTR_TIMEOUTA_SHIFT) /* I2C_ISR values ---------------------------------------------------------- */ #define I2C_ISR_ADDCODE_SHIFT 17 #define I2C_ISR_ADDCODE (0x7F << I2C_ISR_ADDCODE_SHIFT) #define I2C_ISR_ADDCODE_VAL(x) ((x) << I2C_ISR_ADDCODE_SHIFT) #define I2C_ISR_ADDCODE_VALG(reg) (((reg) & I2C_ISR_ADDCODE) >> \ I2C_ISR_ADDCODE_SHIFT) #define I2C_ISR_DIR (1 << 16) #define I2C_ISR_BUSY (1 << 15) #define I2C_ISR_ALERT (1 << 13) #define I2C_ISR_TIMEOUT (1 << 12) #define I2C_ISR_PECERR (1 << 11) #define I2C_ISR_OVR (1 << 10) #define I2C_ISR_ARLO (1 << 9) #define I2C_ISR_BERR (1 << 8) #define I2C_ISR_TCR (1 << 7) #define I2C_ISR_TC (1 << 6) #define I2C_ISR_STOPF (1 << 5) #define I2C_ISR_NACKF (1 << 4) #define I2C_ISR_ADDR (1 << 3) #define I2C_ISR_RXNE (1 << 2) #define I2C_ISR_TXIS (1 << 1) #define I2C_ISR_TXE (1 << 0) /* I2C_ICR values ---------------------------------------------------------- */ #define I2C_ICR_ALERTCF (1 << 13) #define I2C_ICR_TIMEOUTCF (1 << 12) #define I2C_ICR_PECCF (1 << 11) #define I2C_ICR_OVRCF (1 << 10) #define I2C_ICR_ARLOCF (1 << 9) #define I2C_ICR_BERRCF (1 << 8) #define I2C_ICR_STOPCF (1 << 5) #define I2C_ICR_NACKCF (1 << 4) #define I2C_ICR_ADDRCF (1 << 3) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/irq.yaml000066400000000000000000000007471435536612600241130ustar00rootroot00000000000000includeguard: LIBOPENCM3_STM32_F0_NVIC_H partname_humanreadable: STM32 F0 series partname_doxygen: STM32F0 irqs: - wwdg - pvd - rtc - flash - rcc - exti0_1 - exti2_3 - exti4_15 - tsc - dma1_channel1 - dma1_channel2_3 - dma1_channel4_5 - adc_comp - tim1_brk_up_trg_com - tim1_cc - tim2 - tim3 - tim6_dac - reserved0 - tim14 - tim15 - tim16 - tim17 - i2c1 - i2c2 - spi1 - spi2 - usart1 - usart2 - reserved1 - cec - reserved2 hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/iwdg.h000066400000000000000000000051551435536612600235350ustar00rootroot00000000000000/** @defgroup iwdg_defines IWDG Defines * * @brief Defined Constants and Types for the STM32F0xx Independent Watchdog * Timer * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 18 August 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_IWDG_H #define LIBOPENCM3_IWDG_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ /* Key Register (IWDG_WINR) */ #define IWDG_WINR MMIO32(IWDG_BASE + 0x10) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* --- IWDG_SR values ------------------------------------------------------ */ /* WVU: Watchdog counter window value update */ #define IWDG_SR_WVU (1 << 2) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/memorymap.h000066400000000000000000000066201435536612600246070ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * .. based on file from F4. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_MEMORYMAP_H #define LIBOPENCM3_MEMORYMAP_H #include /* --- STM32 specific peripheral definitions ------------------------------- */ /* Memory map for all buses */ #define FLASH_BASE ((uint32_t)0x08000000) #define PERIPH_BASE ((uint32_t)0x40000000) #define INFO_BASE ((uint32_t)0x1ffff000) #define PERIPH_BASE_APB (PERIPH_BASE + 0x00000000) #define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000) #define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x08000000) /* Register boundary addresses */ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB + 0x0000) #define TIM3_BASE (PERIPH_BASE_APB + 0x0400) #define TIM6_BASE (PERIPH_BASE_APB + 0x1000) #define TIM14_BASE (PERIPH_BASE_APB + 0x2000) /* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ #define RTC_BASE (PERIPH_BASE_APB + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB + 0x3000) /* PERIPH_BASE_APB + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ #define SPI2_BASE (PERIPH_BASE_APB + 0x3800) /* PERIPH_BASE_APB + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ #define USART2_BASE (PERIPH_BASE_APB + 0x4400) #define I2C1_BASE (PERIPH_BASE_APB + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB + 0x5800) #define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000) #define DAC_BASE (PERIPH_BASE_APB + 0x7400) #define CEC_BASE (PERIPH_BASE_APB + 0x7800) #define SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000) #define EXTI_BASE (PERIPH_BASE_APB + 0x10400) #define ADC_BASE (PERIPH_BASE_APB + 0x12400) #define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) #define SPI1_I2S1_BASE (PERIPH_BASE_APB + 0x13000) #define USART1_BASE (PERIPH_BASE_APB + 0x13800) #define TIM15_BASE (PERIPH_BASE_APB + 0x14000) #define TIM16_BASE (PERIPH_BASE_APB + 0x14400) #define TIM17_BASE (PERIPH_BASE_APB + 0x14800) #define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800) /* AHB1 */ #define DMA_BASE (PERIPH_BASE_AHB1 + 0x0000) #define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) #define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) #define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) /* AHB2 */ #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) #define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) #define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00) #define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) /* Device Electronic Signature */ /* ??? #define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0) #define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8) */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/pwr.h000066400000000000000000000046571435536612600234210ustar00rootroot00000000000000/** @defgroup pwr_defines PWR Defines * * @brief Defined Constants and Types for the STM32F0xx PWR Control * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 5 December 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_PWR_H #define LIBOPENCM3_PWR_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* EWUP: Enable WKUP2 pin */ #define PWR_CSR_EWUP2 (1 << 9) /* EWUP: Enable WKUP1 pin */ #define PWR_CSR_EWUP1 (1 << 8) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/rcc.h000066400000000000000000000427631435536612600233600ustar00rootroot00000000000000/** @defgroup rcc_defines RCC Defines * * @brief libopencm3 STM32F0xx Reset and Clock Control * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 29 Jun 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LIBOPENCM3_RCC_H #define LIBOPENCM3_RCC_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define RCC_CR MMIO32(RCC_BASE + 0x00) #define RCC_CFGR MMIO32(RCC_BASE + 0x04) #define RCC_CIR MMIO32(RCC_BASE + 0x08) #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) #define RCC_AHBENR MMIO32(RCC_BASE + 0x14) #define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) #define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) #define RCC_BDCR MMIO32(RCC_BASE + 0x20) #define RCC_CSR MMIO32(RCC_BASE + 0x24) #define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) #define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) #define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) #define RCC_CR2 MMIO32(RCC_BASE + 0x32) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* --- RCC_CR values ------------------------------------------------------- */ #define RCC_CR_PLLRDY (1 << 25) #define RCC_CR_PLLON (1 << 24) #define RCC_CR_CSSON (1 << 19) #define RCC_CR_HSEBYP (1 << 18) #define RCC_CR_HSERDY (1 << 17) #define RCC_CR_HSEON (1 << 16) #define RCC_CR_HSICAL_SHIFT 8 #define RCC_CR_HSICAL (0xFF << RCC_CR_HSICAL_SHIFT) #define RCC_CR_HSITRIM_SHIFT 3 #define RCC_CR_HSITRIM (0x1F << RCC_CR_HSITRIM_SHIFT) #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) /* --- RCC_CFGR values ----------------------------------------------------- */ #define RCC_CFGR_PLLNODIV (1 << 31) #define RCC_CFGR_MCOPRE_SHIFT 28 #define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_MCO_SHIFT 24 #define RCC_CFGR_MCO (7 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_NOCLK (0 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_HSI14 (1 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_LSI (2 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_LSE (3 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_HSI (5 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_HSE (6 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_PLL (7 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL2 (0x00 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL3 (0x01 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL4 (0x02 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL5 (0x03 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL6 (0x04 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL7 (0x05 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL8 (0x06 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL9 (0x06 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL10 (0x07 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL11 (0x08 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL12 (0x09 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL13 (0x0A << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL14 (0x0B << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL15 (0x0C << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL16 (0x0D << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLXTPRE (1<<17) #define RCC_CFGR_PLLSRC (1<<16) #define RCC_CFGR_ADCPRE (1<<14) #define RCC_CFGR_PPRE_SHIFT 8 #define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_NODIV (0 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV2 (4 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV4 (5 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV8 (6 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV16 (7 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE (0xf << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_NODIV (0x0 << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV2 (0x8 << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV4 (0x9 << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV8 (0xa << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV16 (0xb << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV64 (0xc << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV128 (0xd << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV256 (0xe << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV512 (0xf << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_SWS_SHIFT 2 #define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) #define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) #define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) #define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) #define RCC_CFGR_SW_SHIFT 0 #define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) #define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) #define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) #define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* --- RCC_CIR values ------------------------------------------------------ */ #define RCC_CIR_CSSC (1 << 23) #define RCC_CIR_HSI14RDYC (1 << 21) #define RCC_CIR_PLLRDYC (1 << 20) #define RCC_CIR_HSERDYC (1 << 19) #define RCC_CIR_HSIRDYC (1 << 18) #define RCC_CIR_LSERDYC (1 << 17) #define RCC_CIR_LSIRDYC (1 << 16) #define RCC_CIR_HSI14RDYIE (1 << 13) #define RCC_CIR_PLLRDYIE (1 << 12) #define RCC_CIR_HSERDYIE (1 << 11) #define RCC_CIR_HSIRDYIE (1 << 10) #define RCC_CIR_LSERDYIE (1 << 9) #define RCC_CIR_LSIRDYIE (1 << 8) #define RCC_CIR_CSSF (1 << 7) #define RCC_CIR_HSI14RDYF (1 << 5) #define RCC_CIR_PLLRDYF (1 << 4) #define RCC_CIR_HSERDYF (1 << 3) #define RCC_CIR_HSIRDYF (1 << 2) #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) /* --- RCC_APB2RSTR values ------------------------------------------------- */ #define RCC_APB2RSTR_DBGMCURST (1 << 22) #define RCC_APB2RSTR_TIM17RST (1 << 18) #define RCC_APB2RSTR_TIM16RST (1 << 17) #define RCC_APB2RSTR_TIM15RST (1 << 16) #define RCC_APB2RSTR_USART1RST (1 << 14) #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_TIM1RST (1 << 11) #define RCC_APB2RSTR_ADCRST (1 << 9) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* --- RCC_APB1RSTR values ------------------------------------------------- */ #define RCC_APB1RSTR_CECRST (1 << 30) #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) #define RCC_APB1RSTR_USART2RST (1 << 17) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_TIM14RST (1 << 8) #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) /* --- RCC_AHBENR values --------------------------------------------------- */ #define RCC_AHBENR_TSCEN (1 << 24) #define RCC_AHBENR_GPIOFEN (1 << 22) #define RCC_AHBENR_GPIODEN (1 << 20) #define RCC_AHBENR_GPIOCEN (1 << 19) #define RCC_AHBENR_GPIOBEN (1 << 18) #define RCC_AHBENR_GPIOAEN (1 << 17) #define RCC_AHBENR_CRCEN (1 << 6) #define RCC_AHBENR_FLTFEN (1 << 4) #define RCC_AHBENR_SRAMEN (1 << 2) #define RCC_AHBENR_DMAEN (1 << 0) /* --- RCC_APB2ENR values -------------------------------------------------- */ #define RCC_APB2ENR_DBGMCUEN (1 << 22) #define RCC_APB2ENR_TIM17EN (1 << 18) #define RCC_APB2ENR_TIM16EN (1 << 17) #define RCC_APB2ENR_TIM15EN (1 << 16) #define RCC_APB2ENR_USART1EN (1 << 14) #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_TIM1EN (1 << 11) #define RCC_APB2ENR_ADCEN (1 << 9) #define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0) /* --- RCC_APB1ENR values -------------------------------------------------- */ #define RCC_APB1ENR_CECEN (1 << 30) #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) #define RCC_APB1ENR_USART2EN (1 << 17) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_TIM14EN (1 << 8) #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /* --- RCC_BDCR values ----------------------------------------------------- */ #define RCC_BDCR_BDRST (1 << 16) #define RCC_BDCR_RTCEN (1 << 15) #define RCC_BDCR_RTCSEL_SHIFT 8 #define RCC_BDCR_RTCSEL (3 << RCC_BDCR_RTCSEL_SHIFT) #define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) #define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) #define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) #define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) #define RCC_BDCR_LSEDRV_SHIFT 3 #define RCC_BDCR_LSEDRV (3 << RCC_BDCR_LSEDRV_SHIFT) #define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) #define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) #define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) #define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) #define RCC_BDCR_LSEBYP (1 << 2) #define RCC_BDCR_LSERDY (1 << 1) #define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ #define RCC_CSR_LPWRRSTF (1 << 31) #define RCC_CSR_WWDGRSTF (1 << 30) #define RCC_CSR_IWDGRSTF (1 << 29) #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) #define RCC_CSR_OBLRSTF (1 << 25) #define RCC_CSR_RMVF (1 << 24) #define RCC_CSR_V18PWRRSTF (1 << 23) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) /* --- RCC_AHBRSTR values -------------------------------------------------- */ #define RCC_AHBRSTR_TSCRST (1 << 24) #define RCC_AHBRSTR_IOPFRST (1 << 22) #define RCC_AHBRSTR_IOPDRST (1 << 20) #define RCC_AHBRSTR_IOPCRST (1 << 19) #define RCC_AHBRSTR_IOPBRST (1 << 18) #define RCC_AHBRSTR_IOPARST (1 << 17) /* --- RCC_CFGR2 values ---------------------------------------------------- */ #define RCC_CFGR2_PREDIV 0xf #define RCC_CFGR2_PREDIV_NODIV 0x0 #define RCC_CFGR2_PREDIV_DIV2 0x1 #define RCC_CFGR2_PREDIV_DIV3 0x2 #define RCC_CFGR2_PREDIV_DIV4 0x3 #define RCC_CFGR2_PREDIV_DIV5 0x4 #define RCC_CFGR2_PREDIV_DIV6 0x5 #define RCC_CFGR2_PREDIV_DIV7 0x6 #define RCC_CFGR2_PREDIV_DIV8 0x7 #define RCC_CFGR2_PREDIV_DIV9 0x8 #define RCC_CFGR2_PREDIV_DIV10 0x9 #define RCC_CFGR2_PREDIV_DIV11 0xa #define RCC_CFGR2_PREDIV_DIV12 0xb #define RCC_CFGR2_PREDIV_DIV13 0xc #define RCC_CFGR2_PREDIV_DIV14 0xd #define RCC_CFGR2_PREDIV_DIV15 0xe #define RCC_CFGR2_PREDIV_DIV16 0xf /* --- RCC_CFGR3 values ---------------------------------------------------- */ #define RCC_CFGR3_ADCSW (1 << 8) #define RCC_CFGR3_CECSW (1 << 6) #define RCC_CFGR3_I2C1SW (1 << 4) #define RCC_CFGR3_USART1SW_SHIFT 0 #define RCC_CFGR3_USART1SW (3 << RCC_CFGR3_USART1SW_SHIFT) #define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) #define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) #define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) #define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) /* --- RCC_CFGR3 values ---------------------------------------------------- */ #define RCC_CR2_HSI14CAL_SHIFT 8 #define RCC_CR2_HSI14CAL (0xFF << RCC_CR2_HSI14CAL_SHIFT) #define RCC_CR2_HSI14TRIM_SHIFT 3 #define RCC_CR2_HSI14TRIM (31 << RCC_CR2_HSI14TRIM_SHIFT) #define RCC_CR2_HSI14DIS (1 << 2) #define RCC_CR2_HSI14RDY (1 << 1) #define RCC_CR2_HSI14ON (1 << 0) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /* --- Variable definitions ------------------------------------------------ */ extern uint32_t rcc_core_frequency; extern uint32_t rcc_ppre_frequency; enum rcc_osc { HSI14, HSI, HSE, PLL, LSI, LSE }; #define _REG_BIT(base, bit) (((base) << 5) + (bit)) enum rcc_periph_clken { /* AHB peripherals */ RCC_DMA = _REG_BIT(0x14, 0), RCC_SRAM = _REG_BIT(0x14, 2), RCC_FLTIF = _REG_BIT(0x14, 4), RCC_CRC = _REG_BIT(0x14, 6), RCC_GPIOA = _REG_BIT(0x14, 17), RCC_GPIOB = _REG_BIT(0x14, 18), RCC_GPIOC = _REG_BIT(0x14, 19), RCC_GPIOD = _REG_BIT(0x14, 20), RCC_GPIOF = _REG_BIT(0x14, 22), RCC_TSC = _REG_BIT(0x14, 24), /* APB2 peripherals */ RCC_SYSCFG_COMP = _REG_BIT(0x18, 0), RCC_ADC = _REG_BIT(0x18, 9), RCC_TIM1 = _REG_BIT(0x18, 11), RCC_SPI1 = _REG_BIT(0x18, 12), RCC_USART1 = _REG_BIT(0x18, 14), RCC_TIM15 = _REG_BIT(0x18, 16), RCC_TIM16 = _REG_BIT(0x18, 17), RCC_TIM17 = _REG_BIT(0x18, 18), RCC_DBGMCU = _REG_BIT(0x18, 22), /* APB1 peripherals */ RCC_TIM2 = _REG_BIT(0x1C, 0), RCC_TIM3 = _REG_BIT(0x1C, 1), RCC_TIM6 = _REG_BIT(0x1C, 4), RCC_TIM14 = _REG_BIT(0x1C, 8), RCC_WWDG = _REG_BIT(0x1C, 11), RCC_SPI2 = _REG_BIT(0x1C, 14), RCC_USART2 = _REG_BIT(0x1C, 17), RCC_I2C1 = _REG_BIT(0x1C, 21), RCC_I2C2 = _REG_BIT(0x1C, 22), RCC_PWR = _REG_BIT(0x1C, 28), RCC_DAC = _REG_BIT(0x1C, 29), RCC_CEC = _REG_BIT(0x1C, 30), /* Advanced peripherals */ RCC_RTC = _REG_BIT(0x20, 15),/* BDCR[15] */ }; enum rcc_periph_rst { /* APB2 peripherals */ RST_SYSCFG = _REG_BIT(0x0C, 0), RST_ADC = _REG_BIT(0x0C, 9), RST_TIM1 = _REG_BIT(0x0C, 11), RST_SPI1 = _REG_BIT(0x0C, 12), RST_USART1 = _REG_BIT(0x0C, 14), RST_TIM15 = _REG_BIT(0x0C, 16), RST_TIM16 = _REG_BIT(0x0C, 17), RST_TIM17 = _REG_BIT(0x0C, 18), RST_DBGMCU = _REG_BIT(0x0C, 22), /* APB1 peripherals */ RST_TIM2 = _REG_BIT(0x10, 0), RST_TIM3 = _REG_BIT(0x10, 1), RST_TIM6 = _REG_BIT(0x10, 4), RST_TIM14 = _REG_BIT(0x10, 8), RST_WWDG = _REG_BIT(0x10, 11), RST_SPI2 = _REG_BIT(0x10, 14), RST_USART2 = _REG_BIT(0x10, 17), RST_I2C1 = _REG_BIT(0x10, 21), RST_I2C2 = _REG_BIT(0x10, 22), RST_PWR = _REG_BIT(0x10, 28), RST_DAC = _REG_BIT(0x10, 29), RST_CEC = _REG_BIT(0x10, 30), /* Advanced peripherals */ RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */ /* AHB peripherals */ RST_GPIOA = _REG_BIT(0x28, 17), RST_GPIOB = _REG_BIT(0x28, 18), RST_GPIOC = _REG_BIT(0x28, 19), RST_GPIOD = _REG_BIT(0x28, 20), RST_GPIOF = _REG_BIT(0x28, 22), RST_TSC = _REG_BIT(0x28, 24), }; #undef _REG_BIT /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS void rcc_osc_ready_int_clear(enum rcc_osc osc); void rcc_osc_ready_int_enable(enum rcc_osc osc); void rcc_osc_ready_int_disable(enum rcc_osc osc); int rcc_osc_ready_int_flag(enum rcc_osc osc); void rcc_wait_for_osc_ready(enum rcc_osc osc); void rcc_osc_on(enum rcc_osc osc); void rcc_osc_off(enum rcc_osc osc); void rcc_osc_bypass_enable(enum rcc_osc osc); void rcc_osc_bypass_disable(enum rcc_osc osc); void rcc_css_enable(void); void rcc_css_disable(void); void rcc_css_int_clear(void); int rcc_css_int_flag(void); void rcc_set_sysclk_source(enum rcc_osc clk); void rcc_set_pll_multiplication_factor(uint32_t mul); void rcc_set_ppre(uint32_t ppre); void rcc_set_hpre(uint32_t hpre); void rcc_set_prediv(uint32_t prediv); void rcc_set_mco(uint32_t mcosrc); enum rcc_osc rcc_system_clock_source(void); void rcc_clock_setup_in_hsi_out_8mhz(void); void rcc_clock_setup_in_hsi_out_16mhz(void); void rcc_clock_setup_in_hsi_out_24mhz(void); void rcc_clock_setup_in_hsi_out_32mhz(void); void rcc_clock_setup_in_hsi_out_40mhz(void); void rcc_clock_setup_in_hsi_out_48mhz(void); void rcc_periph_clock_enable(enum rcc_periph_clken periph); void rcc_periph_clock_disable(enum rcc_periph_clken periph); void rcc_periph_reset_pulse(enum rcc_periph_rst periph); void rcc_periph_reset_hold(enum rcc_periph_rst periph); void rcc_periph_reset_release(enum rcc_periph_rst periph); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/rtc.h000066400000000000000000000021361435536612600233670ustar00rootroot00000000000000/** @defgroup rtc_defines RTC Defines * * @brief Defined Constants and Types for the STM32F0xx RTC * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 5 December 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RTC_H #define LIBOPENCM3_RTC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/spi.h000066400000000000000000000104111435536612600233650ustar00rootroot00000000000000/** @defgroup spi_defines SPI Defines * * @brief Defined Constants and Types for the STM32F0xx SPI * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SPI_H #define LIBOPENCM3_SPI_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ #define SPI1_BASE SPI1_I2S1_BASE /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* DFF: Data frame format */ /** @defgroup spi_dff SPI data frame format * @ingroup spi_defines * * @{*/ #define SPI_CR1_CRCL_8BIT (0 << 11) #define SPI_CR1_CRCL_16BIT (1 << 11) /**@}*/ #define SPI_CR1_CRCL (1 << 11) /* --- SPI_CR2 values ------------------------------------------------------ */ /* LDMA_TX: Last DMA transfer for transmission */ #define SPI_CR2_LDMA_TX (1 << 14) /* LDMA_RX: Last DMA transfer for reception */ #define SPI_CR2_LDMA_RX (1 << 13) /* FRXTH: FIFO reception threshold */ #define SPI_CR2_FRXTH (1 << 12) /* DS [3:0]: Data size */ /* 0x0 - 0x2 NOT USED */ #define SPI_CR2_DS_4BIT (0x3 << 8) #define SPI_CR2_DS_5BIT (0x4 << 8) #define SPI_CR2_DS_6BIT (0x5 << 8) #define SPI_CR2_DS_7BIT (0x6 << 8) #define SPI_CR2_DS_8BIT (0x7 << 8) #define SPI_CR2_DS_9BIT (0x8 << 8) #define SPI_CR2_DS_10BIT (0x9 << 8) #define SPI_CR2_DS_11BIT (0xA << 8) #define SPI_CR2_DS_12BIT (0xB << 8) #define SPI_CR2_DS_13BIT (0xC << 8) #define SPI_CR2_DS_14BIT (0xD << 8) #define SPI_CR2_DS_15BIT (0xE << 8) #define SPI_CR2_DS_16BIT (0xF << 8) #define SPI_CR2_DS_MASK (0xF << 8) /* NSSP: NSS pulse management */ #define SPI_CR2_NSSP (1 << 3) /* --- SPI_SR values ------------------------------------------------------- */ /* FTLVL[1:0]: FIFO Transmission Level */ #define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) #define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) #define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) #define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) /* FRLVL[1:0]: FIFO Reception Level */ #define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) #define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) #define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) #define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS void spi_set_data_size(uint32_t spi, uint16_t data_s); void spi_fifo_reception_threshold_8bit(uint32_t spi); void spi_fifo_reception_threshold_16bit(uint32_t spi); void spi_i2s_mode_spi_mode(uint32_t spi); void spi_send8(uint32_t spi, uint8_t data); uint8_t spi_read8(uint32_t spi); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/syscfg.h000066400000000000000000000101741435536612600240760ustar00rootroot00000000000000/** @defgroup syscfg_defines SYSCFG Defines * * @brief Defined Constants and Types for the STM32F0xx System Config * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SYSCFG_H #define LIBOPENCM3_SYSCFG_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define SYSCFG_CFGR1 MMIO32(SYSCFG_COMP_BASE + 0x00) #define SYSCFG_EXTICR(i) MMIO32(SYSCFG_COMP_BASE + 0x08 + (i)*4) #define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) #define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) #define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) #define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) #define SYSCFG_CFGR2 MMIO32(SYSCFG_COMP_BASE + 0x18) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* SYSCFG_CFGR1 Values -- ---------------------------------------------------*/ #define SYSCFG_CFGR1_MEM_MODE_SHIFT 0 #define SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) #define SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT) #define SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT) #define SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) #define SYSCFG_CFGR1_ADC_DMA_RMP (1 << 8) #define SYSCFG_CFGR1_USART1_TX_DMA_RMP (1 << 9) #define SYSCFG_CFGR1_USART1_RX_DMA_RMP (1 << 10) #define SYSCFG_CFGR1_TIM16_DMA_RMP (1 << 11) #define SYSCFG_CFGR1_TIM17_DMA_RMP (1 << 12) #define SYSCFG_CFGR1_I2C_PB6_FMPLUS (1 << 16) #define SYSCFG_CFGR1_I2C_PB7_FMPLUS (1 << 17) #define SYSCFG_CFGR1_I2C_PB8_FMPLUS (1 << 18) #define SYSCFG_CFGR1_I2C_PB9_FMPLUS (1 << 19) #define SYSCFG_CFGR1_I2C1_FMPLUS (1 << 20) #define SYSCFG_CFGR1_I2C_PA9_FMPLUS (1 << 22) #define SYSCFG_CFGR1_I2C_PA10_FMPLUS (1 << 23) /* SYSCFG_EXTICR Values -- --------------------------------------------------*/ #define SYSCFG_EXTICR_SKIP 4 #define SYSCFG_EXTICR_GPIOA 0 #define SYSCFG_EXTICR_GPIOB 1 #define SYSCFG_EXTICR_GPIOC 2 #define SYSCFG_EXTICR_GPIOD 3 #define SYSCFG_EXTICR_GPIOF 5 /* SYSCFG_CFGR2 Values -- ---------------------------------------------------*/ #define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0) #define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1) #define SYSCFG_CFGR2_PVD_LOCK (1 << 2) #define SYSCFG_CFGR2_SRAM_PEF (1 << 8) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/timer.h000066400000000000000000000020061435536612600237130ustar00rootroot00000000000000/** @defgroup timer_defines Timers Defines * * @brief Defined Constants and Types for the STM32F0xx Timers * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/tsc.h000066400000000000000000000131551435536612600233730ustar00rootroot00000000000000/** @defgroup tsc_defines TSC Defines * * @brief Defined Constants and Types for the STM32F0xx Touch Sensor * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_TSC_H #define LIBOPENCM3_TSC_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ #define TSC TSC_BASE /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define TSC_CR MMIO32(TSC_BASE + 0x00) #define TSC_IER MMIO32(TSC_BASE + 0x04) #define TSC_ICR MMIO32(TSC_BASE + 0x08) #define TSC_ISR MMIO32(TSC_BASE + 0x0c) #define TSC_IOHCR MMIO32(TSC_BASE + 0x10) #define TSC_IOASCR MMIO32(TSC_BASE + 0x18) #define TSC_IOSCR MMIO32(TSC_BASE + 0x20) #define TSC_IOCCR MMIO32(TSC_BASE + 0x28) #define TSC_IOGCSR MMIO32(TSC_BASE + 0x30) #define TSC_IOGxCR(x) MMIO8(TSC_BASE + 0x34 + (x)*4) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* TSC_CR Values ------------------------------------------------------------*/ #define TSC_CR_CTPH_SHIFT 28 #define TSC_CR_CTPH (0xF << TSC_CR_CTPH_SHIFT) #define TSC_CR_CTPL_SHIFT 24 #define TSC_CR_CTPL (0x0F << TSC_CR_CTPL_SHIFT) #define TSC_CR_SSD_SHIFT 17 #define TSC_CR_SSD (0x7F << TSC_CR_SSD_SHIFT) #define TSC_CR_SSE (1 << 16) #define TSC_CR_SSPSC (1 << 15) #define TSC_CR_PGPSC_SHIFT 12 #define TSC_CR_PGPSC (7 << TSC_CR_PGPSC_SHIFT) #define TSC_CR_MCV_SHIFT 5 #define TSC_CR_MCV (7 << TSC_CR_MCV_SHIFT) #define TSC_CR_IODEF (1 << 4) #define TSC_CR_SYNCPOL (1 << 3) #define TSC_CR_AM (1 << 2) #define TSC_CR_START (1 << 1) #define TSC_CR_TSCE (1 << 0) /* TSC_IER Values -----------------------------------------------------------*/ #define TSC_IER_MCEIE (1 << 1) #define TSC_IER_EOAIE (1 << 0) /* TSC_ICR Values -----------------------------------------------------------*/ #define TSC_ICR_MCEIC (1 << 1) #define TSC_ICR_EOAIC (1 << 0) /* TSC_ISR Values -----------------------------------------------------------*/ #define TSC_ISR_MCEF (1 << 1) #define TSC_ISR_EOAF (1 << 0) /* TSC_IOHCR Values ---------------------------------------------------------*/ /* Bit helper g = [1..6] io = [1..4] */ #define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4)) #define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io) #define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io) #define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io) #define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io) #define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io) #define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOASCR Values --------------------------------------------------------*/ #define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io) #define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io) #define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io) #define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io) #define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io) #define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOSCR Values ---------------------------------------------------------*/ #define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io) #define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io) #define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io) #define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io) #define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io) #define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOCCR Values ---------------------------------------------------------*/ #define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io) #define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io) #define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io) #define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io) #define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io) #define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io) /* TSC_IOGCSR Values --------------------------------------------------------*/ #define TSC_IOGCSR_GxE(x) (1 << ((x)-1)) #define TSC_IOGCSR_GxS(x) (1 << ((x)+15)) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f0/usart.h000066400000000000000000000266611435536612600237460ustar00rootroot00000000000000/** @defgroup usart_defines USART Defines * * @brief Defined Constants and Types for the STM32F0xx USART * * @ingroup STM32F0xx_defines * * @version 1.0.0 * * @date 2 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H #include #include /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ #define USART1 USART1_BASE #define USART2 USART2_BASE /*****************************************************************************/ /* Register definitions */ /*****************************************************************************/ #define USART_CR1(usart_base) MMIO32(usart_base + 0x00) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART_CR2(usart_base) MMIO32(usart_base + 0x04) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART_CR3(usart_base) MMIO32(usart_base + 0x08) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART_BRR(usart_base) MMIO32(usart_base + 0x0c) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) #define USART1_RTOR USART_RTOR(USART1_BASE) #define USART2_RTOR USART_RTOR(USART2_BASE) #define USART_RQR(usart_base) MMIO32(usart_base + 0x18) #define USART1_RQR USART_RQR(USART1_BASE) #define USART2_RQR USART_RQR(USART2_BASE) #define USART_ISR(usart_base) MMIO32(usart_base + 0x1c) #define USART1_ISR USART_ISR(USART1_BASE) #define USART2_ISR USART_ISR(USART2_BASE) #define USART_ICR(usart_base) MMIO32(usart_base + 0x20) #define USART1_ICR USART_ICR(USART1_BASE) #define USART2_ICR USART_ICR(USART2_BASE) #define USART_RDR(usart_base) MMIO8(usart_base + 0x24) #define USART1_RDR USART_RDR(USART1_BASE) #define USART2_RDR USART_RDR(USART2_BASE) #define USART_TDR(usart_base) MMIO8(usart_base + 0x28) #define USART1_TDR USART_TDR(USART1_BASE) #define USART2_TDR USART_TDR(USART2_BASE) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ /* USART_CR1 Values ---------------------------------------------------------*/ #define USART_CR1_EOBIE (1 << 27) #define USART_CR1_RTOIE (1 << 26) #define USART_CR1_DEAT_SHIFT 21 #define USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT) #define USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT) #define USART_CR1_DEDT_SHIFT 16 #define USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT) #define USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT) #define USART_CR1_OVER8 (1 << 15) #define USART_CR1_CMIE (1 << 14) #define USART_CR1_MME (1 << 13) #define USART_CR1_M (1 << 12) #define USART_CR1_WAKE (1 << 11) #define USART_CR1_PCE (1 << 10) #define USART_CR1_PS (1 << 9) #define USART_CR1_PEIE (1 << 8) #define USART_CR1_TXEIE (1 << 7) #define USART_CR1_TCIE (1 << 6) #define USART_CR1_RXNEIE (1 << 5) #define USART_CR1_IDLEIE (1 << 4) #define USART_CR1_TE (1 << 3) #define USART_CR1_RE (1 << 2) #define USART_CR1_UESM (1 << 1) #define USART_CR1_UE (1 << 0) /* USART_CR2 Values ---------------------------------------------------------*/ #define USART_CR2_ADD_SHIFT 24 #define USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT) #define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT) #define USART_CR2_RTOEN (1 << 23) #define USART_CR2_ABRMOD_SHIFT 21 #define USART_CR2_ABRMOD (3 << USART_CR2_ABRMOD_SHIFT) #define USART_CR2_ABRMOD_STARTBIT (0 << USART_CR2_ABRMOD_SHIFT) #define USART_CR2_ABRMOD_FALLTOFALL (1 << USART_CR2_ABRMOD_SHIFT) #define USART_CR2_ABREN (1 << 20) #define USART_CR2_MSBFIRST (1 << 19) #define USART_CR2_DATAINV (1 << 18) #define USART_CR2_TXINV (1 << 17) #define USART_CR2_RXINV (1 << 16) #define USART_CR2_SWAP (1 << 15) #define USART_CR2_LINEN (1 << 14) #define USART_CR2_STOP_SHIFT 12 #define USART_CR2_STOP (3 << USART_CR2_STOP_SHIFT) #define USART_CR2_STOP_1_0BIT (0 << USART_CR2_STOP_SHIFT) #define USART_CR2_STOP_2_0BIT (2 << USART_CR2_STOP_SHIFT) #define USART_CR2_STOP_1_5BIT (3 << USART_CR2_STOP_SHIFT) #define USART_CR2_CLKEN (1 << 11) #define USART_CR2_CPOL (1 << 10) #define USART_CR2_CPHA (1 << 9) #define USART_CR2_LBCL (1 << 8) #define USART_CR2_LBIDE (1 << 6) #define USART_CR2_LBDL (1 << 5) #define USART_CR2_ADDM (1 << 4) /* USART_CR3 Values ---------------------------------------------------------*/ #define USART_CR3_WUFIE (1 << 22) #define USART_CR3_WUS_SHIFT 20 #define USART_CR3_WUS (3 << USART_CR3_WUS_SHIFT) #define USART_CR3_WUS_ADDRMATCH (0 << USART_CR3_WUS_SHIFT) #define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) #define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) #define USART_CR3_SCARCNT_SHIFT 17 #define USART_CR3_SCARCNT (7 << USART_CR3_SCARCNT_SHIFT) #define USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT) #define USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT) #define USART_CR3_DEP (1 << 15) #define USART_CR3_DEM (1 << 14) #define USART_CR3_DDRE (1 << 13) #define USART_CR3_OVRDIS (1 << 12) #define USART_CR3_ONEBIT (1 << 11) #define USART_CR3_CTSIE (1 << 10) #define USART_CR3_CTSE (1 << 9) #define USART_CR3_RTSE (1 << 8) #define USART_CR3_DMAT (1 << 7) #define USART_CR3_DMAR (1 << 6) #define USART_CR3_SCEN (1 << 5) #define USART_CR3_NACK (1 << 4) #define USART_CR3_HDSEL (1 << 3) #define USART_CR3_IRLP (1 << 2) #define USART_CR3_IREN (1 << 1) #define USART_CR3_EIE (1 << 0) /* USART_GTPR Values --------------------------------------------------------*/ #define USART_GTPR_GT_SHIFT 8 #define USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT) #define USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT) #define USART_GTPR_PSC_SHIFT 0 #define USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT) #define USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT) /* USART_RTOR Values --------------------------------------------------------*/ #define USART_RTOR_BLEN_SHIFT 24 #define USART_RTOR_BLEN (0xFF << USART_RTOR_BLEN_SHIFT) #define USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT) #define USART_RTOR_RTO_SHIFT 0 #define USART_RTOR_RTO (0xFF << USART_RTOR_RTO_SHIFT) #define USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT) /* USART_RQR Values ---------------------------------------------------------*/ #define USART_RQR_TXFRQ (1 << 4) #define USART_RQR_RXFRQ (1 << 3) #define USART_RQR_MMRQ (1 << 2) #define USART_RQR_SBKRQ (1 << 1) #define USART_RQR_ABRRQ (1 << 0) /* USART_ISR Values ---------------------------------------------------------*/ #define USART_ISR_REACK (1 << 22) #define USART_ISR_TEACK (1 << 21) #define USART_ISR_WUF (1 << 20) #define USART_ISR_RWU (1 << 19) #define USART_ISR_SBKF (1 << 18) #define USART_ISR_CMF (1 << 17) #define USART_ISR_BUSY (1 << 16) #define USART_ISR_ABRF (1 << 15) #define USART_ISR_ABRE (1 << 14) #define USART_ISR_EOBF (1 << 12) #define USART_ISR_RTOF (1 << 11) #define USART_ISR_CTS (1 << 10) #define USART_ISR_CTSIF (1 << 9) #define USART_ISR_LBDF (1 << 8) #define USART_ISR_TXE (1 << 7) #define USART_ISR_TC (1 << 6) #define USART_ISR_RXNE (1 << 5) #define USART_ISR_IDLE (1 << 4) #define USART_ISR_ORE (1 << 3) #define USART_ISR_NF (1 << 2) #define USART_ISR_FE (1 << 1) #define USART_ISR_PE (1 << 0) /* USART_ICR Values ---------------------------------------------------------*/ #define USART_ICR_WUCF (1 << 20) #define USART_ICR_CMCF (1 << 17) #define USART_ICR_EOBCF (1 << 12) #define USART_ICR_RTOCF (1 << 11) #define USART_ICR_CTSCF (1 << 9) #define USART_ICR_LBDCF (1 << 8) #define USART_ICR_TCCF (1 << 6) #define USART_ICR_IDLECF (1 << 4) #define USART_ICR_ORECF (1 << 3) #define USART_ICR_NCF (1 << 2) #define USART_ICR_FECF (1 << 1) #define USART_ICR_PECF (1 << 0) /*****************************************************************************/ /* API definitions */ /*****************************************************************************/ #define USART_PARITY (USART_CR1_PCE | USART_CR1_PS) #define USART_PARITY_NONE (0) #define USART_PARITY_EVEN (USART_CR1_PCE) #define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) #define USART_MODE (USART_CR1_TE | USART_CR1_RE) #define USART_MODE_NONE (0) #define USART_MODE_RX (USART_CR1_RE) #define USART_MODE_TX (USART_CR1_TE) #define USART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) #define USART_FLOWCONTROL (USART_CR3_RTSE | USART_CR3_CTSE) #define USART_FLOWCONTROL_NONE (0) #define USART_FLOWCONTROL_RTS (USART_CR3_RTSE) #define USART_FLOWCONTROL_CTS (USART_CR3_CTSE) #define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*****************************************************************************/ /* API Functions */ /*****************************************************************************/ BEGIN_DECLS void usart_set_baudrate(uint32_t usart, uint32_t baud); void usart_set_databits(uint32_t usart, uint32_t bits); void usart_set_stopbits(uint32_t usart, uint32_t stopbits); void usart_set_parity(uint32_t usart, uint32_t parity); void usart_set_mode(uint32_t usart, uint32_t mode); void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol); void usart_enable(uint32_t usart); void usart_disable(uint32_t usart); void usart_send(uint32_t usart, uint8_t data); uint8_t usart_recv(uint32_t usart); void usart_wait_send_ready(uint32_t usart); void usart_wait_recv_ready(uint32_t usart); void usart_send_blocking(uint32_t usart, uint8_t data); uint8_t usart_recv_blocking(uint32_t usart); void usart_enable_rx_dma(uint32_t usart); void usart_disable_rx_dma(uint32_t usart); void usart_enable_tx_dma(uint32_t usart); void usart_disable_tx_dma(uint32_t usart); void usart_enable_rx_interrupt(uint32_t usart); void usart_disable_rx_interrupt(uint32_t usart); void usart_enable_tx_interrupt(uint32_t usart); void usart_disable_tx_interrupt(uint32_t usart); void usart_enable_error_interrupt(uint32_t usart); void usart_disable_error_interrupt(uint32_t usart); bool usart_get_flag(uint32_t usart, uint32_t flag); bool usart_get_interrupt_source(uint32_t usart, uint32_t flag); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/000077500000000000000000000000001435536612600224255ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/adc.h000066400000000000000000000633341435536612600233360ustar00rootroot00000000000000/** @defgroup adc_defines ADC Defines @brief Defined Constants and Types for the STM32F1xx Analog to Digital Converters @ingroup STM32F1xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Edward Cheeseman @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Edward Cheeseman * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H #include #include /* --- Convenience macros -------------------------------------------------- */ /* ADC port base addresses (for convenience) */ /****************************************************************************/ /** @defgroup adc_reg_base ADC register base addresses @ingroup adc_defines @{*/ #define ADC1 ADC1_BASE #define ADC2 ADC2_BASE #define ADC3 ADC3_BASE /**@}*/ /* --- ADC registers ------------------------------------------------------- */ /* ADC status register (ADC_SR) */ #define ADC_SR(block) MMIO32(block + 0x00) #define ADC1_SR ADC_SR(ADC1) #define ADC2_SR ADC_SR(ADC2) #define ADC3_SR ADC_SR(ADC3) /* ADC control register 1 (ADC_CR1) */ #define ADC_CR1(block) MMIO32(block + 0x04) #define ADC1_CR1 ADC_CR1(ADC1) #define ADC2_CR1 ADC_CR1(ADC2) #define ADC3_CR1 ADC_CR1(ADC3) /* ADC control register 2 (ADC_CR2) */ #define ADC_CR2(block) MMIO32(block + 0x08) #define ADC1_CR2 ADC_CR2(ADC1) #define ADC2_CR2 ADC_CR2(ADC2) #define ADC3_CR2 ADC_CR2(ADC3) /* ADC sample time register 1 (ADC_SMPR1) */ #define ADC_SMPR1(block) MMIO32(block + 0x0c) #define ADC1_SMPR1 ADC_SMPR1(ADC1) #define ADC2_SMPR1 ADC_SMPR1(ADC2) #define ADC3_SMPR1 ADC_SMPR1(ADC3) /* ADC sample time register 2 (ADC_SMPR2) */ #define ADC_SMPR2(block) MMIO32(block + 0x10) #define ADC1_SMPR2 ADC_SMPR2(ADC1) #define ADC2_SMPR2 ADC_SMPR2(ADC2) #define ADC3_SMPR2 ADC_SMPR2(ADC3) /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ #define ADC_JOFR1(block) MMIO32(block + 0x14) #define ADC_JOFR2(block) MMIO32(block + 0x18) #define ADC_JOFR3(block) MMIO32(block + 0x1c) #define ADC_JOFR4(block) MMIO32(block + 0x20) #define ADC1_JOFR1 ADC_JOFR1(ADC1) #define ADC2_JOFR1 ADC_JOFR1(ADC2) #define ADC3_JOFR1 ADC_JOFR1(ADC3) #define ADC1_JOFR2 ADC_JOFR2(ADC1) #define ADC2_JOFR2 ADC_JOFR2(ADC2) #define ADC3_JOFR2 ADC_JOFR2(ADC3) #define ADC1_JOFR3 ADC_JOFR3(ADC1) #define ADC2_JOFR3 ADC_JOFR3(ADC2) #define ADC3_JOFR3 ADC_JOFR3(ADC3) #define ADC1_JOFR4 ADC_JOFR4(ADC1) #define ADC2_JOFR4 ADC_JOFR4(ADC2) #define ADC3_JOFR4 ADC_JOFR4(ADC3) /* ADC watchdog high threshold register (ADC_HTR) */ #define ADC_HTR(block) MMIO32(block + 0x24) #define ADC1_HTR ADC_HTR(ADC1) #define ADC2_HTR ADC_HTR(ADC2) #define ADC3_HTR ADC_HTR(ADC3) /* ADC watchdog low threshold register (ADC_LTR) */ #define ADC_LTR(block) MMIO32(block + 0x28) #define ADC1_LTR ADC_LTR(ADC1_BASE) #define ADC2_LTR ADC_LTR(ADC2_BASE) #define ADC3_LTR ADC_LTR(ADC3_BASE) /* ADC regular sequence register 1 (ADC_SQR1) */ #define ADC_SQR1(block) MMIO32(block + 0x2c) #define ADC1_SQR1 ADC_SQR1(ADC1) #define ADC2_SQR1 ADC_SQR1(ADC2) #define ADC3_SQR1 ADC_SQR1(ADC3) /* ADC regular sequence register 2 (ADC_SQR2) */ #define ADC_SQR2(block) MMIO32(block + 0x30) #define ADC1_SQR2 ADC_SQR2(ADC1) #define ADC2_SQR2 ADC_SQR2(ADC2) #define ADC3_SQR2 ADC_SQR2(ADC3) /* ADC regular sequence register 3 (ADC_SQR3) */ #define ADC_SQR3(block) MMIO32(block + 0x34) #define ADC1_SQR3 ADC_SQR3(ADC1) #define ADC2_SQR3 ADC_SQR3(ADC2) #define ADC3_SQR3 ADC_SQR3(ADC3) /* ADC injected sequence register (ADC_JSQR) */ #define ADC_JSQR(block) MMIO32(block + 0x38) #define ADC1_JSQR ADC_JSQR(ADC1_BASE) #define ADC2_JSQR ADC_JSQR(ADC2_BASE) #define ADC3_JSQR ADC_JSQR(ADC3_BASE) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ #define ADC_JDR1(block) MMIO32(block + 0x3c) #define ADC_JDR2(block) MMIO32(block + 0x40) #define ADC_JDR3(block) MMIO32(block + 0x44) #define ADC_JDR4(block) MMIO32(block + 0x48) #define ADC1_JDR1 ADC_JDR1(ADC1) #define ADC2_JDR1 ADC_JDR1(ADC2) #define ADC3_JDR1 ADC_JDR1(ADC3) #define ADC1_JDR2 ADC_JDR2(ADC1) #define ADC2_JDR2 ADC_JDR2(ADC2) #define ADC3_JDR2 ADC_JDR2(ADC3) #define ADC1_JDR3 ADC_JDR3(ADC1) #define ADC2_JDR3 ADC_JDR3(ADC2) #define ADC3_JDR3 ADC_JDR3(ADC3) #define ADC1_JDR4 ADC_JDR4(ADC1) #define ADC2_JDR4 ADC_JDR4(ADC2) #define ADC3_JDR4 ADC_JDR4(ADC3) /* ADC regular data register (ADC_DR) */ #define ADC_DR(block) MMIO32(block + 0x4c) #define ADC1_DR ADC_DR(ADC1) #define ADC2_DR ADC_DR(ADC2) #define ADC3_DR ADC_DR(ADC3) /* --- ADC Channels ------------------------------------------------------- */ /****************************************************************************/ /** @defgroup adc_channel ADC Channel Numbers @ingroup adc_defines @{*/ #define ADC_CHANNEL0 0x00 #define ADC_CHANNEL1 0x01 #define ADC_CHANNEL2 0x02 #define ADC_CHANNEL3 0x03 #define ADC_CHANNEL4 0x04 #define ADC_CHANNEL5 0x05 #define ADC_CHANNEL6 0x06 #define ADC_CHANNEL7 0x07 #define ADC_CHANNEL8 0x08 #define ADC_CHANNEL9 0x09 #define ADC_CHANNEL10 0x0A #define ADC_CHANNEL11 0x0B #define ADC_CHANNEL12 0x0C #define ADC_CHANNEL13 0x0D #define ADC_CHANNEL14 0x0E #define ADC_CHANNEL15 0x0F #define ADC_CHANNEL16 0x10 #define ADC_CHANNEL17 0x11 /**@}*/ #define ADC_MASK 0x1F #define ADC_SHIFT 0 /* --- ADC_SR values ------------------------------------------------------- */ #define ADC_SR_STRT (1 << 4) #define ADC_SR_JSTRT (1 << 3) #define ADC_SR_JEOC (1 << 2) #define ADC_SR_EOC (1 << 1) #define ADC_SR_AWD (1 << 0) /* --- ADC_CR1 values ------------------------------------------------------ */ /* AWDEN: Analog watchdog enable on regular channels */ #define ADC_CR1_AWDEN (1 << 23) /* JAWDEN: Analog watchdog enable on injected channels */ #define ADC_CR1_JAWDEN (1 << 22) /* Note: Bits [21:20] are reserved, and must be kept at reset value. */ /* DUALMOD[3:0]: Dual mode selection. (ADC1 only) */ /* Legend: * IND: Independent mode. * CRSISM: Combined regular simultaneous + injected simultaneous mode. * CRSATM: Combined regular simultaneous + alternate trigger mode. * CISFIM: Combined injected simultaneous + fast interleaved mode. * CISSIM: Combined injected simultaneous + slow interleaved mode. * ISM: Injected simultaneous mode only. * RSM: Regular simultaneous mode only. * FIM: Fast interleaved mode only. * SIM: Slow interleaved mode only. * ATM: Alternate trigger mode only. */ /****************************************************************************/ /* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */ /** @defgroup adc_cr1_dualmod ADC Mode Selection @ingroup adc_defines @{*/ /** Independent (non-dual) mode */ #define ADC_CR1_DUALMOD_IND (0x0 << 16) /** Combined regular simultaneous + injected simultaneous mode. */ #define ADC_CR1_DUALMOD_CRSISM (0x1 << 16) /** Combined regular simultaneous + alternate trigger mode. */ #define ADC_CR1_DUALMOD_CRSATM (0x2 << 16) /** Combined injected simultaneous + fast interleaved mode. */ #define ADC_CR1_DUALMOD_CISFIM (0x3 << 16) /** Combined injected simultaneous + slow interleaved mode. */ #define ADC_CR1_DUALMOD_CISSIM (0x4 << 16) /** Injected simultaneous mode only. */ #define ADC_CR1_DUALMOD_ISM (0x5 << 16) /** Regular simultaneous mode only. */ #define ADC_CR1_DUALMOD_RSM (0x6 << 16) /** Fast interleaved mode only. */ #define ADC_CR1_DUALMOD_FIM (0x7 << 16) /** Slow interleaved mode only. */ #define ADC_CR1_DUALMOD_SIM (0x8 << 16) /** Alternate trigger mode only. */ #define ADC_CR1_DUALMOD_ATM (0x9 << 16) /**@}*/ #define ADC_CR1_DUALMOD_MASK (0xF << 16) #define ADC_CR1_DUALMOD_SHIFT 16 /* DISCNUM[2:0]: Discontinuous mode channel count. */ /****************************************************************************/ /** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. @ingroup adc_defines @{*/ #define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) #define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) #define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) #define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13) #define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13) #define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13) #define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13) #define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) /**@}*/ #define ADC_CR1_DISCNUM_MASK (0x7 << 13) #define ADC_CR1_DISCNUM_SHIFT 13 /* JDISCEN: */ /** Discontinuous mode on injected channels. */ #define ADC_CR1_JDISCEN (1 << 12) /* DISCEN: */ /** Discontinuous mode on regular channels. */ #define ADC_CR1_DISCEN (1 << 11) /* JAUTO: */ /** Automatic Injection Group conversion. */ #define ADC_CR1_JAUTO (1 << 10) /* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */ #define ADC_CR1_AWDSGL (1 << 9) /* SCAN: */ /** Scan mode. */ #define ADC_CR1_SCAN (1 << 8) /* JEOCIE: */ /** Interrupt enable for injected channels. */ #define ADC_CR1_JEOCIE (1 << 7) /* AWDIE: */ /** Analog watchdog interrupt enable. */ #define ADC_CR1_AWDIE (1 << 6) /* EOCIE: */ /** Interrupt enable EOC. */ #define ADC_CR1_EOCIE (1 << 5) /* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ /* Notes: * ADC1: Analog channel 16 and 17 are internally connected to the temperature * sensor and V_REFINT, respectively. * ADC2: Analog channel 16 and 17 are internally connected to V_SS. * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS. */ /****************************************************************************/ /* ADC_CR1 AWDCH[4:0] ADC watchdog channel */ /** @defgroup adc_watchdog_channel ADC watchdog channel @ingroup adc_defines @{*/ #define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) #define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) #define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) #define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0) #define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0) #define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0) #define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0) #define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0) #define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0) #define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0) #define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0) #define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0) #define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0) #define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0) #define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0) #define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0) #define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0) #define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) /**@}*/ #define ADC_CR1_AWDCH_MASK (0x1F << 0) #define ADC_CR1_AWDCH_SHIFT 0 /* --- ADC_CR2 values ------------------------------------------------------ */ /* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */ #define ADC_CR2_TSVREFE (1 << 23) /* SWSTART: */ /** Start conversion of regular channels. */ #define ADC_CR2_SWSTART (1 << 22) /* JSWSTART: */ /** Start conversion of injected channels. */ #define ADC_CR2_JSWSTART (1 << 21) /* EXTTRIG: */ /** External trigger conversion mode for regular channels. */ #define ADC_CR2_EXTTRIG (1 << 20) /* EXTSEL[2:0]: External event select for regular group. */ /* The following are only valid for ADC1 and ADC2. */ /****************************************************************************/ /* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */ /** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2 @ingroup adc_defines @{*/ /** Timer 1 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17) /** Timer 1 Compare Output 2 */ #define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17) /** Timer 1 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) /** Timer 2 Compare Output 2 */ #define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17) /** Timer 3 Trigger Output */ #define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17) /** Timer 4 Compare Output 4 */ #define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17) /** External Interrupt 11 */ #define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17) /** Software Trigger */ #define ADC_CR2_EXTSEL_SWSTART (0x7 << 17) /**@}*/ /* The following are only valid for ADC3 */ /****************************************************************************/ /* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */ /** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3 @ingroup adc_defines @{*/ /** Timer 2 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17) /** Timer 2 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17) /** Timer 1 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) /** Timer 8 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17) /** Timer 8 Trigger Output */ #define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17) /** Timer 5 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17) /** Timer 5 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17) /**@}*/ #define ADC_CR2_EXTSEL_MASK (0x7 << 17) #define ADC_CR2_EXTSEL_SHIFT 17 /* Note: Bit 16 is reserved, must be kept at reset value. */ /* JEXTTRIG: External trigger conversion mode for injected channels. */ #define ADC_CR2_JEXTTRIG (1 << 15) /* JEXTSEL[2:0]: External event selection for injected group. */ /* The following are only valid for ADC1 and ADC2. */ /****************************************************************************/ /* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */ /** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2 @ingroup adc_defines @{*/ /** Timer 1 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) /** Timer 1 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) /** Timer 2 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12) /** Timer 2 Compare Output 1 */ #define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12) /** Timer 3 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12) /** Timer 4 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12) /** External Interrupt 15 */ #define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12) /** Injected Software Trigger */ #define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ /**@}*/ /* The following are the different meanings for ADC3 only. */ /****************************************************************************/ /* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */ /** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3 @ingroup adc_defines @{*/ /** Timer 1 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) /** Timer 1 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) /** Timer 4 Compare Output 3 */ #define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12) /** Timer 8 Compare Output 2 */ #define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12) /** Timer 8 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12) /** Timer 5 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12) /** Timer 5 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12) /** Injected Software Trigger */ #define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ /**@}*/ #define ADC_CR2_JEXTSEL_MASK (0x7 << 12) #define ADC_CR2_JEXTSEL_SHIFT 12 /* ALIGN: Data alignment. */ #define ADC_CR2_ALIGN_RIGHT (0 << 11) #define ADC_CR2_ALIGN_LEFT (1 << 11) #define ADC_CR2_ALIGN (1 << 11) /* Note: Bits [10:9] are reserved and must be kept at reset value. */ /* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ #define ADC_CR2_DMA (1 << 8) /* Note: Bits [7:4] are reserved and must be kept at reset value. */ /* RSTCAL: Reset calibration. */ #define ADC_CR2_RSTCAL (1 << 3) /* CAL: A/D Calibration. */ #define ADC_CR2_CAL (1 << 2) /* CONT: Continous conversion. */ #define ADC_CR2_CONT (1 << 1) /* ADON: A/D converter On/Off. */ /* Note: If any other bit in this register apart from ADON is changed at the * same time, then conversion is not triggered. This is to prevent triggering * an erroneous conversion. * Conclusion: Must be separately written. */ #define ADC_CR2_ADON (1 << 0) /* --- ADC_SMPR1 values ---------------------------------------------------- */ #define ADC_SMPR1_SMP17_LSB 21 #define ADC_SMPR1_SMP16_LSB 18 #define ADC_SMPR1_SMP15_LSB 15 #define ADC_SMPR1_SMP14_LSB 12 #define ADC_SMPR1_SMP13_LSB 9 #define ADC_SMPR1_SMP12_LSB 6 #define ADC_SMPR1_SMP11_LSB 3 #define ADC_SMPR1_SMP10_LSB 0 #define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) #define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) #define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) #define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) #define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) #define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) #define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) #define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) /* --- ADC_SMPR2 values ---------------------------------------------------- */ #define ADC_SMPR2_SMP9_LSB 27 #define ADC_SMPR2_SMP8_LSB 24 #define ADC_SMPR2_SMP7_LSB 21 #define ADC_SMPR2_SMP6_LSB 18 #define ADC_SMPR2_SMP5_LSB 15 #define ADC_SMPR2_SMP4_LSB 12 #define ADC_SMPR2_SMP3_LSB 9 #define ADC_SMPR2_SMP2_LSB 6 #define ADC_SMPR2_SMP1_LSB 3 #define ADC_SMPR2_SMP0_LSB 0 #define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) #define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) #define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) #define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) #define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) #define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) #define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) #define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) #define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) #define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) /* --- ADC_SMPRx values --------------------------------------------------- */ /****************************************************************************/ /* ADC_SMPRG ADC Sample Time Selection for Channels */ /** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels @ingroup adc_defines @{*/ #define ADC_SMPR_SMP_1DOT5CYC 0x0 #define ADC_SMPR_SMP_7DOT5CYC 0x1 #define ADC_SMPR_SMP_13DOT5CYC 0x2 #define ADC_SMPR_SMP_28DOT5CYC 0x3 #define ADC_SMPR_SMP_41DOT5CYC 0x4 #define ADC_SMPR_SMP_55DOT5CYC 0x5 #define ADC_SMPR_SMP_71DOT5CYC 0x6 #define ADC_SMPR_SMP_239DOT5CYC 0x7 /**@}*/ /* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ #define ADC_JOFFSET_LSB 0 #define ADC_JOFFSET_MSK (0x7ff << 0) #define ADC_HT_LSB 0 #define ADC_HT_MSK (0x7ff << 0) #define ADC_LT_LSB 0 #define ADC_LT_MSK (0x7ff << 0) /* --- ADC_SQR1 values ----------------------------------------------------- */ #define ADC_SQR1_L_LSB 20 #define ADC_SQR1_SQ16_LSB 15 #define ADC_SQR1_SQ15_LSB 10 #define ADC_SQR1_SQ14_LSB 5 #define ADC_SQR1_SQ13_LSB 0 #define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) #define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) #define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) #define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) #define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) /* --- ADC_SQR2 values ----------------------------------------------------- */ #define ADC_SQR2_SQ12_LSB 25 #define ADC_SQR2_SQ11_LSB 20 #define ADC_SQR2_SQ10_LSB 15 #define ADC_SQR2_SQ9_LSB 10 #define ADC_SQR2_SQ8_LSB 5 #define ADC_SQR2_SQ7_LSB 0 #define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) #define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) #define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) #define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) #define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) #define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) /* --- ADC_SQR3 values ----------------------------------------------------- */ #define ADC_SQR3_SQ6_LSB 25 #define ADC_SQR3_SQ5_LSB 20 #define ADC_SQR3_SQ4_LSB 15 #define ADC_SQR3_SQ3_LSB 10 #define ADC_SQR3_SQ2_LSB 5 #define ADC_SQR3_SQ1_LSB 0 #define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) #define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) #define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) #define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) #define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) #define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) /* --- ADC_JSQR values ----------------------------------------------------- */ #define ADC_JSQR_JL_LSB 20 #define ADC_JSQR_JSQ4_LSB 15 #define ADC_JSQR_JSQ3_LSB 10 #define ADC_JSQR_JSQ2_LSB 5 #define ADC_JSQR_JSQ1_LSB 0 /* JL[2:0]: Discontinuous mode channel count injected channels. */ /****************************************************************************/ /** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode from injected channels. @ingroup adc_defines @{*/ #define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) /**@}*/ #define ADC_JSQR_JL_SHIFT 13 #define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) #define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ #define ADC_JDATA_LSB 0 #define ADC_DATA_LSB 0 #define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ #define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) #define ADC_DATA_MSK (0xffff << ADC_DA) #define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) /* ADC1 only (dual mode) */ /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void adc_power_on(uint32_t adc); void adc_start_conversion_direct(uint32_t adc); void adc_set_single_channel(uint32_t adc, uint8_t channel); void adc_set_dual_mode(uint32_t mode); bool adc_eoc(uint32_t adc); bool adc_eoc_injected(uint32_t adc); uint32_t adc_read_regular(uint32_t adc); uint32_t adc_read_injected(uint32_t adc, uint8_t reg); void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); void adc_enable_analog_watchdog_regular(uint32_t adc); void adc_disable_analog_watchdog_regular(uint32_t adc); void adc_enable_analog_watchdog_injected(uint32_t adc); void adc_disable_analog_watchdog_injected(uint32_t adc); void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); void adc_disable_discontinuous_mode_regular(uint32_t adc); void adc_enable_discontinuous_mode_injected(uint32_t adc); void adc_disable_discontinuous_mode_injected(uint32_t adc); void adc_enable_automatic_injected_group_conversion(uint32_t adc); void adc_disable_automatic_injected_group_conversion(uint32_t adc); void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel); void adc_enable_scan_mode(uint32_t adc); void adc_disable_scan_mode(uint32_t adc); void adc_enable_eoc_interrupt_injected(uint32_t adc); void adc_disable_eoc_interrupt_injected(uint32_t adc); void adc_enable_awd_interrupt(uint32_t adc); void adc_disable_awd_interrupt(uint32_t adc); void adc_enable_eoc_interrupt(uint32_t adc); void adc_disable_eoc_interrupt(uint32_t adc); void adc_enable_temperature_sensor(uint32_t adc); void adc_disable_temperature_sensor(uint32_t adc); void adc_start_conversion_regular(uint32_t adc); void adc_start_conversion_injected(uint32_t adc); void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger); void adc_disable_external_trigger_regular(uint32_t adc); void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger); void adc_disable_external_trigger_injected(uint32_t adc); void adc_set_left_aligned(uint32_t adc); void adc_set_right_aligned(uint32_t adc); void adc_enable_dma(uint32_t adc); void adc_disable_dma(uint32_t adc); void adc_reset_calibration(uint32_t adc); void adc_calibration(uint32_t adc); void adc_set_continuous_conversion_mode(uint32_t adc); void adc_set_single_conversion_mode(uint32_t adc); void adc_on(uint32_t adc) LIBOPENCM3_DEPRECATED("will be removed in the first release"); void adc_off(uint32_t adc); void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold); void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold); void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); void adc_set_continous_conversion_mode(uint32_t adc) LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode"); void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time"); void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels"); void adc_enable_jeoc_interrupt(uint32_t adc) LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected"); void adc_disable_jeoc_interrupt(uint32_t adc) LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected"); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/bkp.h000066400000000000000000000143261435536612600233600ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_BKP_H #define LIBOPENCM3_BKP_H #include #include /* --- BKP registers ------------------------------------------------------- */ /* Backup data register 1 (BKP_DR1) */ #define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) /* Backup data register 2 (BKP_DR2) */ #define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) /* Backup data register 3 (BKP_DR3) */ #define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) /* Backup data register 4 (BKP_DR4) */ #define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) /* Backup data register 5 (BKP_DR5) */ #define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) /* Backup data register 6 (BKP_DR6) */ #define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) /* Backup data register 7 (BKP_DR7) */ #define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) /* Backup data register 8 (BKP_DR8) */ #define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) /* Backup data register 9 (BKP_DR9) */ #define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) /* Backup data register 10 (BKP_DR10) */ #define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) /* RTC clock calibration register (BKP_RTCCR) */ #define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) /* Backup control register (BKP_CR) */ #define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) /* Backup control/status register (BKP_CSR) */ #define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) /* Backup data register 11 (BKP_DR11) */ #define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) /* Backup data register 12 (BKP_DR12) */ #define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) /* Backup data register 13 (BKP_DR13) */ #define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) /* Backup data register 14 (BKP_DR14) */ #define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) /* Backup data register 15 (BKP_DR15) */ #define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) /* Backup data register 16 (BKP_DR16) */ #define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) /* Backup data register 17 (BKP_DR17) */ #define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) /* Backup data register 18 (BKP_DR18) */ #define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) /* Backup data register 19 (BKP_DR19) */ #define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) /* Backup data register 20 (BKP_DR20) */ #define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) /* Backup data register 21 (BKP_DR21) */ #define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) /* Backup data register 22 (BKP_DR22) */ #define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) /* Backup data register 23 (BKP_DR23) */ #define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) /* Backup data register 24 (BKP_DR24) */ #define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) /* Backup data register 25 (BKP_DR25) */ #define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) /* Backup data register 26 (BKP_DR26) */ #define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) /* Backup data register 27 (BKP_DR27) */ #define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) /* Backup data register 28 (BKP_DR28) */ #define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) /* Backup data register 29 (BKP_DR29) */ #define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) /* Backup data register 30 (BKP_DR30) */ #define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) /* Backup data register 31 (BKP_DR31) */ #define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) /* Backup data register 32 (BKP_DR32) */ #define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) /* Backup data register 33 (BKP_DR33) */ #define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) /* Backup data register 34 (BKP_DR34) */ #define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) /* Backup data register 35 (BKP_DR35) */ #define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) /* Backup data register 36 (BKP_DR36) */ #define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) /* Backup data register 37 (BKP_DR37) */ #define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) /* Backup data register 38 (BKP_DR38) */ #define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) /* Backup data register 39 (BKP_DR39) */ #define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) /* Backup data register 40 (BKP_DR40) */ #define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) /* Backup data register 41 (BKP_DR41) */ #define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) /* Backup data register 42 (BKP_DR42) */ #define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) /* --- BKP_RTCCR values ---------------------------------------------------- */ /* ASOS: Alarm or second output selection */ #define BKP_RTCCR_ASOS (1 << 9) /* ASOE: Alarm or second output enable */ #define BKP_RTCCR_ASOE (1 << 8) /* CCO: Calibration clock output */ #define BKP_RTCCR_CCO (1 << 7) /* CAL[6:0]: Calibration value */ #define BKP_RTCCR_CAL_LSB 0 /* --- BKP_CR values ------------------------------------------------------- */ /* TPAL: TAMPER pin active level */ #define BKP_CR_TAL (1 << 1) /* TPE: TAMPER pin enable */ #define BKP_CR_TPE (1 << 0) /* --- BKP_CSR values ------------------------------------------------------ */ /* TIF: Tamper interrupt flag */ #define BKP_CSR_TIF (1 << 9) /* TEF: Tamper event flag */ #define BKP_CSR_TEF (1 << 8) /* TPIE: TAMPER pin interrupt enable */ #define BKP_CSR_TPIE (1 << 2) /* CTI: Clear tamper interrupt */ #define BKP_CSR_CTI (1 << 1) /* CTE: Clear tamper event */ #define BKP_CSR_CTE (1 << 0) /* --- BKP_DRx values ------------------------------------------------------ */ /* Bits[15:0]: Backup data */ /* --- BKP function prototypes --------------------------------------------- */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/crc.h000066400000000000000000000022171435536612600233470ustar00rootroot00000000000000/** @defgroup crc_defines CRC Defines @brief libopencm3 Defined Constants and Types for the STM32F1xx CRC Generator @ingroup STM32F1xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRC_H #define LIBOPENCM3_CRC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/dac.h000066400000000000000000000021031435536612600233210ustar00rootroot00000000000000/** @defgroup dac_defines DAC Defines @brief Defined Constants and Types for the STM32F1xx DAC @ingroup STM32F1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DAC_H #define LIBOPENCM3_DAC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/dma.h000066400000000000000000000021131435536612600233340ustar00rootroot00000000000000/** @defgroup dma_defines DMA Defines @ingroup STM32F1xx_defines @brief Defined Constants and Types for the STM32F1xx DMA Controller @version 1.0.0 @date 30 November 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DMA_H #define LIBOPENCM3_DMA_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/doc-stm32f1.h000066400000000000000000000010411435536612600245340ustar00rootroot00000000000000/** @mainpage libopencm3 STM32F1 @version 1.0.0 @date 7 September 2012 API documentation for ST Microelectronics STM32F1 Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F1xx STM32F1xx Libraries for ST Microelectronics STM32F1xx series. @version 1.0.0 @date 7 September 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F1xx_defines STM32F1xx Defines @brief Defined Constants and Types for the STM32F1xx series @version 1.0.0 @date 7 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/ethernet.h000066400000000000000000000177571435536612600244350ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_ETHERNET_H #define LIBOPENCM3_ETHERNET_H #include #include /* Ethernet MAC registers */ #define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) #define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) #define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) #define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) #define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) #define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) #define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) #define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) #define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) #define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) #define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) #define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) #define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40) #define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44) #define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48) #define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C) #define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50) #define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54) #define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58) #define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C) /* Ethernet MMC registers */ #define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) #define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) #define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) #define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) #define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) #define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) #define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) #define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) #define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) #define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) #define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) /* Ethrenet IEEE 1588 time stamp registers */ #define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) #define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) #define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) #define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) #define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) #define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) #define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) #define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) #define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) /* Ethernet DMA registers */ #define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) #define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) #define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) #define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) #define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) #define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) #define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) #define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) #define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) #define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) #define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) #define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) #define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) #define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) /* Ethernet MAC Register bit definitions */ /* Ethernet MAC configuration register ETH_MACCR bits */ #define ETH_MACCR_RE 0x00000004 #define ETH_MACCR_TE 0x00000008 #define ETH_MACCR_DC 0x00000010 #define ETH_MACCR_BL 0x00000060 #define ETH_MACCR_APCS 0x00000080 #define ETH_MACCR_RD 0x00000200 #define ETH_MACCR_IPCO 0x00000400 #define ETH_MACCR_DM 0x00000800 #define ETH_MACCR_LM 0x00001000 #define ETH_MACCR_ROD 0x00002000 #define ETH_MACCR_FES 0x00004000 #define ETH_MACCR_CSD 0x00010000 #define ETH_MACCR_IFG 0x000E0000 #define ETH_MACCR_JD 0x00400000 #define ETH_MACCR_WD 0x00800000 /* Ethernet MAC frame filter register ETH_MACFFR bits */ #define ETH_MACFFR_PM 0x00000001 #define ETH_MACFFR_HU 0x00000002 #define ETH_MACFFR_HM 0x00000004 #define ETH_MACFFR_DAIF 0x00000008 #define ETH_MACFFR_PAM 0x00000010 #define ETH_MACFFR_BFD 0x00000020 #define ETH_MACFFR_PCF 0x000000C0 #define ETH_MACFFR_SAIF 0x00000100 #define ETH_MACFFR_SAF 0x00000200 #define ETH_MACFFR_HPF 0x00000400 #define ETH_MACFFR_PA 0x80000000 /* Ethernet MAC MII address register ETH_MACMIIAR bits */ #define ETH_MACMIIAR_MB 0x0001 #define ETH_MACMIIAR_MW 0x0002 /* Clock Range for MDC frequency */ #define ETH_MACMIIAR_CR_MASK 0x001C #define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */ #define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */ #define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */ #define ETH_MACMIIAR_MR 0x07C0 #define ETH_MACMIIAR_PA 0xF800 /* Ethernet MAC flow control register ETH_MACFCR bits */ #define ETH_MACFCR_FCB 0x00000001 #define ETH_MACFCR_BPA 0x00000001 #define ETH_MACFCR_TFCE 0x00000002 #define ETH_MACFCR_RFCE 0x00000004 #define ETH_MACFCR_UPFD 0x00000008 #define ETH_MACFCR_PLT 0x00000030 #define ETH_MACFCR_ZQPD 0x00000080 #define ETH_MACFCR_PT 0xFFFF0000 /* Ethernet MAC interrupt status register ETH_MACSR bits */ #define ETH_MACSR_PMTS 0x0008 #define ETH_MACSR_MMCS 0x0010 #define ETH_MACSR_MMCRS 0x0020 #define ETH_MACSR_MMCTS 0x0040 #define ETH_MACSR_TSTS 0x0200 /* Ethernet MAC interrupt mask register ETH_MACIMR bits */ #define ETH_MACIMR_PMTIM 0x0008 #define ETH_MACIMR_TSTIM 0x0200 /* Ethernet DMA Register bit definitions */ /* Ethernet DMA bus mode register ETH_DMABMR bits */ #define ETH_DMABMR_SR 0x00000001 #define ETH_DMABMR_DA 0x00000002 #define ETH_DMABMR_DSL_MASK 0x0000007C #define ETH_DMABMR_PBL_MASK 0x00003F00 #define ETH_DMABMR_RTPR_MASK 0x0000C000 #define ETH_DMABMR_RTPR_1TO1 0x00000000 #define ETH_DMABMR_RTPR_2TO1 0x00004000 #define ETH_DMABMR_RTPR_3TO1 0x00008000 #define ETH_DMABMR_RTPR_4TO1 0x0000C000 #define ETH_DMABMR_FB 0x00010000 #define ETH_DMABMR_RDP_MASK 0x007E0000 #define ETH_DMABMR_USP 0x00800000 #define ETH_DMABMR_FPM 0x01000000 #define ETH_DMABMR_AAB 0x02000000 /* Ethernet DMA operation mode register ETH_DMAOMR bits */ #define ETH_DMAOMR_SR 0x00000002 #define ETH_DMAOMR_OSF 0x00000004 #define ETH_DMAOMR_RTC_MASK 0x00000018 #define ETH_DMAOMR_RTC_64 0x00000000 #define ETH_DMAOMR_RTC_32 0x00000008 #define ETH_DMAOMR_RTC_96 0x00000010 #define ETH_DMAOMR_RTC_128 0x00000018 #define ETH_DMAOMR_FUGF 0x00000040 #define ETH_DMAOMR_FEF 0x00000080 #define ETH_DMAOMR_ST 0x00002000 #define ETH_DMAOMR_TTC_MASK 0x0001C000 #define ETH_DMAOMR_FTF 0x00100000 #define ETH_DMAOMR_TSF 0x00200000 #define ETH_DMAOMR_DFRF 0x01000000 #define ETH_DMAOMR_RSF 0x02000000 #define ETH_DMAOMR_DTCEFD 0x04000000 /* Ethernet DMA interrupt enable register ETH_DMAIER bits */ #define ETH_DMAIER_TIE 0x00000001 #define ETH_DMAIER_TPSIE 0x00000002 #define ETH_DMAIER_TBUIE 0x00000004 #define ETH_DMAIER_TJTIE 0x00000008 #define ETH_DMAIER_ROIE 0x00000010 #define ETH_DMAIER_TUIE 0x00000020 #define ETH_DMAIER_RIE 0x00000040 #define ETH_DMAIER_RBUIE 0x00000080 #define ETH_DMAIER_RPSIE 0x00000100 #define ETH_DMAIER_RWTIE 0x00000200 #define ETH_DMAIER_ETIE 0x00000400 #define ETH_DMAIER_FBEIE 0x00002000 #define ETH_DMAIER_ERIE 0x00004000 #define ETH_DMAIER_AISE 0x00008000 #define ETH_DMAIER_NSIE 0x00010000 BEGIN_DECLS void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data); uint16_t eth_smi_read(uint8_t phy, uint8_t reg); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/exti.h000066400000000000000000000016571435536612600235600ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_EXTI_H #define LIBOPENCM3_EXTI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/flash.h000066400000000000000000000101221435536612600236670ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * For details see: * PM0075 programming manual: STM32F10xxx Flash programming * August 2010, Doc ID 17863 Rev 1 * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/CD00283419.pdf */ #ifndef LIBOPENCM3_FLASH_H #define LIBOPENCM3_FLASH_H #include #include /* --- FLASH registers ----------------------------------------------------- */ #define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) #define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) #define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) #define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) #define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) #define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) #define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) #define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) /* --- FLASH_ACR values ---------------------------------------------------- */ #define FLASH_ACR_PRFTBS (1 << 5) #define FLASH_ACR_PRFTBE (1 << 4) #define FLASH_ACR_HLFCYA (1 << 3) #define FLASH_ACR_LATENCY_0WS 0x00 #define FLASH_ACR_LATENCY_1WS 0x01 #define FLASH_ACR_LATENCY_2WS 0x02 /* --- FLASH_SR values ----------------------------------------------------- */ #define FLASH_SR_EOP (1 << 5) #define FLASH_SR_WRPRTERR (1 << 4) #define FLASH_SR_PGERR (1 << 2) #define FLASH_SR_BSY (1 << 0) /* --- FLASH_CR values ----------------------------------------------------- */ #define FLASH_CR_EOPIE (1 << 12) #define FLASH_CR_ERRIE (1 << 10) #define FLASH_CR_OPTWRE (1 << 9) #define FLASH_CR_LOCK (1 << 7) #define FLASH_CR_STRT (1 << 6) #define FLASH_CR_OPTER (1 << 5) #define FLASH_CR_OPTPG (1 << 4) #define FLASH_CR_MER (1 << 2) #define FLASH_CR_PER (1 << 1) #define FLASH_CR_PG (1 << 0) /* --- FLASH_OBR values ---------------------------------------------------- */ /* FLASH_OBR[25:18]: Data1 */ /* FLASH_OBR[17:10]: Data0 */ #define FLASH_OBR_NRST_STDBY (1 << 4) #define FLASH_OBR_NRST_STOP (1 << 3) #define FLASH_OBR_WDG_SW (1 << 2) #define FLASH_OBR_RDPRT (1 << 1) #define FLASH_OBR_OPTERR (1 << 0) /* --- FLASH Keys -----------------------------------------------------------*/ #define FLASH_RDP_KEY ((uint16_t)0x00a5) #define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) #define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void flash_prefetch_buffer_enable(void); void flash_prefetch_buffer_disable(void); void flash_halfcycle_enable(void); void flash_halfcycle_disable(void); void flash_set_ws(uint32_t ws); void flash_unlock(void); void flash_lock(void); void flash_clear_pgerr_flag(void); void flash_clear_eop_flag(void); void flash_clear_wrprterr_flag(void); void flash_clear_bsy_flag(void); void flash_clear_status_flags(void); uint32_t flash_get_status_flags(void); void flash_unlock_option_bytes(void); void flash_erase_all_pages(void); void flash_erase_page(uint32_t page_address); void flash_program_word(uint32_t address, uint32_t data); void flash_program_half_word(uint32_t address, uint16_t data); void flash_wait_for_last_operation(void); void flash_erase_option_bytes(void); void flash_program_option_bytes(uint32_t address, uint16_t data); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/gpio.h000066400000000000000000000760431435536612600235460ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines @brief Defined Constants and Types for the STM32F1xx General Purpose I/O @ingroup STM32F1xx_defines @version 1.0.0 @date 1 July 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Piotr Esden-Tempski * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LIBOPENCM3_GPIO_H #define LIBOPENCM3_GPIO_H #include #include /* --- Convenience macros -------------------------------------------------- */ /* GPIO port base addresses (for convenience) */ /** @defgroup gpio_port_id GPIO Port IDs @ingroup gpio_defines @{*/ /* GPIO port base addresses (for convenience) */ #define GPIOA GPIO_PORT_A_BASE #define GPIOB GPIO_PORT_B_BASE #define GPIOC GPIO_PORT_C_BASE #define GPIOD GPIO_PORT_D_BASE #define GPIOE GPIO_PORT_E_BASE #define GPIOF GPIO_PORT_F_BASE #define GPIOG GPIO_PORT_G_BASE /**@}*/ /* --- Alternate function GPIOs -------------------------------------------- */ /* Default alternate functions of some pins (with and without remapping) */ /* CAN1 / CAN GPIO */ #define GPIO_CAN1_RX GPIO11 /* PA11 */ #define GPIO_CAN1_TX GPIO12 /* PA12 */ #define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ #define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ #define GPIO_CAN_PB_RX GPIO8 /* PB8 */ #define GPIO_CAN_PB_TX GPIO9 /* PB9 */ #define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ #define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ #define GPIO_CAN_PD_RX GPIO0 /* PD0 */ #define GPIO_CAN_PD_TX GPIO1 /* PD1 */ #define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ #define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ /* CAN1 / CAN BANK */ #define GPIO_BANK_CAN1_RX GPIOA /* PA11 */ #define GPIO_BANK_CAN1_TX GPIOA /* PA12 */ #define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */ #define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */ #define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */ #define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */ #define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */ #define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */ #define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */ #define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */ #define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */ #define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */ /* CAN2 GPIO */ #define GPIO_CAN2_RX GPIO12 /* PB12 */ #define GPIO_CAN2_TX GPIO13 /* PB13 */ #define GPIO_CAN2_RE_RX GPIO5 /* PB5 */ #define GPIO_CAN2_RE_TX GPIO6 /* PB6 */ /* CAN2 BANK */ #define GPIO_BANK_CAN2_RX GPIOB /* PB12 */ #define GPIO_BANK_CAN2_TX GPIOB /* PB13 */ #define GPIO_BANK_CAN2_RE_RX GPIOB /* PB5 */ #define GPIO_BANK_CAN2_RE_TX GPIOB /* PB6 */ /* JTAG/SWD GPIO */ #define GPIO_JTMS_SWDIO GPIO13 /* PA13 */ #define GPIO_JTCK_SWCLK GPIO14 /* PA14 */ #define GPIO_JTDI GPIO15 /* PA15 */ #define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ #define GPIO_JNTRST GPIO4 /* PB4 */ #define GPIO_TRACECK GPIO2 /* PE2 */ #define GPIO_TRACED0 GPIO3 /* PE3 */ #define GPIO_TRACED1 GPIO4 /* PE4 */ #define GPIO_TRACED2 GPIO5 /* PE5 */ #define GPIO_TRACED3 GPIO6 /* PE6 */ /* JTAG/SWD BANK */ #define GPIO_BANK_JTMS_SWDIO GPIOA /* PA13 */ #define GPIO_BANK_JTCK_SWCLK GPIOA /* PA14 */ #define GPIO_BANK_JTDI GPIOA /* PA15 */ #define GPIO_BANK_JTDO_TRACESWO GPIOB /* PB3 */ #define GPIO_BANK_JNTRST GPIOB /* PB4 */ #define GPIO_BANK_TRACECK GPIOE /* PE2 */ #define GPIO_BANK_TRACED0 GPIOE /* PE3 */ #define GPIO_BANK_TRACED1 GPIOE /* PE4 */ #define GPIO_BANK_TRACED2 GPIOE /* PE5 */ #define GPIO_BANK_TRACED3 GPIOE /* PE6 */ /* Timer5 GPIO */ #define GPIO_TIM5_CH1 GPIO0 /* PA0 */ #define GPIO_TIM5_CH2 GPIO1 /* PA1 */ #define GPIO_TIM5_CH3 GPIO2 /* PA2 */ #define GPIO_TIM5_CH4 GPIO3 /* PA3 */ /* Timer5 BANK */ #define GPIO_BANK_TIM5_CH1 GPIOA /* PA0 */ #define GPIO_BANK_TIM5_CH2 GPIOA /* PA1 */ #define GPIO_BANK_TIM5_CH3 GPIOA /* PA2 */ #define GPIO_BANK_TIM5_CH4 GPIOA /* PA3 */ #define GPIO_BANK_TIM5 GPIOA /* Timer4 GPIO */ #define GPIO_TIM4_CH1 GPIO6 /* PB6 */ #define GPIO_TIM4_CH2 GPIO7 /* PB7 */ #define GPIO_TIM4_CH3 GPIO8 /* PB8 */ #define GPIO_TIM4_CH4 GPIO9 /* PB9 */ #define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ #define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ #define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ #define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ /* Timer4 BANK */ #define GPIO_BANK_TIM4_CH1 GPIOB /* PB6 */ #define GPIO_BANK_TIM4_CH2 GPIOB /* PB7 */ #define GPIO_BANK_TIM4_CH3 GPIOB /* PB8 */ #define GPIO_BANK_TIM4_CH4 GPIOB /* PB9 */ #define GPIO_BANK_TIM4 GPIOB #define GPIO_BANK_TIM4_RE_CH1 GPIOD /* PD12 */ #define GPIO_BANK_TIM4_RE_CH2 GPIOD /* PD13 */ #define GPIO_BANK_TIM4_RE_CH3 GPIOD /* PD14 */ #define GPIO_BANK_TIM4_RE_CH4 GPIOD /* PD15 */ #define GPIO_BANK_TIM4_RE GPIOD /* Timer3 GPIO */ #define GPIO_TIM3_CH1 GPIO6 /* PA6 */ #define GPIO_TIM3_CH2 GPIO7 /* PA7 */ #define GPIO_TIM3_CH3 GPIO0 /* PB0 */ #define GPIO_TIM3_CH4 GPIO1 /* PB1 */ #define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ #define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ #define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ #define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ #define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ #define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ #define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ #define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ /* Timer3 BANK */ #define GPIO_BANK_TIM3_CH1 GPIOA /* PA6 */ #define GPIO_BANK_TIM3_CH2 GPIOA /* PA7 */ #define GPIO_BANK_TIM3_CH3 GPIOB /* PB0 */ #define GPIO_BANK_TIM3_CH4 GPIOB /* PB1 */ #define GPIO_BANK_TIM3_CH12 GPIOA #define GPIO_BANK_TIM3_CH34 GPIOB #define GPIO_BANK_TIM3_PR_CH1 GPIOB /* PB4 */ #define GPIO_BANK_TIM3_PR_CH2 GPIOB /* PB5 */ #define GPIO_BANK_TIM3_PR_CH3 GPIOB /* PB0 */ #define GPIO_BANK_TIM3_PR_CH4 GPIOB /* PB1 */ #define GPIO_BANK_TIM3_PR GPIOB #define GPIO_BANK_TIM3_FR_CH1 GPIOC /* PC6 */ #define GPIO_BANK_TIM3_FR_CH2 GPIOC /* PC7 */ #define GPIO_BANK_TIM3_FR_CH3 GPIOC /* PC8 */ #define GPIO_BANK_TIM3_FR_CH4 GPIOC /* PC9 */ #define GPIO_BANK_TIM3_FR GPIOC /* Timer2 GPIO */ #define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ #define GPIO_TIM2_CH2 GPIO1 /* PA1 */ #define GPIO_TIM2_CH3 GPIO2 /* PA2 */ #define GPIO_TIM2_CH4 GPIO3 /* PA3 */ #define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ #define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ #define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ #define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ #define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ #define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ #define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ #define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ #define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ #define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ #define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ #define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ /* Timer2 BANK */ #define GPIO_BANK_TIM2_CH1_ETR GPIOA /* PA0 */ #define GPIO_BANK_TIM2_CH2 GPIOA /* PA1 */ #define GPIO_BANK_TIM2_CH3 GPIOA /* PA2 */ #define GPIO_BANK_TIM2_CH4 GPIOA /* PA3 */ #define GPIO_BANK_TIM2 GPIOA #define GPIO_BANK_TIM2_PR1_CH1_ETR GPIOA /* PA15 */ #define GPIO_BANK_TIM2_PR1_CH2 GPIOB /* PB3 */ #define GPIO_BANK_TIM2_PR1_CH3 GPIOA /* PA2 */ #define GPIO_BANK_TIM2_PR1_CH4 GPIOA /* PA3 */ #define GPIO_BANK_TIM2_PR1_CH134 GPIOA #define GPIO_BANK_TIM2_PR2_CH1_ETR GPIOA /* PA0 */ #define GPIO_BANK_TIM2_PR2_CH2 GPIOA /* PA1 */ #define GPIO_BANK_TIM2_PR2_CH3 GPIOB /* PB10 */ #define GPIO_BANK_TIM2_PR2_CH4 GPIOB /* PB11 */ #define GPIO_BANK_TIM2_PR2_CH12 GPIOA #define GPIO_BANK_TIM2_PR2_CH34 GPIOB #define GPIO_BANK_TIM2_FR_CH1_ETR GPIOA /* PA15 */ #define GPIO_BANK_TIM2_FR_CH2 GPIOB /* PB3 */ #define GPIO_BANK_TIM2_FR_CH3 GPIOB /* PB10 */ #define GPIO_BANK_TIM2_FR_CH4 GPIOB /* PB11 */ #define GPIO_BANK_TIM2_FR_CH234 GPIOB /* Timer1 GPIO */ #define GPIO_TIM1_ETR GPIO12 /* PA12 */ #define GPIO_TIM1_CH1 GPIO8 /* PA8 */ #define GPIO_TIM1_CH2 GPIO9 /* PA9 */ #define GPIO_TIM1_CH3 GPIO10 /* PA10 */ #define GPIO_TIM1_CH4 GPIO11 /* PA11 */ #define GPIO_TIM1_BKIN GPIO12 /* PB12 */ #define GPIO_TIM1_CH1N GPIO13 /* PB13 */ #define GPIO_TIM1_CH2N GPIO14 /* PB14 */ #define GPIO_TIM1_CH3N GPIO15 /* PB15 */ #define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ #define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ #define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ #define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ #define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ #define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ #define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ #define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ #define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ #define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ #define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ #define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ #define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ #define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ #define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ #define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ #define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ #define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ /* Timer1 BANK */ #define GPIO_BANK_TIM1_ETR GPIOA /* PA12 */ #define GPIO_BANK_TIM1_CH1 GPIOA /* PA8 */ #define GPIO_BANK_TIM1_CH2 GPIOA /* PA9 */ #define GPIO_BANK_TIM1_CH3 GPIOA /* PA10 */ #define GPIO_BANK_TIM1_CH4 GPIOA /* PA11 */ #define GPIO_BANK_TIM1_BKIN GPIOB /* PB12 */ #define GPIO_BANK_TIM1_CH1N GPIOB /* PB13 */ #define GPIO_BANK_TIM1_CH2N GPIOB /* PB14 */ #define GPIO_BANK_TIM1_CH3N GPIOB /* PB15 */ #define GPIO_BANK_TIM1_ETR_CH1234 GPIOA #define GPIO_BANK_TIM1_BKIN_CH123N GPIOB #define GPIO_BANK_TIM1_PR_ETR GPIOA /* PA12 */ #define GPIO_BANK_TIM1_PR_CH1 GPIOA /* PA8 */ #define GPIO_BANK_TIM1_PR_CH2 GPIOA /* PA9 */ #define GPIO_BANK_TIM1_PR_CH3 GPIOA /* PA10 */ #define GPIO_BANK_TIM1_PR_CH4 GPIOA /* PA11 */ #define GPIO_BANK_TIM1_PR_BKIN GPIOA /* PA6 */ #define GPIO_BANK_TIM1_PR_CH1N GPIOA /* PA7 */ #define GPIO_BANK_TIM1_PR_CH2N GPIOB /* PB0 */ #define GPIO_BANK_TIM1_PR_CH3N GPIOB /* PB1 */ #define GPIO_BANK_TIM1_PR_ETR_CH1234_BKIN_CH1N GPIOA #define GPIO_BANK_TIM1_PR_CH23N GPIOB #define GPIO_BANK_TIM1_FR_ETR GPIOE /* PE7 */ #define GPIO_BANK_TIM1_FR_CH1 GPIOE /* PE9 */ #define GPIO_BANK_TIM1_FR_CH2 GPIOE /* PE11 */ #define GPIO_BANK_TIM1_FR_CH3 GPIOE /* PE13 */ #define GPIO_BANK_TIM1_FR_CH4 GPIOE /* PE14 */ #define GPIO_BANK_TIM1_FR_BKIN GPIOE /* PE15 */ #define GPIO_BANK_TIM1_FR_CH1N GPIOE /* PE8 */ #define GPIO_BANK_TIM1_FR_CH2N GPIOE /* PE10 */ #define GPIO_BANK_TIM1_FR_CH3N GPIOE /* PE12 */ #define GPIO_BANK_TIM1_FR GPIOE /* UART5 GPIO */ #define GPIO_UART5_TX GPIO12 /* PC12 */ #define GPIO_UART5_RX GPIO2 /* PD2 */ /* UART5 BANK */ #define GPIO_BANK_UART5_TX GPIOC /* PC12 */ #define GPIO_BANK_UART5_RX GPIOD /* PD2 */ /* UART4 GPIO */ #define GPIO_UART4_TX GPIO10 /* PC10 */ #define GPIO_UART4_RX GPIO11 /* PC11 */ /* UART4 BANK */ #define GPIO_BANK_UART4_TX GPIOC /* PC10 */ #define GPIO_BANK_UART4_RX GPIOC /* PC11 */ /* USART3 GPIO */ #define GPIO_USART3_TX GPIO10 /* PB10 */ #define GPIO_USART3_RX GPIO11 /* PB11 */ #define GPIO_USART3_CK GPIO12 /* PB12 */ #define GPIO_USART3_CTS GPIO13 /* PB13 */ #define GPIO_USART3_RTS GPIO14 /* PB14 */ #define GPIO_USART3_PR_TX GPIO10 /* PC10 */ #define GPIO_USART3_PR_RX GPIO11 /* PC11 */ #define GPIO_USART3_PR_CK GPIO12 /* PC12 */ #define GPIO_USART3_PR_CTS GPIO13 /* PB13 */ #define GPIO_USART3_PR_RTS GPIO14 /* PB14 */ #define GPIO_USART3_FR_TX GPIO8 /* PD8 */ #define GPIO_USART3_FR_RX GPIO9 /* PD9 */ #define GPIO_USART3_FR_CK GPIO10 /* PD10 */ #define GPIO_USART3_FR_CTS GPIO11 /* PD11 */ #define GPIO_USART3_FR_RTS GPIO12 /* PD12 */ /* USART3 BANK */ #define GPIO_BANK_USART3_TX GPIOB /* PB10 */ #define GPIO_BANK_USART3_RX GPIOB /* PB11 */ #define GPIO_BANK_USART3_CK GPIOB /* PB12 */ #define GPIO_BANK_USART3_CTS GPIOB /* PB13 */ #define GPIO_BANK_USART3_RTS GPIOB /* PB14 */ #define GPIO_BANK_USART3_PR_TX GPIOC /* PC10 */ #define GPIO_BANK_USART3_PR_RX GPIOC /* PC11 */ #define GPIO_BANK_USART3_PR_CK GPIOC /* PC12 */ #define GPIO_BANK_USART3_PR_CTS GPIOB /* PB13 */ #define GPIO_BANK_USART3_PR_RTS GPIOB /* PB14 */ #define GPIO_BANK_USART3_FR_TX GPIOD /* PD8 */ #define GPIO_BANK_USART3_FR_RX GPIOD /* PD9 */ #define GPIO_BANK_USART3_FR_CK GPIOD /* PD10 */ #define GPIO_BANK_USART3_FR_CTS GPIOD /* PD11 */ #define GPIO_BANK_USART3_FR_RTS GPIOD /* PD12 */ /* USART2 GPIO */ #define GPIO_USART2_CTS GPIO0 /* PA0 */ #define GPIO_USART2_RTS GPIO1 /* PA1 */ #define GPIO_USART2_TX GPIO2 /* PA2 */ #define GPIO_USART2_RX GPIO3 /* PA3 */ #define GPIO_USART2_CK GPIO4 /* PA4 */ #define GPIO_USART2_RE_CTS GPIO3 /* PD3 */ #define GPIO_USART2_RE_RTS GPIO4 /* PD4 */ #define GPIO_USART2_RE_TX GPIO5 /* PD5 */ #define GPIO_USART2_RE_RX GPIO6 /* PD6 */ #define GPIO_USART2_RE_CK GPIO7 /* PD7 */ /* USART2 BANK */ #define GPIO_BANK_USART2_CTS GPIOA /* PA0 */ #define GPIO_BANK_USART2_RTS GPIOA /* PA1 */ #define GPIO_BANK_USART2_TX GPIOA /* PA2 */ #define GPIO_BANK_USART2_RX GPIOA /* PA3 */ #define GPIO_BANK_USART2_CK GPIOA /* PA4 */ #define GPIO_BANK_USART2_RE_CTS GPIOD /* PD3 */ #define GPIO_BANK_USART2_RE_RTS GPIOD /* PD4 */ #define GPIO_BANK_USART2_RE_TX GPIOD /* PD5 */ #define GPIO_BANK_USART2_RE_RX GPIOD /* PD6 */ #define GPIO_BANK_USART2_RE_CK GPIOD /* PD7 */ /* USART1 GPIO */ #define GPIO_USART1_TX GPIO9 /* PA9 */ #define GPIO_USART1_RX GPIO10 /* PA10 */ #define GPIO_USART1_RE_TX GPIO6 /* PB6 */ #define GPIO_USART1_RE_RX GPIO7 /* PB7 */ /* USART1 BANK */ #define GPIO_BANK_USART1_TX GPIOA /* PA9 */ #define GPIO_BANK_USART1_RX GPIOA /* PA10 */ #define GPIO_BANK_USART1_RE_TX GPIOB /* PB6 */ #define GPIO_BANK_USART1_RE_RX GPIOB /* PB7 */ /* I2C1 GPIO */ #define GPIO_I2C1_SMBAI GPIO5 /* PB5 */ #define GPIO_I2C1_SCL GPIO6 /* PB6 */ #define GPIO_I2C1_SDA GPIO7 /* PB7 */ #define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ #define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ #define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ /* I2C1 BANK */ #define GPIO_BANK_I2C1_SMBAI GPIOB /* PB5 */ #define GPIO_BANK_I2C1_SCL GPIOB /* PB6 */ #define GPIO_BANK_I2C1_SDA GPIOB /* PB7 */ #define GPIO_BANK_I2C1_RE_SMBAI GPIOB /* PB5 */ #define GPIO_BANK_I2C1_RE_SCL GPIOB /* PB8 */ #define GPIO_BANK_I2C1_RE_SDA GPIOB /* PB9 */ /* I2C2 GPIO */ #define GPIO_I2C2_SCL GPIO10 /* PB10 */ #define GPIO_I2C2_SDA GPIO11 /* PB11 */ #define GPIO_I2C2_SMBAI GPIO12 /* PB12 */ /* I2C2 BANK */ #define GPIO_BANK_I2C2_SCL GPIOB /* PB10 */ #define GPIO_BANK_I2C2_SDA GPIOB /* PB11 */ #define GPIO_BANK_I2C2_SMBAI GPIOB /* PB12 */ /* SPI1 GPIO */ #define GPIO_SPI1_NSS GPIO4 /* PA4 */ #define GPIO_SPI1_SCK GPIO5 /* PA5 */ #define GPIO_SPI1_MISO GPIO6 /* PA6 */ #define GPIO_SPI1_MOSI GPIO7 /* PA7 */ #define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ #define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ #define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ #define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ /* SPI1 BANK */ #define GPIO_BANK_SPI1_NSS GPIOA /* PA4 */ #define GPIO_BANK_SPI1_SCK GPIOA /* PA5 */ #define GPIO_BANK_SPI1_MISO GPIOA /* PA6 */ #define GPIO_BANK_SPI1_MOSI GPIOA /* PA7 */ #define GPIO_BANK_SPI1_RE_NSS GPIOA /* PA15 */ #define GPIO_BANK_SPI1_RE_SCK GPIOB /* PB3 */ #define GPIO_BANK_SPI1_RE_MISO GPIOB /* PB4 */ #define GPIO_BANK_SPI1_RE_MOSI GPIOB /* PB5 */ /* SPI2 GPIO */ #define GPIO_SPI2_NSS GPIO12 /* PB12 */ #define GPIO_SPI2_SCK GPIO13 /* PB13 */ #define GPIO_SPI2_MISO GPIO14 /* PB14 */ #define GPIO_SPI2_MOSI GPIO15 /* PB15 */ /* SPI2 BANK */ #define GPIO_BANK_SPI2_NSS GPIOB /* PB12 */ #define GPIO_BANK_SPI2_SCK GPIOB /* PB13 */ #define GPIO_BANK_SPI2_MISO GPIOB /* PB14 */ #define GPIO_BANK_SPI2_MOSI GPIOB /* PB15 */ /* SPI3 GPIO */ #define GPIO_SPI3_NSS GPIO15 /* PA15 */ #define GPIO_SPI3_SCK GPIO3 /* PB3 */ #define GPIO_SPI3_MISO GPIO4 /* PB4 */ #define GPIO_SPI3_MOSI GPIO5 /* PB5 */ #define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ #define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ #define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ #define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ /* SPI3 BANK */ #define GPIO_BANK_SPI3_NSS GPIOA /* PA15 */ #define GPIO_BANK_SPI3_SCK GPIOB /* PB3 */ #define GPIO_BANK_SPI3_MISO GPIOB /* PB4 */ #define GPIO_BANK_SPI3_MOSI GPIOB /* PB5 */ #define GPIO_BANK_SPI3_RE_NSS GPIOA /* PA4 */ #define GPIO_BANK_SPI3_RE_SCK GPIOC /* PC10 */ #define GPIO_BANK_SPI3_RE_MISO GPIOC /* PC11 */ #define GPIO_BANK_SPI3_RE_MOSI GPIOC /* PC12 */ /* ETH GPIO */ #define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ #define GPIO_ETH_RXD0 GPIO4 /* PC4 */ #define GPIO_ETH_RXD1 GPIO5 /* PC5 */ #define GPIO_ETH_RXD2 GPIO0 /* PB0 */ #define GPIO_ETH_RXD3 GPIO1 /* PB1 */ #define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ #define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ #define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ #define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ #define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ /* ETH BANK */ #define GPIO_BANK_ETH_RX_DV_CRS_DV GPIOA /* PA7 */ #define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */ #define GPIO_BANK_ETH_RXD1 GPIOC /* PC5 */ #define GPIO_BANK_ETH_RXD2 GPIOB /* PB0 */ #define GPIO_BANK_ETH_RXD3 GPIOB /* PB1 */ #define GPIO_BANK_ETH_RE_RX_DV_CRS_DV GPIOD /* PD8 */ #define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */ #define GPIO_BANK_ETH_RE_RXD1 GPIOD /* PD10 */ #define GPIO_BANK_ETH_RE_RXD2 GPIOD /* PD11 */ #define GPIO_BANK_ETH_RE_RXD3 GPIOD /* PD12 */ /* --- GPIO registers ------------------------------------------------------ */ /* Port configuration register low (GPIOx_CRL) */ #define GPIO_CRL(port) MMIO32(port + 0x00) #define GPIOA_CRL GPIO_CRL(GPIOA) #define GPIOB_CRL GPIO_CRL(GPIOB) #define GPIOC_CRL GPIO_CRL(GPIOC) #define GPIOD_CRL GPIO_CRL(GPIOD) #define GPIOE_CRL GPIO_CRL(GPIOE) #define GPIOF_CRL GPIO_CRL(GPIOF) #define GPIOG_CRL GPIO_CRL(GPIOG) /* Port configuration register low (GPIOx_CRH) */ #define GPIO_CRH(port) MMIO32(port + 0x04) #define GPIOA_CRH GPIO_CRH(GPIOA) #define GPIOB_CRH GPIO_CRH(GPIOB) #define GPIOC_CRH GPIO_CRH(GPIOC) #define GPIOD_CRH GPIO_CRH(GPIOD) #define GPIOE_CRH GPIO_CRH(GPIOE) #define GPIOF_CRH GPIO_CRH(GPIOF) #define GPIOG_CRH GPIO_CRH(GPIOG) /* Port input data register (GPIOx_IDR) */ #define GPIO_IDR(port) MMIO32(port + 0x08) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) #define GPIOD_IDR GPIO_IDR(GPIOD) #define GPIOE_IDR GPIO_IDR(GPIOE) #define GPIOF_IDR GPIO_IDR(GPIOF) #define GPIOG_IDR GPIO_IDR(GPIOG) /* Port output data register (GPIOx_ODR) */ #define GPIO_ODR(port) MMIO32(port + 0x0c) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) #define GPIOD_ODR GPIO_ODR(GPIOD) #define GPIOE_ODR GPIO_ODR(GPIOE) #define GPIOF_ODR GPIO_ODR(GPIOF) #define GPIOG_ODR GPIO_ODR(GPIOG) /* Port bit set/reset register (GPIOx_BSRR) */ #define GPIO_BSRR(port) MMIO32(port + 0x10) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) #define GPIOD_BSRR GPIO_BSRR(GPIOD) #define GPIOE_BSRR GPIO_BSRR(GPIOE) #define GPIOF_BSRR GPIO_BSRR(GPIOF) #define GPIOG_BSRR GPIO_BSRR(GPIOG) /* Port bit reset register (GPIOx_BRR) */ #define GPIO_BRR(port) MMIO16(port + 0x14) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) #define GPIOD_BRR GPIO_BRR(GPIOD) #define GPIOE_BRR GPIO_BRR(GPIOE) #define GPIOF_BRR GPIO_BRR(GPIOF) #define GPIOG_BRR GPIO_BRR(GPIOG) /* Port configuration lock register (GPIOx_LCKR) */ #define GPIO_LCKR(port) MMIO32(port + 0x18) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) #define GPIOD_LCKR GPIO_LCKR(GPIOD) #define GPIOE_LCKR GPIO_LCKR(GPIOE) #define GPIOF_LCKR GPIO_LCKR(GPIOF) #define GPIOG_LCKR GPIO_LCKR(GPIOG) /* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ /** @defgroup gpio_cnf GPIO Pin Configuration @ingroup gpio_defines If mode specifies input, configuration can be @li Analog input @li Floating input @li Pull up/down input If mode specifies output, configuration can be @li Digital push-pull @li Digital open drain @li Alternate function push-pull or analog output @li Alternate function open drain or analog output @{*/ /* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ /** Analog Input */ #define GPIO_CNF_INPUT_ANALOG 0x00 /** Digital Input Floating */ #define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ /** Digital Input Pull Up and Down */ #define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 /* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ /** Digital Output Pushpull */ #define GPIO_CNF_OUTPUT_PUSHPULL 0x00 /** Digital Output Open Drain */ #define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 /** Alternate Function Output Pushpull */ #define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 /** Alternate Function Output Open Drain */ #define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 /**@}*/ /* Pin mode (MODE[1:0]) values */ /** @defgroup gpio_mode GPIO Pin Mode @ingroup gpio_defines @li Input (default after reset) @li Output mode at 10 MHz maximum speed @li Output mode at 2 MHz maximum speed @li Output mode at 50 MHz maximum speed @{*/ #define GPIO_MODE_INPUT 0x00 /* Default */ #define GPIO_MODE_OUTPUT_10_MHZ 0x01 #define GPIO_MODE_OUTPUT_2_MHZ 0x02 #define GPIO_MODE_OUTPUT_50_MHZ 0x03 /**@}*/ /* --- GPIO_IDR values ----------------------------------------------------- */ /* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ /* --- GPIO_ODR values ----------------------------------------------------- */ /* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ /* --- GPIO_BSRR values ---------------------------------------------------- */ /* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ /* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ /* --- GPIO_BRR values ----------------------------------------------------- */ /* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ /* --- AFIO registers ------------------------------------------------------ */ /* Event control register (AFIO_EVCR) */ #define AFIO_EVCR MMIO32(AFIO_BASE + 0x00) /* AF remap and debug I/O configuration register (AFIO_MAPR) */ #define AFIO_MAPR MMIO32(AFIO_BASE + 0x04) /* External interrupt configuration register [0..3] (AFIO_EXTICR[1..4])*/ #define AFIO_EXTICR(i) MMIO32(AFIO_BASE + 0x08 + (i)*4) #define AFIO_EXTICR1 AFIO_EXTICR(0) #define AFIO_EXTICR2 AFIO_EXTICR(1) #define AFIO_EXTICR3 AFIO_EXTICR(2) #define AFIO_EXTICR4 AFIO_EXTICR(3) /* AF remap and debug I/O configuration register (AFIO_MAPR) */ #define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C) /* --- AFIO_EVCR values ---------------------------------------------------- */ /* EVOE: Event output enable */ #define AFIO_EVCR_EVOE (1 << 7) /* PORT[2:0]: Port selection */ /** @defgroup afio_evcr_port EVENTOUT Port selection @ingroup gpio_defines @{*/ #define AFIO_EVCR_PORT_PA (0x0 << 4) #define AFIO_EVCR_PORT_PB (0x1 << 4) #define AFIO_EVCR_PORT_PC (0x2 << 4) #define AFIO_EVCR_PORT_PD (0x3 << 4) #define AFIO_EVCR_PORT_PE (0x4 << 4) /**@}*/ /* PIN[3:0]: Pin selection */ /** @defgroup afio_evcr_pin EVENTOUT Pin selection @ingroup gpio_defines @{*/ #define AFIO_EVCR_PIN_Px0 (0x0 << 0) #define AFIO_EVCR_PIN_Px1 (0x1 << 0) #define AFIO_EVCR_PIN_Px2 (0x2 << 0) #define AFIO_EVCR_PIN_Px3 (0x3 << 0) #define AFIO_EVCR_PIN_Px4 (0x4 << 0) #define AFIO_EVCR_PIN_Px5 (0x5 << 0) #define AFIO_EVCR_PIN_Px6 (0x6 << 0) #define AFIO_EVCR_PIN_Px7 (0x7 << 0) #define AFIO_EVCR_PIN_Px8 (0x8 << 0) #define AFIO_EVCR_PIN_Px9 (0x9 << 0) #define AFIO_EVCR_PIN_Px10 (0xA << 0) #define AFIO_EVCR_PIN_Px11 (0xB << 0) #define AFIO_EVCR_PIN_Px12 (0xC << 0) #define AFIO_EVCR_PIN_Px13 (0xD << 0) #define AFIO_EVCR_PIN_Px14 (0xE << 0) #define AFIO_EVCR_PIN_Px15 (0xF << 0) /**@}*/ /* --- AFIO_MAPR values ---------------------------------------------------- */ /* 31 reserved */ /** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity Line Devices only @ingroup gpio_defines @{*/ /* PTP_PPS_REMAP: */ /** Ethernet PTP PPS remapping (only connectivity line devices) */ #define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) /* TIM2ITR1_IREMAP: */ /** TIM2 internal trigger 1 remapping (only connectivity line devices) */ #define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) /* SPI3_REMAP: */ /** SPI3/I2S3 remapping (only connectivity line devices) */ #define AFIO_MAPR_SPI3_REMAP (1 << 28) /* MII_REMAP: */ /** MII or RMII selection (only connectivity line devices) */ #define AFIO_MAPR_MII_RMII_SEL (1 << 23) /* CAN2_REMAP: */ /** CAN2 I/O remapping (only connectivity line devices) */ #define AFIO_MAPR_CAN2_REMAP (1 << 22) /* ETH_REMAP: */ /** Ethernet MAC I/O remapping (only connectivity line devices) */ #define AFIO_MAPR_ETH_REMAP (1 << 21) /**@}*/ /* 27 reserved */ /* SWJ_CFG[2:0]: Serial wire JTAG configuration */ /** @defgroup afio_swj_disable Serial Wire JTAG disables @ingroup gpio_defines @{*/ #define AFIO_MAPR_SWJ_MASK (0x7 << 24) /** Full Serial Wire JTAG capability */ #define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) /** Full Serial Wire JTAG capability without JNTRST */ #define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) /** JTAG-DP disabled with SW-DP enabled */ #define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) /** JTAG-DP disabled and SW-DP disabled */ #define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) /**@}*/ /** @defgroup afio_remap Alternate Function Remap Controls @ingroup gpio_defines @{*/ /* ADC2_ETRGREG_REMAP: */ /** * ADC2 external trigger regulator conversion remapping * (only low-, medium-, high- and XL-density devices) */ #define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) /* ADC2_ETRGINJ_REMAP: */ /** * ADC2 external trigger injected conversion remapping * (only low-, medium-, high- and XL-density devices) */ #define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) /* ADC1_ETRGREG_REMAP: */ /** * ADC1 external trigger regulator conversion remapping * (only low-, medium-, high- and XL-density devices) */ #define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) /* ADC1_ETRGINJ_REMAP: */ /** * ADC1 external trigger injected conversion remapping * (only low-, medium-, high- and XL-density devices) */ #define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) /* TIM5CH4_IREMAP: */ /** TIM5 channel 4 internal remap */ #define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) /* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ #define AFIO_MAPR_PD01_REMAP (1 << 15) /* TIM4_REMAP: */ /** TIM4 remapping */ #define AFIO_MAPR_TIM4_REMAP (1 << 12) /* USART2_REMAP[1:0]: */ /** USART2 remapping */ #define AFIO_MAPR_USART2_REMAP (1 << 3) /* USART1_REMAP[1:0]: */ /** USART1 remapping */ #define AFIO_MAPR_USART1_REMAP (1 << 2) /* I2C1_REMAP[1:0]: */ /** I2C1 remapping */ #define AFIO_MAPR_I2C1_REMAP (1 << 1) /* SPI1_REMAP[1:0]: */ /** SPI1 remapping */ #define AFIO_MAPR_SPI1_REMAP (1 << 0) /**@}*/ /* CAN_REMAP[1:0]: CAN1 alternate function remapping */ /** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1 @ingroup gpio_defines @{*/ #define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) #define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */ #define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) /**@}*/ /* TIM3_REMAP[1:0]: TIM3 remapping */ /** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3 @ingroup gpio_defines @{*/ #define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) #define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) #define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) /**@}*/ /* TIM2_REMAP[1:0]: TIM2 remapping */ /** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2 @ingroup gpio_defines @{*/ #define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) #define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) #define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) #define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) /**@}*/ /* TIM1_REMAP[1:0]: TIM1 remapping */ /** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1 @ingroup gpio_defines @{*/ #define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) #define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) #define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) /**@}*/ /* USART3_REMAP[1:0]: USART3 remapping */ /** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3 @ingroup gpio_defines @{*/ #define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) #define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) #define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) /**@}*/ /** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set @ingroup gpio_defines @{*/ /* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */ #define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10) /* TIM14_REMAP: */ /** TIM14 remapping */ #define AFIO_MAPR2_TIM14_REMAP (1 << 9) /* TIM13_REMAP: */ /** TIM13 remapping */ #define AFIO_MAPR2_TIM13_REMAP (1 << 8) /* TIM11_REMAP: */ /** TIM11 remapping */ #define AFIO_MAPR2_TIM11_REMAP (1 << 7) /* TIM10_REMAP: */ /** TIM10 remapping */ #define AFIO_MAPR2_TIM10_REMAP (1 << 6) /* TIM9_REMAP: */ /** TIM9 remapping */ #define AFIO_MAPR2_TIM9_REMAP (1 << 5) /**@}*/ /* --- AFIO_EXTICR1 values ------------------------------------------------- */ /* --- AFIO_EXTICR2 values ------------------------------------------------- */ /* --- AFIO_EXTICR3 values ------------------------------------------------- */ /* --- AFIO_EXTICR4 values ------------------------------------------------- */ /** @defgroup afio_exti Alternate Function EXTI pin number @ingroup gpio_defines @{*/ #define AFIO_EXTI0 0 #define AFIO_EXTI1 1 #define AFIO_EXTI2 2 #define AFIO_EXTI3 3 #define AFIO_EXTI4 4 #define AFIO_EXTI5 5 #define AFIO_EXTI6 6 #define AFIO_EXTI7 7 #define AFIO_EXTI8 8 #define AFIO_EXTI9 9 #define AFIO_EXTI10 10 #define AFIO_EXTI11 11 #define AFIO_EXTI12 12 #define AFIO_EXTI13 13 #define AFIO_EXTI14 14 #define AFIO_EXTI15 15 /**@}*/ /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint16_t gpios); void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin); void gpio_primary_remap(uint32_t swjenable, uint32_t maps); void gpio_secondary_remap(uint32_t maps); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/i2c.h000066400000000000000000000021041435536612600232500ustar00rootroot00000000000000/** @defgroup i2c_defines I2C Defines @brief Defined Constants and Types for the STM32F1xx I2C @ingroup STM32F1xx_defines @version 1.0.0 @date 12 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_I2C_H #define LIBOPENCM3_I2C_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/irq.yaml000066400000000000000000000017021435536612600241040ustar00rootroot00000000000000includeguard: LIBOPENCM3_STM32_F1_NVIC_H partname_humanreadable: STM32 F1 series partname_doxygen: STM32F1 irqs: - wwdg - pvd - tamper - rtc - flash - rcc - exti0 - exti1 - exti2 - exti3 - exti4 - dma1_channel1 - dma1_channel2 - dma1_channel3 - dma1_channel4 - dma1_channel5 - dma1_channel6 - dma1_channel7 - adc1_2 - usb_hp_can_tx - usb_lp_can_rx0 - can_rx1 - can_sce - exti9_5 - tim1_brk - tim1_up - tim1_trg_com - tim1_cc - tim2 - tim3 - tim4 - i2c1_ev - i2c1_er - i2c2_ev - i2c2_er - spi1 - spi2 - usart1 - usart2 - usart3 - exti15_10 - rtc_alarm - usb_wakeup - tim8_brk - tim8_up - tim8_trg_com - tim8_cc - adc3 - fsmc - sdio - tim5 - spi3 - uart4 - uart5 - tim6 - tim7 - dma2_channel1 - dma2_channel2 - dma2_channel3 - dma2_channel4_5 - dma2_channel5 - eth - eth_wkup - can2_tx - can2_rx0 - can2_rx1 - can2_sce - otg_fs hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/iwdg.h000066400000000000000000000022261435536612600235320ustar00rootroot00000000000000/** @defgroup iwdg_defines IWDG Defines @brief Defined Constants and Types for the STM32F1xx Independent Watchdog Timer @ingroup STM32F1xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_IWDG_H #define LIBOPENCM3_IWDG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/memorymap.h000066400000000000000000000121001435536612600245760ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_MEMORYMAP_H #define LIBOPENCM3_MEMORYMAP_H #include /* --- STM32 specific peripheral definitions ------------------------------- */ /* Memory map for all buses */ #define FLASH_BASE ((uint32_t)0x08000000) #define PERIPH_BASE ((uint32_t)0x40000000) #define INFO_BASE ((uint32_t)0x1ffff000) #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) #define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) /* Register boundary addresses */ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) #define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) #define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) #define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) /* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ #define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) #define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) #define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) #define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) #define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) /* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */ #define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) /* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ /* APB2 */ #define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) #define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) #define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) #define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) #define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) #define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) #define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) #define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) #define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) #define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) #define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) #define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) #define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) #define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) #define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) /* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */ #define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00) #define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000) #define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400) /* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ /* AHB */ #define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) /* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */ #define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) #define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) /* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */ #define RCC_BASE (PERIPH_BASE_AHB + 0x09000) /* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */ #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) #define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) /* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */ #define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) /* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */ #define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000) /* PPIB */ #define DBGMCU_BASE (PPBI_BASE + 0x00042000) /* FSMC */ #define FSMC_BASE (PERIPH_BASE + 0x60000000) /* Device Electronic Signature */ #define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0) #define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/pwr.h000066400000000000000000000021131435536612600234030ustar00rootroot00000000000000/** @defgroup pwr_defines PWR Defines @brief Defined Constants and Types for the STM32F1xx PWR Control @ingroup STM32F1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_PWR_H #define LIBOPENCM3_PWR_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/rcc.h000066400000000000000000000447261435536612600233620ustar00rootroot00000000000000/** @defgroup STM32F1xx_rcc_defines RCC Defines @brief libopencm3 STM32F1xx Reset and Clock Control @ingroup STM32F1xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2009 Federico Ruiz-Ugalde * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LIBOPENCM3_RCC_H #define LIBOPENCM3_RCC_H #include #include /* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */ /* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */ /* --- RCC registers ------------------------------------------------------- */ #define RCC_CR MMIO32(RCC_BASE + 0x00) #define RCC_CFGR MMIO32(RCC_BASE + 0x04) #define RCC_CIR MMIO32(RCC_BASE + 0x08) #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) #define RCC_AHBENR MMIO32(RCC_BASE + 0x14) #define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) #define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) #define RCC_BDCR MMIO32(RCC_BASE + 0x20) #define RCC_CSR MMIO32(RCC_BASE + 0x24) #define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/ #define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/ /* --- RCC_CR values ------------------------------------------------------- */ #define RCC_CR_PLL3RDY (1 << 29) /* (**) */ #define RCC_CR_PLL3ON (1 << 28) /* (**) */ #define RCC_CR_PLL2RDY (1 << 27) /* (**) */ #define RCC_CR_PLL2ON (1 << 26) /* (**) */ #define RCC_CR_PLLRDY (1 << 25) #define RCC_CR_PLLON (1 << 24) #define RCC_CR_CSSON (1 << 19) #define RCC_CR_HSEBYP (1 << 18) #define RCC_CR_HSERDY (1 << 17) #define RCC_CR_HSEON (1 << 16) /* HSICAL: [15:8] */ /* HSITRIM: [7:3] */ #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) /* --- RCC_CFGR values ----------------------------------------------------- */ /* MCO: Microcontroller clock output */ /** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_MCO_NOCLK 0x0 #define RCC_CFGR_MCO_SYSCLK 0x4 #define RCC_CFGR_MCO_HSICLK 0x5 #define RCC_CFGR_MCO_HSECLK 0x6 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x7 #define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */ #define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */ #define RCC_CFGR_MCO_XT1 0xa /* (**) */ #define RCC_CFGR_MCO_PLL3 0xb /* (**) */ /**@}*/ /* USBPRE: USB prescaler (RCC_CFGR[22]) */ /** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 #define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 /**@}*/ /* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ #define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 #define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 /* PLLMUL: PLL multiplication factor */ /** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ /* #define PLLMUL_PLL_CLK_MUL16 0xf */ /* (XX) */ /* Errata? 17? */ /**@}*/ /* TODO: conn. line differs. */ /* PLLXTPRE: HSE divider for PLL entry */ /** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 #define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 /**@}*/ /* PLLSRC: PLL entry clock source */ /** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 #define RCC_CFGR_PLLSRC_HSE_CLK 0x1 #define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ /**@}*/ /* ADCPRE: ADC prescaler */ /****************************************************************************/ /** @defgroup rcc_cfgr_adcpre RCC ADC clock prescaler enable values @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 #define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 #define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 #define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 /**@}*/ /* PPRE2: APB high-speed prescaler (APB2) */ /** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 #define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 #define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 #define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 #define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 /**@}*/ /* PPRE1: APB low-speed prescaler (APB1) */ /** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 #define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 #define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 #define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 #define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 /**@}*/ /* HPRE: AHB prescaler */ /** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 #define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 #define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 #define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa #define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb #define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc #define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd #define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe #define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf /**@}*/ /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 #define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 #define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 /* SW: System clock switch */ /** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 #define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 #define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 /**@}*/ /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ #define RCC_CIR_CSSC (1 << 23) /* OSC ready interrupt clear bits */ #define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ #define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ #define RCC_CIR_PLLRDYC (1 << 20) #define RCC_CIR_HSERDYC (1 << 19) #define RCC_CIR_HSIRDYC (1 << 18) #define RCC_CIR_LSERDYC (1 << 17) #define RCC_CIR_LSIRDYC (1 << 16) /* OSC ready interrupt enable bits */ #define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ #define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ #define RCC_CIR_PLLRDYIE (1 << 12) #define RCC_CIR_HSERDYIE (1 << 11) #define RCC_CIR_HSIRDYIE (1 << 10) #define RCC_CIR_LSERDYIE (1 << 9) #define RCC_CIR_LSIRDYIE (1 << 8) /* Clock security system interrupt flag bit */ #define RCC_CIR_CSSF (1 << 7) /* OSC ready interrupt flag bits */ #define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ #define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ #define RCC_CIR_PLLRDYF (1 << 4) #define RCC_CIR_HSERDYF (1 << 3) #define RCC_CIR_HSIRDYF (1 << 2) #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) /* --- RCC_APB2RSTR values ------------------------------------------------- */ /** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ #define RCC_APB2RSTR_USART1RST (1 << 14) #define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_TIM1RST (1 << 11) #define RCC_APB2RSTR_ADC2RST (1 << 10) #define RCC_APB2RSTR_ADC1RST (1 << 9) #define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ #define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ #define RCC_APB2RSTR_IOPERST (1 << 6) #define RCC_APB2RSTR_IOPDRST (1 << 5) #define RCC_APB2RSTR_IOPCRST (1 << 4) #define RCC_APB2RSTR_IOPBRST (1 << 3) #define RCC_APB2RSTR_IOPARST (1 << 2) #define RCC_APB2RSTR_AFIORST (1 << 0) /**@}*/ /* --- RCC_APB1RSTR values ------------------------------------------------- */ /** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) #define RCC_APB1RSTR_BKPRST (1 << 27) #define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ #define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ #define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ #define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) #define RCC_APB1RSTR_UART5RST (1 << 20) #define RCC_APB1RSTR_UART4RST (1 << 19) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) #define RCC_APB1RSTR_SPI3RST (1 << 15) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM5RST (1 << 3) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) /**@}*/ /* --- RCC_AHBENR values --------------------------------------------------- */ /** @defgroup rcc_ahbenr_en RCC_AHBENR enable values @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_AHBENR_ETHMACENRX (1 << 16) #define RCC_AHBENR_ETHMACENTX (1 << 15) #define RCC_AHBENR_ETHMACEN (1 << 14) #define RCC_AHBENR_OTGFSEN (1 << 12) #define RCC_AHBENR_SDIOEN (1 << 10) #define RCC_AHBENR_FSMCEN (1 << 8) #define RCC_AHBENR_CRCEN (1 << 6) #define RCC_AHBENR_FLITFEN (1 << 4) #define RCC_AHBENR_SRAMEN (1 << 2) #define RCC_AHBENR_DMA2EN (1 << 1) #define RCC_AHBENR_DMA1EN (1 << 0) /**@}*/ /* --- RCC_APB2ENR values -------------------------------------------------- */ /** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ #define RCC_APB2ENR_USART1EN (1 << 14) #define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_TIM1EN (1 << 11) #define RCC_APB2ENR_ADC2EN (1 << 10) #define RCC_APB2ENR_ADC1EN (1 << 9) #define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ #define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ #define RCC_APB2ENR_IOPEEN (1 << 6) #define RCC_APB2ENR_IOPDEN (1 << 5) #define RCC_APB2ENR_IOPCEN (1 << 4) #define RCC_APB2ENR_IOPBEN (1 << 3) #define RCC_APB2ENR_IOPAEN (1 << 2) #define RCC_APB2ENR_AFIOEN (1 << 0) /**@}*/ /* --- RCC_APB1ENR values -------------------------------------------------- */ /** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_BKPEN (1 << 27) #define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ #define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ #define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ #define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) #define RCC_APB1ENR_UART5EN (1 << 20) #define RCC_APB1ENR_UART4EN (1 << 19) #define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) #define RCC_APB1ENR_SPI3EN (1 << 15) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM5EN (1 << 3) #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /**@}*/ /* --- RCC_BDCR values ----------------------------------------------------- */ #define RCC_BDCR_BDRST (1 << 16) #define RCC_BDCR_RTCEN (1 << 15) /* RCC_BDCR[9:8]: RTCSEL */ #define RCC_BDCR_LSEBYP (1 << 2) #define RCC_BDCR_LSERDY (1 << 1) #define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ #define RCC_CSR_LPWRRSTF (1 << 31) #define RCC_CSR_WWDGRSTF (1 << 30) #define RCC_CSR_IWDGRSTF (1 << 29) #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) #define RCC_CSR_RMVF (1 << 24) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) /* --- RCC_AHBRSTR values -------------------------------------------------- */ /** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values @ingroup STM32F1xx_rcc_defines @{*/ #define RCC_AHBRSTR_ETHMACRST (1 << 14) #define RCC_AHBRSTR_OTGFSRST (1 << 12) /**@}*/ /* --- RCC_CFGR2 values ---------------------------------------------------- */ /* I2S3SRC: I2S3 clock source */ #define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 #define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 /* I2S2SRC: I2S2 clock source */ #define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 #define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 /* PREDIV1SRC: PREDIV1 entry clock source */ #define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 #define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 #define RCC_CFGR2_PLL2MUL (1 << 0) #define RCC_CFGR2_PREDIV2 (1 << 0) #define RCC_CFGR2_PREDIV1 (1 << 0) /* PLL3MUL: PLL3 multiplication factor */ #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe #define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf /* PLL2MUL: PLL2 multiplication factor */ #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf /* PREDIV: PREDIV division factor */ #define RCC_CFGR2_PREDIV_NODIV 0x0 #define RCC_CFGR2_PREDIV_DIV2 0x1 #define RCC_CFGR2_PREDIV_DIV3 0x2 #define RCC_CFGR2_PREDIV_DIV4 0x3 #define RCC_CFGR2_PREDIV_DIV5 0x4 #define RCC_CFGR2_PREDIV_DIV6 0x5 #define RCC_CFGR2_PREDIV_DIV7 0x6 #define RCC_CFGR2_PREDIV_DIV8 0x7 #define RCC_CFGR2_PREDIV_DIV9 0x8 #define RCC_CFGR2_PREDIV_DIV10 0x9 #define RCC_CFGR2_PREDIV_DIV11 0xa #define RCC_CFGR2_PREDIV_DIV12 0xb #define RCC_CFGR2_PREDIV_DIV13 0xc #define RCC_CFGR2_PREDIV_DIV14 0xd #define RCC_CFGR2_PREDIV_DIV15 0xe #define RCC_CFGR2_PREDIV_DIV16 0xf /* PREDIV2: PREDIV2 division factor */ #define RCC_CFGR2_PREDIV2_NODIV 0x0 #define RCC_CFGR2_PREDIV2_DIV2 0x1 #define RCC_CFGR2_PREDIV2_DIV3 0x2 #define RCC_CFGR2_PREDIV2_DIV4 0x3 #define RCC_CFGR2_PREDIV2_DIV5 0x4 #define RCC_CFGR2_PREDIV2_DIV6 0x5 #define RCC_CFGR2_PREDIV2_DIV7 0x6 #define RCC_CFGR2_PREDIV2_DIV8 0x7 #define RCC_CFGR2_PREDIV2_DIV9 0x8 #define RCC_CFGR2_PREDIV2_DIV10 0x9 #define RCC_CFGR2_PREDIV2_DIV11 0xa #define RCC_CFGR2_PREDIV2_DIV12 0xb #define RCC_CFGR2_PREDIV2_DIV13 0xc #define RCC_CFGR2_PREDIV2_DIV14 0xd #define RCC_CFGR2_PREDIV2_DIV15 0xe #define RCC_CFGR2_PREDIV2_DIV16 0xf /* --- Variable definitions ------------------------------------------------ */ extern uint32_t rcc_ppre1_frequency; extern uint32_t rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ typedef enum { PLL, PLL2, PLL3, HSE, HSI, LSE, LSI } osc_t; BEGIN_DECLS void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); int rcc_osc_ready_int_flag(osc_t osc); void rcc_css_int_clear(void); int rcc_css_int_flag(void); void rcc_wait_for_osc_ready(osc_t osc); void rcc_osc_on(osc_t osc); void rcc_osc_off(osc_t osc); void rcc_css_enable(void); void rcc_css_disable(void); void rcc_set_mco(uint32_t mcosrc); void rcc_osc_bypass_enable(osc_t osc); void rcc_osc_bypass_disable(osc_t osc); void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); void rcc_set_sysclk_source(uint32_t clk); void rcc_set_pll_multiplication_factor(uint32_t mul); void rcc_set_pll2_multiplication_factor(uint32_t mul); void rcc_set_pll3_multiplication_factor(uint32_t mul); void rcc_set_pll_source(uint32_t pllsrc); void rcc_set_pllxtpre(uint32_t pllxtpre); void rcc_set_adcpre(uint32_t adcpre); void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); void rcc_set_usbpre(uint32_t usbpre); void rcc_set_prediv1(uint32_t prediv); void rcc_set_prediv2(uint32_t prediv); void rcc_set_prediv1_source(uint32_t rccsrc); uint32_t rcc_system_clock_source(void); void rcc_clock_setup_in_hsi_out_64mhz(void); void rcc_clock_setup_in_hsi_out_48mhz(void); void rcc_clock_setup_in_hsi_out_24mhz(void); void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); void rcc_clock_setup_in_hse_25mhz_out_72mhz(void); void rcc_backupdomain_reset(void); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/rtc.h000066400000000000000000000113271435536612600233720ustar00rootroot00000000000000/** @defgroup rtc_defines RTC Defines @brief Defined Constants and Types for the STM32F1xx Real Time Clock @ingroup STM32F1xx_defines @author @htmlonly © @endhtmlonly 2010 Uwe Hermann @version 1.0.0 @date 4 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * The F1 RTC is a straight time stamp, a completely different peripheral to * that found in the F2, F3, F4, L1 and F0. */ #ifndef LIBOPENCM3_RTC_H #define LIBOPENCM3_RTC_H #include #include #include #include /* --- RTC registers ------------------------------------------------------- */ /* RTC control register high (RTC_CRH) */ #define RTC_CRH MMIO32(RTC_BASE + 0x00) /* RTC control register low (RTC_CRL) */ #define RTC_CRL MMIO32(RTC_BASE + 0x04) /* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */ #define RTC_PRLH MMIO32(RTC_BASE + 0x08) #define RTC_PRLL MMIO32(RTC_BASE + 0x0c) /* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */ #define RTC_DIVH MMIO32(RTC_BASE + 0x10) #define RTC_DIVL MMIO32(RTC_BASE + 0x14) /* RTC counter register (RTC_CNTH / RTC_CNTL) */ #define RTC_CNTH MMIO32(RTC_BASE + 0x18) #define RTC_CNTL MMIO32(RTC_BASE + 0x1c) /* RTC alarm register high (RTC_ALRH / RTC_ALRL) */ #define RTC_ALRH MMIO32(RTC_BASE + 0x20) #define RTC_ALRL MMIO32(RTC_BASE + 0x24) /* --- RTC_CRH values -------------------------------------------------------*/ /* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */ /* OWIE: Overflow interrupt enable */ #define RTC_CRH_OWIE (1 << 2) /* ALRIE: Alarm interrupt enable */ #define RTC_CRH_ALRIE (1 << 1) /* SECIE: Second interrupt enable */ #define RTC_CRH_SECIE (1 << 0) /* --- RTC_CRL values -------------------------------------------------------*/ /* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ /* RTOFF: RTC operation OFF */ #define RTC_CRL_RTOFF (1 << 5) /* CNF: Configuration flag */ #define RTC_CRL_CNF (1 << 4) /* RSF: Registers synchronized flag */ #define RTC_CRL_RSF (1 << 3) /* OWF: Overflow flag */ #define RTC_CRL_OWF (1 << 2) /* ALRF: Alarm flag */ #define RTC_CRL_ALRF (1 << 1) /* SECF: Second flag */ #define RTC_CRL_SECF (1 << 0) /* --- RTC_PRLH values ------------------------------------------------------*/ /* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */ /* TODO */ /* --- RTC_PRLL values ------------------------------------------------------*/ /* TODO */ /* --- RTC_DIVH values ------------------------------------------------------*/ /* Bits [15:4] are reserved. */ /* TODO */ /* --- RTC_DIVL values ------------------------------------------------------*/ /* TODO */ /* --- RTC_CNTH values ------------------------------------------------------*/ /* TODO */ /* --- RTC_CNTL values ------------------------------------------------------*/ /* TODO */ /* --- RTC_ALRH values ------------------------------------------------------*/ /* TODO */ /* --- RTC_ALRL values ------------------------------------------------------*/ /* TODO */ /* --- Function prototypes --------------------------------------------------*/ typedef enum { RTC_SEC, RTC_ALR, RTC_OW, } rtcflag_t; BEGIN_DECLS void rtc_awake_from_off(osc_t clock_source); void rtc_enter_config_mode(void); void rtc_exit_config_mode(void); void rtc_set_alarm_time(uint32_t alarm_time); void rtc_enable_alarm(void); void rtc_disable_alarm(void); void rtc_set_prescale_val(uint32_t prescale_val); uint32_t rtc_get_counter_val(void); uint32_t rtc_get_prescale_div_val(void); uint32_t rtc_get_alarm_val(void); void rtc_set_counter_val(uint32_t counter_val); void rtc_interrupt_enable(rtcflag_t flag_val); void rtc_interrupt_disable(rtcflag_t flag_val); void rtc_clear_flag(rtcflag_t flag_val); uint32_t rtc_check_flag(rtcflag_t flag_val); void rtc_awake_from_standby(void); void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/spi.h000066400000000000000000000021041435536612600233660ustar00rootroot00000000000000/** @defgroup spi_defines SPI Defines @brief Defined Constants and Types for the STM32F1xx SPI @ingroup STM32F1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SPI_H #define LIBOPENCM3_SPI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/timer.h000066400000000000000000000027421435536612600237230ustar00rootroot00000000000000/** @defgroup timer_defines Timer Defines @brief libopencm3 Defined Constants and Types for the STM32F1xx Timers @ingroup STM32F1xx_defines @version 1.0.0 @date 8 March 2013 @author @htmlonly © @endhtmlonly 2011 Fergus Noble LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_TIMER_H #define LIBOPENCM3_TIMER_H #include /** Input Capture input polarity */ enum tim_ic_pol { TIM_IC_RISING, TIM_IC_FALLING, }; /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f1/usart.h000066400000000000000000000021201435536612600237270ustar00rootroot00000000000000/** @defgroup usart_defines USART Defines @brief Defined Constants and Types for the STM32F1xx USART @ingroup STM32F1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/000077500000000000000000000000001435536612600224265ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/crc.h000066400000000000000000000022171435536612600233500ustar00rootroot00000000000000/** @defgroup crc_defines CRC Defines @brief libopencm3 Defined Constants and Types for the STM32F2xx CRC Generator @ingroup STM32F2xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRC_H #define LIBOPENCM3_CRC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/crypto.h000066400000000000000000000022251435536612600241200ustar00rootroot00000000000000/** @defgroup crypto_defines CRYPTO Defines * * @brief Defined Constants and Types for the STM32F2xx CRYP Controller * * @ingroup STM32F2xx_defines * * @version 1.0.0 * * @date 17 Jun 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRYPTO_H #define LIBOPENCM3_CRYPTO_H #include #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/dac.h000066400000000000000000000021031435536612600233220ustar00rootroot00000000000000/** @defgroup dac_defines DAC Defines @brief Defined Constants and Types for the STM32F2xx DAC @ingroup STM32F2xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DAC_H #define LIBOPENCM3_DAC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/dma.h000066400000000000000000000021071435536612600233400ustar00rootroot00000000000000/** @defgroup dma_defines DMA Defines @ingroup STM32F2xx_defines @brief Defined Constants and Types for the STM32F2xx DMA Controller @version 1.0.0 @date 18 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DMA_H #define LIBOPENCM3_DMA_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/doc-stm32f2.h000066400000000000000000000010451435536612600245420ustar00rootroot00000000000000/** @mainpage libopencm3 STM32F2 @version 1.0.0 @date 14 September 2012 API documentation for ST Microelectronics STM32F2 Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F2xx STM32F2xx Libraries for ST Microelectronics STM32F2xx series. @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F2xx_defines STM32F2xx Defines @brief Defined Constants and Types for the STM32F2xx series @version 1.0.0 @date 14 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/exti.h000066400000000000000000000016611435536612600235540ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_EXTI_H #define LIBOPENCM3_EXTI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/flash.h000066400000000000000000000015641435536612600237020ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_FLASH_H #define LIBOPENCM3_FLASH_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/gpio.h000066400000000000000000000021241435536612600235340ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines @brief Defined Constants and Types for the STM32F2xx General Purpose I/O @ingroup STM32F2xx_defines @version 1.0.0 @date 1 July 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_GPIO_H #define LIBOPENCM3_GPIO_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/hash.h000066400000000000000000000021101435536612600235140ustar00rootroot00000000000000/** @defgroup hash_defines HASH Defines @ingroup STM32F2xx_defines @brief Defined Constants and Types for the STM32F2xx HASH Controller @version 1.0.0 @date 31 May 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_HASH_H #define LIBOPENCM3_HASH_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/i2c.h000066400000000000000000000021041435536612600232510ustar00rootroot00000000000000/** @defgroup i2c_defines I2C Defines @brief Defined Constants and Types for the STM32F2xx I2C @ingroup STM32F2xx_defines @version 1.0.0 @date 12 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_I2C_H #define LIBOPENCM3_I2C_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/irq.yaml000066400000000000000000000022321435536612600241040ustar00rootroot00000000000000includeguard: LIBOPENCM3_STM32_F2_NVIC_H partname_humanreadable: STM32 F2 series partname_doxygen: STM32F2 irqs: - nvic_wwdg - pvd - tamp_stamp - rtc_wkup - flash - rcc - exti0 - exti1 - exti2 - exti3 - exti4 - dma1_stream0 - dma1_stream1 - dma1_stream2 - dma1_stream3 - dma1_stream4 - dma1_stream5 - dma1_stream6 - adc - can1_tx - can1_rx0 - can1_rx1 - can1_sce - exti9_5 - tim1_brk_tim9 - tim1_up_tim10 - tim1_trg_com_tim11 - tim1_cc - tim2 - tim3 - tim4 - i2c1_ev - i2c1_er - i2c2_ev - i2c2_er - spi1 - spi2 - usart1 - usart2 - usart3 - exti15_10 - rtc_alarm - usb_fs_wkup - tim8_brk_tim12 - tim8_up_tim13 - tim8_trg_com_tim14 - tim8_cc - dma1_stream7 - fsmc - sdio - tim5 - spi3 - uart4 - uart5 - tim6_dac - tim7 - dma2_stream0 - dma2_stream1 - dma2_stream2 - dma2_stream3 - dma2_stream4 - eth - eth_wkup - can2_tx - can2_rx0 - can2_rx1 - can2_sce - otg_fs - dma2_stream5 - dma2_stream6 - dma2_stream7 - usart6 - i2c3_ev - i2c3_er - otg_hs_ep1_out - otg_hs_ep1_in - otg_hs_wkup - otg_hs - dcmi - cryp - hash_rng hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/iwdg.h000066400000000000000000000022261435536612600235330ustar00rootroot00000000000000/** @defgroup iwdg_defines IWDG Defines @brief Defined Constants and Types for the STM32F2xx Independent Watchdog Timer @ingroup STM32F2xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_IWDG_H #define LIBOPENCM3_IWDG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/memorymap.h000066400000000000000000000135571435536612600246200ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_MEMORYMAP_H #define LIBOPENCM3_MEMORYMAP_H #include /* --- STM32F20x specific peripheral definitions --------------------------- */ /* Memory map for all busses */ #define PERIPH_BASE 0x40000000 #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) #define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) #define PERIPH_BASE_AHB2 0x50000000 #define PERIPH_BASE_AHB3 0x60000000 /* Register boundary addresses */ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) #define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) #define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) #define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) /* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ #define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) #define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) #define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) /* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ #define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) #define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) /* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) /* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ /* APB2 */ #define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) #define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) /* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ #define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) #define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) /* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ #define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) #define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000) #define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000) /* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ #define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) /* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */ #define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) #define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) #define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) #define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) #define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) /* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */ /* AHB1 */ #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) #define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) #define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) #define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) #define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) #define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) #define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) #define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) /* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ #define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) /* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ #define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) #define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) /* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ #define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) #define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) /* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ #define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) /* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ #define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) /* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ /* AHB2 */ #define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000) /* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ #define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) /* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ #define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) #define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) #define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) /* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ /* AHB3 */ #define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) /* PPIB */ #define DBGMCU_BASE (PPBI_BASE + 0x00042000) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/pwr.h000066400000000000000000000032151435536612600234100ustar00rootroot00000000000000/** @defgroup pwr_defines PWR Defines @brief Defined Constants and Types for the STM32F2xx PWR Control @ingroup STM32F2xx_defines @version 1.0.0 @date 4 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_PWR_F2_H #define LIBOPENCM3_PWR_F2_H #include /* * This file extends the common STM32 version with definitions only * applicable to the STM32F2 series of devices. */ /* --- PWR_CR values ------------------------------------------------------- */ /* Bits [31:10]: Reserved, always read as 0. */ /* FPDS: Flash power down in stop mode */ #define PWR_CR_FPDS (1 << 9) /* --- PWR_CSR values ------------------------------------------------------ */ /* Bits [31:10]: Reserved, always read as 0. */ /* BRE: Backup regulator enable */ #define PWR_CSR_BRE (1 << 9) /* Bits [7:4]: Reserved, always read as 0. */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/rcc.h000066400000000000000000000435121435536612600233530ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RCC_H #define LIBOPENCM3_RCC_H #include #include /* --- RCC registers ------------------------------------------------------- */ #define RCC_CR MMIO32(RCC_BASE + 0x00) #define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) #define RCC_CFGR MMIO32(RCC_BASE + 0x08) #define RCC_CIR MMIO32(RCC_BASE + 0x0c) #define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) #define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) #define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) /* RCC_BASE + 0x1c Reserved */ #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) /* RCC_BASE + 0x28 Reserved */ /* RCC_BASE + 0x2c Reserved */ #define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) #define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) #define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) /* RCC_BASE + 0x3c Reserved */ #define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) #define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) /* RCC_BASE + 0x48 Reserved */ /* RCC_BASE + 0x4c Reserved */ #define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) #define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) #define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) /* RCC_BASE + 0x5c Reserved */ #define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) #define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) /* RCC_BASE + 0x68 Reserved */ /* RCC_BASE + 0x6c Reserved */ #define RCC_BDCR MMIO32(RCC_BASE + 0x70) #define RCC_CSR MMIO32(RCC_BASE + 0x74) /* RCC_BASE + 0x78 Reserved */ /* RCC_BASE + 0x7c Reserved */ #define RCC_SSCGR MMIO32(RCC_BASE + 0x80) #define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) /* --- RCC_CR values ------------------------------------------------------- */ #define RCC_CR_PLLI2SRDY (1 << 27) #define RCC_CR_PLLI2SON (1 << 26) #define RCC_CR_PLLRDY (1 << 25) #define RCC_CR_PLLON (1 << 24) #define RCC_CR_CSSON (1 << 19) #define RCC_CR_HSEBYP (1 << 18) #define RCC_CR_HSERDY (1 << 17) #define RCC_CR_HSEON (1 << 16) /* HSICAL: [15:8] */ /* HSITRIM: [7:3] */ #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) /* --- RCC_PLLCFGR values -------------------------------------------------- */ /* PLLQ: [27:24] */ #define RCC_PLLCFGR_PLLQ_SHIFT 24 #define RCC_PLLCFGR_PLLSRC (1 << 22) /* PLLP: [17:16] */ #define RCC_PLLCFGR_PLLP_SHIFT 16 /* PLLN: [14:6] */ #define RCC_PLLCFGR_PLLN_SHIFT 6 /* PLLM: [5:0] */ #define RCC_PLLCFGR_PLLM_SHIFT 0 /* --- RCC_CFGR values ----------------------------------------------------- */ /* MCO2: Microcontroller clock output 2 */ #define RCC_CFGR_MCO2_SHIFT 30 #define RCC_CFGR_MCO2_SYSCLK 0x0 #define RCC_CFGR_MCO2_PLLI2S 0x1 #define RCC_CFGR_MCO2_HSE 0x2 #define RCC_CFGR_MCO2_PLL 0x3 /* MCO1/2PRE: MCO Prescalers */ #define RCC_CFGR_MCO2PRE_SHIFT 27 #define RCC_CFGR_MCO1PRE_SHIFT 24 #define RCC_CFGR_MCOPRE_DIV_NONE 0x0 #define RCC_CFGR_MCOPRE_DIV_2 0x4 #define RCC_CFGR_MCOPRE_DIV_3 0x5 #define RCC_CFGR_MCOPRE_DIV_4 0x6 #define RCC_CFGR_MCOPRE_DIV_5 0x7 /* I2SSRC: I2S clock selection */ #define RCC_CFGR_I2SSRC (1 << 23) /* MCO1: Microcontroller clock output 1 */ #define RCC_CFGR_MCO1_SHIFT 21 #define RCC_CFGR_MCO1_HSI 0x0 #define RCC_CFGR_MCO1_LSE 0x1 #define RCC_CFGR_MCO1_HSE 0x2 #define RCC_CFGR_MCO1_PLL 0x3 /* RTCPRE: HSE division factor for RTC clock */ #define RCC_CFGR_RTCPRE_SHIFT 21 /* PPRE1/2: APB high-speed prescalers */ #define RCC_CFGR_PPRE2_SHIFT 13 #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE_DIV_NONE 0x0 #define RCC_CFGR_PPRE_DIV_2 0x4 #define RCC_CFGR_PPRE_DIV_4 0x5 #define RCC_CFGR_PPRE_DIV_8 0x6 #define RCC_CFGR_PPRE_DIV_16 0x7 /* HPRE: AHB high-speed prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_DIV_NONE 0x0 #define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) #define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) #define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) #define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) #define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) #define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) #define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) #define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 #define RCC_CFGR_SWS_HSI 0x0 #define RCC_CFGR_SWS_HSE 0x1 #define RCC_CFGR_SWS_PLL 0x2 /* SW: System clock switch */ #define RCC_CFGR_SW_SHIFT 0 #define RCC_CFGR_SW_HSI 0x0 #define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_PLL 0x2 /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ #define RCC_CIR_CSSC (1 << 23) /* OSC ready interrupt clear bits */ #define RCC_CIR_PLLI2SRDYC (1 << 21) #define RCC_CIR_PLLRDYC (1 << 20) #define RCC_CIR_HSERDYC (1 << 19) #define RCC_CIR_HSIRDYC (1 << 18) #define RCC_CIR_LSERDYC (1 << 17) #define RCC_CIR_LSIRDYC (1 << 16) /* OSC ready interrupt enable bits */ #define RCC_CIR_PLLI2SRDYIE (1 << 13) #define RCC_CIR_PLLRDYIE (1 << 12) #define RCC_CIR_HSERDYIE (1 << 11) #define RCC_CIR_HSIRDYIE (1 << 10) #define RCC_CIR_LSERDYIE (1 << 9) #define RCC_CIR_LSIRDYIE (1 << 8) /* Clock security system interrupt flag bit */ #define RCC_CIR_CSSF (1 << 7) /* OSC ready interrupt flag bits */ #define RCC_CIR_PLLI2SRDYF (1 << 5) #define RCC_CIR_PLLRDYF (1 << 4) #define RCC_CIR_HSERDYF (1 << 3) #define RCC_CIR_HSIRDYF (1 << 2) #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) /* --- RCC_AHB1RSTR values ------------------------------------------------- */ #define RCC_AHB1RSTR_OTGHSRST (1 << 29) #define RCC_AHB1RSTR_ETHMACRST (1 << 25) #define RCC_AHB1RSTR_DMA2RST (1 << 22) #define RCC_AHB1RSTR_DMA1RST (1 << 21) #define RCC_AHB1RSTR_CRCRST (1 << 12) #define RCC_AHB1RSTR_IOPIRST (1 << 8) #define RCC_AHB1RSTR_IOPHRST (1 << 7) #define RCC_AHB1RSTR_IOPGRST (1 << 6) #define RCC_AHB1RSTR_IOPFRST (1 << 5) #define RCC_AHB1RSTR_IOPERST (1 << 4) #define RCC_AHB1RSTR_IOPDRST (1 << 3) #define RCC_AHB1RSTR_IOPCRST (1 << 2) #define RCC_AHB1RSTR_IOPBRST (1 << 1) #define RCC_AHB1RSTR_IOPARST (1 << 0) /* --- RCC_AHB2RSTR values ------------------------------------------------- */ #define RCC_AHB2RSTR_OTGFSRST (1 << 7) #define RCC_AHB2RSTR_RNGRST (1 << 6) #define RCC_AHB2RSTR_HASHRST (1 << 5) #define RCC_AHB2RSTR_CRYPRST (1 << 4) #define RCC_AHB2RSTR_DCMIRST (1 << 0) /* --- RCC_AHB3RSTR values ------------------------------------------------- */ #define RCC_AHB3RSTR_FSMCRST (1 << 0) /* --- RCC_APB1RSTR values ------------------------------------------------- */ #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) #define RCC_APB1RSTR_CAN2RST (1 << 26) #define RCC_APB1RSTR_CAN1RST (1 << 25) #define RCC_APB1RSTR_I2C3RST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) #define RCC_APB1RSTR_UART5RST (1 << 20) #define RCC_APB1RSTR_UART4RST (1 << 19) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) #define RCC_APB1RSTR_SPI3RST (1 << 15) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_TIM14RST (1 << 8) #define RCC_APB1RSTR_TIM13RST (1 << 7) #define RCC_APB1RSTR_TIM12RST (1 << 6) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM5RST (1 << 3) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) /* --- RCC_APB2RSTR values ------------------------------------------------- */ #define RCC_APB2RSTR_TIM11RST (1 << 18) #define RCC_APB2RSTR_TIM10RST (1 << 17) #define RCC_APB2RSTR_TIM9RST (1 << 16) #define RCC_APB2RSTR_SYSCFGRST (1 << 14) #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_SDIORST (1 << 11) #define RCC_APB2RSTR_ADCRST (1 << 8) #define RCC_APB2RSTR_USART6RST (1 << 5) #define RCC_APB2RSTR_USART1RST (1 << 4) #define RCC_APB2RSTR_TIM8RST (1 << 1) #define RCC_APB2RSTR_TIM1RST (1 << 0) /* --- RCC_AHB1ENR values ------------------------------------------------- */ #define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) #define RCC_AHB1ENR_OTGHSEN (1 << 29) #define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) #define RCC_AHB1ENR_ETHMACRXEN (1 << 27) #define RCC_AHB1ENR_ETHMACTXEN (1 << 26) #define RCC_AHB1ENR_ETHMACEN (1 << 25) #define RCC_AHB1ENR_DMA2EN (1 << 22) #define RCC_AHB1ENR_DMA1EN (1 << 21) #define RCC_AHB1ENR_BKPSRAMEN (1 << 18) #define RCC_AHB1ENR_CRCEN (1 << 12) #define RCC_AHB1ENR_IOPIEN (1 << 8) #define RCC_AHB1ENR_IOPHEN (1 << 7) #define RCC_AHB1ENR_IOPGEN (1 << 6) #define RCC_AHB1ENR_IOPFEN (1 << 5) #define RCC_AHB1ENR_IOPEEN (1 << 4) #define RCC_AHB1ENR_IOPDEN (1 << 3) #define RCC_AHB1ENR_IOPCEN (1 << 2) #define RCC_AHB1ENR_IOPBEN (1 << 1) #define RCC_AHB1ENR_IOPAEN (1 << 0) /* --- RCC_AHB2ENR values ------------------------------------------------- */ #define RCC_AHB2ENR_OTGFSEN (1 << 7) #define RCC_AHB2ENR_RNGEN (1 << 6) #define RCC_AHB2ENR_HASHEN (1 << 5) #define RCC_AHB2ENR_CRYPEN (1 << 4) #define RCC_AHB2ENR_DCMIEN (1 << 0) /* --- RCC_AHB3ENR values ------------------------------------------------- */ #define RCC_AHB3ENR_FSMCEN (1 << 0) /* --- RCC_APB1ENR values ------------------------------------------------- */ #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_CAN2EN (1 << 26) #define RCC_APB1ENR_CAN1EN (1 << 25) #define RCC_APB1ENR_I2C3EN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) #define RCC_APB1ENR_UART5EN (1 << 20) #define RCC_APB1ENR_UART4EN (1 << 19) #define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) #define RCC_APB1ENR_SPI3EN (1 << 15) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_TIM14EN (1 << 8) #define RCC_APB1ENR_TIM13EN (1 << 7) #define RCC_APB1ENR_TIM12EN (1 << 6) #define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM5EN (1 << 3) #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /* --- RCC_APB2ENR values ------------------------------------------------- */ #define RCC_APB2ENR_TIM11EN (1 << 18) #define RCC_APB2ENR_TIM10EN (1 << 17) #define RCC_APB2ENR_TIM9EN (1 << 16) #define RCC_APB2ENR_SYSCFGEN (1 << 14) #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_SDIOEN (1 << 11) #define RCC_APB2ENR_ADC3EN (1 << 10) #define RCC_APB2ENR_ADC2EN (1 << 9) #define RCC_APB2ENR_ADC1EN (1 << 8) #define RCC_APB2ENR_USART6EN (1 << 5) #define RCC_APB2ENR_USART1EN (1 << 4) #define RCC_APB2ENR_TIM8EN (1 << 1) #define RCC_APB2ENR_TIM1EN (1 << 0) /* --- RCC_AHB1LPENR values ------------------------------------------------- */ #define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) #define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) #define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) #define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) #define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) #define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) #define RCC_AHB1LPENR_DMA2LPEN (1 << 22) #define RCC_AHB1LPENR_DMA1LPEN (1 << 21) #define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) #define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) #define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) #define RCC_AHB1LPENR_FLITFLPEN (1 << 15) #define RCC_AHB1LPENR_CRCLPEN (1 << 12) #define RCC_AHB1LPENR_IOPILPEN (1 << 8) #define RCC_AHB1LPENR_IOPHLPEN (1 << 7) #define RCC_AHB1LPENR_IOPGLPEN (1 << 6) #define RCC_AHB1LPENR_IOPFLPEN (1 << 5) #define RCC_AHB1LPENR_IOPELPEN (1 << 4) #define RCC_AHB1LPENR_IOPDLPEN (1 << 3) #define RCC_AHB1LPENR_IOPCLPEN (1 << 2) #define RCC_AHB1LPENR_IOPBLPEN (1 << 1) #define RCC_AHB1LPENR_IOPALPEN (1 << 0) /* --- RCC_AHB2LPENR values ------------------------------------------------- */ #define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) #define RCC_AHB2LPENR_RNGLPEN (1 << 6) #define RCC_AHB2LPENR_HASHLPEN (1 << 5) #define RCC_AHB2LPENR_CRYPLPEN (1 << 4) #define RCC_AHB2LPENR_DCMILPEN (1 << 0) /* --- RCC_AHB3LPENR values ------------------------------------------------- */ #define RCC_AHB3LPENR_FSMCLPEN (1 << 0) /* --- RCC_APB1LPENR values ------------------------------------------------- */ #define RCC_APB1LPENR_DACLPEN (1 << 29) #define RCC_APB1LPENR_PWRLPEN (1 << 28) #define RCC_APB1LPENR_CAN2LPEN (1 << 26) #define RCC_APB1LPENR_CAN1LPEN (1 << 25) #define RCC_APB1LPENR_I2C3LPEN (1 << 23) #define RCC_APB1LPENR_I2C2LPEN (1 << 22) #define RCC_APB1LPENR_I2C1LPEN (1 << 21) #define RCC_APB1LPENR_UART5LPEN (1 << 20) #define RCC_APB1LPENR_UART4LPEN (1 << 19) #define RCC_APB1LPENR_USART3LPEN (1 << 18) #define RCC_APB1LPENR_USART2LPEN (1 << 17) #define RCC_APB1LPENR_SPI3LPEN (1 << 15) #define RCC_APB1LPENR_SPI2LPEN (1 << 14) #define RCC_APB1LPENR_WWDGLPEN (1 << 11) #define RCC_APB1LPENR_TIM14LPEN (1 << 8) #define RCC_APB1LPENR_TIM13LPEN (1 << 7) #define RCC_APB1LPENR_TIM12LPEN (1 << 6) #define RCC_APB1LPENR_TIM7LPEN (1 << 5) #define RCC_APB1LPENR_TIM6LPEN (1 << 4) #define RCC_APB1LPENR_TIM5LPEN (1 << 3) #define RCC_APB1LPENR_TIM4LPEN (1 << 2) #define RCC_APB1LPENR_TIM3LPEN (1 << 1) #define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* --- RCC_APB2LPENR values ------------------------------------------------- */ #define RCC_APB2LPENR_TIM11LPEN (1 << 18) #define RCC_APB2LPENR_TIM10LPEN (1 << 17) #define RCC_APB2LPENR_TIM9LPEN (1 << 16) #define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) #define RCC_APB2LPENR_SPI1LPEN (1 << 12) #define RCC_APB2LPENR_SDIOLPEN (1 << 11) #define RCC_APB2LPENR_ADC3LPEN (1 << 10) #define RCC_APB2LPENR_ADC2LPEN (1 << 9) #define RCC_APB2LPENR_ADC1LPEN (1 << 8) #define RCC_APB2LPENR_USART6LPEN (1 << 5) #define RCC_APB2LPENR_USART1LPEN (1 << 4) #define RCC_APB2LPENR_TIM8LPEN (1 << 1) #define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* --- RCC_BDCR values ----------------------------------------------------- */ #define RCC_BDCR_BDRST (1 << 16) #define RCC_BDCR_RTCEN (1 << 15) /* RCC_BDCR[9:8]: RTCSEL */ #define RCC_BDCR_LSEBYP (1 << 2) #define RCC_BDCR_LSERDY (1 << 1) #define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ #define RCC_CSR_LPWRRSTF (1 << 31) #define RCC_CSR_WWDGRSTF (1 << 30) #define RCC_CSR_IWDGRSTF (1 << 29) #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) #define RCC_CSR_BORRSTF (1 << 25) #define RCC_CSR_RMVF (1 << 24) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) /* --- RCC_SSCGR values ---------------------------------------------------- */ /* PLL spread spectrum clock generation documented in Datasheet. */ #define RCC_SSCGR_SSCGEN (1 << 31) #define RCC_SSCGR_SPREADSEL (1 << 30) /* RCC_SSCGR[27:16]: INCSTEP */ #define RCC_SSCGR_INCSTEP_SHIFT 16 /* RCC_SSCGR[15:0]: MODPER */ #define RCC_SSCGR_MODPER_SHIFT 15 /* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ /* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 /* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ #define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 /* --- Variable definitions ------------------------------------------------ */ extern uint32_t rcc_ppre1_frequency; extern uint32_t rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ typedef enum { CLOCK_3V3_120MHZ, CLOCK_3V3_END } clock_3v3_t; typedef struct { uint8_t pllm; uint16_t plln; uint8_t pllp; uint8_t pllq; uint32_t flash_config; uint8_t hpre; uint8_t ppre1; uint8_t ppre2; uint32_t apb1_frequency; uint32_t apb2_frequency; } clock_scale_t; extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END]; typedef enum { PLL, HSE, HSI, LSE, LSI } osc_t; BEGIN_DECLS void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); int rcc_osc_ready_int_flag(osc_t osc); void rcc_css_int_clear(void); int rcc_css_int_flag(void); void rcc_wait_for_osc_ready(osc_t osc); void rcc_wait_for_sysclk_status(osc_t osc); void rcc_osc_on(osc_t osc); void rcc_osc_off(osc_t osc); void rcc_css_enable(void); void rcc_css_disable(void); void rcc_osc_bypass_enable(osc_t osc); void rcc_osc_bypass_disable(osc_t osc); void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); void rcc_set_sysclk_source(uint32_t clk); void rcc_set_pll_source(uint32_t pllsrc); void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); void rcc_set_rtcpre(uint32_t rtcpre); void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq); void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq); uint32_t rcc_system_clock_source(void); void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); void rcc_backupdomain_reset(void); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/rng.h000066400000000000000000000015551435536612600233730ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RNG_H #define LIBOPENCM3_RNG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/rtc.h000066400000000000000000000021051435536612600233650ustar00rootroot00000000000000/** @defgroup rtc_defines RTC Defines @brief Defined Constants and Types for the STM32F2xx RTC @ingroup STM32F2xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RTC_H #define LIBOPENCM3_RTC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/spi.h000066400000000000000000000021031435536612600233660ustar00rootroot00000000000000/** @defgroup spi_defines SPI Defines @brief Defined Constants and Types for the STM32F2xx SPI @ingroup STM32F2xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SPI_H #define LIBOPENCM3_SPI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/syscfg.h000066400000000000000000000016661435536612600241060ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SYSCFG_H #define LIBOPENCM3_SYSCFG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/timer.h000066400000000000000000000022751435536612600237250ustar00rootroot00000000000000/** @defgroup timer_defines Timer Defines @brief libopencm3 Defined Constants and Types for the STM32F2xx Timers @ingroup STM32F2xx_defines @version 1.0.0 @date 8 March 2013 @author @htmlonly © @endhtmlonly 2011 Fergus Noble LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_TIMER_H #define LIBOPENCM3_TIMER_H #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f2/usart.h000066400000000000000000000021171435536612600237360ustar00rootroot00000000000000/** @defgroup usart_defines USART Defines @brief Defined Constants and Types for the STM32F2xx USART @ingroup STM32F2xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/000077500000000000000000000000001435536612600224275ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/adc.h000066400000000000000000000722141435536612600233350ustar00rootroot00000000000000/** @defgroup adc_defines ADC Defines * * @brief Defined Constants and Types for the STM32F3xx Analog to Digital * converter * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 ARCOS-Lab UCR * Copyright (C) 2013 Fernando Cortes * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H #include #include #define ADC1 ADC1_BASE #define ADC2 ADC2_BASE #define ADC3 ADC3_BASE #define ADC4 ADC4_BASE /* Master and slave ADCs common registers (ADC12 or ADC34) */ /*----------- ADC registers -------------------------------------- */ /* ADC interrupt and status register (ADCx_ISR, x=1..4) */ #define ADC_ISR(adc_base) MMIO32(adc_base + 0x00) #define ADC1_ISR ADC_ISR(ADC1_BASE) #define ADC2_ISR ADC_ISR(ADC2_BASE) #define ADC3_ISR ADC_ISR(ADC3_BASE) #define ADC4_ISR ADC_ISR(ADC4_BASE) /* Interrupt Enable Register (ADCx_IER, x=1..4) IER */ #define ADC_IER(adc_base) MMIO32(adc_base + 0x04) #define ADC1_IER ADC_IER(ADC1_BASE) #define ADC2_IER ADC_IER(ADC2_BASE) #define ADC3_IER ADC_IER(ADC3_BASE) #define ADC4_IER ADC_IER(ADC4_BASE) /* Control Register (ADCx_CR, x=1..4) CR */ #define ADC_CR(adc_base) MMIO32(adc_base + 0x08) #define ADC1_CR ADC_CR(ADC1_BASE) #define ADC2_CR ADC_CR(ADC2_BASE) #define ADC3_CR ADC_CR(ADC3_BASE) #define ADC4_CR ADC_CR(ADC4_BASE) /* Configuration Register (ADCx_CFGR, x=1..4) CFGR */ #define ADC_CFGR(adc_base) MMIO32(adc_base + 0x0C) #define ADC1_CFGR ADC_CFGR(ADC1_BASE) #define ADC2_CFGR ADC_CFGR(ADC2_BASE) #define ADC3_CFGR ADC_CFGR(ADC3_BASE) #define ADC4_CFGR ADC_CFGR(ADC4_BASE) /* Sample Time Register 1 (ADCx_SMPR1, x=1..4) SMPR1 */ #define ADC_SMPR1(adc_base) MMIO32(adc_base + 0x14) #define ADC1_SMPR1 ADC_SMPR1(ADC1_BASE) #define ADC2_SMPR1 ADC_SMPR1(ADC2_BASE) #define ADC3_SMPR1 ADC_SMPR1(ADC3_BASE) #define ADC4_SMPR1 ADC_SMPR1(ADC4_BASE) /* Sample Time Register 2 (ADCx_SMPR2, x=1..4) SMPR2 */ #define ADC_SMPR2(adc_base) MMIO32(adc_base + 0x18) #define ADC1_SMPR2 ADC_SMPR2(ADC1_BASE) #define ADC2_SMPR2 ADC_SMPR2(ADC2_BASE) #define ADC3_SMPR2 ADC_SMPR2(ADC3_BASE) #define ADC4_SMPR2 ADC_SMPR2(ADC4_BASE) /* Watchdog Threshold Register 1 (ADCx_TR1, x=1..4) TR1 */ #define ADC_TR1(adc_base) MMIO32(adc_base + 0x20) #define ADC1_TR1 ADC_TR1(ADC1_BASE) #define ADC2_TR1 ADC_TR1(ADC2_BASE) #define ADC3_TR1 ADC_TR1(ADC3_BASE) #define ADC4_TR1 ADC_TR1(ADC4_BASE) /* Watchdog Threshold Register 2 (ADCx_TR2, x=1..4) TR2 */ #define ADC_TR2(adc_base) MMIO32(adc_base + 0x24) #define ADC1_TR2 ADC_TR2(ADC1_BASE) #define ADC2_TR2 ADC_TR2(ADC2_BASE) #define ADC3_TR2 ADC_TR2(ADC3_BASE) #define ADC4_TR2 ADC_TR2(ADC4_BASE) /* Watchdog Threshold Register 3 (ADCx_TR3, x=1..4) TR3 */ #define ADC_TR3(adc_base) MMIO32(adc_base + 0x28) #define ADC1_TR3 ADC_TR3(ADC1_BASE) #define ADC2_TR3 ADC_TR3(ADC2_BASE) #define ADC3_TR3 ADC_TR3(ADC3_BASE) #define ADC4_TR3 ADC_TR3(ADC4_BASE) /* Regular Sequence Register 1 (ADCx_SQR1, x=1..4) SQR1 */ #define ADC_SQR1(adc_base) MMIO32(adc_base + 0x30) #define ADC1_SQR1 ADC_SQR1(ADC1_BASE) #define ADC2_SQR1 ADC_SQR1(ADC2_BASE) #define ADC3_SQR1 ADC_SQR1(ADC3_BASE) #define ADC4_SQR1 ADC_SQR1(ADC4_BASE) /* Regular Sequence Register 2 (ADCx_SQR2, x=1..4) SQR2 */ #define ADC_SQR2(adc_base) MMIO32(adc_base + 0x34) #define ADC1_SQR2 ADC_SQR2(ADC1_BASE) #define ADC2_SQR2 ADC_SQR2(ADC2_BASE) #define ADC3_SQR2 ADC_SQR2(ADC3_BASE) #define ADC4_SQR2 ADC_SQR2(ADC4_BASE) /* Regular Sequence Register 3 (ADCx_SQR3, x=1..4) SQR3 */ #define ADC_SQR3(adc_base) MMIO32(adc_base + 0x38) #define ADC1_SQR3 ADC_SQR3(ADC1_BASE) #define ADC2_SQR3 ADC_SQR3(ADC2_BASE) #define ADC3_SQR3 ADC_SQR3(ADC3_BASE) #define ADC4_SQR3 ADC_SQR3(ADC4_BASE) /* Regular Sequence Register 4 (ADCx_SQR3, x=1..4) SQR4 */ #define ADC_SQR4(adc_base) MMIO32(adc_base + 0x3C) #define ADC1_SQR4 ADC_SQR4(ADC1_BASE) #define ADC2_SQR4 ADC_SQR4(ADC2_BASE) #define ADC3_SQR4 ADC_SQR4(ADC3_BASE) #define ADC4_SQR4 ADC_SQR4(ADC4_BASE) /* regular Data Register (ADCx_DR, x=1..4) DR */ #define ADC_DR(adc_base) MMIO32(adc_base + 0x40) #define ADC1_DR ADC_DR(ADC1_BASE) #define ADC2_DR ADC_DR(ADC2_BASE) #define ADC3_DR ADC_DR(ADC3_BASE) #define ADC4_DR ADC_DR(ADC4_BASE) /* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ #define ADC_JSQR(adc_base) MMIO32(adc_base + 0x30) #define ADC1_JSQR ADC_JSQR(ADC1_BASE) #define ADC2_JSQR ADC_JSQR(ADC2_BASE) #define ADC3_JSQR ADC_JSQR(ADC3_BASE) #define ADC4_JSQR ADC_JSQR(ADC4_BASE) /* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ #define ADC_OFR1(adc_base) MMIO32(adc_base + 0x60) #define ADC1_OFR1 ADC_OFR1(ADC1_BASE) #define ADC2_OFR1 ADC_OFR1(ADC2_BASE) #define ADC3_OFR1 ADC_OFR1(ADC3_BASE) #define ADC4_OFR1 ADC_OFR1(ADC4_BASE) #define ADC_OFR2(adc_base) MMIO32(adc_base + 0x64) #define ADC1_OFR2 ADC_OFR2(ADC1_BASE) #define ADC2_OFR2 ADC_OFR2(ADC2_BASE) #define ADC3_OFR2 ADC_OFR2(ADC3_BASE) #define ADC4_OFR2 ADC_OFR2(ADC4_BASE) #define ADC_OFR3(adc_base) MMIO32(adc_base + 0x68) #define ADC1_OFR3 ADC_OFR3(ADC1_BASE) #define ADC2_OFR3 ADC_OFR3(ADC2_BASE) #define ADC3_OFR3 ADC_OFR3(ADC3_BASE) #define ADC4_OFR3 ADC_OFR3(ADC4_BASE) #define ADC_OFR4(adc_base) MMIO32(adc_base + 0x6C) #define ADC1_OFR4 ADC_OFR4(ADC1_BASE) #define ADC2_OFR4 ADC_OFR4(ADC2_BASE) #define ADC3_OFR4 ADC_OFR4(ADC3_BASE) #define ADC4_OFR4 ADC_OFR4(ADC4_BASE) /* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ #define ADC_JDR1(adc_base) MMIO32(adc_base + 0x80) #define ADC1_JDR1 ADC_JDR1(ADC1_BASE) #define ADC2_JDR1 ADC_JDR1(ADC2_BASE) #define ADC3_JDR1 ADC_JDR1(ADC3_BASE) #define ADC4_JDR1 ADC_JDR1(ADC4_BASE) #define ADC_JDR2(adc_base) MMIO32(adc_base + 0x84) #define ADC1_JDR2 ADC_JDR2(ADC1_BASE) #define ADC2_JDR2 ADC_JDR2(ADC2_BASE) #define ADC3_JDR2 ADC_JDR2(ADC3_BASE) #define ADC4_JDR2 ADC_JDR2(ADC4_BASE) #define ADC_JDR3(adc_base) MMIO32(adc_base + 0x88) #define ADC1_JDR3 ADC_JDR3(ADC1_BASE) #define ADC2_JDR3 ADC_JDR3(ADC2_BASE) #define ADC3_JDR3 ADC_JDR3(ADC3_BASE) #define ADC4_JDR3 ADC_JDR3(ADC4_BASE) #define ADC_JDR4(adc_base) MMIO32(adc_base + 0x8C) #define ADC1_JDR4 ADC_JDR4(ADC1_BASE) #define ADC2_JDR4 ADC_JDR4(ADC2_BASE) #define ADC3_JDR4 ADC_JDR4(ADC3_BASE) #define ADC4_JDR4 ADC_JDR4(ADC4_BASE) /* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ #define ADC_AWD2CR(adc_base) MMIO32(adc_base + 0xA0) #define ADC1_AWD2CR ADC_AWD2CR(ADC1_BASE) #define ADC2_AWD2CR ADC_AWD2CR(ADC2_BASE) #define ADC3_AWD2CR ADC_AWD2CR(ADC3_BASE) #define ADC4_AWD2CR ADC_AWD2CR(ADC4_BASE) /* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ #define ADC_AWD3CR(adc_base) MMIO32(adc_base + 0xA4) #define ADC1_AWD3CR ADC_AWD3CR(ADC1_BASE) #define ADC2_AWD3CR ADC_AWD3CR(ADC2_BASE) #define ADC3_AWD3CR ADC_AWD3CR(ADC3_BASE) #define ADC4_AWD3CR ADC_AWD3CR(ADC4_BASE) /* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ #define ADC_DIFSEL(adc_base) MMIO32(adc_base + 0xB0) #define ADC1_DIFSEL ADC_DIFSEL(ADC1_BASE) #define ADC2_DIFSEL ADC_DIFSEL(ADC2_BASE) #define ADC3_DIFSEL ADC_DIFSEL(ADC3_BASE) #define ADC4_DIFSEL ADC_DIFSEL(ADC4_BASE) /* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ #define ADC_CALFACT(adc_base) MMIO32(adc_base + 0xB4) #define ADC1_CALFACT ADC_CALFACT(ADC1_BASE) #define ADC2_CALFACT ADC_CALFACT(ADC2_BASE) #define ADC3_CALFACT ADC_CALFACT(ADC3_BASE) #define ADC4_CALFACT ADC_CALFACT(ADC4_BASE) /* ADC common (shared) registers */ #define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) #define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) #define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) #define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0xA) /*------- ADC_ISR values ---------*/ /* QOVF: Injected context queue overflow */ #define ADC_ISR_JQOVF (1 << 10) /* AWD3: Analog watchdog 3 flag */ #define ADC_ISR_AWD3 (1 << 9) /* AWD2: Analog watchdog 2 flag */ #define ADC_ISR_AWD2 (1 << 8) /* AWD1: Analog watchdog 1 flag */ #define ADC_ISR_AWD1 (1 << 7) /* JEOS: Injected channel end of sequence flag */ #define ADC_ISR_JEOS (1 << 6) /* JEOC: Injected channel end of conversion flag */ #define ADC_ISR_JEOC (1 << 5) /* OVR: ADC overrun */ #define ADC_ISR_OVR (1 << 4) /* EOS: End of regular sequence flag */ #define ADC_ISR_EOS (1 << 3) /* EOC: End of conversion flag */ #define ADC_ISR_EOC (1 << 2) /* EOSMP: End of sampling flag */ #define ADC_ISR_EOSMP (1 << 1) /* ADRDY: ADC ready */ #define ADC_ISR_ADRDY (1 << 0) /*------- ADC_IER values ---------*/ /* JQOVFIE: Injected context queue overflow interrupt enable */ #define ADC_IER_JQOVFIE (1 << 10) /* AWD3IE: Analog watchdog 3 interrupt enable */ #define ADC_IER_AWD3IE (1 << 9) /* AWD2IE: Analog watchdog 2 interrupt enable */ #define ADC_IER_AWD2IE (1 << 8) /* AWD1IE: Analog watchdog 1 interrupt enable */ #define ADC_IER_AWD1IE (1 << 7) /* JEOSIE: End of injected sequence of conversions interrupt enable */ #define ADC_IER_JEOSIE (1 << 6) /* JEOCIE: End of injected conversion interrupt enable */ #define ADC_IER_JEOCIE (1 << 5) /* OVRIE: Overrun interrupt enable */ #define ADC_IER_OVRIE (1 << 4) /* EOSIE: End of regular sequence of conversions interrupt enable */ #define ADC_IER_EOSIE (1 << 3) /* EOCIE: End of regular conversion interrupt enable */ #define ADC_IER_EOCIE (1 << 2) /* EOSMPIE: End of sampling flag interrupt enable for regular conversions */ #define ADC_IER_EOSMPIE (1 << 1) /* ADRDYIE : ADC ready interrupt enable */ #define ADC_IER_ADRDYIE (1 << 0) /*------- ADC_CR values ---------*/ /* ADCAL: ADC calibration */ #define ADC_CR_ADCAL (1 << 31) /* ADCALDIF: Differential mode for calibration */ #define ADC_CR_ADCALDIF (1 << 30) /* ADVREGEN: ADC voltage regulador enable */ #define ADC_CR_ADVREGEN_INTERMEDIATE (0x0 << 28) #define ADC_CR_ADVREGEN_ENABLE (0x1 << 28) #define ADC_CR_ADVREGEN_DISABLE (0x2 << 28) /* --- Bit 0x3 reserved --- */ /* JADSTP: ADC stop of injected conversion command */ #define ADC_CR_JADSTP (1 << 5) /* ADSTP: ADC stop of regular conversion command */ #define ADC_CR_ADSTP (1 << 4) /* JADSTART: ADC start of injected conversion */ #define ADC_CR_JADSTART (1 << 3) /* ADSTART: ADC start of regular conversion */ #define ADC_CR_ADSTART (1 << 2) /* ADDIS: ADC disable command */ #define ADC_CR_ADDIS (1 << 1) /* ADEN: ADC enable control */ #define ADC_CR_ADEN (1 << 0) /*------- ADC_CFGR values ---------*/ /* AWD1CH[4:0]: Analog watchdog 1 channel selection */ /* Bit 0x0 reserved */ #define ADC_CFGR_AWD1CH_ADC_IN_CH_1 (0x01 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_2 (0x02 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_3 (0x03 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_4 (0x04 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_5 (0x05 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_6 (0x06 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_7 (0x07 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_8 (0x08 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_9 (0x09 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_10 (0x0A << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_11 (0x0B << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_12 (0x0C << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_13 (0x0D << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_14 (0x0E << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_15 (0x0F << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_16 (0x10 << 26) #define ADC_CFGR_AWD1CH_ADC_IN_CH_17 (0x11 << 26) #define ADC_CFGR_AWD1CH_MASK (0x1F << 26) /* Ohters bits reserved, must not be used */ /* JAUTO: Autoamtic injected group conversion */ #define ADC_CFGR_JAUTO (1 << 25) /* JAWD1EN: Analog watchdog 1 enable on injected channels */ #define ADC_CFGR_JAWD1EN (1 << 24) /* AWD1EN: Analog watchdog 1 enable on regular channels */ #define ADC_CFGR_AWD1EN (1 << 23) /* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ #define ADC_CFGR_AWD1SGL (1 << 22) /* JQM: JSQR queue mode */ #define ADC_CFGR_JQM (1 << 21) /* JDISCEN: Discontinuous mode on injected channels */ #define ADC_CFGR_JDISCEN (1 << 20) /* DISCNUM[2:0]: Discontinuous mode channel count */ #define ADC_CFGR_DISCNUM_1_CH (0x0 << 17) #define ADC_CFGR_DISCNUM_2_CH (0x1 << 17) #define ADC_CFGR_DISCNUM_3_CH (0x2 << 17) #define ADC_CFGR_DISCNUM_4_CH (0x3 << 17) #define ADC_CFGR_DISCNUM_5_CH (0x4 << 17) #define ADC_CFGR_DISCNUM_6_CH (0x5 << 17) #define ADC_CFGR_DISCNUM_7_CH (0x6 << 17) #define ADC_CFGR_DISCNUM_8_CH (0x7 << 17) #define ADC_CFGR_DISCNUM_SHIFT 17 /* DISCEN: Discontinuous mode for regular channels */ #define ADC_CFGR_DISCEN (1 << 16) /* AUTDLY: Delayed conversion mode */ #define ADC_CFGR_AUTDLY (1 << 14) /* CONT: Single / continuous conversion mode for regular conversions */ #define ADC_CFGR_CONT (1 << 13) /* OVRMOD: Overrun Mode */ #define ADC_CFGR_OVRMOD (1 << 12) /* * EXTEN[1:0]: External trigger enable and polarity selection for regular * channels */ #define ADC_CFGR_EXTEN_DISABLED (0x0 << 10) #define ADC_CFGR_EXTEN_RISING_EDGE (0x1 << 10) #define ADC_CFGR_EXTEN_FALLING_EDGE (0x2 << 10) #define ADC_CFGR_EXTEN_BOTH_EDGES (0x3 << 10) #define ADC_CFGR_EXTEN_MASK (0x3 << 10) /* EXTSEL[3:0]: External trigger selection for regular group */ #define ADC_CFGR_EXTSEL_EVENT_0 (0x0 << 6) #define ADC_CFGR_EXTSEL_EVENT_1 (0x1 << 6) #define ADC_CFGR_EXTSEL_EVENT_2 (0x2 << 6) #define ADC_CFGR_EXTSEL_EVENT_3 (0x3 << 6) #define ADC_CFGR_EXTSEL_EVENT_4 (0x4 << 6) #define ADC_CFGR_EXTSEL_EVENT_5 (0x5 << 6) #define ADC_CFGR_EXTSEL_EVENT_6 (0x6 << 6) #define ADC_CFGR_EXTSEL_EVENT_7 (0x7 << 6) #define ADC_CFGR_EXTSEL_EVENT_8 (0x8 << 6) #define ADC_CFGR_EXTSEL_EVENT_9 (0x9 << 6) #define ADC_CFGR_EXTSEL_EVENT_10 (0xA << 6) #define ADC_CFGR_EXTSEL_EVENT_11 (0xB << 6) #define ADC_CFGR_EXTSEL_EVENT_12 (0xC << 6) #define ADC_CFGR_EXTSEL_EVENT_13 (0xD << 6) #define ADC_CFGR_EXTSEL_EVENT_14 (0xE << 6) #define ADC_CFGR_EXTSEL_EVENT_15 (0xF << 6) #define ADC_CFGR_EXTSEL_MASK (0xF << 6) /* ALIGN: Data alignment */ #define ADC_CFGR_ALIGN (1 << 5) /* RES[1:0]: Data resolution */ #define ADC_CFGR_RES_12_BIT (0x0 << 3) #define ADC_CFGR_RES_10_BIT (0x1 << 3) #define ADC_CFGR_RES_8_BIT (0x2 << 3) #define ADC_CFGR_RES_6_BIT (0x3 << 3) #define ADC_CFGR_RES_MASK (0x3 << 3) /* DMACFG: Direct memory access configuration */ #define ADC_CFGR_DMACFG (1 << 1) /* DMAEN: Direct memory access enable */ #define ADC_CFGR_DMAEN (1 << 0) /*------- ADC_SMPR1 values ---------*/ #define ADC_SMPR1_SMP8_LSB 24 #define ADC_SMPR1_SMP7_LSB 21 #define ADC_SMPR1_SMP6_LSB 18 #define ADC_SMPR1_SMP5_LSB 15 #define ADC_SMPR1_SMP4_LSB 12 #define ADC_SMPR1_SMP3_LSB 9 #define ADC_SMPR1_SMP2_LSB 6 #define ADC_SMPR1_SMP1_LSB 3 #define ADC_SMPR1_SMP8_MSK (0x7 << ADC_SMP8_LSB) #define ADC_SMPR1_SMP7_MSK (0x7 << ADC_SMP7_LSB) #define ADC_SMPR1_SMP6_MSK (0x7 << ADC_SMP6_LSB) #define ADC_SMPR1_SMP5_MSK (0x7 << ADC_SMP5_LSB) #define ADC_SMPR1_SMP4_MSK (0x7 << ADC_SMP4_LSB) #define ADC_SMPR1_SMP3_MSK (0x7 << ADC_SMP3_LSB) #define ADC_SMPR1_SMP2_MSK (0x7 << ADC_SMP2_LSB) #define ADC_SMPR1_SMP1_MSK (0x7 << ADC_SMP1_LSB) /****************************************************************************/ /* ADC_SMPR1 ADC Sample Time Selection for Channels */ /** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1 @ingroup adc_defines @{*/ #define ADC_SMPR1_SMP_1DOT5CYC 0x0 #define ADC_SMPR1_SMP_2DOT5CYC 0x1 #define ADC_SMPR1_SMP_4DOT5CYC 0x2 #define ADC_SMPR1_SMP_7DOT5CYC 0x3 #define ADC_SMPR1_SMP_19DOT5CYC 0x4 #define ADC_SMPR1_SMP_61DOT5CYC 0x5 #define ADC_SMPR1_SMP_181DOT5CYC 0x6 #define ADC_SMPR1_SMP_601DOT5CYC 0x7 /**@}*/ /* SMPx[2:0]: Channel x sampling time selection */ /*------- ADC_SMPR2 values ---------*/ /* SMPx[2:0]: Channel x sampling time selection */ /*------- ADC_TR1 values ---------*/ /* Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold */ /* Bit 11:0 LT1[11:0]: Analog watchdog 1 lower threshold */ /*------- ADC_T2 values ---------*/ /* Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold */ /* Bit 7:0 LT2[7:0]: Analog watchdog 2 lower threshold */ /*------- ADC_T3 values ---------*/ /* Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold */ /* Bit 7:0 LT3[7:0]: Analog watchdog 3 lower threshold */ /*------- ADC_SQR1 values ---------*/ #define ADC_SQR1_L_LSB 0 #define ADC_SQR1_SQ1_LSB 6 #define ADC_SQR1_SQ2_LSB 12 #define ADC_SQR1_SQ3_LSB 18 #define ADC_SQR1_SQ4_LSB 24 #define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) #define ADC_SQR1_SQ1_MSK (0x1f << ADC_SQR1_SQ1_LSB) #define ADC_SQR1_SQ2_MSK (0x1f << ADC_SQR1_SQ2_LSB) #define ADC_SQR1_SQ3_MSK (0x1f << ADC_SQR1_SQ3_LSB) #define ADC_SQR1_SQ4_MSK (0x1f << ADC_SQR1_SQ4_LSB) /* Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence */ /* Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence */ /* Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence */ /* Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence */ /* L[3:0]: Regular channel sequence length */ #define ADC_SQR1_L_1_CONVERSION (0x0 << 0) #define ADC_SQR1_L_2_CONVERSION (0x1 << 0) #define ADC_SQR1_L_3_CONVERSION (0x2 << 0) #define ADC_SQR1_L_4_CONVERSION (0x3 << 0) #define ADC_SQR1_L_5_CONVERSION (0x4 << 0) #define ADC_SQR1_L_6_CONVERSION (0x5 << 0) #define ADC_SQR1_L_7_CONVERSION (0x6 << 0) #define ADC_SQR1_L_8_CONVERSION (0x7 << 0) #define ADC_SQR1_L_9_CONVERSION (0x8 << 0) #define ADC_SQR1_L_10_CONVERSION (0x9 << 0) #define ADC_SQR1_L_11_CONVERSION (0xA << 0) #define ADC_SQR1_L_12_CONVERSION (0xB << 0) #define ADC_SQR1_L_13_CONVERSION (0xC << 0) #define ADC_SQR1_L_14_CONVERSION (0xD << 0) #define ADC_SQR1_L_15_CONVERSION (0xE << 0) #define ADC_SQR1_L_16_CONVERSION (0xF << 0) /*------- ADC_SQR2 values ---------*/ /* Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence */ /* Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence */ /* Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence */ /* Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence */ /* Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence */ /*------- ADC_SQR3 values ---------*/ /* Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence */ /* Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence */ /* Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence */ /* Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence */ /* Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence */ /*------- ADC_SQR4 values ---------*/ /* Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence */ /* Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence */ /*------- ADC_DR values ---------*/ /* Bits 15:0 RDATA[15:0]: Regular Data converted */ /*------- ADC_JSQR values ---------*/ #define ADC_JSQR_JL_LSB 0 #define ADC_JSQR_JSQ4_LSB 26 #define ADC_JSQR_JSQ3_LSB 20 #define ADC_JSQR_JSQ2_LSB 14 #define ADC_JSQR_JSQ1_LSB 8 /* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */ /* Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence */ /* Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence */ /* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */ /* * JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected * channels */ #define ADC_JSQR_JEXTEN_DISABLED (0x0 << 6) #define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 6) #define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 6) #define ADC_JSQR_JEXTEN_BOTH_EDGES (0x3 << 6) #define ADC_JSQR_JEXTEN_MASK (0x3 << 6) /* JEXTSEL[3:0]: External Trigger Selection for injected group */ #define ADC_JSQR_JEXTSEL_EVENT_0 (0x0 << 2) #define ADC_JSQR_JEXTSEL_EVENT_1 (0x1 << 2) #define ADC_JSQR_JEXTSEL_EVENT_2 (0x2 << 2) #define ADC_JSQR_JEXTSEL_EVENT_3 (0x3 << 2) #define ADC_JSQR_JEXTSEL_EVENT_4 (0x4 << 2) #define ADC_JSQR_JEXTSEL_EVENT_5 (0x5 << 2) #define ADC_JSQR_JEXTSEL_EVENT_6 (0x6 << 2) #define ADC_JSQR_JEXTSEL_EVENT_7 (0x7 << 2) #define ADC_JSQR_JEXTSEL_EVENT_8 (0x8 << 2) #define ADC_JSQR_JEXTSEL_EVENT_9 (0x9 << 2) #define ADC_JSQR_JEXTSEL_EVENT_10 (0xA << 2) #define ADC_JSQR_JEXTSEL_EVENT_11 (0xB << 2) #define ADC_JSQR_JEXTSEL_EVENT_12 (0xC << 2) #define ADC_JSQR_JEXTSEL_EVENT_13 (0xD << 2) #define ADC_JSQR_JEXTSEL_EVENT_14 (0xE << 2) #define ADC_JSQR_JEXTSEL_EVENT_15 (0xF << 2) #define ADC_JSQR_JEXTSEL_MASK (0xF << 2) /* JL[1:0]: Injected channel sequence length */ #define ADC_JSQR_JL_1_CONVERSION (0x0 << 0) #define ADC_JSQR_JL_2_CONVERSIONS (0x1 << 0) #define ADC_JSQR_JL_3_CONVERSIONS (0x2 << 0) #define ADC_JSQR_JL_4_CONVERSIONS (0x3 << 0) /*------- ADC_OFR1 values ---------*/ /* OFFSET1_EN: Offset 1 Enable */ #define ADC_OFR1_OFFSET1_EN (1 << 31) /* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */ /* * Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits * OFFSET1_CH[4:0] */ /*------- ADC_OFR2 values ---------*/ /* OFFSET2_EN: Offset 2 Enable */ #define ADC_OFR2_OFFSET2_EN (1 << 31) /* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */ /* * Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits * OFFSET2_CH[4:0] */ /*------- ADC_OFR3 values ---------*/ /* OFFSET3_EN: Offset 3 Enable */ #define ADC_OFR3_OFFSET3_EN (1 << 31) /* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */ /* * Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits * OFFSET3_CH[4:0] */ /*------- ADC_OFR4 values ---------*/ /* OFFSET4_EN: Offset 4 Enable */ #define ADC_OFR4_OFFSET4_EN (1 << 31) /* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */ /* * Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits * OFFSET4_CH[4:0] */ /*------- ADC_JDRy, y= 1..4 values -------*/ /* Bits 15:0 JDATA[15:0]: Injected data */ /*------- ADC_AWD2CR values ---------*/ /* Bits 18:1 AWD2CH[18:1]: Analog watchdog 2 channel selection */ /*------- ADC_AWD3CR values ---------*/ /* Bits 18:1 AWD3CH[18:1]: Analog watchdog 3 channel selection */ /*------- ADC_DIFSEL values ---------*/ /* DIFSEL[18:16]: Differential mode for channels 18 to 16. */ /* Bits 15:1 DIFSEL[15:1]: Differential mode for channels 15 to 1 */ /*------- ADC_CALFACT values ---------*/ /* Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode */ /* Bits 6:0 CALFACT_S[6:0]: Calibration Factors In Single-Ended mode */ /*--------------- ADC_CSR values ------------------------*/ /* Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC */ #define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC */ #define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC */ #define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC */ #define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC */ #define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC */ #define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 20 OVR_SLV: Overrun flag of the slave ADC */ #define ADC_CSR_OVR_SLV (1 << 20) /* Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC */ #define ADC_CSR_EOS_SLV (1 << 19) /* Bit 18 EOC_SLV: End of regular conversion of the slave ADC */ #define ADC_CSR_EOC_SLV (1 << 18) /* Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC */ #define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 16 ADRDY_SLV: Slave ADC ready */ #define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC */ #define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC */ #define ADC_CSR_AWD3_MST (1 << 9) /* Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC */ #define ADC_CSR_AWD2_MST (1 << 8) /* Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC */ #define ADC_CSR_AWD1_MST (1 << 7) /* Bit 6 JEOS_MST: End of injected sequence flag of the master ADC */ #define ADC_CSR_JEOS_MST (1 << 6) /* Bit 5 JEOC_MST: End of injected conversion flag of the master ADC */ #define ADC_CSR_JEOC_MST (1 << 5) /* Bit 4 OVR_MST: Overrun flag of the master ADC */ #define ADC_CSR_OVR_MST (1 << 4) /* Bit 3 EOS_MST: End of regular sequence flag of the master ADC */ #define ADC_CSR_EOS_MST (1 << 3) /* Bit 2 EOC_MST: End of regular conversion of the master ADC */ #define ADC_CSR_EOC_MST (1 << 2) /* Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC */ #define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 0 ADRDY_MST: Master ADC ready */ #define ADC_CSR_ADRDY_MST (1 << 0) /*-------- ADC_CCR values ------------*/ /* VBATEN: VBAT enable */ #define ADC_CCR_VBATEN (1 << 24) /* TSEN: Temperature sensor enable */ #define ADC_CCR_TSEN (1 << 23) /* VREFEN: VREFINT enable */ #define ADC_CCR_VREFEN (1 << 22) /* CKMODE[1:0]: ADC clock mode */ #define ADC_CCR_CKMODE_CKX (0x0 << 16) #define ADC_CCR_CKMODE_DIV1 (0x1 << 16) #define ADC_CCR_CKMODE_DIV2 (0x2 << 16) #define ADC_CCR_CKMODE_DIV4 (0x3 << 16) #define ADC_CCR_CKMODE_MASK (0x3 << 16) /* MDMA[1:0]: Direct memory access mode for dual ADC mode */ #define ADC_CCR_MDMA_DISABLE (0x0 << 14) /*#define ADC_CCR_MDMA_RESERVED (0x1 << 14)*/ #define ADC_CCR_MDMA_12_10_BIT (0x2 << 14) #define ADC_CCR_MDMA_8_6_BIT (0x3 << 14) /* DMACFG: DMA configuration (for dual ADC mode) */ #define ADC_CCR_DMACFG (1 << 13) /* DELAY: Delay between 2 sampling phases */ #define ADC_CCR_DELAY_SHIFT 8 /* DUAL[4:0]: Dual ADC mode selection */ #define ADC_CCR_DUAL_SHIFT 0 /*---------------- ADC_CDR values -----------------*/ /* Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC */ /* Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. */ BEGIN_DECLS void adc_power_on(uint32_t adc); void adc_off(uint32_t adc); void adc_enable_analog_watchdog_regular(uint32_t adc); void adc_disable_analog_watchdog_regular(uint32_t adc); void adc_enable_analog_watchdog_injected(uint32_t adc); void adc_disable_analog_watchdog_injected(uint32_t adc); void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); void adc_disable_discontinuous_mode_regular(uint32_t adc); void adc_enable_discontinuous_mode_injected(uint32_t adc); void adc_disable_discontinuous_mode_injected(uint32_t adc); void adc_enable_automatic_injected_group_conversion(uint32_t adc); void adc_disable_automatic_injected_group_conversion(uint32_t adc); void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel); /*void adc_enable_scan_mode(uint32_t adc);*/ /*void adc_disable_scan_mode(uint32_t adc);*/ void adc_enable_eoc_interrupt_injected(uint32_t adc); void adc_disable_eoc_interrupt_injected(uint32_t adc); void adc_enable_all_awd_interrupt(uint32_t adc); void adc_disable_all_awd_interrupt(uint32_t adc); void adc_enable_eoc_interrupt(uint32_t adc); void adc_disable_eoc_interrupt(uint32_t adc); void adc_start_conversion_regular(uint32_t adc); void adc_start_conversion_injected(uint32_t adc); void adc_disable_external_trigger_regular(uint32_t adc); void adc_disable_external_trigger_injected(uint32_t adc); void adc_set_left_aligned(uint32_t adc); void adc_set_right_aligned(uint32_t adc); void adc_enable_dma(uint32_t adc); void adc_disable_dma(uint32_t adc); void adc_set_continuous_conversion_mode(uint32_t adc); void adc_set_single_conversion_mode(uint32_t adc); void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold); void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold); void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); bool adc_eoc(uint32_t adc); bool adc_eoc_injected(uint32_t adc); uint32_t adc_read_regular(uint32_t adc); uint32_t adc_read_injected(uint32_t adc, uint8_t reg); void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); void adc_set_clk_prescale(uint32_t prescaler); void adc_set_multi_mode(uint32_t mode); void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity); void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity); void adc_set_resolution(uint32_t adc, uint16_t resolution); void adc_enable_overrun_interrupt(uint32_t adc); void adc_disable_overrun_interrupt(uint32_t adc); bool adc_get_overrun_flag(uint32_t adc); void adc_clear_overrun_flag(uint32_t adc); bool adc_awd(uint32_t adc); void adc_eoc_after_each(uint32_t adc); void adc_eoc_after_group(uint32_t adc); /*void adc_set_dma_continue(uint32_t adc);*/ /*void adc_set_dma_terminate(uint32_t adc);*/ void adc_enable_temperature_sensor(void); void adc_disable_temperature_sensor(void); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/crc.h000066400000000000000000000042761435536612600233600ustar00rootroot00000000000000/** @defgroup crc_defines CRC Defines * * @brief Defined Constants and Types for the STM32F3xx CRC Generator * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 18 August 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRC_H #define LIBOPENCM3_CRC_H #include #include /* --- CRC registers ------------------------------------------------------- */ /* Initial CRC value (CRC_INIT) */ #define CRC_INIT MMIO32(CRC_BASE + 0x10) /* CRC polynomial (CRC_POL) */ #define CRC_POL MMIO32(CRC_BASE + 0x14) /* --- CRC_CR values ------------------------------------------------------- */ /* REV_OUT: Reverse output data */ #define CRC_CR_REV_OUT (1 << 7) /* REV_IN[1:0]: Reverse input data */ #define CRC_CR_REV_IN_NOT_AFFECTED (0x0 << 5) #define CRC_CR_REV_IN_BYTE (0x1 << 5) #define CRC_CR_REV_IN_HALF_WORD (0x2 << 5) #define CRC_CR_REV_IN_WORD (0x3 << 5) /* POLYSIZE[1:0]: Polynomial size */ #define CRC_CR_POLYSIZE_32 (0x0 << 3) #define CRC_CR_POLYSIZE_16 (0x1 << 3) #define CRC_CR_POLYSIZE_8 (0x2 << 3) #define CRC_CR_POLYSIZE_7 (0x3 << 3) /* --- CRC_INIT values ----------------------------------------------------- */ /* Bits 31:0 CRC_INIT: Programmable initial CRC value */ /* --- CRC_POL values ------------------------------------------------------ */ /* Bits 31:0 POL[31:0]: Programmable polynomial */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/dac.h000066400000000000000000000021341435536612600233270ustar00rootroot00000000000000/** @defgroup dac_defines DAC Defines * * @brief Defined Constants and Types for the STM32F3xx DAC * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 5 December 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DAC_H #define LIBOPENCM3_DAC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/dma.h000066400000000000000000000021531435536612600233420ustar00rootroot00000000000000/** @defgroup dma_defines DMA Defines * * @ingroup STM32F3xx_defines * * @brief Defined Constants and Types for the STM32F3xx DMA Controller * * @version 1.0.0 * * @date 30 November 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DMA_H #define LIBOPENCM3_DMA_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/doc-stm32f3.h000066400000000000000000000011221435536612600245400ustar00rootroot00000000000000/** @mainpage libopencm3 STM32F3 * * @version 1.0.0 * * @date 11 July 2013 * * API documentation for ST Microelectronics STM32F3 Cortex M3 series. * * LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F3xx STM32F3xx * Libraries for ST Microelectronics STM32F3xx series. * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F3xx_defines STM32F3xx Defines * * @brief Defined Constants and Types for the STM32F3xx series * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/exti.h000066400000000000000000000030211435536612600235450ustar00rootroot00000000000000/** @defgroup exti_defines EXTI Defines * * @brief Defined Constants and Types for the STM32F3xx External Interrupts * * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_EXTI_H #define LIBOPENCM3_EXTI_H #include #include /* --- EXTI registers ------------------------------------------------------ */ #define EXTI_IMR2 MMIO32(EXTI_BASE + 0x18) #define EXTI_EMR2 MMIO32(EXTI_BASE + 0x1C) #define EXTI_RTSR2 MMIO32(EXTI_BASE + 0x20) #define EXTI_FTSR2 MMIO32(EXTI_BASE + 0x24) #define EXTI_SWIER2 MMIO32(EXTI_BASE + 0x28) #define EXTI_PR2 MMIO32(EXTI_BASE + 0x2C) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/flash.h000066400000000000000000000043701435536612600237010ustar00rootroot00000000000000/** @defgroup flash_defines FLASH Defines * * @brief Defined Constants and Types for the STM32F3xx Flash * controller * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_FLASH_H #define LIBOPENCM3_FLASH_H #include #include /* --- FLASH registers ----------------------------------------------------- */ #define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) #define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) #define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) /* --- FLASH_ACR values ---------------------------------------------------- */ #define FLASH_ACR_PRFTBS (1 << 5) #define FLASH_ACR_PRFTBE (1 << 4) #define FLASH_ACR_HLFCYA (1 << 3) /* --- FLASH_SR values ----------------------------------------------------- */ #define FLASH_SR_BSY (1 << 0) #define FLASH_SR_ERLYBSY (1 << 1) #define FLASH_SR_PGPERR (1 << 2) #define FLASH_SR_WRPRTERR (1 << 4) #define FLASH_SR_EOP (1 << 5) /* --- FLASH_CR values ----------------------------------------------------- */ #define FLASH_CR_OBL_LAUNCH (1 << 13) #define FLASH_CR_EOPIE (1 << 12) #define FLASH_CR_ERRIE (1 << 10) #define FLASH_CR_OPTWRE (1 << 9) #define FLASH_CR_LOCK (1 << 7) #define FLASH_CR_STRT (1 << 6) #define FLASH_CR_OPTER (1 << 5) #define FLASH_CR_OPTPG (1 << 4) #define FLASH_CR_MER (1 << 2) #define FLASH_CR_PER (1 << 1) #define FLASH_CR_PG (1 << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/gpio.h000066400000000000000000000021611435536612600235360ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines * * @brief Defined Constants and Types for the STM32F3xx General Purpose * I/O * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 1 July 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_GPIO_H #define LIBOPENCM3_GPIO_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/i2c.h000066400000000000000000000330651435536612600232640ustar00rootroot00000000000000/** @defgroup i2c_defines I2C Defines * * @brief Defined Constants and Types for the STM32F3xx I2C * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 12 October 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_I2C_H #define LIBOPENCM3_I2C_H #include #include /**@{*/ /* --- Convenience macros -------------------------------------------------- */ /* I2C register base addresses (for convenience) */ /*****************************************************************************/ /** @defgroup i2c_reg_base I2C register base address * @ingroup i2c_defines * @{*/ #define I2C1 I2C1_BASE #define I2C2 I2C2_BASE /**@}*/ /* --- I2C registers ------------------------------------------------------- */ /* Control register 1 (I2Cx_CR1) */ #define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) #define I2C1_CR1 I2C_CR1(I2C1) #define I2C2_CR1 I2C_CR1(I2C2) /* Control register 2 (I2Cx_CR2) */ #define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) #define I2C1_CR2 I2C_CR2(I2C1) #define I2C2_CR2 I2C_CR2(I2C2) /* Own address register 1 (I2Cx_OAR1) */ #define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) #define I2C1_OAR1 I2C_OAR1(I2C1) #define I2C2_OAR1 I2C_OAR1(I2C2) /* Own address register 2 (I2Cx_OAR2) */ #define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) #define I2C1_OAR2 I2C_OAR2(I2C1) #define I2C2_OAR2 I2C_OAR2(I2C2) /* Timing register (I2Cx_TIMINGR) */ #define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10) #define I2C1_TIMINGR I2C_TIMINGR(I2C1) #define I2C2_TIMINGR I2C_TIMINGR(I2C2) /* Timeout register (I2Cx_TIMEOUTR) */ #define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14) #define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) #define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) /* Interrupt and Status register (I2Cx_ISR) */ #define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18) #define I2C1_ISR I2C_ISR(I2C1) #define I2C2_ISR I2C_ISR(I2C2) /* Interrupt clear register (I2Cx_ICR) */ #define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C) #define I2C1_ICR I2C_ICR(I2C1) #define I2C2_ICR I2C_ICR(I2C2) /* PEC register (I2Cx_PECR) */ #define I2C_PECR(i2c_base) MMIO32(i2c_base + 0x20) #define I2C1_PECR I2C_PECR(I2C1) #define I2C2_PECR I2C_PECR(I2C2) /* Receive data register (I2Cx_RXDR) */ #define I2C_RXDR(i2c_base) MMIO32(i2c_base + 0x24) #define I2C1_RXDR I2C_RXDR(I2C1) #define I2C2_RXDR I2C_RXDR(I2C2) /* Transmit data register (I2Cx_TXDR) */ #define I2C_TXDR(i2c_base) MMIO32(i2c_base + 0x28) #define I2C1_TXDR I2C_TXDR(I2C1) #define I2C2_TXDR I2C_TXDR(I2C2) /* --- I2Cx_CR1 values ----------------------------------------------------- */ /* PECEN: PEC enable */ #define I2C_CR1_PECEN (1 << 23) /* ALERTEN: SMBus alert enable */ #define I2C_CR1_ALERTEN (1 << 22) /* SMBDEN: SMBus Device Default address enable */ #define I2C_CR1_SMBDEN (1 << 21) /* SMBHEN: SMBus Host address enable */ #define I2C_CR1_SMBHEN (1 << 20) /* GCEN: General call enable */ #define I2C_CR1_GCEN (1 << 19) /* WUPEN: Wakeup from STOP enable */ #define I2C_CR1_WUPEN (1 << 18) /* NOSTRETCH: Clock stretching disable */ #define I2C_CR1_NOSTRETCH (1 << 17) /* SBC: Slave byte control */ #define I2C_CR1_SBC (1 << 16) /* RXDMAEN: DMA reception requests enable */ #define I2C_CR1_RXDMAEN (1 << 15) /* TXDMAEN: DMA transmission requests enable */ #define I2C_CR1_TXDMAEN (1 << 14) /* ANFOFF: Analog noise filter OFF */ #define I2C_CR1_ANFOFF (1 << 12) /* DNF[3:0]: Digital noise filter */ #define I2C_CR1_DNF_DISABLED (0x0 << 8) #define I2C_CR1_DNF_UP_1_TI2CCLK (0x1 << 8) #define I2C_CR1_DNF_UP_2_TI2CCLK (0x2 << 8) #define I2C_CR1_DNF_UP_3_TI2CCLK (0x3 << 8) #define I2C_CR1_DNF_UP_4_TI2CCLK (0x4 << 8) #define I2C_CR1_DNF_UP_5_TI2CCLK (0x5 << 8) #define I2C_CR1_DNF_UP_6_TI2CCLK (0x6 << 8) #define I2C_CR1_DNF_UP_7_TI2CCLK (0x7 << 8) #define I2C_CR1_DNF_UP_8_TI2CCLK (0x8 << 8) #define I2C_CR1_DNF_UP_9_TI2CCLK (0x9 << 8) #define I2C_CR1_DNF_UP_10_TI2CCLK (0xA << 8) #define I2C_CR1_DNF_UP_11_TI2CCLK (0xB << 8) #define I2C_CR1_DNF_UP_12_TI2CCLK (0xC << 8) #define I2C_CR1_DNF_UP_13_TI2CCLK (0xD << 8) #define I2C_CR1_DNF_UP_14_TI2CCLK (0xE << 8) #define I2C_CR1_DNF_UP_15_TI2CCLK (0xF << 8) #define I2C_CR1_DNF_MASK (0xF << 8) /* ERRIE: Error interrupts enable */ #define I2C_CR1_ERRIE (1 << 7) /* TCIE: Transfer Complete interrupt enable */ #define I2C_CR1_TCIE (1 << 6) /* STOPIE: STOP detection Interrupt enable */ #define I2C_CR1_STOPIE (1 << 5) /* NACKIE: Not acknowledge received Interrupt enable */ #define I2C_CR1_NACKIE (1 << 4) /* ADDRIE: Address match Interrupt enable (slave only) */ #define I2C_CR1_DDRIE (1 << 3) /* RXIE: RX Interrupt enable */ #define I2C_CR1_RXIE (1 << 2) /* TXIE: TX Interrupt enable */ #define I2C_CR1_TXIE (1 << 1) /* PE: Peripheral enable */ #define I2C_CR1_PE (1 << 0) /* --- I2Cx_CR2 values ----------------------------------------------------- */ /* PECBYTE: Packet error checking byte */ #define I2C_CR2_PECBYTE (1 << 26) /* AUTOEND: Automatic end mode (master mode) */ #define I2C_CR2_AUTOEND (1 << 25) /* RELOAD: NBYTES reload mode */ #define I2C_CR2_RELOAD (1 << 24) /* NBYTES[7:0]: Number of bytes (23,16) */ #define I2C_CR2_NBYTES_SHIFT 16 #define I2C_CR2_NBYTES_MASK (0xFF << I2C_CR2_NBYTES_SHIFT) /* NACK: NACK generation (slave mode) */ #define I2C_CR2_NACK (1 << 15) /* STOP: Stop generation (master mode) */ #define I2C_CR2_STOP (1 << 14) /* START: Start generation */ #define I2C_CR2_START (1 << 13) /* HEAD10R: 10-bit address header only read direction (master receiver mode) */ #define I2C_CR2_HEAD10R (1 << 12) /* ADD10: 10-bit addressing mode (master mode) */ #define I2C_CR2_ADD10 (1 << 11) /* RD_WRN: Transfer direction (master mode) */ #define I2C_CR2_RD_WRN (1 << 10) #define I2C_CR2_SADD_7BIT_SHIFT 1 #define I2C_CR2_SADD_10BIT_SHIFT 0 #define I2C_CR2_SADD_7BIT_MASK (0x7F << I2C_CR2_SADD_7BIT_SHIFT) #define I2C_CR2_SADD_10BIT_MASK 0x3FF /* --- I2Cx_OAR1 values ---------------------------------------------------- */ /* OA1EN: Own Address 1 enable */ #define I2C_OAR1_OA1EN_DISABLE (0x0 << 15) #define I2C_OAR1_OA1EN_ENABLE (0x1 << 15) /* OA1MODE Own Address 1 10-bit mode */ #define I2C_OAR1_OA1MODE (1 << 10) #define I2C_OAR1_OA1MODE_7BIT 0 #define I2C_OAR1_OA1MODE_10BIT 1 /* OA1[9:8]: Interface address */ /* OA1[7:1]: Interface address */ /* OA1[0]: Interface address */ #define I2C_OAR1_OA1 (1 << 10) #define I2C_OAR1_OA1_7BIT 0 #define I2C_OAR1_OA1_10BIT 1 /* --- I2Cx_OAR2 values ---------------------------------------------------- */ /* OA2EN: Own Address 2 enable */ #define I2C_OAR2_OA2EN (1 << 15) /* OA2MSK[2:0]: Own Address 2 masks */ #define I2C_OAR2_OA2MSK_NO_MASK (0x0 << 8) #define I2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8) #define I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8) #define I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8) #define I2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8) #define I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8) #define I2C_OAR2_OA2MSK_OA2_7 (0x6 << 8) #define I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8) /* OA2[7:1]: Interface address */ /* --- I2Cx_TIMINGR values ------------------------------------------------- */ /* PRESC[3:0]: Timing prescaler (31,28) */ #define I2C_TIMINGR_PRESC_SHIFT 28 #define I2C_TIMINGR_PRESC_MASK (0xF << 28) /* SCLDEL[3:0]: Data setup time (23,20) */ #define I2C_TIMINGR_SCLDEL_SHIFT 20 #define I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT) /* SDADEL[3:0]: Data hold time (19,16) */ #define I2C_TIMINGR_SDADEL_SHIFT 16 #define I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT) /* SCLH[7:0]: SCL high period (master mode) (15,8) */ #define I2C_TIMINGR_SCLH_SHIFT 8 #define I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT) /* SCLL[7:0]: SCL low period (master mode) (7,0) */ #define I2C_TIMINGR_SCLL_SHIFT 0 #define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT) /* --- I2Cx_TIEMOUTR values ------------------------------------------------ */ /* TEXTEN: Extended clock timeout enable */ #define I2C_TIEMOUTR_TEXTEN (1 << 31) /* XXX: Not clear yet. */ /* TIMEOUTB[11:0]: Bus timeout B */ /* TIMOUTEN: Clock timeout enable */ #define I2C_TIEMOUTR_TIMOUTEN (1 << 15) /* TIDLE: Idle clock timeout detection */ #define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12) #define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12) /* XXX: Not clear yet. */ /* TIMEOUTA[11:0]: Bus Timeout A */ /* --- I2Cx_ISR values ----------------------------------------------------- */ /* Bits 31:24 Reserved, must be kept at reset value */ /* XXX: Not clear yet. */ /* ADDCODE[6:0]: Address match code (Slave mode) */ /* DIR: Transfer direction (Slave mode) */ #define I2C_ISR_DIR_READ (0x1 << 16) #define I2C_ISR_DIR_WRITE (0x0 << 16) /* BUSY: Bus busy */ #define I2C_ISR_BUSY (1 << 15) /* ALERT: SMBus alert */ #define I2C_ISR_ALERT (1 << 13) /* TIMEOUT: Timeout or tLOW detection flag */ #define I2C_ISR_TIMEOUT (1 << 12) /* PECERR: PEC Error in reception */ #define I2C_ISR_PECERR (1 << 11) /* OVR: Overrun/Underrun (slave mode) */ #define I2C_ISR_OVR (1 << 10) /* ARLO: Arbitration lost */ #define I2C_ISR_ARLO (1 << 9) /* BERR: Bus error */ #define I2C_ISR_BERR (1 << 8) /* TCR: Transfer Complete Reload */ #define I2C_ISR_TCR (1 << 7) /* TC: Transfer Complete (master mode) */ #define I2C_ISR_TC (1 << 6) /* STOPF: Stop detection flag */ #define I2C_ISR_STOPF (1 << 5) /* NACKF: Not Acknowledge received flag */ #define I2C_ISR_NACKF (1 << 4) /* ADDR: Address matched (slave mode) */ #define I2C_ISR_ADDR (1 << 3) /* RXNE: Receive data register not empty (receivers) */ #define I2C_ISR_RXNE (1 << 2) /* TXIS: Transmit interrupt status (transmitters) */ #define I2C_ISR_TXIS (1 << 1) /* TXE: Transmit data register empty (transmitters) */ #define I2C_ISR_TXE (1 << 0) /* --- I2Cx_ICR values ----------------------------------------------------- */ /* ALERTCF: Alert flag clear */ #define I2C_ICR_ALERTCF (1 << 13) /* TIMOUTCF: Timeout detection flag clear */ #define I2C_ICR_TIMOUTCF (1 << 12) /* PECCF: PEC Error flag clear */ #define I2C_ICR_PECCF (1 << 11) /* OVRCF: Overrun/Underrun flag clear */ #define I2C_ICR_OVRCF (1 << 10) /* ARLOCF: Arbitration Lost flag clear */ #define I2C_ICR_ARLOCF (1 << 9) /* BERRCF: Bus error flag clear */ #define I2C_ICR_BERRCF (1 << 8) /* STOPCF: Stop detection flag clear */ #define I2C_ICR_STOPCF (1 << 5) /* NACKCF: Not Acknowledge flag clear */ #define I2C_ICR_NACKCF (1 << 4) /* ADDRCF: Address Matched flag clear */ #define I2C_ICR_ADDRCF (1 << 3) /* --- I2Cx_PECR values ---------------------------------------------------- */ /* PEC[7:0] Packet error checking register */ /* --- I2C function prototypes---------------------------------------------- */ BEGIN_DECLS void i2c_reset(uint32_t i2c); void i2c_peripheral_enable(uint32_t i2c); void i2c_peripheral_disable(uint32_t i2c); void i2c_send_start(uint32_t i2c); void i2c_send_stop(uint32_t i2c); void i2c_clear_stop(uint32_t i2c); void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); void i2c_send_data(uint32_t i2c, uint8_t data); uint8_t i2c_get_data(uint32_t i2c); void i2c_enable_analog_filter(uint32_t i2c); void i2c_disable_analog_filter(uint32_t i2c); void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting); void i2c_set_prescaler(uint32_t i2c, uint8_t presc); void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time); void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time); void i2c_set_scl_high_period(uint32_t i2c, uint8_t period); void i2c_set_scl_low_period(uint32_t i2c, uint8_t period); void i2c_enable_stretching(uint32_t i2c); void i2c_disable_stretching(uint32_t i2c); void i2c_100khz_i2cclk8mhz(uint32_t i2c); void i2c_set_7bit_addr_mode(uint32_t i2c); void i2c_set_10bit_addr_mode(uint32_t i2c); void i2c_set_7bit_address(uint32_t i2c, uint8_t addr); void i2c_set_10bit_address(uint32_t i2c, uint16_t addr); void i2c_set_write_transfer_dir(uint32_t i2c); void i2c_set_read_transfer_dir(uint32_t i2c); void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes); uint8_t i2c_is_start(uint32_t i2c); void i2c_enable_autoend(uint32_t i2c); void i2c_disable_autoend(uint32_t i2c); uint8_t i2c_nack(uint32_t i2c); uint8_t i2c_busy(uint32_t i2c); uint8_t i2c_transmit_int_status(uint32_t i2c); uint8_t i2c_transfer_complete(uint32_t i2c); uint8_t i2c_received_data(uint32_t i2c); void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); void i2c_enable_rxdma(uint32_t i2c); void i2c_disable_rxdma(uint32_t i2c); void i2c_enable_txdma(uint32_t i2c); void i2c_disable_txdma(uint32_t i2c); void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data); void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data); END_DECLS /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/irq.yaml000066400000000000000000000022671435536612600241150ustar00rootroot00000000000000includeguard: LIBOPENCM3_STM32_F3_NVIC_H partname_humanreadable: STM32 F3 series partname_doxygen: STM32F3 irqs: - nvic_wwdg - pvd - tamp_stamp - rtc_wkup - flash - rcc - exti0 - exti1 - exti2_tsc - exti3 - exti4 - dma1_ch1 - dma1_ch2 - dma1_ch3 - dma1_ch4 - dma1_ch5 - dma1_ch6 - dma1_ch7 - adc1_2 - usb_hp_can1_tx - usb_lp_can1_rx0 - can1_rx1 - can1_sce - exti9_5 - tim1_brk_tim15 - tim1_up_tim16 - tim1_trg_com_tim17 - tim1_cc - tim2 - tim3 - tim4 - i2c1_ev_exti23 - i2c1_er - i2c2_ev_exti24 - i2c2_er - spi1 - spi2 - usart1_exti25 - usart2_exti26 - usart3_exti28 - exti15_10 - rtc_alarm - usb_wkup_a - tim8_brk - tim8_up - tim8_trg_com - tim8_cc - adc3 - reserved_1 - reserved_2 - reserved_3 - spi3 - uart4_exti34 - uart5_exti35 - tim6_dac - tim7 - dma2_ch1 - dma2_ch2 - dma2_ch3 - dma2_ch4 - dma2_ch5 - eth - reserved_4 - reserved_5 - comp123 - comp456 - comp7 - reserved_6 - reserved_7 - reserved_8 - reserved_9 - reserved_10 - reserved_11 - reserved_12 - usb_hp - usb_lp - usb_wkup - reserved_13 - reserved_14 - reserved_15 - reserved_16 hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/iwdg.h000066400000000000000000000032551435536612600235370ustar00rootroot00000000000000/** @defgroup iwdg_defines IWDG Defines * * @brief Defined Constants and Types for the STM32F3xx Independent Watchdog * Timer * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 18 August 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_IWDG_H #define LIBOPENCM3_IWDG_H #include #include /* --- IWDG registers ------------------------------------------------------ */ /* Window register (IWDG_WINR) */ #define IWDG_WINR MMIO32(IWDG_BASE + 0x10) /* --- IWDG_SR values ------------------------------------------------------ */ /* WVU: Watchdog counter window value update */ #define IWGD_SR_WVU (1 << 2) /* --- IWDG_WIN values ----------------------------------------------------- */ /* Bits 11:0 WIN[11:0]: Watchdog counter window value */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/memorymap.h000066400000000000000000000113371435536612600246130ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * Modified by 2013 Fernando Cortes (stm32f3) * Modified by 2013 Guillermo Rivera (stm32f3) * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_MEMORYMAP_H #define LIBOPENCM3_MEMORYMAP_H #include /* --- STM32F3 specific peripheral definitions ----------------------------- */ /* Memory map for all busses */ #define PERIPH_BASE 0x40000000 #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) #define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) #define PERIPH_BASE_AHB2 0x48000000 #define PERIPH_BASE_AHB3 0x50000000 /* Register boundary addresses */ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) /* PERIPH_BASE_APB1 + 0x0C00 (0x4000 0C00 - 0x4000 0FFF): Reserved */ #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) /* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */ #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) #define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) #define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) #define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5C00) #define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) #define BX_CAN_BASE (PERIPH_BASE_APB1 + 0x6400) /* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved */ /* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) /* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 7FFF): Reserved */ /* APB2 */ #define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) #define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) #define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) /* PERIPH_BASE_APB2 + 0x3C00 (0x4001 3C00 - 0x4001 3FFF): Reserved */ #define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) #define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) #define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00) /* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 2BFF): Reserved */ #define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) #define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) #define COMP_BASE (PERIPH_BASE_APB2 + 0x0000) #define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0000) /* AHB2 */ #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) #define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) #define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00) #define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) #define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) /* AHB1 */ #define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) /* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ #define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) /* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) /* PERIPH_BASE_AHB1 + 0x1400 (0x4002 1400 - 0x4002 1FFF): Reserved */ #define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) /* PERIPH_BASE_AHB1 + 0x0800 (0x4002 0800 - 0x4002 0FFF): Reserved */ #define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) #define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) /* AHB3 */ #define ADC3_BASE (PERIPH_BASE_AHB3 + 0x0400) #define ADC4_BASE (PERIPH_BASE_AHB3 + 0x0400) #define ADC1_BASE (PERIPH_BASE_AHB3 + 0x0000) #define ADC2_BASE (PERIPH_BASE_AHB3 + 0x0000) /* PPIB */ #define DBGMCU_BASE (PPBI_BASE + 0x00042000) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/pwr.h000066400000000000000000000036331435536612600234150ustar00rootroot00000000000000/** @defgroup pwr_defines PWR Defines * * @brief Defined Constants and Types for the STM32F3xx Power control * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Stephen Caudle * Modified by 2013 Fernando Cortes (stm32f3) * Modified by 2013 Guillermo Rivera (stm32f3) * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_PWR_F3_H #define LIBOPENCM3_PWR_F3_H #include /* --- PWR_CR values ------------------------------------------------------- */ /* Bits [31:10]: Reserved */ #define PWR_CR_DBP (1 << 8) /* Bits [7:5]: Reserved PLS: PVD level selection. (Power Voltage Detector) */ #define PWR_CR_PVDE (1 << 4) #define PWR_CR_CSBF (1 << 3) #define PWR_CR_CWUF (1 << 2) #define PWR_CR_PDDS (1 << 1) #define PWR_CR_LPDS (1 << 0) /* --- PWR_CSR values ------------------------------------------------------ */ /* Bits [31:10]: Reserved */ #define PWR_CSR_EWUP2 (1 << 9) #define PWR_CSR_EWUP1 (1 << 8) /* Bits [7:3]: Reserved */ #define PWR_CSR_PVDO (1 << 2) #define PWR_CSR_SBF (1 << 1) #define PWR_CSR_WUF (1 << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/rcc.h000066400000000000000000000372071435536612600233600ustar00rootroot00000000000000/** @defgroup rcc_defines RCC Defines * * @brief Defined Constants and Types for the STM32F3xx Reset and Clock * control * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2011 Fergus Noble * Copyright (C) 2011 Stephen Caudle * Modified by 2013 Fernando Cortes (stm32f3) * Modified by 2013 Guillermo Rivera (stm32f3) * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RCC_H #define LIBOPENCM3_RCC_H #include #include /* --- RCC registers ------------------------------------------------------- */ #define RCC_CR MMIO32(RCC_BASE + 0x00) #define RCC_CFGR MMIO32(RCC_BASE + 0x04) #define RCC_CIR MMIO32(RCC_BASE + 0x08) #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0C) #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) #define RCC_AHBENR MMIO32(RCC_BASE + 0x14) #define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) #define RCC_APB1ENR MMIO32(RCC_BASE + 0x1C) #define RCC_BDCR MMIO32(RCC_BASE + 0x20) #define RCC_CSR MMIO32(RCC_BASE + 0x24) #define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) #define RCC_CFGR2 MMIO32(RCC_BASE + 0x2C) #define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) /* --- RCC_CR values ------------------------------------------------------- */ #define RCC_CR_PLLRDY (1 << 25) #define RCC_CR_PLLON (1 << 24) #define RCC_CR_CSSON (1 << 19) #define RCC_CR_HSEBYP (1 << 18) #define RCC_CR_HSERDY (1 << 17) #define RCC_CR_HSEON (1 << 16) /* HSICAL: [15:8] */ /* HSITRIM: [7:3] */ #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) /* --- RCC_CFGR values ----------------------------------------------------- */ #define RCC_CFGR_MCOF (1 << 28) #define RCC_CFGR_I2SSRC (1 << 23) #define RCC_CFGR_USBPRES (1 << 22) #define RCC_CFGR_PLLXTPRE (1 << 17) #define RCC_CFGR_PLLSRC (1 << 16) /* MCO: Microcontroller clock output */ #define RCC_CFGR_MCO_SHIFT 24 #define RCC_CFGR_MCO_DISABLED 0x0 /*Reserve RCC_CFGR_MCO 0x1*/ #define RCC_CFGR_MCO_LSI 0x2 #define RCC_CFGR_MCO_LSE 0x3 #define RCC_CFGR_MCO_SYSCLK 0x4 #define RCC_CFGR_MCO_HSI 0x5 #define RCC_CFGR_MCO_HSE 0x6 #define RCC_CFGR_MCO_PLL 0x7 /* PLLSRC: PLL source values */ #define RCC_CFGR_PLLSRC_HSI_DIV2 0 #define RCC_CFGR_PLLSRC_HSE_PREDIV 1 /* PLLMUL: PLL multiplication factor */ #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X5 0x3 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X6 0x4 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X7 0x5 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X8 0x6 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X9 0x7 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X10 0x8 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X11 0x9 #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X12 0xA #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X13 0xB #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD #define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE #define RCC_CFGR_PLLMUL_MASK (0xF << RCC_CFGR_PLLMUL_SHIFT) /* PPRE2: APB high-speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_SHIFT 11 /* 0XX: HCLK not divided */ #define RCC_CFGR_PPRE2_DIV_NONE 0x0 #define RCC_CFGR_PPRE2_DIV_2 0x4 #define RCC_CFGR_PPRE2_DIV_4 0x5 #define RCC_CFGR_PPRE2_DIV_8 0x6 #define RCC_CFGR_PPRE2_DIV_16 0x7 /* PPRE1:APB Low-speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_SHIFT 8 /* 0XX: HCLK not divided */ #define RCC_CFGR_PPRE1_DIV_NONE 0x0 #define RCC_CFGR_PPRE1_DIV_2 0x4 #define RCC_CFGR_PPRE1_DIV_4 0x5 #define RCC_CFGR_PPRE1_DIV_8 0x6 #define RCC_CFGR_PPRE1_DIV_16 0x7 /* HPRE: HLCK prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 /* 0XXX: SYSCLK not divided */ #define RCC_CFGR_HPRE_DIV_NONE 0x0 #define RCC_CFGR_HPRE_DIV_2 0x8 #define RCC_CFGR_HPRE_DIV_4 0x9 #define RCC_CFGR_HPRE_DIV_8 0xA #define RCC_CFGR_HPRE_DIV_16 0xB #define RCC_CFGR_HPRE_DIV_64 0xC #define RCC_CFGR_HPRE_DIV_128 0xD #define RCC_CFGR_HPRE_DIV_256 0xE #define RCC_CFGR_HPRE_DIV_512 0xF /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 #define RCC_CFGR_SWS_HSI 0x0 #define RCC_CFGR_SWS_HSE 0x1 #define RCC_CFGR_SWS_PLL 0x2 /* SW: System clock switch */ #define RCC_CFGR_SW_SHIFT 0 #define RCC_CFGR_SW_HSI 0x0 #define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_PLL 0x2 /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ #define RCC_CIR_CSSC (1 << 23) /* OSC ready interrupt clear bits */ #define RCC_CIR_PLLRDYC (1 << 20) #define RCC_CIR_HSERDYC (1 << 19) #define RCC_CIR_HSIRDYC (1 << 18) #define RCC_CIR_LSERDYC (1 << 17) #define RCC_CIR_LSIRDYC (1 << 16) /* OSC ready interrupt enable bits */ #define RCC_CIR_PLLRDYIE (1 << 12) #define RCC_CIR_HSERDYIE (1 << 11) #define RCC_CIR_HSIRDYIE (1 << 10) #define RCC_CIR_LSERDYIE (1 << 9) #define RCC_CIR_LSIRDYIE (1 << 8) /* Clock security system interrupt flag bit */ #define RCC_CIR_CSSF (1 << 7) /* OSC ready interrupt flag bits */ #define RCC_CIR_PLLRDYF (1 << 4) #define RCC_CIR_HSERDYF (1 << 3) #define RCC_CIR_HSIRDYF (1 << 2) #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) /* --- RCC_APB2RSTR values ------------------------------------------------- */ #define RCC_APB2RSTR_TIM17RST (1 << 18) #define RCC_APB2RSTR_TIM16RST (1 << 17) #define RCC_APB2RSTR_TIM15RST (1 << 16) #define RCC_APB2RSTR_USART1RST (1 << 14) #define RCC_APB2RSTR_TIM8RST (1 << 13) #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_TIM1RST (1 << 11) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* --- RCC_APB1RSTR values ------------------------------------------------- */ #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) #define RCC_APB1RSTR_CANRST (1 << 25) #define RCC_APB1RSTR_USBRST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) #define RCC_APB1RSTR_UART5RST (1 << 20) #define RCC_APB1RSTR_UART4RST (1 << 19) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) #define RCC_APB1RSTR_SPI3RST (1 << 15) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) /* --- RCC_AHBENR values --------------------------------------------------- */ #define RCC_AHBENR_ADC34EN (1 << 29) #define RCC_AHBENR_ADC12EN (1 << 28) #define RCC_AHBENR_TSCEN (1 << 24) #define RCC_AHBENR_IOPFEN (1 << 22) #define RCC_AHBENR_IOPEEN (1 << 21) #define RCC_AHBENR_IOPDEN (1 << 20) #define RCC_AHBENR_IOPCEN (1 << 19) #define RCC_AHBENR_IOPBEN (1 << 18) #define RCC_AHBENR_IOPAEN (1 << 17) #define RCC_AHBENR_CRCEN (1 << 1) /* --- RCC_APB2ENR values -------------------------------------------------- */ #define RCC_APB2ENR_TIM17EN (1 << 18) #define RCC_APB2ENR_TIM16EN (1 << 17) #define RCC_APB2ENR_TIM15EN (1 << 16) #define RCC_APB2ENR_USART1EN (1 << 14) #define RCC_APB2ENR_TIM8EN (1 << 13) #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_TIM1EN (1 << 11) #define RCC_APB2ENR_SYSCFGEN (1 << 0) /* --- RCC_APB1ENR values -------------------------------------------------- */ #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_CANEN (1 << 25) #define RCC_APB1ENR_USBEN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) #define RCC_APB1ENR_USART2EN (1 << 17) #define RCC_APB1ENR_SPI3EN (1 << 15) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /* --- RCC_BDCR values ----------------------------------------------------- */ #define RCC_BDCR_BDRST (1 << 16) #define RCC_BDCR_RTCEN (1 << 15) /* RCC_BDCR[9:8]: RTCSEL */ /* RCC_BDCR[4:3]: LSEDRV */ #define RCC_BDCR_LSEBYP (1 << 2) #define RCC_BDCR_LSERDY (1 << 1) #define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ #define RCC_CSR_LPWRRSTF (1 << 31) #define RCC_CSR_WWDGRSTF (1 << 30) #define RCC_CSR_IWDGRSTF (1 << 29) #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) #define RCC_CSR_OBLRSTF (1 << 25) #define RCC_CSR_RMVF (1 << 24) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) /* --- RCC_AHBRSTR values -------------------------------------------------- */ #define RCC_AHBRSTR_ADC34RST (1 << 29) #define RCC_AHBRSTR_ADC12RST (1 << 28) #define RCC_AHBRSTR_TSCRST (1 << 24) #define RCC_AHBRSTR_IOPFRST (1 << 22) #define RCC_AHBRSTR_IOPERST (1 << 21) #define RCC_AHBRSTR_IOPDRST (1 << 20) #define RCC_AHBRSTR_IOPCRST (1 << 19) #define RCC_AHBRSTR_IOPBRST (1 << 18) #define RCC_AHBRSTR_IOPARST (1 << 17) /* --- RCC_CFGR2 values ---------------------------------------------------- */ /* ADC34PRES: ADC34 prescaler */ #define RCC_CFGR2_ADC34PRES_SHIFT 9 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1 0x10 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_2 0x11 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_4 0x12 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_6 0x13 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_8 0x14 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_10 0x15 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_12 0x16 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_16 0x17 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_32 0x18 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64 0x19 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128 0x1A #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256 0x1B /* OTHERS */ /* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x */ /* ADC12PRES ADC prescaler */ /* REVISAR DIRECCIONES */ #define RCC_CFGR2_ADC12PRES_SHIFT 4 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1 0x10 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2 0x11 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_4 0x12 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_6 0x13 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_8 0x14 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_10 0x15 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_12 0x16 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_16 0x17 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_32 0x18 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64 0x19 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128 0x1A #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256 0x1B /* OTHERS */ /* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x */ /* PREDIV[3:0] PREDIV division factor */ /* REVISAR DIRECCIONES */ #define RCC_CFGR2_PREDIV_SHIFT 0 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE 0x0 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2 0x1 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_3 0x2 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_4 0x3 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_5 0x4 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_6 0x5 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_7 0x6 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_8 0x7 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_9 0x8 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_10 0x9 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_11 0xA #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_12 0xB #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_13 0xC #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_14 0xD #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15 0xE #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16 0xF /* --- RCC_CFGR3 values ---------------------------------------------------- */ #define RCC_CFGR3_TIM8SW (1 << 9) #define RCC_CFGR3_TIM1SW (1 << 8) #define RCC_CFGR3_I2C2SW (1 << 5) #define RCC_CFGR3_I2C1SW (1 << 4) /* UART5SW: UART5 clock source selection */ #define RCC_CFGR3_UART5SW_SHIFT 22 #define RCC_CFGR3_UART5SW_PCLK 0x0 #define RCC_CFGR3_UART5SW_SYSCLK 0x1 #define RCC_CFGR3_UART5SW_LSE 0x2 #define RCC_CFGR3_UART5SW_HSI 0x3 /* UART4SW: UART4 clock source selection */ #define RCC_CFGR3_UART4SW_SHIFT 20 #define RCC_CFGR3_UART4SW_PCLK 0x0 #define RCC_CFGR3_UART4SW_SYSCLK 0x1 #define RCC_CFGR3_UART4SW_LSE 0x2 #define RCC_CFGR3_UART4SW_HSI 0x3 /* UART3SW: UART3 clock source selection */ #define RCC_CFGR3_UART3SW_SHIFT 18 #define RCC_CFGR3_UART3SW_PCLK 0x0 #define RCC_CFGR3_UART3SW_SYSCLK 0x1 #define RCC_CFGR3_UART3SW_LSE 0x2 #define RCC_CFGR3_UART3SW_HSI 0x3 /* UART2SW: UART2 clock source selection */ #define RCC_CFGR3_UART2SW_SHIFT 16 #define RCC_CFGR3_UART2SW_PCLK 0x0 #define RCC_CFGR3_UART2SW_SYSCLK 0x1 #define RCC_CFGR3_UART2SW_LSE 0x2 #define RCC_CFGR3_UART2SW_HSI 0x3 /* UART1SW: UART1 clock source selection */ #define RCC_CFGR3_UART1SW_SHIFT 0 #define RCC_CFGR3_UART1SW_PCLK 0x0 #define RCC_CFGR3_UART1SW_SYSCLK 0x1 #define RCC_CFGR3_UART1SW_LSE 0x2 #define RCC_CFGR3_UART1SW_HSI 0x3 /* --- Variable definitions ------------------------------------------------ */ extern uint32_t rcc_ppre1_frequency; extern uint32_t rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ enum rcc_clock { CLOCK_44MHZ, CLOCK_48MHZ, CLOCK_64MHZ, CLOCK_END }; typedef struct { uint8_t pll; uint8_t pllsrc; uint32_t flash_config; uint8_t hpre; uint8_t ppre1; uint8_t ppre2; uint8_t power_save; uint32_t apb1_frequency; uint32_t apb2_frequency; } clock_scale_t; extern const clock_scale_t hsi_8mhz[CLOCK_END]; enum osc { PLL, HSE, HSI, LSE, LSI }; BEGIN_DECLS void rcc_osc_ready_int_clear(enum osc osc); void rcc_osc_ready_int_enable(enum osc osc); void rcc_osc_ready_int_disable(enum osc osc); int rcc_osc_ready_int_flag(enum osc osc); void rcc_css_int_clear(void); int rcc_css_int_flag(void); void rcc_wait_for_osc_ready(enum osc osc); void rcc_wait_for_osc_not_ready(enum osc osc); void rcc_wait_for_sysclk_status(enum osc osc); void rcc_osc_on(enum osc osc); void rcc_osc_off(enum osc osc); void rcc_css_enable(void); void rcc_css_disable(void); void rcc_osc_bypass_enable(enum osc osc); void rcc_osc_bypass_disable(enum osc osc); void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); void rcc_set_sysclk_source(uint32_t clk); void rcc_set_pll_source(uint32_t pllsrc); void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); void rcc_set_main_pll_hsi(uint32_t pll); uint32_t rcc_get_system_clock_source(void); void rcc_backupdomain_reset(void); void rcc_clock_setup_hsi(const clock_scale_t *clock); void rcc_set_i2c_clock_hsi(uint32_t i2c); void rcc_set_i2c_clock_sysclk(uint32_t i2c); uint32_t rcc_get_i2c_clocks(void); void rcc_usb_prescale_1_5(void); void rcc_usb_prescale_1(void); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/spi.h000066400000000000000000000065761435536612600234110ustar00rootroot00000000000000/** @defgroup spi_defines SPI Defines * * @brief Defined Constants and Types for the STM32F3xx SPI * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 5 December 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SPI_H #define LIBOPENCM3_SPI_H #include #include /* DFF: Data frame format */ /****************************************************************************/ /** @defgroup spi_dff SPI data frame format * @ingroup spi_defines * * @{*/ #define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) #define SPI1_DR8 SPI_DR8(SPI1_BASE) #define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) #define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) #define SPI_CR1_CRCL_8BIT (0 << 11) #define SPI_CR1_CRCL_16BIT (1 << 11) /**@}*/ #define SPI_CR1_CRCL (1 << 11) /* --- SPI_CR2 values ------------------------------------------------------ */ /* LDMA_TX: Last DMA transfer for transmission */ #define SPI_CR2_LDMA_TX (1 << 14) /* LDMA_RX: Last DMA transfer for reception */ #define SPI_CR2_LDMA_RX (1 << 13) /* FRXTH: FIFO reception threshold */ #define SPI_CR2_FRXTH (1 << 12) /* DS [3:0]: Data size */ /* 0x0 - 0x2 NOT USED */ #define SPI_CR2_DS_4BIT (0x3 << 8) #define SPI_CR2_DS_5BIT (0x4 << 8) #define SPI_CR2_DS_6BIT (0x5 << 8) #define SPI_CR2_DS_7BIT (0x6 << 8) #define SPI_CR2_DS_8BIT (0x7 << 8) #define SPI_CR2_DS_9BIT (0x8 << 8) #define SPI_CR2_DS_10BIT (0x9 << 8) #define SPI_CR2_DS_11BIT (0xA << 8) #define SPI_CR2_DS_12BIT (0xB << 8) #define SPI_CR2_DS_13BIT (0xC << 8) #define SPI_CR2_DS_14BIT (0xD << 8) #define SPI_CR2_DS_15BIT (0xE << 8) #define SPI_CR2_DS_16BIT (0xF << 8) #define SPI_CR2_DS_MASK (0xF << 8) /* NSSP: NSS pulse management */ #define SPI_CR2_NSSP (1 << 3) /* --- SPI_SR values ------------------------------------------------------- */ /* FTLVL[1:0]: FIFO Transmission Level */ #define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) #define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) #define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) #define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) /* FRLVL[1:0]: FIFO Reception Level */ #define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) #define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) #define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) #define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void spi_set_data_size(uint32_t spi, uint16_t data_s); void spi_fifo_reception_threshold_8bit(uint32_t spi); void spi_fifo_reception_threshold_16bit(uint32_t spi); void spi_i2s_mode_spi_mode(uint32_t spi); void spi_send8(uint32_t spi, uint8_t data); uint8_t spi_read8(uint32_t spi); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/syscfg.h000066400000000000000000000016661435536612600241070ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SYSCFG_H #define LIBOPENCM3_SYSCFG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/timer.h000066400000000000000000000023201435536612600237150ustar00rootroot00000000000000/** @defgroup timer_defines Timer Defines * * @brief Defined Constants and Types for the STM32F3xx Timers * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 8 March 2013 * * @author @htmlonly © @endhtmlonly 2011 Fergus Noble * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_TIMER_H #define LIBOPENCM3_TIMER_H #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f3/usart.h000066400000000000000000000344051435536612600237440ustar00rootroot00000000000000/** @defgroup usart_defines USART Defines * * @brief Defined Constants and Types for the STM32F3xx USART * * @ingroup STM32F3xx_defines * * @version 1.0.0 * * @date 5 December 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H #include #include /* --- USART registers ----------------------------------------------------- */ /* Control register 1 (USARTx_CR1) */ #define USART_CR1(usart_base) MMIO32(usart_base + 0x00) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) #define UART4_CR1 USART_CR1(UART4_BASE) #define UART5_CR1 USART_CR1(UART5_BASE) /* Control register 2 (USARTx_CR2) */ #define USART_CR2(usart_base) MMIO32(usart_base + 0x04) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) #define UART4_CR2 USART_CR2(UART4_BASE) #define UART5_CR2 USART_CR2(UART5_BASE) /* Control register 3 (USARTx_CR3) */ #define USART_CR3(usart_base) MMIO32(usart_base + 0x08) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) #define UART4_CR3 USART_CR3(UART4_BASE) #define UART5_CR3 USART_CR3(UART5_BASE) /* Baud rate register (USARTx_BRR) */ #define USART_BRR(usart_base) MMIO32(usart_base + 0x0C) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) #define UART4_BRR USART_BRR(UART4_BASE) #define UART5_BRR USART_BRR(UART5_BASE) /* Guard time and prescaler register (USARTx_GTPR) */ #define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) #define UART4_GTPR USART_GTPR(UART4_BASE) #define UART5_GTPR USART_GTPR(UART5_BASE) /* Receiver timeout register (USART_RTOR) */ #define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) #define USART1_RTOR USART_RTOR(USART1_BASE) #define USART2_RTOR USART_RTOR(USART2_BASE) #define USART3_RTOR USART_RTOR(USART3_BASE) #define UART4_RTOR USART_RTOR(UART4_BASE) #define UART5_RTOR USART_RTOR(UART5_BASE) /* Request register (USART_RQR) */ #define USART_RQR(usart_base) MMIO32(usart_base + 0x18) #define USART1_RQR USART_RQR(USART1_BASE) #define USART2_RQR USART_RQR(USART2_BASE) #define USART3_RQR USART_RQR(USART3_BASE) #define UART4_RQR USART_RQR(UART4_BASE) #define UART5_RQR USART_RQR(UART5_BASE) /* Interrupt & status register (USART_ISR) */ #define USART_ISR(usart_base) MMIO32(usart_base + 0x1C) #define USART1_ISR USART_ISR(USART1_BASE) #define USART2_ISR USART_ISR(USART2_BASE) #define USART3_ISR USART_ISR(USART3_BASE) #define UART4_ISR USART_ISR(UART4_BASE) #define UART5_ISR USART_ISR(UART5_BASE) /* Interrupt flag clear register (USART_ICR) */ #define USART_ICR(usart_base) MMIO32(usart_base + 0x20) #define USART1_ICR USART_ICR(USART1_BASE) #define USART2_ICR USART_ICR(USART2_BASE) #define USART3_ICR USART_ICR(USART3_BASE) #define UART4_ICR USART_ICR(UART4_BASE) #define UART5_ICR USART_ICR(UART5_BASE) /* Receive data register (USART_RDR) */ #define USART_RDR(usart_base) MMIO32(usart_base + 0x24) #define USART1_RDR USART_RDR(USART1_BASE) #define USART2_RDR USART_RDR(USART2_BASE) #define USART3_RDR USART_RDR(USART3_BASE) #define UART4_RDR USART_RDR(UART4_BASE) #define UART5_RDR USART_RDR(UART5_BASE) /* Transmit data register (USART_TDR) */ #define USART_TDR(usart_base) MMIO32(usart_base + 0x28) #define USART1_TDR USART_TDR(USART1_BASE) #define USART2_TDR USART_TDR(USART2_BASE) #define USART3_TDR USART_TDR(USART3_BASE) #define UART4_TDR USART_TDR(UART4_BASE) #define UART5_TDR USART_TDR(UART5_BASE) /* --- USART_CR1 values ---------------------------------------------------- */ /* EOBIE: End of Block interrupt enable */ #define USART_CR1_EOBIE (1 << 27) /* RTOIE: Receiver timeout interrupt enable */ #define USART_CR1_RTOIE (1 << 26) /* DEAT[4:0]: Driver Enable assertion time */ /* DEDT[4:0]: Driver Enable deassertion time */ /* OVER8: Oversampling mode */ #define USART_CR1_OVER8 (1 << 15) /* CMIE: Character match interrupt enable */ #define USART_CR1_CMIE (1 << 14) /* MME: Mute mode enable */ #define USART_CR1_MME (1 << 13) /* M: Word length */ #define USART_CR1_M (1 << 12) /* WAKE: Receiver wakeup method */ #define USART_CR1_WAKE (1 << 11) /* PCE: Parity control enable */ #define USART_CR1_PCE (1 << 10) /* PS: Parity selection */ #define USART_CR1_PS (1 << 9) /* PEIE: PE interrupt enable */ #define USART_CR1_PEIE (1 << 8) /* TXEIE: Interrupt enable */ #define USART_CR1_TXEIE (1 << 7) /* TCIE: Transmission complete interrupt enable */ #define USART_CR1_TCIE (1 << 6) /* RXNEIE: RXNE interrupt enable */ #define USART_CR1_RXNEIE (1 << 5) /* IDLEIE: IDLE interrupt enable */ #define USART_CR1_IDLEIE (1 << 4) /* TE: Transmitter enable */ #define USART_CR1_TE (1 << 3) /* RE: Receiver enable */ #define USART_CR1_RE (1 << 2) /* UESM: USART enable in Stop mode */ #define USART_CR1_UESM (1 << 1) /* UE: USART enable */ #define USART_CR1_UE (1 << 0) /* --- USART_CR2 values ---------------------------------------------------- */ /* ADD[7:4]: Address of the USART node (31,28) */ #define USART_CR2_ADD1_MASK (0xF << 28) /* ADD[3:0]: Address of the USART node (27,24) */ #define USART_CR2_ADD2_MASK (0xF << 24) /* RTOEN: Receiver timeout enable */ #define USART_CR2_RTOEN (1 << 23) /* ABRMOD[1:0]: Auto baud rate mode */ #define USART_CR2_ABRMOD_BAUD (0x0 << 21) #define USART_CR2_ABRMOD_FALL_EDGE (0x1 << 21) #define USART_CR2_ABRMOD_FRAME_0x7F (0x2 << 21) #define USART_CR2_ABRMOD_FRAME_0x55 (0x3 << 21) /* ABREN: Auto baud rate enable */ #define USART_CR2_ABREN (1 << 20) /* MSBFIRST: Most significant bit first */ #define USART_CR2_MSBFIRST (1 << 19) /* DATAINV: Binary data inversion */ #define USART_CR2_DATAINV (1 << 18) /* TXINV: TX pin active level inversion */ #define USART_CR2_TXINV (1 << 17) /* RXINV: RX pin active level inversion */ #define USART_CR2_RXINV (1 << 16) /* SWAP: Swap TX/RX pins */ #define USART_CR2_SWAP (1 << 15) /* LINEN: LIN mode enable */ #define USART_CR2_LINEN (1 << 14) /* STOP[13:12]: STOP bits */ #define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ #define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ #define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ #define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ #define USART_CR2_STOPBITS_MASK (0x03 << 12) #define USART_CR2_STOPBITS_SHIFT 12 /* CLKEN: Clock enable */ #define USART_CR2_CLKEN (1 << 11) /* CPOL: Clock polarity */ #define USART_CR2_CPOL (1 << 10) /* CPHA: Clock phase */ #define USART_CR2_CPHA (1 << 9) /* LBCL: Last bit clock pulse */ #define USART_CR2_LBCL (1 << 8) /* LBDIE: LIN break detection interrupt enable */ #define USART_CR2_LBDIE (1 << 6) /* LBDL: LIN break detection length */ #define USART_CR2_LBDL (1 << 5) /* ADDM7:7-bit Address Detection/4-bit Address Detection */ #define USART_CR2_ADDM7 (1 << 4) /* ADD[3:0]: Addres of the usart node #define USART_CR2_ADD_MASK 0xF */ /* --- USART_CR3 values ---------------------------------------------------- */ /* WUFIE: Wakeup from Stop mode interrupt enable */ #define USART_CR3_WUFIE (1 << 22) /* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */ #define USART_CR3_WUS_ON (0x0 << 20) /* RESERVE #define USART_CR3_WUS (0x1 << 20) */ #define USART_CR3_WUS_START_BIT (0x2 << 20) #define USART_CR3_WUS_RXNE (0x3 << 20) /* SCARCNT[2:0]: Smartcard auto-retry count */ #define USART_CR3_SCARCNT_OFF (0x0 << 17) /* 0x1 to 0x7: number of automatic retransmission attempts */ /* DEP: Driver enable polarity selection */ #define USART_CR3_DEP (1 << 15) /* DEM: Driver enable mode */ #define USART_CR3_DEM (1 << 14) /* DDRE: DMA Disable on Reception Error */ #define USART_CR3_DDRE (1 << 13) /* OVRDIS: Overrun Disable */ #define USART_CR3_OVRDIS (1 << 12) /* ONEBIT: One sample bit method enable */ #define USART_CR3_ONEBIT (1 << 11) /* CTSIE: CTS interrupt enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_CTSIE (1 << 10) /* CTSE: CTS enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_CTSE (1 << 9) /* RTSE: RTS enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_RTSE (1 << 8) /* DMAT: DMA enable transmitter */ /* Note: N/A on UART5 */ #define USART_CR3_DMAT (1 << 7) /* DMAR: DMA enable receiver */ /* Note: N/A on UART5 */ #define USART_CR3_DMAR (1 << 6) /* SCEN: Smartcard mode enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_SCEN (1 << 5) /* NACK: Smartcard NACK enable */ /* Note: N/A on UART4 & UART5 */ #define USART_CR3_NACK (1 << 4) /* HDSEL: Half-duplex selection */ #define USART_CR3_HDSEL (1 << 3) /* IRLP: IrDA low-power */ #define USART_CR3_IRLP (1 << 2) /* IREN: IrDA mode enable */ #define USART_CR3_IREN (1 << 1) /* EIE: Error interrupt enable */ #define USART_CR3_EIE (1 << 0) /* --- USART_BRR values ---------------------------------------------------- */ /* DIV_Mantissa[11:0]: mantissa of USARTDIV */ #define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) /* DIV_Fraction[3:0]: fraction of USARTDIV */ #define USART_BRR_DIV_FRACTION_MASK 0xF /* --- USART_GTPR values --------------------------------------------------- */ /* GT[7:0]: Guard time value */ /* Note: N/A on UART4 & UART5 */ #define USART_GTPR_GT_MASK (0xFF << 8) /* PSC[7:0]: Prescaler value */ /* Note: N/A on UART4/5 */ #define USART_GTPR_PSC_MASK 0xFF /* --- USART_RTOR values --------------------------------------------------- */ /* XXX: Preguntar */ /* BLEN[7:0]: Block Length */ #define USART_RTOR_BLEN1_MASK (0xFF << 24) /* RTO[23:0]: Receiver timeout value */ #define USART_RTOR_BLEN2_MASK (0xFFFF << 0) /* --- USART_RQR values --------------------------------------------------- */ /* TXFRQ: Transmit data flush request */ #define USART_RQR_TXFRQ (1 << 4) /* RXFRQ: Receive data flush request */ #define USART_RQR_RXFRQ (1 << 3) /* MMRQ: Mute mode request */ #define USART_RQR_MMRQ (1 << 2) /* SBKRQ: Send break request */ #define USART_RQR_SBKRQ (1 << 1) /* ABRRQ: Auto baud rate request */ #define USART_RQR_ABKRQ (1 << 0) /* --- USART_ISR values --------------------------------------------------- */ /* REACK: Receive enable acknowledge flag */ #define USART_ISR_REACK (1 << 22) /* TEACK: Transmit enable acknowledge flag */ #define USART_ISR_TEACK (1 << 21) /* WUF: Wakeup from Stop mode flag */ #define USART_ISR_WUF (1 << 20) /* RWU: Receiver wakeup from Mute mode */ #define USART_ISR_RWU (1 << 19) /* SBKF: Send break flag */ #define USART_ISR_SBKF (1 << 18) /* CMF: Character match flag */ #define USART_ISR_CMF (1 << 17) /* BUSY: Busy flag */ #define USART_ISR_BUSY (1 << 16) /* ABRF: Auto baud rate flag */ #define USART_ISR_ABRF (1 << 15) /* ABRE: Auto baud rate error */ #define USART_ISR_ABRE (1 << 14) /* EOBF: End of block flag */ #define USART_ISR_EOBF (1 << 12) /* RTOF: Receiver timeout */ #define USART_ISR_RTOF (1 << 11) /* CTS: CTS flag */ #define USART_ISR_CTS (1 << 10) /* CTSIF: CTS interrupt flag */ #define USART_ISR_CTSIF (1 << 9) /* LBDF: LIN break detection flag */ #define USART_ISR_LBDF (1 << 8) /* TXE: Transmit data register empty */ #define USART_ISR_TXE (1 << 7) /* TC: Transmission complete */ #define USART_ISR_TC (1 << 6) /* RXNE: Read data register not empty */ #define USART_ISR_RXNE (1 << 5) /* IDLE: Idle line detected */ #define USART_ISR_IDLE (1 << 4) /* ORE: Overrun error */ #define USART_ISR_ORE (1 << 3) /* NF: Noise detected flag */ #define USART_ISR_NF (1 << 2) /* FE: Framing error */ #define USART_ISR_FE (1 << 1) /* PE: Parity error */ #define USART_ISR_PE (1 << 0) /* --- USART_ICR values --------------------------------------------------- */ /* WUCF: Wakeup from Stop mode clear flag */ #define USART_ICR_WUCF (1 << 20) /* CMCF: Character match clear flag */ #define USART_ICR_CMCF (1 << 17) /* EOBCF: End of timeout clear flag */ #define USART_ICR_EOBCF (1 << 12) /* RTOCF: Receiver timeout clear flag */ #define USART_ICR_RTOCF (1 << 11) /* CTSCF: CTS clear flag */ #define USART_ICR_CTSCF (1 << 9) /* LBDCF: LIN break detection clear flag */ #define USART_ICR_LBDCF (1 << 8) /* TCCF: Transmission complete clear flag */ #define USART_ICR_TCCF (1 << 6) /* IDLECF: Idle line detected clear flag */ #define USART_ICR_IDLECF (1 << 4) /* ORECF: Overrun error clear flag */ #define USART_ICR_ORECF (1 << 3) /* NCF: Noise detected clear flag */ #define USART_ICR_NCF (1 << 2) /* FECF: Framing error clear flag */ #define USART_ICR_FECF (1 << 1) /* PECF: Parity error clear flag */ #define USART_ICR_PECF (1 << 0) /* --- USART_RDR values --------------------------------------------------- */ /* RDR[8:0]: Receive data value */ #define USART_RDR_MASK (0x1FF << 0) /* --- USART_TDR values --------------------------------------------------- */ /* TDR[8:0]: Transmit data value */ #define USART_TDR_MASK (0x1FF << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/000077500000000000000000000000001435536612600224305ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/adc.h000066400000000000000000000736231435536612600233430ustar00rootroot00000000000000/** @defgroup STM32F4xx_adc_defines ADC Defines @brief Defined Constants and Types for the STM32F4xx Analog to Digital Converters @ingroup STM32F4xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Matthew Lai @author @htmlonly © @endhtmlonly 2009 Edward Cheeseman @date 31 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Matthew Lai * Copyright (C) 2009 Edward Cheeseman * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H #include #include /* --- Convenience macros -------------------------------------------------- */ /* ADC port base addresses (for convenience) */ /****************************************************************************/ /** @defgroup adc_reg_base ADC register base addresses @ingroup STM32F4xx_adc_defines @{*/ #define ADC1 ADC1_BASE #define ADC2 ADC2_BASE #define ADC3 ADC3_BASE /**@}*/ /* --- ADC registers ------------------------------------------------------- */ /* ADC status register (ADC_SR) */ #define ADC_SR(block) MMIO32(block + 0x00) #define ADC1_SR ADC_SR(ADC1) #define ADC2_SR ADC_SR(ADC2) #define ADC3_SR ADC_SR(ADC3) /* ADC control register 1 (ADC_CR1) */ #define ADC_CR1(block) MMIO32(block + 0x04) #define ADC1_CR1 ADC_CR1(ADC1) #define ADC2_CR1 ADC_CR1(ADC2) #define ADC3_CR1 ADC_CR1(ADC3) /* ADC control register 2 (ADC_CR2) */ #define ADC_CR2(block) MMIO32(block + 0x08) #define ADC1_CR2 ADC_CR2(ADC1) #define ADC2_CR2 ADC_CR2(ADC2) #define ADC3_CR2 ADC_CR2(ADC3) /* ADC sample time register 1 (ADC_SMPR1) */ #define ADC_SMPR1(block) MMIO32(block + 0x0c) #define ADC1_SMPR1 ADC_SMPR1(ADC1) #define ADC2_SMPR1 ADC_SMPR1(ADC2) #define ADC3_SMPR1 ADC_SMPR1(ADC3) /* ADC sample time register 2 (ADC_SMPR2) */ #define ADC_SMPR2(block) MMIO32(block + 0x10) #define ADC1_SMPR2 ADC_SMPR2(ADC1) #define ADC2_SMPR2 ADC_SMPR2(ADC2) #define ADC3_SMPR2 ADC_SMPR2(ADC3) /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ #define ADC_JOFR1(block) MMIO32(block + 0x14) #define ADC_JOFR2(block) MMIO32(block + 0x18) #define ADC_JOFR3(block) MMIO32(block + 0x1c) #define ADC_JOFR4(block) MMIO32(block + 0x20) #define ADC1_JOFR1 ADC_JOFR1(ADC1) #define ADC2_JOFR1 ADC_JOFR1(ADC2) #define ADC3_JOFR1 ADC_JOFR1(ADC3) #define ADC1_JOFR2 ADC_JOFR2(ADC1) #define ADC2_JOFR2 ADC_JOFR2(ADC2) #define ADC3_JOFR2 ADC_JOFR2(ADC3) #define ADC1_JOFR3 ADC_JOFR3(ADC1) #define ADC2_JOFR3 ADC_JOFR3(ADC2) #define ADC3_JOFR3 ADC_JOFR3(ADC3) #define ADC1_JOFR4 ADC_JOFR4(ADC1) #define ADC2_JOFR4 ADC_JOFR4(ADC2) #define ADC3_JOFR4 ADC_JOFR4(ADC3) /* ADC watchdog high threshold register (ADC_HTR) */ #define ADC_HTR(block) MMIO32(block + 0x24) #define ADC1_HTR ADC_HTR(ADC1) #define ADC2_HTR ADC_HTR(ADC2) #define ADC3_HTR ADC_HTR(ADC3) /* ADC watchdog low threshold register (ADC_LTR) */ #define ADC_LTR(block) MMIO32(block + 0x28) #define ADC1_LTR ADC_LTR(ADC1_BASE) #define ADC2_LTR ADC_LTR(ADC2_BASE) #define ADC3_LTR ADC_LTR(ADC3_BASE) /* ADC regular sequence register 1 (ADC_SQR1) */ #define ADC_SQR1(block) MMIO32(block + 0x2c) #define ADC1_SQR1 ADC_SQR1(ADC1) #define ADC2_SQR1 ADC_SQR1(ADC2) #define ADC3_SQR1 ADC_SQR1(ADC3) /* ADC regular sequence register 2 (ADC_SQR2) */ #define ADC_SQR2(block) MMIO32(block + 0x30) #define ADC1_SQR2 ADC_SQR2(ADC1) #define ADC2_SQR2 ADC_SQR2(ADC2) #define ADC3_SQR2 ADC_SQR2(ADC3) /* ADC regular sequence register 3 (ADC_SQR3) */ #define ADC_SQR3(block) MMIO32(block + 0x34) #define ADC1_SQR3 ADC_SQR3(ADC1) #define ADC2_SQR3 ADC_SQR3(ADC2) #define ADC3_SQR3 ADC_SQR3(ADC3) /* ADC injected sequence register (ADC_JSQR) */ #define ADC_JSQR(block) MMIO32(block + 0x38) #define ADC1_JSQR ADC_JSQR(ADC1_BASE) #define ADC2_JSQR ADC_JSQR(ADC2_BASE) #define ADC3_JSQR ADC_JSQR(ADC3_BASE) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ #define ADC_JDR1(block) MMIO32(block + 0x3c) #define ADC_JDR2(block) MMIO32(block + 0x40) #define ADC_JDR3(block) MMIO32(block + 0x44) #define ADC_JDR4(block) MMIO32(block + 0x48) #define ADC1_JDR1 ADC_JDR1(ADC1) #define ADC2_JDR1 ADC_JDR1(ADC2) #define ADC3_JDR1 ADC_JDR1(ADC3) #define ADC1_JDR2 ADC_JDR2(ADC1) #define ADC2_JDR2 ADC_JDR2(ADC2) #define ADC3_JDR2 ADC_JDR2(ADC3) #define ADC1_JDR3 ADC_JDR3(ADC1) #define ADC2_JDR3 ADC_JDR3(ADC2) #define ADC3_JDR3 ADC_JDR3(ADC3) #define ADC1_JDR4 ADC_JDR4(ADC1) #define ADC2_JDR4 ADC_JDR4(ADC2) #define ADC3_JDR4 ADC_JDR4(ADC3) /* ADC regular data register (ADC_DR) */ #define ADC_DR(block) MMIO32(block + 0x4c) #define ADC1_DR ADC_DR(ADC1) #define ADC2_DR ADC_DR(ADC2) #define ADC3_DR ADC_DR(ADC3) /* ADC common (shared) registers */ #define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) #define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) #define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) #define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) /* --- ADC Channels ------------------------------------------------------- */ /****************************************************************************/ /** @defgroup adc_channel ADC Channel Numbers @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CHANNEL0 0x00 #define ADC_CHANNEL1 0x01 #define ADC_CHANNEL2 0x02 #define ADC_CHANNEL3 0x03 #define ADC_CHANNEL4 0x04 #define ADC_CHANNEL5 0x05 #define ADC_CHANNEL6 0x06 #define ADC_CHANNEL7 0x07 #define ADC_CHANNEL8 0x08 #define ADC_CHANNEL9 0x09 #define ADC_CHANNEL10 0x0A #define ADC_CHANNEL11 0x0B #define ADC_CHANNEL12 0x0C #define ADC_CHANNEL13 0x0D #define ADC_CHANNEL14 0x0E #define ADC_CHANNEL15 0x0F #define ADC_CHANNEL16 0x10 #define ADC_CHANNEL17 0x11 #define ADC_CHANNEL18 0x12 /**@}*/ #define ADC_MASK 0x1F #define ADC_SHIFT 0 /* --- ADC_SR values ------------------------------------------------------- */ #define ADC_SR_OVR (1 << 5) #define ADC_SR_STRT (1 << 4) #define ADC_SR_JSTRT (1 << 3) #define ADC_SR_JEOC (1 << 2) #define ADC_SR_EOC (1 << 1) #define ADC_SR_AWD (1 << 0) /* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */ /* OVRIE: Overrun interrupt enable */ #define ADC_CR1_OVRIE (1 << 26) /* RES[1:0]: Resolution */ /****************************************************************************/ /** @defgroup adc_cr1_res ADC Resolution. @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CR1_RES_12BIT (0x0 << 24) #define ADC_CR1_RES_10BIT (0x1 << 24) #define ADC_CR1_RES_8BIT (0x2 << 24) #define ADC_CR1_RES_6BIT (0x3 << 24) /**@}*/ #define ADC_CR1_RES_MASK (0x3 << 24) #define ADC_CR1_RES_SHIFT 24 /* Note: Bits [21:16] are reserved, and must be kept at reset value. */ /* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ /* AWDEN: Analog watchdog enable on regular channels */ #define ADC_CR1_AWDEN (1 << 23) /* JAWDEN: Analog watchdog enable on injected channels */ #define ADC_CR1_JAWDEN (1 << 22) /* DISCNUM[2:0]: Discontinuous mode channel count. */ /****************************************************************************/ /** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) #define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) #define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) #define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13) #define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13) #define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13) #define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13) #define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) /**@}*/ #define ADC_CR1_DISCNUM_MASK (0x7 << 13) #define ADC_CR1_DISCNUM_SHIFT 13 /* JDISCEN: */ /** Discontinuous mode on injected channels. */ #define ADC_CR1_JDISCEN (1 << 12) /* DISCEN: */ /** Discontinuous mode on regular channels. */ #define ADC_CR1_DISCEN (1 << 11) /* JAUTO: */ /** Automatic Injection Group conversion. */ #define ADC_CR1_JAUTO (1 << 10) /* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */ #define ADC_CR1_AWDSGL (1 << 9) /* SCAN: */ /** Scan mode. */ #define ADC_CR1_SCAN (1 << 8) /* JEOCIE: */ /** Interrupt enable for injected channels. */ #define ADC_CR1_JEOCIE (1 << 7) /* AWDIE: */ /** Analog watchdog interrupt enable. */ #define ADC_CR1_AWDIE (1 << 6) /* EOCIE: */ /** Interrupt enable EOC. */ #define ADC_CR1_EOCIE (1 << 5) /* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ /* Notes: * ADC1: Analog channel 16 and 17 are internally connected to the temperature * sensor and V_REFINT, respectively. * ADC2: Analog channel 16 and 17 are internally connected to V_SS. * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS. */ /****************************************************************************/ /* ADC_CR1 AWDCH[4:0] ADC watchdog channel */ /** @defgroup adc_watchdog_channel ADC watchdog channel @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) #define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) #define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) #define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0) #define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0) #define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0) #define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0) #define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0) #define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0) #define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0) #define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0) #define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0) #define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0) #define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0) #define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0) #define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0) #define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0) #define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) /**@}*/ #define ADC_CR1_AWDCH_MASK (0x1F << 0) #define ADC_CR1_AWDCH_SHIFT 0 /* --- ADC_CR2 values ------------------------------------------------------ */ /* SWSTART: Start conversion of regular channels. */ #define ADC_CR2_SWSTART (1 << 30) /* EXTEN[1:0]: External trigger enable for regular channels. */ /****************************************************************************/ /** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CR2_EXTEN_DISABLED (0x0 << 28) #define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28) #define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28) #define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28) /**@}*/ #define ADC_CR2_EXTEN_MASK (0x3 << 28) #define ADC_CR2_EXTEN_SHIFT 28 /* EXTSEL[3:0]: External event selection for regular group. */ /****************************************************************************/ /** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group @ingroup STM32F4xx_adc_defines @{*/ /** Timer 1 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) /** Timer 1 Compare Output 2 */ #define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) /** Timer 1 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) /** Timer 2 Compare Output 2 */ #define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) /** Timer 2 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24) /** Timer 2 Compare Output 4 */ #define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24) /** Timer 2 TRGO Event */ #define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24) /** Timer 3 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24) /** Timer 3 TRGO Event */ #define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24) /** Timer 4 Compare Output 4 */ #define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24) /** Timer 5 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24) /** Timer 5 Compare Output 2 */ #define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24) /** Timer 5 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24) /** Timer 8 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24) /** Timer 8 TRGO Event */ #define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24) /** EXTI Line 11 Event */ #define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) /**@}*/ #define ADC_CR2_EXTSEL_MASK (0xF << 24) #define ADC_CR2_EXTSEL_SHIFT 24 /* Bit 23 is reserved */ /* JSWSTART: Start conversion of injected channels. */ #define ADC_CR2_JSWSTART (1 << 22) /* JEXTEN[1:0]: External trigger enable for injected channels. */ /****************************************************************************/ /** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CR2_JEXTEN_DISABLED (0x0 << 20) #define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20) #define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20) #define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20) /**@}*/ #define ADC_CR2_JEXTEN_MASK (0x3 << 20) #define ADC_CR2_JEXTEN_SHIFT 20 /* JEXTSEL[3:0]: External event selection for injected group. */ /****************************************************************************/ /** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16) #define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16) #define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16) #define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16) #define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16) #define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16) #define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16) #define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16) #define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16) #define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16) #define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16) #define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16) #define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16) #define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16) #define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) #define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16) /**@}*/ #define ADC_CR2_JEXTSEL_MASK (0xF << 16) #define ADC_CR2_JEXTSEL_SHIFT 16 /* ALIGN: Data alignement. */ #define ADC_CR2_ALIGN_RIGHT (0 << 11) #define ADC_CR2_ALIGN_LEFT (1 << 11) #define ADC_CR2_ALIGN (1 << 11) /* EOCS: End of conversion selection. */ #define ADC_CR2_EOCS (1 << 10) /* DDS: DMA disable selection */ #define ADC_CR2_DDS (1 << 9) /* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ #define ADC_CR2_DMA (1 << 8) /* Note: Bits [7:2] are reserved and must be kept at reset value. */ /* CONT: Continous conversion. */ #define ADC_CR2_CONT (1 << 1) /* ADON: A/D converter On/Off. */ /* Note: If any other bit in this register apart from ADON is changed at the * same time, then conversion is not triggered. This is to prevent triggering * an erroneous conversion. * Conclusion: Must be separately written. */ #define ADC_CR2_ADON (1 << 0) /* --- ADC_SMPR1 values ---------------------------------------------------- */ #define ADC_SMPR1_SMP17_LSB 21 #define ADC_SMPR1_SMP16_LSB 18 #define ADC_SMPR1_SMP15_LSB 15 #define ADC_SMPR1_SMP14_LSB 12 #define ADC_SMPR1_SMP13_LSB 9 #define ADC_SMPR1_SMP12_LSB 6 #define ADC_SMPR1_SMP11_LSB 3 #define ADC_SMPR1_SMP10_LSB 0 #define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) #define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) #define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) #define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) #define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) #define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) #define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) #define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) /* --- ADC_SMPR2 values ---------------------------------------------------- */ #define ADC_SMPR2_SMP9_LSB 27 #define ADC_SMPR2_SMP8_LSB 24 #define ADC_SMPR2_SMP7_LSB 21 #define ADC_SMPR2_SMP6_LSB 18 #define ADC_SMPR2_SMP5_LSB 15 #define ADC_SMPR2_SMP4_LSB 12 #define ADC_SMPR2_SMP3_LSB 9 #define ADC_SMPR2_SMP2_LSB 6 #define ADC_SMPR2_SMP1_LSB 3 #define ADC_SMPR2_SMP0_LSB 0 #define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) #define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) #define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) #define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) #define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) #define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) #define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) #define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) #define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) #define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) /* --- ADC_SMPRx values --------------------------------------------------- */ /****************************************************************************/ /* ADC_SMPRG ADC Sample Time Selection for Channels */ /** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels @ingroup STM32F4xx_adc_defines @{*/ #define ADC_SMPR_SMP_3CYC 0x0 #define ADC_SMPR_SMP_15CYC 0x1 #define ADC_SMPR_SMP_28CYC 0x2 #define ADC_SMPR_SMP_56CYC 0x3 #define ADC_SMPR_SMP_84CYC 0x4 #define ADC_SMPR_SMP_112CYC 0x5 #define ADC_SMPR_SMP_144CYC 0x6 #define ADC_SMPR_SMP_480CYC 0x7 /**@}*/ /* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ #define ADC_JOFFSET_LSB 0 #define ADC_JOFFSET_MSK (0x7ff << 0) #define ADC_HT_LSB 0 #define ADC_HT_MSK (0x7ff << 0) #define ADC_LT_LSB 0 #define ADC_LT_MSK (0x7ff << 0) /* --- ADC_SQR1 values ----------------------------------------------------- */ #define ADC_SQR1_L_LSB 20 #define ADC_SQR1_SQ16_LSB 15 #define ADC_SQR1_SQ15_LSB 10 #define ADC_SQR1_SQ14_LSB 5 #define ADC_SQR1_SQ13_LSB 0 #define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) #define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) #define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) #define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) #define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) /* --- ADC_SQR2 values ----------------------------------------------------- */ #define ADC_SQR2_SQ12_LSB 25 #define ADC_SQR2_SQ11_LSB 20 #define ADC_SQR2_SQ10_LSB 15 #define ADC_SQR2_SQ9_LSB 10 #define ADC_SQR2_SQ8_LSB 5 #define ADC_SQR2_SQ7_LSB 0 #define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) #define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) #define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) #define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) #define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) #define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) /* --- ADC_SQR3 values ----------------------------------------------------- */ #define ADC_SQR3_SQ6_LSB 25 #define ADC_SQR3_SQ5_LSB 20 #define ADC_SQR3_SQ4_LSB 15 #define ADC_SQR3_SQ3_LSB 10 #define ADC_SQR3_SQ2_LSB 5 #define ADC_SQR3_SQ1_LSB 0 #define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) #define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) #define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) #define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) #define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) #define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) /* --- ADC_JSQR values ----------------------------------------------------- */ #define ADC_JSQR_JL_LSB 20 #define ADC_JSQR_JSQ4_LSB 15 #define ADC_JSQR_JSQ3_LSB 10 #define ADC_JSQR_JSQ2_LSB 5 #define ADC_JSQR_JSQ1_LSB 0 /* JL[2:0]: Discontinous mode channel count injected channels. */ /****************************************************************************/ /** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels. @ingroup STM32F4xx_adc_defines @{*/ #define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) /**@}*/ #define ADC_JSQR_JL_SHIFT 13 #define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) #define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ #define ADC_JDATA_LSB 0 #define ADC_DATA_LSB 0 #define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) #define ADC_DATA_MSK (0xffff << ADC_DA) /* --- Common Registers ---------------------------------------------------- */ /* --- ADC_CSR values (read only images) ------------------------------------ */ /* OVR3: Overrun ADC3. */ #define ADC_CSR_OVR3 (1 << 21) /* STRT3: Regular channel start ADC3. */ #define ADC_CSR_STRT3 (1 << 20) /* JSTRT3: Injected channel start ADC3. */ #define ADC_CSR_JSTRT3 (1 << 19) /* JEOC3: Injected channel end of conversion ADC3. */ #define ADC_CSR_JEOC3 (1 << 18) /* EOC3: Regular channel end of conversion ADC3. */ #define ADC_CSR_EOC3 (1 << 17) /* EOC3: Regular channel end of conversion ADC3. */ #define ADC_CSR_AWD3 (1 << 16) /* Bits 15:14 Reserved, must be kept at reset value */ /* OVR2: Overrun ADC2. */ #define ADC_CSR_OVR2 (1 << 13) /* STRT2: Regular channel start ADC2. */ #define ADC_CSR_STRT2 (1 << 12) /* JSTRT2: Injected channel start ADC2. */ #define ADC_CSR_JSTRT2 (1 << 11) /* JEOC2: Injected channel end of conversion ADC2. */ #define ADC_CSR_JEOC2 (1 << 10) /* EOC2: Regular channel end of conversion ADC2. */ #define ADC_CSR_EOC2 (1 << 9) /* EOC2: Regular channel end of conversion ADC2. */ #define ADC_CSR_AWD2 (1 << 8) /* Bits 7:6 Reserved, must be kept at reset value */ /* OVR1: Overrun ADC1. */ #define ADC_CSR_OVR1 (1 << 5) /* STRT1: Regular channel start ADC1. */ #define ADC_CSR_STRT1 (1 << 4) /* JSTRT1: Injected channel start ADC1. */ #define ADC_CSR_JSTRT1 (1 << 3) /* JEOC1: Injected channel end of conversion ADC1. */ #define ADC_CSR_JEOC1 (1 << 2) /* EOC1: Regular channel end of conversion ADC1. */ #define ADC_CSR_EOC1 (1 << 1) /* EOC1: Regular channel end of conversion ADC1. */ #define ADC_CSR_AWD1 (1 << 0) /* --- ADC_CCR values ------------------------------------------------------ */ /* TSVREFE: Temperature sensor and Vrefint enable. */ #define ADC_CCR_TSVREFE (1 << 23) /* VBATE: VBat enable. */ #define ADC_CCR_VBATE (1 << 22) /* Bit 18:21 reserved, must be kept at reset value. */ /* ADCPRE: ADC prescaler. */ /****************************************************************************/ /** @defgroup adc_ccr_adcpre ADC Prescale @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CCR_ADCPRE_BY2 (0x0 << 16) #define ADC_CCR_ADCPRE_BY4 (0x1 << 16) #define ADC_CCR_ADCPRE_BY6 (0x2 << 16) #define ADC_CCR_ADCPRE_BY8 (0x3 << 16) /**@}*/ #define ADC_CCR_ADCPRE_MASK (0x3 << 16) #define ADC_CCR_ADCPRE_SHIFT 16 /* DMA: Direct memory access mode for multi ADC mode. */ /****************************************************************************/ /** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CCR_DMA_DISABLE (0x0 << 14) #define ADC_CCR_DMA_MODE_1 (0x1 << 14) #define ADC_CCR_DMA_MODE_2 (0x2 << 14) #define ADC_CCR_DMA_MODE_3 (0x3 << 14) /**@}*/ #define ADC_CCR_DMA_MASK (0x3 << 14) #define ADC_CCR_DMA_SHIFT 14 /* DDS: DMA disable selection (for multi-ADC mode). */ #define ADC_CCR_DDS (1 << 13) /* Bit 12 reserved, must be kept at reset value */ /* DELAY: Delay between 2 sampling phases. */ /****************************************************************************/ /** @defgroup adc_delay ADC Delay between 2 sampling phases @ingroup STM32F4xx_adc_defines @{*/ #define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) #define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) #define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) #define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) #define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) #define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) #define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) #define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) #define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) #define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) #define ADC_CCR_DELAY_15ADCCLK (0xa << 8) #define ADC_CCR_DELAY_16ADCCLK (0xb << 8) #define ADC_CCR_DELAY_17ADCCLK (0xc << 8) #define ADC_CCR_DELAY_18ADCCLK (0xd << 8) #define ADC_CCR_DELAY_19ADCCLK (0xe << 8) #define ADC_CCR_DELAY_20ADCCLK (0xf << 8) /**@}*/ #define ADC_CCR_DELAY_MASK (0xf << 8) #define ADC_CCR_DELAY_SHIFT 8 /* Bit 7:5 reserved, must be kept at reset value */ /* MULTI: Multi ADC mode selection. */ /****************************************************************************/ /** @defgroup adc_multi_mode ADC Multi mode selection @ingroup STM32F4xx_adc_defines @{*/ /** All ADCs independent */ #define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) /* Dual modes (ADC1 + ADC2) */ /** * Dual modes (ADC1 + ADC2) Combined regular simultaneous + * injected simultaneous mode. */ #define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) /** * Dual modes (ADC1 + ADC2) Combined regular simultaneous + * alternate trigger mode. */ #define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) /** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ #define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) /** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ #define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) /** Dual modes (ADC1 + ADC2) Interleaved mode only. */ #define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) /** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ #define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) /* Triple modes (ADC1 + ADC2 + ADC3) */ /** * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + * injected simultaneous mode. */ #define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) /** * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + * alternate trigger mode. */ #define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ #define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ #define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ #define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ #define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) /**@}*/ #define ADC_CCR_MULTI_MASK (0x1f << 0) #define ADC_CCR_MULTI_SHIFT 0 /* --- ADC_CDR values ------------------------------------------------------ */ #define ADC_CDR_DATA2_MASK (0xffff << 16) #define ADC_CDR_DATA2_SHIFT 16 #define ADC_CDR_DATA1_MASK (0xffff << 0) #define ADC_CDR_DATA1_SHIFT 0 BEGIN_DECLS void adc_power_on(uint32_t adc); void adc_off(uint32_t adc); void adc_enable_analog_watchdog_regular(uint32_t adc); void adc_disable_analog_watchdog_regular(uint32_t adc); void adc_enable_analog_watchdog_injected(uint32_t adc); void adc_disable_analog_watchdog_injected(uint32_t adc); void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); void adc_disable_discontinuous_mode_regular(uint32_t adc); void adc_enable_discontinuous_mode_injected(uint32_t adc); void adc_disable_discontinuous_mode_injected(uint32_t adc); void adc_enable_automatic_injected_group_conversion(uint32_t adc); void adc_disable_automatic_injected_group_conversion(uint32_t adc); void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel); void adc_enable_scan_mode(uint32_t adc); void adc_disable_scan_mode(uint32_t adc); void adc_enable_eoc_interrupt_injected(uint32_t adc); void adc_disable_eoc_interrupt_injected(uint32_t adc); void adc_enable_awd_interrupt(uint32_t adc); void adc_disable_awd_interrupt(uint32_t adc); void adc_enable_eoc_interrupt(uint32_t adc); void adc_disable_eoc_interrupt(uint32_t adc); void adc_start_conversion_regular(uint32_t adc); void adc_start_conversion_injected(uint32_t adc); void adc_disable_external_trigger_regular(uint32_t adc); void adc_disable_external_trigger_injected(uint32_t adc); void adc_set_left_aligned(uint32_t adc); void adc_set_right_aligned(uint32_t adc); void adc_enable_dma(uint32_t adc); void adc_disable_dma(uint32_t adc); void adc_set_continuous_conversion_mode(uint32_t adc); void adc_set_single_conversion_mode(uint32_t adc); void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold); void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold); void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); bool adc_eoc(uint32_t adc); bool adc_eoc_injected(uint32_t adc); uint32_t adc_read_regular(uint32_t adc); uint32_t adc_read_injected(uint32_t adc, uint8_t reg); void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); void adc_set_clk_prescale(uint32_t prescaler); void adc_set_multi_mode(uint32_t mode); void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity); void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity); void adc_set_resolution(uint32_t adc, uint32_t resolution); void adc_enable_overrun_interrupt(uint32_t adc); void adc_disable_overrun_interrupt(uint32_t adc); bool adc_get_overrun_flag(uint32_t adc); void adc_clear_overrun_flag(uint32_t adc); bool adc_awd(uint32_t adc); void adc_eoc_after_each(uint32_t adc); void adc_eoc_after_group(uint32_t adc); void adc_set_dma_continue(uint32_t adc); void adc_set_dma_terminate(uint32_t adc); void adc_enable_temperature_sensor(void); void adc_disable_temperature_sensor(void); END_DECLS /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/crc.h000066400000000000000000000022171435536612600233520ustar00rootroot00000000000000/** @defgroup crc_defines CRC Defines @brief libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator @ingroup STM32F4xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRC_H #define LIBOPENCM3_CRC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/crypto.h000066400000000000000000000055441435536612600241310ustar00rootroot00000000000000/** @defgroup crypto_defines CRYPTO Defines * * @brief Defined constants and Types for the STM32F4xx Crypto Coprocessor * * @ingroup STM32F4xx_defines * * @version 1.0.0 * * @date 22 Jun 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRYPTO_H #define LIBOPENCM3_CRYPTO_H #include #include /**@{*/ /* --- CRYP registers ------------------------------------------------------ */ /** @defgroup crypto_defines_registers Registers (for F42xx or F43xx only) * * @brief Register access to the CRYP controller. Registers for F42xx and 43xx * * @ingroup crypto_defines */ /**@{*/ /* CRYP_CSGCMCCMxR: Crypto context registers CCM mode, i=0-7*/ #define CRYP_CSGCMCCMR(i) MMIO32(CRYP_BASE + 0x50 + (i) * 4) /* CRYP_CSGCMxR: Crypto context registers all modes, i=0-7*/ #define CRYP_CSGCMR(i) MMIO32(CRYP_BASE + 0x70 + (i) * 4) /* --- CRYP_CR values ------------------------------------------------------ */ /* Only for part STM32F42xx and STM32F43xx: */ /* GCM_CMPH: GCM or CCM phase state */ #define CRYP_CR_GCM_CMPH_SHIFT 16 #define CRYP_CR_GCM_CMPH (3 << CRYP_CR_GCM_CMPH_SHIFT) #define CRYP_CR_GCM_CMPH_INIT (0 << CRYP_CR_GCM_CMPH_SHIFT) #define CRYP_CR_GCM_CMPH_HEADER (1 << CRYP_CR_GCM_CMPH_SHIFT) #define CRYP_CR_GCM_CMPH_PAYLOAD (2 << CRYP_CR_GCM_CMPH_SHIFT) #define CRYP_CR_GCM_CMPH_FINAL (3 << CRYP_CR_GCM_CMPH_SHIFT) /* ALGOMODE3: Algorithm mode, fourth bit */ #define CRYP_CR_ALGOMODE3 (1 << 19) /**@}*/ /** @defgroup crypto_api API (for F42xx or F43xx only) * * @brief API for the CRYP controller. * * @warning Only for F42xx and 43xx * * @ingroup crypto_defines */ /**@{*/ enum crypto_mode_mac { ENCRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3, ENCRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3, DECRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3 | CRYP_CR_ALGODIR, DECRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3 | CRYP_CR_ALGODIR, }; BEGIN_DECLS void crypto_context_swap(uint32_t *buf); void crypto_set_mac_algorithm(enum crypto_mode_mac mode); END_DECLS /**@}*/ /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/dac.h000066400000000000000000000021031435536612600233240ustar00rootroot00000000000000/** @defgroup dac_defines DAC Defines @brief Defined Constants and Types for the STM32F4xx DAC @ingroup STM32F4xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DAC_H #define LIBOPENCM3_DAC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/dma.h000066400000000000000000000021101435536612600233340ustar00rootroot00000000000000/** @defgroup dma_defines DMA Defines @ingroup STM32F4xx_defines @brief Defined Constants and Types for the STM32F4xx DMA Controller @version 1.0.0 @date 30 November 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DMA_H #define LIBOPENCM3_DMA_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/doc-stm32f4.h000066400000000000000000000010411435536612600245420ustar00rootroot00000000000000/** @mainpage libopencm3 STM32F4 @version 1.0.0 @date 7 September 2012 API documentation for ST Microelectronics STM32F4 Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F4xx STM32F4xx Libraries for ST Microelectronics STM32F4xx series. @version 1.0.0 @date 7 September 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup STM32F4xx_defines STM32F4xx Defines @brief Defined Constants and Types for the STM32F4xx series @version 1.0.0 @date 7 September 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/exti.h000066400000000000000000000016611435536612600235560ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_EXTI_H #define LIBOPENCM3_EXTI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/flash.h000066400000000000000000000015641435536612600237040ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_FLASH_H #define LIBOPENCM3_FLASH_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/gpio.h000066400000000000000000000021241435536612600235360ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines @brief Defined Constants and Types for the STM32F4xx General Purpose I/O @ingroup STM32F4xx_defines @version 1.0.0 @date 1 July 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_GPIO_H #define LIBOPENCM3_GPIO_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/hash.h000066400000000000000000000021101435536612600235160ustar00rootroot00000000000000/** @defgroup hash_defines HASH Defines @ingroup STM32F4xx_defines @brief Defined Constants and Types for the STM32F4xx HASH Controller @version 1.0.0 @date 31 May 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_HASH_H #define LIBOPENCM3_HASH_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/i2c.h000066400000000000000000000021041435536612600232530ustar00rootroot00000000000000/** @defgroup i2c_defines I2C Defines @brief Defined Constants and Types for the STM32F4xx I2C @ingroup STM32F4xx_defines @version 1.0.0 @date 12 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_I2C_H #define LIBOPENCM3_I2C_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/irq.yaml000066400000000000000000000022321435536612600241060ustar00rootroot00000000000000includeguard: LIBOPENCM3_STM32_F4_NVIC_H partname_humanreadable: STM32 F4 series partname_doxygen: STM32F4 irqs: - nvic_wwdg - pvd - tamp_stamp - rtc_wkup - flash - rcc - exti0 - exti1 - exti2 - exti3 - exti4 - dma1_stream0 - dma1_stream1 - dma1_stream2 - dma1_stream3 - dma1_stream4 - dma1_stream5 - dma1_stream6 - adc - can1_tx - can1_rx0 - can1_rx1 - can1_sce - exti9_5 - tim1_brk_tim9 - tim1_up_tim10 - tim1_trg_com_tim11 - tim1_cc - tim2 - tim3 - tim4 - i2c1_ev - i2c1_er - i2c2_ev - i2c2_er - spi1 - spi2 - usart1 - usart2 - usart3 - exti15_10 - rtc_alarm - usb_fs_wkup - tim8_brk_tim12 - tim8_up_tim13 - tim8_trg_com_tim14 - tim8_cc - dma1_stream7 - fsmc - sdio - tim5 - spi3 - uart4 - uart5 - tim6_dac - tim7 - dma2_stream0 - dma2_stream1 - dma2_stream2 - dma2_stream3 - dma2_stream4 - eth - eth_wkup - can2_tx - can2_rx0 - can2_rx1 - can2_sce - otg_fs - dma2_stream5 - dma2_stream6 - dma2_stream7 - usart6 - i2c3_ev - i2c3_er - otg_hs_ep1_out - otg_hs_ep1_in - otg_hs_wkup - otg_hs - dcmi - cryp - hash_rng hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/iwdg.h000066400000000000000000000022261435536612600235350ustar00rootroot00000000000000/** @defgroup iwdg_defines IWDG Defines @brief Defined Constants and Types for the STM32F4xx Independent Watchdog Timer @ingroup STM32F4xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_IWDG_H #define LIBOPENCM3_IWDG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/memorymap.h000066400000000000000000000137611435536612600246170ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_MEMORYMAP_H #define LIBOPENCM3_MEMORYMAP_H #include /* --- STM32F4 specific peripheral definitions ----------------------------- */ /* Memory map for all busses */ #define PERIPH_BASE 0x40000000 #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) #define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) #define PERIPH_BASE_AHB2 0x50000000 #define PERIPH_BASE_AHB3 0x60000000 /* Register boundary addresses */ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) #define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) #define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) #define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) /* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ #define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) #define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) #define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) /* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ #define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) #define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) /* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) /* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ /* APB2 */ #define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) #define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) /* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ #define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) #define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) /* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ #define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) #define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) #define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) #define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) /* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ #define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) /* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */ #define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) #define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) #define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) #define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) #define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) /* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */ /* AHB1 */ #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) #define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) #define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) #define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) #define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) #define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) #define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) #define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) /* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ #define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) /* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ #define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) #define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) /* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ #define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) #define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) /* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ #define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) /* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ #define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) /* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ /* AHB2 */ #define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000) /* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ #define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) /* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ #define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) #define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) /* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */ #define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) /* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ /* AHB3 */ #define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) /* PPIB */ #define DBGMCU_BASE (PPBI_BASE + 0x00042000) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/pwr.h000066400000000000000000000043311435536612600234120ustar00rootroot00000000000000/** @defgroup pwr_defines PWR Defines @brief Defined Constants and Types for the STM32F4xx Power Control @ingroup STM32F4xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2011 Stephen Caudle @date 4 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_PWR_H #define LIBOPENCM3_PWR_H #include #include /* * This file extends the common STM32 version with definitions only * applicable to the STM32F4 series of devices. */ /* --- PWR_CR values ------------------------------------------------------- */ /* Bits [31:15]: Reserved */ /* VOS: Regulator voltage scaling output selection */ #define PWR_CR_VOS (1 << 14) /* Bits [13:10]: Reserved */ /* FPDS: Flash power down in stop mode */ #define PWR_CR_FPDS (1 << 9) /* --- PWR_CSR values ------------------------------------------------------ */ /* Bits [31:15]: Reserved */ /* VOSRDY: Regulator voltage scaling output selection ready bit */ #define PWR_CSR_VOSRDY (1 << 14) /* Bits [13:10]: Reserved */ /* BRE: Backup regulator enable */ #define PWR_CSR_BRE (1 << 9) /* Bits [7:4]: Reserved */ /* BRR: Backup regulator ready */ #define PWR_CSR_BRR (1 << 3) /* --- Function prototypes ------------------------------------------------- */ typedef enum { SCALE1, SCALE2, } vos_scale_t; BEGIN_DECLS void pwr_set_vos_scale(vos_scale_t scale); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/rcc.h000066400000000000000000000440601435536612600233540ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2011 Fergus Noble * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RCC_H #define LIBOPENCM3_RCC_H #include #include /* --- RCC registers ------------------------------------------------------- */ #define RCC_CR MMIO32(RCC_BASE + 0x00) #define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) #define RCC_CFGR MMIO32(RCC_BASE + 0x08) #define RCC_CIR MMIO32(RCC_BASE + 0x0c) #define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) #define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) #define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) /* RCC_BASE + 0x1c Reserved */ #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) /* RCC_BASE + 0x28 Reserved */ /* RCC_BASE + 0x2c Reserved */ #define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) #define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) #define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) /* RCC_BASE + 0x3c Reserved */ #define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) #define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) /* RCC_BASE + 0x48 Reserved */ /* RCC_BASE + 0x4c Reserved */ #define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) #define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) #define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) /* RCC_BASE + 0x5c Reserved */ #define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) #define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) /* RCC_BASE + 0x68 Reserved */ /* RCC_BASE + 0x6c Reserved */ #define RCC_BDCR MMIO32(RCC_BASE + 0x70) #define RCC_CSR MMIO32(RCC_BASE + 0x74) /* RCC_BASE + 0x78 Reserved */ /* RCC_BASE + 0x7c Reserved */ #define RCC_SSCGR MMIO32(RCC_BASE + 0x80) #define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) /* --- RCC_CR values ------------------------------------------------------- */ #define RCC_CR_PLLI2SRDY (1 << 27) #define RCC_CR_PLLI2SON (1 << 26) #define RCC_CR_PLLRDY (1 << 25) #define RCC_CR_PLLON (1 << 24) #define RCC_CR_CSSON (1 << 19) #define RCC_CR_HSEBYP (1 << 18) #define RCC_CR_HSERDY (1 << 17) #define RCC_CR_HSEON (1 << 16) /* HSICAL: [15:8] */ /* HSITRIM: [7:3] */ #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) /* --- RCC_PLLCFGR values -------------------------------------------------- */ /* PLLQ: [27:24] */ #define RCC_PLLCFGR_PLLQ_SHIFT 24 #define RCC_PLLCFGR_PLLSRC (1 << 22) /* PLLP: [17:16] */ #define RCC_PLLCFGR_PLLP_SHIFT 16 /* PLLN: [14:6] */ #define RCC_PLLCFGR_PLLN_SHIFT 6 /* PLLM: [5:0] */ #define RCC_PLLCFGR_PLLM_SHIFT 0 /* --- RCC_CFGR values ----------------------------------------------------- */ /* MCO2: Microcontroller clock output 2 */ #define RCC_CFGR_MCO2_SHIFT 30 #define RCC_CFGR_MCO2_SYSCLK 0x0 #define RCC_CFGR_MCO2_PLLI2S 0x1 #define RCC_CFGR_MCO2_HSE 0x2 #define RCC_CFGR_MCO2_PLL 0x3 /* MCO1/2PRE: MCO Prescalers */ #define RCC_CFGR_MCO2PRE_SHIFT 27 #define RCC_CFGR_MCO1PRE_SHIFT 24 #define RCC_CFGR_MCOPRE_DIV_NONE 0x0 #define RCC_CFGR_MCOPRE_DIV_2 0x4 #define RCC_CFGR_MCOPRE_DIV_3 0x5 #define RCC_CFGR_MCOPRE_DIV_4 0x6 #define RCC_CFGR_MCOPRE_DIV_5 0x7 /* I2SSRC: I2S clock selection */ #define RCC_CFGR_I2SSRC (1 << 23) /* MCO1: Microcontroller clock output 1 */ #define RCC_CFGR_MCO1_SHIFT 21 #define RCC_CFGR_MCO1_HSI 0x0 #define RCC_CFGR_MCO1_LSE 0x1 #define RCC_CFGR_MCO1_HSE 0x2 #define RCC_CFGR_MCO1_PLL 0x3 /* RTCPRE: HSE division factor for RTC clock */ #define RCC_CFGR_RTCPRE_SHIFT 21 /* PPRE1/2: APB high-speed prescalers */ #define RCC_CFGR_PPRE2_SHIFT 13 #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE_DIV_NONE 0x0 #define RCC_CFGR_PPRE_DIV_2 0x4 #define RCC_CFGR_PPRE_DIV_4 0x5 #define RCC_CFGR_PPRE_DIV_8 0x6 #define RCC_CFGR_PPRE_DIV_16 0x7 /* HPRE: AHB high-speed prescaler */ #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_DIV_NONE 0x0 #define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) #define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) #define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) #define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) #define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) #define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) #define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) #define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SHIFT 2 #define RCC_CFGR_SWS_HSI 0x0 #define RCC_CFGR_SWS_HSE 0x1 #define RCC_CFGR_SWS_PLL 0x2 /* SW: System clock switch */ #define RCC_CFGR_SW_SHIFT 0 #define RCC_CFGR_SW_HSI 0x0 #define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_PLL 0x2 /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ #define RCC_CIR_CSSC (1 << 23) /* OSC ready interrupt clear bits */ #define RCC_CIR_PLLI2SRDYC (1 << 21) #define RCC_CIR_PLLRDYC (1 << 20) #define RCC_CIR_HSERDYC (1 << 19) #define RCC_CIR_HSIRDYC (1 << 18) #define RCC_CIR_LSERDYC (1 << 17) #define RCC_CIR_LSIRDYC (1 << 16) /* OSC ready interrupt enable bits */ #define RCC_CIR_PLLI2SRDYIE (1 << 13) #define RCC_CIR_PLLRDYIE (1 << 12) #define RCC_CIR_HSERDYIE (1 << 11) #define RCC_CIR_HSIRDYIE (1 << 10) #define RCC_CIR_LSERDYIE (1 << 9) #define RCC_CIR_LSIRDYIE (1 << 8) /* Clock security system interrupt flag bit */ #define RCC_CIR_CSSF (1 << 7) /* OSC ready interrupt flag bits */ #define RCC_CIR_PLLI2SRDYF (1 << 5) #define RCC_CIR_PLLRDYF (1 << 4) #define RCC_CIR_HSERDYF (1 << 3) #define RCC_CIR_HSIRDYF (1 << 2) #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) /* --- RCC_AHB1RSTR values ------------------------------------------------- */ #define RCC_AHB1RSTR_OTGHSRST (1 << 29) #define RCC_AHB1RSTR_ETHMACRST (1 << 25) #define RCC_AHB1RSTR_DMA2RST (1 << 22) #define RCC_AHB1RSTR_DMA1RST (1 << 21) #define RCC_AHB1RSTR_CRCRST (1 << 12) #define RCC_AHB1RSTR_IOPIRST (1 << 8) #define RCC_AHB1RSTR_IOPHRST (1 << 7) #define RCC_AHB1RSTR_IOPGRST (1 << 6) #define RCC_AHB1RSTR_IOPFRST (1 << 5) #define RCC_AHB1RSTR_IOPERST (1 << 4) #define RCC_AHB1RSTR_IOPDRST (1 << 3) #define RCC_AHB1RSTR_IOPCRST (1 << 2) #define RCC_AHB1RSTR_IOPBRST (1 << 1) #define RCC_AHB1RSTR_IOPARST (1 << 0) /* --- RCC_AHB2RSTR values ------------------------------------------------- */ #define RCC_AHB2RSTR_OTGFSRST (1 << 7) #define RCC_AHB2RSTR_RNGRST (1 << 6) #define RCC_AHB2RSTR_HASHRST (1 << 5) #define RCC_AHB2RSTR_CRYPRST (1 << 4) #define RCC_AHB2RSTR_DCMIRST (1 << 0) /* --- RCC_AHB3RSTR values ------------------------------------------------- */ #define RCC_AHB3RSTR_FSMCRST (1 << 0) /* --- RCC_APB1RSTR values ------------------------------------------------- */ #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) #define RCC_APB1RSTR_CAN2RST (1 << 26) #define RCC_APB1RSTR_CAN1RST (1 << 25) #define RCC_APB1RSTR_I2C3RST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) #define RCC_APB1RSTR_UART5RST (1 << 20) #define RCC_APB1RSTR_UART4RST (1 << 19) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) #define RCC_APB1RSTR_SPI3RST (1 << 15) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_TIM14RST (1 << 8) #define RCC_APB1RSTR_TIM13RST (1 << 7) #define RCC_APB1RSTR_TIM12RST (1 << 6) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM5RST (1 << 3) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) /* --- RCC_APB2RSTR values ------------------------------------------------- */ #define RCC_APB2RSTR_TIM11RST (1 << 18) #define RCC_APB2RSTR_TIM10RST (1 << 17) #define RCC_APB2RSTR_TIM9RST (1 << 16) #define RCC_APB2RSTR_SYSCFGRST (1 << 14) #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_SDIORST (1 << 11) #define RCC_APB2RSTR_ADCRST (1 << 8) #define RCC_APB2RSTR_USART6RST (1 << 5) #define RCC_APB2RSTR_USART1RST (1 << 4) #define RCC_APB2RSTR_TIM8RST (1 << 1) #define RCC_APB2RSTR_TIM1RST (1 << 0) /* --- RCC_AHB1ENR values ------------------------------------------------- */ #define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) #define RCC_AHB1ENR_OTGHSEN (1 << 29) #define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) #define RCC_AHB1ENR_ETHMACRXEN (1 << 27) #define RCC_AHB1ENR_ETHMACTXEN (1 << 26) #define RCC_AHB1ENR_ETHMACEN (1 << 25) #define RCC_AHB1ENR_DMA2EN (1 << 22) #define RCC_AHB1ENR_DMA1EN (1 << 21) #define RCC_AHB1ENR_BKPSRAMEN (1 << 18) #define RCC_AHB1ENR_CRCEN (1 << 12) #define RCC_AHB1ENR_IOPIEN (1 << 8) #define RCC_AHB1ENR_IOPHEN (1 << 7) #define RCC_AHB1ENR_IOPGEN (1 << 6) #define RCC_AHB1ENR_IOPFEN (1 << 5) #define RCC_AHB1ENR_IOPEEN (1 << 4) #define RCC_AHB1ENR_IOPDEN (1 << 3) #define RCC_AHB1ENR_IOPCEN (1 << 2) #define RCC_AHB1ENR_IOPBEN (1 << 1) #define RCC_AHB1ENR_IOPAEN (1 << 0) /* --- RCC_AHB2ENR values ------------------------------------------------- */ #define RCC_AHB2ENR_OTGFSEN (1 << 7) #define RCC_AHB2ENR_RNGEN (1 << 6) #define RCC_AHB2ENR_HASHEN (1 << 5) #define RCC_AHB2ENR_CRYPEN (1 << 4) #define RCC_AHB2ENR_DCMIEN (1 << 0) /* --- RCC_AHB3ENR values ------------------------------------------------- */ #define RCC_AHB3ENR_FSMCEN (1 << 0) /* --- RCC_APB1ENR values ------------------------------------------------- */ #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_CAN2EN (1 << 26) #define RCC_APB1ENR_CAN1EN (1 << 25) #define RCC_APB1ENR_I2C3EN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) #define RCC_APB1ENR_UART5EN (1 << 20) #define RCC_APB1ENR_UART4EN (1 << 19) #define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) #define RCC_APB1ENR_SPI3EN (1 << 15) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_TIM14EN (1 << 8) #define RCC_APB1ENR_TIM13EN (1 << 7) #define RCC_APB1ENR_TIM12EN (1 << 6) #define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM5EN (1 << 3) #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /* --- RCC_APB2ENR values ------------------------------------------------- */ #define RCC_APB2ENR_TIM11EN (1 << 18) #define RCC_APB2ENR_TIM10EN (1 << 17) #define RCC_APB2ENR_TIM9EN (1 << 16) #define RCC_APB2ENR_SYSCFGEN (1 << 14) #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_SDIOEN (1 << 11) #define RCC_APB2ENR_ADC3EN (1 << 10) #define RCC_APB2ENR_ADC2EN (1 << 9) #define RCC_APB2ENR_ADC1EN (1 << 8) #define RCC_APB2ENR_USART6EN (1 << 5) #define RCC_APB2ENR_USART1EN (1 << 4) #define RCC_APB2ENR_TIM8EN (1 << 1) #define RCC_APB2ENR_TIM1EN (1 << 0) /* --- RCC_AHB1LPENR values ------------------------------------------------- */ #define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) #define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) #define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) #define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) #define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) #define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) #define RCC_AHB1LPENR_DMA2LPEN (1 << 22) #define RCC_AHB1LPENR_DMA1LPEN (1 << 21) #define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) #define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) #define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) #define RCC_AHB1LPENR_FLITFLPEN (1 << 15) #define RCC_AHB1LPENR_CRCLPEN (1 << 12) #define RCC_AHB1LPENR_IOPILPEN (1 << 8) #define RCC_AHB1LPENR_IOPHLPEN (1 << 7) #define RCC_AHB1LPENR_IOPGLPEN (1 << 6) #define RCC_AHB1LPENR_IOPFLPEN (1 << 5) #define RCC_AHB1LPENR_IOPELPEN (1 << 4) #define RCC_AHB1LPENR_IOPDLPEN (1 << 3) #define RCC_AHB1LPENR_IOPCLPEN (1 << 2) #define RCC_AHB1LPENR_IOPBLPEN (1 << 1) #define RCC_AHB1LPENR_IOPALPEN (1 << 0) /* --- RCC_AHB2LPENR values ------------------------------------------------- */ #define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) #define RCC_AHB2LPENR_RNGLPEN (1 << 6) #define RCC_AHB2LPENR_HASHLPEN (1 << 5) #define RCC_AHB2LPENR_CRYPLPEN (1 << 4) #define RCC_AHB2LPENR_DCMILPEN (1 << 0) /* --- RCC_AHB3LPENR values ------------------------------------------------- */ #define RCC_AHB3LPENR_FSMCLPEN (1 << 0) /* --- RCC_APB1LPENR values ------------------------------------------------- */ #define RCC_APB1LPENR_DACLPEN (1 << 29) #define RCC_APB1LPENR_PWRLPEN (1 << 28) #define RCC_APB1LPENR_CAN2LPEN (1 << 26) #define RCC_APB1LPENR_CAN1LPEN (1 << 25) #define RCC_APB1LPENR_I2C3LPEN (1 << 23) #define RCC_APB1LPENR_I2C2LPEN (1 << 22) #define RCC_APB1LPENR_I2C1LPEN (1 << 21) #define RCC_APB1LPENR_UART5LPEN (1 << 20) #define RCC_APB1LPENR_UART4LPEN (1 << 19) #define RCC_APB1LPENR_USART3LPEN (1 << 18) #define RCC_APB1LPENR_USART2LPEN (1 << 17) #define RCC_APB1LPENR_SPI3LPEN (1 << 15) #define RCC_APB1LPENR_SPI2LPEN (1 << 14) #define RCC_APB1LPENR_WWDGLPEN (1 << 11) #define RCC_APB1LPENR_TIM14LPEN (1 << 8) #define RCC_APB1LPENR_TIM13LPEN (1 << 7) #define RCC_APB1LPENR_TIM12LPEN (1 << 6) #define RCC_APB1LPENR_TIM7LPEN (1 << 5) #define RCC_APB1LPENR_TIM6LPEN (1 << 4) #define RCC_APB1LPENR_TIM5LPEN (1 << 3) #define RCC_APB1LPENR_TIM4LPEN (1 << 2) #define RCC_APB1LPENR_TIM3LPEN (1 << 1) #define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* --- RCC_APB2LPENR values ------------------------------------------------- */ #define RCC_APB2LPENR_TIM11LPEN (1 << 18) #define RCC_APB2LPENR_TIM10LPEN (1 << 17) #define RCC_APB2LPENR_TIM9LPEN (1 << 16) #define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) #define RCC_APB2LPENR_SPI1LPEN (1 << 12) #define RCC_APB2LPENR_SDIOLPEN (1 << 11) #define RCC_APB2LPENR_ADC3LPEN (1 << 10) #define RCC_APB2LPENR_ADC2LPEN (1 << 9) #define RCC_APB2LPENR_ADC1LPEN (1 << 8) #define RCC_APB2LPENR_USART6LPEN (1 << 5) #define RCC_APB2LPENR_USART1LPEN (1 << 4) #define RCC_APB2LPENR_TIM8LPEN (1 << 1) #define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* --- RCC_BDCR values ----------------------------------------------------- */ #define RCC_BDCR_BDRST (1 << 16) #define RCC_BDCR_RTCEN (1 << 15) /* RCC_BDCR[9:8]: RTCSEL */ #define RCC_BDCR_LSEBYP (1 << 2) #define RCC_BDCR_LSERDY (1 << 1) #define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ #define RCC_CSR_LPWRRSTF (1 << 31) #define RCC_CSR_WWDGRSTF (1 << 30) #define RCC_CSR_IWDGRSTF (1 << 29) #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) #define RCC_CSR_BORRSTF (1 << 25) #define RCC_CSR_RMVF (1 << 24) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) /* --- RCC_SSCGR values ---------------------------------------------------- */ /* PLL spread spectrum clock generation documented in Datasheet. */ #define RCC_SSCGR_SSCGEN (1 << 31) #define RCC_SSCGR_SPREADSEL (1 << 30) /* RCC_SSCGR[27:16]: INCSTEP */ #define RCC_SSCGR_INCSTEP_SHIFT 16 /* RCC_SSCGR[15:0]: MODPER */ #define RCC_SSCGR_MODPER_SHIFT 15 /* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ /* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 /* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ #define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 /* --- Variable definitions ------------------------------------------------ */ extern uint32_t rcc_ppre1_frequency; extern uint32_t rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ typedef enum { CLOCK_3V3_48MHZ, CLOCK_3V3_120MHZ, CLOCK_3V3_168MHZ, CLOCK_3V3_END } clock_3v3_t; typedef struct { uint8_t pllm; uint16_t plln; uint8_t pllp; uint8_t pllq; uint32_t flash_config; uint8_t hpre; uint8_t ppre1; uint8_t ppre2; uint8_t power_save; uint32_t apb1_frequency; uint32_t apb2_frequency; } clock_scale_t; extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END]; extern const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END]; extern const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END]; typedef enum { PLL, HSE, HSI, LSE, LSI } osc_t; BEGIN_DECLS void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); int rcc_osc_ready_int_flag(osc_t osc); void rcc_css_int_clear(void); int rcc_css_int_flag(void); void rcc_wait_for_osc_ready(osc_t osc); void rcc_wait_for_sysclk_status(osc_t osc); void rcc_osc_on(osc_t osc); void rcc_osc_off(osc_t osc); void rcc_css_enable(void); void rcc_css_disable(void); void rcc_osc_bypass_enable(osc_t osc); void rcc_osc_bypass_disable(osc_t osc); void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); void rcc_set_sysclk_source(uint32_t clk); void rcc_set_pll_source(uint32_t pllsrc); void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); void rcc_set_rtcpre(uint32_t rtcpre); void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq); void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq); uint32_t rcc_system_clock_source(void); void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); void rcc_backupdomain_reset(void); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/rng.h000066400000000000000000000015551435536612600233750ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RNG_H #define LIBOPENCM3_RNG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/rtc.h000066400000000000000000000024041435536612600233710ustar00rootroot00000000000000/** @defgroup rtc_defines RTC Defines @brief Defined Constants and Types for the STM32F4xx RTC @ingroup STM32F4xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RTC_H #define LIBOPENCM3_RTC_H #include #include BEGIN_DECLS void rtc_enable_wakeup_timer(void); void rtc_disable_wakeup_timer(void); void rtc_enable_wakeup_timer_interrupt(void); void rtc_disable_wakeup_timer_interrupt(void); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/spi.h000066400000000000000000000021031435536612600233700ustar00rootroot00000000000000/** @defgroup spi_defines SPI Defines @brief Defined Constants and Types for the STM32F4xx SPI @ingroup STM32F4xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SPI_H #define LIBOPENCM3_SPI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/syscfg.h000066400000000000000000000016661435536612600241100ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SYSCFG_H #define LIBOPENCM3_SYSCFG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/timer.h000066400000000000000000000022751435536612600237270ustar00rootroot00000000000000/** @defgroup timer_defines Timer Defines @brief libopencm3 Defined Constants and Types for the STM32F4xx Timers @ingroup STM32F4xx_defines @version 1.0.0 @date 8 March 2013 @author @htmlonly © @endhtmlonly 2011 Fergus Noble LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_TIMER_H #define LIBOPENCM3_TIMER_H #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/f4/usart.h000066400000000000000000000021171435536612600237400ustar00rootroot00000000000000/** @defgroup usart_defines USART Defines @brief Defined Constants and Types for the STM32F4xx USART @ingroup STM32F4xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/flash.h000066400000000000000000000023521435536612600233670ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/fsmc.h000066400000000000000000000215451435536612600232270ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_FSMC_H #define LIBOPENCM3_FSMC_H #include #include /* --- Convenience macros -------------------------------------------------- */ #define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */ #define FSMC_BANK2_BASE 0x70000000 /* NAND flash */ #define FSMC_BANK3_BASE 0x80000000 /* NAND flash */ #define FSMC_BANK4_BASE 0x90000000 /* PC card */ /* --- FSMC registers ------------------------------------------------------ */ /* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ #define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) #define FSMC_BCR1 FSMC_BCR(0) #define FSMC_BCR2 FSMC_BCR(1) #define FSMC_BCR3 FSMC_BCR(2) #define FSMC_BCR4 FSMC_BCR(3) /* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ #define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) #define FSMC_BTR1 FSMC_BTR(0) #define FSMC_BTR2 FSMC_BTR(1) #define FSMC_BTR3 FSMC_BTR(2) #define FSMC_BTR4 FSMC_BTR(3) /* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ #define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) #define FSMC_BWTR1 FSMC_BWTR(0) #define FSMC_BWTR2 FSMC_BWTR(1) #define FSMC_BWTR3 FSMC_BWTR(2) #define FSMC_BWTR4 FSMC_BWTR(3) /* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ #define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) #define FSMC_PCR2 FSMC_PCR(1) #define FSMC_PCR3 FSMC_PCR(2) #define FSMC_PCR4 FSMC_PCR(3) /* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ #define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) #define FSMC_SR2 FSMC_SR(1) #define FSMC_SR3 FSMC_SR(2) #define FSMC_SR4 FSMC_SR(3) /* Common memory space timing registers 2..4 (FSMC_PMEMx) */ #define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) #define FSMC_PMEM2 FSMC_PMEM(1) #define FSMC_PMEM3 FSMC_PMEM(2) #define FSMC_PMEM4 FSMC_PMEM(3) /* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ #define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) #define FSMC_PATT2 FSMC_PATT(1) #define FSMC_PATT3 FSMC_PATT(2) #define FSMC_PATT4 FSMC_PATT(3) /* I/O space timing register 4 (FSMC_PIO4) */ #define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) /* ECC result registers 2/3 (FSMC_ECCRx) */ #define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) #define FSMC_ECCR2 FSMC_ECCR(1) #define FSMC_ECCR3 FSMC_ECCR(2) /* --- FSMC_BCRx values ---------------------------------------------------- */ /* Bits [31:20]: Reserved. */ /* CBURSTRW: Write burst enable */ #define FSMC_BCR_CBURSTRW (1 << 19) /* Bits [18:16]: Reserved. */ /* ASYNCWAIT: Wait signal during asynchronous transfers */ #define FSMC_BCR_ASYNCWAIT (1 << 15) /* EXTMOD: Extended mode enable */ #define FSMC_BCR_EXTMOD (1 << 14) /* WAITEN: Wait enable bit */ #define FSMC_BCR_WAITEN (1 << 13) /* WREN: Write enable bit */ #define FSMC_BCR_WREN (1 << 12) /* WAITCFG: Wait timing configuration */ #define FSMC_BCR_WAITCFG (1 << 11) /* WRAPMOD: Wrapped burst mode support */ #define FSMC_BCR_WRAPMOD (1 << 10) /* WAITPOL: Wait signal polarity bit */ #define FSMC_BCR_WAITPOL (1 << 9) /* BURSTEN: Burst enable bit */ #define FSMC_BCR_BURSTEN (1 << 8) /* Bit 7: Reserved. */ /* FACCEN: Flash access enable */ #define FSMC_BCR_FACCEN (1 << 6) /* MWID[5:4]: Memory data bus width */ #define FSMC_BCR_MWID (1 << 4) /* MTYP[3:2]: Memory type */ #define FSMC_BCR_MTYP (1 << 2) /* MUXEN: Address/data multiplexing enable bit */ #define FSMC_BCR_MUXEN (1 << 1) /* MBKEN: Memory bank enable bit */ #define FSMC_BCR_MBKEN (1 << 0) /* --- FSMC_BTRx values ---------------------------------------------------- */ /* Bits [31:30]: Reserved. */ /* Same for read and write */ #define FSMC_BTx_ACCMOD_A (0) #define FSMC_BTx_ACCMOD_B (1) #define FSMC_BTx_ACCMOD_C (2) #define FSMC_BTx_ACCMOD_D (3) /* ACCMOD[29:28]: Access mode */ #define FSMC_BTR_ACCMOD (1 << 28) #define FSMC_BTR_ACCMODx(x) (((x) & 0x03) << 28) /* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ #define FSMC_BTR_DATLAT (1 << 24) #define FSMC_BTR_DATLATx(x) (((x) & 0x0f) << 24) /* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ #define FSMC_BTR_CLKDIV (1 << 20) #define FSMC_BTR_CLKDIVx(x) (((x) & 0x0f) << 20) /* BUSTURN[19:16]: Bus turnaround phase duration */ #define FSMC_BTR_BUSTURN (1 << 16) #define FSMC_BTR_BUSTURNx(x) (((x) & 0x0f) << 16) /* DATAST[15:8]: Data-phase duration */ #define FSMC_BTR_DATAST (1 << 8) #define FSMC_BTR_DATASTx(x) (((x) & 0xff) << 8) /* ADDHLD[7:4]: Address-hold phase duration */ #define FSMC_BTR_ADDHLD (1 << 4) #define FSMC_BTR_ADDHLDx(x) (((x) & 0x0f) << 4) /* ADDSET[3:0]: Address setup phase duration */ #define FSMC_BTR_ADDSET (1 << 0) #define FSMC_BTR_ADDSETx(x) (((x) & 0x0f) << 0) /* --- FSMC_BWTRx values --------------------------------------------------- */ /* Bits [31:30]: Reserved. */ /* ACCMOD[29:28]: Access mode */ #define FSMC_BWTR_ACCMOD (1 << 28) /* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ #define FSMC_BWTR_DATLAT (1 << 24) /* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ #define FSMC_BWTR_CLKDIV (1 << 20) /* Bits [19..16]: Reserved. */ /* DATAST[15:8]: Data-phase duration */ #define FSMC_BWTR_DATAST (1 << 8) /* ADDHLD[7:4]: Address-hold phase duration */ #define FSMC_BWTR_ADDHLD (1 << 4) /* ADDSET[3:0]: Address setup phase duration */ #define FSMC_BWTR_ADDSET (1 << 0) /* --- FSMC_PCRx values ---------------------------------------------------- */ /* Bits [31:20]: Reserved. */ /* ECCPS[19:17]: ECC page size */ #define FSMC_PCR_ECCPS (1 << 17) /* TAR[16:13]: ALE to RE delay */ #define FSMC_PCR_TAR (1 << 13) /* TCLR[12:9]: CLE to RE delay */ #define FSMC_PCR_TCLR (1 << 9) /* Bits [8..7]: Reserved. */ /* ECCEN: ECC computation logic enable bit */ #define FSMC_PCR_ECCEN (1 << 6) /* PWID[5:4]: Databus width */ #define FSMC_PCR_PWID (1 << 4) /* PTYP: Memory type */ #define FSMC_PCR_PTYP (1 << 3) /* PBKEN: PC Card/NAND Flash memory bank enable bit */ #define FSMC_PCR_PBKEN (1 << 2) /* PWAITEN: Wait feature enable bit */ #define FSMC_PCR_PWAITEN (1 << 1) /* Bit 0: Reserved. */ /* --- FSMC_SRx values ----------------------------------------------------- */ /* Bits [31:7]: Reserved. */ /* FEMPT: FIFO empty */ #define FSMC_SR_FEMPT (1 << 6) /* IFEN: Interrupt falling edge detection enable bit */ #define FSMC_SR_IFEN (1 << 5) /* ILEN: Interrupt high-level detection enable bit */ #define FSMC_SR_ILEN (1 << 4) /* IREN: Interrupt rising edge detection enable bit */ #define FSMC_SR_IREN (1 << 3) /* IFS: Interrupt falling edge status */ #define FSMC_SR_IFS (1 << 2) /* ILS: Interrupt high-level status */ #define FSMC_SR_ILS (1 << 1) /* IRS: Interrupt rising edge status */ #define FSMC_SR_IRS (1 << 0) /* --- FSMC_PMEMx values --------------------------------------------------- */ /* MEMHIZx[31:24]: Common memory x databus HiZ time */ #define FSMC_PMEM_MEMHIZX (1 << 24) /* MEMHOLDx[23:16]: Common memory x hold time */ #define FSMC_PMEM_MEMHOLDX (1 << 16) /* MEMWAITx[15:8]: Common memory x wait time */ #define FSMC_PMEM_MEMWAITX (1 << 8) /* MEMSETx[7:0]: Common memory x setup time */ #define FSMC_PMEM_MEMSETX (1 << 0) /* --- FSMC_PATTx values --------------------------------------------------- */ /* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ #define FSMC_PATT_ATTHIZX (1 << 24) /* ATTHOLDx[23:16]: Attribute memory x hold time */ #define FSMC_PATT_ATTHOLDX (1 << 16) /* ATTWAITx[15:8]: Attribute memory x wait time */ #define FSMC_PATT_ATTWAITX (1 << 8) /* ATTSETx[7:0]: Attribute memory x setup time */ #define FSMC_PATT_ATTSETX (1 << 0) /* --- FSMC_PIO4 values ---------------------------------------------------- */ /* IOHIZx[31:24]: I/O x databus HiZ time */ #define FSMC_PIO4_IOHIZX (1 << 24) /* IOHOLDx[23:16]: I/O x hold time */ #define FSMC_PIO4_IOHOLDX (1 << 16) /* IOWAITx[15:8]: I/O x wait time */ #define FSMC_PIO4_IOWAITX (1 << 8) /* IOSETx[7:0]: I/O x setup time */ #define FSMC_PIO4_IOSETX (1 << 0) /* --- FSMC_ECCRx values --------------------------------------------------- */ /* ECCx[31:0]: ECC result */ #define FSMC_ECCR_ECCX (1 << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/gpio.h000066400000000000000000000023451435536612600232320ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/hash.h000066400000000000000000000020151435536612600232110ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F2) # include #elif defined(STM32F4) # include #else # error "hash processor is supported only" \ "in stm32f21, stm32f41 and stm32f43 families." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/i2c.h000066400000000000000000000023371435536612600227520ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/iwdg.h000066400000000000000000000023441435536612600232250ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/000077500000000000000000000000001435536612600224335ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/crc.h000066400000000000000000000022171435536612600233550ustar00rootroot00000000000000/** @defgroup crc_defines CRC Defines @brief libopencm3 Defined Constants and Types for the STM32L1xx CRC Generator @ingroup STM32L1xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_CRC_H #define LIBOPENCM3_CRC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/dac.h000066400000000000000000000021031435536612600233270ustar00rootroot00000000000000/** @defgroup dac_defines DAC Defines @brief Defined Constants and Types for the STM32L1xx DAC @ingroup STM32L1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DAC_H #define LIBOPENCM3_DAC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/dma.h000066400000000000000000000023731435536612600233520ustar00rootroot00000000000000/** @defgroup STM32L1xx_dma_defines DMA Defines @ingroup STM32L1xx_defines @brief Defined Constants and Types for the STM32L1xx DMA Controller @version 1.0.0 @author @htmlonly © @endhtmlonly 2011 Fergus Noble @author @htmlonly © @endhtmlonly 2012 Ken Sarkies @date 18 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_DMA_H #define LIBOPENCM3_DMA_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/doc-stm32l1.h000066400000000000000000000010411435536612600245500ustar00rootroot00000000000000/** @mainpage libopencm3 STM32L1 @version 1.0.0 @date 12 November 2012 API documentation for ST Microelectronics STM32L1 Cortex M3 series. LGPL License Terms @ref lgpl_license */ /** @defgroup STM32L1xx STM32L1xx Libraries for ST Microelectronics STM32L1xx series. @version 1.0.0 @date 12 November 2012 LGPL License Terms @ref lgpl_license */ /** @defgroup STM32L1xx_defines STM32L1xx Defines @brief Defined Constants and Types for the STM32L1xx series @version 1.0.0 @date 12 November 2012 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/exti.h000066400000000000000000000016611435536612600235610ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_EXTI_H #define LIBOPENCM3_EXTI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/flash.h000066400000000000000000000110131435536612600236750ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming * manual. */ #ifndef LIBOPENCM3_FLASH_H #define LIBOPENCM3_FLASH_H #include #include /* --- FLASH registers ----------------------------------------------------- */ #define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) #define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) #define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) #define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) #define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) #define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) #define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) #define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c) #define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) #define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) #define FLASH_WRPR3 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x84) /* --- FLASH_ACR values ---------------------------------------------------- */ #define FLASH_ACR_RUNPD (1 << 4) #define FLASH_ACR_SLEEPPD (1 << 3) #define FLASH_ACR_ACC64 (1 << 2) #define FLASH_ACR_PRFTEN (1 << 1) #define FLASH_ACR_LATENCY_0WS 0x00 #define FLASH_ACR_LATENCY_1WS 0x01 /* --- FLASH_PECR values. Program/erase control register */ #define FLASH_PECR_OBL_LAUNCH (1 << 18) #define FLASH_PECR_ERRIE (1 << 17) #define FLASH_PECR_EOPIE (1 << 16) #define FLASH_PECR_PARALLBANK (1 << 15) #define FLASH_PECR_FPRG (1 << 10) #define FLASH_PECR_ERASE (1 << 9) #define FLASH_PECR_FTDW (1 << 8) #define FLASH_PECR_FTDW (1 << 8) #define FLASH_PECR_DATA (1 << 4) #define FLASH_PECR_PROG (1 << 3) #define FLASH_PECR_OPTLOCK (1 << 2) #define FLASH_PECR_PRGLOCK (1 << 1) #define FLASH_PECR_PELOCK (1 << 0) /* Power down key register (FLASH_PDKEYR) */ #define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) #define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD) /* Program/erase key register (FLASH_PEKEYR) */ #define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF) #define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405) /* Program memory key register (FLASH_PRGKEYR) */ #define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF) #define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516) /* Option byte key register (FLASH_OPTKEYR) */ #define FLASH_OPTKEYR_OPTKEY1 ((uint32_t)0xFBEAD9C8) #define FLASH_OPTKEYR_OPTKEY2 ((uint32_t)0x24252627) /* --- FLASH_SR values ----------------------------------------------------- */ #define FLASH_SR_OPTVERRUSR (1 << 12) #define FLASH_SR_OPTVERR (1 << 11) #define FLASH_SR_SIZEERR (1 << 10) #define FLASH_SR_PGAERR (1 << 9) #define FLASH_SR_WRPERR (1 << 8) #define FLASH_SR_READY (1 << 3) #define FLASH_SR_ENDHV (1 << 2) #define FLASH_SR_EOP (1 << 1) #define FLASH_SR_BSY (1 << 0) /* --- FLASH_OBR values ----------------------------------------------------- */ #define FLASH_OBR_BFB2 (1 << 23) #define FLASH_OBR_NRST_STDBY (1 << 22) #define FLASH_OBR_NRST_STOP (1 << 21) #define FLASH_OBR_IWDG_SW (1 << 20) #define FLASH_OBR_BOR_OFF (0x0 << 16) #define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16) #define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16) #define FLASH_OBR_BOR_LEVEL_3 (0xa << 16) #define FLASH_OBR_BOR_LEVEL_4 (0xb << 16) #define FLASH_OBR_BOR_LEVEL_5 (0xc << 16) #define FLASH_OBR_RDPRT_LEVEL_0 (0xaa) #define FLASH_OBR_RDPRT_LEVEL_1 (0x00) #define FLASH_OBR_RDPRT_LEVEL_2 (0xcc) /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void flash_64bit_enable(void); void flash_64bit_disable(void); void flash_prefetch_enable(void); void flash_prefetch_disable(void); void flash_set_ws(uint32_t ws); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/gpio.h000066400000000000000000000222301435536612600235410ustar00rootroot00000000000000/** @defgroup gpio_defines GPIO Defines @brief Defined Constants and Types for the STM32L1xx General Purpose I/O @ingroup STM32L1xx_defines @version 1.0.0 @date 1 July 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Piotr Esden-Tempski * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LIBOPENCM3_GPIO_H #define LIBOPENCM3_GPIO_H #include #include /* --- Convenience macros -------------------------------------------------- */ /* GPIO port base addresses (for convenience) */ /* GPIO port base addresses (for convenience) */ /** @defgroup gpio_port_id GPIO Port IDs @ingroup gpio_defines @{*/ #define GPIOA GPIO_PORT_A_BASE #define GPIOB GPIO_PORT_B_BASE #define GPIOC GPIO_PORT_C_BASE #define GPIOD GPIO_PORT_D_BASE #define GPIOE GPIO_PORT_E_BASE #define GPIOH GPIO_PORT_H_BASE /**@}*/ /* --- GPIO registers ------------------------------------------------------ */ /* Port mode register (GPIOx_MODER) */ #define GPIO_MODER(port) MMIO32(port + 0x00) #define GPIOA_MODER GPIO_MODER(GPIOA) #define GPIOB_MODER GPIO_MODER(GPIOB) #define GPIOC_MODER GPIO_MODER(GPIOC) #define GPIOD_MODER GPIO_MODER(GPIOD) #define GPIOE_MODER GPIO_MODER(GPIOE) #define GPIOH_MODER GPIO_MODER(GPIOH) /* Port output type register (GPIOx_OTYPER) */ #define GPIO_OTYPER(port) MMIO32(port + 0x04) #define GPIOA_OTYPER GPIO_OTYPER(GPIOA) #define GPIOB_OTYPER GPIO_OTYPER(GPIOB) #define GPIOC_OTYPER GPIO_OTYPER(GPIOC) #define GPIOD_OTYPER GPIO_OTYPER(GPIOD) #define GPIOE_OTYPER GPIO_OTYPER(GPIOE) #define GPIOH_OTYPER GPIO_OTYPER(GPIOH) /* Port output speed register (GPIOx_OSPEEDR) */ #define GPIO_OSPEEDR(port) MMIO32(port + 0x08) #define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) #define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) #define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) #define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) #define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) #define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) /* Port pull-up/pull-down register (GPIOx_PUPDR) */ #define GPIO_PUPDR(port) MMIO32(port + 0x0c) #define GPIOA_PUPDR GPIO_PUPDR(GPIOA) #define GPIOB_PUPDR GPIO_PUPDR(GPIOB) #define GPIOC_PUPDR GPIO_PUPDR(GPIOC) #define GPIOD_PUPDR GPIO_PUPDR(GPIOD) #define GPIOE_PUPDR GPIO_PUPDR(GPIOE) #define GPIOH_PUPDR GPIO_PUPDR(GPIOH) /* Port input data register (GPIOx_IDR) */ #define GPIO_IDR(port) MMIO32(port + 0x10) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) #define GPIOD_IDR GPIO_IDR(GPIOD) #define GPIOE_IDR GPIO_IDR(GPIOE) #define GPIOH_IDR GPIO_IDR(GPIOH) /* Port output data register (GPIOx_ODR) */ #define GPIO_ODR(port) MMIO32(port + 0x14) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) #define GPIOD_ODR GPIO_ODR(GPIOD) #define GPIOE_ODR GPIO_ODR(GPIOE) #define GPIOH_ODR GPIO_ODR(GPIOH) /* Port bit set/reset register (GPIOx_BSRR) */ #define GPIO_BSRR(port) MMIO32(port + 0x18) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) #define GPIOD_BSRR GPIO_BSRR(GPIOD) #define GPIOE_BSRR GPIO_BSRR(GPIOE) #define GPIOH_BSRR GPIO_BSRR(GPIOH) /* Port configuration lock register (GPIOx_LCKR) */ #define GPIO_LCKR(port) MMIO32(port + 0x1C) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) #define GPIOD_LCKR GPIO_LCKR(GPIOD) #define GPIOE_LCKR GPIO_LCKR(GPIOE) #define GPIOH_LCKR GPIO_LCKR(GPIOH) /* Alternate function low register (GPIOx_AFRL) */ #define GPIO_AFRL(port) MMIO32(port + 0x20) #define GPIOA_AFRL GPIO_AFRL(GPIOA) #define GPIOB_AFRL GPIO_AFRL(GPIOB) #define GPIOC_AFRL GPIO_AFRL(GPIOC) #define GPIOD_AFRL GPIO_AFRL(GPIOD) #define GPIOE_AFRL GPIO_AFRL(GPIOE) #define GPIOH_AFRL GPIO_AFRL(GPIOH) /* Alternate function high register (GPIOx_AFRH) */ #define GPIO_AFRH(port) MMIO32(port + 0x24) #define GPIOA_AFRH GPIO_AFRH(GPIOA) #define GPIOB_AFRH GPIO_AFRH(GPIOB) #define GPIOC_AFRH GPIO_AFRH(GPIOC) #define GPIOD_AFRH GPIO_AFRH(GPIOD) #define GPIOE_AFRH GPIO_AFRH(GPIOE) #define GPIOH_AFRH GPIO_AFRH(GPIOH) /* --- GPIOx_MODER values-------------------------------------------- */ #define GPIO_MODE(n, mode) (mode << (2 * (n))) #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode @ingroup gpio_defines @{*/ #define GPIO_MODE_INPUT 0x00 /* Default */ #define GPIO_MODE_OUTPUT 0x01 #define GPIO_MODE_AF 0x02 #define GPIO_MODE_ANALOG 0x03 /**@}*/ /* --- GPIOx_OTYPER values -------------------------------------------- */ /* Output type (OTx values) */ /** @defgroup gpio_output_type GPIO Output Pin Driver Type @ingroup gpio_defines @list Push Pull @list Open Drain @{*/ #define GPIO_OTYPE_PP 0x0 #define GPIO_OTYPE_OD 0x1 /**@}*/ /* Output speed values */ #define GPIO_OSPEED(n, speed) (speed << (2 * (n))) #define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_speed GPIO Output Pin Speed @ingroup gpio_defines @{*/ #define GPIO_OSPEED_400KHZ 0x0 #define GPIO_OSPEED_2MHZ 0x1 #define GPIO_OSPEED_10MHZ 0x2 #define GPIO_OSPEED_40MHZ 0x3 /**@}*/ /* --- GPIOx_PUPDR values ------------------------------------------- */ #define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) #define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_pup GPIO Output Pin Pullup @ingroup gpio_defines @{*/ #define GPIO_PUPD_NONE 0x0 #define GPIO_PUPD_PULLUP 0x1 #define GPIO_PUPD_PULLDOWN 0x2 /**@}*/ /* --- GPIO_IDR values ----------------------------------------------------- */ /* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ /* --- GPIO_ODR values ----------------------------------------------------- */ /* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ /* --- GPIO_BSRR values ---------------------------------------------------- */ /* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ /* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ /* --- GPIO_LCKR values ---------------------------------------------------- */ #define GPIO_LCKK (1 << 16) /* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ /* --- GPIOx_AFRL/H values ------------------------------------------------- */ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See datasheet table 5, page 35 for the definitions */ #define GPIO_AFR(n, af) (af << ((n) * 4)) #define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) /** @defgroup gpio_af_num Alternate Function Pin Selection @ingroup gpio_defines @{*/ #define GPIO_AF0 0x0 #define GPIO_AF1 0x1 #define GPIO_AF2 0x2 #define GPIO_AF3 0x3 #define GPIO_AF4 0x4 #define GPIO_AF5 0x5 #define GPIO_AF6 0x6 #define GPIO_AF7 0x7 #define GPIO_AF8 0x8 #define GPIO_AF9 0x9 #define GPIO_AF10 0xa #define GPIO_AF11 0xb #define GPIO_AF12 0xc #define GPIO_AF13 0xd #define GPIO_AF14 0xe #define GPIO_AF15 0xf /**@}*/ /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS /* * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style * however the number of ports is reduced and H port naming is different. * TODO: this should all really be moved to a "common" gpio header */ void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios); void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios); void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/i2c.h000066400000000000000000000021041435536612600232560ustar00rootroot00000000000000/** @defgroup i2c_defines I2C Defines @brief Defined Constants and Types for the STM32L1xx I2C @ingroup STM32L1xx_defines @version 1.0.0 @date 12 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_I2C_H #define LIBOPENCM3_I2C_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/irq.yaml000066400000000000000000000014541435536612600241160ustar00rootroot00000000000000includeguard: LIBOPENCM3_STM32_L1_NVIC_H partname_humanreadable: STM32 L1 series partname_doxygen: STM32L1 irqs: - wwdg - pvd - tamper_stamp - rtc_wkup - flash - rcc - exti0 - exti1 - exti2 - exti3 - exti4 - dma1_channel1 - dma1_channel2 - dma1_channel3 - dma1_channel4 - dma1_channel5 - dma1_channel6 - dma1_channel7 - adc1 - usb_hp - usb_lp - dac - comp - exti9_5 - lcd - tim9 - tim10 - tim11 - tim2 - tim3 - tim4 - i2c1_ev - i2c1_er - i2c2_ev - i2c2_er - spi1 - spi2 - usart1 - usart2 - usart3 - exti15_10 - rtc_alarm - usb_fs_wakeup - tim6 - tim7 # below here is medium+/high density - sdio - tim5 - spi3 - uart4 - uart5 - dma2_ch1 - dma2_ch2 - dma2_ch3 - dma2_ch4 - dma2_ch5 - aes - comp_acqhackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/iwdg.h000066400000000000000000000022261435536612600235400ustar00rootroot00000000000000/** @defgroup iwdg_defines IWDG Defines @brief Defined Constants and Types for the STM32L1xx Independent Watchdog Timer @ingroup STM32L1xx_defines @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_IWDG_H #define LIBOPENCM3_IWDG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/memorymap.h000066400000000000000000000105651435536612600246210ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_MEMORYMAP_H #define LIBOPENCM3_MEMORYMAP_H #include /* --- STM32 specific peripheral definitions ------------------------------- */ /* Memory map for all busses */ #define PERIPH_BASE ((uint32_t)0x40000000) #define INFO_BASE ((uint32_t)0x1ff00000) #define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) #define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) #define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) /* Register boundary addresses */ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) #define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00) #define USART5_BASE (PERIPH_BASE_APB1 + 0x5000) #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) #define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) /* gap */ #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) #define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c) #define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00) #define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04) /* APB2 */ #define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) #define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) #define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800) #define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00) #define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000) /* gap */ #define ADC_BASE (PERIPH_BASE_APB2 + 0x2400) /* gap */ #define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00) #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) /* gap */ #define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) /* AHB */ #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000) #define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400) #define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800) #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00) #define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000) #define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400) #define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800) #define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00) /* gap */ #define CRC_BASE (PERIPH_BASE_AHB + 0x03000) /* gap */ #define RCC_BASE (PERIPH_BASE_AHB + 0x03800) #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00) /* gap */ #define DMA1_BASE (PERIPH_BASE_AHB + 0x06000) #define DMA2_BASE (PERIPH_BASE_AHB + 0x04000) /* PPIB */ #define DBGMCU_BASE (PPBI_BASE + 0x00042000) /* FSMC */ #define FSMC_BASE (PERIPH_BASE + 0x60000000) /* AES */ #define AES_BASE (PERIPH_BASE + 0x10000000) /* Device Electronic Signature */ #define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C) #define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050) /* Make the map names match those for other families to allow commonality */ #define SPI1_I2S_BASE SPI1_BASE #define SPI2_I2S_BASE SPI2_BASE #define SPI3_I2S_BASE SPI3_BASE #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/pwr.h000066400000000000000000000060251435536612600234170ustar00rootroot00000000000000/** @defgroup pwr_defines PWR Defines @brief Defined Constants and Types for the STM32L1xx Power Control @ingroup STM32L1xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2011 Stephen Caudle @author @htmlonly © @endhtmlonly 2012 Karl Palsson @date 1 July 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Stephen Caudle * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_PWR_H #define LIBOPENCM3_PWR_H #include #include /* * This file extends the common STM32 version with definitions only * applicable to the STM32L1 series of devices. */ /* --- PWR_CR values ------------------------------------------------------- */ /* Bits [31:15]: Reserved */ /* LPRUN: Low power run mode */ #define PWR_CR_LPRUN (1 << 14) /* VOS[12:11]: Regulator voltage scaling output selection */ #define PWR_CR_VOS_LSB 11 /** @defgroup pwr_vos Voltage Scaling Output level selection @ingroup pwr_defines @{*/ #define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) #define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) #define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) /**@}*/ #define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) /* FWU: Fast wakeup */ #define PWR_CR_FWU (1 << 10) /* ULP: Ultralow power mode */ #define PWR_CR_ULP (1 << 9) /* LPSDSR: Low-power deepsleep/sleep/low power run */ #define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */ /* --- PWR_CSR values ------------------------------------------------------- */ /* Bits [31:11]: Reserved */ /* EWUP3: Enable WKUP3 pin */ #define PWR_CSR_EWUP3 (1 << 10) /* EWUP2: Enable WKUP2 pin */ #define PWR_CSR_EWUP2 (1 << 9) /* EWUP1: Enable WKUP1 pin */ #define PWR_CSR_EWUP1 PWR_CSR_EWUP /* REGLPF : Regulator LP flag */ #define PWR_CSR_REGLPF (1 << 5) /* VOSF: Voltage Scaling select flag */ #define PWR_CSR_VOSF (1 << 4) /* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ #define PWR_CSR_VREFINTRDYF (1 << 3) /* --- Function prototypes ------------------------------------------------- */ typedef enum { RANGE1, RANGE2, RANGE3, } vos_scale_t; BEGIN_DECLS void pwr_set_vos_scale(vos_scale_t scale); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/rcc.h000066400000000000000000000361271435536612600233640ustar00rootroot00000000000000/** @defgroup STM32L1xx_rcc_defines RCC Defines @ingroup STM32L1xx_defines @brief libopencm3 STM32L1xx Reset and Clock Control @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2012 Karl Palsson @date 11 November 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * * Originally based on the F1 code, as it seemed most similar to the L1 * TODO: very incomplete still! */ /**@{*/ #ifndef LIBOPENCM3_RCC_H #define LIBOPENCM3_RCC_H #include #include #include /* --- RCC registers ------------------------------------------------------- */ #define RCC_CR MMIO32(RCC_BASE + 0x00) #define RCC_ICSCR MMIO32(RCC_BASE + 0x04) #define RCC_CFGR MMIO32(RCC_BASE + 0x08) #define RCC_CIR MMIO32(RCC_BASE + 0x0c) #define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10) #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14) #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18) #define RCC_AHBENR MMIO32(RCC_BASE + 0x1c) #define RCC_APB2ENR MMIO32(RCC_BASE + 0x20) #define RCC_APB1ENR MMIO32(RCC_BASE + 0x24) #define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28) #define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c) #define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30) #define RCC_CSR MMIO32(RCC_BASE + 0x34) /* --- RCC_CR values ------------------------------------------------------- */ /* RTCPRE[1:0] at 30:29 */ #define RCC_CR_CSSON (1 << 28) #define RCC_CR_PLLRDY (1 << 25) #define RCC_CR_PLLON (1 << 24) #define RCC_CR_HSEBYP (1 << 18) #define RCC_CR_HSERDY (1 << 17) #define RCC_CR_HSEON (1 << 16) #define RCC_CR_MSIRDY (1 << 9) #define RCC_CR_MSION (1 << 8) #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) #define RCC_CR_RTCPRE_DIV2 0 #define RCC_CR_RTCPRE_DIV4 1 #define RCC_CR_RTCPRE_DIV8 2 #define RCC_CR_RTCPRE_DIV16 3 #define RCC_CR_RTCPRE_SHIFT 29 #define RCC_CR_RTCPRE_MASK 0x3 /* --- RCC_ICSCR values ---------------------------------------------------- */ #define RCC_ICSCR_MSITRIM_SHIFT 24 #define RCC_ICSCR_MSITRIM_MASK 0xff #define RCC_ICSCR_MSICAL_SHIFT 16 #define RCC_ICSCR_MSICAL_MASK 0xff #define RCC_ICSCR_MSIRANGE_SHIFT 13 #define RCC_ICSCR_MSIRANGE_MASK 0x7 #define RCC_ICSCR_MSIRANGE_65KHZ 0x0 #define RCC_ICSCR_MSIRANGE_131KHZ 0x1 #define RCC_ICSCR_MSIRANGE_262KHZ 0x2 #define RCC_ICSCR_MSIRANGE_524KHZ 0x3 #define RCC_ICSCR_MSIRANGE_1MHZ 0x4 #define RCC_ICSCR_MSIRANGE_2MHZ 0x5 #define RCC_ICSCR_MSIRANGE_4MHZ 0x6 #define RCC_ICSCR_HSITRIM_SHIFT 8 #define RCC_ICSCR_HSITRIM_MASK 0x1f #define RCC_ICSCR_HSICAL_SHIFT 0 #define RCC_ICSCR_HSICAL_MASK 0xff /* --- RCC_CFGR values ----------------------------------------------------- */ /* MCOPRE */ #define RCC_CFGR_MCOPRE_DIV1 0 #define RCC_CFGR_MCOPRE_DIV2 1 #define RCC_CFGR_MCOPRE_DIV4 2 #define RCC_CFGR_MCOPRE_DIV8 3 #define RCC_CFGR_MCOPRE_DIV16 4 /* MCO: Microcontroller clock output */ #define RCC_CFGR_MCO_NOCLK 0x0 #define RCC_CFGR_MCO_SYSCLK 0x1 #define RCC_CFGR_MCO_HSICLK 0x2 #define RCC_CFGR_MCO_MSICLK 0x3 #define RCC_CFGR_MCO_HSECLK 0x4 #define RCC_CFGR_MCO_PLLCLK 0x5 #define RCC_CFGR_MCO_LSICLK 0x6 #define RCC_CFGR_MCO_LSECLK 0x7 /* PLL Output division selection */ #define RCC_CFGR_PLLDIV_DIV2 0x1 #define RCC_CFGR_PLLDIV_DIV3 0x2 #define RCC_CFGR_PLLDIV_DIV4 0x3 #define RCC_CFGR_PLLDIV_SHIFT 22 #define RCC_CFGR_PLLDIV_MASK 0x3 /* PLLMUL: PLL multiplication factor */ #define RCC_CFGR_PLLMUL_MUL3 0x0 #define RCC_CFGR_PLLMUL_MUL4 0x1 #define RCC_CFGR_PLLMUL_MUL6 0x2 #define RCC_CFGR_PLLMUL_MUL8 0x3 #define RCC_CFGR_PLLMUL_MUL12 0x4 #define RCC_CFGR_PLLMUL_MUL16 0x5 #define RCC_CFGR_PLLMUL_MUL24 0x6 #define RCC_CFGR_PLLMUL_MUL32 0x7 #define RCC_CFGR_PLLMUL_MUL48 0x8 #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL_MASK 0xf /* PLLSRC: PLL entry clock source */ #define RCC_CFGR_PLLSRC_HSI_CLK 0x0 #define RCC_CFGR_PLLSRC_HSE_CLK 0x1 /* PPRE2: APB high-speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 #define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 #define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 #define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 #define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 /* PPRE1: APB low-speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 #define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 #define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 #define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 #define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 /* HPRE: AHB prescaler */ #define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 #define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 #define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 #define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa #define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb #define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc #define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd #define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe #define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf /* SWS: System clock switch status */ #define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0 #define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1 #define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2 #define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3 /* SW: System clock switch */ #define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0 #define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1 #define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2 #define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3 /* --- RCC_CIR values ------------------------------------------------------ */ /* Clock security system interrupt clear bit */ #define RCC_CIR_CSSC (1 << 23) /* OSC ready interrupt clear bits */ #define RCC_CIR_MSIRDYC (1 << 21) #define RCC_CIR_PLLRDYC (1 << 20) #define RCC_CIR_HSERDYC (1 << 19) #define RCC_CIR_HSIRDYC (1 << 18) #define RCC_CIR_LSERDYC (1 << 17) #define RCC_CIR_LSIRDYC (1 << 16) /* OSC ready interrupt enable bits */ #define RCC_CIR_MSIRDYIE (1 << 13) #define RCC_CIR_PLLRDYIE (1 << 12) #define RCC_CIR_HSERDYIE (1 << 11) #define RCC_CIR_HSIRDYIE (1 << 10) #define RCC_CIR_LSERDYIE (1 << 9) #define RCC_CIR_LSIRDYIE (1 << 8) /* Clock security system interrupt flag bit */ #define RCC_CIR_CSSF (1 << 7) /* OSC ready interrupt flag bits */ #define RCC_CIR_MSIRDYF (1 << 5) /* (**) */ #define RCC_CIR_PLLRDYF (1 << 4) #define RCC_CIR_HSERDYF (1 << 3) #define RCC_CIR_HSIRDYF (1 << 2) #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) /* --- RCC_AHBRSTR values ------------------------------------------------- */ #define RCC_AHBRSTR_DMA1RST (1 << 24) #define RCC_AHBRSTR_FLITFRST (1 << 15) #define RCC_AHBRSTR_CRCRST (1 << 12) #define RCC_AHBRSTR_GPIOHRST (1 << 5) #define RCC_AHBRSTR_GPIOERST (1 << 4) #define RCC_AHBRSTR_GPIODRST (1 << 3) #define RCC_AHBRSTR_GPIOCRST (1 << 2) #define RCC_AHBRSTR_GPIOBRST (1 << 1) #define RCC_AHBRSTR_GPIOARST (1 << 0) /* --- RCC_APB2RSTR values ------------------------------------------------- */ #define RCC_APB2RSTR_USART1RST (1 << 14) #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_ADC1RST (1 << 9) #define RCC_APB2RSTR_TIM11RST (1 << 4) #define RCC_APB2RSTR_TIM10RST (1 << 3) #define RCC_APB2RSTR_TIM9RST (1 << 2) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* --- RCC_APB1RSTR values ------------------------------------------------- */ #define RCC_APB1RSTR_COMPRST (1 << 31) #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) #define RCC_APB1RSTR_USBRST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_LCDRST (1 << 9) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM5RST (1 << 3) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) /* --- RCC_AHBENR values --------------------------------------------------- */ /** @defgroup rcc_ahbenr_en RCC_AHBENR enable values @ingroup STM32L1xx_rcc_defines @{*/ #define RCC_AHBENR_DMA1EN (1 << 24) #define RCC_AHBENR_FLITFEN (1 << 15) #define RCC_AHBENR_CRCEN (1 << 12) #define RCC_AHBENR_GPIOHEN (1 << 5) #define RCC_AHBENR_GPIOEEN (1 << 4) #define RCC_AHBENR_GPIODEN (1 << 3) #define RCC_AHBENR_GPIOCEN (1 << 2) #define RCC_AHBENR_GPIOBEN (1 << 1) #define RCC_AHBENR_GPIOAEN (1 << 0) /*@}*/ /* --- RCC_APB2ENR values -------------------------------------------------- */ /** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values @ingroup STM32L1xx_rcc_defines @{*/ #define RCC_APB2ENR_USART1EN (1 << 14) #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_ADC1EN (1 << 9) #define RCC_APB2ENR_TIM11EN (1 << 4) #define RCC_APB2ENR_TIM10EN (1 << 3) #define RCC_APB2ENR_TIM9EN (1 << 2) #define RCC_APB2ENR_SYSCFGEN (1 << 0) /*@}*/ /* --- RCC_APB1ENR values -------------------------------------------------- */ /** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values @ingroup STM32L1xx_rcc_defines @{*/ #define RCC_APB1ENR_COMPEN (1 << 31) #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_USBEN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) #define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_LCDEN (1 << 9) #define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /*@}*/ /* --- RCC_AHBLPENR -------------------------------------------------------- */ #define RCC_AHBLPENR_DMA1LPEN (1 << 24) #define RCC_AHBLPENR_SRAMLPEN (1 << 16) #define RCC_AHBLPENR_FLITFLPEN (1 << 15) #define RCC_AHBLPENR_CRCLPEN (1 << 12) #define RCC_AHBLPENR_GPIOHLPEN (1 << 5) #define RCC_AHBLPENR_GPIOELPEN (1 << 4) #define RCC_AHBLPENR_GPIODLPEN (1 << 3) #define RCC_AHBLPENR_GPIOCLPEN (1 << 2) #define RCC_AHBLPENR_GPIOBLPEN (1 << 1) #define RCC_AHBLPENR_GPIOALPEN (1 << 0) #define RCC_APB2LPENR_USART1LPEN (1 << 14) #define RCC_APB2LPENR_SPI1LPEN (1 << 12) #define RCC_APB2LPENR_ADC1LPEN (1 << 9) #define RCC_APB2LPENR_TIM11LPEN (1 << 4) #define RCC_APB2LPENR_TIM10LPEN (1 << 3) #define RCC_APB2LPENR_TIM9LPEN (1 << 2) #define RCC_APB2LPENR_SYSCFGLPEN (1 << 0) #define RCC_APB1LPENR_COMPLPEN (1 << 31) #define RCC_APB1LPENR_DACLPEN (1 << 29) #define RCC_APB1LPENR_PWRLPEN (1 << 28) #define RCC_APB1LPENR_USBLPEN (1 << 23) #define RCC_APB1LPENR_I2C2LPEN (1 << 22) #define RCC_APB1LPENR_I2C1LPEN (1 << 21) #define RCC_APB1LPENR_USART3LPEN (1 << 18) #define RCC_APB1LPENR_USART2LPEN (1 << 17) #define RCC_APB1LPENR_SPI2LPEN (1 << 14) #define RCC_APB1LPENR_WWDGLPEN (1 << 11) #define RCC_APB1LPENR_LCDLPEN (1 << 9) #define RCC_APB1LPENR_TIM7LPEN (1 << 5) #define RCC_APB1LPENR_TIM6LPEN (1 << 4) #define RCC_APB1LPENR_TIM4LPEN (1 << 2) #define RCC_APB1LPENR_TIM3LPEN (1 << 1) #define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ #define RCC_CSR_LPWRRSTF (1 << 31) #define RCC_CSR_WWDGRSTF (1 << 30) #define RCC_CSR_IWDGRSTF (1 << 29) #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) #define RCC_CSR_OBLRSTF (1 << 25) #define RCC_CSR_RMVF (1 << 24) #define RCC_CSR_RTCRST (1 << 23) #define RCC_CSR_RTCEN (1 << 22) #define RCC_CSR_RTCSEL_SHIFT (16) #define RCC_CSR_RTCSEL_MASK (0x3) #define RCC_CSR_RTCSEL_NONE (0x0) #define RCC_CSR_RTCSEL_LSE (0x1) #define RCC_CSR_RTCSEL_LSI (0x2) #define RCC_CSR_RTCSEL_HSI (0x3) #define RCC_CSR_LSECSSD (1 << 12) #define RCC_CSR_LSECSSON (1 << 11) #define RCC_CSR_LSEBYP (1 << 10) #define RCC_CSR_LSERDY (1 << 9) #define RCC_CSR_LSEON (1 << 8) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) typedef struct { uint8_t pll_mul; uint16_t pll_div; uint8_t pll_source; uint32_t flash_config; uint8_t hpre; uint8_t ppre1; uint8_t ppre2; vos_scale_t voltage_scale; uint32_t apb1_frequency; uint32_t apb2_frequency; uint8_t msi_range; } clock_scale_t; typedef enum { CLOCK_VRANGE1_HSI_PLL_24MHZ, CLOCK_VRANGE1_HSI_PLL_32MHZ, CLOCK_VRANGE1_HSI_RAW_16MHZ, CLOCK_VRANGE1_HSI_RAW_4MHZ, CLOCK_VRANGE1_MSI_RAW_4MHZ, CLOCK_VRANGE1_MSI_RAW_2MHZ, CLOCK_CONFIG_END } clock_config_entry_t; extern const clock_scale_t clock_config[CLOCK_CONFIG_END]; /* --- Variable definitions ------------------------------------------------ */ extern uint32_t rcc_ppre1_frequency; extern uint32_t rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ typedef enum { PLL, HSE, HSI, MSI, LSE, LSI } osc_t; BEGIN_DECLS void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); int rcc_osc_ready_int_flag(osc_t osc); void rcc_css_int_clear(void); int rcc_css_int_flag(void); void rcc_wait_for_osc_ready(osc_t osc); void rcc_wait_for_sysclk_status(osc_t osc); void rcc_osc_on(osc_t osc); void rcc_osc_off(osc_t osc); void rcc_css_enable(void); void rcc_css_disable(void); void rcc_osc_bypass_enable(osc_t osc); void rcc_osc_bypass_disable(osc_t osc); void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); void rcc_set_sysclk_source(uint32_t clk); void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, uint32_t divisor); void rcc_set_pll_source(uint32_t pllsrc); void rcc_set_adcpre(uint32_t adcpre); void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); void rcc_set_usbpre(uint32_t usbpre); void rcc_set_rtcpre(uint32_t rtcpre); uint32_t rcc_system_clock_source(void); void rcc_rtc_select_clock(uint32_t clock); void rcc_clock_setup_msi(const clock_scale_t *clock); void rcc_clock_setup_hsi(const clock_scale_t *clock); void rcc_clock_setup_pll(const clock_scale_t *clock); void rcc_backupdomain_reset(void); END_DECLS /**@}*/ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/rtc.h000066400000000000000000000021051435536612600233720ustar00rootroot00000000000000/** @defgroup rtc_defines RTC Defines @brief Defined Constants and Types for the STM32L1xx RTC @ingroup STM32L1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_RTC_H #define LIBOPENCM3_RTC_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/spi.h000066400000000000000000000021031435536612600233730ustar00rootroot00000000000000/** @defgroup spi_defines SPI Defines @brief Defined Constants and Types for the STM32L1xx SPI @ingroup STM32L1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SPI_H #define LIBOPENCM3_SPI_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/syscfg.h000066400000000000000000000016661435536612600241130ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SYSCFG_H #define LIBOPENCM3_SYSCFG_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/timer.h000066400000000000000000000053131435536612600237260ustar00rootroot00000000000000/** @defgroup timer_defines Timer Defines @brief libopencm3 Defined Constants and Types for the STM32L1xx Timers @ingroup STM32L1xx_defines @version 1.0.0 @date 8 March 2013 @author @htmlonly © @endhtmlonly 2011 Fergus Noble LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_TIMER_H #define LIBOPENCM3_TIMER_H #include /* * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: * CNT, ARR, CCR1, CCR2, CCR3, CCR4 */ /* Timer 2/3 option register (TIMx_OR) */ #define TIM_OR(tim_base) MMIO32(tim_base + 0x50) #define TIM2_OR TIM_OR(TIM2) #define TIM3_OR TIM_OR(TIM3) /* --- TIMx_OR values ---------------------------------------------------- */ /* ITR1_RMP */ /****************************************************************************/ /** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap @ingroup timer_defines @{*/ /** Internal Trigger 1 remapped to timer 10 output compare */ #define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0) /** Internal Trigger 1 remapped to timer 5 TGO */ #define TIM2_OR_ITR1_RMP_TIM5_TGO (0x1 << 0) /**@}*/ #define TIM3_OR_ITR1_RMP_MASK (0x1 << 0) /* --- TIMx_OR values ---------------------------------------------------- */ /* ITR2_RMP */ /****************************************************************************/ /** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Option Register Internal Trigger 2 Remap @ingroup timer_defines @{*/ /** Internal Trigger 1 remapped to timer 11 output compare */ #define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0) /** Internal Trigger 1 remapped to timer 5 TGO */ #define TIM3_OR_ITR2_RMP_PTP (0x1 << 0) /**@}*/ #define TIM3_OR_ITR2_RMP_MASK (0x1 << 0) /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS void timer_set_option(uint32_t timer_peripheral, uint32_t option); END_DECLS #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/l1/usart.h000066400000000000000000000021201435536612600237350ustar00rootroot00000000000000/** @defgroup usart_defines USART Defines @brief Defined Constants and Types for the STM32L1xx USART @ingroup STM32L1xx_defines @version 1.0.0 @date 5 December 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H #include #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/memorymap.h000066400000000000000000000025161435536612600243020ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_MEMORYMAP_COMMON_H #define LIBOPENCM3_MEMORYMAP_COMMON_H #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif #endif /* LIBOPENCM3_MEMORYMAP_COMMON_H */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/otg_fs.h000066400000000000000000000324111435536612600235520ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_OTG_FS_H #define LIBOPENCM3_OTG_FS_H #include #include /* Core Global Control and Status Registers */ #define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) #define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) #define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) #define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) #define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) #define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) #define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) #define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) #define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) #define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) #define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) #define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) #define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) #define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) #define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) #define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 \ + 4*(x-1)) /* Host-mode Control and Status Registers */ #define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) #define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) #define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) #define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) #define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) #define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) #define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) #define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) #define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) #define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) #define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) /* Device-mode Control and Status Registers */ #define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) #define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) #define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) #define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) #define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) #define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) #define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) #define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) #define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) #define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) #define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) #define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + \ 0x20*(x)) #define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) #define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + \ 0x20*(x)) #define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + \ 0x20*(x)) #define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + \ 0x20*(x)) #define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) #define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) #define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + \ 0x20*(x)) #define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + \ 0x20*(x)) #define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + \ 0x20*(x)) /* Power and clock gating control and status register */ #define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) /* Data FIFO */ #define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \ + (((x) + 1) \ << 12))) /* Global CSRs */ /* OTG_FS USB control registers (OTG_HS_GOTGCTL) */ #define OTG_FS_GOTGCTL_BSVLD (1 << 19) #define OTG_FS_GOTGCTL_ASVLD (1 << 18) #define OTG_FS_GOTGCTL_DBCT (1 << 17) #define OTG_FS_GOTGCTL_CIDSTS (1 << 16) #define OTG_FS_GOTGCTL_DHNPEN (1 << 11) #define OTG_FS_GOTGCTL_HSHNPEN (1 << 10) #define OTG_FS_GOTGCTL_HNPRQ (1 << 9) #define OTG_FS_GOTGCTL_HNGSCS (1 << 8) #define OTG_FS_GOTGCTL_SRQ (1 << 1) #define OTG_FS_GOTGCTL_SRQSCS (1 << 0) /* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ #define OTG_FS_GAHBCFG_GINT 0x0001 #define OTG_FS_GAHBCFG_TXFELVL 0x0080 #define OTG_FS_GAHBCFG_PTXFELVL 0x0100 /* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ #define OTG_FS_GUSBCFG_TOCAL 0x00000003 #define OTG_FS_GUSBCFG_SRPCAP 0x00000100 #define OTG_FS_GUSBCFG_HNPCAP 0x00000200 #define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) #define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) #define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) #define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 #define OTG_FS_GUSBCFG_FHMOD 0x20000000 #define OTG_FS_GUSBCFG_FDMOD 0x40000000 #define OTG_FS_GUSBCFG_CTXPKT 0x80000000 #define OTG_FS_GUSBCFG_PHYSEL (1 << 7) /* OTG_FS reset register (OTG_FS_GRSTCTL) */ #define OTG_FS_GRSTCTL_AHBIDL (1 << 31) /* Bits 30:11 - Reserved */ #define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) #define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) #define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 3 - Reserved */ #define OTG_FS_GRSTCTL_FCRST (1 << 2) #define OTG_FS_GRSTCTL_HSRST (1 << 1) #define OTG_FS_GRSTCTL_CSRST (1 << 0) /* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ #define OTG_FS_GINTSTS_WKUPINT (1 << 31) #define OTG_FS_GINTSTS_SRQINT (1 << 30) #define OTG_FS_GINTSTS_DISCINT (1 << 29) #define OTG_FS_GINTSTS_CIDSCHG (1 << 28) /* Bit 27 - Reserved */ #define OTG_FS_GINTSTS_PTXFE (1 << 26) #define OTG_FS_GINTSTS_HCINT (1 << 25) #define OTG_FS_GINTSTS_HPRTINT (1 << 24) /* Bits 23:22 - Reserved */ #define OTG_FS_GINTSTS_IPXFR (1 << 21) #define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) #define OTG_FS_GINTSTS_IISOIXFR (1 << 20) #define OTG_FS_GINTSTS_OEPINT (1 << 19) #define OTG_FS_GINTSTS_IEPINT (1 << 18) /* Bits 17:16 - Reserved */ #define OTG_FS_GINTSTS_EOPF (1 << 15) #define OTG_FS_GINTSTS_ISOODRP (1 << 14) #define OTG_FS_GINTSTS_ENUMDNE (1 << 13) #define OTG_FS_GINTSTS_USBRST (1 << 12) #define OTG_FS_GINTSTS_USBSUSP (1 << 11) #define OTG_FS_GINTSTS_ESUSP (1 << 10) /* Bits 9:8 - Reserved */ #define OTG_FS_GINTSTS_GONAKEFF (1 << 7) #define OTG_FS_GINTSTS_GINAKEFF (1 << 6) #define OTG_FS_GINTSTS_NPTXFE (1 << 5) #define OTG_FS_GINTSTS_RXFLVL (1 << 4) #define OTG_FS_GINTSTS_SOF (1 << 3) #define OTG_FS_GINTSTS_OTGINT (1 << 2) #define OTG_FS_GINTSTS_MMIS (1 << 1) #define OTG_FS_GINTSTS_CMOD (1 << 0) /* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ #define OTG_FS_GINTMSK_MMISM 0x00000002 #define OTG_FS_GINTMSK_OTGINT 0x00000004 #define OTG_FS_GINTMSK_SOFM 0x00000008 #define OTG_FS_GINTMSK_RXFLVLM 0x00000010 #define OTG_FS_GINTMSK_NPTXFEM 0x00000020 #define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 #define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 #define OTG_FS_GINTMSK_ESUSPM 0x00000400 #define OTG_FS_GINTMSK_USBSUSPM 0x00000800 #define OTG_FS_GINTMSK_USBRST 0x00001000 #define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 #define OTG_FS_GINTMSK_ISOODRPM 0x00004000 #define OTG_FS_GINTMSK_EOPFM 0x00008000 #define OTG_FS_GINTMSK_EPMISM 0x00020000 #define OTG_FS_GINTMSK_IEPINT 0x00040000 #define OTG_FS_GINTMSK_OEPINT 0x00080000 #define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 #define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 #define OTG_FS_GINTMSK_IPXFRM 0x00200000 #define OTG_FS_GINTMSK_PRTIM 0x01000000 #define OTG_FS_GINTMSK_HCIM 0x02000000 #define OTG_FS_GINTMSK_PTXFEM 0x04000000 #define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 #define OTG_FS_GINTMSK_DISCINT 0x20000000 #define OTG_FS_GINTMSK_SRQIM 0x40000000 #define OTG_FS_GINTMSK_WUIM 0x80000000 /* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ /* Bits 31:25 - Reserved */ #define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) #define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) #define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) #define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) #define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) #define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) #define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) #define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) #define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) #define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) #define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) #define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) #define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) #define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) /* OTG_FS general core configuration register (OTG_FS_GCCFG) */ /* Bits 31:21 - Reserved */ #define OTG_FS_GCCFG_SOFOUTEN (1 << 20) #define OTG_FS_GCCFG_VBUSBSEN (1 << 19) #define OTG_FS_GCCFG_VBUSASEN (1 << 18) /* Bit 17 - Reserved */ #define OTG_FS_GCCFG_PWRDWN (1 << 16) /* Bits 15:0 - Reserved */ /* Device-mode CSRs */ /* OTG_FS device control register (OTG_FS_DCTL) */ /* Bits 31:12 - Reserved */ #define OTG_FS_DCTL_POPRGDNE (1 << 11) #define OTG_FS_DCTL_CGONAK (1 << 10) #define OTG_FS_DCTL_SGONAK (1 << 9) #define OTG_FS_DCTL_SGINAK (1 << 8) #define OTG_FS_DCTL_TCTL_MASK (7 << 4) #define OTG_FS_DCTL_GONSTS (1 << 3) #define OTG_FS_DCTL_GINSTS (1 << 2) #define OTG_FS_DCTL_SDIS (1 << 1) #define OTG_FS_DCTL_RWUSIG (1 << 0) /* OTG_FS device configuration register (OTG_FS_DCFG) */ #define OTG_FS_DCFG_DSPD 0x0003 #define OTG_FS_DCFG_NZLSOHSK 0x0004 #define OTG_FS_DCFG_DAD 0x07F0 #define OTG_FS_DCFG_PFIVL 0x1800 /* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ /* Bits 31:10 - Reserved */ #define OTG_FS_DIEPMSK_BIM (1 << 9) #define OTG_FS_DIEPMSK_TXFURM (1 << 8) /* Bit 7 - Reserved */ #define OTG_FS_DIEPMSK_INEPNEM (1 << 6) #define OTG_FS_DIEPMSK_INEPNMM (1 << 5) #define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) #define OTG_FS_DIEPMSK_TOM (1 << 3) /* Bit 2 - Reserved */ #define OTG_FS_DIEPMSK_EPDM (1 << 1) #define OTG_FS_DIEPMSK_XFRCM (1 << 0) /* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ /* Bits 31:10 - Reserved */ #define OTG_FS_DOEPMSK_BOIM (1 << 9) #define OTG_FS_DOEPMSK_OPEM (1 << 8) /* Bit 7 - Reserved */ #define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) /* Bit 5 - Reserved */ #define OTG_FS_DOEPMSK_OTEPDM (1 << 4) #define OTG_FS_DOEPMSK_STUPM (1 << 3) /* Bit 2 - Reserved */ #define OTG_FS_DOEPMSK_EPDM (1 << 1) #define OTG_FS_DOEPMSK_XFRCM (1 << 0) /* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ #define OTG_FS_DIEPCTL0_EPENA (1 << 31) #define OTG_FS_DIEPCTL0_EPDIS (1 << 30) /* Bits 29:28 - Reserved */ #define OTG_FS_DIEPCTLX_SD0PID (1 << 28) #define OTG_FS_DIEPCTL0_SNAK (1 << 27) #define OTG_FS_DIEPCTL0_CNAK (1 << 26) #define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) #define OTG_FS_DIEPCTL0_STALL (1 << 21) /* Bit 20 - Reserved */ #define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) #define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 16 - Reserved */ #define OTG_FS_DIEPCTL0_USBAEP (1 << 15) /* Bits 14:2 - Reserved */ #define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) #define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) #define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) #define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) #define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) /* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ #define OTG_FS_DOEPCTL0_EPENA (1 << 31) #define OTG_FS_DOEPCTL0_EPDIS (1 << 30) /* Bits 29:28 - Reserved */ #define OTG_FS_DOEPCTLX_SD0PID (1 << 28) #define OTG_FS_DOEPCTL0_SNAK (1 << 27) #define OTG_FS_DOEPCTL0_CNAK (1 << 26) /* Bits 25:22 - Reserved */ #define OTG_FS_DOEPCTL0_STALL (1 << 21) #define OTG_FS_DOEPCTL0_SNPM (1 << 20) #define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) #define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 16 - Reserved */ #define OTG_FS_DOEPCTL0_USBAEP (1 << 15) /* Bits 14:2 - Reserved */ #define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) #define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) #define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) #define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) #define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) /* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ /* Bits 31:8 - Reserved */ #define OTG_FS_DIEPINTX_TXFE (1 << 7) #define OTG_FS_DIEPINTX_INEPNE (1 << 6) /* Bit 5 - Reserved */ #define OTG_FS_DIEPINTX_ITTXFE (1 << 4) #define OTG_FS_DIEPINTX_TOC (1 << 3) /* Bit 2 - Reserved */ #define OTG_FS_DIEPINTX_EPDISD (1 << 1) #define OTG_FS_DIEPINTX_XFRC (1 << 0) /* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ /* Bits 31:7 - Reserved */ #define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) /* Bit 5 - Reserved */ #define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) #define OTG_FS_DOEPINTX_STUP (1 << 3) /* Bit 2 - Reserved */ #define OTG_FS_DOEPINTX_EPDISD (1 << 1) #define OTG_FS_DOEPINTX_XFRC (1 << 0) /* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_FS_DOEPTSIZ0) */ /* Bit 31 - Reserved */ #define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) #define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) #define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) #define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) /* Bits 28:20 - Reserved */ #define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) /* Bits 18:7 - Reserved */ #define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/otg_hs.h000066400000000000000000000362611435536612600235630ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_OTG_HS_H #define LIBOPENCM3_OTG_HS_H #include #include /* Core Global Control and Status Registers */ #define OTG_GOTGCTL 0x000 #define OTG_GOTGIN 0x004 #define OTG_GAHBCFG 0x008 #define OTG_GUSBCFG 0x00C #define OTG_GRSTCTL 0x010 #define OTG_GINTSTS 0x014 #define OTG_GINTMSK 0x018 #define OTG_GRXSTSR 0x01C #define OTG_GRXSTSP 0x020 #define OTG_GRXFSIZ 0x024 #define OTG_GNPTXFSIZ 0x028 #define OTG_GNPTXSTS 0x02C #define OTG_GCCFG 0x038 #define OTG_CID 0x03C #define OTG_HPTXFSIZ 0x100 #define OTG_DIEPTXF(x) (0x104 + 4*(x-1)) /* Host-mode Control and Status Registers */ #define OTG_HCFG 0x400 #define OTG_HFIR 0x404 #define OTG_HFNUM 0x408 #define OTG_HPTXSTS 0x410 #define OTG_HAINT 0x414 #define OTG_HAINTMSK 0x418 #define OTG_HPRT 0x440 #define OTG_HCCHARx 0x500 #define OTG_HCINTx 0x508 #define OTG_HCINTMSKx 0x50C #define OTG_HCTSIZx 0x510 /* Device-mode Control and Status Registers */ #define OTG_DCFG 0x800 #define OTG_DCTL 0x804 #define OTG_DSTS 0x808 #define OTG_DIEPMSK 0x810 #define OTG_DOEPMSK 0x814 #define OTG_DAINT 0x818 #define OTG_DAINTMSK 0x81C #define OTG_DVBUSDIS 0x828 #define OTG_DVBUSPULSE 0x82C #define OTG_DIEPEMPMSK 0x834 #define OTG_DIEPCTL0 0x900 #define OTG_DIEPCTL(x) (0x900 + 0x20*(x)) #define OTG_DOEPCTL0 0xB00 #define OTG_DOEPCTL(x) (0xB00 + 0x20*(x)) #define OTG_DIEPINT(x) (0x908 + 0x20*(x)) #define OTG_DOEPINT(x) (0xB08 + 0x20*(x)) #define OTG_DIEPTSIZ0 0x910 #define OTG_DOEPTSIZ0 0xB10 #define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x)) #define OTG_DTXFSTS(x) (0x918 + 0x20*(x)) #define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x)) /* Power and clock gating control and status register */ #define OTG_PCGCCTL 0xE00 /* Data FIFO */ #define OTG_FIFO(x) (((x) + 1) << 12) /***********************************************************************/ /* Core Global Control and Status Registers */ #define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL) #define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT) #define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG) #define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG) #define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL) #define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS) #define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK) #define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR) #define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP) #define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ) #define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ) #define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS) #define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG) #define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID) #define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ) #define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x)) /* Host-mode Control and Status Registers */ #define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG) #define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR) #define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM) #define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS) #define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT) #define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK) #define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT) #define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx) #define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx) #define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx) #define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx) /* Device-mode Control and Status Registers */ #define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG) #define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL) #define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS) #define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK) #define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK) #define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT) #define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK) #define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS) #define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE) #define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK) #define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0) #define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x)) #define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0) #define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x)) #define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x)) #define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x)) #define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0) #define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0) #define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ OTG_DIEPTSIZ(x)) #define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x)) #define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ OTG_DOEPTSIZ(x)) /* Power and clock gating control and status register */ #define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL) /* Data FIFO */ #define OTG_HS_FIFO(x) (&MMIO32(USB_OTG_HS_BASE + OTG_FIFO(x))) /* Global CSRs */ /* OTG_HS USB control registers (OTG_FS_GOTGCTL) */ #define OTG_HS_GOTGCTL_BSVLD (1 << 19) #define OTG_HS_GOTGCTL_ASVLD (1 << 18) #define OTG_HS_GOTGCTL_DBCT (1 << 17) #define OTG_HS_GOTGCTL_CIDSTS (1 << 16) #define OTG_HS_GOTGCTL_DHNPEN (1 << 11) #define OTG_HS_GOTGCTL_HSHNPEN (1 << 10) #define OTG_HS_GOTGCTL_HNPRQ (1 << 9) #define OTG_HS_GOTGCTL_HNGSCS (1 << 8) #define OTG_HS_GOTGCTL_SRQ (1 << 1) #define OTG_HS_GOTGCTL_SRQSCS (1 << 0) /* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */ #define OTG_HS_GAHBCFG_GINT 0x0001 #define OTG_HS_GAHBCFG_TXFELVL 0x0080 #define OTG_HS_GAHBCFG_PTXFELVL 0x0100 /* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */ #define OTG_HS_GUSBCFG_TOCAL 0x00000003 #define OTG_HS_GUSBCFG_SRPCAP 0x00000100 #define OTG_HS_GUSBCFG_HNPCAP 0x00000200 #define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10) #define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10) #define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10) #define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000 #define OTG_HS_GUSBCFG_FHMOD 0x20000000 #define OTG_HS_GUSBCFG_FDMOD 0x40000000 #define OTG_HS_GUSBCFG_CTXPKT 0x80000000 #define OTG_HS_GUSBCFG_PHYSEL (1 << 6) /* OTG_FS reset register (OTG_HS_GRSTCTL) */ #define OTG_HS_GRSTCTL_AHBIDL (1 << 31) /* Bits 30:11 - Reserved */ #define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6) #define OTG_HS_GRSTCTL_TXFFLSH (1 << 5) #define OTG_HS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 3 - Reserved */ #define OTG_HS_GRSTCTL_FCRST (1 << 2) #define OTG_HS_GRSTCTL_HSRST (1 << 1) #define OTG_HS_GRSTCTL_CSRST (1 << 0) /* OTG_FS interrupt status register (OTG_HS_GINTSTS) */ #define OTG_HS_GINTSTS_WKUPINT (1 << 31) #define OTG_HS_GINTSTS_SRQINT (1 << 30) #define OTG_HS_GINTSTS_DISCINT (1 << 29) #define OTG_HS_GINTSTS_CIDSCHG (1 << 28) /* Bit 27 - Reserved */ #define OTG_HS_GINTSTS_PTXFE (1 << 26) #define OTG_HS_GINTSTS_HCINT (1 << 25) #define OTG_HS_GINTSTS_HPRTINT (1 << 24) /* Bits 23:22 - Reserved */ #define OTG_HS_GINTSTS_IPXFR (1 << 21) #define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21) #define OTG_HS_GINTSTS_IISOIXFR (1 << 20) #define OTG_HS_GINTSTS_OEPINT (1 << 19) #define OTG_HS_GINTSTS_IEPINT (1 << 18) /* Bits 17:16 - Reserved */ #define OTG_HS_GINTSTS_EOPF (1 << 15) #define OTG_HS_GINTSTS_ISOODRP (1 << 14) #define OTG_HS_GINTSTS_ENUMDNE (1 << 13) #define OTG_HS_GINTSTS_USBRST (1 << 12) #define OTG_HS_GINTSTS_USBSUSP (1 << 11) #define OTG_HS_GINTSTS_ESUSP (1 << 10) /* Bits 9:8 - Reserved */ #define OTG_HS_GINTSTS_GONAKEFF (1 << 7) #define OTG_HS_GINTSTS_GINAKEFF (1 << 6) #define OTG_HS_GINTSTS_NPTXFE (1 << 5) #define OTG_HS_GINTSTS_RXFLVL (1 << 4) #define OTG_HS_GINTSTS_SOF (1 << 3) #define OTG_HS_GINTSTS_OTGINT (1 << 2) #define OTG_HS_GINTSTS_MMIS (1 << 1) #define OTG_HS_GINTSTS_CMOD (1 << 0) /* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */ #define OTG_HS_GINTMSK_MMISM 0x00000002 #define OTG_HS_GINTMSK_OTGINT 0x00000004 #define OTG_HS_GINTMSK_SOFM 0x00000008 #define OTG_HS_GINTMSK_RXFLVLM 0x00000010 #define OTG_HS_GINTMSK_NPTXFEM 0x00000020 #define OTG_HS_GINTMSK_GINAKEFFM 0x00000040 #define OTG_HS_GINTMSK_GONAKEFFM 0x00000080 #define OTG_HS_GINTMSK_ESUSPM 0x00000400 #define OTG_HS_GINTMSK_USBSUSPM 0x00000800 #define OTG_HS_GINTMSK_USBRST 0x00001000 #define OTG_HS_GINTMSK_ENUMDNEM 0x00002000 #define OTG_HS_GINTMSK_ISOODRPM 0x00004000 #define OTG_HS_GINTMSK_EOPFM 0x00008000 #define OTG_HS_GINTMSK_EPMISM 0x00020000 #define OTG_HS_GINTMSK_IEPINT 0x00040000 #define OTG_HS_GINTMSK_OEPINT 0x00080000 #define OTG_HS_GINTMSK_IISOIXFRM 0x00100000 #define OTG_HS_GINTMSK_IISOOXFRM 0x00200000 #define OTG_HS_GINTMSK_IPXFRM 0x00200000 #define OTG_HS_GINTMSK_PRTIM 0x01000000 #define OTG_HS_GINTMSK_HCIM 0x02000000 #define OTG_HS_GINTMSK_PTXFEM 0x04000000 #define OTG_HS_GINTMSK_CIDSCHGM 0x10000000 #define OTG_HS_GINTMSK_DISCINT 0x20000000 #define OTG_HS_GINTMSK_SRQIM 0x40000000 #define OTG_HS_GINTMSK_WUIM 0x80000000 /* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */ /* Bits 31:25 - Reserved */ #define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21) #define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17) #define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) #define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17) #define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) #define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) #define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) #define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15) #define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15) #define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15) #define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15) #define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15) #define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4) #define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0) /* OTG_FS general core configuration register (OTG_HS_GCCFG) */ /* Bits 31:21 - Reserved */ #define OTG_HS_GCCFG_SOFOUTEN (1 << 20) #define OTG_HS_GCCFG_VBUSBSEN (1 << 19) #define OTG_HS_GCCFG_VBUSASEN (1 << 18) /* Bit 17 - Reserved */ #define OTG_HS_GCCFG_PWRDWN (1 << 16) /* Bits 15:0 - Reserved */ /* Device-mode CSRs */ /* OTG_FS device control register (OTG_HS_DCTL) */ /* Bits 31:12 - Reserved */ #define OTG_HS_DCTL_POPRGDNE (1 << 11) #define OTG_HS_DCTL_CGONAK (1 << 10) #define OTG_HS_DCTL_SGONAK (1 << 9) #define OTG_HS_DCTL_SGINAK (1 << 8) #define OTG_HS_DCTL_TCTL_MASK (7 << 4) #define OTG_HS_DCTL_GONSTS (1 << 3) #define OTG_HS_DCTL_GINSTS (1 << 2) #define OTG_HS_DCTL_SDIS (1 << 1) #define OTG_HS_DCTL_RWUSIG (1 << 0) /* OTG_FS device configuration register (OTG_HS_DCFG) */ #define OTG_HS_DCFG_DSPD 0x0003 #define OTG_HS_DCFG_NZLSOHSK 0x0004 #define OTG_HS_DCFG_DAD 0x07F0 #define OTG_HS_DCFG_PFIVL 0x1800 /* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */ /* Bits 31:10 - Reserved */ #define OTG_HS_DIEPMSK_BIM (1 << 9) #define OTG_HS_DIEPMSK_TXFURM (1 << 8) /* Bit 7 - Reserved */ #define OTG_HS_DIEPMSK_INEPNEM (1 << 6) #define OTG_HS_DIEPMSK_INEPNMM (1 << 5) #define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4) #define OTG_HS_DIEPMSK_TOM (1 << 3) /* Bit 2 - Reserved */ #define OTG_HS_DIEPMSK_EPDM (1 << 1) #define OTG_HS_DIEPMSK_XFRCM (1 << 0) /* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */ /* Bits 31:10 - Reserved */ #define OTG_HS_DOEPMSK_BOIM (1 << 9) #define OTG_HS_DOEPMSK_OPEM (1 << 8) /* Bit 7 - Reserved */ #define OTG_HS_DOEPMSK_B2BSTUP (1 << 6) /* Bit 5 - Reserved */ #define OTG_HS_DOEPMSK_OTEPDM (1 << 4) #define OTG_HS_DOEPMSK_STUPM (1 << 3) /* Bit 2 - Reserved */ #define OTG_HS_DOEPMSK_EPDM (1 << 1) #define OTG_HS_DOEPMSK_XFRCM (1 << 0) /* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */ #define OTG_HS_DIEPCTL0_EPENA (1 << 31) #define OTG_HS_DIEPCTL0_EPDIS (1 << 30) /* Bits 29:28 - Reserved */ #define OTG_HS_DIEPCTLX_SD0PID (1 << 28) #define OTG_HS_DIEPCTL0_SNAK (1 << 27) #define OTG_HS_DIEPCTL0_CNAK (1 << 26) #define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22) #define OTG_HS_DIEPCTL0_STALL (1 << 21) /* Bit 20 - Reserved */ #define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18) #define OTG_HS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 16 - Reserved */ #define OTG_HS_DIEPCTL0_USBAEP (1 << 15) /* Bits 14:2 - Reserved */ #define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) #define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0) #define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0) #define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0) #define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0) /* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */ #define OTG_HS_DOEPCTL0_EPENA (1 << 31) #define OTG_HS_DOEPCTL0_EPDIS (1 << 30) /* Bits 29:28 - Reserved */ #define OTG_HS_DOEPCTLX_SD0PID (1 << 28) #define OTG_HS_DOEPCTL0_SNAK (1 << 27) #define OTG_HS_DOEPCTL0_CNAK (1 << 26) /* Bits 25:22 - Reserved */ #define OTG_HS_DOEPCTL0_STALL (1 << 21) #define OTG_HS_DOEPCTL0_SNPM (1 << 20) #define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18) #define OTG_HS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 16 - Reserved */ #define OTG_HS_DOEPCTL0_USBAEP (1 << 15) /* Bits 14:2 - Reserved */ #define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) #define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0) #define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0) #define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0) #define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0) /* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */ /* Bits 31:8 - Reserved */ #define OTG_HS_DIEPINTX_TXFE (1 << 7) #define OTG_HS_DIEPINTX_INEPNE (1 << 6) /* Bit 5 - Reserved */ #define OTG_HS_DIEPINTX_ITTXFE (1 << 4) #define OTG_HS_DIEPINTX_TOC (1 << 3) /* Bit 2 - Reserved */ #define OTG_HS_DIEPINTX_EPDISD (1 << 1) #define OTG_HS_DIEPINTX_XFRC (1 << 0) /* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */ /* Bits 31:7 - Reserved */ #define OTG_HS_DOEPINTX_B2BSTUP (1 << 6) /* Bit 5 - Reserved */ #define OTG_HS_DOEPINTX_OTEPDIS (1 << 4) #define OTG_HS_DOEPINTX_STUP (1 << 3) /* Bit 2 - Reserved */ #define OTG_HS_DOEPINTX_EPDISD (1 << 1) #define OTG_HS_DOEPINTX_XFRC (1 << 0) /* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_HS_DOEPTSIZ0) */ /* Bit 31 - Reserved */ #define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) #define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) #define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) #define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) /* Bits 28:20 - Reserved */ #define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19) /* Bits 18:7 - Reserved */ #define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/pwr.h000066400000000000000000000023361435536612600231040ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/rcc.h000066400000000000000000000023371435536612600230440ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/rtc.h000066400000000000000000000022331435536612600230600ustar00rootroot00000000000000/* This provides unification of code over STM32 subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/sdio.h000066400000000000000000000321731435536612600232340ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Felix Held * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_SDIO_H #define LIBOPENCM3_SDIO_H #include #include /* --- SDIO registers ------------------------------------------------------ */ /* SDIO power control register (SDIO_POWER) */ #define SDIO_POWER MMIO32(SDIO_BASE + 0x00) /* SDI clock control register (SDIO_CLKCR) */ #define SDIO_CLKCR MMIO32(SDIO_BASE + 0x04) /* SDIO argument register (SDIO_ARG) */ #define SDIO_ARG MMIO32(SDIO_BASE + 0x08) /* SDIO command register (SDIO_CMD) */ #define SDIO_CMD MMIO32(SDIO_BASE + 0x0C) /* SDIO command response register (SDIO_RESPCMD) */ #define SDIO_RESPCMD MMIO32(SDIO_BASE + 0x10) /* SDIO response 1..4 register (SDIO_RESPx) */ #define SDIO_RESP1 MMIO32(SDIO_BASE + 0x14) #define SDIO_RESP2 MMIO32(SDIO_BASE + 0x18) #define SDIO_RESP3 MMIO32(SDIO_BASE + 0x1C) #define SDIO_RESP4 MMIO32(SDIO_BASE + 0x20) /* SDIO data timer register (SDIO_DTIMER) */ #define SDIO_DTIMER MMIO32(SDIO_BASE + 0x24) /* SDIO data length register (SDIO_DLEN) */ #define SDIO_DLEN MMIO32(SDIO_BASE + 0x28) /* SDIO data control register (SDIO_DCTRL) */ #define SDIO_DCTRL MMIO32(SDIO_BASE + 0x2C) /* SDIO data counter register (SDIO_DCOUNT) */ /* read only, write has no effect */ #define SDIO_DCOUNT MMIO32(SDIO_BASE + 0x30) /* SDIO status register (SDIO_STA) */ #define SDIO_STA MMIO32(SDIO_BASE + 0x34) /* SDIO interrupt clear register (SDIO_ICR) */ #define SDIO_ICR MMIO32(SDIO_BASE + 0x38) /* SDIO mask register (SDIO_MASK) */ #define SDIO_MASK MMIO32(SDIO_BASE + 0x3C) /* SDIO FIFO counter register (SDIO_FIFOCNT) */ #define SDIO_FIFOCNT MMIO32(SDIO_BASE + 0x48) /* SDIO data FIFO register (SDIO_FIFO) */ /* the SDIO data FIFO is 32 32bit words long, beginning at this address */ #define SDIO_FIFO MMIO32(SDIO_BASE + 0x80) /* --- SDIO_POWER values --------------------------------------------------- */ #define SDIO_POWER_PWRCTRL_SHIFT 0 #define SDIO_POWER_PWRCTRL_PWROFF (0x0 << SDIO_POWER_PWRCTRL_SHIFT) /* what does "10: Reserved power-up" mean? */ #define SDIO_POWER_PWRCTRL_RSVPWRUP (0x2 << SDIO_POWER_PWRCTRL_SHIFT) #define SDIO_POWER_PWRCTRL_PWRON (0x3 << SDIO_POWER_PWRCTRL_SHIFT) /* --- SDIO_POWER values --------------------------------------------------- */ /* HWFC_EN: HW Flow Control enable */ #define SDIO_CLKCR_HWFC_EN (1 << 14) /* NEGEDGE: SDIO_CK dephasing selection bit */ #define SDIO_CLKCR_NEGEDGE (1 << 13) /* WIDBUS: Wide bus mode enable bit */ /* set the width of the data bus */ #define SDIO_CLKCR_WIDBUS_SHIFT 11 #define SDIO_CLKCR_WIDBUS_1 (0x0 << SDIO_CLKCR_WIDBUS_SHIFT) #define SDIO_CLKCR_WIDBUS_4 (0x1 << SDIO_CLKCR_WIDBUS_SHIFT) #define SDIO_CLKCR_WIDBUS_8 (0x2 << SDIO_CLKCR_WIDBUS_SHIFT) /* BYPASS: Clock divider bypass enable bit */ #define SDIO_CLKCR_BYPASS (1 << 10) /* PWRSAV: Power saving configuration bit */ #define SDIO_CLKCR_PWRSAV (1 << 9) /* CLKEN: Clock enable bit */ #define SDIO_CLKCR_CLKEN (1 << 8) /* CLKDIV: Clock divide factor */ #define SDIO_CLKCR_CLKDIV_SHIFT 0 #define SDIO_CLKCR_CLKDIV_MSK (0xFF << SDIO_CLKCR_CLKDIV_SHIFT) /* --- SDIO_CMD values ---------------------------------------------------- */ /* ATACMD: CE-ATA command */ #define SDIO_CMD_ATACMD (1 << 14) /* nIEN: not Interrupt Enable */ #define SDIO_CMD_NIEN (1 << 13) /* ENCMDcompl: Enable CMD completion */ #define SDIO_CMD_ENCMDCOMPL (1 << 12) /* SDIOSuspend: SD I/O suspend command */ #define SDIO_CMD_SDIOSUSPEND (1 << 11) /* CPSMEN: Command path state machine (CPSM) Enable bit */ #define SDIO_CMD_CPSMEN (1 << 10) /* WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal) */ #define SDIO_CMD_WAITPEND (1 << 9) /* WAITINT: CPSM waits for interrupt request */ #define SDIO_CMD_WAITINT (1 << 8) /* WAITRESP: Wait for response bits */ #define SDIO_CMD_WAITRESP_SHIFT 6 /* 00: No response, expect CMDSENT flag */ #define SDIO_CMD_WAITRESP_NO_0 (0x0 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response, expect CMDREND or CCRCFAIL flag */ #define SDIO_CMD_WAITRESP_SHORT (0x1 << SDIO_CMD_WAITRESP_SHIFT) /* 10: No response, expect CMDSENT flag */ #define SDIO_CMD_WAITRESP_NO_2 (0x2 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response, expect CMDREND or CCRCFAIL flag */ #define SDIO_CMD_WAITRESP_LONG (0x3 << SDIO_CMD_WAITRESP_SHIFT) /* CMDINDEX: Command index */ #define SDIO_CMD_CMDINDEX_SHIFT 0 #define SDIO_CMD_CMDINDEX_MSK (0x3F << SDIO_CMD_CMDINDEX_SHIFT) /* --- SDIO_RESPCMD values ------------------------------------------------ */ #define SDIO_RESPCMD_SHIFT 0 #define SDIO_RESPCMD_MSK (0x3F << SDIO_RESPCMD_SHIFT) /* --- SDIO_DCTRL values -------------------------------------------------- */ /* SDIOEN: SD I/O enable functions */ #define SDIO_DCTRL_SDIOEN (1 << 11) /* RWMOD: Read wait mode */ /* 0: Read Wait control stopping SDIO_D2 * 1: Read Wait control using SDIO_CK */ #define SDIO_DCTRL_RWMOD (1 << 10) /* RWSTOP: Read wait stop */ /* 0: Read wait in progress if RWSTART bit is set * 1: Enable for read wait stop if RWSTART bit is set */ #define SDIO_DCTRL_RWSTOP (1 << 9) /* RWSTART: Read wait start */ #define SDIO_DCTRL_RWSTART (1 << 8) /* DBLOCKSIZE: Data block size */ /* SDIO_DCTRL_DBLOCKSIZE_n * block size is 2**n bytes with 0<=n<=14 */ #define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_1 (0x1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_2 (0x2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_3 (0x3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_4 (0x4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_5 (0x5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_6 (0x6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_7 (0x7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_8 (0x8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_9 (0x9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_10 (0xA << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_11 (0xB << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_12 (0xC << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_13 (0xD << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_14 (0xE << SDIO_DCTRL_DBLOCKSIZE_SHIFT) /* DMAEN: DMA enable bit */ #define SDIO_DCTRL_DMAEN (1 << 3) /* DTMODE: Data transfer mode selection 1: Stream or SDIO multi byte transfer */ #define SDIO_DCTRL_DTMODE (1 << 2) /* DTDIR: Data transfer direction selection */ /* 0: From controller to card. * 1: From card to controller. */ #define SDIO_DCTRL_DTDIR (1 << 1) /* DTEN: Data transfer enabled bit */ #define SDIO_DCTRL_DTEN (1 << 0) /* --- SDIO_STA values ---------------------------------------------------- */ /* CEATAEND: CE-ATA command completion signal received for CMD61 */ #define SDIO_STA_CEATAEND (1 << 23) /* SDIOIT: SDIO interrupt received */ #define SDIO_STA_SDIOIT (1 << 22) /* RXDAVL: Data available in receive FIFO */ #define SDIO_STA_RXDAVL (1 << 21) /* TXDAVL: Data available in transmit FIFO */ #define SDIO_STA_TXDAVL (1 << 20) /* RXFIFOE: Receive FIFO empty */ #define SDIO_STA_RXFIFOE (1 << 19) /* TXFIFOE: Transmit FIFO empty */ /* HW Flow Control enabled -> TXFIFOE signals becomes activated when the FIFO * contains 2 words. */ #define SDIO_STA_TXFIFOE (1 << 18) /* RXFIFOF: Receive FIFO full */ /* HW Flow Control enabled => RXFIFOF signals becomes activated 2 words before * the FIFO is full. */ #define SDIO_STA_RXFIFOF (1 << 17) /* TXFIFOF: Transmit FIFO full */ #define SDIO_STA_TXFIFOF (1 << 16) /* RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO */ #define SDIO_STA_RXFIFOHF (1 << 15) /* TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into * the FIFO */ #define SDIO_STA_TXFIFOHE (1 << 14) /* RXACT: Data receive in progress */ #define SDIO_STA_RXACT (1 << 13) /* TXACT: Data transmit in progress */ #define SDIO_STA_TXACT (1 << 12) /* CMDACT: Command transfer in progress */ #define SDIO_STA_CMDACT (1 << 11) /* DBCKEND: Data block sent/received (CRC check passed) */ #define SDIO_STA_DBCKEND (1 << 10) /* STBITERR: Start bit not detected on all data signals in wide bus mode */ #define SDIO_STA_STBITERR (1 << 9) /* DATAEND: Data end (data counter, SDIDCOUNT, is zero) */ #define SDIO_STA_DATAEND (1 << 8) /* CMDSENT: Command sent (no response required) */ #define SDIO_STA_CMDSENT (1 << 7) /* CMDREND: Command response received (CRC check passed) */ #define SDIO_STA_CMDREND (1 << 6) /* RXOVERR: Received FIFO overrun error */ #define SDIO_STA_RXOVERR (1 << 5) /* TXUNDERR: Transmit FIFO underrun error */ #define SDIO_STA_TXUNDERR (1 << 4) /* DTIMEOUT: Data timeout */ #define SDIO_STA_DTIMEOUT (1 << 3) /* CTIMEOUT: Command response timeout */ #define SDIO_STA_CTIMEOUT (1 << 2) /* DCRCFAIL: Data block sent/received (CRC check failed) */ #define SDIO_STA_DCRCFAIL (1 << 1) /* CCRCFAIL: Command response received (CRC check failed) */ #define SDIO_STA_CCRCFAIL (1 << 0) /* --- SDIO_ICR values ---------------------------------------------------- */ /* CEATAENDC: CEATAEND flag clear bit */ #define SDIO_ICR_CEATAENDC (1 << 23) /* SDIOITC: SDIOIT flag clear bit */ #define SDIO_ICR_SDIOITC (1 << 22) /* DBCKENDC: DBCKEND flag clear bit */ #define SDIO_ICR_DBCKENDC (1 << 10) /* STBITERRC: STBITERR flag clear bit */ #define SDIO_ICR_STBITERRC (1 << 9) /* DATAENDC: DATAEND flag clear bit */ #define SDIO_ICR_DATAENDC (1 << 8) /* CMDSENTC: CMDSENT flag clear bit */ #define SDIO_ICR_CMDSENTC (1 << 7) /* CMDRENDC: CMDREND flag clear bit */ #define SDIO_ICR_CMDRENDC (1 << 6) /* RXOVERRC: RXOVERR flag clear bit */ #define SDIO_ICR_RXOVERRC (1 << 5) /* TXUNDERRC: TXUNDERR flag clear bit */ #define SDIO_ICR_TXUNDERRC (1 << 4) /* DTIMEOUTC: DTIMEOUT flag clear bit */ #define SDIO_ICR_DTIMEOUTC (1 << 3) /* CTIMEOUTC: CTIMEOUT flag clear bit */ #define SDIO_ICR_CTIMEOUTC (1 << 2) /* DCRCFAILC: DCRCFAIL flag clear bit */ #define SDIO_ICR_DCRCFAILC (1 << 1) /* CCRCFAILC: CCRCFAIL flag clear bit */ #define SDIO_ICR_CCRCFAILC (1 << 0) /* --- SDIO_MASK values --------------------------------------------------- */ /* CEATAENDIE: CE-ATA command completion signal received interrupt enable */ #define SDIO_MASK_CEATAENDIE (1 << 23) /* SDIOITIE: SDIO mode interrupt received interrupt enable */ #define SDIO_MASK_SDIOITIE (1 << 22) /* RXDAVLIE: Data available in Rx FIFO interrupt enable */ #define SDIO_MASK_RXDAVLIE (1 << 21) /* TXDAVLIE: Data available in Tx FIFO interrupt enable */ #define SDIO_MASK_TXDAVLIE (1 << 20) /* RXFIFOEIE: Rx FIFO empty interrupt enable */ #define SDIO_MASK_RXFIFOEIE (1 << 19) /* TXFIFOEIE: Tx FIFO empty interrupt enable */ #define SDIO_MASK_TXFIFOEIE (1 << 18) /* RXFIFOFIE: Rx FIFO full interrupt enable */ #define SDIO_MASK_RXFIFOFIE (1 << 17) /* TXFIFOFIE: Tx FIFO full interrupt enable */ #define SDIO_MASK_TXFIFOFIE (1 << 16) /* RXFIFOHFIE: Rx FIFO half full interrupt enable */ #define SDIO_MASK_RXFIFOHFIE (1 << 15) /* TXFIFOHEIE: Tx FIFO half empty interrupt enable */ #define SDIO_MASK_TXFIFOHEIE (1 << 14) /* RXACTIE: Data receive acting interrupt enable */ #define SDIO_MASK_RXACTIE (1 << 13) /* TXACTIE: Data transmit acting interrupt enable */ #define SDIO_MASK_TXACTIE (1 << 12) /* CMDACTIE: Command acting interrupt enable */ #define SDIO_MASK_CMDACTIE (1 << 11) /* DBCKENDIE: Data block end interrupt enable */ #define SDIO_MASK_DBCKENDIE (1 << 10) /* STBITERRIE: Start bit error interrupt enable */ #define SDIO_MASK_STBITERRIE (1 << 9) /* DATAENDIE: Data end interrupt enable */ #define SDIO_MASK_DATAENDIE (1 << 8) /* CMDSENTIE: Command sent interrupt enable */ #define SDIO_MASK_CMDSENTIE (1 << 7) /* CMDRENDIE: Command response received interrupt enable */ #define SDIO_MASK_CMDRENDIE (1 << 6) /* RXOVERRIE: Rx FIFO overrun error interrupt enable */ #define SDIO_MASK_RXOVERRIE (1 << 5) /* TXUNDERRIE: Tx FIFO underrun error interrupt enable */ #define SDIO_MASK_TXUNDERRIE (1 << 4) /* DTIMEOUTIE: Data timeout interrupt enable */ #define SDIO_MASK_DTIMEOUTIE (1 << 3) /* CTIMEOUTIE: Command timeout interrupt enable */ #define SDIO_MASK_CTIMEOUTIE (1 << 2) /* DCRCFAILIE: Data CRC fail interrupt enable */ #define SDIO_MASK_DCRCFAILIE (1 << 1) /* CCRCFAILIE: Command CRC fail interrupt enable */ #define SDIO_MASK_CCRCFAILIE (1 << 0) /* --- Function prototypes ------------------------------------------------- */ /* TODO */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/spi.h000066400000000000000000000023371435536612600230700ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/syscfg.h000066400000000000000000000022531435536612600235700ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/timer.h000066400000000000000000000024511435536612600234120ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/tools.h000066400000000000000000000041101435536612600234240ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_TOOLS_H #define LIBOPENCM3_TOOLS_H /* * Register accessors / manipulators */ /* Get register content. */ #define GET_REG(REG) ((uint16_t) *REG) /* Set register content. */ #define SET_REG(REG, VAL) (*REG = (uint16_t)VAL) /* Clear register bit. */ #define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) /* Clear register bit masking out some bits that must not be touched. */ #define CLR_REG_BIT_MSK(REG, MSK, BIT) \ SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) /* Get masked out bit value. */ #define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) /* * Set/reset a bit in a masked window by using toggle mechanism. * * This means that we look at the bits in the bit window designated by * the mask. If the bit in the masked window is not matching the * bit mask BIT then we write 1 and if the bit in the masked window is * matching the bit mask BIT we write 0. * * TODO: We may need a faster implementation of that one? */ #define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ do { \ register uint16_t toggle_mask = GET_REG(REG) & (MSK); \ register uint16_t bit_selector; \ for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ if ((bit_selector & (BIT)) != 0) { \ toggle_mask ^= bit_selector; \ } \ } \ SET_REG(REG, toggle_mask); \ } while (0) #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/tsc.h000066400000000000000000000016201435536612600230600ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/usart.h000066400000000000000000000023531435536612600234310ustar00rootroot00000000000000/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #if defined(STM32F0) # include #elif defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F3) # include #elif defined(STM32F4) # include #elif defined(STM32L1) # include #else # error "stm32 family not defined." #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/usb.h000066400000000000000000000223611435536612600230650ustar00rootroot00000000000000/** @defgroup adc_defines USB Defines @brief Defined Constants and Types for the STM32F1xx USB Module @ingroup STM32F1xx_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski @date 11 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef LIBOPENCM3_USB_H #define LIBOPENCM3_USB_H #include #include #include /* --- USB base addresses -------------------------------------------------- */ /* USB packet buffer memory base address. */ #define USB_PMA_BASE 0x40006000L /* --- USB general registers ----------------------------------------------- */ /* USB Control register */ #define USB_CNTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x40)) /* USB Interrupt status register */ #define USB_ISTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x44)) /* USB Frame number register */ #define USB_FNR_REG (&MMIO32(USB_DEV_FS_BASE + 0x48)) /* USB Device address register */ #define USB_DADDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x4C)) /* USB Buffer table address register */ #define USB_BTABLE_REG (&MMIO32(USB_DEV_FS_BASE + 0x50)) /* USB EP register */ #define USB_EP_REG(EP) (&MMIO32(USB_DEV_FS_BASE) + (EP)) /* --- USB control register masks / bits ----------------------------------- */ /* Interrupt mask bits, set to 1 to enable interrupt generation */ #define USB_CNTR_CTRM 0x8000 #define USB_CNTR_PMAOVRM 0x4000 #define USB_CNTR_ERRM 0x2000 #define USB_CNTR_WKUPM 0x1000 #define USB_CNTR_SUSPM 0x0800 #define USB_CNTR_RESETM 0x0400 #define USB_CNTR_SOFM 0x0200 #define USB_CNTR_ESOFM 0x0100 /* Request/Force bits */ #define USB_CNTR_RESUME 0x0010 /* Resume request */ #define USB_CNTR_FSUSP 0x0008 /* Force suspend */ #define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */ #define USB_CNTR_PWDN 0x0002 /* Power down */ #define USB_CNTR_FRES 0x0001 /* Force reset */ /* --- USB interrupt status register masks / bits -------------------------- */ #define USB_ISTR_CTR 0x8000 /* Correct Transfer */ #define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ #define USB_ISTR_ERR 0x2000 /* Error */ #define USB_ISTR_WKUP 0x1000 /* Wake up */ #define USB_ISTR_SUSP 0x0800 /* Suspend mode request */ #define USB_ISTR_RESET 0x0400 /* USB RESET request */ #define USB_ISTR_SOF 0x0200 /* Start Of Frame */ #define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */ #define USB_ISTR_DIR 0x0010 /* Direction of transaction */ #define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ /* --- USB interrupt status register manipulators -------------------------- */ /* Note: CTR is read only! */ #define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) #define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) #define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) #define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP) #define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET) #define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) #define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) /* --- USB device address register masks / bits ---------------------------- */ #define USB_DADDR_ENABLE 0x0080 #define USB_DADDR_ADDR 0x007F /* --- USB device address register manipulators ---------------------------- */ /* --- USB endpoint register offsets --------------------------------------- */ #define USB_EP0 0 #define USB_EP1 1 #define USB_EP2 2 #define USB_EP3 3 #define USB_EP4 4 #define USB_EP5 5 #define USB_EP6 6 #define USB_EP7 7 /* --- USB endpoint register masks / bits ---------------------------------- */ /* Masks and toggle bits */ #define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */ #define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */ #define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */ #define USB_EP_SETUP 0x0800 /* Setup transaction completed */ #define USB_EP_TYPE 0x0600 /* Endpoint type */ #define USB_EP_KIND 0x0100 /* Endpoint kind. * When set and type=bulk -> double buffer * When set and type=control -> status out */ #define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ #define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ #define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */ #define USB_EP_ADDR 0x000F /* Endpoint Address */ /* Masking all toggle bits */ #define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ USB_EP_SETUP | \ USB_EP_TYPE | \ USB_EP_KIND | \ USB_EP_TX_CTR | \ USB_EP_ADDR) /* All non toggle bits plus EP_RX toggle bits */ #define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK) /* All non toggle bits plus EP_TX toggle bits */ #define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) /* Endpoint status bits for USB_EP_RX_STAT bit field */ #define USB_EP_RX_STAT_DISABLED 0x0000 #define USB_EP_RX_STAT_STALL 0x1000 #define USB_EP_RX_STAT_NAK 0x2000 #define USB_EP_RX_STAT_VALID 0x3000 /* Endpoint status bits for USB_EP_TX_STAT bit field */ #define USB_EP_TX_STAT_DISABLED 0x0000 #define USB_EP_TX_STAT_STALL 0x0010 #define USB_EP_TX_STAT_NAK 0x0020 #define USB_EP_TX_STAT_VALID 0x0030 /* Endpoint type bits for USB_EP_TYPE bit field */ #define USB_EP_TYPE_BULK 0x0000 #define USB_EP_TYPE_CONTROL 0x0200 #define USB_EP_TYPE_ISO 0x0400 #define USB_EP_TYPE_INTERRUPT 0x0600 /* --- USB endpoint register manipulators ---------------------------------- */ /* * Set USB endpoint tx/rx status. * * USB status field is changed using an awkward toggle mechanism, that * is why we use some helper macros for that. */ #define USB_SET_EP_RX_STAT(EP, STAT) \ TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT) #define USB_SET_EP_TX_STAT(EP, STAT) \ TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT) /* * Macros for clearing and setting USB endpoint register bits that do * not use the toggle mechanism. * * Because the register contains some bits that use the toggle * mechanism we need a helper macro here. Otherwise the code gets really messy. */ #define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \ CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT) #define USB_CLR_EP_RX_CTR(EP) \ USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR) #define USB_CLR_EP_TX_CTR(EP) \ USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR) #define USB_SET_EP_TYPE(EP, TYPE) \ SET_REG(USB_EP_REG(EP), \ (GET_REG(USB_EP_REG(EP)) & \ (USB_EP_NTOGGLE_MSK & \ (~USB_EP_TYPE))) | TYPE) #define USB_SET_EP_KIND(EP) \ SET_REG(USB_EP_REG(EP), \ (GET_REG(USB_EP_REG(EP)) & \ (USB_EP_NTOGGLE_MSK & \ (~USB_EP_KIND))) | USB_EP_KIND) #define USB_CLR_EP_KIND(EP) \ SET_REG(USB_EP_REG(EP), \ (GET_REG(USB_EP_REG(EP)) & \ (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND)))) #define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP) #define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP) #define USB_SET_EP_ADDR(EP, ADDR) \ SET_REG(USB_EP_REG(EP), \ ((GET_REG(USB_EP_REG(EP)) & \ (USB_EP_NTOGGLE_MSK & \ (~USB_EP_ADDR))) | ADDR)) /* Macros for clearing DTOG bits */ #define USB_CLR_EP_TX_DTOG(EP) \ SET_REG(USB_EP_REG(EP), \ GET_REG(USB_EP_REG(EP)) & \ (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG)) #define USB_CLR_EP_RX_DTOG(EP) \ SET_REG(USB_EP_REG(EP), \ GET_REG(USB_EP_REG(EP)) & \ (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) /* --- USB BTABLE registers ------------------------------------------------ */ #define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) #define USB_EP_TX_ADDR(EP) \ ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2)) #define USB_EP_TX_COUNT(EP) \ ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2)) #define USB_EP_RX_ADDR(EP) \ ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2)) #define USB_EP_RX_COUNT(EP) \ ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2)) /* --- USB BTABLE manipulators --------------------------------------------- */ #define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP)) #define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP)) #define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP)) #define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP)) #define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR) #define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT) #define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR) #define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT) #define USB_GET_EP_TX_BUFF(EP) \ (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(EP) * 2)) #define USB_GET_EP_RX_BUFF(EP) \ (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(EP) * 2)) #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/usb_desc.h000066400000000000000000000064261435536612600240670ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_USB_DESC #define LIBOPENCM3_USB_DESC /* Descriptor types */ #define USB_DT_DEVICE 0x01 #define USB_DT_CONF 0x02 #define USB_DT_STRING 0x03 #define USB_DT_INTERFACE 0x04 #define USB_DT_ENDPOINT 0x05 struct usb_desc_head { uint8_t length; /* Descriptor size 0x012 */ uint8_t type; /* Descriptor type ID */ }; struct usb_device_desc { struct usb_desc_head h; /* Size 0x12, ID 0x01 */ uint16_t bcd_usb; /* USB Version */ uint8_t class; /* Device class */ uint8_t sub_class; /* Subclass code */ uint8_t protocol; /* Protocol code */ uint8_t max_psize; /* Maximum packet size -> 64bytes */ uint16_t vendor; /* Vendor number */ uint16_t product; /* Device number */ uint16_t bcd_dev; /* Device version */ uint8_t man_desc; /* Index of manufacturer string desc */ uint8_t prod_desc; /* Index of product string desc */ uint8_t sn_desc; /* Index of serial number string desc */ uint8_t num_conf; /* Number of possible configurations */ }; struct usb_conf_desc_header { struct usb_desc_head h; /* Size 0x09, Id 0x02 */ uint16_t tot_leng; /* Total length of data */ uint8_t num_int; /* Number of interfaces */ uint8_t conf_val; /* Configuration selector */ uint8_t conf_desc; /* Index of conf string desc */ uint8_t attr; /* Attribute bitmap: * 7 : Bus powered * 6 : Self powered * 5 : Remote wakeup * 4..0 : Reserved -> 0000 */ uint8_t max_power; /* Maximum power consumption in 2mA steps */ }; struct usb_int_desc_header { struct usb_desc_head h; /* Size 0x09, Id 0x04 */ uint8_t iface_num; /* Interface id number */ uint8_t alt_setting; /* Alternative setting selector */ uint8_t num_endp; /* Endpoints used */ uint8_t class; /* Interface class */ uint8_t sub_class; /* Subclass code */ uint8_t protocol; /* Protocol code */ uint8_t iface_desc; /* Index of interface string desc */ }; struct usb_ep_desc { struct usb_desc_head h; /* Size 0x07, Id 0x05 */ uint8_t ep_addr; /* Endpoint address: 0..3 : Endpoint Number 4..6 : Reserved -> 0 7 : Direction 0=out 1=in */ uint8_t ep_attr; /* Endpoint attributes */ uint16_t max_psize; /* Maximum packet size -> 64bytes */ uint8_t interval; /* Interval for polling endpoint data. Ignored for bulk & control endpoints. */ }; struct usb_conf_desc { struct usb_conf_desc_header cdh; struct usb_int_desc_header idh; struct usb_ep_desc ep[]; }; struct usb_string_desc { struct usb_desc_head h; /* Size > 0x02, Id 0x03 */ uint16_t string[]; /* String UTF16 encoded */ }; #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/stm32/wwdg.h000066400000000000000000000046061435536612600232460ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef LIBOPENCM3_WWDG_H #define LIBOPENCM3_WWDG_H #include #include /* --- WWDG registers ------------------------------------------------------ */ /* Control register (WWDG_CR) */ #define WWDG_CR MMIO32(WWDG_BASE + 0x00) /* Configuration register (WWDG_CFR) */ #define WWDG_CFR MMIO32(WWDG_BASE + 0x04) /* Status register (WWDG_SR) */ #define WWDG_SR MMIO32(WWDG_BASE + 0x08) /* --- WWDG_CR values ------------------------------------------------------ */ /* Bits [31:8]: Reserved */ /* WDGA: Activation bit */ #define WWDG_CR_WDGA (1 << 7) /* T[6:0]: 7-bit counter (MSB to LSB) */ #define WWDG_CR_T_LSB 0 #define WWDG_CR_T0 (1 << 0) #define WWDG_CR_T1 (1 << 1) #define WWDG_CR_T2 (1 << 2) #define WWDG_CR_T3 (1 << 3) #define WWDG_CR_T4 (1 << 4) #define WWDG_CR_T5 (1 << 5) #define WWDG_CR_T6 (1 << 6) /* --- WWDG_CFR values ----------------------------------------------------- */ /* Bits [31:10]: Reserved */ /* EWI: Early wakeup interrupt */ #define WWDG_CFR_EWI (1 << 9) /* WDGTB[8:7]: Timer base */ #define WWDG_CFR_WDGTB_LSB 7 #define WWDG_CFR_WDGTB_CK_DIV1 0x0 #define WWDG_CFR_WDGTB_CK_DIV2 0x1 #define WWDG_CFR_WDGTB_CK_DIV4 0x2 #define WWDG_CFR_WDGTB_CK_DIV8 0x3 /* W[6:0]: 7-bit window value */ #define WWDG_CFG_W_LSB 0 #define WWDG_CFG_W (1 << 0) /* --- WWDG_SR values ------------------------------------------------------ */ /* Bits [31:1]: Reserved */ /* EWIF: Early wakeup interrupt flag */ #define WWDG_SR_EWIF (1 << 0) /* --- WWDG function prototypes---------------------------------------------- */ /* TODO */ #endif hackrf-0.0~git20230104.cfc2f34/include/libopencm3/usb/000077500000000000000000000000001435536612600217405ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencm3/usb/cdc.h000066400000000000000000000075031435536612600226470ustar00rootroot00000000000000/** @defgroup usb_cdc_defines USB CDC Type Definitions @brief Defined Constants and Types for the USB CDC Type Definitions @ingroup USB_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef __CDC_H #define __CDC_H /* Definitions of Communications Device Class from * "Universal Serial Bus Class Definitions for Communications Devices * Revision 1.2" */ /* Table 2: Communications Device Class Code */ #define USB_CLASS_CDC 0x02 /* Table 4: Class Subclass Code */ #define USB_CDC_SUBCLASS_DLCM 0x01 #define USB_CDC_SUBCLASS_ACM 0x02 /* ... */ /* Table 5 Communications Interface Class Control Protocol Codes */ #define USB_CDC_PROTOCOL_NONE 0x00 #define USB_CDC_PROTOCOL_AT 0x01 /* ... */ /* Table 6: Data Interface Class Code */ #define USB_CLASS_DATA 0x0A /* Table 12: Type Values for the bDescriptorType Field */ #define CS_INTERFACE 0x24 #define CS_ENDPOINT 0x25 /* Table 13: bDescriptor SubType in Communications Class Functional * Descriptors */ #define USB_CDC_TYPE_HEADER 0x00 #define USB_CDC_TYPE_CALL_MANAGEMENT 0x01 #define USB_CDC_TYPE_ACM 0x02 /* ... */ #define USB_CDC_TYPE_UNION 0x06 /* ... */ /* Table 15: Class-Specific Descriptor Header Format */ struct usb_cdc_header_descriptor { uint8_t bFunctionLength; uint8_t bDescriptorType; uint8_t bDescriptorSubtype; uint16_t bcdCDC; } __attribute__((packed)); /* Table 16: Union Interface Functional Descriptor */ struct usb_cdc_union_descriptor { uint8_t bFunctionLength; uint8_t bDescriptorType; uint8_t bDescriptorSubtype; uint8_t bControlInterface; uint8_t bSubordinateInterface0; /* ... */ } __attribute__((packed)); /* Definitions for Abstract Control Model devices from: * "Universal Serial Bus Communications Class Subclass Specification for * PSTN Devices" */ /* Table 3: Call Management Functional Descriptor */ struct usb_cdc_call_management_descriptor { uint8_t bFunctionLength; uint8_t bDescriptorType; uint8_t bDescriptorSubtype; uint8_t bmCapabilities; uint8_t bDataInterface; } __attribute__((packed)); /* Table 4: Abstract Control Management Functional Descriptor */ struct usb_cdc_acm_descriptor { uint8_t bFunctionLength; uint8_t bDescriptorType; uint8_t bDescriptorSubtype; uint8_t bmCapabilities; } __attribute__((packed)); /* Table 13: Class-Specific Request Codes for PSTN subclasses */ /* ... */ #define USB_CDC_REQ_SET_LINE_CODING 0x20 /* ... */ #define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22 /* ... */ /* Table 17: Line Coding Structure */ struct usb_cdc_line_coding { uint32_t dwDTERate; uint8_t bCharFormat; uint8_t bParityType; uint8_t bDataBits; } __attribute__((packed)); /* Table 30: Class-Specific Notification Codes for PSTN subclasses */ /* ... */ #define USB_CDC_NOTIFY_SERIAL_STATE 0x20 /* ... */ /* Notification Structure */ struct usb_cdc_notification { uint8_t bmRequestType; uint8_t bNotification; uint16_t wValue; uint16_t wIndex; uint16_t wLength; } __attribute__((packed)); #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/usb/dfu.h000066400000000000000000000044241435536612600226730ustar00rootroot00000000000000/** @defgroup usb_dfu_defines USB DFU Type Definitions @brief Defined Constants and Types for the USB DFU Type Definitions @ingroup USB_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef __DFU_H #define __DFU_H enum dfu_req { DFU_DETACH, DFU_DNLOAD, DFU_UPLOAD, DFU_GETSTATUS, DFU_CLRSTATUS, DFU_GETSTATE, DFU_ABORT, }; enum dfu_status { DFU_STATUS_OK, DFU_STATUS_ERR_TARGET, DFU_STATUS_ERR_FILE, DFU_STATUS_ERR_WRITE, DFU_STATUS_ERR_ERASE, DFU_STATUS_ERR_CHECK_ERASED, DFU_STATUS_ERR_PROG, DFU_STATUS_ERR_VERIFY, DFU_STATUS_ERR_ADDRESS, DFU_STATUS_ERR_NOTDONE, DFU_STATUS_ERR_FIRMWARE, DFU_STATUS_ERR_VENDOR, DFU_STATUS_ERR_USBR, DFU_STATUS_ERR_POR, DFU_STATUS_ERR_UNKNOWN, DFU_STATUS_ERR_STALLEDPKT, }; enum dfu_state { STATE_APP_IDLE, STATE_APP_DETACH, STATE_DFU_IDLE, STATE_DFU_DNLOAD_SYNC, STATE_DFU_DNBUSY, STATE_DFU_DNLOAD_IDLE, STATE_DFU_MANIFEST_SYNC, STATE_DFU_MANIFEST, STATE_DFU_MANIFEST_WAIT_RESET, STATE_DFU_UPLOAD_IDLE, STATE_DFU_ERROR, }; #define DFU_FUNCTIONAL 0x21 struct usb_dfu_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint8_t bmAttributes; #define USB_DFU_CAN_DOWNLOAD 0x01 #define USB_DFU_CAN_UPLOAD 0x02 #define USB_DFU_MANIFEST_TOLERANT 0x04 #define USB_DFU_WILL_DETACH 0x08 uint16_t wDetachTimeout; uint16_t wTransferSize; uint16_t bcdDFUVersion; } __attribute__((packed)); #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/usb/doc-usb.h000066400000000000000000000007221435536612600234460ustar00rootroot00000000000000/** @mainpage libopencm3 Generic USB @version 1.0.0 @date 10 March 2013 API documentation for Generic USB. LGPL License Terms @ref lgpl_license */ /** @defgroup USB Generic USB Libraries for Generic USB. @version 1.0.0 @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /** @defgroup USB_defines Generic USB Defines @brief Defined Constants and Types for Generic USB. @version 1.0.0 @date 10 March 2013 LGPL License Terms @ref lgpl_license */ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/usb/hid.h000066400000000000000000000026351435536612600226630ustar00rootroot00000000000000/** @defgroup usb_hid_defines USB HID Type Definitions @brief Defined Constants and Types for the USB HID Type Definitions @ingroup USB_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef __HID_H #define __HID_H #include #define USB_CLASS_HID 3 #define USB_DT_HID 0x21 #define USB_DT_REPORT 0x22 struct usb_hid_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint16_t bcdHID; uint8_t bCountryCode; uint8_t bNumDescriptors; } __attribute__((packed)); #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/usb/usbd.h000066400000000000000000000072331435536612600230530ustar00rootroot00000000000000/** @defgroup usb_driver_defines USB Drivers @brief Defined Constants and Types for the USB Drivers @ingroup USB_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef __USBD_H #define __USBD_H #include BEGIN_DECLS enum usbd_request_return_codes { USBD_REQ_NOTSUPP = 0, USBD_REQ_HANDLED = 1, USBD_REQ_NEXT_CALLBACK = 2, }; typedef struct _usbd_driver usbd_driver; typedef struct _usbd_device usbd_device; extern const usbd_driver stm32f103_usb_driver; extern const usbd_driver stm32f107_usb_driver; extern const usbd_driver stm32f207_usb_driver; #define otgfs_usb_driver stm32f107_usb_driver #define otghs_usb_driver stm32f207_usb_driver /* */ extern usbd_device * usbd_init(const usbd_driver *driver, const struct usb_device_descriptor *dev, const struct usb_config_descriptor *conf, const char **strings, int num_strings, uint8_t *control_buffer, uint16_t control_buffer_size); extern void usbd_register_reset_callback(usbd_device *usbd_dev, void (*callback)(void)); extern void usbd_register_suspend_callback(usbd_device *usbd_dev, void (*callback)(void)); extern void usbd_register_resume_callback(usbd_device *usbd_dev, void (*callback)(void)); extern void usbd_register_sof_callback(usbd_device *usbd_dev, void (*callback)(void)); typedef int (*usbd_control_callback)(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)); /* */ extern int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type, uint8_t type_mask, usbd_control_callback callback); /* */ extern void usbd_register_set_config_callback(usbd_device *usbd_dev, void (*callback)(usbd_device *usbd_dev, uint16_t wValue)); /* Functions to be provided by the hardware abstraction layer */ extern void usbd_poll(usbd_device *usbd_dev); extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected); extern void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*callback)(usbd_device *usbd_dev, uint8_t ep)); extern uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len); extern uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len); extern void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall); extern uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr); extern void usbd_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak); /* Optional */ extern void usbd_cable_connect(usbd_device *usbd_dev, uint8_t on); END_DECLS #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencm3/usb/usbstd.h000066400000000000000000000162101435536612600234150ustar00rootroot00000000000000/** @defgroup usb_type_defines USB Standard Structure Definitions @brief Defined Constants and Types for the USB Standard Structure Definitions @ingroup USB_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 A set of structure definitions for the USB control structures defined in chapter 9 of the "Univeral Serial Bus Specification Revision 2.0" Available from the USB Implementers Forum - http://www.usb.org/ LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef __USBSTD_H #define __USBSTD_H #include #include /* * This file contains structure definitions for the USB control structures * defined in chapter 9 of the "Univeral Serial Bus Specification Revision 2.0" * Available from the USB Implementers Forum - http://www.usb.org/ */ /* USB Setup Data structure - Table 9-2 */ struct usb_setup_data { uint8_t bmRequestType; uint8_t bRequest; uint16_t wValue; uint16_t wIndex; uint16_t wLength; } __attribute__((packed)); /* Class Definition */ #define USB_CLASS_VENDOR 0xFF /* bmRequestType bit definitions */ #define USB_REQ_TYPE_IN 0x80 #define USB_REQ_TYPE_STANDARD 0x00 #define USB_REQ_TYPE_CLASS 0x20 #define USB_REQ_TYPE_VENDOR 0x40 #define USB_REQ_TYPE_DEVICE 0x00 #define USB_REQ_TYPE_INTERFACE 0x01 #define USB_REQ_TYPE_ENDPOINT 0x02 #define USB_REQ_TYPE_DIRECTION 0x80 #define USB_REQ_TYPE_TYPE 0x60 #define USB_REQ_TYPE_RECIPIENT 0x1F /* USB Standard Request Codes - Table 9-4 */ #define USB_REQ_GET_STATUS 0 #define USB_REQ_CLEAR_FEATURE 1 /* Reserved for future use: 2 */ #define USB_REQ_SET_FEATURE 3 /* Reserved for future use: 3 */ #define USB_REQ_SET_ADDRESS 5 #define USB_REQ_GET_DESCRIPTOR 6 #define USB_REQ_SET_DESCRIPTOR 7 #define USB_REQ_GET_CONFIGURATION 8 #define USB_REQ_SET_CONFIGURATION 9 #define USB_REQ_GET_INTERFACE 10 #define USB_REQ_SET_INTERFACE 11 #define USB_REQ_SET_SYNCH_FRAME 12 /* USB Descriptor Types - Table 9-5 */ #define USB_DT_DEVICE 1 #define USB_DT_CONFIGURATION 2 #define USB_DT_STRING 3 #define USB_DT_INTERFACE 4 #define USB_DT_ENDPOINT 5 #define USB_DT_DEVICE_QUALIFIER 6 #define USB_DT_OTHER_SPEED_CONFIGURATION 7 #define USB_DT_INTERFACE_POWER 8 /* From ECNs */ #define USB_DT_OTG 9 #define USB_DT_DEBUG 10 #define USB_DT_INTERFACE_ASSOCIATION 11 /* USB Standard Feature Selectors - Table 9-6 */ #define USB_FEAT_ENDPOINT_HALT 0 #define USB_FEAT_DEVICE_REMOTE_WAKEUP 1 #define USB_FEAT_TEST_MODE 2 /* Information Returned by a GetStatus() Request to a Device - Figure 9-4 */ #define USB_DEV_STATUS_SELF_POWERED 0x01 #define USB_DEV_STATUS_REMOTE_WAKEUP 0x02 /* USB Standard Device Descriptor - Table 9-8 */ struct usb_device_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint16_t bcdUSB; uint8_t bDeviceClass; uint8_t bDeviceSubClass; uint8_t bDeviceProtocol; uint8_t bMaxPacketSize0; uint16_t idVendor; uint16_t idProduct; uint16_t bcdDevice; uint8_t iManufacturer; uint8_t iProduct; uint8_t iSerialNumber; uint8_t bNumConfigurations; } __attribute__((packed)); #define USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor) /* USB Device_Qualifier Descriptor - Table 9-9 * Not used in this implementation. */ struct usb_device_qualifier_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint16_t bcdUSB; uint8_t bDeviceClass; uint8_t bDeviceSubClass; uint8_t bDeviceProtocol; uint8_t bMaxPacketSize0; uint8_t bNumConfigurations; uint8_t bReserved; } __attribute__((packed)); /* USB Standard Configuration Descriptor - Table 9-10 */ struct usb_config_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint16_t wTotalLength; uint8_t bNumInterfaces; uint8_t bConfigurationValue; uint8_t iConfiguration; uint8_t bmAttributes; uint8_t bMaxPower; /* Descriptor ends here. The following are used internally: */ const struct usb_interface { int num_altsetting; const struct usb_iface_assoc_descriptor *iface_assoc; const struct usb_interface_descriptor *altsetting; } *interface; } __attribute__((packed)); #define USB_DT_CONFIGURATION_SIZE 9 /* USB Configuration Descriptor bmAttributes bit definitions */ #define USB_CONFIG_ATTR_SELF_POWERED 0x40 #define USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20 /* Other Speed Configuration is the same as Configuration Descriptor. * - Table 9-11 */ /* USB Standard Interface Descriptor - Table 9-12 */ struct usb_interface_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint8_t bInterfaceNumber; uint8_t bAlternateSetting; uint8_t bNumEndpoints; uint8_t bInterfaceClass; uint8_t bInterfaceSubClass; uint8_t bInterfaceProtocol; uint8_t iInterface; /* Descriptor ends here. The following are used internally: */ const struct usb_endpoint_descriptor *endpoint; const void *extra; int extralen; } __attribute__((packed)); #define USB_DT_INTERFACE_SIZE 9 /* USB Standard Endpoint Descriptor - Table 9-13 */ struct usb_endpoint_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint8_t bEndpointAddress; uint8_t bmAttributes; uint16_t wMaxPacketSize; uint8_t bInterval; } __attribute__((packed)); #define USB_DT_ENDPOINT_SIZE sizeof(struct usb_endpoint_descriptor) /* USB Endpoint Descriptor bmAttributes bit definitions */ #define USB_ENDPOINT_ATTR_CONTROL 0x00 #define USB_ENDPOINT_ATTR_ISOCHRONOUS 0x01 #define USB_ENDPOINT_ATTR_BULK 0x02 #define USB_ENDPOINT_ATTR_INTERRUPT 0x03 #define USB_ENDPOINT_ATTR_NOSYNC 0x00 #define USB_ENDPOINT_ATTR_ASYNC 0x04 #define USB_ENDPOINT_ATTR_ADAPTIVE 0x08 #define USB_ENDPOINT_ATTR_SYNC 0x0C #define USB_ENDPOINT_ATTR_DATA 0x00 #define USB_ENDPOINT_ATTR_FEEDBACK 0x10 #define USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA 0x20 /* Table 9-15 specifies String Descriptor Zero. * Table 9-16 specified UNICODE String Descriptor. */ struct usb_string_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint16_t wData[]; } __attribute__((packed)); /* From ECN: Interface Association Descriptors, Table 9-Z */ struct usb_iface_assoc_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint8_t bFirstInterface; uint8_t bInterfaceCount; uint8_t bFunctionClass; uint8_t bFunctionSubClass; uint8_t bFunctionProtocol; uint8_t iFunction; } __attribute__((packed)); #define USB_DT_INTERFACE_ASSOCIATION_SIZE \ sizeof(struct usb_iface_assoc_descriptor) enum usb_language_id { USB_LANGID_ENGLISH_US = 0x409, }; #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/include/libopencmsis/000077500000000000000000000000001435536612600216035ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencmsis/core_cm3.h000066400000000000000000000120171435536612600234470ustar00rootroot00000000000000/* big fat FIXME: this should use a consistent structure, and reference * functionality from libopencm3 instead of copypasting. * * particularly unimplemented features are FIXME'd extra * */ /* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant * of the symbols efm32lib needs of CMSIS. */ #ifndef OPENCMSIS_CORECM3_H #define OPENCMSIS_CORECM3_H #include #include #include #include #include /* needed by system_efm32.h:196, guessing */ #define __INLINE inline /* new since emlib 3.0 */ #define __STATIC_INLINE static inline /* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the * libopencm3 ones, "volatile" is all that's missing. */ #define __IO volatile #define __O volatile #define __I volatile /* -> style access for what is defined in libopencm3/stm32/f1/scb.h / * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */ /* from cm3/scb.h */ #define SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPDEEP /* structure as in, for example, * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from * libopencm3/cm3/scb.h. FIXME incomplete. */ typedef struct { __IO uint32_t CPUID; __IO uint32_t ICSR; __IO uint32_t VTOR; __IO uint32_t AIRCR; __IO uint32_t SCR; __IO uint32_t CCR; __IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */ __IO uint32_t SHCSR; } SCB_TypeDef; #define SCB ((SCB_TypeDef *) SCB_BASE) /* needed by efm32_emu.h, guessing and taking the implementation used in * lightswitch-interrupt.c */ #define __WFI() __asm__("wfi") /* needed by efm32_cmu.h, probably it's just what gcc provides anyway */ #define __CLZ(div) __builtin_clz(div) /* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev * instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */ #define __REV(x) __builtin_bswap32(x) /* stubs for efm32_dbg.h */ typedef struct { uint32_t DHCSR; uint32_t DEMCR; /* needed by efm32tg stk trace.c */ } CoreDebug_TypeDef; /* FIXME let's just hope writes to flash are protected */ #define CoreDebug ((CoreDebug_TypeDef *) 0) #define CoreDebug_DHCSR_C_DEBUGEN_Msk 0 #define CoreDebug_DEMCR_TRCENA_Msk 0 /* stubs for efm32_dma */ static inline void NVIC_ClearPendingIRQ(uint8_t irqn) { nvic_clear_pending_irq(irqn); } static inline void NVIC_EnableIRQ(uint8_t irqn) { nvic_enable_irq(irqn); } static inline void NVIC_DisableIRQ(uint8_t irqn) { nvic_disable_irq(irqn); } /* stubs for efm32_int. FIXME: how do they do that? nvic documentation in the * efm32 core manual doesn't tell anything of a global on/off switch */ #define __enable_irq() 1 #define __disable_irq() 1 /* stubs for efm32_mpu FIXME */ #define SCB_SHCSR_MEMFAULTENA_Msk 0 typedef struct { uint32_t CTRL; uint32_t RNR; uint32_t RBAR; uint32_t RASR; } MPU_TypeDef; /* FIXME struct at NULL */ #define MPU ((MPU_TypeDef *) 0) #define MPU_CTRL_ENABLE_Msk 0 #define MPU_RASR_XN_Pos 0 #define MPU_RASR_AP_Pos 0 #define MPU_RASR_TEX_Pos 0 #define MPU_RASR_S_Pos 0 #define MPU_RASR_C_Pos 0 #define MPU_RASR_B_Pos 0 #define MPU_RASR_SRD_Pos 0 #define MPU_RASR_SIZE_Pos 0 #define MPU_RASR_ENABLE_Pos 0 /* required for the blink example */ /* if if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) while (1) ; * configures the sys ticks to 1ms, then the argument to SysTick_Config * describes how many cycles to wait between two systicks. * * the endless loop part looks like an "if it returns an error condition, * rather loop here than continue"; every other solution would involve things * that are dark magic to my understanding. * * implementation more or less copypasted from lib/stm32/systick.c, FIXME until * the generic cm3 functionality is moved out from stm32 and can be used here * easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable * and systick_set_clocksource). * * modified for CMSIS style array as the powertest example needs it. * */ /* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */ typedef struct { uint32_t CTRL; uint32_t LOAD; uint32_t VAL; uint32_t CALIB; } SysTick_TypeDef; #define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE) static inline uint32_t SysTick_Config(uint32_t n_ticks) { /* constant from systick_set_reload -- as this returns something that's * not void, this is the only possible error condition */ if (n_ticks & ~0x00FFFFFF) { return 1; } systick_set_reload(n_ticks); systick_set_clocksource(true); systick_interrupt_enable(); systick_counter_enable(); return 0; } /* stubs for efm32tg stk trace.c */ typedef struct { uint32_t LAR; uint32_t TCR; } ITM_TypeDef; /* FIXME struct at NULL */ #define ITM ((ITM_TypeDef *) 0) /* blink.h expects the isr for systicks to be named SysTick_Handler. with this, * its Systick_Handler function gets renamed to the weak symbol exported by * vector.c */ #define SysTick_Handler sys_tick_handler /* FIXME: this needs to be done for all of the 14 hard vectors */ #include #endif hackrf-0.0~git20230104.cfc2f34/include/libopencmsis/dispatch/000077500000000000000000000000001435536612600234025ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/include/libopencmsis/dispatch/irqhandlers.h000066400000000000000000000012321435536612600260650ustar00rootroot00000000000000#if defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F4) # include #elif defined(EFM32TG) # include #elif defined(EFM32G) # include #elif defined(EFM32LG) # include #elif defined(EFM32GG) # include #elif defined(LPC43XX) # include #else # warning"no chipset defined; user interrupts are not redirected" #endif hackrf-0.0~git20230104.cfc2f34/ld/000077500000000000000000000000001435536612600160705ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/ld/devices.data000066400000000000000000000303501435536612600203460ustar00rootroot00000000000000################################################################################ # # Device chip tree definition file. # # Copyright (c) 2013 Frantisek Burian # Copyright (C) 2013 Werner Almesberger # # Line description: # ( ...) # # : is the pattern for the chip description to be searched for. # The case of the pattern string is ignored. # Pattern match symbols: # ? - matches exactly one character # * - matches none or more characters # + - matches single or more characters # # : is the parent group name, where the search will continue. # There are special parents names that controls traversing: # "END" - Exit traversal. # "+" - Don't change the parent. Use for split long line to two. # # : space-separated list of preprocessor symbols supplied to the linker. # -D option name is automatically prepended to each symbol definition # # All lines starting with # symbol are treated as Comments # # Recommended tree hierarchy: # # # +- # +- # +- END # # You can split the long line into two or more by using "+" in the parent field, # and defining same regex with appropriate parent on the next line. Example: # # device + PARAM1=aaa PARAM2=bbbb PARAM3=ccc PARAM4=dddd PARAM5=eeee # device parent PARAM6=ffff PARAM7=gggg PARAM8=hhhh # parent END # # The order of the lines is important. After the regex match, its parent will # be used for match on the next line. If two regexp lines matches input, only # the first will be evaluated, except special group definition "+" # # The regex matches entire sym ################################################################################ # the STM32 chips stm32f05[01]?4* stm32f0 ROM=16K RAM=4K stm32f05[01]?6* stm32f0 ROM=32K RAM=4K stm32f051?8* stm32f0 ROM=64K RAM=8K stm32f10[012]?4* stm32f1 ROM=16K RAM=4K stm32f103?4* stm32f1 ROM=16K RAM=6K stm32f100?6* stm32f1 ROM=32K RAM=4K stm32f103?6* stm32f1 ROM=32K RAM=10K stm32f10[12]?6* stm32f1 ROM=32K RAM=6K stm32f100?8* stm32f1 ROM=64K RAM=8K stm32f10[12]?8* stm32f1 ROM=64K RAM=10K stm32f103?8* stm32f1 ROM=64K RAM=20K stm32f100?b* stm32f1 ROM=128K RAM=8K stm32f10[12]?b* stm32f1 ROM=128K RAM=16K stm32f103?b* stm32f1 ROM=128K RAM=20K stm32f10[57]?b* stm32f1 ROM=128K RAM=64K stm32f100?c* stm32f1 ROM=256K RAM=24K stm32f101?c* stm32f1 ROM=256K RAM=32K stm32f103?c* stm32f1 ROM=256K RAM=48K stm32f10[57]?c* stm32f1 ROM=256K RAM=64K stm32f100?d* stm32f1 ROM=384K RAM=32K stm32f101?d* stm32f1 ROM=384K RAM=48K stm32f103?d* stm32f1 ROM=384K RAM=64K stm32f100?e* stm32f1 ROM=512K RAM=32K stm32f101?e* stm32f1 ROM=512K RAM=48K stm32f103?e* stm32f1 ROM=512K RAM=64K stm32f100?f* stm32f1 ROM=768K RAM=80K stm32f103?f* stm32f1 ROM=768K RAM=96K stm32f100?g* stm32f1 ROM=1024K RAM=80K stm32f103?g* stm32f1 ROM=1024K RAM=96K stm32f205?b* stm32f2 ROM=128K RAM=64K stm32f205?c* stm32f2 ROM=256K RAM=96K stm32f207?c* stm32f2 ROM=256K RAM=128K stm32f2[01][57]?e* stm32f2 ROM=512K RAM=128K stm32f20[57]?f* stm32f2 ROM=768K RAM=128K stm32f2[01][57]?g* stm32f2 ROM=1024K RAM=128K stm32f302?b* stm32f3ccm ROM=128K RAM=24K CCM=8K stm32f302?c* stm32f3ccm ROM=256K RAM=32K CCM=8K stm32f303?b* stm32f3ccm ROM=128K RAM=40K CCM=8K stm32f3[01]3?c* stm32f3ccm ROM=256K RAM=48K CCM=8K stm32f373?8* stm32f3 ROM=64K RAM=16K stm32f373?b* stm32f3 ROM=128K RAM=24K stm32f3[78]3?8* stm32f3 ROM=256K RAM=32K stm32f401?b* stm32f4 ROM=128K RAM=64K stm32f401?c* stm32f4 ROM=256K RAM=64K stm32f4[01][57]?e* stm32f4ccm ROM=512K RAM=128K CCM=64K stm32f4[01][57]?g* stm32f4ccm ROM=1024K RAM=128K CCM=64K stm32f4[23][79]?g* stm32f4ccm ROM=1024K RAM=192K CCM=64K stm32f4[23][79]?i* stm32f4ccm ROM=2048K RAM=192K CCM=64K stm32l100?6* stm32l1 ROM=32K RAM=4K stm32l100?8* stm32l1 ROM=64K RAM=8K stm32l100?b* stm32l1 ROM=128K RAM=10K stm32l15[12]?6* stm32l1eep ROM=32K RAM=10K EEP=4K stm32l15[12]?8* stm32l1eep ROM=64K RAM=10K EEP=4K stm32l15[12]?b* stm32l1eep ROM=128K RAM=16K EEP=4K stm32l15[12]?c* stm32l1eep ROM=256K RAM=32K EEP=8K stm32l15[12]?d* stm32l1eep ROM=384K RAM=48K EEP=12K stm32ts60 stm32t ROM=32K RAM=10K stm32w108c8 stm32w ROM=64K RAM=8K stm32w108?b stm32w ROM=128K RAM=8K stm32w108cz stm32w ROM=192K RAM=12K stm32w108cc stm32w ROM=256K RAM=16K ################################################################################ # the SAM3 chips sam3a4* sam3a ROM=256K RAM=64K sam3a8* sam3a ROM=512K RAM=96K sam3n00* sam3n ROM=16K RAM=4K sam3n0* sam3n ROM=32K RAM=8K sam3n1* sam3n ROM=64K RAM=8K sam3n2* sam3n ROM=128K RAM=16K sam3n4* sam3n ROM=256K RAM=24K sam3s1* sam3s ROM=64K RAM=16K sam3s2* sam3s ROM=128K RAM=32K sam3s4* sam3s ROM=256K RAM=48K sam3u1* sam3u ROM=64K RAM=20K sam3u2* sam3u ROM=128K RAM=36K sam3u4* sam3u ROM=256K RAM=52K sam3x4* sam3x ROM=256K RAM=64K sam3x8* sam3x ROM=512K RAM=96K ################################################################################ # the lpc chips lpc1311* lpc13 ROM=8K RAM=4K lpc1313* lpc13 ROM=32K RAM=8K lpc1342* lpc13 ROM=16K RAM=4K lpc1343* lpc13 ROM=32K RAM=8K lpc1315* lpc13u ROM=32K RAM=8K lpc1316* lpc13u ROM=48K RAM=8K lpc1317* lpc13u ROM=64K RAM=8K RAM1=2K lpc1345* lpc13u ROM=32K RAM=8K USBRAM=2K lpc1346* lpc13u ROM=48K RAM=8K USBRAM=2K lpc1346* lpc13u ROM=64K RAM=8K USBRAM=2K RAM1=2K lpc1751* lpc175x ROM=32K RAM=8K lpc1752* lpc175x ROM=64K RAM=16K lpc1754* lpc175x ROM=128K RAM=16K RAM1=16K lpc1756* lpc175x ROM=256K RAM=16K RAM1=16K lpc1758* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K lpc1759* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K lpc1763* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K lpc1764* lpc176x ROM=128K RAM=16K RAM1=16K lpc1765* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K lpc1766* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K lpc1767* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K lpc1768* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K lpc1769* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K lpc1774* lpc177x ROM=128K RAM=32K RAM1=8K lpc1776* lpc177x ROM=256K RAM=64K RAM1=16K lpc1777* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K lpc1778* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K lpc1785* lpc178x ROM=256K RAM=64K RAM1=16K lpc1786* lpc178x ROM=256K RAM=64K RAM1=16K lpc1787* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K lpc1788* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K ################################################################################ # the efm32 chips # Zero Gecko efm32zg???f4 efm32zg ROM=4K RAM=2K efm32zg???f8 efm32zg ROM=8K RAM=2K efm32zg???f16 efm32zg ROM=16K RAM=4K efm32zg???f32 efm32zg ROM=32K RAM=4K # Tiny Gecko efm32tg108f4 efm32tg ROM=4K RAM=1K efm32tg110f4 efm32tg ROM=4K RAM=2K efm32tg???f8 efm32tg ROM=8K RAM=2K efm32tg???f16 efm32tg ROM=16K RAM=4K efm32tg???f32 efm32tg ROM=32K RAM=4K # Gecko efm32g200f16 efm32g ROM=16K RAM=8K efm32g???f32 efm32g ROM=32K RAM=8K efm32g???f64 efm32g ROM=64K RAM=16K efm32g???f128 efm32g ROM=128K RAM=16K # Large Gecko efm32lg???f64 efm32lg ROM=64K RAM=32K efm32lg???f128 efm32lg ROM=128K RAM=32K efm32lg???f256 efm32lg ROM=256K RAM=32K # Giant Gecko efm32gg???f512 efm32gg ROM=512K RAM=128K efm32gg???f1024 efm32gg ROM=1024K RAM=128K # Wonder Gecko efm32wg???f64 efm32gg ROM=64K RAM=32K efm32wg???f128 efm32gg ROM=128K RAM=32K efm32wg???f256 efm32gg ROM=256K RAM=32K ################################################################################ # the TI cortex M3 chips lm3s101 lm3sandstorm ROM=8K RAM=2K lm3s102 lm3sandstorm ROM=8K RAM=2K lm3s300 lm3sandstorm ROM=16K RAM=4K lm3s301 lm3sandstorm ROM=16K RAM=2K lm3s308 lm3sandstorm ROM=16K RAM=4K lm3s310 lm3sandstorm ROM=16K RAM=4K lm3s315 lm3sandstorm ROM=16K RAM=4K lm3s316 lm3sandstorm ROM=16K RAM=4K lm3s317 lm3sandstorm ROM=16K RAM=4K lm3s328 lm3sandstorm ROM=16K RAM=4K lm3s600 lm3sandstorm ROM=32K RAM=8K lm3s601 lm3sandstorm ROM=32K RAM=8K lm3s608 lm3sandstorm ROM=32K RAM=8K lm3s610 lm3sandstorm ROM=32K RAM=8K lm3s611 lm3sandstorm ROM=32K RAM=8K lm3s612 lm3sandstorm ROM=32K RAM=8K lm3s613 lm3sandstorm ROM=32K RAM=8K lm3s615 lm3sandstorm ROM=32K RAM=8K lm3s617 lm3sandstorm ROM=32K RAM=8K lm3s618 lm3sandstorm ROM=32K RAM=8K lm3s628 lm3sandstorm ROM=32K RAM=8K lm3s800 lm3sandstorm ROM=64K RAM=8K lm3s801 lm3sandstorm ROM=64K RAM=8K lm3s808 lm3sandstorm ROM=64K RAM=8K lm3s811 lm3sandstorm ROM=64K RAM=8K lm3s812 lm3sandstorm ROM=64K RAM=8K lm3s815 lm3sandstorm ROM=64K RAM=8K lm3s817 lm3sandstorm ROM=64K RAM=8K lm3s818 lm3sandstorm ROM=64K RAM=8K lm3s828 lm3sandstorm ROM=64K RAM=8K lm3s1110 lm3fury ROM=64K RAM=16K lm3s1133 lm3fury ROM=64K RAM=16K lm3s1138 lm3fury ROM=64K RAM=16K lm3s1150 lm3fury ROM=64K RAM=16K lm3s1162 lm3fury ROM=64K RAM=16K lm3s1165 lm3fury ROM=64K RAM=16K lm3s1332 lm3fury ROM=96K RAM=16K lm3s1435 lm3fury ROM=96K RAM=32K lm3s1439 lm3fury ROM=96K RAM=32K lm3s1512 lm3fury ROM=96K RAM=64K lm3s1538 lm3fury ROM=96K RAM=64K lm3s1601 lm3fury ROM=128K RAM=32K lm3s1607 lm3fury ROM=128K RAM=32K lm3s1608 lm3fury ROM=128K RAM=32K lm3s1620 lm3fury ROM=128K RAM=32K lm3s8962 lm3fury ROM=256K RAM=64K ################################################################################ # the TI cortex R4F chips rm46l852* rm46l ROM=1280K RAM=192K ################################################################################ ################################################################################ ################################################################################ # the STM32 family groups stm32f3ccm stm32f3 CCM_OFF=0x10000000 stm32f4ccm stm32f4 CCM_OFF=0x10000000 stm32l1eep stm32l1 EEP_OFF=0x08080000 ################################################################################ # the lpc family groups lpc13u lpc13 USBRAM_OFF=0x20004000 lpc17[56]x lpc17 RAM1_OFF=0x2007C000 RAM2_OFF=0x20080000 lpc17[78]x lpc17 RAM1_OFF=0x20000000 RAM2_OFF=0x20040000 ################################################################################ ################################################################################ ################################################################################ # the STM32 families stm32f0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 stm32f1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 stm32f2 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 stm32f3 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 stm32f4 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 stm32l1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 stm32w stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 stm32t stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 ################################################################################ # the SAM3 families sam3a sam3 ROM_OFF=0x00800000 RAM_OFF=0x20000000 sam3n sam3 ROM_OFF=0x00400000 RAM_OFF=0x20000000 sam3s sam3 ROM_OFF=0x00400000 RAM_OFF=0x20000000 sam3u sam3 ROM_OFF=0x00080000 RAM_OFF=0x20000000 sam3x sam3 ROM_OFF=0x00800000 RAM_OFF=0x20000000 ################################################################################ # the lpc families lpc13 lpc ROM_OFF=0x00000000 RAM_OFF=0x10000000 RAM1_OFF=0x20000000 lpc17 lpc ROM_OFF=0x00000000 RAM_OFF=0x10000000 ################################################################################ # the efm32 Gecko families efm32zg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 efm32tg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 efm32g efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 efm32lg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 efm32gg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 efm32wg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000 ################################################################################ # Cortex LM3 families lm3fury lm3 ROM_OFF=0x00000000 RAM_OFF=0x20000000 lm3sandstorm lm3 ROM_OFF=0x00000000 RAM_OFF=0x20000000 ################################################################################ # Cortex R4F families rm46l rm4 ROM_OFF=0x00000000 RAM_OFF=0x08000000 RAM1_OFF=0x08400000 ################################################################################ ################################################################################ ################################################################################ # the architectures stm32 END sam3 END lpc END efm32 END lm3 END rm4 END hackrf-0.0~git20230104.cfc2f34/lib/000077500000000000000000000000001435536612600162375ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/Makefile.include000066400000000000000000000031311435536612600213170ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 Piotr Esden-Tempski ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) Q := @ endif # common objects OBJS += vector.o systick.o scb.o nvic.o assert.o sync.o all: $(SRCLIBDIR)/$(LIBNAME).a $(SRCLIBDIR)/$(LIBNAME).a: $(SRCLIBDIR)/$(LIBNAME).ld $(OBJS) @printf " AR $(@F)\n" $(Q)$(AR) $(ARFLAGS) $@ $(OBJS) $(SRCLIBDIR)/$(LIBNAME).ld: $(LIBNAME).ld @printf " CP $(@F)\n" $(Q)cp $^ $@ $(Q)if [ -f $(LIBNAME)_rom_to_ram.ld ]; then cp $(LIBNAME)_rom_to_ram.ld $(SRCLIBDIR); fi %.o: %.c @printf " CC $( * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void __attribute__((weak)) cm3_assert_failed(void) { while (1); } void __attribute__((weak)) cm3_assert_failed_verbose( const char *file __attribute__((unused)), int line __attribute__((unused)), const char *func __attribute__((unused)), const char *assert_expr __attribute__((unused))) { cm3_assert_failed(); } hackrf-0.0~git20230104.cfc2f34/lib/cm3/nvic.c000066400000000000000000000137631435536612600200360ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Fergus Noble * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @defgroup CM3_nvic_file NVIC * * @ingroup CM3_files * * @brief libopencm3 Cortex Nested Vectored Interrupt Controller * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2010 Thomas Otto * @author @htmlonly © @endhtmlonly 2012 Fergus Noble * * * @date 18 August 2012 * * Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults, * systicks etc.) and varying numbers of implementation defined interrupts * (typically peripherial interrupts and DMA). * * @see Cortex-M3 Devices Generic User Guide * @see STM32F10xxx Cortex-M3 programming manual * * LGPL License Terms @ref lgpl_license */ /**@{*/ #include #include /*---------------------------------------------------------------------------*/ /** @brief NVIC Enable Interrupt * * Enables a user interrupt. * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint */ void nvic_enable_irq(uint8_t irqn) { NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); } /*---------------------------------------------------------------------------*/ /** @brief NVIC Disable Interrupt * * Disables a user interrupt. * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint */ void nvic_disable_irq(uint8_t irqn) { NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); } /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Pending Interrupt * * True if the interrupt has occurred and is waiting for service. * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint * @return Boolean. Interrupt pending. */ uint8_t nvic_get_pending_irq(uint8_t irqn) { return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; } /*---------------------------------------------------------------------------*/ /** @brief NVIC Set Pending Interrupt * * Force a user interrupt to a pending state. This has no effect if the * interrupt is already pending. * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint */ void nvic_set_pending_irq(uint8_t irqn) { NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); } /*---------------------------------------------------------------------------*/ /** @brief NVIC Clear Pending Interrupt * * Force remove a user interrupt from a pending state. This has no effect if * the interrupt is actively being serviced. * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint */ void nvic_clear_pending_irq(uint8_t irqn) { NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); } /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Enabled Interrupt * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint * @return Boolean. Interrupt enabled. */ uint8_t nvic_get_irq_enabled(uint8_t irqn) { return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; } /*---------------------------------------------------------------------------*/ /** @brief NVIC Set Interrupt Priority * * CM3, CM4: * * There are 16 priority levels only, given by the upper four bits of the * priority byte, as required by ARM standards. The priority levels are * interpreted according to the pre-emptive priority grouping set in the * SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done * in @ref scb_set_priority_grouping. * * CM0: * * There are 4 priority levels only, given by the upper two bits of the * priority byte, as required by ARM standards. No grouping available. * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint * @param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of * 16) */ void nvic_set_priority(uint8_t irqn, uint8_t priority) { /* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the * negative interrupt numbers assigned to the system interrupts. better * handling would mean signed integers. */ if (irqn >= NVIC_IRQ_COUNT) { /* Cortex-M system interrupts */ SCS_SHPR((irqn & 0xF) - 4) = priority; } else { /* Device specific interrupts */ NVIC_IPR(irqn) = priority; } } /* Those are defined only on CM3 or CM4 */ #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Active Interrupt * * Interrupt has occurred and is currently being serviced. * * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint * @return Boolean. Interrupt active. */ uint8_t nvic_get_active_irq(uint8_t irqn) { return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; } /*---------------------------------------------------------------------------*/ /** @brief NVIC Software Trigger Interrupt * * Generate an interrupt from software. This has no effect for unprivileged * access unless the privilege level has been elevated through the System * Control Registers. * * @param[in] irqn Unsigned int16. Interrupt number (0 ... 239) */ void nvic_generate_software_interrupt(uint16_t irqn) { if (irqn <= 239) { NVIC_STIR |= irqn; } } #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/cm3/scb.c000066400000000000000000000025231435536612600176360ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /* Those are defined only on CM3 or CM4 */ #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) void scb_reset_core(void) { SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; while (1); } #endif void scb_reset_system(void) { SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; while (1); } /* Those are defined only on CM3 or CM4 */ #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) void scb_set_priority_grouping(uint32_t prigroup) { SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; } #endif hackrf-0.0~git20230104.cfc2f34/lib/cm3/sync.c000066400000000000000000000034631435536612600200470ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /* DMB is supported on CM0 */ void __dmb() { __asm__ volatile ("dmb"); } /* Those are defined only on CM3 or CM4 */ #if defined(__ARM_ARCH_6M__) #warning "sync not supported on ARMv6-M arch" #else uint32_t __ldrex(volatile uint32_t *addr) { uint32_t res; __asm__ volatile ("ldrex %0, [%1]" : "=r" (res) : "r" (addr)); return res; } uint32_t __strex(uint32_t val, volatile uint32_t *addr) { uint32_t res; __asm__ volatile ("strex %0, %2, [%1]" : "=&r" (res) : "r" (addr), "r" (val)); return res; } void mutex_lock(mutex_t *m) { uint32_t status = 0; do { /* Wait until the mutex is unlocked. */ while (__ldrex(m) != MUTEX_UNLOCKED); /* Try to acquire it. */ status = __strex(MUTEX_LOCKED, m); /* Did we get it? If not then try again. */ } while (status != 0); /* Execute the mysterious Data Memory Barrier instruction! */ __dmb(); } void mutex_unlock(mutex_t *m) { /* Ensure accesses to protected resource are finished */ __dmb(); /* Free the lock. */ *m = MUTEX_UNLOCKED; } #endif hackrf-0.0~git20230104.cfc2f34/lib/cm3/systick.c000066400000000000000000000100161435536612600205540ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @defgroup CM3_systick_file SysTick * * @ingroup CM3_files * * @brief libopencm3 Cortex System Tick Timer * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2010 Thomas Otto * * @date 19 August 2012 * * This library supports the System Tick timer in ARM Cortex Microcontrollers. * * The System Tick timer is part of the ARM Cortex core. It is a 24 bit * down counter that can be configured with an automatical reload value. * * LGPL License Terms @ref lgpl_license */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief SysTick Set the Automatic Reload Value. * * The counter is set to the reload value when the counter starts and after it * reaches zero. * * @param[in] value uint32_t. 24 bit reload value. */ void systick_set_reload(uint32_t value) { STK_RVR = (value & STK_RVR_RELOAD); } /*---------------------------------------------------------------------------*/ /** @brief SysTick Read the Automatic Reload Value. * * @returns 24 bit reload value as uint32_t. */ uint32_t systick_get_reload(void) { return STK_RVR & STK_RVR_RELOAD; } /*---------------------------------------------------------------------------*/ /** @brief Get the current SysTick counter value. * * @returns 24 bit current value as uint32_t. */ uint32_t systick_get_value(void) { return STK_CVR & STK_CVR_CURRENT; } /*---------------------------------------------------------------------------*/ /** @brief Set the SysTick Clock Source. * * The clock source can be either the AHB clock or the same clock divided by 8. * * @param[in] clocksource uint8_t. Clock source from @ref systick_clksource. */ void systick_set_clocksource(uint8_t clocksource) { STK_CSR = (STK_CSR & (~STK_CSR_CLKSOURCE)) | (clocksource << STK_CSR_CLKSOURCE_LSB); } /*---------------------------------------------------------------------------*/ /** @brief Enable SysTick Interrupt. * */ void systick_interrupt_enable(void) { STK_CSR |= STK_CSR_TICKINT; } /*---------------------------------------------------------------------------*/ /** @brief Disable SysTick Interrupt. * */ void systick_interrupt_disable(void) { STK_CSR &= ~STK_CSR_TICKINT; } /*---------------------------------------------------------------------------*/ /** @brief Enable SysTick Counter. * */ void systick_counter_enable(void) { STK_CSR |= STK_CSR_ENABLE; } /*---------------------------------------------------------------------------*/ /** @brief Disable SysTick Counter. * */ void systick_counter_disable(void) { STK_CSR &= ~STK_CSR_ENABLE; } /*---------------------------------------------------------------------------*/ /** @brief SysTick Read the Counter Flag. * * The count flag is set when the timer count becomes zero, and is cleared when * the flag is read. * * @returns Boolean if flag set. */ uint8_t systick_get_countflag(void) { return (STK_CSR & STK_CSR_COUNTFLAG) ? 1 : 0; } /*---------------------------------------------------------------------------*/ /** @brief SysTick Get Calibration Value * * @returns Current calibration value */ uint32_t systick_get_calib(void) { return STK_CALIB & STK_CALIB_TENMS; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/cm3/vector.c000066400000000000000000000063601435536612600203740ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski , * Copyright (C) 2012 chrysn * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /* load optional platform dependent initialization routines */ #include "../dispatch/vector_chipset.c" /* load the weak symbols for IRQ_HANDLERS */ #include "../dispatch/vector_nvic.c" /* Symbols exported by the linker script(s): */ extern unsigned _data_loadaddr, _data, _edata, _bss, _ebss, _stack; typedef void (*funcp_t) (void); extern funcp_t __preinit_array_start, __preinit_array_end; extern funcp_t __init_array_start, __init_array_end; extern funcp_t __fini_array_start, __fini_array_end; void main(void); void blocking_handler(void); void null_handler(void); __attribute__ ((section(".vectors"))) vector_table_t vector_table = { .initial_sp_value = &_stack, .reset = reset_handler, .nmi = nmi_handler, .hard_fault = hard_fault_handler, /* Those are defined only on CM3 or CM4 */ #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) .memory_manage_fault = mem_manage_handler, .bus_fault = bus_fault_handler, .usage_fault = usage_fault_handler, .debug_monitor = debug_monitor_handler, #endif .sv_call = sv_call_handler, .pend_sv = pend_sv_handler, .systick = sys_tick_handler, .irq = { IRQ_HANDLERS } }; void WEAK __attribute__ ((naked)) reset_handler(void) { volatile unsigned *src, *dest; funcp_t *fp; for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) { *dest = *src; } for (dest = &_bss; dest < &_ebss; ) { *dest++ = 0; } /* Constructors. */ for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) { (*fp)(); } for (fp = &__init_array_start; fp < &__init_array_end; fp++) { (*fp)(); } /* might be provided by platform specific vector.c */ pre_main(); /* Call the application's entry point. */ main(); /* Destructors. */ for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) { (*fp)(); } } void blocking_handler(void) { while (1); } void null_handler(void) { /* Do nothing. */ } #pragma weak nmi_handler = null_handler #pragma weak hard_fault_handler = blocking_handler #pragma weak sv_call_handler = null_handler #pragma weak pend_sv_handler = null_handler #pragma weak sys_tick_handler = null_handler /* Those are defined only on CM3 or CM4 */ #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) #pragma weak mem_manage_handler = blocking_handler #pragma weak bus_fault_handler = blocking_handler #pragma weak usage_fault_handler = blocking_handler #pragma weak debug_monitor_handler = null_handler #endif hackrf-0.0~git20230104.cfc2f34/lib/dispatch/000077500000000000000000000000001435536612600200365ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/dispatch/vector_chipset.c000066400000000000000000000002621435536612600232230ustar00rootroot00000000000000#if defined(STM32F4) # include "../stm32/f4/vector_chipset.c" #elif defined(LPC43XX_M4) # include "../lpc43xx/m4/vector_chipset.c" #else static void pre_main(void) {} #endif hackrf-0.0~git20230104.cfc2f34/lib/dispatch/vector_nvic.c000066400000000000000000000023561435536612600225310ustar00rootroot00000000000000#if defined(STM32F0) # include "../stm32/f0/vector_nvic.c" #elif defined(STM32F1) # include "../stm32/f1/vector_nvic.c" #elif defined(STM32F2) # include "../stm32/f2/vector_nvic.c" #elif defined(STM32F3) # include "../stm32/f3/vector_nvic.c" #elif defined(STM32F4) # include "../stm32/f4/vector_nvic.c" #elif defined(STM32L1) # include "../stm32/l1/vector_nvic.c" #elif defined(EFM32TG) # include "../efm32/efm32tg/vector_nvic.c" #elif defined(EFM32G) # include "../efm32/efm32g/vector_nvic.c" #elif defined(EFM32LG) # include "../efm32/efm32lg/vector_nvic.c" #elif defined(EFM32GG) # include "../efm32/efm32gg/vector_nvic.c" #elif defined(LPC13XX) # include "../lpc13xx/vector_nvic.c" #elif defined(LPC17XX) # include "../lpc17xx/vector_nvic.c" #elif defined(LPC43XX_M4) # include "../lpc43xx/m4/vector_nvic.c" #elif defined(LPC43XX_M0) # include "../lpc43xx/m0/vector_nvic.c" #elif defined(SAM3X) # include "../sam/3x/vector_nvic.c" #elif defined(SAM3N) # include "../sam/3n/vector_nvic.c" #elif defined(LM3S) || defined(LM4F) /* Yes, we use the same interrupt table for both LM3S and LM4F */ # include "../lm3s/vector_nvic.c" #else # warning "no interrupts defined for chipset;"\ "not allocating space in the vector table" #define IRQ_HANDLERS #endif hackrf-0.0~git20230104.cfc2f34/lib/efm32/000077500000000000000000000000001435536612600171535ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32g/000077500000000000000000000000001435536612600202365ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32g/Makefile000066400000000000000000000025331435536612600217010ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 chrysn ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_efm32g FAMILY = EFM32G PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -D$(FAMILY) # ARFLAGS = rcsv ARFLAGS = rcs OBJS = VPATH += ../:../../cm3 include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32g/libopencm3_efm32g.ld000066400000000000000000000047631435536612600237670ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for EFM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32g/libopencm3_efm32g880f128.ld000066400000000000000000000006701435536612600246210ustar00rootroot00000000000000/* lengths from d011_efm32tg840_datasheet.pdf table 1.1, offset from * d0034_efm32tg_reference_manual.pdf figure 5.2. * * the origins and memory structure are constant over all tinygeckos, but the * MEMORY section requires the use of constants, and has thus to be duplicated * over the chip variants. * */ MEMORY { rom (rx) : ORIGIN = 0, LENGTH = 128k ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16k } INCLUDE libopencm3_efm32g.ld; hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32gg/000077500000000000000000000000001435536612600204055ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32gg/Makefile000066400000000000000000000025351435536612600220520ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 chrysn ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_efm32gg FAMILY = EFM32GG PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -D$(FAMILY) # ARFLAGS = rcsv ARFLAGS = rcs OBJS = VPATH += ../:../../cm3 include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32gg/libopencm3_efm32gg.ld000066400000000000000000000047631435536612600243050ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for EFM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32gg/libopencm3_efm32gg990f1024.ld000066400000000000000000000006741435536612600252210ustar00rootroot00000000000000/* lengths from d046_efm32gg990_datasheet.pdf table 1.1, offset from * d0034_efm32tg_reference_manual.pdf figure 5.2. * * the origins and memory structure are constant over all giantgeckos, but the * MEMORY section requires the use of constants, and has thus to be duplicated * over the chip variants. * */ MEMORY { rom (rx) : ORIGIN = 0, LENGTH = 1024k ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128k } INCLUDE libopencm3_efm32gg.ld; hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32lg/000077500000000000000000000000001435536612600204125ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32lg/Makefile000066400000000000000000000025351435536612600220570ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 chrysn ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_efm32lg FAMILY = EFM32LG PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -D$(FAMILY) # ARFLAGS = rcsv ARFLAGS = rcs OBJS = VPATH += ../:../../cm3 include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32lg/libopencm3_efm32lg.ld000066400000000000000000000047631435536612600243170ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for EFM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32tg/000077500000000000000000000000001435536612600204225ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32tg/Makefile000066400000000000000000000025351435536612600220670ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 chrysn ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_efm32tg FAMILY = EFM32TG PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -D$(FAMILY) # ARFLAGS = rcsv ARFLAGS = rcs OBJS = VPATH += ../:../../cm3 include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32tg/libopencm3_efm32tg.ld000066400000000000000000000047631435536612600243370ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for EFM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/efm32/efm32tg/libopencm3_efm32tg840f32.ld000066400000000000000000000006671435536612600251050ustar00rootroot00000000000000/* lengths from d011_efm32tg840_datasheet.pdf table 1.1, offset from * d0034_efm32tg_reference_manual.pdf figure 5.2. * * the origins and memory structure are constant over all tinygeckos, but the * MEMORY section requires the use of constants, and has thus to be duplicated * over the chip variants. * */ MEMORY { rom (rx) : ORIGIN = 0, LENGTH = 32k ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4k } INCLUDE libopencm3_efm32tg.ld; hackrf-0.0~git20230104.cfc2f34/lib/linker.ld.S000066400000000000000000000071041435536612600202470ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for all targets using libopencm3. */ /* Enforce emmition of the vector table. */ EXTERN(vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define memory regions. */ MEMORY { /* RAM is always used */ ram (rwx) : ORIGIN = RAM_OFF, LENGTH = RAM #if defined(ROM) rom (rx) : ORIGIN = ROM_OFF, LENGTH = ROM #endif #if defined(ROM2) rom2 (rx) : ORIGIN = ROM2_OFF, LENGTH = ROM2 #endif #if defined(RAM1) ram1 (rwx) : ORIGIN = RAM1_OFF, LENGTH = RAM1 #endif #if defined(RAM2) ram2 (rwx) : ORIGIN = RAM2_OFF, LENGTH = RAM2 #endif #if defined(CCM) ccm (rwx) : ORIGIN = CCM_OFF, LENGTH = CCM #endif #if defined(EEP) eep (r) : ORIGIN = EEP_OFF, LENGTH = EEP #endif #if defined(XSRAM) xsram (rw) : ORIGIN = XSRAM_OFF, LENGTH = XSRAM #endif #if defined(XDRAM) xdram (rw) : ORIGIN = XDRAM_OFF, LENGTH = XDRAM #endif } /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for * __attribute__((constructor)) and the likes. */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram #if defined(EEP) .eep : { *(.eeprom*) . = ALIGN(4); } >eep #endif #if defined(CCM) .ccm : { *(.ccmram*) . = ALIGN(4); } >ccm #endif #if defined(RAM1) .ram1 : { *(.ram1*) . = ALIGN(4); } >ram1 #endif #if defined(RAM2) .ram2 : { *(.ram2*) . = ALIGN(4); } >ram2 #endif #if defined(XSRAM) .xsram : { *(.xsram*) . = ALIGN(4); } >xsram #endif #if defined(XDRAM) .xdram : { *(.xdram*) . = ALIGN(4); } >xdram #endif /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/lm3s/000077500000000000000000000000001435536612600171155ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lm3s/Makefile000066400000000000000000000024151435536612600205570ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_lm3s PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DLM3S # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o vector.o assert.o VPATH += ../cm3 include ../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/lm3s/gpio.c000066400000000000000000000025151435536612600202220ustar00rootroot00000000000000/** @defgroup gpio_file General Purpose I/O @brief LM3S General Purpose I/O @ingroup LM3Sxx @version 1.0.0 @author @htmlonly © @endhtmlonly 2011 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include void gpio_set(uint32_t gpioport, uint8_t gpios) { /* ipaddr[9:2] mask the bits to be set, hence the array index */ GPIO_DATA(gpioport)[gpios] = 0xff; } void gpio_clear(uint32_t gpioport, uint8_t gpios) { GPIO_DATA(gpioport)[gpios] = 0; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lm3s/libopencm3_lm3s.ld000066400000000000000000000047621435536612600224400ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for LM3S targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/lm4f/000077500000000000000000000000001435536612600171015ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lm4f/Makefile000066400000000000000000000027231435536612600205450ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2013 Alexandru Gagniuc ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_lm4f FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../include -fno-common \ -mcpu=cortex-m4 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DLM4F # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o vector.o assert.o systemcontrol.o rcc.o uart.o \ usb_lm4f.o usb.o usb_control.o usb_standard.o VPATH += ../usb:../cm3 include ../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/lm4f/gpio.c000066400000000000000000000477121435536612600202160ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * Copyright (C) 2013 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** @defgroup gpio_file GPIO * * * @ingroup LM4Fxx * * @version 1.0.0 * * @author @htmlonly © @endhtmlonly 2011 * Gareth McMullin * @author @htmlonly © @endhtmlonly 2013 * Alexandru Gagniuc * * @date 16 March 2013 * * LGPL License Terms @ref lgpl_license * * @brief libopencm3 LM4F General Purpose I/O * * The LM4F GPIO API provides functionality for accessing the GPIO pins of the * LM4F. * * @attention @code An important aspect to consider is that libopencm3 uses the * AHB aperture for accessing the GPIO registers on the LM4F. The AHB must be * explicitly enabled with a call to gpio_enable_ahb_aperture() before accessing * any GPIO functionality. * @endcode * * Please see the individual GPIO modules for more details. To use the GPIO, the * gpio.h header needs to be included: * @code{.c} * #include * @endcode */ /**@{*/ #include #include /* Value we need to write to unlock the GPIO commit register */ #define GPIO_LOCK_UNLOCK_CODE 0x4C4F434B /** @defgroup gpio_config GPIO pin configuration * @ingroup gpio_file * * \brief Enabling and configuring GPIO pins * * @section gpio_api_enable Enabling GPIO ports * @attention * Before accessing GPIO functionality through this API, the AHB aperture for * GPIO ports must be enabled via a call to @ref gpio_enable_ahb_aperture(). * Failing to do so will cause a hard fault. * * @note * Once the AHB aperture is enabled, GPIO registers can no longer be accessed * via the APB aperture. The two apertures are mutually exclusive. * * Enabling the AHB aperture only needs to be done once. However, in order to * access a certain GPIO port, its clock must also be enabled. Enabling the * GPIO clock needs to be done for every port that will be used. * * For example, to enable GPIOA and GPIOD: * @code{.c} * // Make sure we can access the GPIO via the AHB aperture * gpio_enable_ahb_aperture(); * ... * // Enable GPIO ports A and D * periph_clock_enable(RCC_GPIOA); * periph_clock_enable(RCC_GPIOD); * @endcode * * On reset all ports are configured as digital floating inputs (no pull-up or * pull-down), except for special function pins. * * * @section gpio_api_in Configuring pins as inputs * * Configuring GPIO pins as inputs is done with @ref gpio_mode_setup(), with * @ref GPIO_MODE_INPUT for the mode parameter. The direction of the pull-up * must be specified with the same call * * For example, PA2, PA3, and PA4 as inputs, with pull-up on PA4: * @code{.c} * gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO2 | GPIO3); * gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO4); * @endcode * * * @section gpio_api_out Configuring pins as outputs * * Output pins have more configuration options than input pins. LM4F pins can be * configured as either push-pull, or open drain. The drive strength of each pin * can be adjusted between 2mA, 4mA, or 8mA. Slew-rate control is available when * the pins are configured to drive 8mA. These extra options can be specified * with @ref gpio_set_output_config(). * The default is push-pull configuration with 2mA drive capability. * * @note * @ref gpio_set_output_config() controls different capabilities than the * similar sounding gpio_set_output_options() from the STM GPIO API. They are * intentionally named differently to prevent confusion between the two. They * are API incompatible. * * For example, to set PA2 to output push-pull with a drive strength of 8mA: * @code{.c} * gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO2); * gpio_set_output_config(GPIOA, GPIO_OTYPE_PP, GPIO_DRIVE_8MA, GPIO2); * @endcode * * * @section gpio_api_analog Configuring pins as analog function * * Configuring GPIO pins to their analog function is done with * @ref gpio_mode_setup(), with @ref GPIO_MODE_ANALOG for the mode parameter. * * Suppose PD4 and PD5 are the USB pins. To enable their analog functionality * (USB D+ and D- in this case), use: * @code * // Mux USB pins to their analog function * gpio_mode_setup(GPIOD, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4 | GPIO5); * @endcode * * @section gpio_api_alf_func Configuring pins as alternate functions * * Most pins have alternate functions associated with them. When a pin is set to * an alternate function, it is multiplexed to one of the dedicated hardware * peripheral in the chip. The alternate function mapping can be found in the * part's datasheet, and usually varies between arts of the same family. * * Multiplexing a pin, or group of pins to an alternate function is done with * @ref gpio_set_af(). Because AF0 is not used on the LM4F, passing 0 as the * alt_func_num parameter will disable the alternate function of the given pins. * * @code * // Mux PB0 and PB1 to AF1 (UART1 TX/RX in this case) * gpio_set_af(GPIOB, 1, GPIO0 | GPIO1); * @endcode * * @section gpio_api_sfpins Changing configuration of special function pins * * On the LM4F, the NMI and JTAG/SWD default to their alternate function. These * pins cannot normally be committed to GPIO usage. To enable these special * function pins to be used as GPIO, they must be unlocked. This may be achieved * via @ref gpio_unlock_commit. Once a special function pin is unlocked, its * settings may be altered in the usual way. * * For example, to unlock the PF0 pin (NMI on the LM4F120): * @code * // PF0 is an NMI pin, and needs to be unlocked * gpio_unlock_commit(GPIOF, GPIO0); * // Now the pin can be configured * gpio_mode_setup(RGB_PORT, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, btnpins); * @endcode */ /**@{*/ /** * \brief Enable access to GPIO registers via the AHB aperture * * All GPIO registers are accessed in libopencm3 via the AHB aperture. It * provides faster control over the older APB aperture. This aperture must be * enabled before calling any other gpio_*() function. * */ void gpio_enable_ahb_aperture(void) { SYSCTL_GPIOHBCTL = 0xffffffff; } /** * \brief Configure a group of pins * * Sets the Pin direction, analog/digital mode, and pull-up configuration of * or a set of GPIO pins on a given GPIO port. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] mode Pin mode (@ref gpio_mode) \n * - GPIO_MODE_OUTPUT -- Configure pin as output \n * - GPIO_MODE_INPUT -- Configure pin as input \n * - GPIO_MODE_ANALOG -- Configure pin as analog function * @param[in] pullup Pin pullup/pulldown configuration (@ref gpio_pullup) \n * - GPIO_PUPD_NONE -- Do not pull the pin high or low \n * - GPIO_PUPD_PULLUP -- Pull the pin high \n * - GPIO_PUPD_PULLDOWN -- Pull the pin low * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together */ void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, enum gpio_pullup pullup, uint8_t gpios) { switch (mode) { case GPIO_MODE_OUTPUT: GPIO_DIR(gpioport) |= gpios; GPIO_DEN(gpioport) |= gpios; GPIO_AMSEL(gpioport) &= ~gpios; break; case GPIO_MODE_INPUT: GPIO_DIR(gpioport) &= ~gpios; GPIO_DEN(gpioport) |= gpios; GPIO_AMSEL(gpioport) &= ~gpios; break; case GPIO_MODE_ANALOG: GPIO_DEN(gpioport) &= ~gpios; GPIO_AMSEL(gpioport) |= gpios; break; default: /* Don't do anything */ break; } /* * Setting a bit in the GPIO_PDR register clears the corresponding bit * in the GPIO_PUR register, and vice-versa. */ switch (pullup) { case GPIO_PUPD_PULLUP: GPIO_PUR(gpioport) |= gpios; break; case GPIO_PUPD_PULLDOWN: GPIO_PDR(gpioport) |= gpios; break; case GPIO_PUPD_NONE: /* Fall through */ default: GPIO_PUR(gpioport) &= ~gpios; GPIO_PDR(gpioport) &= ~gpios; break; } } /** * \brief Configure output parameters of a group of pins * * Sets the output configuration and drive strength, of or a set of GPIO pins * for a set of GPIO pins in output mode. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] otype Output driver configuration (@ref gpio_output_type) \n * - GPIO_OTYPE_PP -- Configure pin driver as push-pull \n * - GPIO_OTYPE_OD -- Configure pin driver as open drain * @param[in] drive Pin drive strength (@ref gpio_drive_strength) \n * - GPIO_DRIVE_2MA -- 2mA drive \n * - GPIO_DRIVE_4MA -- 4mA drive \n * - GPIO_DRIVE_8MA -- 8mA drive \n * - GPIO_DRIVE_8MA_SLEW_CTL -- 8mA drive with slew rate * control * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together */ void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype, enum gpio_drive_strength drive, uint8_t gpios) { if (otype == GPIO_OTYPE_OD) { GPIO_ODR(gpioport) |= gpios; } else { GPIO_ODR(gpioport) &= ~gpios; } /* * Setting a bit in the GPIO_DRxR register clears the corresponding bit * in the other GPIO_DRyR registers, and vice-versa. */ switch (drive) { case GPIO_DRIVE_8MA_SLEW_CTL: GPIO_DR8R(gpioport) |= gpios; GPIO_SLR(gpioport) |= gpios; break; case GPIO_DRIVE_8MA: GPIO_DR8R(gpioport) |= gpios; GPIO_SLR(gpioport) &= ~gpios; break; case GPIO_DRIVE_4MA: GPIO_DR4R(gpioport) |= gpios; break; case GPIO_DRIVE_2MA: /* Fall through */ default: GPIO_DR2R(gpioport) |= gpios; break; } } #define PCTL_AF(pin, af) (af << (pin << 2)) #define PCTL_MASK(pin) PCTL_AF(pin, 0xf) /** * \brief Multiplex group of pins to the given alternate function * * Mux the pin or group of pins to the given alternate function. Note that a * number of pins may be set but only with a single AF number. This is useful * when one or more of a peripheral's pins are assigned to the same alternate * function. * * Because AF0 is not used on the LM4F, passing 0 as the alt_func_num parameter * will disable the alternate function of the given pins. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] alt_func_num Pin alternate function number or 0 to disable the * alternate function multiplexing. * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together */ void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios) { uint32_t pctl32; uint8_t pin_mask; int i; /* Did we mean to disable the alternate function? */ if (alt_func_num == 0) { GPIO_AFSEL(gpioport) &= ~gpios; return; } /* Enable the alternate function */ GPIO_AFSEL(gpioport) |= gpios; /* Alternate functions are digital */ GPIO_DEN(gpioport) |= gpios; /* Now take care of the actual multiplexing */ pctl32 = GPIO_PCTL(gpioport); for (i = 0; i < 8; i++) { pin_mask = (1 << i); if (!(gpios & pin_mask)) { continue; } pctl32 &= ~PCTL_MASK(i); pctl32 |= PCTL_AF(i, (alt_func_num & 0xf)); } GPIO_PCTL(gpioport) = pctl32; } /** * \brief Unlock the commit control of a special function pin * * Unlocks the commit control of the given pin or group of pins. If a pin is a * JTAG/SWD or NMI, the pin may then be reconfigured as a GPIO pin. If the pin * is not locked by default, this has no effect. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together. */ void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios) { /* Unlock the GPIO_CR register */ GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE; /* Enable committing changes */ GPIO_CR(gpioport) |= gpios; /* Lock the GPIO_CR register */ GPIO_LOCK(gpioport) = ~GPIO_LOCK_UNLOCK_CODE; } /**@}*/ /** @defgroup gpio_control GPIO pin control * @ingroup gpio_file * * \brief Controlling GPIO pins * * Each I/O port has 8 individually configurable bits. When reading and writing * data to the GPIO ports, address bits [9:2] mask the pins to be read or * written. This mechanism makes all GPIO port reads and writes on the LM4F * atomic operations. The GPIO API takes full advantage of this fact to preserve * the atomicity of these operations. * * Setting or clearing a group of bits can be accomplished with @ref gpio_set() * and @ref gpio_clear() respectively. These operation use the masking mechanism * described above to only affect the specified pins. * * Sometimes it is more appropriate to read or set the level of a group of pins * on a port, in one atomic operation. Reading the status can be accomplished * with @ref gpio_read(). The result is equivalent to reading all the pins, then * masking only the desired pins; however, the masking is done in hardware, and * does not require an extra hardware operation. * * Writing a group of pins can be accomplished with @ref gpio_write(). The mask * ('gpios' parameter) is applied in hardware, and the masked pins are not * affected, regardless of the value of the respective bits written to the GPIO * port. * * Two extra functions are provided, @ref gpio_port_read() and * @ref gpio_port_write(). They are functionally identical to * @ref gpio_read (port, GPIO_ALL) and @ref gpio_write (port, GPIO_ALL, val) * respectively. Hence, they are also atomic. * * GPIO pins may be toggled with @ref gpio_toggle(). This function does not * translate to an atomic operation. * * @note * The @ref gpio_toggle() operation is the only GPIO port operation which is not * atomic. It involves a read-modify-write cycle. * * Suppose PA0, PA1, PA2, and PA3 are to be modified without affecting the other * pins on port A. This is common when controlling, for example, a 4-bit bus: * @code{.c} * // Pins 4,5,6, and 7 are unaffected, regardless of the bits in val * gpio_write(GPIOA, GPIO0 | GPIO1 | GPIO2 | GPIO3, val); * // Wait a bit then send the other 4 bits * wait_a_bit(); * gpio_write(GPIOA, GPIO0 | GPIO1 | GPIO2 | GPIO3, val >> 4); * @endcode * * Suppose a LED is connected to PD4, and we want to flash the LED for a brief * period of time: * @code * gpio_set(GPIOD, GPIO4); * wait_a_bit(); * gpio_set(GPIOD, GPIO4); * @endcode */ /**@{*/ /** * \brief Toggle a Group of Pins * * Toggle one or more pins of the given GPIO port. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios Pin identifiers. @ref gpio_pin_id */ void gpio_toggle(uint32_t gpioport, uint8_t gpios) { /* The mask makes sure we only toggle the GPIOs we want to */ GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL; } /**@}*/ /** @defgroup gpio_irq GPIO Interrupt control * @ingroup gpio_file * * \brief Configuring interrupts from GPIO pins * * GPIO pins can trigger interrupts on either edges or levels. The type of * trigger can be configured with @ref gpio_configure_int_trigger(). To have an * event on the given pin generate an interrupt, its interrupt source must be * unmasked. This can be achieved with @ref gpio_enable_interrupts(). Interrupts * which are no longer needed can be disabled through * @ref gpio_disable_interrupts(). * * In order for the interrupt to generate an IRQ and a call to the interrupt * service routine, the interrupt for the GPIO port must be routed through the * NVIC with @ref nvic_enable_irq(). For this last step, the nvic.h header is * needed: * @code{.c} * #include * @endcode * * Enabling an interrupt is as simple as configuring the desired trigger, * unmasking the desired interrupt, and routing the desired GPIO port's * interrupt through the NVIC. * @code{.c} * // Trigger interrupt on each rising edge * gpio_configure_trigger(GPIOF, GPIO_TRIG_EDGE_RISE, GPIO0 | GPIO4); * // Unmask the interrupt on those pins * gpio_enable_interrupts(GPIOF, GPIO0 | GPIO4); * // Enable the interrupt in the NVIC as well * nvic_enable_irq(NVIC_GPIOF_IRQ); * @endcode * * After interrupts are properly enabled and routed through the NVIC, when an * event occurs, the appropriate IRQ flag is set by hardware, and execution * jumps to the GPIO ISR. The ISR should query the IRQ flags to determine which * event caused the interrupt. For this, use @ref gpio_is_interrupt_source(), * with the desired GPIO flag. After one or more interrupt sources are * serviced, the IRQ flags must be cleared by the ISR. This can be done with * @ref gpio_clear_interrupt_flag(). * * A typical GPIO ISR may look like the following: * @code{.c} * void gpiof_isr(void) * { * uint8_t serviced_irqs = 0; * * // Process individual IRQs * if (gpio_is_interrupt_source(GPIOF, GPIO0)) { * process_gpio0_event(); * serviced_irq |= GPIO0; * } * if (gpio_is_interrupt_source(GPIOF, GPIO4)) { * process_gpio4_event(); * serviced_irq |= GPIO4; * } * * // Clear the interupt flag for the processed IRQs * gpio_clear_interrupt_flag(GPIOF, serviced_irqs); * } * @endcode */ /**@{*/ /** * \brief Configure the interrupt trigger on the given GPIO pins * * Sets the Pin direction, analog/digital mode, and pull-up configuration of * or a set of GPIO pins on a given GPIO port. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] trigger Trigger configuration (@ref gpio_trigger) \n * - GPIO_TRIG_LVL_LOW -- Trigger on low level \n * - GPIO_TRIG_LVL_HIGH -- Trigger on high level \n * - GPIO_TRIG_EDGE_FALL -- Trigger on falling edges \n * - GPIO_TRIG_EDGE_RISE -- Trigger on rising edges \n * - GPIO_TRIG_EDGE_BOTH -- Trigger on all edges * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together */ void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, uint8_t gpios) { switch (trigger) { case GPIO_TRIG_LVL_LOW: GPIO_IS(gpioport) |= gpios; GPIO_IEV(gpioport) &= ~gpios; break; case GPIO_TRIG_LVL_HIGH: GPIO_IS(gpioport) |= gpios; GPIO_IEV(gpioport) |= gpios; break; case GPIO_TRIG_EDGE_FALL: GPIO_IS(gpioport) &= ~gpios; GPIO_IBE(gpioport) &= ~gpios; GPIO_IEV(gpioport) &= ~gpios; break; case GPIO_TRIG_EDGE_RISE: GPIO_IS(gpioport) &= ~gpios; GPIO_IBE(gpioport) &= ~gpios; GPIO_IEV(gpioport) |= gpios; break; case GPIO_TRIG_EDGE_BOTH: GPIO_IS(gpioport) &= ~gpios; GPIO_IBE(gpioport) |= gpios; break; default: /* Don't do anything */ break; } } /** * \brief Enable interrupts on specified GPIO pins * * Enable interrupts on the specified GPIO pins * * Note that the NVIC must be enabled and properly configured for the interrupt * to be routed to the CPU. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Pins whose interrupts to enable. Any * combination of pins may be specified by OR'ing them * together. */ void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios) { GPIO_IM(gpioport) |= gpios; } /** * \brief Disable interrupts on specified GPIO pins * * Disable interrupts on the specified GPIO pins * * Note that the NVIC must be enabled and properly configured for the interrupt * to be routed to the CPU. * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] gpios @ref gpio_pin_id. Pins whose interrupts to disable. Any * combination of pins may be specified by OR'ing them * together. */ void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios) { GPIO_IM(gpioport) |= gpios; } /**@}*/ /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lm4f/libopencm3_lm4f.ld000066400000000000000000000001211435536612600223710ustar00rootroot00000000000000/* Yes, we can simply use the lm3s linker script */ INCLUDE "libopencm3_lm3s.ld" hackrf-0.0~git20230104.cfc2f34/lib/lm4f/rcc.c000066400000000000000000000326131435536612600200210ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * */ /** * @defgroup rcc_file RCC * * @ingroup LM4Fxx * @author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc * \brief libopencm3 LM4F Clock control API * * The LM$F clock API provides functionaliity for manipulating the system clock, * oscillator, and PLL. Functions are provided for fine-grained control of clock * control registers, while also providing higher level functionality to easily * configure the main system clock source. * * The following code snippet uses fine-grained mechanisms to configures the * chip to run off an external 16MHz crystal, and use the PLL to derive a clock * frequency of 80MHz. * @code{.c} * // A divisor of 5 gives us a clock of 400/5 = 80MHz * #define PLLDIV_80MHZ 5 * * // Enable the main oscillator * rcc_enable_main_osc(); * * // Make RCC2 override RCC * rcc_enable_rcc2(); * * // Set XTAL value to 16MHz * rcc_configure_xtal(XTAL_16M); * // Set the oscillator source as the main oscillator * rcc_set_osc_source(OSCSRC_MOSC); * // Enable the PLL * rcc_pll_on(); * * // Change the clock divisor * rcc_set_pll_divisor(PLLDIV_80MHZ); * * // We cannot use the PLL as a clock source until it locks * rcc_wait_for_pll_ready(); * // Disable PLL bypass to derive the system clock from the PLL clock * rcc_pll_bypass_disable(); * * // Keep track of frequency * lm4f_rcc_sysclk_freq = 80E6; * @endcode * * The same can be achieved by a simple call to high-level routines: * @code * // A divisor of 5 gives us a clock of 400/5 = 80MHz * #define PLLDIV_80MHZ 5 * * rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLLDIV_80MHZ); * @endcode * * @{ */ #include /** * @defgroup rcc_low_level Low-level clock control API @ingroup rcc_file * @{ */ /** * \brief System clock frequency * * This variable is provided to keep track of the system clock frequency. It * should be updated every time the system clock is changed via the fine-grained * mechanisms. The initial value is 16MHz, which corresponds to the clock of the * internal 16MHz oscillator. * * High-level routines update the system clock automatically. * For read access, it is recommended to acces this variable via * @code * rcc_get_system_clock_frequency(); * @endcode * * If write access is desired (i.e. when changing the system clock via the * fine-grained mechanisms), then include the following line in your code: * @code * extern uint32_t lm4f_rcc_sysclk_freq; * @endcode */ uint32_t lm4f_rcc_sysclk_freq = 16000000; /** * \brief Configure the crystal type connected to the device. * * Configure the crystal type connected between the OSCO and OSCI pins by * writing the appropriate value to the XTAL field in SYSCTL_RCC. The PLL * parameters are automatically adjusted in hardware to provide a PLL clock of * 400MHz. * * @param[in] xtal predefined crystal type @see xtal_t */ void rcc_configure_xtal(enum xtal_t xtal) { uint32_t reg32; reg32 = SYSCTL_RCC; reg32 &= ~SYSCTL_RCC_XTAL_MASK; reg32 |= (xtal & SYSCTL_RCC_XTAL_MASK); SYSCTL_RCC = reg32; } /** * \brief Disable the main oscillator * * Sets the IOSCDIS bit in SYSCTL_RCC, disabling the main oscillator. */ void rcc_disable_main_osc(void) { SYSCTL_RCC |= SYSCTL_RCC_MOSCDIS; } /** * \brief Disable the internal oscillator * * Sets the IOSCDIS bit in SYSCTL_RCC, disabling the internal oscillator. */ void rcc_disable_interal_osc(void) { SYSCTL_RCC |= SYSCTL_RCC_IOSCDIS; } /** * \brief Enable the main oscillator * * Clears the MOSCDIS bit in SYSCTL_RCC, enabling the main oscillator. */ void rcc_enable_main_osc(void) { SYSCTL_RCC &= ~SYSCTL_RCC_MOSCDIS; } /** * \brief Enable the internal oscillator * * Clears the IOSCDIS bit in SYSCTL_RCC, enabling the internal oscillator. */ void rcc_enable_interal_osc(void) { SYSCTL_RCC &= ~SYSCTL_RCC_IOSCDIS; } /** * \brief Enable the use of SYSCTL_RCC2 register for clock control * * Enables the USERCC2 bit in SYSCTTL_RCC2. Settings in SYSCTL_RCC2 will * override settings in SYSCTL_RCC. * This function must be called before other calls to manipulate the clock, as * libopencm3 uses the SYSCTL_RCC2 register. */ void rcc_enable_rcc2(void) { SYSCTL_RCC2 |= SYSCTL_RCC2_USERCC2; } /** * \brief Power down the main PLL * * Sets the SYSCTL_RCC2_PWRDN2 in SYSCTL_RCC2 to power down the PLL. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ void rcc_pll_off(void) { SYSCTL_RCC2 |= SYSCTL_RCC2_PWRDN2; } /** * \brief Power up the main PLL * * Clears the PWRDN2 in SYSCTL_RCC2 to power on the PLL. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ void rcc_pll_on(void) { SYSCTL_RCC2 &= ~SYSCTL_RCC2_PWRDN2; } /** * \brief Set the oscillator source to be used by the system clock * * Set the clock source for the system clock. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ void rcc_set_osc_source(enum osc_src src) { uint32_t reg32; reg32 = SYSCTL_RCC2; reg32 &= ~SYSCTL_RCC2_OSCSRC2_MASK; reg32 |= (src & SYSCTL_RCC2_OSCSRC2_MASK); SYSCTL_RCC2 = reg32; } /** * \brief Disable the PLL bypass and use the PLL clock * * Clear BYPASS2 in SYSCTL_RCC2. The system clock is derived from the PLL * clock divided by the divisor specified in SYSDIV2. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ void rcc_pll_bypass_disable(void) { SYSCTL_RCC2 &= ~SYSCTL_RCC2_BYPASS2; } /** * \brief Enable the PLL bypass and use the oscillator clock * * Set BYPASS2 in SYSCTL_RCC2. The system clock is derived from the oscillator * clock divided by the divisor specified in SYSDIV2. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ void rcc_pll_bypass_enable(void) { SYSCTL_RCC2 |= SYSCTL_RCC2_BYPASS2; } /** * \brief Set the PLL clock divisor (from 400MHz) * * Set the binary divisor used to predivide the system clock down for use as the * timing reference for the PWM module. The divisor is expected to be a divisor * from 400MHz, not 200MHz. The DIV400 is also set. * * Specifies the divisor that used to generate the system clock from either the * PLL output or the oscillator source (depending on the BYPASS2 bit in * SYSCTL_RCC2). SYSDIV2 is used for the divisor when both the USESYSDIV bit in * SYSCTL_RCC is set. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. * * @param[in] div clock divisor to apply to the 400MHz PLL clock. It is the * caller's responsibility to ensure that the divisor will not create * a system clock that is out of spec. */ void rcc_set_pll_divisor(uint8_t div400) { uint32_t reg32; SYSCTL_RCC |= SYSCTL_RCC_USESYSDIV; reg32 = SYSCTL_RCC2; reg32 &= ~SYSCTL_RCC2_SYSDIV400_MASK; reg32 |= ((div400 - 1) << 22) & SYSCTL_RCC2_SYSDIV400_MASK; /* We are expecting a divider from 400MHz */ reg32 |= SYSCTL_RCC2_DIV400; SYSCTL_RCC2 = reg32; } /** * \brief Set the PWM unit clock divisor * * Set the binary divisor used to predivide the system clock down for use as the * timing reference for the PWM module. * * @param[in] div clock divisor to use @see pwm_clkdiv_t */ void rcc_set_pwm_divisor(enum pwm_clkdiv div) { uint32_t reg32; reg32 = SYSCTL_RCC; reg32 &= ~SYSCTL_RCC_PWMDIV_MASK; reg32 |= (div & SYSCTL_RCC_PWMDIV_MASK); SYSCTL_RCC = reg32; } /** * \brief Power down the USB PLL * * Sets the USBPWRDN in SYSCTL_RCC2 to power down the USB PLL. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ void rcc_usb_pll_off(void) { SYSCTL_RCC2 |= SYSCTL_RCC2_USBPWRDN; } /** * \brief Power up the USB PLL * * Clears the USBPWRDN in SYSCTL_RCC2 to power on the USB PLL. * * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ void rcc_usb_pll_on(void) { SYSCTL_RCC2 &= ~SYSCTL_RCC2_USBPWRDN; } /** * \brief Wait for main PLL to lock * * Waits until the LOCK bit in SYSCTL_PLLSTAT is set. This guarantees that the * PLL is locked, and ready to use. */ void rcc_wait_for_pll_ready(void) { while (!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK)); } /** * @} */ /** * @defgroup rcc_high_level High-level clock control API @ingroup rcc_file * @{ */ /** * \brief Change the PLL divisor * * Changes the divisor applied to the 400MHz PLL clock. The PLL must have * previously been configured by selecting an appropriate XTAL value, and * turning on the PLL. This function does not reconfigure the XTAL value or * oscillator source. It only changes the PLL divisor. * * The PLL is bypassed before modifying the divisor, and the function blocks * until the PLL is locked, then the bypass is disabled, before returning. * * @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock. */ void rcc_change_pll_divisor(uint8_t pll_div400) { /* Bypass the PLL while its settings are modified */ rcc_pll_bypass_enable(); /* Change the clock divisor */ rcc_set_pll_divisor(pll_div400); /* We cannot use the PLL as a clock source until it locks */ rcc_wait_for_pll_ready(); /* Disable PLL bypass to derive the system clock from the PLL clock */ rcc_pll_bypass_disable(); /* Update the system clock frequency for housekeeping */ lm4f_rcc_sysclk_freq = (uint32_t)400E6 / pll_div400; } /** * \brief Get the system clock frequency * * @return System clock frequency in Hz */ uint32_t rcc_get_system_clock_frequency(void) { return lm4f_rcc_sysclk_freq; } /* Get the clock frequency corresponding to a given XTAL value */ static uint32_t xtal_to_freq(enum xtal_t xtal) { const uint32_t freqs[] = { 4000000, /* XTAL_4M */ 4096000, /* XTAL_4M_096 */ 4915200, /* XTAL_4M_9152 */ 5000000, /* ,XTAL_5M */ 5120000, /* XTAL_5M_12 */ 6000000, /* XTAL_6M */ 6144000, /* XTAL_6M_144 */ 7372800, /* XTAL_7M_3728 */ 8000000, /* XTAL_8M */ 8192000, /* XTAL_8M_192 */ 10000000, /* XTAL_10M */ 12000000, /* XTAL_12M */ 12288000, /* XTAL_12M_288 */ 13560000, /* XTAL_13M_56 */ 14318180, /* XTAL_14M_31818 */ 16000000, /* XTAL_16M */ 16384000, /* XTAL_16M_384 */ 18000000, /* XTAL_18M */ 20000000, /* XTAL_20M */ 24000000, /* XTAL_24M */ 25000000, /* XTAL_25M */ }; return freqs[xtal - XTAL_4M]; } /** * \brief Configure the system clock source * * Sets up the system clock, including configuring the oscillator source, and * PLL to acheve the desired system clock frequency. Where applicable, The LM4F * clock API uses the new RCC2 register to configure clock parameters. * * Enables the main oscillator if the clock source is OSCSRC_MOSC. If the main * oscillator was previously enabled, it will not be disabled. If desired, it * can be separately disabled by a call to rcc_disable_main_osc(). * * Configures the system clock to run from the 400MHz PLL with a divisor of * pll_div400 applied. If pll_div400 is 0, then the PLL is disabled, and the * system clock is configured to run off a "raw" clock. If the PLL was * previously powered on, it will not be disabled. If desired, it can de powered * off by a call to rcc_pll_off(). * * @param [in] osc_src Oscillator from where to derive the system clock. * @param [in] xtal Type of crystal connected to the OSCO/OSCI pins * @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock. * If 0, then the PLL is disabled, and the system runs * off a "raw" clock. * * @return System clock frequency in Hz */ void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400) { /* * We could be using the PLL at this point, or we could be running of a * raw clock. Either way, it is safer to bypass the PLL now. */ rcc_pll_bypass_enable(); /* Enable the main oscillator, if needed */ if (src == OSCSRC_MOSC) { rcc_enable_main_osc(); } /* Make RCC2 override RCC */ rcc_enable_rcc2(); /* Set XTAL value to 16MHz */ rcc_configure_xtal(xtal); /* Set the oscillator source */ rcc_set_osc_source(src); if (pll_div400) { /* Enable the PLL */ rcc_pll_on(); /* Configure the PLL to the divisor we want */ rcc_change_pll_divisor(pll_div400); } else { /* We are running off a raw clock */ switch (src) { case OSCSRC_PIOSC: lm4f_rcc_sysclk_freq = 16000000; break; case OSCSRC_PIOSC_D4: lm4f_rcc_sysclk_freq = 4000000; break; case OSCSRC_MOSC: lm4f_rcc_sysclk_freq = xtal_to_freq(xtal); break; case OSCSRC_32K_EXT: lm4f_rcc_sysclk_freq = 32768; break; case OSCSRC_30K_INT: /* Fall through. */ default: /* * We either are running off the internal 30KHz * oscillator, which is +- 50% imprecise, or we got a * bad osc_src parameter. */ lm4f_rcc_sysclk_freq = 0; } } } /** * @} * @} */ hackrf-0.0~git20230104.cfc2f34/lib/lm4f/systemcontrol.c000066400000000000000000000025021435536612600221710ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /** * \brief Enable the clock source for the peripheral * * @param[in] periph peripheral and clock type to enable @see lm4f_clken */ void periph_clock_enable(enum lm4f_clken periph) { MMIO32(SYSCTL_BASE + (periph >> 5)) |= 1 << (periph & 0x1f); } /** * \brief Disable the clock source for the peripheral * * @param[in] periph peripheral and clock type to enable @see lm4f_clken */ void periph_clock_disable(enum lm4f_clken periph) { MMIO32(SYSCTL_BASE + (periph >> 5)) &= ~(1 << (periph & 0x1f)); } hackrf-0.0~git20230104.cfc2f34/lib/lm4f/uart.c000066400000000000000000000431631435536612600202270ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** * @defgroup uart_file UART * * @ingroup LM4Fxx * * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc * * \brief libopencm3 LM4F Universal Asynchronous Receiver Transmitter * * The LM4F UART API provides functionality for accessing the UART hardware of * the LM4F. * * Please see the individual UART modules for more details. To use the UART, the * uart.h header needs to be included: * @code{.c} * #include * @endcode * * @{ */ #include #include #include /** @defgroup uart_config UART configuration * @ingroup uart_file * * \brief Enabling and configuring the UART * * Enabling the UART is a two step process. The GPIO on which the UART resides * must be enabled, and the UART pins must be configured as alternate function, * digital pins. Pins must also be muxed to the appropriate alternate function. * This is done with the GPIO API. * * The second step involves enabling and the UART itself. The UART should be * disabled while it is being configured. * -# The UART clock must be enabled with @ref periph_clock_enable(). * -# The UART must be disabled with @ref uart_disable(). * -# The UART clock source should be chosen before setting the baudrate. * -# Baudrate, data bits, stop bit length, and parity can be configured. * -# If needed, enable CTS or RTS lines via the @ref uart_set_flow_control(). * -# The UART can now be enabled with @ref uart_enable(). * * For example, to enable UART1 at 115200 8n1 with hardware flow control: * @code{.c} * // Enable the UART clock * periph_clock_enable(RCC_UART1); * // We need a brief delay before we can access UART config registers * __asm__("nop"); __asm__("nop"); __asm__("nop"); * // Disable the UART while we mess with its settings * uart_disable(UART1); * // Configure the UART clock source as precision internal oscillator * uart_clock_from_piosc(); * // Set communication parameters * uart_set_baudrate(UART1, 115200); * uart_set_databits(UART1, 8); * uart_set_parity(UART1, UART_PARITY_NONE); * uart_set_stopbits(UART1, 1); * // Enable RTC and CTS lines * uart_set_flow_control(UART1, UART_FLOWCTL_HARD_RTS_CTS); * // Now that we're done messing with the settings, enable the UART * uart_enable(UART1); * @endcode */ /**@{*/ /** * \brief Enable the UART * * Enable the UART. The Rx and Tx lines are also enabled. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_enable(uint32_t uart) { UART_CTL(uart) |= (UART_CTL_UARTEN | UART_CTL_RXE | UART_CTL_TXE); } /** * \brief Disable the UART * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_disable(uint32_t uart) { UART_CTL(uart) &= ~UART_CTL_UARTEN; } /** * \brief Set UART baudrate * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] baud Baud rate in bits per second (bps).* */ void uart_set_baudrate(uint32_t uart, uint32_t baud) { uint32_t clock; /* Are we running off the internal clock or system clock? */ if (UART_CC(uart) == UART_CC_CS_PIOSC) { clock = 16000000; } else { clock = rcc_get_system_clock_frequency(); } /* Find the baudrate divisor */ uint32_t div = (((clock * 8) / baud) + 1) / 2; /* Set the baudrate divisors */ UART_IBRD(uart) = div / 64; UART_FBRD(uart) = div % 64; } /** * \brief Set UART databits * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] databits number of data bits per transmission. */ void uart_set_databits(uint32_t uart, uint8_t databits) { uint32_t reg32, bitint32_t; /* This has the same effect as using UART_LCRH_WLEN_5/6/7/8 directly */ bitint32_t = (databits - 5) << 5; /* TODO: What about 9 data bits? */ reg32 = UART_LCRH(uart); reg32 &= ~UART_LCRH_WLEN_MASK; reg32 |= bitint32_t; UART_LCRH(uart) = reg32; } /** * \brief Set UART stopbits * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] bits the requested number of stopbits, either 1 or 2. */ void uart_set_stopbits(uint32_t uart, uint8_t stopbits) { if (stopbits == 2) { UART_LCRH(uart) |= UART_LCRH_STP2; } else { UART_LCRH(uart) &= ~UART_LCRH_STP2; } } /** * \brief Set UART parity * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] bits the requested parity scheme. */ void uart_set_parity(uint32_t uart, enum uart_parity parity) { uint32_t reg32; reg32 = UART_LCRH(uart); reg32 |= UART_LCRH_PEN; reg32 &= ~(UART_LCRH_SPS | UART_LCRH_EPS); switch (parity) { case UART_PARITY_NONE: /* Once we disable parity the other bits are meaningless */ UART_LCRH(uart) &= ~UART_LCRH_PEN; return; case UART_PARITY_ODD: break; case UART_PARITY_EVEN: reg32 |= UART_LCRH_EPS; break; case UART_PARITY_STICK_0: reg32 |= (UART_LCRH_SPS | UART_LCRH_EPS); break; case UART_PARITY_STICK_1: reg32 |= UART_LCRH_SPS; break; } UART_LCRH(uart) = reg32; } /** * \brief Set the flow control scheme * * Set the flow control scheme by enabling or disabling RTS and CTS lines. This * will only have effect if the given UART supports the RTS and CTS lines. * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] flow The flow control scheme to use (none, RTS, CTS or both) \n * UART_FLOWCTL_RTS -- enable the RTS line \n * UART_FLOWCTL_CTS -- enable the CTS line \n * UART_FLOWCTL_RTS_CTS -- enable both RTS and CTS lines */ void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow) { uint32_t reg32 = UART_CTL(uart); reg32 &= ~(UART_CTL_RTSEN | UART_CTL_CTSEN); if (flow == UART_FLOWCTL_RTS) { reg32 |= UART_CTL_RTSEN; } else if (flow == UART_FLOWCTL_CTS) { reg32 |= UART_CTL_CTSEN; } else if (flow == UART_FLOWCTL_RTS_CTS) { reg32 |= (UART_CTL_RTSEN | UART_CTL_CTSEN); } UART_CTL(uart) = reg32; } /** * \brief Clock the UART module from the internal oscillator * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_clock_from_piosc(uint32_t uart) { UART_CC(uart) = UART_CC_CS_PIOSC; } /** * \brief Clock the UART module from the system clock * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_clock_from_sysclk(uint32_t uart) { UART_CC(uart) = UART_CC_CS_SYSCLK; } /**@}*/ /** @defgroup uart_send_recv UART transmission and reception * @ingroup uart_file * * \brief Sending and receiving data through the UART * * Primitives for sending and recieving data are provided, @ref uart_send() and * @ref uart_recv(). These primitives do not check if data can be transmitted * or wait for data. If waiting until data is available or can be transmitted is * desired, blocking primitives are also available, @ref uart_send_blocking() * and @ref uart_recv_blocking(). * * These primitives only handle one byte at at time, and thus may be unsuited * for some applications. You may also consider using @ref uart_dma. */ /**@{*/ /** * \brief UART Send a Data Word. * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] data data to send. */ void uart_send(uint32_t uart, uint16_t data) { data &= 0xFF; UART_DR(uart) = data; } /** * \brief UART Read a Received Data Word. * * @param[in] uart UART block register address base @ref uart_reg_base * @return data from the Rx FIFO. */ uint16_t uart_recv(uint32_t uart) { return UART_DR(uart) & UART_DR_DATA_MASK; } /** * \brief UART Wait for Transmit Data Buffer Not Full * * Blocks until the transmit data FIFO is not empty and can accept the next data * word. * \n * Even if the FIFO is not empty, this function will return as long as there is * room for at least one more word. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_wait_send_ready(uint32_t uart) { /* Wait until the Tx FIFO is no longer full */ while (UART_FR(uart) & UART_FR_TXFF); } /** * \brief UART Wait for Received Data Available * * Blocks until the receive data FIFO holds a at least valid received data word. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_wait_recv_ready(uint32_t uart) { /* Wait until the Tx FIFO is no longer empty */ while (UART_FR(uart) & UART_FR_RXFE); } /** * \brief UART Send Data Word with Blocking * * Blocks until the transmit data FIFO can accept the next data word for * transmission. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_send_blocking(uint32_t uart, uint16_t data) { uart_wait_send_ready(uart); uart_send(uart, data); } /** * \brief UART Read a Received Data Word with Blocking. * * Wait until a data word has been received then return the word. * * @param[in] uart UART block register address base @ref uart_reg_base * @return data from the Rx FIFO. */ uint16_t uart_recv_blocking(uint32_t uart) { uart_wait_recv_ready(uart); return uart_recv(uart); } /**@}*/ /** @defgroup uart_irq UART Interrupt control * @ingroup uart_file * * \brief Configuring interrupts from the UART * * To have an event generate an interrupt, its interrupt source must be * unmasked. This can be achieved with @ref uart_enable_interrupts(). Interrupts * which are no longer needed can be disabled through * @ref uart_disable_interrupts(). * * In order for the interrupt to generate an IRQ and a call to the interrupt * service routine, the interrupt for the target UART must be routed through the * NVIC with @ref nvic_enable_irq(). For this last step, the nvic.h header is * needed: * @code{.c} * #include * @endcode * * Enabling an interrupt is as simple as unmasking the desired interrupt, and * routing the desired UART's interrupt through the NVIC. * @code{.c} * // Unmask receive interrupt * uart_enable_rx_interrupt(UART0); * // Make sure the interrupt is routed through the NVIC * nvic_enable_irq(NVIC_UART0_IRQ); * @endcode * * If a more than one interrupt is to be enabled at one time, the interrupts * can be enabled by a single call to @ref uart_enable_interrupts(). * For example: * @code{.c} * // Unmask receive, CTS, and RI, interrupts * uart_enable_interrupts(UART0, UART_INT_RX | UART_INT_RI | UART_INT_CTS); * @endcode * * After interrupts are properly enabled and routed through the NVIC, when an * event occurs, the appropriate IRQ flag is set by hardware, and execution * jumps to the UART ISR. The ISR should query the IRQ flags to determine which * event caused the interrupt. For this, use @ref uart_is_interrupt_source(), * with the desired UART_INT flag. After one or more interrupt sources are * serviced, the IRQ flags must be cleared by the ISR. This can be done with * @ref uart_clear_interrupt_flag(). * * A typical UART ISR may look like the following: * @code{.c} * void uart0_isr(void) * { * uint32_t serviced_irqs = 0; * * // Process individual IRQs * if (uart_is_interrupt_source(UART0, UART_INT_RX)) { * process_rx_event(); * serviced_irq |= UART_INT_RX; * } * if (uart_is_interrupt_source(UART0, UART_INT_CTS)) { * process_cts_event(); * serviced_irq |= UART_INT_CTS; * } * * // Clear the interupt flag for the processed IRQs * uart_clear_interrupt_flag(UART0, serviced_irqs); * } * @endcode */ /**@{*/ /** * \brief Enable Specific UART Interrupts * * Enable any combination of interrupts. Interrupts may be OR'ed together to * enable them with one call. For example, to enable both the RX and CTS * interrupts, pass (UART_INT_RX | UART_INT_CTS) * * Note that the NVIC must be enabled and properly configured for the interrupt * to be routed to the CPU. * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] ints Interrupts which to enable. Any combination of interrupts may * be specified by OR'ing then together */ void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints) { UART_IM(uart) |= ints; } /** * \brief Enable Specific UART Interrupts * * Disabe any combination of interrupts. Interrupts may be OR'ed together to * disable them with one call. For example, to disable both the RX and CTS * interrupts, pass (UART_INT_RX | UART_INT_CTS) * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] ints Interrupts which to disable. Any combination of interrupts * may be specified by OR'ing then together */ void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints) { UART_IM(uart) &= ~ints; } /** * \brief Enable the UART Receive Interrupt. * * Note that the NVIC must be enabled and properly configured for the interrupt * to be routed to the CPU. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_enable_rx_interrupt(uint32_t uart) { uart_enable_interrupts(uart, UART_INT_RX); } /** * \brief Disable the UART Receive Interrupt. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_disable_rx_interrupt(uint32_t uart) { uart_disable_interrupts(uart, UART_INT_RX); } /** * \brief Enable the UART Transmit Interrupt. * * Note that the NVIC must be enabled and properly configured for the interrupt * to be routed to the CPU. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_enable_tx_interrupt(uint32_t uart) { uart_enable_interrupts(uart, UART_INT_TX); } /** * \brief Disable the UART Transmit Interrupt. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_disable_tx_interrupt(uint32_t uart) { uart_disable_interrupts(uart, UART_INT_TX); } /** * \brief Mark interrupt as serviced * * After an interrupt is services, its flag must be cleared. If the flag is not * cleared, then execution will jump back to the start of the ISR after the ISR * returns. * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] ints Interrupts which to clear. Any combination of interrupts may * be specified by OR'ing then together */ void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints) { UART_ICR(uart) |= ints; } /**@}*/ /** @defgroup uart_dma UART DMA control * @ingroup uart_file * * \brief Enabling Direct Memory Access transfers for the UART * */ /**@{*/ /** * \brief Enable the UART Receive DMA. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_enable_rx_dma(uint32_t uart) { UART_DMACTL(uart) |= UART_DMACTL_RXDMAE; } /** * \brief Disable the UART Receive DMA. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_disable_rx_dma(uint32_t uart) { UART_DMACTL(uart) &= ~UART_DMACTL_RXDMAE; } /** * \brief Enable the UART Transmit DMA. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_enable_tx_dma(uint32_t uart) { UART_DMACTL(uart) |= UART_DMACTL_TXDMAE; } /** * \brief Disable the UART Transmit DMA. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_disable_tx_dma(uint32_t uart) { UART_DMACTL(uart) &= ~UART_DMACTL_TXDMAE; } /**@}*/ /** @defgroup uart_fifo UART FIFO control * @ingroup uart_file * * \brief Enabling and controlling UART FIFO * * The UART on the LM4F can either be used with a single character TX and RX * buffer, or with a 8 character TX and RX FIFO. In order to use the FIFO it * must be enabled, this is done with uart_enable_fifo() and can be disabled * again with uart_disable_fifo(). On reset the FIFO is disabled, and it must * be explicitly be enabled. * * When enabling the UART FIFOs, RX and TX interrupts are triggered according * to the amount of data in the FIFOs. For the RX FIFO the trigger level is * defined by how full the FIFO is. The TX FIFO trigger level is defined by * how empty the FIFO is instead. * * For example, to enable the FIFOs and trigger interrupts for a single * received and single transmitted character: * @code{.c} * uart_enable_fifo(UART0); * uart_set_fifo_trigger_levels(UART0, UART_FIFO_RX_TRIG_1_8, * UART_FIFO_TX_TRIG_7_8); * @endcode */ /**@{*/ /** * \brief Enable FIFO for the UART. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_enable_fifo(uint32_t uart) { UART_LCRH(uart) |= UART_LCRH_FEN; } /** * \brief Disable FIFO for the UART. * * @param[in] uart UART block register address base @ref uart_reg_base */ void uart_disable_fifo(uint32_t uart) { UART_LCRH(uart) &= ~UART_LCRH_FEN; } /** * \brief Set the FIFO trigger levels. * * @param[in] uart UART block register address base @ref uart_reg_base * @param[in] rx_level Trigger level for RX FIFO * @param[in] tx_level Trigger level for TX FIFO */ void uart_set_fifo_trigger_levels(uint32_t uart, enum uart_fifo_rx_trigger_level rx_level, enum uart_fifo_tx_trigger_level tx_level) { UART_IFLS(uart) = rx_level | tx_level; } /**@}*/ /** * @} */ hackrf-0.0~git20230104.cfc2f34/lib/lm4f/usb_lm4f.c000066400000000000000000000411621435536612600207640ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Alexandru Gagniuc * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /** * @defgroup usb_file USB * * @ingroup LM4Fxx * * @author @htmlonly © @endhtmlonly 2013 * Alexandru Gagniuc * * \brief libopencm3 LM4F Universal Serial Bus controller * * The LM4F USB driver is integrated with the libopencm3 USB stack. You should * use the generic stack. * * To use this driver, tell the linker to look for it: * @code{.c} * extern usbd_driver lm4f_usb_driver; * @endcode * * And pass this driver as an argument when initializing the USB stack: * @code{.c} * usbd_device *usbd_dev; * usbd_dev = usbd_init(&lm4f_usb_driver, ...); * @endcode * * Polling or interrupt-driven? * * The LM4F USB driver will work fine regardless of whether it is called from an * interrupt service routine, or from the main program loop. * * Polling USB from the main loop requires calling @ref usbd_poll() from the * main program loop. * For example: * @code{.c} * // Main program loop * while(1) { * usbd_poll(usb_dev); * do_other_stuff(); * ... * @endcode * * Running @ref usbd_poll() from an interrupt has the advantage that it is only * called when needed, saving CPU cycles for the main program. * * RESET, DISCON, RESUME, and SUSPEND interrupts must be enabled, along with the * interrupts for any endpoint that is used. The EP0_TX interrupt must be * enabled for the control endpoint to function correctly. * For example, if EP1IN and EP2OUT are used, then the EP0_TX, EP1_TX, and * EP2_RX interrupts should be enabled: * @code{.c} * // Enable USB interrupts for EP0, EP1IN, and EP2OUT * ints = USB_INT_RESET | USB_INT_DISCON | USB_INT_RESUME | * USB_INT_SUSPEND; * usb_enable_interrupts(ints, USB_EP2_INT, USB_EP0_INT | USB_EP1_INT); * // Route the interrupts through the NVIC * nvic_enable_irq(NVIC_USB0_IRQ); * @endcode * * The USB ISR only has to call @ref usbd_poll(). * * @code{.c} * void usb0_isr(void) * { * usbd_poll(usb_dev); * } * @endcode * @{ */ /* * TODO list: * * 1) Driver works by reading and writing to the FIFOs one byte at a time. It * has no knowledge of DMA. * 2) Double-buffering is supported. How can we take advantage of it to speed * up endpoint transfers. * 3) No benchmarks as to the endpoint's performance has been done. */ /* * The following are resources referenced in comments: * [1] http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/238784.aspx */ #include #include #include #include #include "../../lib/usb/usb_private.h" #include #define MAX_FIFO_RAM (4 * 1024) const struct _usbd_driver lm4f_usb_driver; /** * \brief Enable Specific USB Interrupts * * Enable any combination of interrupts. Interrupts may be OR'ed together to * enable them with one call. For example, to enable both the RESUME and RESET * interrupts, pass (USB_INT_RESUME | USB_INT_RESET) * * Note that the NVIC must be enabled and properly configured for the interrupt * to be routed to the CPU. * * @param[in] ints Interrupts which to enable. Any combination of interrupts may * be specified by OR'ing then together * @param[in] rx_ints Endpoints for which to generate an interrupt when a packet * packet is received. * @param[in] tx_ints Endpoints for which to generate an interrupt when a packet * packet is finished transmitting. */ void usb_enable_interrupts(enum usb_interrupt ints, enum usb_ep_interrupt rx_ints, enum usb_ep_interrupt tx_ints) { USB_IE |= ints; USB_RXIE |= rx_ints; USB_TXIE |= tx_ints; } /** * \brief Disable Specific USB Interrupts * * Disable any combination of interrupts. Interrupts may be OR'ed together to * enable them with one call. For example, to disable both the RESUME and RESET * interrupts, pass (USB_INT_RESUME | USB_INT_RESET) * * Note that the NVIC must be enabled and properly configured for the interrupt * to be routed to the CPU. * * @param[in] ints Interrupts which to disable. Any combination of interrupts * may be specified by OR'ing then together * @param[in] rx_ints Endpoints for which to stop generating an interrupt when a * packet packet is received. * @param[in] tx_ints Endpoints for which to stop generating an interrupt when a * packet packet is finished transmitting. */ void usb_disable_interrupts(enum usb_interrupt ints, enum usb_ep_interrupt rx_ints, enum usb_ep_interrupt tx_ints) { USB_IE &= ~ints; USB_RXIE &= ~rx_ints; USB_TXIE &= ~tx_ints; } /** * @cond private */ static inline void lm4f_usb_soft_disconnect(void) { USB_POWER &= ~USB_POWER_SOFTCONN; } static inline void lm4f_usb_soft_connect(void) { USB_POWER |= USB_POWER_SOFTCONN; } static void lm4f_set_address(usbd_device *usbd_dev, uint8_t addr) { (void)usbd_dev; USB_FADDR = addr & USB_FADDR_FUNCADDR_MASK; } static void lm4f_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*callback) (usbd_device *usbd_dev, uint8_t ep)) { (void)usbd_dev; (void)type; uint8_t reg8; uint16_t fifo_size; const bool dir_tx = addr & 0x80; const uint8_t ep = addr & 0x0f; /* * We do not mess with the maximum packet size, but we can only allocate * the FIFO in power-of-two increments. */ if (max_size > 1024) { fifo_size = 2048; reg8 = USB_FIFOSZ_SIZE_2048; } else if (max_size > 512) { fifo_size = 1024; reg8 = USB_FIFOSZ_SIZE_1024; } else if (max_size > 256) { fifo_size = 512; reg8 = USB_FIFOSZ_SIZE_512; } else if (max_size > 128) { fifo_size = 256; reg8 = USB_FIFOSZ_SIZE_256; } else if (max_size > 64) { fifo_size = 128; reg8 = USB_FIFOSZ_SIZE_128; } else if (max_size > 32) { fifo_size = 64; reg8 = USB_FIFOSZ_SIZE_64; } else if (max_size > 16) { fifo_size = 32; reg8 = USB_FIFOSZ_SIZE_32; } else if (max_size > 8) { fifo_size = 16; reg8 = USB_FIFOSZ_SIZE_16; } else { fifo_size = 8; reg8 = USB_FIFOSZ_SIZE_8; } /* Endpoint 0 is more special */ if (addr == 0) { USB_EPIDX = 0; if (reg8 > USB_FIFOSZ_SIZE_64) { reg8 = USB_FIFOSZ_SIZE_64; } /* The RX and TX FIFOs are shared for EP0 */ USB_RXFIFOSZ = reg8; USB_TXFIFOSZ = reg8; /* * Regardless of how much we allocate, the first 64 bytes * are always reserved for EP0. */ usbd_dev->fifo_mem_top_ep0 = 64; return; } /* Are we out of FIFO space? */ if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM) { return; } USB_EPIDX = addr & USB_EPIDX_MASK; /* FIXME: What about double buffering? */ if (dir_tx) { USB_TXMAXP(ep) = max_size; USB_TXFIFOSZ = reg8; USB_TXFIFOADD = ((usbd_dev->fifo_mem_top) >> 3); if (callback) { usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_IN] = (void *)callback; } if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) { USB_TXCSRH(ep) |= USB_TXCSRH_ISO; } else { USB_TXCSRH(ep) &= ~USB_TXCSRH_ISO; } } else { USB_RXMAXP(ep) = max_size; USB_RXFIFOSZ = reg8; USB_RXFIFOADD = ((usbd_dev->fifo_mem_top) >> 3); if (callback) { usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_OUT] = (void *)callback; } if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) { USB_RXCSRH(ep) |= USB_RXCSRH_ISO; } else { USB_RXCSRH(ep) &= ~USB_RXCSRH_ISO; } } usbd_dev->fifo_mem_top += fifo_size; } static void lm4f_endpoints_reset(usbd_device *usbd_dev) { /* * The core resets the endpoints automatically on reset. * The first 64 bytes are always reserved for EP0 */ usbd_dev->fifo_mem_top = 64; } static void lm4f_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall) { (void)usbd_dev; const uint8_t ep = addr & 0x0f; const bool dir_tx = addr & 0x80; if (ep == 0) { if (stall) { USB_CSRL0 |= USB_CSRL0_STALL; } else { USB_CSRL0 &= ~USB_CSRL0_STALL; } return; } if (dir_tx) { if (stall) { (USB_TXCSRL(ep)) |= USB_TXCSRL_STALL; } else { (USB_TXCSRL(ep)) &= ~USB_TXCSRL_STALL; } } else { if (stall) { (USB_RXCSRL(ep)) |= USB_RXCSRL_STALL; } else { (USB_RXCSRL(ep)) &= ~USB_RXCSRL_STALL; } } } static uint8_t lm4f_ep_stall_get(usbd_device *usbd_dev, uint8_t addr) { (void)usbd_dev; const uint8_t ep = addr & 0x0f; const bool dir_tx = addr & 0x80; if (ep == 0) { return USB_CSRL0 & USB_CSRL0_STALLED; } if (dir_tx) { return USB_TXCSRL(ep) & USB_TXCSRL_STALLED; } else { return USB_RXCSRL(ep) & USB_RXCSRL_STALLED; } } static void lm4f_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak) { (void)usbd_dev; (void)addr; (void)nak; /* NAK's are handled automatically by hardware. Move along. */ } static uint16_t lm4f_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len) { const uint8_t ep = addr & 0xf; uint16_t i; (void)usbd_dev; /* Don't touch the FIFO if there is still a packet being transmitted */ if (ep == 0 && (USB_CSRL0 & USB_CSRL0_TXRDY)) { return 0; } else if (USB_TXCSRL(ep) & USB_TXCSRL_TXRDY) { return 0; } /* * We don't need to worry about buf not being aligned. If it's not, * the reads are downgraded to 8-bit in hardware. We lose a bit of * performance, but we don't crash. */ for (i = 0; i < (len & ~0x3); i += 4) { USB_FIFO32(ep) = *((uint32_t *)(buf + i)); } if (len & 0x2) { USB_FIFO16(ep) = *((uint16_t *)(buf + i)); i += 2; } if (len & 0x1) { USB_FIFO8(ep) = *((uint8_t *)(buf + i)); i += 1; } if (ep == 0) { /* * EP0 is very special. We should only set DATAEND when we * transmit the last packet in the transaction. A transaction * that is a multiple of 64 bytes will end with a zero-length * packet, so our check is sane. */ if (len != 64) { USB_CSRL0 |= USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; } else { USB_CSRL0 |= USB_CSRL0_TXRDY; } } else { USB_TXCSRL(ep) |= USB_TXCSRL_TXRDY; } return i; } static uint16_t lm4f_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len) { (void)usbd_dev; uint16_t rlen; uint8_t ep = addr & 0xf; uint16_t fifoin = USB_RXCOUNT(ep); rlen = (fifoin > len) ? len : fifoin; /* * We don't need to worry about buf not being aligned. If it's not, * the writes are downgraded to 8-bit in hardware. We lose a bit of * performance, but we don't crash. */ for (len = 0; len < (rlen & ~0x3); len += 4) { *((uint32_t *)(buf + len)) = USB_FIFO32(ep); } if (rlen & 0x2) { *((uint16_t *)(buf + len)) = USB_FIFO16(ep); len += 2; } if (rlen & 0x1) { *((uint8_t *)(buf + len)) = USB_FIFO8(ep); } if (ep == 0) { /* * Clear RXRDY * Datasheet says that DATAEND must also be set when clearing * RXRDY. We don't do that. If did this when transmitting a * packet larger than 64 bytes, only the first 64 bytes would * be transmitted, followed by a handshake. The host would only * get 64 bytes, seeing it as a malformed packet. Usually, we * would not get past enumeration. */ USB_CSRL0 |= USB_CSRL0_RXRDYC; } else { USB_RXCSRL(ep) &= ~USB_RXCSRL_RXRDY; } return rlen; } static void lm4f_poll(usbd_device *usbd_dev) { void (*tx_cb)(usbd_device *usbd_dev, uint8_t ea); void (*rx_cb)(usbd_device *usbd_dev, uint8_t ea); int i; /* * The initial state of these registers might change, as we process the * interrupt, but we need the initial state in order to decide how to * handle events. */ const uint8_t usb_is = USB_IS; const uint8_t usb_rxis = USB_RXIS; const uint8_t usb_txis = USB_TXIS; const uint8_t usb_csrl0 = USB_CSRL0; if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) { usbd_dev->user_callback_suspend(); } if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume)) { usbd_dev->user_callback_resume(); } if (usb_is & USB_IM_RESET) { _usbd_reset(usbd_dev); } if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof)) { usbd_dev->user_callback_sof(); } if (usb_txis & USB_EP0) { /* * The EP0 bit in USB_TXIS is special. It tells us that * something happened on EP0, but does not tell us what. This * bit does not necessarily tell us that a packet was * transmitted, so we have to go through all the possibilities * to figure out exactly what did. Only after we've exhausted * all other possibilities, can we assume this is a EPO * "transmit complete" interrupt. */ if (usb_csrl0 & USB_CSRL0_RXRDY) { enum _usbd_transaction type; type = (usbd_dev->control_state.state != DATA_OUT && usbd_dev->control_state.state != LAST_DATA_OUT) ? USB_TRANSACTION_SETUP : USB_TRANSACTION_OUT; if (usbd_dev->user_callback_ctr[0][type]) { usbd_dev-> user_callback_ctr[0][type](usbd_dev, 0); } } else { tx_cb = usbd_dev->user_callback_ctr[0] [USB_TRANSACTION_IN]; /* * EP0 bit in TXIS is set not only when a packet is * finished transmitting, but also when RXRDY is set, or * when we set TXRDY to transmit a packet. If any of * those are the case, then we do not want to call our * IN callback, since the state machine will be in the * wrong state, and we'll just stall our control * endpoint. * In fact, the only way to know if it's time to call * our TX callback is to know what to expect. The * hardware does not tell us what sort of transaction * this is. We need to work with the state machine to * figure it all out. See [1] for details. */ if ((usbd_dev->control_state.state != DATA_IN) && (usbd_dev->control_state.state != LAST_DATA_IN) && (usbd_dev->control_state.state != STATUS_IN)) { return; } if (tx_cb) { tx_cb(usbd_dev, 0); } } } /* See which interrupt occurred */ for (i = 1; i < 8; i++) { tx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN]; rx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_OUT]; if ((usb_txis & (1 << i)) && tx_cb) { tx_cb(usbd_dev, i); } if ((usb_rxis & (1 << i)) && rx_cb) { rx_cb(usbd_dev, i); } } } static void lm4f_disconnect(usbd_device *usbd_dev, bool disconnected) { (void)usbd_dev; /* * This is all it takes: * usbd_disconnect(dev, 1) followed by usbd_disconnect(dev, 0) * causes the device to re-enumerate and re-configure properly. */ if (disconnected) { lm4f_usb_soft_disconnect(); } else { lm4f_usb_soft_connect(); } } /* * A static struct works as long as we have only one USB peripheral. If we * meet LM4Fs with more than one USB, then we need to rework this approach. */ static struct _usbd_device usbd_dev; /** Initialize the USB device controller hardware of the LM4F. */ static usbd_device *lm4f_usbd_init(void) { int i; /* Start the USB clock */ periph_clock_enable(RCC_USB0); /* Enable the USB PLL interrupts - used to assert PLL lock */ SYSCTL_IMC |= (SYSCTL_IMC_USBPLLLIM | SYSCTL_IMC_PLLLIM); rcc_usb_pll_on(); /* Make sure we're disconnected. We'll reconnect later */ lm4f_usb_soft_disconnect(); /* Software reset USB */ SYSCTL_SRUSB = 1; for (i = 0; i < 1000; i++) { __asm__("nop"); } SYSCTL_SRUSB = 0; /* * Wait for the PLL to lock before soft connecting * This will result in a deadlock if the system clock is not setup * correctly (clock from main oscillator). */ /* Wait for it */ i = 0; while ((SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) { i++; if (i > 0xffff) { return 0; } } /* Now connect to USB */ lm4f_usb_soft_connect(); /* No FIFO allocated yet, but the first 64 bytes are still reserved */ usbd_dev.fifo_mem_top = 64; return &usbd_dev; } /* What is this thing even good for */ #define RX_FIFO_SIZE 512 const struct _usbd_driver lm4f_usb_driver = { .init = lm4f_usbd_init, .set_address = lm4f_set_address, .ep_setup = lm4f_ep_setup, .ep_reset = lm4f_endpoints_reset, .ep_stall_set = lm4f_ep_stall_set, .ep_stall_get = lm4f_ep_stall_get, .ep_nak_set = lm4f_ep_nak_set, .ep_write_packet = lm4f_ep_write_packet, .ep_read_packet = lm4f_ep_read_packet, .poll = lm4f_poll, .disconnect = lm4f_disconnect, .base_address = USB_BASE, .set_address_before_status = false, .rx_fifo_size = RX_FIFO_SIZE, }; /** * @endcond */ /** * @} */ hackrf-0.0~git20230104.cfc2f34/lib/lpc13xx/000077500000000000000000000000001435536612600175415ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lpc13xx/Makefile000066400000000000000000000024011435536612600211760ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_lpc13xx PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DLPC13XX # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o VPATH += ../cm3 include ../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/lpc13xx/gpio.c000066400000000000000000000022071435536612600206440ustar00rootroot00000000000000/** @defgroup gpio_file GPIO @ingroup LPC13xx @brief libopencm3 LPC13xx General Purpose I/O @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Uwe Hermann LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include void gpio_set(uint32_t gpioport, uint16_t gpios) { GPIO_DATA(gpioport) = gpios; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lpc13xx/libopencm3_lpc13xx.ld000066400000000000000000000047651435536612600235130ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for LPC13XX targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/lpc17xx/000077500000000000000000000000001435536612600175455ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lpc17xx/Makefile000066400000000000000000000024011435536612600212020ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_lpc17xx PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -O0 -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DLPC17XX # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o VPATH += ../cm3 include ../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/lpc17xx/gpio.c000066400000000000000000000023341435536612600206510ustar00rootroot00000000000000/** @defgroup gpio_file GPIO @ingroup LPC17xx @brief libopencm3 LPC17xx General Purpose I/O @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Uwe Hermann LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include void gpio_set(uint32_t gpioport, uint32_t gpios) { GPIO_SET(gpioport) = gpios; } void gpio_clear(uint32_t gpioport, uint32_t gpios) { GPIO_CLR(gpioport) = gpios; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lpc17xx/libopencm3_lpc17xx.ld000066400000000000000000000047651435536612600235230ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for LPC13XX targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/000077500000000000000000000000001435536612600175445ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/gpio.c000066400000000000000000000026271435536612600206550ustar00rootroot00000000000000/** @defgroup gpio_file GPIO @ingroup LPC43xx @brief libopencm3 LPC43xx General Purpose I/O @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Uwe Hermann LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include void gpio_set(uint32_t gpioport, uint32_t gpios) { GPIO_SET(gpioport) = gpios; } void gpio_clear(uint32_t gpioport, uint32_t gpios) { GPIO_CLR(gpioport) = gpios; } void gpio_toggle(uint32_t gpioport, uint32_t gpios) { GPIO_NOT(gpioport) = gpios; } uint32_t gpio_get(uint32_t gpioport, uint32_t gpios) { return (GPIO_PIN(gpioport) & gpios) != 0; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/i2c.c000066400000000000000000000103571435536612600203730ustar00rootroot00000000000000/** @defgroup i2c_file I2C @ingroup LPC43xx @brief libopencm3 LPC43xx I2C @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Michael Ossmann @author @htmlonly © @endhtmlonly 2014 Jared Boone LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2014 Benjamin Vernoux * Copyright (C) 2014 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * This is a very minimal I2C driver just to make sure we can get the * peripheral working. */ /**@{*/ #include #include #include #define I2C_TIMEOUT (10000) #define SFSP_I2C1_SDA_SCL (0x00000001 | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT | SCU_CONF_EZI_EN_IN_BUFFER) void i2c_init(i2c_port_t port, const uint16_t duty_cycle_count) { I2C_SCLH(port) = duty_cycle_count; I2C_SCLL(port) = duty_cycle_count; /* clear the control bits */ I2C_CONCLR(port) = (I2C_CONCLR_AAC | I2C_CONCLR_SIC | I2C_CONCLR_STAC | I2C_CONCLR_I2ENC); /* enable I2C0 */ I2C_CONSET(port) = I2C_CONSET_I2EN; } void i2c_disable(i2c_port_t port) { I2C_CONCLR(port) = I2C_CONCLR_I2ENC; } /* transmit start bit */ void i2c_tx_start(i2c_port_t port) { uint32_t timeout; I2C_CONCLR(port) = I2C_CONCLR_SIC; I2C_CONSET(port) = I2C_CONSET_STA; timeout = 0; while( (!(I2C_CONSET(port) & I2C_CONSET_SI)) && (timeout < I2C_TIMEOUT) ) { timeout++; } I2C_CONCLR(port) = I2C_CONCLR_STAC; } /* transmit data byte */ void i2c_tx_byte(i2c_port_t port, uint8_t byte) { uint32_t timeout; if (I2C_CONSET(port) & I2C_CONSET_STA) { I2C_CONCLR(port) = I2C_CONCLR_STAC; } I2C_DAT(port) = byte; I2C_CONCLR(port) = I2C_CONCLR_SIC; timeout = 0; while( (!(I2C_CONSET(port) & I2C_CONSET_SI)) && (timeout < I2C_TIMEOUT) ) { timeout++; } } /* receive data byte */ uint8_t i2c_rx_byte(i2c_port_t port, bool ack) { uint32_t timeout; if (I2C_CONSET(port) & I2C_CONSET_STA) { I2C_CONCLR(port) = I2C_CONCLR_STAC; } I2C_CONCLR(port) = I2C_CONCLR_SIC; if (ack) { I2C_CONSET(port) = I2C_CONSET_AA; } else { I2C_CONCLR(port) = I2C_CONCLR_AAC; } timeout = 0; while( (!(I2C_CONSET(port) & I2C_CONSET_SI)) && (timeout < I2C_TIMEOUT) ) { timeout++; } return I2C_DAT(port); } /* transmit stop bit */ void i2c_stop(i2c_port_t port) { if (I2C_CONSET(port) & I2C_CONSET_STA) { I2C_CONCLR(port) = I2C_CONCLR_STAC; } I2C_CONSET(port) = I2C_CONSET_STO; I2C_CONCLR(port) = I2C_CONCLR_SIC; } /* I2C0 wrappers for compatibility with old code */ void i2c0_init(const uint16_t duty_cycle_count) { /* enable input on SCL and SDA pins */ SCU_SFSI2C0 = SCU_I2C0_NOMINAL; i2c_init(I2C0, duty_cycle_count); } void i2c1_init(const uint16_t duty_cycle_count) { /* Configure pin function for I2C1*/ SCU_SFSP2_3 = SFSP_I2C1_SDA_SCL; SCU_SFSP2_4 = SFSP_I2C1_SDA_SCL; i2c_init(I2C1, duty_cycle_count); } /* transmit start bit */ void i2c0_tx_start(void) { i2c_tx_start(I2C0); } /* transmit start bit */ void i2c1_tx_start(void) { i2c_tx_start(I2C1); } /* transmit data byte */ void i2c0_tx_byte(uint8_t byte) { i2c_tx_byte(I2C0, byte); } /* transmit data byte */ void i2c1_tx_byte(uint8_t byte) { i2c_tx_byte(I2C1, byte); } /* receive data byte */ uint8_t i2c0_rx_byte(bool ack) { return i2c_rx_byte(I2C0, ack); } /* receive data byte */ uint8_t i2c1_rx_byte(bool ack) { return i2c_rx_byte(I2C1, ack); } /* transmit stop bit */ void i2c0_stop(void) { i2c_stop(I2C0); } /* transmit stop bit */ void i2c1_stop(void) { i2c_stop(I2C1); } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/ipc.c000066400000000000000000000036051435536612600204670ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include /* Set M0 in reset mode */ void ipc_halt_m0(void) { volatile uint32_t rst_active_status1; /* Check if M0 is reset by reading status */ rst_active_status1 = RESET_ACTIVE_STATUS1; /* If the M0 has reset not asserted, halt it... */ while (rst_active_status1 & RESET_CTRL1_M0APP_RST) { RESET_CTRL1 = ((~rst_active_status1) | RESET_CTRL1_M0APP_RST); rst_active_status1 = RESET_ACTIVE_STATUS1; } } void ipc_start_m0(uint32_t cm0_baseaddr) { volatile uint32_t rst_active_status1; /* Set M0 memory mapping to point to start of M0 image */ CREG_M0APPMEMMAP = cm0_baseaddr; /* Start/run M0 core */ /* Release Slave from reset, first read status */ rst_active_status1 = RESET_ACTIVE_STATUS1; /* If the M0 is being held in reset, release it */ /* 1 = no reset, 0 = reset */ while (!(rst_active_status1 & RESET_CTRL1_M0APP_RST)) { RESET_CTRL1 = ((~rst_active_status1) & ~RESET_CTRL1_M0APP_RST); rst_active_status1 = RESET_ACTIVE_STATUS1; } } void ipc_m0apptxevent_clear(void) { CREG_M0TXEVENT &= ~CREG_M0TXEVENT_TXEVCLR; } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m0/000077500000000000000000000000001435536612600200605ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m0/Makefile000066400000000000000000000026731435536612600215300ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 Michael Ossmann ## Copyright (C) 2012/2013 Benjamin Vernoux ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_lpc43xx_m0 PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -O2 -g3 -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m0 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DLPC43XX -DLPC43XX_M0 # ARFLAGS = rcsv ARFLAGS = rcs # LPC43xx common files for M4 / M0 OBJ_LPC43XX = gpio.o scu.o i2c.o ssp.o uart.o timer.o #LPC43xx M0 specific file + Generic LPC43xx M4/M0 files OBJS = $(OBJ_LPC43XX) VPATH += ../:../../cm3 include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m0/libopencm3_lpc43xx_m0.ld000066400000000000000000000057701435536612600244260ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2012 Benjamin Vernoux * Copyright (C) 2012 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for LPC43XX targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { . = ORIGIN(ram); .text : { . = ALIGN(0x400); *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >ram /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >ram .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >ram .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >ram /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >ram /* exception index - required due to libgcc.a issuing /0 exceptions */ .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >ram . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram _data_loadaddr = _data; /* Force src and dest equal (no-op) */ _edata = _data; /* Prevent copying data */ .bss : { _bss = .; *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ .ARM.extab : { *(.ARM.extab*) } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; __StackTop = ORIGIN(ram) + LENGTH(ram); PROVIDE(_stack = __StackTop); } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m4/000077500000000000000000000000001435536612600200645ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m4/Makefile000066400000000000000000000032411435536612600215240ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 Michael Ossmann ## Copyright (C) 2012 Benjamin Vernoux ## Copyright (C) 2013 Alexandru Gagniuc ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_lpc43xx FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -O2 -g3 \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m4 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD \ $(FP_FLAGS) -DLPC43XX -DLPC43XX_M4 ARFLAGS = rcs # LPC43xx common files for M4 / M0 OBJ_LPC43XX = gpio.o scu.o i2c.o ssp.o uart.o timer.o wwdt.o #LPC43xx M4 specific file + Generic LPC43xx M4/M0 files OBJS = $(OBJ_LPC43XX) ipc.o VPATH += ../:../../cm3 include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m4/libopencm3_lpc43xx.ld000066400000000000000000000070371435536612600240340ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2012 Benjamin Vernoux * Copyright (C) 2012 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for LPC43XX targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { . = ALIGN(0x400); _text_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ *(.vectors) /* Vector table */ . = ALIGN(0x400); ASSERT(. == 0x400, "Error: attempting to place firmware information section at incorrect location"); KEEP(*(.firmware_info)); *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom /* exception index - required due to libgcc.a issuing /0 exceptions */ .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; _etext_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ _etext_rom = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ . = ORIGIN(ram_local2); .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram_local2 AT >rom _data_loadaddr = LOADADDR(.data); _data_rom = LOADADDR (.data) + ORIGIN(rom); _edata_rom = _data_rom + SIZEOF (.data); .bss : { _bss = .; *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram_local2 /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ .ARM.extab : { *(.ARM.extab*) } >ram_local2 /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; /* Leave room above stack for IAP to run. */ __StackTop = ORIGIN(ram_local2) + LENGTH(ram_local2) - 32; PROVIDE(_stack = __StackTop); } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m4/libopencm3_lpc43xx_ram_only.ld000066400000000000000000000074751435536612600257420ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2012 Benjamin Vernoux * Copyright (C) 2012 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for LPC43XX targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { . = ORIGIN(ram_local1); .text : { . = ALIGN(0x400); _text_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ *(.vectors) /* Vector table */ . = ALIGN(0x400); ASSERT(. == 0x400, "Error: attempting to place firmware information section at incorrect location"); KEEP(*(.firmware_info)); *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >ram_local1 /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >ram_local1 .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >ram_local1 .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >ram_local1 /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >ram_local1 /* exception index - required due to libgcc.a issuing /0 exceptions */ __exidx_start = .; .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } > ram_local1 . = ALIGN(4); _etext = .; _etext_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ _etext_rom = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */ . = ORIGIN(ram_local2); .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram_local2 _data_loadaddr = LOADADDR(.data); /* Running from RAM only, loading the .elf will initialize data for us. */ _data_rom = .; _edata_rom = .; _data = .; _edata = .; .bss : { _bss = .; *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram_local2 /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ .ARM.extab : { *(.ARM.extab*) } >ram_local2 /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support - discard it for now. */ /DISCARD/ : { *(.ARM.exidx) } end = .; /* Leave room above stack for IAP to run. */ __StackTop = ORIGIN(ram_local2) + LENGTH(ram_local2) - 32; PROVIDE(_stack = __StackTop); } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m4/libopencm3_lpc43xx_rom_to_ram.ld000066400000000000000000000067051435536612600262530ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2012 Michael Ossmann * Copyright (C) 2012 Benjamin Vernoux * Copyright (C) 2012 Jared Boone * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for LPC43XX targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { . = ALIGN(0x400); _text_ram = (. - ORIGIN(rom)) + ORIGIN(ram_local1); /* Start of Code in RAM */ *(.vectors) /* Vector table */ . = ALIGN(0x400); ASSERT(. == 0x400, "Error: attempting to place firmware information section at incorrect location"); KEEP(*(.firmware_info)); *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom /* exception index - required due to libgcc.a issuing /0 exceptions */ .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; _etext_ram = (. - ORIGIN(rom)) + ORIGIN(ram_local1); _etext_rom = (. - ORIGIN(rom)) + ORIGIN(rom_flash); . = ORIGIN(ram_local2); .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram_local2 AT >rom _data_loadaddr = LOADADDR(.data); _data_rom = LOADADDR (.data) + ORIGIN(rom_flash); _edata_rom = _data_rom + SIZEOF (.data); .bss : { _bss = .; *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram_local2 /* exception unwind data - required due to libgcc.a issuing /0 exceptions */ .ARM.extab : { *(.ARM.extab*) } >ram_local2 /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; /* Leave room above stack for IAP to run. */ __StackTop = ORIGIN(ram_local2) + LENGTH(ram_local2) - 32; PROVIDE(_stack = __StackTop); } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/m4/vector_chipset.c000066400000000000000000000032551435536612600232560ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2012 Michael Ossmann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include extern unsigned _etext_ram, _text_ram, _etext_rom; #define CREG_M4MEMMAP MMIO32((0x40043000 + 0x100)) static void pre_main(void) { volatile unsigned *src, *dest; /* Copy the code from ROM to Real RAM (if enabled) */ if ((&_etext_ram-&_text_ram) > 0) { src = &_etext_rom-(&_etext_ram-&_text_ram); /* Change Shadow memory to ROM (for Debug Purpose in case Boot * has not set correctly the M4MEMMAP because of debug) */ CREG_M4MEMMAP = (unsigned long)src; for (dest = &_text_ram; dest < &_etext_ram; ) { *dest++ = *src++; } /* Change Shadow memory to Real RAM */ CREG_M4MEMMAP = (unsigned long)&_text_ram; /* Continue Execution in RAM */ } /* Enable access to Floating-Point coprocessor. */ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/scu.c000066400000000000000000000026661435536612600205140ustar00rootroot00000000000000/** @defgroup scu_file System Control Unit @ingroup LPC43xx @brief libopencm3 LPC43xx System Control Unit @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Benjamin Vernoux LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for * different I/O pins types */ void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf) { MMIO32(group_pin) = scu_conf; } /* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See * scu.h */ /* For Pin interrupt select register see scu.h SCU_PINTSEL0 & SCU_PINTSEL1 */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/ssp.c000066400000000000000000000070001435536612600205120ustar00rootroot00000000000000/** @defgroup ssp_file SSP @ingroup LPC43xx @brief libopencm3 LPC43xx SSP @version 1.0.0 @author @htmlonly © @endhtmlonly 2012/2014 Benjamin Vernoux LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include #include /* Disable SSP */ void ssp_disable(ssp_num_t ssp_num) { uint32_t ssp_port; if (ssp_num == SSP0_NUM) { ssp_port = SSP0; } else { ssp_port = SSP1; } /* Disable SSP */ SSP_CR1(ssp_port) = 0x0; } /* * SSP Init function */ void ssp_init(ssp_num_t ssp_num, ssp_datasize_t data_size, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, uint8_t serial_clock_rate, uint8_t clk_prescale, ssp_mode_t mode, ssp_master_slave_t master_slave, ssp_slave_option_t slave_option) { uint32_t ssp_port; uint32_t clock; if (ssp_num == SSP0_NUM) { ssp_port = SSP0; CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_SSP0_CLK_AUTOBLOCK(1); CCU1_CLK_M4_SSP0_CFG |= 1; /* Enable SSP0 Clock */ /* use PLL1 as clock source for SSP0 */ } else { ssp_port = SSP1; /* use PLL1 as clock source for SSP1 */ CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_SSP1_CLK_AUTOBLOCK(1); CCU1_CLK_M4_SSP1_CFG |= 1; /* Enable SSP1 Clock */ } /* Disable SSP before to configure it */ SSP_CR1(ssp_port) = 0x0; /* Configure SSP */ clock = serial_clock_rate; SSP_CPSR(ssp_port) = clk_prescale; SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8)); /* Enable SSP */ SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option); } static void ssp_wait_until_not_busy(ssp_num_t ssp_num) { uint32_t ssp_port; if (ssp_num == SSP0_NUM) { ssp_port = SSP0; } else { ssp_port = SSP1; } while ((SSP_SR(ssp_port) & SSP_SR_BSY)); } /* This Function Wait Data TX Ready, and Write Data to SSP */ uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data) { uint32_t ssp_port; if (ssp_num == SSP0_NUM) { ssp_port = SSP0; } else { ssp_port = SSP1; } /* Wait Until FIFO not full */ while ((SSP_SR(ssp_port) & SSP_SR_TNF) == 0); SSP_DR(ssp_port) = data; /* Wait for not busy, since we're controlling CS# of * devices manually and need to wait for the data to * be sent. It may also be important to wait here * in case we're configuring devices via SPI and also * with GPIO control -- we need to know when SPI * commands are effective before altering a device's * state with GPIO. I'm thinking the MAX2837, for * example... */ ssp_wait_until_not_busy(ssp_num); /* Wait Until Data Received (Rx FIFO not Empty) */ while ((SSP_SR(ssp_port) & SSP_SR_RNE) == 0); return SSP_DR(ssp_port); } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/timer.c000066400000000000000000000040361435536612600210330ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Ben Gamari * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * * This provides the code for the "next gen" EXTI block provided in F2/F4/L1 * devices. (differences only in the source selection) */ #include void timer_reset(uint32_t timer_peripheral) { TIMER_TCR(timer_peripheral) |= TIMER_TCR_CRST; TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CRST; } void timer_enable_counter(uint32_t timer_peripheral) { TIMER_TCR(timer_peripheral) |= TIMER_TCR_CEN; } void timer_disable_counter(uint32_t timer_peripheral) { TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CEN; } void timer_set_counter(uint32_t timer_peripheral, uint32_t count) { TIMER_TC(timer_peripheral) = count; } uint32_t timer_get_counter(uint32_t timer_peripheral) { return TIMER_TC(timer_peripheral); } uint32_t timer_get_prescaler(uint32_t timer_peripheral) { return TIMER_PR(timer_peripheral); } void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler) { TIMER_PR(timer_peripheral) = prescaler; } void timer_set_mode(uint32_t timer_peripheral, uint32_t mode) { TIMER_CTCR(timer_peripheral) = mode | (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_MODE_MASK); } void timer_set_count_input(uint32_t timer_peripheral, uint32_t input) { TIMER_CTCR(timer_peripheral) = input | (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_CINSEL_MASK); } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/uart.c000066400000000000000000000144201435536612600206640ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #define UART_SRC_32K 0x00 #define UART_SRC_IRC 0x01 #define UART_SRC_ENET_RX 0x02 #define UART_SRC_ENET_TX 0x03 #define UART_SRC_GP_CLKIN 0x04 #define UART_SRC_XTAL 0x06 #define UART_SRC_PLL0USB 0x07 #define UART_SRC_PLL0AUDIO 0x08 #define UART_SRC_PLL1 0x09 #define UART_SRC_IDIVA 0x0C #define UART_SRC_IDIVB 0x0D #define UART_SRC_IDIVC 0x0E #define UART_SRC_IDIVD 0x0F #define UART_SRC_IDIVE 0x10 #define UART_CGU_AUTOBLOCK_CLOCK_BIT 11 /* clock source selection (5 bits) */ #define UART_CGU_BASE_CLK_SEL_SHIFT 24 uint32_t dummy_read; /* * UART Init function */ void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, uart_stopbit_t data_nb_stop, uart_parity_t data_parity, uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval) { uint32_t lcr_config; uint32_t uart_port; uart_port = uart_num; switch (uart_num) { case UART0_NUM: /* use PLL1 as clock source for UART0 */ CGU_BASE_UART0_CLK = (1< 0) { counter++; if (counter >= rx_timeout_nb_cycles) { *error = UART_TIMEOUT_ERROR; return 0; } } } uart_val = (UART_RBR(uart_port) & UART_RBR_MASKBIT); /* Clear error */ *error = UART_NO_ERROR; return uart_val; } /* This Function Wait Data TX Ready, and Write Data to UART if rx_timeout_nb_cycles = 0 Infinite wait */ void uart_write(uart_num_t uart_num, uint8_t data) { uint32_t uart_port; uart_port = uart_num; /* Wait Until FIFO not full */ while ((UART_LSR(uart_port) & UART_LSR_THRE) == 0); UART_THR(uart_port) = data; } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx/wwdt.c000066400000000000000000000017071435536612600207020ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2016 Dominic Spill * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void wwdt_reset(uint32_t timeout) { WWDT_MOD = WWDT_MOD_WDEN | WWDT_MOD_WDRESET; timeout &= 0xFFFFFF; WWDT_TC = timeout; WWDT_FEED_SEQUENCE; } hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx_m0/000077500000000000000000000000001435536612600201405ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx_m0/Makefile000066400000000000000000000036501435536612600216040ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2012 Michael Ossmann ## Copyright (C) 2012/2013 Benjamin Vernoux ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_lpc43xx_m0 PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \ -mcpu=cortex-m0 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD # ARFLAGS = rcsv ARFLAGS = rcs # LPC43xx common files for M4 / M0 OBJ_LPC43XX = gpio.o scu.o i2c.o ssp.o nvic.o uart.o #LPC43xx M0 specific file + Generic LPC43xx M4/M0 files OBJS = vector.o $(OBJ_LPC43XX) # VPATH += ../usb # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) Q := @ endif all: $(LIBNAME).a $(LIBNAME).a: $(OBJS) @printf " AR $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AR) $(ARFLAGS) $@ $^ %.o: %.c @printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(CFLAGS) -o $@ -c $< %.o: ../lpc43xx/%.c @printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(CFLAGS) -o $@ -c $< clean: @printf " CLEAN lib/lpc43xx_m0\n" $(Q)rm -f *.o *.d $(Q)rm -f $(LIBNAME).a .PHONY: clean -include $(OBJS:.o=.d) hackrf-0.0~git20230104.cfc2f34/lib/lpc43xx_m0/vector.c000066400000000000000000000147271435536612600216210ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski , * Copyright (C) 2012 chrysn * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ extern unsigned _bss, _ebss, _stack; void main(void); void blocking_handler(void); void null_handler(void); void WEAK reset_handler(void); void WEAK nmi_handler(void); void WEAK hard_fault_handler(void); void WEAK mem_manage_handler(void); void WEAK bus_fault_handler(void); void WEAK usage_fault_handler(void); void WEAK sv_call_handler(void); void WEAK debug_monitor_handler(void); void WEAK pend_sv_handler(void); void WEAK m0_rtc_isr(void); void WEAK m0_m4core_isr(void); void WEAK m0_dma_isr(void); void WEAK m0_ethernet_isr(void); void WEAK m0_flasheepromat_isr(void); void WEAK m0_sdio_isr(void); void WEAK m0_lcd_isr(void); void WEAK m0_usb0_isr(void); void WEAK m0_usb1_isr(void); void WEAK m0_sct_isr(void); void WEAK m0_ritimer_or_wwdt_isr(void); void WEAK m0_timer0_isr(void); void WEAK m0_gint1_isr(void); void WEAK m0_pin_int4_isr(void); void WEAK m0_timer3_isr(void); void WEAK m0_mcpwm_isr(void); void WEAK m0_adc0_isr(void); void WEAK m0_i2c0_or_i2c1_isr(void); void WEAK m0_sgpio_isr(void); void WEAK m0_spi_or_dac_isr(void); void WEAK m0_adc1_isr(void); void WEAK m0_ssp0_or_ssp1_isr(void); void WEAK m0_eventrouter_isr(void); void WEAK m0_usart0_isr(void); void WEAK m0_uart1_isr(void); void WEAK m0_usart2_or_c_can1_isr(void); void WEAK m0_usart3_isr(void); void WEAK m0_i2s0_or_i2s1_isr(void); void WEAK m0_c_can0_isr(void); /* Initialization template for the interrupt vector table. This definition is * used by the startup code generator (vector.c) to set the initial values for * the interrupt handling routines to the chip family specific _isr weak * symbols. */ /* See UserManual LPC43xx rev1_4 UM10503 Table 26. Connection of interrupt sources to the Cortex-M0 NVIC */ __attribute__ ((section(".vectors"))) void (*const vector_table[]) (void) = { /* Cortex-M4 interrupts */ (void*)&_stack, reset_handler, nmi_handler, hard_fault_handler, mem_manage_handler, bus_fault_handler, usage_fault_handler, 0, 0, 0, 0, /* reserved */ sv_call_handler, debug_monitor_handler, 0, /* reserved */ pend_sv_handler, 0, /* sys_tick_handler not supported on LPC4330 M0 */ /* IrqID 0 , ExcNo 16 */ m0_rtc_isr, /* IrqID 1 , ExcNo 17 */ m0_m4core_isr, /* IrqID 2 , ExcNo 18 */ m0_dma_isr, /* IrqID 3 , ExcNo 19 */ 0, /* IrqID 4 , ExcNo 20 */ m0_flasheepromat_isr, /* IrqID 5 , ExcNo 21 */ m0_ethernet_isr, /* IrqID 6 , ExcNo 22 */ m0_sdio_isr, /* IrqID 7 , ExcNo 23 */ m0_lcd_isr, /* IrqID 8 , ExcNo 24 */ m0_usb0_isr, /* IrqID 9 , ExcNo 25 */ m0_usb1_isr, /* IrqID 10, ExcNo 26 */ m0_sct_isr, /* IrqID 11, ExcNo 27 */ m0_ritimer_or_wwdt_isr, /* IrqID 12, ExcNo 28 */ m0_timer0_isr, /* IrqID 13, ExcNo 29 */ m0_gint1_isr, /* IrqID 14, ExcNo 30 */ m0_pin_int4_isr, /* IrqID 15, ExcNo 31 */ m0_timer3_isr, /* IrqID 16, ExcNo 32 */ m0_mcpwm_isr, /* IrqID 17, ExcNo 33 */ m0_adc0_isr, /* IrqID 18, ExcNo 34 */ m0_i2c0_or_i2c1_isr, /* IrqID 19, ExcNo 35 */ m0_sgpio_isr, /* IrqID 20, ExcNo 36 */ m0_spi_or_dac_isr, /* IrqID 21, ExcNo 37 */ m0_adc1_isr, /* IrqID 22, ExcNo 38 */ m0_ssp0_or_ssp1_isr, /* IrqID 23, ExcNo 39 */ m0_eventrouter_isr, /* IrqID 24, ExcNo 40 */ m0_usart0_isr, /* IrqID 25, ExcNo 41 */ m0_uart1_isr, /* IrqID 26, ExcNo 42 */ m0_usart2_or_c_can1_isr, /* IrqID 27, ExcNo 43 */ m0_usart3_isr, /* IrqID 28, ExcNo 44 */ m0_i2s0_or_i2s1_isr, /* IrqID 29, ExcNo 45 */ m0_c_can0_isr, /* IrqID 30, ExcNo 46 */ 0, /* IrqID 31, ExcNo 47 */ 0 }; void WEAK reset_handler(void) { volatile unsigned long *dest; __asm__("MSR msp, %0" : : "r"(&_stack)); /* Data does not need to be copied as M4 have already copied the whole bin including code+data */ /* Set BSS */ for (dest = (unsigned long*)(&_bss); dest < (unsigned long*)(&_ebss); ) *dest++ = 0; /* Call the application's entry point. */ main(); } void blocking_handler(void) { while (1) ; } void null_handler(void) { /* Do nothing. */ } #pragma weak nmi_handler = null_handler #pragma weak hard_fault_handler = blocking_handler #pragma weak mem_manage_handler = blocking_handler #pragma weak bus_fault_handler = blocking_handler #pragma weak usage_fault_handler = blocking_handler #pragma weak sv_call_handler = null_handler #pragma weak debug_monitor_handler = null_handler #pragma weak pend_sv_handler = null_handler /* M0 */ #pragma weak m0_rtc_isr = blocking_handler #pragma weak m0_m4core_isr = blocking_handler #pragma weak m0_dma_isr = blocking_handler #pragma weak m0_flasheepromat_isr = blocking_handler #pragma weak m0_ethernet_isr = blocking_handler #pragma weak m0_sdio_isr = blocking_handler #pragma weak m0_lcd_isr = blocking_handler #pragma weak m0_usb0_isr = blocking_handler #pragma weak m0_usb1_isr = blocking_handler #pragma weak m0_sct_isr = blocking_handler #pragma weak m0_ritimer_or_wwdt_isr = blocking_handler #pragma weak m0_timer0_isr = blocking_handler #pragma weak m0_gint1_isr = blocking_handler #pragma weak m0_pin_int4_isr = blocking_handler #pragma weak m0_timer3_isr = blocking_handler #pragma weak m0_mcpwm_isr = blocking_handler #pragma weak m0_adc0_isr = blocking_handler #pragma weak m0_i2c0_or_i2c1_isr = blocking_handler #pragma weak m0_sgpio_isr = blocking_handler #pragma weak m0_spi_or_dac_isr = blocking_handler #pragma weak m0_adc1_isr = blocking_handler #pragma weak m0_ssp0_or_ssp1_isr = blocking_handler #pragma weak m0_eventrouter_isr = blocking_handler #pragma weak m0_usart0_isr = blocking_handler #pragma weak m0_uart1_isr = blocking_handler #pragma weak m0_usart2_or_c_can1_isr = blocking_handler #pragma weak m0_usart3_isr = blocking_handler #pragma weak m0_i2s0_or_i2s1_isr = blocking_handler #pragma weak m0_c_can0_isr = blocking_handler hackrf-0.0~git20230104.cfc2f34/lib/sam/000077500000000000000000000000001435536612600170175ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/sam/3n/000077500000000000000000000000001435536612600173375ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/sam/3n/Makefile000066400000000000000000000022331435536612600207770ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_sam3n PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3N # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o pmc.o usart.o VPATH += ../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/sam/3n/libopencm3_sam3n.ld000066400000000000000000000047631435536612600230260ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/sam/3x/000077500000000000000000000000001435536612600173515ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/sam/3x/Makefile000066400000000000000000000022451435536612600210140ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_sam3x PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3X # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o pmc.o usart.o VPATH += ../../usb:../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/sam/3x/libopencm3_sam3x.ld000066400000000000000000000047631435536612600230520ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/sam/common/000077500000000000000000000000001435536612600203075ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/sam/common/gpio.c000066400000000000000000000033041435536612600214110ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void gpio_init(uint32_t port, uint32_t pins, enum gpio_flags flags) { switch (flags & 3) { case GPIO_FLAG_GPINPUT: /* input mode doesn't really exist, so we make a high * output in open-drain mode */ PIO_SODR(port) = pins; flags |= GPIO_FLAG_OPEN_DRAIN; /* fall through */ case GPIO_FLAG_GPOUTPUT: PIO_OER(port) = pins; PIO_PER(port) = pins; break; case GPIO_FLAG_PERIPHA: PIO_ABSR(port) &= ~pins; PIO_PDR(port) = pins; break; case GPIO_FLAG_PERIPHB: PIO_ABSR(port) |= pins; PIO_PDR(port) = pins; } if (flags & GPIO_FLAG_OPEN_DRAIN) { PIO_MDER(port) = pins; } else { PIO_MDDR(port) = pins; } if (flags & GPIO_FLAG_PULL_UP) { PIO_PUER(port) = pins; } else { PIO_PUDR(port) = pins; } } void gpio_toggle(uint32_t gpioport, uint32_t gpios) { uint32_t odsr = PIO_ODSR(gpioport); PIO_CODR(gpioport) = odsr & gpios; PIO_SODR(gpioport) = ~odsr & gpios; } hackrf-0.0~git20230104.cfc2f34/lib/sam/common/pmc.c000066400000000000000000000047271435536612600212440ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /** Default peripheral clock frequency after reset. */ uint32_t pmc_mck_frequency = 4000000; void pmc_xtal_enable(bool en, uint8_t startup_time) { if (en) { CKGR_MOR = (CKGR_MOR & ~CKGR_MOR_MOSCXTST_MASK) | CKGR_MOR_KEY | CKGR_MOR_MOSCXTEN | (startup_time << 8); while (!(PMC_SR & PMC_SR_MOSCXTS)); } else { CKGR_MOR = CKGR_MOR_KEY | (CKGR_MOR & ~CKGR_MOR_MOSCXTEN); } } void pmc_plla_config(uint8_t mul, uint8_t div) { CKGR_PLLAR = CKGR_PLLAR_ONE | ((mul - 1) << 16) | CKGR_PLLAR_PLLACOUNT_MASK | div; while (!(PMC_SR & PMC_SR_LOCKA)); } void pmc_peripheral_clock_enable(uint8_t pid) { if (pid < 32) { PMC_PCER0 = 1 << pid; } else { PMC_PCER1 = 1 << (pid & 31); } } void pmc_peripheral_clock_disable(uint8_t pid) { if (pid < 32) { PMC_PCDR0 = 1 << pid; } else { PMC_PCDR1 = 1 << (pid & 31); } } void pmc_mck_set_source(enum mck_src src) { PMC_MCKR = (PMC_MCKR & ~PMC_MCKR_CSS_MASK) | src; while (!(PMC_SR & PMC_SR_MCKRDY)); } void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void) { eefc_set_latency(4); /* 12MHz external xtal, maximum possible startup time */ pmc_xtal_enable(true, 0xff); /* Select as main oscillator */ CKGR_MOR |= CKGR_MOR_KEY | CKGR_MOR_MOSCSEL; /* Multiply by 7 for 84MHz */ pmc_plla_config(7, 1); pmc_mck_set_source(MCK_SRC_PLLA); pmc_mck_frequency = 84000000; } void pmc_clock_setup_in_rc_4mhz_out_84mhz(void) { eefc_set_latency(4); /* Select as main oscillator */ CKGR_MOR = CKGR_MOR_KEY | (CKGR_MOR & ~(CKGR_MOR_MOSCSEL | CKGR_MOR_MOSCRCF_MASK)); /* Multiply by 21 for 84MHz */ pmc_plla_config(21, 1); pmc_mck_set_source(MCK_SRC_PLLA); pmc_mck_frequency = 84000000; } hackrf-0.0~git20230104.cfc2f34/lib/sam/common/usart.c000066400000000000000000000051251435536612600216140ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include void usart_set_baudrate(uint32_t usart, uint32_t baud) { USART_BRGR(usart) = pmc_mck_frequency / (16 * baud); } void usart_set_databits(uint32_t usart, int bits) { USART_MR(usart) = (USART_MR(usart) & ~USART_MR_CHRL_MASK) | ((bits - 5) << 6); } void usart_set_stopbits(uint32_t usart, enum usart_stopbits sb) { USART_MR(usart) = (USART_MR(usart) & ~USART_MR_NBSTOP_MASK) | (sb << 12); } void usart_set_parity(uint32_t usart, enum usart_parity par) { USART_MR(usart) = (USART_MR(usart) & ~USART_MR_PAR_MASK) | (par << 9); } void usart_set_mode(uint32_t usart, enum usart_mode mode) { USART_CR(usart) = (mode & USART_MODE_RX) ? USART_CR_RXEN : USART_CR_RXDIS; USART_CR(usart) = (mode & USART_MODE_TX) ? USART_CR_TXEN : USART_CR_TXDIS; } void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol fc) { USART_MR(usart) = (USART_MR(usart) & ~USART_MR_MODE_MASK) | (fc ? USART_MR_MODE_HW_HANDSHAKING : 0); } void usart_enable(uint32_t usart) { } void usart_disable(uint32_t usart) { } void usart_send(uint32_t usart, uint16_t data) { USART_THR(usart) = data; } uint16_t usart_recv(uint32_t usart) { return USART_RHR(usart) & 0x1f; } void usart_wait_send_ready(uint32_t usart) { while ((USART_CSR(usart) & USART_CSR_TXRDY) == 0); } void usart_wait_recv_ready(uint32_t usart) { while ((USART_CSR(usart) & USART_CSR_RXRDY) == 0); } void usart_send_blocking(uint32_t usart, uint16_t data) { usart_wait_send_ready(usart); usart_send(usart, data); } uint16_t usart_recv_blocking(uint32_t usart) { usart_wait_recv_ready(usart); return usart_recv(usart); } void usart_enable_rx_interrupt(uint32_t usart) { USART_IER(usart) = USART_CSR_RXRDY; } void usart_disable_rx_interrupt(uint32_t usart) { USART_IDR(usart) = USART_CSR_RXRDY; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/000077500000000000000000000000001435536612600172075ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/can.c000066400000000000000000000405421435536612600201210ustar00rootroot00000000000000/** @defgroup can_file CAN @ingroup STM32F_files @brief libopencm3 STM32Fxxx CAN @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski @date 12 November 2012 Devices can have up to two CAN peripherals. The peripherals support up to 1MBit transmission rate. The peripheral has several filters for incoming messages that can be distributed between two FIFOs and three transmit mailboxes. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #if defined(STM32F1) # include #elif defined(STM32F2) # include #elif defined(STM32F4) # include #else # error "stm32 family not defined." #endif /* Timeout for CAN INIT acknowledge * this value is difficult to define. * INIT is set latest after finishing the current transfer. * Assuming the lowest CAN speed of 100kbps one CAN frame may take about 1.6ms * WAIT loop timeout varies on compiler switches, optimization, CPU architecture * and CPU speed * * The same timeout value is used for leaving INIT where the longest time is * 11 bits(110 us on 100 kbps). */ #define CAN_MSR_INAK_TIMEOUT 0x0000FFFF /*---------------------------------------------------------------------------*/ /** @brief CAN Reset The CAN peripheral and all its associated configuration registers are placed in the reset condition. The reset is effective via the RCC peripheral reset system. @param[in] canport Unsigned int32. CAN block register address base @ref can_reg_base. */ void can_reset(uint32_t canport) { if (canport == CAN1) { rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST); } else { rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST); } } /*---------------------------------------------------------------------------*/ /** @brief CAN Init Initialize the selected CAN peripheral block. @param[in] canport Unsigend int32. CAN register base address @ref can_reg_base. @param[in] ttcm bool. Time triggered communication mode. @param[in] abom bool. Automatic bus-off management. @param[in] awum bool. Automatic wakeup mode. @param[in] nart bool. No automatic retransmission. @param[in] rflm bool. Receive FIFO locked mode. @param[in] txfp bool. Transmit FIFO priority. @param[in] sjw Unsigned int32. Resynchronization time quanta jump width. @param[in] ts1 Unsigned int32. Time segment 1 time quanta width. @param[in] ts2 Unsigned int32. Time segment 2 time quanta width. @param[in] brp Unsigned int32. Baud rate prescaler. @returns int 0 on success, 1 on initialization failure. */ int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart, bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp, bool loopback, bool silent) { volatile uint32_t wait_ack; int ret = 0; /* Exit from sleep mode. */ CAN_MCR(canport) &= ~CAN_MCR_SLEEP; /* Request initialization "enter". */ CAN_MCR(canport) |= CAN_MCR_INRQ; /* Wait for acknowledge. */ wait_ack = CAN_MSR_INAK_TIMEOUT; while ((--wait_ack) && ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)); /* Check the acknowledge. */ if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) { return 1; } /* clear can timing bits */ CAN_BTR(canport) = 0; /* Set the automatic bus-off management. */ if (ttcm) { CAN_MCR(canport) |= CAN_MCR_TTCM; } else { CAN_MCR(canport) &= ~CAN_MCR_TTCM; } if (abom) { CAN_MCR(canport) |= CAN_MCR_ABOM; } else { CAN_MCR(canport) &= ~CAN_MCR_ABOM; } if (awum) { CAN_MCR(canport) |= CAN_MCR_AWUM; } else { CAN_MCR(canport) &= ~CAN_MCR_AWUM; } if (nart) { CAN_MCR(canport) |= CAN_MCR_NART; } else { CAN_MCR(canport) &= ~CAN_MCR_NART; } if (rflm) { CAN_MCR(canport) |= CAN_MCR_RFLM; } else { CAN_MCR(canport) &= ~CAN_MCR_RFLM; } if (txfp) { CAN_MCR(canport) |= CAN_MCR_TXFP; } else { CAN_MCR(canport) &= ~CAN_MCR_TXFP; } if (silent) { CAN_BTR(canport) |= CAN_BTR_SILM; } else { CAN_BTR(canport) &= ~CAN_BTR_SILM; } if (loopback) { CAN_BTR(canport) |= CAN_BTR_LBKM; } else { CAN_BTR(canport) &= ~CAN_BTR_LBKM; } /* Set bit timings. */ CAN_BTR(canport) |= sjw | ts2 | ts1 | ((brp - 1ul) & CAN_BTR_BRP_MASK); /* Request initialization "leave". */ CAN_MCR(canport) &= ~CAN_MCR_INRQ; /* Wait for acknowledge. */ wait_ack = CAN_MSR_INAK_TIMEOUT; while ((--wait_ack) && ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)); if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) { ret = 1; } return ret; } /*---------------------------------------------------------------------------*/ /** @brief CAN Filter Init Initialize incoming message filter and assign to FIFO. @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] nr Unsigned int32. ID number of the filter. @param[in] scale_32bit bool. 32-bit scale for the filter? @param[in] id_list_mode bool. ID list filter mode? @param[in] fr1 Unsigned int32. First filter register content. @param[in] fr2 Unsigned int32. Second filter register content. @param[in] fifo Unsigned int32. FIFO id. @param[in] enable bool. Enable filter? */ void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode, uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable) { uint32_t filter_select_bit = 0x00000001 << nr; /* Request initialization "enter". */ CAN_FMR(canport) |= CAN_FMR_FINIT; /* Deactivate the filter. */ CAN_FA1R(canport) &= ~filter_select_bit; if (scale_32bit) { /* Set 32-bit scale for the filter. */ CAN_FS1R(canport) |= filter_select_bit; } else { /* Set 16-bit scale for the filter. */ CAN_FS1R(canport) &= ~filter_select_bit; } if (id_list_mode) { /* Set filter mode to ID list mode. */ CAN_FM1R(canport) |= filter_select_bit; } else { /* Set filter mode to id/mask mode. */ CAN_FM1R(canport) &= ~filter_select_bit; } /* Set the first filter register. */ CAN_FiR1(canport, nr) = fr1; /* Set the second filter register. */ CAN_FiR2(canport, nr) = fr2; /* Select FIFO0 or FIFO1 as filter assignement. */ if (fifo) { CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */ } else { CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */ } if (enable) { CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */ } /* Request initialization "leave". */ CAN_FMR(canport) &= ~CAN_FMR_FINIT; } /*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 16bit Message ID Mask Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] nr Unsigned int32. ID number of the filter. @param[in] id1 Unsigned int16. First message ID to filter. @param[in] mask1 Unsigned int16. First message ID bit mask. @param[in] id2 Unsigned int16. Second message ID to filter. @param[in] mask2 Unsigned int16. Second message ID bit mask. @param[in] fifo Unsigned int32. FIFO id. @param[in] enable bool. Enable filter? */ void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1, uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable) { can_filter_init(canport, nr, false, false, ((uint32_t)id1 << 16) | (uint32_t)mask1, ((uint32_t)id2 << 16) | (uint32_t)mask2, fifo, enable); } /*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 32bit Message ID Mask Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] nr Unsigned int32. ID number of the filter. @param[in] id Unsigned int32. Message ID to filter. @param[in] mask Unsigned int32. Message ID bit mask. @param[in] fifo Unsigned int32. FIFO id. @param[in] enable bool. Enable filter? */ void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask, uint32_t fifo, bool enable) { can_filter_init(canport, nr, true, false, id, mask, fifo, enable); } /*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 16bit Message ID List Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] nr Unsigned int32. ID number of the filter. @param[in] id1 Unsigned int16. First message ID to match. @param[in] id2 Unsigned int16. Second message ID to match. @param[in] id3 Unsigned int16. Third message ID to match. @param[in] id4 Unsigned int16. Fourth message ID to match. @param[in] fifo Unsigned int32. FIFO id. @param[in] enable bool. Enable filter? */ void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2, uint16_t id3, uint16_t id4, uint32_t fifo, bool enable) { can_filter_init(canport, nr, false, true, ((uint32_t)id1 << 16) | (uint32_t)id2, ((uint32_t)id3 << 16) | (uint32_t)id4, fifo, enable); } /*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 32bit Message ID List Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] nr Unsigned int32. ID number of the filter. @param[in] id1 Unsigned int32. First message ID to match. @param[in] id2 Unsigned int32. Second message ID to match. @param[in] fifo Unsigned int32. FIFO id. @param[in] enable bool. Enable filter? */ void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2, uint32_t fifo, bool enable) { can_filter_init(canport, nr, true, true, id1, id2, fifo, enable); } /*---------------------------------------------------------------------------*/ /** @brief CAN Enable IRQ @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] irq Unsigned int32. IRQ bit(s). */ void can_enable_irq(uint32_t canport, uint32_t irq) { CAN_IER(canport) |= irq; } /*---------------------------------------------------------------------------*/ /** @brief CAN Disable IRQ @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] irq Unsigned int32. IRQ bit(s). */ void can_disable_irq(uint32_t canport, uint32_t irq) { CAN_IER(canport) &= ~irq; } /*---------------------------------------------------------------------------*/ /** @brief CAN Transmit Message @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] id Unsigned int32. Message ID. @param[in] ext bool. Extended message ID? @param[in] rtr bool. Request transmit? @param[in] length Unsigned int8. Message payload length. @param[in] data Unsigned int8[]. Message payload data. @returns int 0, 1 or 2 on success and depending on which outgoing mailbox got selected. -1 if no mailbox was available and no transmission got queued. */ int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data) { int ret = 0; uint32_t mailbox = 0; union { uint8_t data8[4]; uint32_t data32; } tdlxr, tdhxr; /* Check which transmit mailbox is empty if any. */ if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) { ret = 0; mailbox = CAN_MBOX0; } else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) { ret = 1; mailbox = CAN_MBOX1; } else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) { ret = 2; mailbox = CAN_MBOX2; } else { ret = -1; } /* If we have no empty mailbox return with an error. */ if (ret == -1) { return ret; } if (ext) { /* Set extended ID. */ CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) | CAN_TIxR_IDE; } else { /* Set standard ID. */ CAN_TIxR(canport, mailbox) = id << CAN_TIxR_STID_SHIFT; } /* Set/clear remote transmission request bit. */ if (rtr) { CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */ } /* Set the DLC. */ CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK; CAN_TDTxR(canport, mailbox) |= (length & CAN_TDTxR_DLC_MASK); switch (length) { case 8: tdhxr.data8[3] = data[7]; /* no break */ case 7: tdhxr.data8[2] = data[6]; /* no break */ case 6: tdhxr.data8[1] = data[5]; /* no break */ case 5: tdhxr.data8[0] = data[4]; /* no break */ case 4: tdlxr.data8[3] = data[3]; /* no break */ case 3: tdlxr.data8[2] = data[2]; /* no break */ case 2: tdlxr.data8[1] = data[1]; /* no break */ case 1: tdlxr.data8[0] = data[0]; /* no break */ default: break; } /* Set the data. */ CAN_TDLxR(canport, mailbox) = tdlxr.data32; CAN_TDHxR(canport, mailbox) = tdhxr.data32; /* Request transmission. */ CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ; return ret; } /*---------------------------------------------------------------------------*/ /** @brief CAN Release FIFO @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] fifo Unsigned int8. FIFO id. */ void can_fifo_release(uint32_t canport, uint8_t fifo) { if (fifo == 0) { CAN_RF0R(canport) |= CAN_RF1R_RFOM1; } else { CAN_RF1R(canport) |= CAN_RF1R_RFOM1; } } /*---------------------------------------------------------------------------*/ /** @brief CAN Receive Message @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @param[in] fifo Unsigned int8. FIFO id. @param[in] release bool. Release the FIFO automatically after coping data out. @param[out] id Unsigned int32 pointer. Message ID. @param[out] ext bool pointer. The message ID is extended? @param[out] rtr bool pointer. Request of transmission? @param[out] fmi Unsigned int32 pointer. ID of the matched filter. @param[out] length Unsigned int8 pointer. Length of message payload. @param[out] data Unsigned int8[]. Message payload data. */ void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext, bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data) { uint32_t fifo_id = 0; union { uint8_t data8[4]; uint32_t data32; } rdlxr, rdhxr; const uint32_t fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1}; fifo_id = fifoid_array[fifo]; /* Get type of CAN ID and CAN ID. */ if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) { *ext = true; /* Get extended CAN ID. */ *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) & CAN_RIxR_EXID_MASK; } else { *ext = false; /* Get standard CAN ID. */ *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) & CAN_RIxR_STID_MASK; } /* Get remote transmit flag. */ if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) { *rtr = true; } else { *rtr = false; } /* Get filter match ID. */ *fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) >> CAN_RDTxR_FMI_SHIFT); /* Get data length. */ *length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK; /* accelerate reception by copying the CAN data from the controller * memory to the fast internal RAM */ rdlxr.data32 = CAN_RDLxR(canport, fifo_id); rdhxr.data32 = CAN_RDHxR(canport, fifo_id); /* */ /* Get data. * Byte wise copy is needed because we do not know the alignment * of the input buffer. * Here copying 8 bytes unconditionally is faster than using loop * * It is OK to copy all 8 bytes because the upper layer must be * prepared for data length bigger expected. * In contrary the driver has no information about the intended size. * This could be different if the max length would be handed over * to the function, but it is not the case */ data[0] = rdlxr.data8[0]; data[1] = rdlxr.data8[1]; data[2] = rdlxr.data8[2]; data[3] = rdlxr.data8[3]; data[4] = rdhxr.data8[0]; data[5] = rdhxr.data8[1]; data[6] = rdhxr.data8[2]; data[7] = rdhxr.data8[3]; /* Release the FIFO. */ if (release) { can_fifo_release(canport, fifo); } } bool can_available_mailbox(uint32_t canport) { return CAN_TSR(canport) & (CAN_TSR_TME0 | CAN_TSR_TME1 | CAN_TSR_TME2); } hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/000077500000000000000000000000001435536612600204775ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/crc_common_all.c000066400000000000000000000041111435536612600236070ustar00rootroot00000000000000/** @addtogroup crc_file @author @htmlonly © @endhtmlonly 2012 Karl Palsson */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief CRC Reset. Reset the CRC unit and forces the data register to all 1s. */ void crc_reset(void) { CRC_CR |= CRC_CR_RESET; } /*---------------------------------------------------------------------------*/ /** @brief CRC Calculate. Writes a data word to the register, the write operation stalling until the computation is complete. @param[in] data Unsigned int32. @returns int32 Computed CRC result */ uint32_t crc_calculate(uint32_t data) { CRC_DR = data; /* Data sheet says this blocks until it's ready.... */ return CRC_DR; } /*---------------------------------------------------------------------------*/ /** @brief CRC Calculate of a Block of Data. Writes data words consecutively to the register, the write operation stalling until the computation of each word is complete. @param[in] datap Unsigned int32. pointer to an array of 32 bit data words. @param[in] size int. Size of the array. @returns int32 Final computed CRC result */ uint32_t crc_calculate_block(uint32_t *datap, int size) { int i; for (i = 0; i < size; i++) { CRC_DR = datap[i]; } return CRC_DR; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/crypto_common_f24.c000066400000000000000000000101001435536612600241760ustar00rootroot00000000000000/** @addtogroup crypto_file * * @brief libopencm3 STM32 Cryptographic controller * * @version 1.0.0 * * @date 17 Jun 2013 * * This library supports the cryptographic coprocessor system for the * STM32 series of ARM Cortex Microcontrollers * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #define CRYP_CR_ALGOMODE_MASK ((1 << 19) | CRYP_CR_ALGOMODE) /** * @brief Wait, if the Controller is busy */ void crypto_wait_busy(void) { while (CRYP_SR & CRYP_SR_BUSY); } /** * @brief Set key value to the controller * @param[in] keysize enum crypto_keysize Specified size of the key. * @param[in] key uint64_t[] Key value (array of 4 items) */ void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]) { int i; crypto_wait_busy(); CRYP_CR = (CRYP_CR & ~CRYP_CR_KEYSIZE) | (keysize << CRYP_CR_KEYSIZE_SHIFT); for (i = 0; i < 4; i++) { CRYP_KR(i) = key[i]; } } /** * @brief Set Initialization Vector * * @param[in] iv uint64_t[] Initialization vector (array of 4 items) * @note Cryptographic controller must be in disabled state */ void crypto_set_iv(uint64_t iv[]) { int i; crypto_wait_busy(); for (i = 0; i < 4; i++) { CRYP_IVR(i) = iv[i]; } } /** * @brief Set the order of the data to be crypted * * @param[in] datatype enum crypto_datatype Specified datatype of the key. */ void crypto_set_datatype(enum crypto_datatype datatype) { CRYP_CR = (CRYP_CR & ~CRYP_CR_DATATYPE) | (datatype << CRYP_CR_DATATYPE_SHIFT); } /** * @brief Set the algoritm for Encryption/decryption * *@param[in] mode enum crypto_mode Mode of execution */ void crypto_set_algorithm(enum crypto_mode mode) { mode &= ~CRYP_CR_ALGOMODE_MASK; if ((mode == DECRYPT_AES_ECB) || (mode == DECRYPT_AES_CBC)) { /* Unroll keys for the AES encoder for the user automatically */ CRYP_CR = (CRYP_CR & ~CRYP_CR_ALGOMODE_MASK) | CRYP_CR_ALGOMODE_AES_PREP; crypto_start(); crypto_wait_busy(); /* module switches to DISABLE automatically */ } /* set algo mode */ CRYP_CR = (CRYP_CR & ~CRYP_CR_ALGOMODE_MASK) | mode; /* flush buffers */ CRYP_CR |= CRYP_CR_FFLUSH; } /** * @brief Enable the cryptographic controller and start processing */ void crypto_start(void) { CRYP_CR |= CRYP_CR_CRYPEN; } /** * @brief Disable the cryptographic controller and stop processing */ void crypto_stop(void) { CRYP_CR &= ~CRYP_CR_CRYPEN; } /** * @brief Start of encryption or decryption on data buffers * * This blocking method transfers input buffer of specified length to the * cryptographic coprocessor, and instructs him to begin of ciphering or * deciphering. It waits for data to be ready, and then fills the processed * data to output buffer. * * @param[in] inp uint32_t* Input array to crypt/decrypt. * @param[in] outp uint32_t* Output array with crypted/encrypted data. * @param[in] length uint32_t Length of the arrays * * @returns uint32_t Number of written words */ uint32_t crypto_process_block(uint32_t *inp, uint32_t *outp, uint32_t length) { uint32_t rd = 0, wr = 0; /* Transfer the data */ while (rd != length) { if ((wr < length) && (CRYP_SR & CRYP_SR_IFNF)) { CRYP_DIN = *inp++; wr++; } if (CRYP_SR & CRYP_SR_OFNE) { *outp++ = CRYP_DOUT; rd++; } } /* Wait to finish - Not needed ? */ crypto_wait_busy(); return wr; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/dac_common_all.c000066400000000000000000000353271435536612600236040ustar00rootroot00000000000000/** @addtogroup dac_file @author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net This library supports the Digital to Analog Conversion System in the STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. The DAC is present only in a limited set of devices, notably some of the connection line, high density and XL devices. Two DAC channels are available, however unlike the ADC channels these are separate DAC devices controlled by the same register block. The DAC is on APB1. Its clock must be enabled in RCC and the GPIO ports set to alternate function output before it can be used. The digital output driver is disabled so the output driver mode (push-pull/open drain) is arbitrary. The DAC has a holding (buffer) register and an output register from which the analog output is derived. The holding register must be loaded first. If triggering is enabled the output register is loaded from the holding register after a trigger occurs. If triggering is not enabled the holding register contents are transferred directly to the output register. @note To avoid nonlinearities, do not allow outputs to range close to zero or V_analog. @section dac_api_dual Dual Channel Conversion There are dual modes in which both DACs are used to output data simultaneously or independently on both channels. The data must be presented according to the formats described in the datasheets. A convenience function @ref dac_load_data_buffer_dual is provided for software controlled use. A variety of modes are available depending on whether independent or simultaneous output is desired, and whether waveforms are to be superimposed. Refer to the datasheets. If DMA is used, only enable it for one of the channels. The DMA requests will then serve data in dual format to the data register dedicated to dual mode. The data will then be split and loaded to the appropriate DAC following the next trigger. There are three registers available, one for each of the formats: 12 bit right-aligned, 12 bit left-aligned and 8 bit right-aligned. The desired format is determined by specifying the appropriate register to the DMA controller. @section dac_api_basic_ex Basic DAC handling API. Set the DAC's GPIO port to any alternate function output mode. Enable the DAC clock. Enable the DAC, set a trigger source and load the buffer with the first value. After the DAC is triggered, load the buffer with the next value. This example uses software triggering and added noise. The trigger and further buffer load calls are made when data is to be sent out. @code gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4); rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN); dac_disable(CHANNEL_1); dac_set_waveform_characteristics(DAC_CR_MAMP1_8); dac_set_waveform_generation(DAC_CR_WAVE1_NOISE); dac_enable(CHANNEL_1); dac_set_trigger_source(DAC_CR_TSEL1_SW); dac_load_data_buffer_single(0, RIGHT12, CHANNEL_1); .... dac_software_trigger(CHANNEL_1); dac_load_data_buffer_single(value, RIGHT12, CHANNEL_1); @endcode @section dac_api_dma_ex Simultaneous Dual DAC with DMA. This example in part sets up the DAC channel 1 DMA (DMA2 channel 3) to read 16 bit data from memory into the right-aligned 8 bit dual register DAC_DHR8RD. Both DAC channels are enabled, and both triggers are set to the same timer 2 input as required for simultaneous operation. DMA is enabled for DAC channel 1 only to ensure that only one DMA request is generated. @code dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT); dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT); dma_set_read_from_memory(DMA2,DMA_CHANNEL3); dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(uint32_t) &DAC_DHR8RD); dma_enable_channel(DMA2,DMA_CHANNEL3); ... dac_trigger_enable(CHANNEL_D); dac_set_trigger_source(DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2); dac_dma_enable(CHANNEL_1); dac_enable(CHANNEL_D); @endcode LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #define MASK8 0xFF #define MASK12 0xFFF /*---------------------------------------------------------------------------*/ /** @brief DAC Channel Enable. Enable a digital to analog converter channel. After setting this enable, the DAC requires a twakeup time typically around 10 microseconds before it actually wakes up. @param[in] dac_channel enum ::data_channel. */ void dac_enable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR |= DAC_CR_EN1; break; case CHANNEL_2: DAC_CR |= DAC_CR_EN2; break; case CHANNEL_D: DAC_CR |= (DAC_CR_EN1 | DAC_CR_EN2); break; } } /*---------------------------------------------------------------------------*/ /** @brief DAC Channel Disable. Disable a digital to analog converter channel. @param[in] dac_channel enum ::data_channel. */ void dac_disable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR &= ~DAC_CR_EN1; break; case CHANNEL_2: DAC_CR &= ~DAC_CR_EN2; break; case CHANNEL_D: DAC_CR &= ~(DAC_CR_EN1 | DAC_CR_EN2); break; } } /*---------------------------------------------------------------------------*/ /** @brief DAC Channel Output Buffer Enable. Enable a digital to analog converter channel output drive buffer. This is an optional amplifying buffer that provides additional drive for the output signal. The buffer is enabled by default after a reset and needs to be explicitly disabled if required. @param[in] dac_channel enum ::data_channel. */ void dac_buffer_enable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR |= DAC_CR_BOFF1; break; case CHANNEL_2: DAC_CR |= DAC_CR_BOFF2; break; case CHANNEL_D: DAC_CR |= (DAC_CR_BOFF1 | DAC_CR_BOFF2); break; } } /*---------------------------------------------------------------------------*/ /** @brief DAC Channel Output Buffer Disable. Disable a digital to analog converter channel output drive buffer. Disabling this will reduce power consumption slightly and will increase the output impedance of the DAC. The buffers are enabled by default after a reset. @param[in] dac_channel enum ::data_channel. */ void dac_buffer_disable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR &= ~DAC_CR_BOFF1; break; case CHANNEL_2: DAC_CR &= ~DAC_CR_BOFF2; break; case CHANNEL_D: DAC_CR &= ~(DAC_CR_BOFF1 | DAC_CR_BOFF2); break; } } /*---------------------------------------------------------------------------*/ /** @brief DAC Channel DMA Enable. Enable a digital to analog converter channel DMA mode (connected to DMA2 channel 3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is generated following an external trigger. @param[in] dac_channel enum ::data_channel. */ void dac_dma_enable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR |= DAC_CR_DMAEN1; break; case CHANNEL_2: DAC_CR |= DAC_CR_DMAEN2; break; case CHANNEL_D: DAC_CR |= (DAC_CR_DMAEN1 | DAC_CR_DMAEN2); break; } } /*---------------------------------------------------------------------------*/ /** @brief DAC Channel DMA Disable. Disable a digital to analog converter channel DMA mode. @param[in] dac_channel enum ::data_channel. */ void dac_dma_disable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR &= ~DAC_CR_DMAEN1; break; case CHANNEL_2: DAC_CR &= ~DAC_CR_DMAEN2; break; case CHANNEL_D: DAC_CR &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2); break; } } /*---------------------------------------------------------------------------*/ /** @brief DAC Channel Trigger Enable. Enable a digital to analog converter channel external trigger mode. This allows an external trigger to initiate register transfers from the buffer register to the DAC output register, followed by a DMA transfer to the buffer register if DMA is enabled. The trigger source must also be selected. @param[in] dac_channel enum ::data_channel. */ void dac_trigger_enable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR |= DAC_CR_TEN1; break; case CHANNEL_2: DAC_CR |= DAC_CR_TEN2; break; case CHANNEL_D: DAC_CR |= (DAC_CR_TEN1 | DAC_CR_TEN2); break; } } /*---------------------------------------------------------------------------*/ /** @brief DAC Channel Trigger Disable. Disable a digital to analog converter channel external trigger. @param[in] dac_channel enum ::data_channel. */ void dac_trigger_disable(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR &= ~DAC_CR_TEN1; break; case CHANNEL_2: DAC_CR &= ~DAC_CR_TEN2; break; case CHANNEL_D: DAC_CR &= ~(DAC_CR_TEN1 | DAC_CR_TEN2); break; } } /*---------------------------------------------------------------------------*/ /** @brief Set DAC Channel Trigger Source. Sets the digital to analog converter trigger source, which can be taken from various timers, an external trigger or a software trigger. @param[in] dac_trig_src uint32_t. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or a logical OR of one of each of these to set both channels simultaneously. */ void dac_set_trigger_source(uint32_t dac_trig_src) { DAC_CR |= dac_trig_src; } /*---------------------------------------------------------------------------*/ /** @brief Enable and Set DAC Channel Waveform Generation. Enable the digital to analog converter waveform generation as either pseudo-random noise or triangular wave. These signals are superimposed on existing output values in the DAC output registers. @note The DAC trigger must be enabled for this to work. @param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref dac_wave2_en or a logical OR of one of each of these to set both channels simultaneously. */ void dac_set_waveform_generation(uint32_t dac_wave_ens) { DAC_CR |= dac_wave_ens; } /*---------------------------------------------------------------------------*/ /** @brief Disable DAC Channel Waveform Generation. Disable a digital to analog converter channel superimposed waveform generation. @param[in] dac_channel enum ::data_channel. */ void dac_disable_waveform_generation(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_CR &= ~DAC_CR_WAVE1_DIS; break; case CHANNEL_2: DAC_CR &= ~DAC_CR_WAVE2_DIS; break; case CHANNEL_D: DAC_CR &= ~(DAC_CR_WAVE1_DIS | DAC_CR_WAVE2_DIS); break; } } /*---------------------------------------------------------------------------*/ /** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude. Sets the digital to analog converter superimposed waveform generation characteristics. @li If the noise generation mode is set, this sets the length of the PRBS sequence and hence the amplitude of the output noise signal. Default setting is length 1. @li If the triangle wave generation mode is set, this sets the amplitude of the output signal as 2^(n)-1 where n is the parameter value. Default setting is 1. @note High amplitude levels of these waveforms can overload the DAC and distort the signal output. @note This must be called before enabling the DAC as the settings will then become read-only. @note The DAC trigger must be enabled for this to work. @param[in] dac_mamp uint32_t. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR of one of each of these to set both channels simultaneously. */ void dac_set_waveform_characteristics(uint32_t dac_mamp) { DAC_CR |= dac_mamp; } /*---------------------------------------------------------------------------*/ /** @brief Load DAC Data Register. Loads the appropriate digital to analog converter data register with 12 or 8 bit data to be converted on a channel. The data can be aligned as follows: @li right-aligned 8 bit data in bits 0-7 @li right-aligned 12 bit data in bits 0-11 @li left aligned 12 bit data in bits 4-15 @param[in] dac_data uint16_t with appropriate alignment. @param[in] dac_data_format enum ::data_align. Alignment and size. @param[in] dac_channel enum ::data_channel. */ void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, data_channel dac_channel) { if (dac_channel == CHANNEL_1) { switch (dac_data_format) { case RIGHT8: DAC_DHR8R1 = dac_data; break; case RIGHT12: DAC_DHR12R1 = dac_data; break; case LEFT12: DAC_DHR12L1 = dac_data; break; } } else if (dac_channel == CHANNEL_2) { switch (dac_data_format) { case RIGHT8: DAC_DHR8R2 = dac_data; break; case RIGHT12: DAC_DHR12R2 = dac_data; break; case LEFT12: DAC_DHR12L2 = dac_data; break; } } } /*---------------------------------------------------------------------------*/ /** @brief Load DAC Dual Data Register. Loads the appropriate digital to analog converter dual data register with 12 or 8 bit data to be converted for both channels. This allows high bandwidth simultaneous or independent analog output. The data in both channels are aligned identically. @param[in] dac_data1 uint16_t for channel 1 with appropriate alignment. @param[in] dac_data2 uint16_t for channel 2 with appropriate alignment. @param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit. */ void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, data_align dac_data_format) { switch (dac_data_format) { case RIGHT8: DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8)); break; case RIGHT12: DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); break; case LEFT12: DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); break; } } /*---------------------------------------------------------------------------*/ /** @brief Trigger the DAC by a Software Trigger. If the trigger source is set to be a software trigger, cause a trigger to occur. The trigger is cleared by hardware after conversion. @param[in] dac_channel enum ::data_channel. */ void dac_software_trigger(data_channel dac_channel) { switch (dac_channel) { case CHANNEL_1: DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG1; break; case CHANNEL_2: DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG2; break; case CHANNEL_D: DAC_SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2); break; } } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/dma_common_f24.c000066400000000000000000000673421435536612600234430ustar00rootroot00000000000000/** @addtogroup dma_file @author @htmlonly © @endhtmlonly 2012 Ken Sarkies This library supports the DMA Control System in the STM32F2 and STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. Up to two DMA controllers are supported each with 8 streams, and each stream having up to 8 channels hardware dedicated to various peripheral DMA signals. DMA transfers can be configured to occur between peripheral and memory in either direction, and memory to memory. Peripheral to peripheral transfer is not supported. Circular mode transfers are also supported in transfers involving a peripheral. An arbiter is provided to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit words. Each stream has access to a 4 word deep FIFO and can use double buffering by means of two memory pointers. When using the FIFO it is possible to configure transfers to occur in indivisible bursts. It is also possible to select a peripheral instead of the DMA controller to control the flow of data. This limits the functionality but is useful when the number of transfers is unknown. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Reset The specified stream is disabled and configuration registers are cleared. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_stream_reset(uint32_t dma, uint8_t stream) { /* Disable stream (must be done before register is otherwise changed). */ DMA_SCR(dma, stream) &= ~DMA_SxCR_EN; /* Reset all config bits. */ DMA_SCR(dma, stream) = 0; /* Reset data transfer number. */ DMA_SNDTR(dma, stream) = 0; /* Reset peripheral and memory addresses. */ DMA_SPAR(dma, stream) = 0; DMA_SM0AR(dma, stream) = 0; DMA_SM1AR(dma, stream) = 0; /* This is the default setting */ DMA_SFCR(dma, stream) = 0x21; /* Reset all stream interrupt flags using the interrupt flag clear register. */ uint32_t mask = DMA_ISR_MASK(stream); if (stream < 4) { DMA_LIFCR(dma) |= mask; } else { DMA_HIFCR(dma) |= mask; } } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Clear Interrupt Flag The interrupt flag for the stream is cleared. More than one interrupt for the same stream may be cleared by using the bitwise OR of the interrupt flags. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref dma_if_offset */ void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts) { /* Get offset to interrupt flag location in stream field */ uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream)); /* First four streams are in low register. Flag clear must be set then * reset. */ if (stream < 4) { DMA_LIFCR(dma) = flags; } else { DMA_HIFCR(dma) = flags; } } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Read Interrupt Flag The interrupt flag for the stream is returned. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] interrupt unsigned int32. Interrupt number: @ref dma_if_offset @returns bool interrupt flag is set. */ bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt) { /* get offset to interrupt flag location in stream field. Assumes * stream and interrupt parameters are integers. */ uint32_t flag = (interrupt << DMA_ISR_OFFSET(stream)); /* First four streams are in low register */ if (stream < 4) { return ((DMA_LISR(dma) & flag) > 0); } else { return ((DMA_HISR(dma) & flag) > 0); } } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Transfer Direction Set peripheral to memory, memory to peripheral or memory to memory. If memory to memory mode is selected, circular mode and double buffer modes are disabled. Ensure that these modes are not enabled at a later time. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir */ void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction) { uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK); /* Disable circular and double buffer modes if memory to memory * transfers are in effect. (Direct Mode is automatically disabled by * hardware) */ if (direction == DMA_SxCR_DIR_MEM_TO_MEM) { reg32 &= ~(DMA_SxCR_CIRC | DMA_SxCR_DBM); } DMA_SCR(dma, stream) = (reg32 | direction); } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Priority Stream Priority has four levels: low to very high. This has precedence over the hardware priority. In the event of equal software priority the lower numbered stream has priority. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] prio unsigned int32. Priority level @ref dma_st_pri. */ void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio) { DMA_SCR(dma, stream) &= ~(DMA_SxCR_PL_MASK); DMA_SCR(dma, stream) |= prio; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Memory Word Width Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for alignment information if the source and destination widths do not match. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth. */ void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size) { DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK); DMA_SCR(dma, stream) |= mem_size; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Peripheral Word Width Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for alignment information if the source and destination widths do not match, or if the peripheral does not support byte or half-word writes. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_st_perwidth. */ void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size) { DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK); DMA_SCR(dma, stream) |= peripheral_size; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Memory Increment after Transfer Following each transfer the current memory address is incremented by 1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The value held by the base memory address register is unchanged. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) |= DMA_SxCR_MINC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Memory Increment after Transfer Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer Following each transfer the current peripheral address is incremented by 1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The value held by the base peripheral address register is unchanged. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream) { uint32_t reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC); DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS); } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Peripheral Increment after Transfer Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer Following each transfer the current peripheral address is incremented by 4 regardless of the data size. The value held by the base peripheral address register is unchanged. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS); } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Memory Circular Mode After the number of bytes/words to be transferred has been completed, the original transfer block size, memory and peripheral base addresses are reloaded and the process repeats. Ensure that the stream is disabled otherwise the setting will not be changed. @note This cannot be used with memory to memory mode. It is disabled automatically if the peripheral is selected as the flow controller. It is enabled automatically if double buffered mode is selected. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_circular_mode(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) |= DMA_SxCR_CIRC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Channel Select Associate an input channel to the stream. Not every channel is allocated to a hardware DMA request signal. The allocations for each stream are given in the STM32F4 Reference Manual. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] channel unsigned int8. Channel selection @ref dma_ch_sel */ void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel) { DMA_SCR(dma, stream) |= channel; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Memory Burst Configuration Set the memory burst type to none, 4 8 or 16 word length. This is forced to none if direct mode is used. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst */ void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst) { uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK); DMA_SCR(dma, stream) = (reg32 | burst); } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Peripheral Burst Configuration Set the memory burst type to none, 4 8 or 16 word length. This is forced to none if direct mode is used. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst */ void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst) { uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK); DMA_SCR(dma, stream) = (reg32 | burst); } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Initial Target Memory In double buffered mode, set the target memory (M0 or M1) to be used for the first transfer. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1 */ void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory) { uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT); if (memory == 1) { reg32 |= DMA_SxCR_CT; } DMA_SCR(dma, stream) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Read Current Memory Target In double buffer mode, return the current memory target (M0 or M1). It is possible to update the memory pointer in the register that is not currently in use. An attempt to change the register currently in use will cause the stream to be disabled and the transfer error flag to be set. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @returns unsigned int8. Memory buffer in use: 0 or 1 */ uint8_t dma_get_target(uint32_t dma, uint8_t stream) { if (DMA_SCR(dma, stream) & DMA_SxCR_CT) { return 1; } return 0; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Double Buffer Mode Double buffer mode is used for memory to/from peripheral transfers only, and in circular mode which is automatically enabled. Two memory buffers must be established with pointers stored in the memory pointer registers. Ensure that the stream is disabled otherwise the setting will not be changed. @note This cannot be used with memory to memory mode. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) |= DMA_SxCR_DBM; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Double Buffer Mode @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Peripheral Flow Control Set the peripheral to control DMA flow. Useful when the number of transfers is unknown. This is forced off when memory to memory mode is selected. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set DMA Flow Control Set the DMA controller to control DMA flow. This is the default. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_set_dma_flow_control(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream) { dma_clear_interrupt_flags(dma, stream, DMA_TEIF); DMA_SCR(dma, stream) |= DMA_SxCR_TEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream) { dma_clear_interrupt_flags(dma, stream, DMA_HTIF); DMA_SCR(dma, stream) |= DMA_SxCR_HTIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream) { dma_clear_interrupt_flags(dma, stream, DMA_TCIF); DMA_SCR(dma, stream) |= DMA_SxCR_TCIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Direct Mode Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream) { dma_clear_interrupt_flags(dma, stream, DMA_DMEIF); DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Direct Mode Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Enable Interrupt on FIFO Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream) { dma_clear_interrupt_flags(dma, stream, DMA_FEIF); DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Disable Interrupt on FIFO Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream) { DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Get FIFO Status Status of FIFO (empty. full or partial filled states) is returned. This has no meaning if direct mode is enabled (as the FIFO is not used). @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @returns uint32_t FIFO Status @ref dma_fifo_status */ uint32_t dma_fifo_status(uint32_t dma, uint8_t stream) { return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK; } /*---------------------------------------------------------------------------*/ /** @brief DMA Enable Direct Mode Direct mode is the default. Data is transferred as soon as a DMA request is received. The FIFO is not used. This must not be set when memory to memory mode is selected. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_direct_mode(uint32_t dma, uint8_t stream) { DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS; } /*---------------------------------------------------------------------------*/ /** @brief DMA Enable FIFO Mode Data is transferred via a FIFO. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_fifo_mode(uint32_t dma, uint8_t stream) { DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS; } /*---------------------------------------------------------------------------*/ /** @brief DMA Set FIFO Threshold This is the filled level at which data is transferred out of the FIFO to the destination. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh */ void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold) { uint32_t reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK); DMA_SFCR(dma, stream) = (reg32 | threshold); } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_enable_stream(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) |= DMA_SxCR_EN; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable @note The DMA stream registers retain their values when the stream is disabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number */ void dma_disable_stream(uint32_t dma, uint8_t stream) { DMA_SCR(dma, stream) &= ~DMA_SxCR_EN; } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Peripheral Address Set the address of the peripheral register to or from which data is to be transferred. Refer to the documentation for the specific peripheral. @note The DMA stream must be disabled before setting this address. This function has no effect if the stream is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] address unsigned int32. Peripheral Address. */ void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address) { if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) { DMA_SPAR(dma, stream) = (uint32_t *) address; } } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Base Memory Address 0 Set the address pointer to the memory location for DMA transfers. The DMA stream must normally be disabled before setting this address, however it is possible to change this in double buffer mode when the current target is memory area 1 (see @ref dma_get_target). This is the default base memory address used in direct mode. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] address unsigned int32. Memory Initial Address. */ void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address) { uint32_t reg32 = DMA_SCR(dma, stream); if (!(reg32 & DMA_SxCR_EN) || ((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) { DMA_SM0AR(dma, stream) = (uint32_t *) address; } } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Base Memory Address 1 Set the address pointer to the memory location for DMA transfers. The DMA stream must normally be disabled before setting this address, however it is possible to change this in double buffer mode when the current target is memory area 0 (see @ref dma_get_target). @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] address unsigned int32. Memory Initial Address. */ void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address) { uint32_t reg32 = DMA_SCR(dma, stream); if (!(reg32 & DMA_SxCR_EN) || (!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) { DMA_SM1AR(dma, stream) = (uint32_t *) address; } } /*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Transfer Block Size @note The DMA stream must be disabled before setting this count value. The count is not changed if the stream is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @param[in] number unsigned int16. Number of data words to transfer (65535 maximum). */ void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number) { DMA_SNDTR(dma, stream) = number; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/dma_common_l1f013.c000066400000000000000000000362361435536612600237540ustar00rootroot00000000000000/** @addtogroup dma_file @author @htmlonly © @endhtmlonly 2010 Thomas Otto This library supports the DMA Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics. Up to two DMA controllers are supported. 12 DMA channels are allocated 7 to the first DMA controller and 5 to the second. Each channel is connected to between 3 and 6 hardware peripheral DMA signals in a logical OR arrangement. DMA transfers can be configured to occur between peripheral and memory in any combination including memory to memory. Circular mode transfers are also supported in transfers involving a peripheral. An arbiter is provided to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit words. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Reset The channel is disabled and configuration registers are cleared. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_channel_reset(uint32_t dma, uint8_t channel) { /* Disable channel and reset config bits. */ DMA_CCR(dma, channel) = 0; /* Reset data transfer number. */ DMA_CNDTR(dma, channel) = 0; /* Reset peripheral address. */ DMA_CPAR(dma, channel) = 0; /* Reset memory address. */ DMA_CMAR(dma, channel) = 0; /* Reset interrupt flags. */ DMA_IFCR(dma) |= DMA_IFCR_CIF(channel); } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Clear Interrupt Flag The interrupt flag for the channel is cleared. More than one interrupt for the same channel may be cleared by using the logical OR of the interrupt flags. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: @ref dma_ch @param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset */ void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts) { /* Get offset to interrupt flag location in channel field */ uint32_t flags = (interrupts << DMA_FLAG_OFFSET(channel)); DMA_IFCR(dma) = flags; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Read Interrupt Flag The interrupt flag for the channel is returned. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: @ref dma_ch @param[in] interrupt unsigned int32. Interrupt number: @ref dma_if_offset @returns bool interrupt flag is set. */ bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupt) { /* get offset to interrupt flag location in channel field. */ uint32_t flag = (interrupt << DMA_FLAG_OFFSET(channel)); return ((DMA_ISR(dma) & flag) > 0); } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory to Memory Transfers Memory to memory transfers do not require a trigger to activate each transfer. Transfers begin immediately the channel has been enabled, and proceed without intervention. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM; DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set Priority Channel Priority has four levels: low to very high. This has precedence over the hardware priority. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @param[in] prio unsigned int32. Priority level @ref dma_ch_pri. */ void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio) { DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK); DMA_CCR(dma, channel) |= prio; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set Memory Word Width Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for alignment information if the source and destination widths do not match. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth. */ void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size) { DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK); DMA_CCR(dma, channel) |= mem_size; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set Peripheral Word Width Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for alignment information if the source and destination widths do not match, or if the peripheral does not support byte or half-word writes. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth. */ void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size) { DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK); DMA_CCR(dma, channel) |= peripheral_size; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory Increment after Transfer Following each transfer the current memory address is incremented by 1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The value held by the base memory address register is unchanged. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_MINC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Memory Increment after Transfer @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_MINC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Peripheral Increment after Transfer Following each transfer the current peripheral address is incremented by 1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The value held by the base peripheral address register is unchanged. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_PINC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Peripheral Increment after Transfer @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_PINC; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory Circular Mode After the number of bytes/words to be transferred has been completed, the original transfer block size, memory and peripheral base addresses are reloaded and the process repeats. @note This cannot be used with memory to memory mode, which is explictly disabled here. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_circular_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_CIRC; DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Transfers from a Peripheral The data direction is set to read from a peripheral. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_DIR; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Transfers from Memory The data direction is set to read from memory. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_set_read_from_memory(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_DIR; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_TEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_HTIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_TCIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_enable_channel(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_EN; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable @note The DMA channel registers retain their values when the channel is disabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 */ void dma_disable_channel(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_EN; } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set the Peripheral Address Set the address of the peripheral register to or from which data is to be transferred. Refer to the documentation for the specific peripheral. @note The DMA channel must be disabled before setting this address. This function has no effect if the channel is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @param[in] address unsigned int32. Peripheral Address. */ void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address) { if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) { DMA_CPAR(dma, channel) = (uint32_t) address; } } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set the Base Memory Address @note The DMA channel must be disabled before setting this address. This function has no effect if the channel is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @param[in] address unsigned int32. Memory Initial Address. */ void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address) { if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) { DMA_CMAR(dma, channel) = (uint32_t) address; } } /*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set the Transfer Block Size @note The DMA channel must be disabled before setting this count value. The count is not changed if the channel is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @param[in] number unsigned int16. Number of data words to transfer (65535 maximum). */ void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number) { DMA_CNDTR(dma, channel) = number; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/exti_common_all.c000066400000000000000000000064001435536612600240140ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Mark Butler * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * * This provides the code for the "next gen" EXTI block provided in F2/F4/L1 * devices. (differences only in the source selection) */ #include #include #include #if !defined(AFIO_BASE) # include #endif void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig) { switch (trig) { case EXTI_TRIGGER_RISING: EXTI_RTSR |= extis; EXTI_FTSR &= ~extis; break; case EXTI_TRIGGER_FALLING: EXTI_RTSR &= ~extis; EXTI_FTSR |= extis; break; case EXTI_TRIGGER_BOTH: EXTI_RTSR |= extis; EXTI_FTSR |= extis; break; } } void exti_enable_request(uint32_t extis) { /* Enable interrupts. */ EXTI_IMR |= extis; /* Enable events. */ EXTI_EMR |= extis; } void exti_disable_request(uint32_t extis) { /* Disable interrupts. */ EXTI_IMR &= ~extis; /* Disable events. */ EXTI_EMR &= ~extis; } /* * Reset the interrupt request by writing a 1 to the corresponding * pending bit register. */ void exti_reset_request(uint32_t extis) { EXTI_PR = extis; } /* * Check the flag of a given EXTI interrupt. * */ uint32_t exti_get_flag_status(uint32_t exti) { return EXTI_PR & exti; } /* * Remap an external interrupt line to the corresponding pin on the * specified GPIO port. * * TODO: This could be rewritten in fewer lines of code. */ void exti_select_source(uint32_t exti, uint32_t gpioport) { uint32_t line; for (line = 0; line < 16; line++) { if (!(exti & (1 << line))) { continue; } uint32_t bits = 0, mask = 0x0F; switch (gpioport) { case GPIOA: bits = 0; break; case GPIOB: bits = 1; break; case GPIOC: bits = 2; break; case GPIOD: bits = 3; break; #if defined(GPIOE) && defined(GPIO_PORT_E_BASE) case GPIOE: bits = 4; break; #endif #if defined(GPIOF) && defined(GPIO_PORT_F_BASE) case GPIOF: bits = 5; break; #endif #if defined(GPIOG) && defined(GPIO_PORT_G_BASE) case GPIOG: bits = 6; break; #endif #if defined(GPIOH) && defined(GPIO_PORT_H_BASE) case GPIOH: bits = 7; break; #endif #if defined(GPIOI) && defined(GPIO_PORT_I_BASE) case GPIOI: bits = 8; break; #endif } uint8_t shift = (uint8_t)(4 * (line % 4)); uint32_t reg = line / 4; bits <<= shift; mask <<= shift; #if defined(AFIO_BASE) AFIO_EXTICR(reg) = (AFIO_EXTICR(reg) & ~mask) | bits; #else SYSCFG_EXTICR(reg) = (SYSCFG_EXTICR(reg) & ~mask) | bits; #endif }; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/flash_common_f234.c000066400000000000000000000030571435536612600240530ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void flash_set_ws(uint32_t ws) { uint32_t reg32; reg32 = FLASH_ACR; reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2)); reg32 |= ws; FLASH_ACR = reg32; } void flash_unlock(void) { /* Clear the unlock sequence state. */ FLASH_CR |= FLASH_CR_LOCK; /* Authorize the FPEC access. */ FLASH_KEYR = FLASH_KEYR_KEY1; FLASH_KEYR = FLASH_KEYR_KEY2; } void flash_lock(void) { FLASH_CR |= FLASH_CR_LOCK; } void flash_clear_pgperr_flag(void) { FLASH_SR |= FLASH_SR_PGPERR; } void flash_clear_eop_flag(void) { FLASH_SR |= FLASH_SR_EOP; } void flash_clear_bsy_flag(void) { FLASH_SR &= ~FLASH_SR_BSY; } void flash_wait_for_last_operation(void) { while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY); } hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/flash_common_f24.c000066400000000000000000000115521435536612600237670ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include static inline void flash_set_program_size(uint32_t psize) { FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8); FLASH_CR |= psize; } void flash_dcache_enable(void) { FLASH_ACR |= FLASH_ACR_DCE; } void flash_dcache_disable(void) { FLASH_ACR &= ~FLASH_ACR_DCE; } void flash_icache_enable(void) { FLASH_ACR |= FLASH_ACR_ICE; } void flash_icache_disable(void) { FLASH_ACR &= ~FLASH_ACR_ICE; } void flash_prefetch_enable(void) { FLASH_ACR |= FLASH_ACR_PRFTEN; } void flash_prefetch_disable(void) { FLASH_ACR &= ~FLASH_ACR_PRFTEN; } void flash_dcache_reset(void) { FLASH_ACR |= FLASH_ACR_DCRST; } void flash_icache_reset(void) { FLASH_ACR |= FLASH_ACR_ICRST; } void flash_clear_pgserr_flag(void) { FLASH_SR |= FLASH_SR_PGSERR; } void flash_clear_pgaerr_flag(void) { FLASH_SR |= FLASH_SR_PGAERR; } void flash_clear_wrperr_flag(void) { FLASH_SR |= FLASH_SR_WRPERR; } void flash_clear_status_flags(void) { flash_clear_pgserr_flag(); flash_clear_pgaerr_flag(); flash_clear_wrperr_flag(); flash_clear_pgperr_flag(); flash_clear_eop_flag(); flash_clear_bsy_flag(); } void flash_unlock_option_bytes(void) { /* Clear the unlock state. */ FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK; /* Unlock option bytes. */ FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; } void flash_lock_option_bytes(void) { FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK; } void flash_program_double_word(uint32_t address, uint64_t data) { /* Ensure that all flash operations are complete. */ flash_wait_for_last_operation(); flash_set_program_size(FLASH_CR_PROGRAM_X64); /* Enable writes to flash. */ FLASH_CR |= FLASH_CR_PG; /* Program the first half of the word. */ MMIO64(address) = data; /* Wait for the write to complete. */ flash_wait_for_last_operation(); /* Disable writes to flash. */ FLASH_CR &= ~FLASH_CR_PG; } void flash_program_word(uint32_t address, uint32_t data) { /* Ensure that all flash operations are complete. */ flash_wait_for_last_operation(); flash_set_program_size(FLASH_CR_PROGRAM_X32); /* Enable writes to flash. */ FLASH_CR |= FLASH_CR_PG; /* Program the first half of the word. */ MMIO32(address) = data; /* Wait for the write to complete. */ flash_wait_for_last_operation(); /* Disable writes to flash. */ FLASH_CR &= ~FLASH_CR_PG; } void flash_program_half_word(uint32_t address, uint16_t data) { flash_wait_for_last_operation(); flash_set_program_size(FLASH_CR_PROGRAM_X16); FLASH_CR |= FLASH_CR_PG; MMIO16(address) = data; flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */ } void flash_program_byte(uint32_t address, uint8_t data) { flash_wait_for_last_operation(); flash_set_program_size(FLASH_CR_PROGRAM_X8); FLASH_CR |= FLASH_CR_PG; MMIO8(address) = data; flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */ } void flash_program(uint32_t address, uint8_t *data, uint32_t len) { /* TODO: Use dword and word size program operations where possible for * turbo speed. */ uint32_t i; for (i = 0; i < len; i++) { flash_program_byte(address+i, data[i]); } } void flash_erase_sector(uint8_t sector, uint32_t program_size) { flash_wait_for_last_operation(); flash_set_program_size(program_size); FLASH_CR &= ~(0xF << 3); FLASH_CR |= (sector << 3) & 0x78; FLASH_CR |= FLASH_CR_SER; FLASH_CR |= FLASH_CR_STRT; flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_SER; FLASH_CR &= ~(0xF << 3); } void flash_erase_all_sectors(uint32_t program_size) { flash_wait_for_last_operation(); flash_set_program_size(program_size); FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */ flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */ } void flash_program_option_bytes(uint32_t data) { flash_wait_for_last_operation(); if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) { flash_unlock_option_bytes(); } FLASH_OPTCR = data & ~0x3; FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte prog. */ flash_wait_for_last_operation(); } hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/gpio_common_all.c000066400000000000000000000116041435536612600240030ustar00rootroot00000000000000/** @addtogroup gpio_file @author @htmlonly © @endhtmlonly 2009 Uwe Hermann */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #define WEAK __attribute__((weak)) #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief Set a Group of Pins Atomic Set one or more pins of the given GPIO port to 1 in an atomic operation. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use logical OR '|' to separate them. */ void gpio_set(uint32_t gpioport, uint16_t gpios) { GPIO_BSRR(gpioport) = gpios; } /*---------------------------------------------------------------------------*/ /** @brief Clear a Group of Pins Atomic Clear one or more pins of the given GPIO port to 0 in an atomic operation. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use logical OR '|' to separate them. */ void gpio_clear(uint32_t gpioport, uint16_t gpios) { GPIO_BSRR(gpioport) = (gpios << 16); } /*---------------------------------------------------------------------------*/ /** @brief Read a Group of Pins. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be read, use logical OR '|' to separate them. @return Unsigned int16 value of the pin values. The bit position of the pin value returned corresponds to the pin number. */ uint16_t gpio_get(uint32_t gpioport, uint16_t gpios) { return gpio_port_read(gpioport) & gpios; } /*---------------------------------------------------------------------------*/ /** @brief Toggle a Group of Pins Toggle one or more pins of the given GPIO port. This is not an atomic operation. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be changed, use logical OR '|' to separate them. */ void gpio_toggle(uint32_t gpioport, uint16_t gpios) { GPIO_ODR(gpioport) ^= gpios; } /*---------------------------------------------------------------------------*/ /** @brief Read from a Port Read the current value of the given GPIO port. Only the lower 16 bits contain valid pin data. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @return Unsigned int16. The value held in the specified GPIO port. */ uint16_t gpio_port_read(uint32_t gpioport) { return (uint16_t)GPIO_IDR(gpioport); } /*---------------------------------------------------------------------------*/ /** @brief Write to a Port Write a value to the given GPIO port. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] data Unsigned int16. The value to be written to the GPIO port. */ void gpio_port_write(uint32_t gpioport, uint16_t data) { GPIO_ODR(gpioport) = data; } /*---------------------------------------------------------------------------*/ /** @brief Lock the Configuration of a Group of Pins The configuration of one or more pins of the given GPIO port is locked. There is no mechanism to unlock these via software. Unlocking occurs at the next reset. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be locked, use logical OR '|' to separate them. */ void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios) { uint32_t reg32; /* Special "Lock Key Writing Sequence", see datasheet. */ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ /* Tell the compiler the variable is actually used. It will get * optimized out anyways. */ reg32 = reg32; /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/gpio_common_f0234.c000066400000000000000000000147421435536612600237770ustar00rootroot00000000000000/** @addtogroup gpio_file @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2012 Ken Sarkies Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO functionality with a number of alternate functions and must be configured to the alternate function mode if these are to be accessed. A feature is available to remap alternative functions to a limited set of alternative pins in the event of a clash of requirements. The data registers associated with each port for input and output are 32 bit with the upper 16 bits unused. The output buffer must be written as a 32 bit word, but individual bits may be set or reset separately in atomic operations to avoid race conditions during interrupts. Bits may also be individually locked to prevent accidental configuration changes. Once locked the configuration cannot be changed until after the next reset. Each port bit can be configured as analog or digital input, the latter can be floating or pulled up or down. As outputs they can be configured as either push-pull or open drain, digital I/O or alternate function, and with maximum output speeds of 2MHz, 10MHz, or 50MHz. On reset all ports are configured as digital floating input. @section gpio_api_ex Basic GPIO Handling API. Example 1: Push-pull digital output actions with pullup on ports C2 and C9 @code gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO2 | GPIO9); gpio_output_options(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO2 | GPIO9); gpio_set(GPIOC, GPIO2 | GPIO9); gpio_clear(GPIOC, GPIO2); gpio_toggle(GPIOC, GPIO2 | GPIO9); gpio_port_write(GPIOC, 0x204); @endcode Example 2: Digital input on port C12 with pullup @code gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO12); reg16 = gpio_port_read(GPIOC); @endcode */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief Set GPIO Pin Mode Sets the Pin Direction and Analog/Digital Mode, and Output Pin Pullup, for a set of GPIO pins on a given GPIO port. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] mode Unsigned int8. Pin mode @ref gpio_mode @param[in] pull_up_down Unsigned int8. Pin pullup/pulldown configuration @ref gpio_pup @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be set, use bitwise OR '|' to separate them. */ void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios) { uint16_t i; uint32_t moder, pupd; /* * We want to set the config only for the pins mentioned in gpios, * but keeping the others, so read out the actual config first. */ moder = GPIO_MODER(gpioport); pupd = GPIO_PUPDR(gpioport); for (i = 0; i < 16; i++) { if (!((1 << i) & gpios)) { continue; } moder &= ~GPIO_MODE_MASK(i); moder |= GPIO_MODE(i, mode); pupd &= ~GPIO_PUPD_MASK(i); pupd |= GPIO_PUPD(i, pull_up_down); } /* Set mode and pull up/down control registers. */ GPIO_MODER(gpioport) = moder; GPIO_PUPDR(gpioport) = pupd; } /*---------------------------------------------------------------------------*/ /** @brief Set GPIO Output Options When the pin is set to output mode, this sets the configuration (analog/digital and open drain/push pull) and speed, for a set of GPIO pins on a given GPIO port. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] otype Unsigned int8. Pin output type @ref gpio_output_type @param[in] speed Unsigned int8. Pin speed @ref gpio_speed @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be set, use bitwise OR '|' to separate them. */ void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios) { uint16_t i; uint32_t ospeedr; if (otype == 0x1) { GPIO_OTYPER(gpioport) |= gpios; } else { GPIO_OTYPER(gpioport) &= ~gpios; } ospeedr = GPIO_OSPEEDR(gpioport); for (i = 0; i < 16; i++) { if (!((1 << i) & gpios)) { continue; } ospeedr &= ~GPIO_OSPEED_MASK(i); ospeedr |= GPIO_OSPEED(i, speed); } GPIO_OSPEEDR(gpioport) = ospeedr; } /*---------------------------------------------------------------------------*/ /** @brief Set GPIO Alternate Function Selection Set the alternate function mapping number for each pin. Most pins have alternate functions associated with them. When set to AF mode, a pin may be used for one of its allocated alternate functions selected by the number given here. To determine the number to be used for the desired function refer to the individual datasheet for the particular device. A table is given under the Pin Selection chapter. Note that a number of pins may be set but only with a single AF number. In practice this would rarely be useful as each pin is likely to require a different number. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] alt_func_num Unsigned int8. Pin alternate function number @ref gpio_af_num @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be set, use bitwise OR '|' to separate them. */ void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios) { uint16_t i; uint32_t afrl, afrh; afrl = GPIO_AFRL(gpioport); afrh = GPIO_AFRH(gpioport); for (i = 0; i < 8; i++) { if (!((1 << i) & gpios)) { continue; } afrl &= ~GPIO_AFR_MASK(i); afrl |= GPIO_AFR(i, alt_func_num); } for (i = 8; i < 16; i++) { if (!((1 << i) & gpios)) { continue; } afrh &= ~GPIO_AFR_MASK(i - 8); afrh |= GPIO_AFR(i - 8, alt_func_num); } GPIO_AFRL(gpioport) = afrl; GPIO_AFRH(gpioport) = afrh; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/hash_common_f24.c000066400000000000000000000076331435536612600236220ustar00rootroot00000000000000/** @addtogroup hash_file @author @htmlonly © @endhtmlonly 2013 Mikhail Avkhimenia This library supports the HASH processor in the STM32F2 and STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Mikhail Avkhimenia * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief HASH Set Mode Sets up the specified mode - either HASH or HMAC. @param[in] mode unsigned int8. Hash processor mode: @ref hash_mode */ void hash_set_mode(uint8_t mode) { HASH_CR &= ~HASH_CR_MODE; HASH_CR |= mode; } /*---------------------------------------------------------------------------*/ /** @brief HASH Set Algorithm Sets up the specified algorithm - either MD5 or SHA1. @param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm */ void hash_set_algorithm(uint8_t algorithm) { HASH_CR &= ~HASH_CR_ALGO; HASH_CR |= algorithm; } /*---------------------------------------------------------------------------*/ /** @brief HASH Set Data Type Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring. @param[in] datatype unsigned int8. Hash data type: @ref hash_data_type */ void hash_set_data_type(uint8_t datatype) { HASH_CR &= ~HASH_CR_DATATYPE; HASH_CR |= datatype; } /*---------------------------------------------------------------------------*/ /** @brief HASH Set Key Length Sets up the specified key length: Long, Short. @param[in] keylength unsigned int8. Hash data type: @ref hash_key_length */ void hash_set_key_length(uint8_t keylength) { HASH_CR &= ~HASH_CR_LKEY; HASH_CR |= keylength; } /*---------------------------------------------------------------------------*/ /** @brief HASH Set Last Word Valid Bits Specifies the number of valid bits in the last word. @param[in] validbits unsigned int8. Number of valid bits. */ void hash_set_last_word_valid_bits(uint8_t validbits) { HASH_STR &= ~(HASH_STR_NBW); HASH_STR |= 32 - validbits; } /*---------------------------------------------------------------------------*/ /** @brief HASH Init Initializes the HASH processor. */ void hash_init() { HASH_CR |= HASH_CR_INIT; } /*---------------------------------------------------------------------------*/ /** @brief HASH Add data Puts data into the HASH processor's queue. @param[in] data unsigned int32. Hash input data. */ void hash_add_data(uint32_t data) { HASH_DIN = data; } /*---------------------------------------------------------------------------*/ /** @brief HASH Digest Starts the processing of the last data block. */ void hash_digest() { HASH_STR |= HASH_STR_DCAL; } /*---------------------------------------------------------------------------*/ /** @brief HASH Get Hash Result Makes a copy of the resulting hash. @param[out] data unsigned int32. Hash 4\5 words long depending on the algorithm. @param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm */ void hash_get_result(uint32_t *data) { data[0] = HASH_HR[0]; data[1] = HASH_HR[1]; data[2] = HASH_HR[2]; data[3] = HASH_HR[3]; if ((HASH_CR & HASH_CR_ALGO) == HASH_ALGO_SHA1) { data[4] = HASH_HR[4]; } } hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/i2c_common_all.c000066400000000000000000000303561435536612600235270ustar00rootroot00000000000000/** @addtogroup i2c_file @author @htmlonly © @endhtmlonly 2010 Thomas Otto @author @htmlonly © @endhtmlonly 2012 Ken Sarkies Devices can have up to two I2C peripherals. The peripherals support SMBus and PMBus variants. A peripheral begins after reset in Slave mode. To become a Master a start condition must be generated. The peripheral will remain in Master mode unless a multimaster contention is lost or a stop condition is generated. @todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status register access, Error conditions */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief I2C Reset. The I2C peripheral and all its associated configuration registers are placed in the reset condition. The reset is effected via the RCC peripheral reset system. @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. */ void i2c_reset(uint32_t i2c) { switch (i2c) { case I2C1: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); break; case I2C2: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); break; } } /*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Enable. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_peripheral_enable(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_PE; } /*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Disable. This must not be reset while in Master mode until a communication has finished. In Slave mode, the peripheral is disabled only after communication has ended. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_peripheral_disable(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_PE; } /*---------------------------------------------------------------------------*/ /** @brief I2C Send Start Condition. If in Master mode this will cause a restart condition to occur at the end of the current transmission. If in Slave mode, this will initiate a start condition when the current bus activity is completed. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_send_start(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_START; } /*---------------------------------------------------------------------------*/ /** @brief I2C Send Stop Condition. After the current byte transfer this will initiate a stop condition if in Master mode, or simply release the bus if in Slave mode. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_send_stop(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_STOP; } /*---------------------------------------------------------------------------*/ /** @brief I2C Clear Stop Flag. Clear the "Send Stop" flag in the I2C config register @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_clear_stop(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_STOP; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set the 7 bit Slave Address for the Peripheral. This sets an address for Slave mode operation, in 7 bit form. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] slave Unsigned int8. Slave address 0...127. */ void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave) { I2C_OAR1(i2c) = (uint16_t)(slave << 1); I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE; I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ } /*---------------------------------------------------------------------------*/ /** @brief I2C Set the 10 bit Slave Address for the Peripheral. This sets an address for Slave mode operation, in 10 bit form. @todo add "I2C_OAR1(i2c) |= (1 << 14);" as above @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] slave Unsigned int16. Slave address 0...1023. */ void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave) { I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_ADDMODE | slave); } /*---------------------------------------------------------------------------*/ /** @brief I2C Set Peripheral Clock Frequency. Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that this is not the I2C bus clock. This is set in conjunction with the Clock Control register to generate the Master bus clock, see @ref i2c_set_ccr @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. */ void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq) { uint16_t reg16; reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */ reg16 |= freq; I2C_CR2(i2c) = reg16; } /*---------------------------------------------------------------------------*/ /** @brief I2C Send Data. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] data Unsigned int8. Byte to send. */ void i2c_send_data(uint32_t i2c, uint8_t data) { I2C_DR(i2c) = data; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set Fast Mode. Set the clock frequency to the high clock rate mode (up to 400kHz). The actual clock frequency must be set with @ref i2c_set_clock_frequency @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_set_fast_mode(uint32_t i2c) { I2C_CCR(i2c) |= I2C_CCR_FS; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set Standard Mode. Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual clock frequency must be set with @ref i2c_set_clock_frequency @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_set_standard_mode(uint32_t i2c) { I2C_CCR(i2c) &= ~I2C_CCR_FS; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set Bus Clock Frequency. Set the bus clock frequency. This is a 12 bit number (0...4095) calculated from the formulae given in the STM32F1 reference manual in the description of the CCR field. It is a divisor of the peripheral clock frequency @ref i2c_set_clock_frequency modified by the fast mode setting @ref i2c_set_fast_mode @todo provide additional API assitance to set the clock, eg macros @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095. */ void i2c_set_ccr(uint32_t i2c, uint16_t freq) { uint16_t reg16; reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */ reg16 |= freq; I2C_CCR(i2c) = reg16; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set the Rise Time. Set the maximum rise time on the bus according to the I2C specification, as 1 more than the specified rise time in peripheral clock cycles. This is a 6 bit number. @todo provide additional APIP assistance. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] trise Unsigned int16. Rise Time Setting 0...63. */ void i2c_set_trise(uint32_t i2c, uint16_t trise) { I2C_TRISE(i2c) = trise; } /*---------------------------------------------------------------------------*/ /** @brief I2C Send the 7-bit Slave Address. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] slave Unsigned int16. Slave address 0...1023. @param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. */ void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite) { I2C_DR(i2c) = (uint8_t)((slave << 1) | readwrite); } /*---------------------------------------------------------------------------*/ /** @brief I2C Get Data. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ uint8_t i2c_get_data(uint32_t i2c) { return I2C_DR(i2c) & 0xff; } /*---------------------------------------------------------------------------*/ /** @brief I2C Enable Interrupt @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] interrupt Unsigned int32. Interrupt to enable. */ void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt) { I2C_CR2(i2c) |= interrupt; } /*---------------------------------------------------------------------------*/ /** @brief I2C Disable Interrupt @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] interrupt Unsigned int32. Interrupt to disable. */ void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt) { I2C_CR2(i2c) &= ~interrupt; } /*---------------------------------------------------------------------------*/ /** @brief I2C Enable ACK Enables acking of own 7/10 bit address @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_enable_ack(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_ACK; } /*---------------------------------------------------------------------------*/ /** @brief I2C Disable ACK Disables acking of own 7/10 bit address @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_disable_ack(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_ACK; } /*---------------------------------------------------------------------------*/ /** @brief I2C NACK Next Byte Causes the I2C controller to NACK the reception of the next byte @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_nack_next(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_POS; } /*---------------------------------------------------------------------------*/ /** @brief I2C NACK Next Byte Causes the I2C controller to NACK the reception of the current byte @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_nack_current(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_POS; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set clock duty cycle @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle. */ void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle) { if (dutycycle == I2C_CCR_DUTY_DIV2) { I2C_CCR(i2c) &= ~I2C_CCR_DUTY; } else { I2C_CCR(i2c) |= I2C_CCR_DUTY; } } /*---------------------------------------------------------------------------*/ /** @brief I2C Enable DMA @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_enable_dma(uint32_t i2c) { I2C_CR2(i2c) |= I2C_CR2_DMAEN; } /*---------------------------------------------------------------------------*/ /** @brief I2C Disable DMA @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_disable_dma(uint32_t i2c) { I2C_CR2(i2c) &= ~I2C_CR2_DMAEN; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set DMA last transfer @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_set_dma_last_transfer(uint32_t i2c) { I2C_CR2(i2c) |= I2C_CR2_LAST; } /*---------------------------------------------------------------------------*/ /** @brief I2C Clear DMA last transfer @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_clear_dma_last_transfer(uint32_t i2c) { I2C_CR2(i2c) &= ~I2C_CR2_LAST; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/iwdg_common_all.c000066400000000000000000000110331435536612600237730ustar00rootroot00000000000000/** @addtogroup iwdg_file @author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net This library supports the Independent Watchdog Timer System in the STM32F1xx series of ARM Cortex Microcontrollers by ST Microelectronics. The watchdog timer uses the LSI (low speed internal) clock which is low power and continues to operate during stop and standby modes. Its frequency is nominally 32kHz (40kHz for the STM32F1xx series) but can vary from as low as 17kHz up to 60kHz (refer to datasheet electrical characteristics). Note that the User Configuration option byte provides a means of automatically enabling the IWDG timer at power on (with counter value 0xFFF). If the relevant bit is not set, the IWDG timer must be enabled by software. @note: Tested: CPU STM32F103RET6, Board ET-ARM Stamp STM32 */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #define LSI_FREQUENCY 32000 #define COUNT_LENGTH 12 #define COUNT_MASK ((1 << COUNT_LENGTH)-1) /*---------------------------------------------------------------------------*/ /** @brief IWDG Enable Watchdog Timer The watchdog timer is started. The timeout period defaults to 512 milliseconds unless it has been previously defined. */ void iwdg_start(void) { IWDG_KR = IWDG_KR_START; } /*---------------------------------------------------------------------------*/ /** @brief IWDG Set Period in Milliseconds The countdown period is converted into count and prescale values. The maximum period is 32.76 seconds; values above this are truncated. Periods less than 1ms are not supported by this library. A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) can occasionally occur if the prescale or preload registers are currently busy loading a previous value. @param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset until a system reset is issued. */ void iwdg_set_period_ms(uint32_t period) { uint32_t count, prescale, reload, exponent; /* Set the count to represent ticks of the 32kHz LSI clock */ count = (period << 5); /* Strip off the first 12 bits to get the prescale value required */ prescale = (count >> 12); if (prescale > 256) { exponent = IWDG_PR_DIV256; reload = COUNT_MASK; } else if (prescale > 128) { exponent = IWDG_PR_DIV256; reload = (count >> 8); } else if (prescale > 64) { exponent = IWDG_PR_DIV128; reload = (count >> 7); } else if (prescale > 32) { exponent = IWDG_PR_DIV64; reload = (count >> 6); } else if (prescale > 16) { exponent = IWDG_PR_DIV32; reload = (count >> 5); } else if (prescale > 8) { exponent = IWDG_PR_DIV16; reload = (count >> 4); } else if (prescale > 4) { exponent = IWDG_PR_DIV8; reload = (count >> 3); } else { exponent = IWDG_PR_DIV4; reload = (count >> 2); } /* Avoid the undefined situation of a zero count */ if (count == 0) { count = 1; } while (iwdg_prescaler_busy()); IWDG_KR = IWDG_KR_UNLOCK; IWDG_PR = exponent; while (iwdg_reload_busy()); IWDG_KR = IWDG_KR_UNLOCK; IWDG_RLR = (reload & COUNT_MASK); } /*---------------------------------------------------------------------------*/ /** @brief IWDG Get Reload Register Status @returns boolean: TRUE if the reload register is busy and unavailable for loading a new count value. */ bool iwdg_reload_busy(void) { return IWDG_SR & IWDG_SR_RVU; } /*---------------------------------------------------------------------------*/ /** @brief IWDG Get Prescaler Register Status @returns boolean: TRUE if the prescaler register is busy and unavailable for loading a new period value. */ bool iwdg_prescaler_busy(void) { return IWDG_SR & IWDG_SR_PVU; } /*---------------------------------------------------------------------------*/ /** @brief IWDG reset Watchdog Timer The watchdog timer is reset. The counter restarts from the value in the reload register. */ void iwdg_reset(void) { IWDG_KR = IWDG_KR_RESET; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/pwr_common_all.c000066400000000000000000000121151435536612600236530ustar00rootroot00000000000000/** @addtogroup pwr_file PWR @author @htmlonly © @endhtmlonly 2012 Ken Sarkies */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief Disable Backup Domain Write Protection. This allows backup domain registers to be changed. These registers are write protected after a reset. */ void pwr_disable_backup_domain_write_protect(void) { PWR_CR |= PWR_CR_DBP; } /*---------------------------------------------------------------------------*/ /** @brief Re-enable Backup Domain Write Protection. This protects backup domain registers from inadvertent change. */ void pwr_enable_backup_domain_write_protect(void) { PWR_CR &= ~PWR_CR_DBP; } /*---------------------------------------------------------------------------*/ /** @brief Enable Power Voltage Detector. This provides voltage level threshold detection. The result of detection is provided in the power voltage detector output flag (see @ref pwr_voltage_high) or by setting the EXTI16 interrupt (see datasheet for configuration details). @param[in] pvd_level uint32_t. Taken from @ref pwr_pls. */ void pwr_enable_power_voltage_detect(uint32_t pvd_level) { PWR_CR &= ~PWR_CR_PLS_MASK; PWR_CR |= (PWR_CR_PVDE | pvd_level); } /*---------------------------------------------------------------------------*/ /** @brief Disable Power Voltage Detector. */ void pwr_disable_power_voltage_detect(void) { PWR_CR &= ~PWR_CR_PVDE; } /*---------------------------------------------------------------------------*/ /** @brief Clear the Standby Flag. This is set when the processor returns from a standby mode. */ void pwr_clear_standby_flag(void) { PWR_CR |= PWR_CR_CSBF; } /*---------------------------------------------------------------------------*/ /** @brief Clear the Wakeup Flag. This is set when the processor receives a wakeup signal. */ void pwr_clear_wakeup_flag(void) { PWR_CR |= PWR_CR_CWUF; } /*---------------------------------------------------------------------------*/ /** @brief Set Standby Mode in Deep Sleep. */ void pwr_set_standby_mode(void) { PWR_CR |= PWR_CR_PDDS; } /*---------------------------------------------------------------------------*/ /** @brief Set Stop Mode in Deep Sleep. */ void pwr_set_stop_mode(void) { PWR_CR &= ~PWR_CR_PDDS; } /*---------------------------------------------------------------------------*/ /** @brief Voltage Regulator On in Stop Mode. */ void pwr_voltage_regulator_on_in_stop(void) { PWR_CR &= ~PWR_CR_LPDS; } /*---------------------------------------------------------------------------*/ /** @brief Voltage Regulator Low Power in Stop Mode. */ void pwr_voltage_regulator_low_power_in_stop(void) { PWR_CR |= PWR_CR_LPDS; } /*---------------------------------------------------------------------------*/ /** @brief Enable Wakeup Pin. The wakeup pin is used for waking the processor from standby mode. */ void pwr_enable_wakeup_pin(void) { PWR_CSR |= PWR_CSR_EWUP; } /*---------------------------------------------------------------------------*/ /** @brief Release Wakeup Pin. The wakeup pin is used for general purpose I/O. */ void pwr_disable_wakeup_pin(void) { PWR_CSR &= ~PWR_CSR_EWUP; } /*---------------------------------------------------------------------------*/ /** @brief Get Voltage Detector Output. The voltage detector threshold must be set when the power voltage detector is enabled, see @ref pwr_enable_power_voltage_detect. @returns boolean: TRUE if the power voltage is above the preset voltage threshold. */ bool pwr_voltage_high(void) { return PWR_CSR & PWR_CSR_PVDO; } /*---------------------------------------------------------------------------*/ /** @brief Get Standby Flag. The standby flag is set when the processor returns from a standby state. It is cleared by software (see @ref pwr_clear_standby_flag). @returns boolean: TRUE if the processor was in standby state. */ bool pwr_get_standby_flag(void) { return PWR_CSR & PWR_CSR_SBF; } /*---------------------------------------------------------------------------*/ /** @brief Get Wakeup Flag. The wakeup flag is set when a wakeup event has been received. It is cleared by software (see @ref pwr_clear_wakeup_flag). @returns boolean: TRUE if a wakeup event was received. */ bool pwr_get_wakeup_flag(void) { return PWR_CSR & PWR_CSR_WUF; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/rtc_common_l1f024.c000066400000000000000000000067121435536612600240010ustar00rootroot00000000000000/** @addtogroup rtc_file @author @htmlonly © @endhtmlonly 2012 Karl Palsson */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief Set RTC prescalars. This sets the RTC synchronous and asynchronous prescalars. */ void rtc_set_prescaler(uint32_t sync, uint32_t async) { /* * Even if only one of the two fields needs to be changed, * 2 separate write accesses must be performed to the RTC_PRER register. */ RTC_PRER = (sync & RTC_PRER_PREDIV_S_MASK); RTC_PRER |= (async << RTC_PRER_PREDIV_A_SHIFT); } /*---------------------------------------------------------------------------*/ /** @brief Wait for RTC registers to be synchronised with the APB1 bus Time and Date are accessed through shadow registers which must be synchronized */ void rtc_wait_for_synchro(void) { /* Unlock RTC registers */ RTC_WPR = 0xca; RTC_WPR = 0x53; RTC_ISR &= ~(RTC_ISR_RSF); while (!(RTC_ISR & RTC_ISR_RSF)); /* disable write protection again */ RTC_WPR = 0xff; } /*---------------------------------------------------------------------------*/ /** @brief Unlock write access to the RTC registers */ void rtc_unlock(void) { RTC_WPR = 0xca; RTC_WPR = 0x53; } /*---------------------------------------------------------------------------*/ /** @brief Lock write access to the RTC registers */ void rtc_lock(void) { RTC_WPR = 0xff; } /*---------------------------------------------------------------------------*/ /** @brief Sets the wakeup time auto-reload value */ void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel) { /* FTFM: * The following sequence is required to configure or change the wakeup * timer auto-reload value (WUT[15:0] in RTC_WUTR): * 1. Clear WUTE in RTC_CR to disable the wakeup timer. */ RTC_CR &= ~RTC_CR_WUTE; /* 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to * wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed. * It takes around 2 RTCCLK clock cycles (due to clock * synchronization). */ while (!((RTC_ISR) & (RTC_ISR_WUTWF))); /* 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup * clock selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR * to enable the timer again. The wakeup timer restarts * down-counting. */ RTC_WUTR = wkup_time; RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT); RTC_CR |= RTC_CR_WUTE; } /*---------------------------------------------------------------------------*/ /** @brief Clears the wakeup flag @details This function should be called first in the rtc_wkup_isr() */ void rtc_clear_wakeup_flag(void) { RTC_ISR &= ~RTC_ISR_WUTF; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/spi_common_all.c000066400000000000000000000475731435536612600236560ustar00rootroot00000000000000/** @addtogroup spi_file @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2012 Ken Sarkies Devices can have up to three SPI peripherals. The common 4-wire full-duplex mode of operation is supported, along with 3-wire variants using unidirectional communication modes or half-duplex bidirectional communication. A variety of options allows many of the SPI variants to be supported. Multimaster operation is also supported. A CRC can be generated and checked in hardware. @note Some JTAG pins need to be remapped if SPI is to be used. @note The I2S protocol shares the SPI hardware so the two protocols cannot be used at the same time on the same peripheral. Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, LSB first. @code spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_LSBFIRST); spi_write(SPI1, 0x55); // 8-bit write spi_write(SPI1, 0xaa88); // 16-bit write reg8 = spi_read(SPI1); // 8-bit read reg16 = spi_read(SPI1); // 16-bit read @endcode @todo need additional functions to aid ISRs in retrieving status */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /* * SPI and I2S code. * * Examples: * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, * SPI_CR1_LSBFIRST); * spi_write(SPI1, 0x55); // 8-bit write * spi_write(SPI1, 0xaa88); // 16-bit write * reg8 = spi_read(SPI1); // 8-bit read * reg16 = spi_read(SPI1); // 16-bit read */ /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief SPI Reset. The SPI peripheral and all its associated configuration registers are placed in the reset condition. The reset is effected via the RCC peripheral reset system. @param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_reset(uint32_t spi_peripheral) { /* there is another way of resetting mechanism on F0. It will be extended to all families of stm32 and this function will be deprecated and deleted in the future.*/ #if !defined(STM32F0) switch (spi_peripheral) { case SPI1: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST); break; case SPI2: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST); break; #if defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) case SPI3: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST); break; #endif } #endif } /* TODO: Error handling? */ /*---------------------------------------------------------------------------*/ /** @brief SPI Enable. The SPI peripheral is enabled. @todo Error handling? @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */ } /* TODO: Error handling? */ /*---------------------------------------------------------------------------*/ /** @brief SPI Disable. The SPI peripheral is disabled. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable(uint32_t spi) { uint32_t reg32; reg32 = SPI_CR1(spi); reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ SPI_CR1(spi) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief SPI Clean Disable. Disable the SPI peripheral according to the procedure in section 23.3.8 of the reference manual. This prevents corruption of any ongoing transfers and prevents the BSY flag from becoming unreliable. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @returns data Unsigned int16. 8 or 16 bit data from final read. */ uint16_t spi_clean_disable(uint32_t spi) { /* Wait to receive last data */ while (!(SPI_SR(spi) & SPI_SR_RXNE)); uint16_t data = SPI_DR(spi); /* Wait to transmit last data */ while (!(SPI_SR(spi) & SPI_SR_TXE)); /* Wait until not busy */ while (SPI_SR(spi) & SPI_SR_BSY); SPI_CR1(spi) &= ~SPI_CR1_SPE; return data; } /*---------------------------------------------------------------------------*/ /** @brief SPI Data Write. Data is written to the SPI interface. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] data Unsigned int16. 8 or 16 bit data to be written. */ void spi_write(uint32_t spi, uint16_t data) { /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; } /*---------------------------------------------------------------------------*/ /** @brief SPI Data Write with Blocking. Data is written to the SPI interface after the previous write transfer has finished. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] data Unsigned int16. 8 or 16 bit data to be written. */ void spi_send(uint32_t spi, uint16_t data) { /* Wait for transfer finished. */ while (!(SPI_SR(spi) & SPI_SR_TXE)); /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; } /*---------------------------------------------------------------------------*/ /** @brief SPI Data Read. Data is read from the SPI interface after the incoming transfer has finished. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @returns data Unsigned int16. 8 or 16 bit data. */ uint16_t spi_read(uint32_t spi) { /* Wait for transfer finished. */ while (!(SPI_SR(spi) & SPI_SR_RXNE)); /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ return SPI_DR(spi); } /*---------------------------------------------------------------------------*/ /** @brief SPI Data Write and Read Exchange. Data is written to the SPI interface, then a read is done after the incoming transfer has finished. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] data Unsigned int16. 8 or 16 bit data to be written. @returns data Unsigned int16. 8 or 16 bit data. */ uint16_t spi_xfer(uint32_t spi, uint16_t data) { spi_write(spi, data); /* Wait for transfer finished. */ while (!(SPI_SR(spi) & SPI_SR_RXNE)); /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ return SPI_DR(spi); } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Bidirectional Simplex Mode. The SPI peripheral is set for bidirectional transfers in two-wire simplex mode (using a clock wire and a bidirectional data wire). @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_bidirectional_mode(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Unidirectional Mode. The SPI peripheral is set for unidirectional transfers. This is used in full duplex mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a unidirectional data wire. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_unidirectional_mode(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Bidirectional Simplex Receive Only Mode. The SPI peripheral is set for bidirectional transfers in two-wire simplex mode (using a clock wire and a bidirectional data wire), and is placed in a receive state. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_bidirectional_receive_only_mode(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Bidirectional Simplex Receive Only Mode. The SPI peripheral is set for bidirectional transfers in two-wire simplex mode (using a clock wire and a bidirectional data wire), and is placed in a transmit state. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_bidirectional_transmit_only_mode(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; SPI_CR1(spi) |= SPI_CR1_BIDIOE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable the CRC. The SPI peripheral is set to use a CRC field for transmit and receive. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_crc(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_CRCEN; } /*---------------------------------------------------------------------------*/ /** @brief SPI Disable the CRC. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_crc(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_CRCEN; } /*---------------------------------------------------------------------------*/ /** @brief SPI Next Transmit is a Data Word The next transmission to take place is a data word from the transmit buffer. This must be called before transmission to distinguish between sending of a data or CRC word. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_next_tx_from_buffer(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; } /*---------------------------------------------------------------------------*/ /** @brief SPI Next Transmit is a CRC Word The next transmission to take place is a crc word from the hardware crc unit. This must be called before transmission to distinguish between sending of a data or CRC word. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_next_tx_from_crc(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_CRCNEXT; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Full Duplex (3-wire) Mode @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_full_duplex_mode(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_RXONLY; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_receive_only_mode(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_RXONLY; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable Slave Management by Hardware In slave mode the NSS hardware input is used as a select enable for the slave. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_software_slave_management(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_SSM; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable Slave Management by Software In slave mode the NSS hardware input is replaced by an internal software enable/disable of the slave (@ref spi_set_nss_high). @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_software_slave_management(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_SSM; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the Software NSS Signal High In slave mode, and only when software slave management is used, this replaces the NSS signal with a slave select enable signal. @todo these should perhaps be combined with an SSM enable as it is meaningless otherwise @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_nss_high(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_SSI; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the Software NSS Signal Low In slave mode, and only when software slave management is used, this replaces the NSS signal with a slave select disable signal. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_nss_low(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_SSI; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set to Send LSB First @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_send_lsb_first(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_LSBFIRST; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set to Send MSB First @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_send_msb_first(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the Baudrate Prescaler @todo Why is this specification different to the spi_init_master baudrate values? @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre. */ void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate) { uint32_t reg32; if (baudrate > 7) { return; } reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */ reg32 |= (baudrate << 3); SPI_CR1(spi) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set to Master Mode @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_master_mode(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_MSTR; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set to Slave Mode @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_slave_mode(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_MSTR; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Polarity to High when Idle @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_clock_polarity_1(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_CPOL; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Polarity to Low when Idle @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_clock_polarity_0(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_CPOL; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Phase to Capture on Trailing Edge @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_clock_phase_1(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_CPHA; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Phase to Capture on Leading Edge @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_clock_phase_0(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_CPHA; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable the Transmit Buffer Empty Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_tx_buffer_empty_interrupt(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_TXEIE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Disable the Transmit Buffer Empty Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_tx_buffer_empty_interrupt(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_TXEIE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable the Receive Buffer Ready Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_RXNEIE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Disable the Receive Buffer Ready Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable the Error Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_error_interrupt(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_ERRIE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Disable the Error Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_error_interrupt(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_ERRIE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the NSS Pin as an Output Normally used in master mode to allows the master to place all devices on the SPI bus into slave mode. Multimaster mode is not possible. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_ss_output(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_SSOE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set the NSS Pin as an Input In master mode this allows the master to sense the presence of other masters. If NSS is then pulled low the master is placed into slave mode. In slave mode NSS becomes a slave enable. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_ss_output(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_SSOE; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable Transmit Transfers via DMA This allows transmissions to proceed unattended using DMA to move data to the transmit buffer as it becomes available. The DMA channels provided for each SPI peripheral are given in the Technical Manual DMA section. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_tx_dma(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_TXDMAEN; } /*---------------------------------------------------------------------------*/ /** @brief SPI Disable Transmit Transfers via DMA @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_tx_dma(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; } /*---------------------------------------------------------------------------*/ /** @brief SPI Enable Receive Transfers via DMA This allows received data streams to proceed unattended using DMA to move data from the receive buffer as data becomes available. The DMA channels provided for each SPI peripheral are given in the Technical Manual DMA section. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_enable_rx_dma(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_RXDMAEN; } /*---------------------------------------------------------------------------*/ /** @brief SPI Disable Receive Transfers via DMA @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_disable_rx_dma(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/spi_common_f124.c000066400000000000000000000107111435536612600235420ustar00rootroot00000000000000/** @addtogroup spi_file @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2012 Ken Sarkies Devices can have up to three SPI peripherals. The common 4-wire full-duplex mode of operation is supported, along with 3-wire variants using unidirectional communication modes or half-duplex bidirectional communication. A variety of options allows many of the SPI variants to be supported. Multimaster operation is also supported. A CRC can be generated and checked in hardware. @note Some JTAG pins need to be remapped if SPI is to be used. @note The I2S protocol shares the SPI hardware so the two protocols cannot be used at the same time on the same peripheral. Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, LSB first. @code spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_LSBFIRST); spi_write(SPI1, 0x55); // 8-bit write spi_write(SPI1, 0xaa88); // 16-bit write reg8 = spi_read(SPI1); // 8-bit read reg16 = spi_read(SPI1); // 16-bit read @endcode @todo need additional functions to aid ISRs in retrieving status */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /* * SPI and I2S code. * * Examples: * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, * SPI_CR1_LSBFIRST); * spi_write(SPI1, 0x55); // 8-bit write * spi_write(SPI1, 0xaa88); // 16-bit write * reg8 = spi_read(SPI1); // 8-bit read * reg16 = spi_read(SPI1); // 16-bit read */ /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief Configure the SPI as Master. The SPI peripheral is configured as a master with communication parameters baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity and phase. The SPI enable, CRC enable and CRC next controls are not affected. These must be controlled separately. @todo NSS pin handling. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] br Unsigned int32. Baudrate @ref spi_baudrate. @param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. @param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. @param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. @param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst. @returns int. Error code. */ int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst) { uint32_t reg32 = SPI_CR1(spi); /* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */ reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT; reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ reg32 |= br; /* Set baud rate bits. */ reg32 |= cpol; /* Set CPOL value. */ reg32 |= cpha; /* Set CPHA value. */ reg32 |= dff; /* Set data format (8 or 16 bits). */ reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ /* TODO: NSS pin handling. */ SPI_CR1(spi) = reg32; return 0; /* TODO */ } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Data Frame Format to 8 bits @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_dff_8bit(uint32_t spi) { SPI_CR1(spi) &= ~SPI_CR1_DFF; } /*---------------------------------------------------------------------------*/ /** @brief SPI Set Data Frame Format to 16 bits @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ void spi_set_dff_16bit(uint32_t spi) { SPI_CR1(spi) |= SPI_CR1_DFF; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/timer_common_all.c000066400000000000000000001775451435536612600242060ustar00rootroot00000000000000/** @addtogroup timer_file @author @htmlonly © @endhtmlonly 2010 Edward Cheeseman @author @htmlonly © @endhtmlonly 2011 Stephen Caudle @section tim_common Notes for All Timers This library supports the General Purpose and Advanced Control Timers for the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics. The STM32 series have four general purpose timers (2-5), while some have an additional two advanced timers (1,8), and some have two basic timers (6,7). Some of the larger devices have additional general purpose timers (9-14). @todo Add timer DMA burst settings @section tim_api_ex Basic TIMER handling API. Enable the timer clock first. The timer mode sets the clock division ratio, the count alignment (edge or centred) and count direction. Finally enable the timer. The timer output compare block produces a signal that can be configured for output to a pin or passed to other peripherals for use as a trigger. In all cases the output compare mode must be set to define how the output responds to a compare match, and the output must be enabled. If output to a pin is required, enable the appropriate GPIO clock and set the pin to alternate output mode. Example: Timer 2 with 2x clock divide, edge aligned and up counting. @code rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM2EN); timer_reset(TIM2); timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT_MUL_2, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); ... timer_set_period(TIM2, 1000); timer_enable_counter(TIM2); @endcode Example: Timer 1 with PWM output, no clock divide and centre alignment. Set the Output Compare mode to PWM and enable the output of channel 1. Note that for the advanced timers the break functionality must be enabled before the signal will appear at the output, even though break is not being used. This is in addition to the normal output enable. Enable the alternate function clock (APB2 only) and port A clock. Set ports A8 and A9 (timer 1 channel 1 compare outputs) to alternate function push-pull outputs where the PWM output will appear. @code rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO8 | GPIO9); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); timer_reset(TIM1); timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2); timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_break_main_output(TIM1); timer_set_oc_value(TIM1, TIM_OC1, 200); timer_set_period(TIM1, 1000); timer_enable_counter(TIM1); @endcode @todo input capture example */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * Basic TIMER handling API. * * Examples: * timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2, * TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP); */ /**@{*/ #include #include #define ADVANCED_TIMERS (defined(TIM1_BASE) || defined(TIM8_BASE)) /*---------------------------------------------------------------------------*/ /** @brief Reset a Timer. The counter and all its associated configuration registers are placed in the reset condition. The reset is effected via the RCC peripheral reset system. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base (TIM9 .. TIM14 not yet supported here). */ void timer_reset(uint32_t timer_peripheral) { switch (timer_peripheral) { #if defined(TIM1_BASE) case TIM1: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); break; #endif case TIM2: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); break; case TIM3: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); break; case TIM4: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); break; #if defined(TIM5_BASE) case TIM5: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); break; #endif case TIM6: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST); break; case TIM7: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST); break; #if defined(TIM8_BASE) case TIM8: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); break; #endif /* These timers are not supported in libopencm3 yet */ /* case TIM9: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST); break; case TIM10: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); break; case TIM11: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); break; case TIM12: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); break; case TIM13: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); break; case TIM14: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); break; */ } } /*---------------------------------------------------------------------------*/ /** @brief Enable Interrupts for a Timer @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt enable bits to be set */ void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq) { TIM_DIER(timer_peripheral) |= irq; } /*---------------------------------------------------------------------------*/ /** @brief Disable Interrupts for a Timer. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt enable bits to be cleared */ void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq) { TIM_DIER(timer_peripheral) &= ~irq; } /*---------------------------------------------------------------------------*/ /** @brief Return Interrupt Source. Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or COMIF for advanced timers) was set and the interrupt was enabled. If the specified flag is not an interrupt flag, the function returns false. @todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught here. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] flag Unsigned int32. Status register flag @ref tim_sr_values. @returns boolean: flag set. */ bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag) { /* flag not set or interrupt disabled or not an interrupt source */ if (((TIM_SR(timer_peripheral) & TIM_DIER(timer_peripheral) & flag) == 0) || (flag > TIM_SR_BIF)) { return false; } /* Only an interrupt source for advanced timers */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF)) { return (timer_peripheral == TIM1) || (timer_peripheral == TIM8); } #endif return true; } /*---------------------------------------------------------------------------*/ /** @brief Read a Status Flag. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] flag Unsigned int32. Status register flag @ref tim_sr_values. @returns boolean: flag set. */ bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag) { if ((TIM_SR(timer_peripheral) & flag) != 0) { return true; } return false; } /*---------------------------------------------------------------------------*/ /** @brief Clear a Status Flag. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] flag Unsigned int32. @ref tim_sr_values. Status register flag. */ void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag) { TIM_SR(timer_peripheral) &= ~flag; } /*---------------------------------------------------------------------------*/ /** @brief Set the Timer Mode. The modes are: @li Clock divider ratio (to form the sampling clock for the input filters, and the dead-time clock in the advanced timers 1 and 8) @li Edge/centre alignment @li Count direction The alignment and count direction are effective only for timers 1 to 5 and 8 while the clock divider ratio is effective for all timers except 6,7 The remaining timers are limited hardware timers which do not support these mode settings. @note: When center alignment mode is selected, count direction is controlled by hardware and cannot be written. The count direction setting has no effect in this case. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base (TIM1, TIM2 ... TIM5, TIM8) @param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref tim_x_cr1_cdr @param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms @param[in] direction Unsigned int32. Count direction in bit 4,: @ref tim_x_cr1_dir */ void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div, uint32_t alignment, uint32_t direction) { uint32_t cr1; cr1 = TIM_CR1(timer_peripheral); cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | TIM_CR1_CMS_MASK | TIM_CR1_DIR_DOWN); cr1 |= clock_div | alignment | direction; TIM_CR1(timer_peripheral) = cr1; } /*---------------------------------------------------------------------------*/ /** @brief Set Input Filter and Dead-time Clock Divider Ratio. This forms the sampling clock for the input filters and the dead-time clock in the advanced timers 1 and 8, by division from the timer clock. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref tim_x_cr1_cdr */ void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div) { clock_div &= TIM_CR1_CKD_CK_INT_MASK; TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK; TIM_CR1(timer_peripheral) |= clock_div; } /*---------------------------------------------------------------------------*/ /** @brief Enable Auto-Reload Buffering. During counter operation this causes the counter to be loaded from its auto-reload register only at the next update event. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_enable_preload(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE; } /*---------------------------------------------------------------------------*/ /** @brief Disable Auto-Reload Buffering. This causes the counter to be loaded immediately with a new count value when the auto-reload register is written, so that the new value becomes effective for the current count cycle rather than for the cycle following an update event. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_disable_preload(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE; } /*---------------------------------------------------------------------------*/ /** @brief Specify the counter alignment mode. The mode can be edge aligned or centered. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms */ void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment) { alignment &= TIM_CR1_CMS_MASK; TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK; TIM_CR1(timer_peripheral) |= alignment; } /*---------------------------------------------------------------------------*/ /** @brief Set the Timer to Count Up. This has no effect if the timer is set to center aligned. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_direction_up(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN; } /*---------------------------------------------------------------------------*/ /** @brief Set the Timer to Count Down. This has no effect if the timer is set to center aligned. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_direction_down(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN; } /*---------------------------------------------------------------------------*/ /** @brief Enable the Timer for One Cycle and Stop. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_one_shot_mode(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) |= TIM_CR1_OPM; } /*---------------------------------------------------------------------------*/ /** @brief Enable the Timer to Run Continuously. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_continuous_mode(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM; } /*---------------------------------------------------------------------------*/ /** @brief Set the Timer to Generate Update IRQ or DMA on any Event. The events which will generate an interrupt or DMA request can be @li a counter underflow/overflow, @li a forced update, @li an event from the slave mode controller. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_update_on_any(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS; } /*---------------------------------------------------------------------------*/ /** @brief Set the Timer to Generate Update IRQ or DMA only from Under/Overflow Events. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_update_on_overflow(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) |= TIM_CR1_URS; } /*---------------------------------------------------------------------------*/ /** @brief Enable Timer Update Events. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_enable_update_event(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS; } /*---------------------------------------------------------------------------*/ /** @brief Disable Timer Update Events. Update events are not generated and the shadow registers keep their values. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_disable_update_event(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS; } /*---------------------------------------------------------------------------*/ /** @brief Enable the timer to start counting. This should be called after the timer initial configuration has been completed. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_enable_counter(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) |= TIM_CR1_CEN; } /*---------------------------------------------------------------------------*/ /** @brief Stop the timer from counting. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_disable_counter(uint32_t timer_peripheral) { TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN; } /*---------------------------------------------------------------------------*/ /** @brief Set Timer Output Idle States High. This determines the value of the timer output compare when it enters idle state. @sa @ref timer_set_oc_idle_state_set @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref tim_x_cr2_ois. If several settings are to be made, use the logical OR of the output control values. */ void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK; } #else (void)timer_peripheral; (void)outputs; #endif } /*---------------------------------------------------------------------------*/ /** @brief Set Timer Output Idle States Low. This determines the value of the timer output compare when it enters idle state. @sa @ref timer_set_oc_idle_state_unset @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref tim_x_cr2_ois */ void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK); } #else (void)timer_peripheral; (void)outputs; #endif } /*---------------------------------------------------------------------------*/ /** @brief Set Timer 1 Input to XOR of Three Channels. The first timer capture input is formed from the XOR of the first three timer input channels 1, 2, 3. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_set_ti1_ch123_xor(uint32_t timer_peripheral) { TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S; } /*---------------------------------------------------------------------------*/ /** @brief Set Timer 1 Input to Channel 1. The first timer capture input is taken from the timer input channel 1 only. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_set_ti1_ch1(uint32_t timer_peripheral) { TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S; } /*---------------------------------------------------------------------------*/ /** @brief Set the Master Mode This sets the Trigger Output TRGO for synchronizing with slave timers or passing as an internal trigger to the ADC or DAC. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] mode Unsigned int32. Master Mode @ref tim_mastermode */ void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode) { TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK; TIM_CR2(timer_peripheral) |= mode; } /*---------------------------------------------------------------------------*/ /** @brief Set Timer DMA Requests on Capture/Compare Events. Capture/compare events will cause DMA requests to be generated. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_set_dma_on_compare_event(uint32_t timer_peripheral) { TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS; } /*---------------------------------------------------------------------------*/ /** @brief Set Timer DMA Requests on Update Events. Update events will cause DMA requests to be generated. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_set_dma_on_update_event(uint32_t timer_peripheral) { TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS; } /*---------------------------------------------------------------------------*/ /** @brief Enable Timer Capture/Compare Control Update with Trigger. If the capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded, they are updated by software generating the COMG event (@ref timer_generate_event) or when a rising edge occurs on the trigger input TRGI. @note This setting is only valid for the advanced timer channels with complementary outputs. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Disable Timer Capture/Compare Control Update with Trigger. If the capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded, they are updated by software generating the COMG event (@ref timer_generate_event). @note This setting is only valid for the advanced timer channels with complementary outputs. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Enable Timer Capture/Compare Control Preload. The capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded when a COM event occurs. @note This setting is only valid for the advanced timer channels with complementary outputs. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Disable Timer Capture/Compare Control Preload. The capture/compare control bits CCxE, CCxNE and OCxM preload is disabled. @note This setting is only valid for the advanced timer channels with complementary outputs. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base */ void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Set the Value for the Timer Prescaler. The timer clock is prescaled by the 16 bit scale value plus 1. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] value Unsigned int32. Prescaler values 0...0xFFFF. */ void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value) { TIM_PSC(timer_peripheral) = value; } /*---------------------------------------------------------------------------*/ /** @brief Set the Value for the Timer Repetition Counter. A timer update event is generated only after the specified number of repeat count cycles have been completed. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] value Unsigned int32. Repetition values 0...0xFF. */ void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_RCR(timer_peripheral) = value; } #else (void)timer_peripheral; (void)value; #endif } /*---------------------------------------------------------------------------*/ /** @brief Timer Set Period Specify the timer period in the auto-reload register. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] period Unsigned int32. Period in counter clock ticks. */ void timer_set_period(uint32_t timer_peripheral, uint32_t period) { TIM_ARR(timer_peripheral) = period; } /*---------------------------------------------------------------------------*/ /** @brief Timer Enable the Output Compare Clear Function When this is enabled, the output compare signal is cleared when a high is detected on the external trigger input. This works in the output compare and PWM modes only (not forced mode). The output compare signal remains off until the next update event. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1CE; break; case TIM_OC2: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2CE; break; case TIM_OC3: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3CE; break; case TIM_OC4: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4CE; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as oc clear enable only applies to the whole * channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Disable the Output Compare Clear Function @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1CE; break; case TIM_OC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2CE; break; case TIM_OC3: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3CE; break; case TIM_OC4: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4CE; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as oc clear enable only applies to the whole * channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Enable the Output Compare Fast Mode When this is enabled, the output compare signal is forced to the compare state by a trigger input, independently of the compare match. This speeds up the setting of the output compare to 3 clock cycles as opposed to at least 5 in the slow mode. This works in the PWM1 and PWM2 modes only. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE; break; case TIM_OC2: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE; break; case TIM_OC3: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE; break; case TIM_OC4: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as fast enable only applies to the whole channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Enable the Output Compare Slow Mode This disables the fast compare mode and the output compare depends on the counter and compare register values. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1FE; break; case TIM_OC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2FE; break; case TIM_OC3: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3FE; break; case TIM_OC4: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4FE; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to the whole channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Set Output Compare Mode Specifies how the comparator output will respond to a compare match. The mode can be: @li Frozen - the output does not respond to a match. @li Active - the output assumes the active state on the first match. @li Inactive - the output assumes the inactive state on the first match. @li Toggle - The output switches between active and inactive states on each match. @li Force inactive. The output is forced low regardless of the compare state. @li Force active. The output is forced high regardless of the compare state. @li PWM1 - The output is active when the counter is less than the compare register contents and inactive otherwise. @li PWM2 - The output is inactive when the counter is less than the compare register contents and active otherwise. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) @param[in] oc_mode enum ::tim_oc_mode. OC mode designators. TIM_OCM_FROZEN, TIM_OCM_ACTIVE, TIM_OCM_INACTIVE, TIM_OCM_TOGGLE, TIM_OCM_FORCE_LOW, TIM_OCM_FORCE_HIGH, TIM_OCM_PWM1, TIM_OCM_PWM2 */ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT; TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK; switch (oc_mode) { case TIM_OCM_FROZEN: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN; break; case TIM_OCM_ACTIVE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE; break; case TIM_OCM_INACTIVE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE; break; case TIM_OCM_TOGGLE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE; break; case TIM_OCM_FORCE_LOW: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW; break; case TIM_OCM_FORCE_HIGH: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_HIGH; break; case TIM_OCM_PWM1: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1; break; case TIM_OCM_PWM2: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2; break; } break; case TIM_OC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT; TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK; switch (oc_mode) { case TIM_OCM_FROZEN: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN; break; case TIM_OCM_ACTIVE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE; break; case TIM_OCM_INACTIVE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE; break; case TIM_OCM_TOGGLE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE; break; case TIM_OCM_FORCE_LOW: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW; break; case TIM_OCM_FORCE_HIGH: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_HIGH; break; case TIM_OCM_PWM1: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1; break; case TIM_OCM_PWM2: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2; break; } break; case TIM_OC3: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT; TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK; switch (oc_mode) { case TIM_OCM_FROZEN: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN; break; case TIM_OCM_ACTIVE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE; break; case TIM_OCM_INACTIVE: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE; break; case TIM_OCM_TOGGLE: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE; break; case TIM_OCM_FORCE_LOW: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW; break; case TIM_OCM_FORCE_HIGH: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_HIGH; break; case TIM_OCM_PWM1: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1; break; case TIM_OCM_PWM2: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2; break; } break; case TIM_OC4: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT; TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK; switch (oc_mode) { case TIM_OCM_FROZEN: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN; break; case TIM_OCM_ACTIVE: TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE; break; case TIM_OCM_INACTIVE: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE; break; case TIM_OCM_TOGGLE: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE; break; case TIM_OCM_FORCE_LOW: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW; break; case TIM_OCM_FORCE_HIGH: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_HIGH; break; case TIM_OCM_PWM1: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1; break; case TIM_OCM_PWM2: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2; break; } break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to the whole channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Enable the Output Compare Preload Register @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1PE; break; case TIM_OC2: TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2PE; break; case TIM_OC3: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3PE; break; case TIM_OC4: TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4PE; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to the whole channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Disable the Output Compare Preload Register @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action) */ void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1PE; break; case TIM_OC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2PE; break; case TIM_OC3: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3PE; break; case TIM_OC4: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4PE; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to the whole channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Set the Output Polarity High The polarity of the channel output is set active high. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) */ void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1P; break; case TIM_OC2: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2P; break; case TIM_OC3: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3P; break; case TIM_OC4: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4P; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to TIM1 and TIM8 only. */ break; } /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; } #else return; #endif switch (oc_id) { case TIM_OC1N: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NP; break; case TIM_OC2N: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NP; break; case TIM_OC3N: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NP; break; case TIM_OC1: case TIM_OC2: case TIM_OC3: case TIM_OC4: /* Ignoring as this option was already set above. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Set the Output Polarity Low The polarity of the channel output is set active low. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) */ void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCER(timer_peripheral) |= TIM_CCER_CC1P; break; case TIM_OC2: TIM_CCER(timer_peripheral) |= TIM_CCER_CC2P; break; case TIM_OC3: TIM_CCER(timer_peripheral) |= TIM_CCER_CC3P; break; case TIM_OC4: TIM_CCER(timer_peripheral) |= TIM_CCER_CC4P; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to TIM1 and TIM8 only. */ break; } /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; } #else return; #endif switch (oc_id) { case TIM_OC1N: TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NP; break; case TIM_OC2N: TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NP; break; case TIM_OC3N: TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NP; break; case TIM_OC1: case TIM_OC2: case TIM_OC3: case TIM_OC4: /* Ignoring as this option was already set above. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Enable the Output Compare The channel output compare functionality is enabled. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) */ void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCER(timer_peripheral) |= TIM_CCER_CC1E; break; case TIM_OC2: TIM_CCER(timer_peripheral) |= TIM_CCER_CC2E; break; case TIM_OC3: TIM_CCER(timer_peripheral) |= TIM_CCER_CC3E; break; case TIM_OC4: TIM_CCER(timer_peripheral) |= TIM_CCER_CC4E; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to TIM1 and TIM8 only. */ break; } /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; } #else return; #endif switch (oc_id) { case TIM_OC1N: TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NE; break; case TIM_OC2N: TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NE; break; case TIM_OC3N: TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NE; break; case TIM_OC1: case TIM_OC2: case TIM_OC3: case TIM_OC4: /* Ignoring as this option was already set above. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer Disable the Output Compare The channel output compare functionality is disabled. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) */ void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id) { switch (oc_id) { case TIM_OC1: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1E; break; case TIM_OC2: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2E; break; case TIM_OC3: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3E; break; case TIM_OC4: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4E; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to TIM1 and TIM8 only. */ break; } /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; } #else return; #endif switch (oc_id) { case TIM_OC1N: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NE; break; case TIM_OC2N: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NE; break; case TIM_OC3N: TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NE; break; case TIM_OC1: case TIM_OC2: case TIM_OC3: case TIM_OC4: /* Ignoring as this option was already set above. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Timer set Output Compare Idle State High @sa Similar function suitable for multiple OC idle state settings @ref timer_set_output_idle_state @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) */ void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) /* Acting for TIM1 and TIM8 only. */ if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; } switch (oc_id) { case TIM_OC1: TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1; break; case TIM_OC1N: TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1N; break; case TIM_OC2: TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2; break; case TIM_OC2N: TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2N; break; case TIM_OC3: TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3; break; case TIM_OC3N: TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3N; break; case TIM_OC4: TIM_CR2(timer_peripheral) |= TIM_CR2_OIS4; break; } #else (void)timer_peripheral; (void)oc_id; #endif } /*---------------------------------------------------------------------------*/ /** @brief Timer Set Output Compare Idle State Low @sa Similar function suitable for multiple OC idle state settings @ref timer_reset_output_idle_state @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) */ void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) /* Acting for TIM1 and TIM8 only. */ if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; } switch (oc_id) { case TIM_OC1: TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1; break; case TIM_OC1N: TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1N; break; case TIM_OC2: TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2; break; case TIM_OC2N: TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2N; break; case TIM_OC3: TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3; break; case TIM_OC3N: TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3N; break; case TIM_OC4: TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS4; break; } #else (void)timer_peripheral; (void)oc_id; #endif } /*---------------------------------------------------------------------------*/ /** @brief Timer Set Output Compare Value This is a convenience function to set the OC preload register value for loading to the compare register. @param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base (TIM9 .. TIM14 not yet supported here). @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) @param[in] value Unsigned int32. Compare value. */ void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value) { switch (oc_id) { case TIM_OC1: TIM_CCR1(timer_peripheral) = value; break; case TIM_OC2: TIM_CCR2(timer_peripheral) = value; break; case TIM_OC3: TIM_CCR3(timer_peripheral) = value; break; case TIM_OC4: TIM_CCR4(timer_peripheral) = value; break; case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: /* Ignoring as this option applies to the whole channel. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief Enable Output in Break Enables the output in the Break feature of an advanced timer. This does not enable the break functionality itself but only sets the Master Output Enable in the Break and Deadtime Register. @note This setting is only valid for the advanced timers. @note It is necessary to call this function to enable the output on an advanced timer even if break or deadtime features are not being used. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_enable_break_main_output(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Disable Output in Break Disables the output in the Break feature of an advanced timer. This clears the Master Output Enable in the Break and Deadtime Register. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_disable_break_main_output(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Enable Automatic Output in Break Enables the automatic output feature of the Break function of an advanced timer so that the output is re-enabled at the next update event following a break event. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_enable_break_automatic_output(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Disable Automatic Output in Break Disables the automatic output feature of the Break function of an advanced timer so that the output is re-enabled at the next update event following a break event. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_disable_break_automatic_output(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Activate Break when Input High Sets the break function to activate when the break input becomes high. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_set_break_polarity_high(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Activate Break when Input Low Sets the break function to activate when the break input becomes low. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_set_break_polarity_low(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Enable Break Enables the break function of an advanced timer. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_enable_break(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Disable Break Disables the break function of an advanced timer. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_disable_break(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Enable Off-State in Run Mode Enables the off-state in run mode for the break function of an advanced timer in which the complementary outputs have been configured. It has no effect if no complementary output is present. When the capture-compare output is disabled while the complementary output is enabled, the output is set to its inactive level as defined by the output polarity. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Disable Off-State in Run Mode Disables the off-state in run mode for the break function of an advanced timer in which the complementary outputs have been configured. It has no effect if no complementary output is present. When the capture-compare output is disabled, the output is also disabled. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Enable Off-State in Idle Mode Enables the off-state in idle mode for the break function of an advanced timer. When the master output is disabled the output is set to its inactive level as defined by the output polarity. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Disable Off-State in Idle Mode Disables the off-state in idle mode for the break function of an advanced timer. When the master output is disabled the output is also disabled. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 */ void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI; } #else (void)timer_peripheral; #endif } /*---------------------------------------------------------------------------*/ /** @brief Set Lock Bits Set the lock bits for an advanced timer. Three levels of lock providing protection against software errors. Once written they cannot be changed until a timer reset has occurred. @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 @param[in] lock Unsigned int32. Lock specification @ref tim_lock */ void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= lock; } #else (void)timer_peripheral; (void)lock; #endif } /*---------------------------------------------------------------------------*/ /** @brief Set Deadtime The deadtime and sampling clock (DTSC) is set in the clock division ratio part of the timer mode settings. The deadtime count is an 8 bit value defined in terms of the number of DTSC cycles: @li Bit 7 = 0, deadtime = bits(6:0) @li Bits 7:6 = 10, deadtime = 2x(64+bits(5:0)) @li Bits 7:5 = 110, deadtime = 8x(32+bits(5:0)) @li Bits 7:5 = 111, deadtime = 16x(32+bits(5:0)) @note This setting is only valid for the advanced timers. @param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 @param[in] deadtime Unsigned int32. Deadtime count specification as defined above. */ void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= deadtime; } #else (void)timer_peripheral; (void)deadtime; #endif } /*---------------------------------------------------------------------------*/ /** @brief Force generate a timer event. The event specification consists of 8 possible events that can be forced on the timer. The forced events are automatically cleared by hardware. The UG event is useful to cause shadow registers to be preloaded before the timer is started to avoid uncertainties in the first cycle in case an update event may never be generated. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] event Unsigned int32. Event specification @ref tim_event_gen */ void timer_generate_event(uint32_t timer_peripheral, uint32_t event) { TIM_EGR(timer_peripheral) |= event; } /*---------------------------------------------------------------------------*/ /** @brief Read Counter Read back the value of a timer's counter register contents @param[in] timer_peripheral Unsigned int32. Timer register address base @returns Unsigned int32. Counter value. */ uint32_t timer_get_counter(uint32_t timer_peripheral) { return TIM_CNT(timer_peripheral); } /*---------------------------------------------------------------------------*/ /** @brief Set Counter Set the value of a timer's counter register contents. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] count Unsigned int32. Counter value. */ void timer_set_counter(uint32_t timer_peripheral, uint32_t count) { TIM_CNT(timer_peripheral) = count; } /*---------------------------------------------------------------------------*/ /** @brief Set Input Capture Filter Parameters Set the input filter parameters for an input channel, specifying: @li the frequency of sampling from the Deadtime and Sampling clock (@see @ref timer_set_clock_division) @li the number of events that must occur before a transition is considered valid. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. @param[in] flt ::tim_ic_filter. Input Capture Filter identifier. */ void timer_ic_set_filter(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_filter flt) { switch (ic) { case TIM_IC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1F_MASK; TIM_CCMR1(timer_peripheral) |= flt << 4; break; case TIM_IC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2F_MASK; TIM_CCMR1(timer_peripheral) |= flt << 12; break; case TIM_IC3: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3F_MASK; TIM_CCMR2(timer_peripheral) |= flt << 4; break; case TIM_IC4: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4F_MASK; TIM_CCMR2(timer_peripheral) |= flt << 12; break; } } /*---------------------------------------------------------------------------*/ /** @brief Set Input Capture Prescaler Set the number of events between each capture. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. @param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler. */ void timer_ic_set_prescaler(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_psc psc) { switch (ic) { case TIM_IC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1PSC_MASK; TIM_CCMR1(timer_peripheral) |= psc << 2; break; case TIM_IC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2PSC_MASK; TIM_CCMR1(timer_peripheral) |= psc << 10; break; case TIM_IC3: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3PSC_MASK; TIM_CCMR2(timer_peripheral) |= psc << 4; break; case TIM_IC4: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4PSC_MASK; TIM_CCMR2(timer_peripheral) |= psc << 10; break; } } /*---------------------------------------------------------------------------*/ /** @brief Set Capture/Compare Channel Direction/Input The Capture/Compare channel is defined as output (compare) or input with the input mapping specified: @li channel is configured as output @li channel is configured as input and mapped on corresponding input @li channel is configured as input and mapped on alternate input (TI2 for channel 1, TI1 for channel 2, TI4 for channel 3, TI3 for channel 4) @li channel is configured as input and is mapped on TRC (requires an internal trigger input selected through TS bit @note not all combinations of the input and channel are valid, see datasheets. @note these parameters are writable only when the channel is off. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. @param[in] in ::tim_ic_input. Input Capture channel direction and source input. */ void timer_ic_set_input(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_input in) { in &= 3; if (((ic == TIM_IC2) || (ic == TIM_IC4)) && ((in == TIM_IC_IN_TI1) || (in == TIM_IC_IN_TI2))) { /* Input select bits are flipped for these combinations */ in ^= 3; } switch (ic) { case TIM_IC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK; TIM_CCMR1(timer_peripheral) |= in; break; case TIM_IC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK; TIM_CCMR1(timer_peripheral) |= in << 8; break; case TIM_IC3: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK; TIM_CCMR2(timer_peripheral) |= in; break; case TIM_IC4: TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK; TIM_CCMR2(timer_peripheral) |= in << 8; break; } } /*---------------------------------------------------------------------------*/ /** @brief Enable Timer Input Capture @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. */ void timer_ic_enable(uint32_t timer_peripheral, enum tim_ic_id ic) { TIM_CCER(timer_peripheral) |= (0x1 << (ic * 4)); } /*---------------------------------------------------------------------------*/ /** @brief Disable Timer Input Capture @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. */ void timer_ic_disable(uint32_t timer_peripheral, enum tim_ic_id ic) { TIM_CCER(timer_peripheral) &= ~(0x1 << (ic * 4)); } /*---------------------------------------------------------------------------*/ /** @brief Set External Trigger Filter Parameters for Slave Set the input filter parameters for the external trigger, specifying: @li the frequency of sampling from the Deadtime and Sampling clock (@see @ref timer_set_clock_division) @li the number of events that must occur before a transition is considered valid. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] flt ::tim_ic_filter. Input Capture Filter identifier. */ void timer_slave_set_filter(uint32_t timer_peripheral, enum tim_ic_filter flt) { TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETF_MASK; TIM_SMCR(timer_peripheral) |= flt << 8; } /*---------------------------------------------------------------------------*/ /** @brief Set External Trigger Prescaler for Slave Set the external trigger frequency division ratio. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler. */ void timer_slave_set_prescaler(uint32_t timer_peripheral, enum tim_ic_psc psc) { TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETPS_MASK; TIM_SMCR(timer_peripheral) |= psc << 12; } /*---------------------------------------------------------------------------*/ /** @brief Set External Trigger Polarity for Slave @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] pol ::tim_et_pol. Slave External Trigger polarity. */ void timer_slave_set_polarity(uint32_t timer_peripheral, enum tim_et_pol pol) { if (pol) { TIM_SMCR(timer_peripheral) |= TIM_SMCR_ETP; } else { TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETP; } } /*---------------------------------------------------------------------------*/ /** @brief Set Slave Mode @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] mode Unsigned int8. Slave mode @ref tim_sms */ void timer_slave_set_mode(uint32_t timer_peripheral, uint8_t mode) { TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_SMS_MASK; TIM_SMCR(timer_peripheral) |= mode; } /*---------------------------------------------------------------------------*/ /** @brief Set Slave Trigger Source @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] trigger Unsigned int8. Slave trigger source @ref tim_ts */ void timer_slave_set_trigger(uint32_t timer_peripheral, uint8_t trigger) { TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_TS_MASK; TIM_SMCR(timer_peripheral) |= trigger; } /* TODO Timer DMA burst */ /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/timer_common_f234.c000066400000000000000000000034141435536612600240730ustar00rootroot00000000000000/** @addtogroup timer_file */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief Set Input Polarity The timer channel must be set to input capture mode. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. @param[in] pol ::tim_ic_pol. Input Capture polarity control. */ void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol) { /* Clear CCxP and CCxNP to zero. For both edge trigger both fields are * set. Case 10 is invalid. */ TIM_CCER(timer_peripheral) &= ~(0x6 << (ic * 4)); switch (pol) { case TIM_IC_RISING: /* 00 */ break; case TIM_IC_BOTH: /* 11 */ TIM_CCER(timer_peripheral) |= (0x6 << (ic * 4)); break; case TIM_IC_FALLING: /* 01 */ TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4)); } } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/timer_common_f24.c000066400000000000000000000032601435536612600240070ustar00rootroot00000000000000/** @addtogroup timer_file */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief Set Timer Option Set timer options register on TIM2 or TIM5, used for trigger remapping on TIM2, and similarly for TIM5 for oscillator calibration purposes. @param[in] timer_peripheral Unsigned int32. Timer register address base @returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5: @ref tim5_opt_trigger_remap. */ void timer_set_option(uint32_t timer_peripheral, uint32_t option) { if (timer_peripheral == TIM2) { TIM_OR(timer_peripheral) &= ~TIM2_OR_ITR1_RMP_MASK; TIM_OR(timer_peripheral) |= option; } else if (timer_peripheral == TIM5) { TIM_OR(timer_peripheral) &= ~TIM5_OR_TI4_RMP_MASK; TIM_OR(timer_peripheral) |= option; } } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/usart_common_all.c000066400000000000000000000233241435536612600242050ustar00rootroot00000000000000/** @addtogroup usart_file @author @htmlonly © @endhtmlonly 2009 Uwe Hermann This library supports the USART/UART in the STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. Devices can have up to 3 USARTs and 2 UARTs. */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include /*---------------------------------------------------------------------------*/ /** @brief USART Set Baudrate. The baud rate is computed from the APB high-speed prescaler clock (for USART1/6) or the APB low-speed prescaler clock (for other USARTs). These values must be correctly set before calling this function (refer to the rcc_clock_setup-* functions in RCC). @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] baud unsigned 32 bit. Baud rate specified in Hz. */ void usart_set_baudrate(uint32_t usart, uint32_t baud) { uint32_t clock = rcc_ppre1_frequency; #if defined STM32F2 || defined STM32F4 if ((usart == USART1) || (usart == USART6)) { clock = rcc_ppre2_frequency; } #else if (usart == USART1) { clock = rcc_ppre2_frequency; } #endif /* * Yes it is as simple as that. The reference manual is * talking about fractional calculation but it seems to be only * marketting babble to sound awesome. It is nothing else but a * simple divider to generate the correct baudrate. * * Note: We round() the value rather than floor()ing it, for more * accurate divisor selection. */ USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); } /*---------------------------------------------------------------------------*/ /** @brief USART Set Word Length. The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit if parity is enabled, in which case the data length will be 7 or 8 bits respectively. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] bits unsigned 32 bit. Word length in bits 8 or 9. */ void usart_set_databits(uint32_t usart, uint32_t bits) { if (bits == 8) { USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ } else { USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ } } /*---------------------------------------------------------------------------*/ /** @brief USART Set Stop Bit(s). The stop bits are specified as 0.5, 1, 1.5 or 2. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. */ void usart_set_stopbits(uint32_t usart, uint32_t stopbits) { uint32_t reg32; reg32 = USART_CR2(usart); reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits; USART_CR2(usart) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief USART Set Parity. The parity bit can be selected as none, even or odd. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. */ void usart_set_parity(uint32_t usart, uint32_t parity) { uint32_t reg32; reg32 = USART_CR1(usart); reg32 = (reg32 & ~USART_PARITY_MASK) | parity; USART_CR1(usart) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief USART Set Rx/Tx Mode. The mode can be selected as Rx only, Tx only or Rx+Tx. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. */ void usart_set_mode(uint32_t usart, uint32_t mode) { uint32_t reg32; reg32 = USART_CR1(usart); reg32 = (reg32 & ~USART_MODE_MASK) | mode; USART_CR1(usart) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief USART Set Hardware Flow Control. The flow control bit can be selected as none, RTS, CTS or RTS+CTS. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol. */ void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol) { uint32_t reg32; reg32 = USART_CR3(usart); reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; USART_CR3(usart) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief USART Enable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_enable(uint32_t usart) { USART_CR1(usart) |= USART_CR1_UE; } /*---------------------------------------------------------------------------*/ /** @brief USART Disable. At the end of the current frame, the USART is disabled to reduce power. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_disable(uint32_t usart) { USART_CR1(usart) &= ~USART_CR1_UE; } /*---------------------------------------------------------------------------*/ /** @brief USART Send Data Word with Blocking Blocks until the transmit data buffer becomes empty then writes the next data word for transmission. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] data unsigned 16 bit. */ void usart_send_blocking(uint32_t usart, uint16_t data) { usart_wait_send_ready(usart); usart_send(usart, data); } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word with Blocking. Wait until a data word has been received then return the word. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @returns unsigned 16 bit data word. */ uint16_t usart_recv_blocking(uint32_t usart) { usart_wait_recv_ready(usart); return usart_recv(usart); } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver DMA Enable. DMA is available on: @li USART1 Rx DMA1 channel 5. @li USART2 Rx DMA1 channel 6. @li USART3 Rx DMA1 channel 3. @li UART4 Rx DMA2 channel 3. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_enable_rx_dma(uint32_t usart) { USART_CR3(usart) |= USART_CR3_DMAR; } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver DMA Disable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_disable_rx_dma(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_DMAR; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter DMA Enable. DMA is available on: @li USART1 Tx DMA1 channel 4. @li USART2 Tx DMA1 channel 7. @li USART3 Tx DMA1 channel 2. @li UART4 Tx DMA2 channel 5. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_enable_tx_dma(uint32_t usart) { USART_CR3(usart) |= USART_CR3_DMAT; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter DMA Disable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_disable_tx_dma(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_DMAT; } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver Interrupt Enable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_enable_rx_interrupt(uint32_t usart) { USART_CR1(usart) |= USART_CR1_RXNEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver Interrupt Disable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_disable_rx_interrupt(uint32_t usart) { USART_CR1(usart) &= ~USART_CR1_RXNEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter Interrupt Enable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_enable_tx_interrupt(uint32_t usart) { USART_CR1(usart) |= USART_CR1_TXEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter Interrupt Disable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_disable_tx_interrupt(uint32_t usart) { USART_CR1(usart) &= ~USART_CR1_TXEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Error Interrupt Enable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_enable_error_interrupt(uint32_t usart) { USART_CR3(usart) |= USART_CR3_EIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Error Interrupt Disable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_disable_error_interrupt(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_EIE; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/common/usart_common_f124.c000066400000000000000000000104541435536612600241110ustar00rootroot00000000000000/** @addtogroup usart_file @author @htmlonly © @endhtmlonly 2009 Uwe Hermann This library supports the USART/UART in the STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. Devices can have up to 3 USARTs and 2 UARTs. */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include /*---------------------------------------------------------------------------*/ /** @brief USART Send a Data Word. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] data unsigned 16 bit. */ void usart_send(uint32_t usart, uint16_t data) { /* Send data. */ USART_DR(usart) = (data & USART_DR_MASK); } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word. If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @returns unsigned 16 bit data word. */ uint16_t usart_recv(uint32_t usart) { /* Receive data. */ return USART_DR(usart) & USART_DR_MASK; } /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Transmit Data Buffer Empty Blocks until the transmit data buffer becomes empty and is ready to accept the next data word. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_wait_send_ready(uint32_t usart) { /* Wait until the data has been transferred into the shift register. */ while ((USART_SR(usart) & USART_SR_TXE) == 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Received Data Available Blocks until the receive data buffer holds a valid received data word. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_wait_recv_ready(uint32_t usart) { /* Wait until the data is ready to be received. */ while ((USART_SR(usart) & USART_SR_RXNE) == 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Status Flag. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. @returns boolean: flag set. */ bool usart_get_flag(uint32_t usart, uint32_t flag) { return ((USART_SR(usart) & flag) != 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Return Interrupt Source. Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was set and the interrupt was enabled. If the specified flag is not an interrupt flag, the function returns false. @todo These are the most important interrupts likely to be used. Others relating to LIN break, and error conditions in multibuffer communication, need to be added for completeness. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. @returns boolean: flag and interrupt enable both set. */ bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) { uint32_t flag_set = (USART_SR(usart) & flag); /* IDLE, RXNE, TC, TXE interrupts */ if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) { return ((flag_set & USART_CR1(usart)) != 0); /* Overrun error */ } else if (flag == USART_SR_ORE) { return flag_set && (USART_CR3(usart) & USART_CR3_CTSIE); } return false; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/desig.c000066400000000000000000000033641435536612600204540ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include uint16_t desig_get_flash_size(void) { return DESIG_FLASH_SIZE; } void desig_get_unique_id(uint32_t result[]) { /* Could also just return a pointer to the start? read it as they wish? */ uint16_t bits15_0 = DESIG_UID_15_0; uint32_t bits31_16 = DESIG_UID_31_16; uint32_t bits63_32 = DESIG_UID_63_32; uint32_t bits95_64 = DESIG_UID_95_64; result[0] = bits95_64; result[1] = bits63_32; result[2] = bits31_16 << 16 | bits15_0; } void desig_get_unique_id_as_string(char *string, unsigned int string_len) { int i, len; uint8_t device_id[12]; static const char chars[] = "0123456789ABCDEF"; desig_get_unique_id((uint32_t *)device_id); /* Each byte produces two characters */ len = (2 * sizeof(device_id) < string_len) ? 2 * sizeof(device_id) : string_len - 1; for (i = 0; i < len; i += 2) { string[i] = chars[(device_id[i / 2] >> 0) & 0x0F]; string[i + 1] = chars[(device_id[i / 2] >> 4) & 0x0F]; } string[len] = '\0'; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/000077500000000000000000000000001435536612600175145ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/Makefile000066400000000000000000000032031435536612600211520ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2013 Frantisek Burian ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_stm32f0 PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m0 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F0 ARFLAGS = rcs OBJS = flash.o rcc.o usart.o dma.o rtc.o comparator.o spi.o crc.o \ dac.o i2c.o iwdg.o pwr.o gpio.o timer.o adc.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o \ pwr_common_all.o iwdg_common_all.o rtc_common_l1f024.o \ dma_common_l1f013.o exti_common_all.o spi_common_all.o VPATH += ../../usb:../:../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/adc.c000066400000000000000000000600601435536612600204110ustar00rootroot00000000000000/** @defgroup adc_file ADC * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx Analog to Digital Converters * * based on F3 file * * @date 14 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /**@{*/ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /** * @defgroup adc_api_opmode ADC Operation mode API * @ingroup adc_file * * @brief ADC Result API * *@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode * * In this mode the ADC starts a new conversion of a single channel or a channel * group immediately following completion of the previous channel group * conversion. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_set_continuous_conversion_mode(uint32_t adc) { ADC_CFGR1(adc) |= ADC_CFGR1_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode * * In this mode the ADC performs a conversion of one channel or a channel group * and stops. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_set_single_conversion_mode(uint32_t adc) { ADC_CFGR1(adc) &= ~ADC_CFGR1_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_enable_discontinuous_mode(uint32_t adc) { ADC_CFGR1(adc) |= ADC_CFGR1_DISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_discontinuous_mode(uint32_t adc) { ADC_CFGR1(adc) &= ~ADC_CFGR1_DISCEN; } /*---------------------------------------------------------------------------*/ /** ADC Set operation mode * * There are some operation modes, common for entire stm32 branch. In the text * the braces are describing result to single trigger event. The trigger event * is described by character T in the description. The ADC is configured to * convert list of inputs [0, 1, 2, 3]. In Grouped modes, there is used group * size of 2 conversions in the examples * * @li @c ADC_MODE_SEQUENTIAL: T(0) T(1) T(2) T(3)[EOSEQ] T(0) T(1) T(2) ... * * In this mode, after the trigger event a single channel is converted and the * next channel in the list is prepared to convert on next trigger edge. * * @note This mode can be emulated by ADC_MODE_GROUPED with group size * of 1. @par * * @li @c ADC_MODE_SCAN: T(0123)[EOSEQ] T(0123)[EOSEQ] T(0123)[EOSEQ] * * In this mode, after the trigger event, all channels will be converted once, * storing results sequentially. * * @note The DMA must be configured properly for more than single channel to * convert. @par * * @li @c ADC_MODE_SCAN_INFINITE: T(0123[EOSEQ]0123[EOSEQ]0123[EOSEQ]...) * * In this mode, after the trigger event, all channels from the list are * converted. At the end of list, the conversion continues from the beginning. * * @note The DMA must be configured properly to operate in this mode.@par * * @li @c ADC_MODE_GROUPED: T(12) T(34)[EOSEQ] T(12) T(34)[EOSEQ] T(12) * * In this mode, after the trigger event, a specified group size of channels * are converted. If the end of channel list occurs, the EOSEQ is generated * and on the next trigger it wraps to the beginning. * * @note The DMA must be configured properly to operate on more than single * channel conversion groups.@par * * @warning not all families supports all modes of operation of ADC. * * @par * */ /*---------------------------------------------------------------------------*/ /** @brief ADC Set conversion operation mode * * @note on SEQUENTIAL mode, the trigger event is neccesary to start conversion. * @par * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] adc ::adc_opmode. ADC operation mode (@ref adc_opmode) */ void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode) { switch (opmode) { case ADC_MODE_SEQUENTIAL: ADC_CFGR1(adc) &= ~ADC_CFGR1_CONT; ADC_CFGR1(adc) |= ADC_CFGR1_DISCEN; break; case ADC_MODE_SCAN: ADC_CFGR1(adc) &= ~(ADC_CFGR1_CONT | ADC_CFGR1_DISCEN); break; case ADC_MODE_SCAN_INFINITE: ADC_CFGR1(adc) &= ~ADC_CFGR1_DISCEN; ADC_CFGR1(adc) |= ADC_CFGR1_CONT; break; } } /**@}*/ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /** * @defgroup adc_api_result ADC Result API * @ingroup adc_file * * @brief ADC Result API * *@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels * * This starts conversion on a set of defined regular channels. It is cleared * by hardware once conversion starts. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_start_conversion_regular(uint32_t adc) { /* Start conversion on regular channels. */ ADC_CR(adc) |= ADC_CR_ADSTART; /* Wait until the ADC starts the conversion. */ while (ADC_CR(adc) & ADC_CR_ADSTART); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag * * This flag is set after all channels of a regular or injected group have been * converted. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @returns bool. End of conversion flag. */ bool adc_eoc(uint32_t adc) { return ((ADC_ISR(adc) & ADC_ISR_EOC) != 0); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register * * The result read back is 12 bits, right or left aligned within the first * 16 bits. For ADC1 only, the higher 16 bits will hold the result from ADC2 if * an appropriate dual mode has been set @see adc_set_dual_mode. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @returns Unsigned int32 conversion result. */ uint32_t adc_read_regular(uint32_t adc) { return ADC_DR(adc); } /**@}*/ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /** * @defgroup adc_api_trigger ADC Trigger API * @ingroup adc_file * * @brief ADC Trigger API * *@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels * * This enables an external trigger for set of defined regular channels, and * sets the polarity of the trigger event: rising or falling edge or both. Note * that if the trigger polarity is zero, triggering is disabled. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] trigger Unsigned int32. Trigger identifier * @ref adc_trigger_regular * @param[in] polarity Unsigned int32. Trigger polarity @ref * adc_trigger_polarity_regular */ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity) { ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_EXTSEL) | trigger; ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_EXTEN) | polarity; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_external_trigger_regular(uint32_t adc) { ADC_CFGR1(adc) &= ~ADC_CFGR1_EXTEN; } /**@}*/ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /** * @defgroup adc_api_interrupts ADC Interrupt configuration API * @ingroup adc_file * * @brief ADC Interrupt configuration API * *@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_enable_watchdog_interrupt(uint32_t adc) { ADC_IER(adc) |= ADC_IER_AWDIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_watchdog_interrupt(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_AWDIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Analog Watchdog Flag * * This flag is set when the converted voltage crosses the high or low * thresholds. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @returns bool true, if the signal is out of defined analog range. */ bool adc_get_watchdog_flag(uint32_t adc) { return ADC_ISR(adc) & ADC_ISR_AWD; } /*---------------------------------------------------------------------------*/ /** @brief ADC Clear Analog Watchdog Flag * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_clear_watchdog_flag(uint32_t adc) { ADC_ISR(adc) = ADC_ISR_AWD; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable the Overrun Interrupt * * The overrun interrupt is generated when data is not read from a result * register before the next conversion is written. If DMA is enabled, all * transfers are terminated and any conversion sequence is aborted. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_enable_overrun_interrupt(uint32_t adc) { ADC_IER(adc) |= ADC_IER_OVRIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable the Overrun Interrupt * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_overrun_interrupt(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_OVRIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Overrun Flag * * The overrun flag is set when data is not read from a result register before * the next conversion is written. If DMA is enabled, all transfers are * terminated and any conversion sequence is aborted. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ bool adc_get_overrun_flag(uint32_t adc) { return ADC_ISR(adc) & ADC_ISR_OVR; } /*---------------------------------------------------------------------------*/ /** @brief ADC Clear Overrun Flags * * The overrun flag is cleared. Note that if an overrun occurs, DMA is * terminated. * The flag must be cleared and the DMA stream and ADC reinitialised to resume * conversions (see the reference manual). * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_clear_overrun_flag(uint32_t adc) { ADC_ISR(adc) = ADC_ISR_OVR; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Sequence Interrupt * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_enable_eoc_sequence_interrupt(uint32_t adc) { ADC_IER(adc) |= ADC_IER_EOSEQIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Sequence Interrupt * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_eoc_sequence_interrupt(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_EOSEQIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Regular End-Of-Conversion Sequence Flag * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ bool adc_get_eoc_sequence_flag(uint32_t adc) { return ADC_ISR(adc) & ADC_ISR_EOSEQ; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_enable_eoc_interrupt(uint32_t adc) { ADC_IER(adc) |= ADC_IER_EOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_eoc_interrupt(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_EOCIE; } /**@}*/ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /** * @defgroup adc_api_config ADC Basic configuration API * @ingroup adc_file * * @brief ADC Basic configuration API * *@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Power Off * * Turn off the ADC to reduce power consumption to a few microamps. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_power_off(uint32_t adc) { ADC_CR(adc) &= ~ADC_CR_ADEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Power On * * If the ADC is in power-down mode then it is powered up. The application * needs to wait a time of about 3 microseconds for stabilization before using * the ADC. If the ADC is already on this function call will have no effect. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_power_on(uint32_t adc) { ADC_CR(adc) |= ADC_CR_ADEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale * * The ADC clock taken from the many sources. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] prescale Unsigned int32. Prescale value (@ref adc_api_clksource) */ void adc_set_clk_source(uint32_t adc, uint32_t source) { ADC_CFGR2(adc) = ((ADC_CFGR2(adc) & ~ADC_CFGR2_CKMODE) | source); } /*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence * * Define a sequence of channels to be converted as a regular group with a * length from 1 to 18 channels. If this is called during conversion, the * current conversion is reset and conversion begins again with the newly * defined group. * * @warning This core doesn't support the random order of ADC conversions. * The channel list must be ordered by channel number. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] length Unsigned int8. Number of channels in the group. * @param[in] channel Unsigned int8[]. Set of channels to convert, integers * 0..18. */ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { uint32_t reg32 = 0; uint8_t i = 0; bool stepup = false, stepdn = false; if (length == 0) { ADC_CHSELR(adc) = 0; return; } reg32 |= (1 << channel[0]); for (i = 1; i < length; i++) { reg32 |= (1 << channel[i]); stepup |= channel[i-1] < channel[i]; stepdn |= channel[i-1] > channel[i]; } /* Check, if the channel list is in order */ if (stepup && stepdn) { cm3_assert_not_reached(); } /* Update the scan direction flag */ if (stepdn) { ADC_CFGR1(adc) |= ADC_CFGR1_SCANDIR; } else { ADC_CFGR1(adc) &= ~ADC_CFGR1_SCANDIR; } ADC_CHSELR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels * * The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, * same for all channels. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] time Unsigned int8. Sampling time selection (@ref adc_api_smptime) */ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) { ADC_SMPR(adc) = time & ADC_SMPR_SMP; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Resolution * * ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a * corresponding reduction in conversion time. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] resolution Unsigned int16. Resolution value (@ref adc_api_res) */ void adc_set_resolution(uint32_t adc, uint16_t resolution) { ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_RES) | resolution; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_set_left_aligned(uint32_t adc) { ADC_CFGR1(adc) |= ADC_CFGR1_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_set_right_aligned(uint32_t adc) { ADC_CFGR1(adc) &= ~ADC_CFGR1_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_enable_dma(uint32_t adc) { ADC_CFGR1(adc) |= ADC_CFGR1_DMAEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_dma(uint32_t adc) { ADC_CFGR1(adc) &= ~ADC_CFGR1_DMAEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor * * This enables the sensor on channel 16 */ void adc_enable_temperature_sensor(void) { ADC_CCR |= ADC_CCR_TSEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor * * Disabling this will reduce power consumption from the temperature sensor * measurement. */ void adc_disable_temperature_sensor(void) { ADC_CCR &= ~ADC_CCR_TSEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The VRef Sensor * * This enables the reference voltage measurements on channel 17. */ void adc_enable_vref_sensor(void) { ADC_CCR |= ADC_CCR_VREFEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable The VRef Sensor * * Disabling this will reduce power consumption from the reference voltage * measurement. */ void adc_disable_vref_sensor(void) { ADC_CCR &= ~ADC_CCR_VREFEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The VBat Sensor * * This enables the battery voltage measurements on channel 17. */ void adc_enable_vbat_sensor(void) { ADC_CCR |= ADC_CCR_VBATEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable The VBat Sensor * * Disabling this will reduce power consumption from the battery voltage * measurement. */ void adc_disable_vbat_sensor(void) { ADC_CCR &= ~ADC_CCR_VBATEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Start the calibration procedure * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_calibrate_start(uint32_t adc) { ADC_CR(adc) = ADC_CR_ADCAL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Wait to finish the ADC calibration procedure * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_calibrate_wait_finish(uint32_t adc) { while (ADC_CR(adc) & ADC_CR_ADCAL); } /**@}*/ /*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/ /** * @defgroup adc_api_wdg ADC Analog watchdog API * @ingroup adc_file * * @brief ADC analog watchdog API definitions. * * The analog watchdog allows the monitoring of an analog signal between two * threshold levels. The thresholds must be preset. Analog watchdog is disabled * by default. * * @warning Comparison is done before data alignment takes place, so the * thresholds are left-aligned. * * Example 1: Enable watchdog checking on all channels * * @code * // in configuration * adc_enable_analog_watchdog_on_all_channels(ADC1); * adc_set_watchdog_high_threshold(ADC1, 0xE00); * adc_set_watchdog_low_threshold(ADC1, 0x200); * * // in the main application thread * if (adc_get_watchdog_flag(ADC1)) { * // the converted signal is out of AWD ranges * adc_clear_watchdog_flag(ADC1); * } * @endcode * * Example 2: Enable watchdog checking on channel 5 * * @code * // in configuration * adc_enable_analog_watchdog_on_selected_channel(ADC1,5); * adc_set_watchdog_high_threshold(ADC1, 0xE00); * adc_set_watchdog_low_threshold(ADC1, 0x200); * * // in the main application thread * if (adc_get_watchdog_flag(ADC1)) { * // the converted signal is out of AWD ranges * adc_clear_watchdog_flag(ADC1); * } * @endcode *@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Channels * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) { ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN; ADC_CFGR1(adc) &= ~ADC_CFGR1_AWDSGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] chan Unsigned int8. ADC channel number @ref adc_api_channel */ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan) { ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | \ ADC_CFGR1_AWDCH_VAL(chan); ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) */ void adc_disable_analog_watchdog(uint32_t adc) { ADC_CFGR1(adc) &= ~ADC_CFGR1_AWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] threshold Unsigned int8. Upper threshold value */ void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold) { ADC_TR(adc) = (ADC_TR(adc) & ~ADC_TR_HT) | ADC_TR_HT_VAL(threshold); } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) * @param[in] threshold Unsigned int8. Lower threshold value */ void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold) { ADC_TR(adc) = (ADC_TR(adc) & ~ADC_TR_LT) | ADC_TR_LT_VAL(threshold); } /**@}*/ /*---------------------------------------------------------------------------*/ /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/comparator.c000066400000000000000000000030131435536612600220240ustar00rootroot00000000000000/** @defgroup comp_file COMP * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx COMP * * @version 1.0.0 * * @date 10 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void comp_enable(uint8_t id) { COMP_CSR(id) |= COMP_CSR_EN; } void comp_disable(uint8_t id) { COMP_CSR(id) &= ~COMP_CSR_EN; } void comp_select_input(uint8_t id, uint32_t input) { COMP_CSR(id) = (COMP_CSR(id) & ~COMP_CSR_INSEL) | input; } void comp_select_output(uint8_t id, uint32_t output) { COMP_CSR(id) = (COMP_CSR(id) & ~COMP_CSR_OUTSEL) | output; } void comp_select_hyst(uint8_t id, uint32_t hyst) { COMP_CSR(id) = (COMP_CSR(id) & ~COMP_CSR_HYST) | hyst; } void comp_select_speed(uint8_t id, uint32_t speed) { COMP_CSR(id) = (COMP_CSR(id) & ~COMP_CSR_SPEED) | speed; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/crc.c000066400000000000000000000017541435536612600204360ustar00rootroot00000000000000/** @defgroup crc_file CRC * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx CRC * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/dac.c000066400000000000000000000017541435536612600204160ustar00rootroot00000000000000/** @defgroup dac_file DAC * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx DAC * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/dma.c000066400000000000000000000017571435536612600204330ustar00rootroot00000000000000/** @defgroup dma_file DMA * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx DMA * * @version 1.0.0 * * @date 10 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/flash.c000066400000000000000000000037401435536612600207610ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void flash_prefetch_buffer_enable(void) { FLASH_ACR |= FLASH_ACR_PRFTBE; } void flash_prefetch_buffer_disable(void) { FLASH_ACR &= ~FLASH_ACR_PRFTBE; } void flash_set_ws(uint32_t ws) { FLASH_ACR = (FLASH_ACR & ~FLASH_ACR_LATENCY) | ws; } void flash_wait_busy(void) { while ((FLASH_SR & FLASH_SR_BSY) != 0); } void flash_program_u32(uint32_t address, uint32_t data) { flash_wait_busy(); FLASH_CR |= FLASH_CR_PG; MMIO16(address) = (uint16_t)data; flash_wait_busy(); MMIO16(address + 2) = data >> 16; flash_wait_busy(); FLASH_CR &= ~FLASH_CR_PG; } void flash_program_u16(uint32_t address, uint16_t data) { flash_wait_busy(); FLASH_CR |= FLASH_CR_PG; MMIO16(address) = data; flash_wait_busy(); FLASH_CR &= ~FLASH_CR_PG; } void flash_erase_page(uint32_t page_address) { flash_wait_busy(); FLASH_CR |= FLASH_CR_PER; FLASH_AR = page_address; FLASH_CR |= FLASH_CR_STRT; flash_wait_busy(); FLASH_CR &= ~FLASH_CR_PER; } void flash_erase_all_pages(void) { flash_wait_busy(); FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */ flash_wait_busy(); FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */ } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/gpio.c000066400000000000000000000017141435536612600206210ustar00rootroot00000000000000/** @defgroup gpio_file GPIO * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx General Purpose I/O * * @version 1.0.0 * * @date 18 August 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/i2c.c000066400000000000000000000016701435536612600203410ustar00rootroot00000000000000/** @defgroup i2c_file I2C * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx I2C * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/iwdg.c000066400000000000000000000020071435536612600206110ustar00rootroot00000000000000/** @defgroup iwdg_file IWDG * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx Independent Watchdog Timer * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/libopencm3_stm32f0.ld000066400000000000000000000047631435536612600233600ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/pwr.c000066400000000000000000000021311435536612600204650ustar00rootroot00000000000000/** @defgroup pwr-file PWR * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx Power Control * * @version 1.0.0 * * @date 11 July 2013 * * This library supports the power control system for the * STM32F0 series of ARM Cortex Microcontrollers by ST Microelectronics. * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/rcc.c000066400000000000000000000334341435536612600204360ustar00rootroot00000000000000/** @defgroup STM32F0xx-rcc-file RCC * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx Reset and Clock Control * * @version 1.0.0 * * @date 29 Jun 2013 * * This library supports the Reset and Clock Control System in the STM32F0xx * series of ARM Cortex Microcontrollers by ST Microelectronics. * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include #include uint32_t rcc_core_frequency = 8000000; /* 8MHz after reset */ uint32_t rcc_ppre_frequency = 8000000; /* 8MHz after reset */ /*---------------------------------------------------------------------------*/ /** @brief RCC Clear the Oscillator Ready Interrupt Flag * * Clear the interrupt flag that was set when a clock oscillator became ready * to use. * * @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) { switch (osc) { case HSI14: RCC_CIR |= RCC_CIR_HSI14RDYC; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; case PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt * * @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) { switch (osc) { case HSI14: RCC_CIR |= RCC_CIR_HSI14RDYIE; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; case PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt * * @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) { switch (osc) { case HSI14: RCC_CIR &= ~RCC_CIR_HSI14RDYC; break; case HSI: RCC_CIR &= ~RCC_CIR_HSIRDYC; break; case HSE: RCC_CIR &= ~RCC_CIR_HSERDYC; break; case PLL: RCC_CIR &= ~RCC_CIR_PLLRDYC; break; case LSE: RCC_CIR &= ~RCC_CIR_LSERDYC; break; case LSI: RCC_CIR &= ~RCC_CIR_LSIRDYC; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag * * @param[in] osc enum ::osc_t. Oscillator ID * @returns int. Boolean value for flag set. */ int rcc_osc_ready_int_flag(enum rcc_osc osc) { switch (osc) { case HSI14: return (RCC_CIR & RCC_CIR_HSI14RDYF) != 0; break; case HSI: return (RCC_CIR & RCC_CIR_HSIRDYF) != 0; break; case HSE: return (RCC_CIR & RCC_CIR_HSERDYF) != 0; break; case PLL: return (RCC_CIR & RCC_CIR_PLLRDYF) != 0; break; case LSE: return (RCC_CIR & RCC_CIR_LSERDYF) != 0; break; case LSI: return (RCC_CIR & RCC_CIR_LSIRDYF) != 0; break; } cm3_assert_not_reached(); } /*---------------------------------------------------------------------------*/ /** @brief RCC Clear the Clock Security System Interrupt Flag */ void rcc_css_int_clear(void) { RCC_CIR |= RCC_CIR_CSSC; } /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Clock Security System Interrupt Flag * * @returns int. Boolean value for flag set. */ int rcc_css_int_flag(void) { return ((RCC_CIR & RCC_CIR_CSSF) != 0); } /*---------------------------------------------------------------------------*/ /** @brief RCC Wait for Oscillator Ready. * * @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_wait_for_osc_ready(enum rcc_osc osc) { switch (osc) { case HSI14: while ((RCC_CIR & RCC_CIR_HSI14RDYF) != 0); break; case HSI: while ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; case HSE: while ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; case PLL: while ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; case LSE: while ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; case LSI: while ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Turn on an Oscillator. * * Enable an oscillator and power on. Each oscillator requires an amount of * time to settle to a usable state. Refer to datasheets for time delay * information. A status flag is available to indicate when the oscillator * becomes ready (see @ref rcc_osc_ready_int_flag and @ref * rcc_wait_for_osc_ready). * * @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_on(enum rcc_osc osc) { switch (osc) { case HSI14: RCC_CR2 |= RCC_CR2_HSI14ON; break; case HSI: RCC_CR |= RCC_CR_HSION; break; case HSE: RCC_CR |= RCC_CR_HSEON; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEON; break; case LSI: RCC_CSR |= RCC_CSR_LSION; break; case PLL: /* don't do anything */ break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Turn off an Oscillator. * * Disable an oscillator and power off. * * @note An oscillator cannot be turned off if it is selected as the system * clock. * * @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_off(enum rcc_osc osc) { switch (osc) { case HSI14: RCC_CR2 &= ~RCC_CR2_HSI14ON; break; case HSI: RCC_CR &= ~RCC_CR_HSION; break; case HSE: RCC_CR &= ~RCC_CR_HSEON; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEON; break; case LSI: RCC_CSR &= ~RCC_CSR_LSION; break; case PLL: /* don't do anything */ break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Clock Security System. */ void rcc_css_enable(void) { RCC_CR |= RCC_CR_CSSON; } /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Clock Security System. */ void rcc_css_disable(void) { RCC_CR &= ~RCC_CR_CSSON; } /*---------------------------------------------------------------------------*/ /** @brief RCC Enable Bypass. * * Enable an external clock to bypass the internal clock (high speed and low * speed clocks only). The external clock must be enabled (see @ref rcc_osc_on) * and the internal clock must be disabled (see @ref rcc_osc_off) for this to * have effect. * * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect. */ void rcc_osc_bypass_enable(enum rcc_osc osc) { switch (osc) { case HSE: RCC_CR |= RCC_CR_HSEBYP; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEBYP; break; case HSI14: case HSI: case LSI: case PLL: /* Do nothing */ break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Disable Bypass. * * Re-enable the internal clock (high speed and low speed clocks only). The * internal clock must be disabled (see @ref rcc_osc_off) for this to have * effect. * * * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect. */ void rcc_osc_bypass_disable(enum rcc_osc osc) { switch (osc) { case HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEBYP; break; case HSI14: case PLL: case HSI: case LSI: /* Do nothing */ break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. * * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, LSE and PLL have * effect. */ void rcc_set_sysclk_source(enum rcc_osc clk) { switch (clk) { case HSI: RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_HSI; break; case HSE: RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_HSE; break; case PLL: RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; break; case LSI: case LSE: case HSI14: /* do nothing */ break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL Multiplication Factor. * * @note This only has effect when the PLL is disabled. * * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll_multiplication_factor(uint32_t mul) { RCC_CFGR = (RCC_CFGR & RCC_CFGR_PLLMUL) | mul; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB Prescale Factor. * * @note The APB1 clock frequency must not exceed 36MHz. * * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre(uint32_t ppre) { RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE) | ppre; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the AHB Prescale Factor. * * @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre */ void rcc_set_hpre(uint32_t hpre) { RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_HPRE) | hpre; } void rcc_set_prediv(uint32_t prediv) { RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv; } void rcc_set_mco(uint32_t mcosrc) { RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_MCO) | mcosrc; } /*---------------------------------------------------------------------------*/ /** @brief RCC Get the System Clock Source. * * @returns ::osc_t System clock source: */ enum rcc_osc rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ switch (RCC_CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: return HSI; case RCC_CFGR_SWS_HSE: return HSE; case RCC_CFGR_SWS_PLL: return PLL; } cm3_assert_not_reached(); } void rcc_clock_setup_in_hsi_out_8mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ); rcc_ppre_frequency = 8000000; rcc_core_frequency = 8000000; } void rcc_clock_setup_in_hsi_out_16mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ); /* 8MHz * 4 / 2 = 16MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4); RCC_CFGR &= RCC_CFGR_PLLSRC; rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); rcc_ppre_frequency = 16000000; rcc_core_frequency = 16000000; } void rcc_clock_setup_in_hsi_out_24mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ); /* 8MHz * 6 / 2 = 24MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6); RCC_CFGR &= RCC_CFGR_PLLSRC; rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); rcc_ppre_frequency = 24000000; rcc_core_frequency = 24000000; } void rcc_clock_setup_in_hsi_out_32mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); /* 8MHz * 8 / 2 = 32MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL8); RCC_CFGR &= RCC_CFGR_PLLSRC; rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); rcc_ppre_frequency = 32000000; rcc_core_frequency = 32000000; } void rcc_clock_setup_in_hsi_out_40mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); /* 8MHz * 10 / 2 = 40MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10); RCC_CFGR &= RCC_CFGR_PLLSRC; rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); rcc_ppre_frequency = 32000000; rcc_core_frequency = 32000000; } void rcc_clock_setup_in_hsi_out_48mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); /* 8MHz * 12 / 2 = 24MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL16); RCC_CFGR &= RCC_CFGR_PLLSRC; rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); rcc_ppre_frequency = 48000000; rcc_core_frequency = 48000000; } #define _RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5)) #define _RCC_BIT(i) (1 << ((i) & 0x1f)) void rcc_periph_clock_enable(enum rcc_periph_clken periph) { _RCC_REG(periph) |= _RCC_BIT(periph); } void rcc_periph_clock_disable(enum rcc_periph_clken periph) { _RCC_REG(periph) &= ~_RCC_BIT(periph); } void rcc_periph_reset_pulse(enum rcc_periph_rst periph) { _RCC_REG(periph) |= _RCC_BIT(periph); _RCC_REG(periph) &= ~_RCC_BIT(periph); } void rcc_periph_reset_hold(enum rcc_periph_rst periph) { _RCC_REG(periph) |= _RCC_BIT(periph); } void rcc_periph_reset_release(enum rcc_periph_rst periph) { _RCC_REG(periph) &= ~_RCC_BIT(periph); } #undef _RCC_REG #undef _RCC_BIT /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/rtc.c000066400000000000000000000017561435536612600204610ustar00rootroot00000000000000/** @defgroup rtc_file RTC * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx RTC * * @version 1.0.0 * * @date 10 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/spi.c000066400000000000000000000027141435536612600204570ustar00rootroot00000000000000/** @defgroup spi_file SPI * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx Serial Peripheral Interface * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include void spi_set_data_size(uint32_t spi, uint16_t data_s) { SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | (data_s & SPI_CR2_DS_MASK); } void spi_fifo_reception_threshold_8bit(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_FRXTH; } void spi_fifo_reception_threshold_16bit(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_FRXTH; } void spi_i2s_mode_spi_mode(uint32_t spi) { SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/syscfg.c000066400000000000000000000017031435536612600211570ustar00rootroot00000000000000/** @defgroup syscfg_file SYSCFG * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx SYSCFG * * @version 1.0.0 * * @date 10 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/timer.c000066400000000000000000000020401435536612600207740ustar00rootroot00000000000000/** @defgroup timer_file Timers * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx Timers * * @version 1.0.0 * * @date 11 July 2013 * */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f0/usart.c000066400000000000000000000276451435536612600210340ustar00rootroot00000000000000/** @defgroup usart_file USART * * @ingroup STM32F0xx * * @brief libopencm3 STM32F0xx USART * * @version 1.0.0 * * @date 7 Jul 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /*---------------------------------------------------------------------------*/ /** @brief USART Set Baudrate. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] baud unsigned 32 bit. Baud rate specified in Hz. */ void usart_set_baudrate(uint32_t usart, uint32_t baud) { uint32_t clock = rcc_ppre_frequency; if (usart == USART1) { clock = rcc_ppre_frequency; /* TODO selective PCLK, SYSCLK, HSI or LSE */ } /* TODO check oversampling 16 */ USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); } /*---------------------------------------------------------------------------*/ /** @brief USART Set Word Length. * * The word length is set to 8 or 9 bits. Note that the last bit will be a * parity bit if parity is enabled, in which case the data length will be 7 * or 8 bits respectively. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] bits unsigned 32 bit. Word length in bits 8 or 9. */ void usart_set_databits(uint32_t usart, uint32_t bits) { if (bits == 8) { USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ } else { USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ } } /*---------------------------------------------------------------------------*/ /** @brief USART Set Stop Bit(s). * * The stop bits are specified as 0.5, 1, 1.5 or 2. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. */ void usart_set_stopbits(uint32_t usart, uint32_t stopbits) { USART_CR2(usart) = (USART_CR2(usart) & ~USART_CR2_STOP) | stopbits; } /*---------------------------------------------------------------------------*/ /** @brief USART Set Parity. * * The parity bit can be selected as none, even or odd. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. */ void usart_set_parity(uint32_t usart, uint32_t parity) { USART_CR1(usart) = (USART_CR1(usart) & ~USART_PARITY) | parity; } /*---------------------------------------------------------------------------*/ /** @brief USART Set Rx/Tx Mode. * * The mode can be selected as Rx only, Tx only or Rx+Tx. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. */ void usart_set_mode(uint32_t usart, uint32_t mode) { USART_CR1(usart) = (USART_CR1(usart) & ~USART_MODE) | mode; } /*---------------------------------------------------------------------------*/ /** @brief USART Set Hardware Flow Control. * * The flow control bit can be selected as none, RTS, CTS or RTS+CTS. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref * usart_cr3_flowcontrol. */ void usart_set_flow_control(uint32_t usart, uint32_t flowctrl) { USART_CR3(usart) = (USART_CR3(usart) & ~USART_FLOWCONTROL) | flowctrl; } /*---------------------------------------------------------------------------*/ /** @brief USART Enable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_enable(uint32_t usart) { USART_CR1(usart) |= USART_CR1_UE; } /*---------------------------------------------------------------------------*/ /** @brief USART Disable. * * At the end of the current frame, the USART is disabled to reduce power. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_disable(uint32_t usart) { USART_CR1(usart) &= ~USART_CR1_UE; } /*---------------------------------------------------------------------------*/ /** @brief USART Send a Data Word. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] data unsigned 16 bit. */ void usart_send(uint32_t usart, uint8_t data) { USART_TDR(usart) = data; } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word. * * If parity is enabled the MSB (bit 7 or 8 depending on the word length) is * the parity bit. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @returns unsigned 16 bit data word. */ uint8_t usart_recv(uint32_t usart) { /* Receive data. */ return USART_RDR(usart); } /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Transmit Data Buffer Empty * * Blocks until the transmit data buffer becomes empty and is ready to accept * the next data word. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_wait_send_ready(uint32_t usart) { /* Wait until the data has been transferred into the shift register. */ while ((USART_ISR(usart) & USART_ISR_TXE) == 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Received Data Available * * Blocks until the receive data buffer holds a valid received data word. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_wait_recv_ready(uint32_t usart) { /* Wait until the data is ready to be received. */ while ((USART_ISR(usart) & USART_ISR_RXNE) == 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Send Data Word with Blocking * * Blocks until the transmit data buffer becomes empty then writes the next * data word for transmission. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] data unsigned 16 bit. */ void usart_send_blocking(uint32_t usart, uint8_t data) { usart_wait_send_ready(usart); usart_send(usart, data); } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word with Blocking. * * Wait until a data word has been received then return the word. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @returns unsigned 16 bit data word. */ uint8_t usart_recv_blocking(uint32_t usart) { usart_wait_recv_ready(usart); return usart_recv(usart); } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver DMA Enable. * * DMA is available on: * @li USART1 Rx DMA1 channel 3 or 5. * @li USART2 Rx DMA1 channel 5. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_enable_rx_dma(uint32_t usart) { USART_CR3(usart) |= USART_CR3_DMAR; } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver DMA Disable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_disable_rx_dma(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_DMAR; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter DMA Enable. * * DMA is available on: * @li USART1 Tx DMA1 channel 2 or 4. * @li USART2 Tx DMA1 channel 4. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_enable_tx_dma(uint32_t usart) { USART_CR3(usart) |= USART_CR3_DMAT; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter DMA Disable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_disable_tx_dma(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_DMAT; } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver Interrupt Enable. @param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base */ void usart_enable_rx_interrupt(uint32_t usart) { USART_CR1(usart) |= USART_CR1_RXNEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Receiver Interrupt Disable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_disable_rx_interrupt(uint32_t usart) { USART_CR1(usart) &= ~USART_CR1_RXNEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter Interrupt Enable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_enable_tx_interrupt(uint32_t usart) { USART_CR1(usart) |= USART_CR1_TXEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Transmitter Interrupt Disable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_disable_tx_interrupt(uint32_t usart) { USART_CR1(usart) &= ~USART_CR1_TXEIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Error Interrupt Enable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_enable_error_interrupt(uint32_t usart) { USART_CR3(usart) |= USART_CR3_EIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Error Interrupt Disable. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_disable_error_interrupt(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_EIE; } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Status Flag. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. * @returns boolean: flag set. */ bool usart_get_flag(uint32_t usart, uint32_t flag) { return ((USART_ISR(usart) & flag) != 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Return Interrupt Source. * * Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was * set and the interrupt was enabled. If the specified flag is not an interrupt * flag, the function returns false. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. * @returns boolean: flag and interrupt enable both set. */ bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) { uint32_t flag_set = (USART_ISR(usart) & flag); /* IDLE, RXNE, TC, TXE interrupts */ if ((flag >= USART_ISR_IDLE) && (flag <= USART_ISR_TXE)) { return ((flag_set & USART_CR1(usart)) != 0); /* Overrun error */ } else if (flag == USART_ISR_ORE) { return flag_set && (USART_CR3(usart) & USART_CR3_CTSIE); } return false; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/000077500000000000000000000000001435536612600175155ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/Makefile000066400000000000000000000034721435536612600211630ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_stm32f1 PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F1 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = adc.o can.o desig.o ethernet.o flash.o gpio.o \ rcc.o rtc.o timer.o OBJS += crc_common_all.o dac_common_all.o dma_common_l1f013.o \ gpio_common_all.o i2c_common_all.o iwdg_common_all.o \ pwr_common_all.o spi_common_all.o spi_common_f124.o \ timer_common_all.o usart_common_all.o usart_common_f124.o \ exti_common_all.o OBJS += usb.o usb_control.o usb_standard.o usb_f103.o usb_f107.o \ usb_fx07_common.o VPATH += ../../usb:../:../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/adc.c000066400000000000000000001027051435536612600204150ustar00rootroot00000000000000/** @defgroup STM32F1xx_adc_file ADC @ingroup STM32F1xx @brief libopencm3 STM32F1xx Analog to Digital Converters @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Edward Cheeseman @author @htmlonly © @endhtmlonly 2012 Ken Sarkies @date 18 August 2012 This library supports the A/D Converter Control System in the STM32F1xx series of ARM Cortex Microcontrollers by ST Microelectronics. Devices can have up to three A/D converters each with their own set of registers. However all the A/D converters share a common clock which is prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum of 8. Each A/D converter has up to 18 channels: @li On ADC1 the analog channels 16 and 17 are internally connected to the temperature sensor and VREFINT, respectively. @li On ADC2 the analog channels 16 and 17 are internally connected to VSS. @li On ADC3 the analog channels 9, 14, 15, 16 and 17 are internally connected to VSS. The conversions can occur as a one-off conversion whereby the process stops once conversion is complete. The conversions can also be continuous wherein a new conversion starts immediately the previous conversion has ended. Conversion can occur as a single channel conversion or a scan of a group of channels in either continuous or one-off mode. If more than one channel is converted in a scan group, DMA must be used to transfer the data as there is only one result register available. An interrupt can be set to occur at the end of conversion, which occurs after all channels have been scanned. A discontinuous mode allows a subgroup of group of a channels to be converted in bursts of a given length. Injected conversions allow a second group of channels to be converted separately from the regular group. An interrupt can be set to occur at the end of conversion, which occurs after all channels have been scanned. @section adc_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock and ADC, reset ADC and set the prescaler divider. Set dual mode to independent (default). Enable triggering for a software trigger. @code rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); adc_off(ADC1); rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); adc_set_dual_mode(ADC_CR1_DUALMOD_IND); adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); adc_set_single_channel(ADC1, ADC_CHANNEL0); adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART); adc_power_on(ADC1); adc_reset_calibration(ADC1); adc_calibration(ADC1); adc_start_conversion_regular(ADC1); while (! adc_eoc(ADC1)); reg16 = adc_read_regular(ADC1); @endcode LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Edward Cheeseman * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* * Basic ADC handling API. * * Examples: * rcc_peripheral_enable_clock(&RCC_APB2ENR, ADC1EN); * rcc_peripheral_disable_clock(&RCC_APB2ENR, ADC1EN); * rcc_peripheral_reset(&RCC_APB2RSTR, ADC1RST); * rcc_peripheral_clear_reset(&RCC_APB2RSTR, ADC1RST); * * rcc_set_adc_clk(ADC_PRE_PLCK2_DIV2); * adc_set_dual_mode(ADC1, TODO); * reg16 = adc_read(ADC1, ADC_CH_0); */ /**@{*/ #include /*---------------------------------------------------------------------------*/ /** @brief ADC Power On If the ADC is in power-down mode then it is powered up. The application needs to wait a time of about 3 microseconds for stabilization before using the ADC. If the ADC is already on this function call has no effect. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_power_on(uint32_t adc) { if (!(ADC_CR2(adc) & ADC_CR2_ADON)) { ADC_CR2(adc) |= ADC_CR2_ADON; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Start a Conversion Without Trigger This initiates a conversion by software without a trigger. The ADC needs to be powered on before this is called, otherwise this function has no effect. Note that this is not available in other STM32F families. To ensure code compatibility, enable triggering and use a software trigger source @see adc_start_conversion_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_start_conversion_direct(uint32_t adc) { if (ADC_CR2(adc) & ADC_CR2_ADON) { ADC_CR2(adc) |= ADC_CR2_ADON; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Dual A/D Mode The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting is applied to ADC1 only. Start of conversion when triggered can cause simultaneous conversion with ADC2, or alternate conversion. Regular and injected conversions can be configured, each one being separately simultaneous or alternate. Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock cycles later. Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen clock cycles later, followed by ADC1 fourteen cycles later again. This can only be used on a single channel. Alternate trigger mode must occur on an injected channel group, and alternates between the ADCs on each trigger. Note that sampling must not overlap between ADCs on the same channel. Dual A/D converter modes possible: @li IND: Independent mode. @li CRSISM: Combined regular simultaneous + injected simultaneous mode. @li CRSATM: Combined regular simultaneous + alternate trigger mode. @li CISFIM: Combined injected simultaneous + fast interleaved mode. @li CISSIM: Combined injected simultaneous + slow interleaved mode. @li ISM: Injected simultaneous mode only. @li RSM: Regular simultaneous mode only. @li FIM: Fast interleaved mode only. @li SIM: Slow interleaved mode only. @li ATM: Alternate trigger mode only. @param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod */ void adc_set_dual_mode(uint32_t mode) { ADC1_CR1 |= mode; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag This flag is set after all channels of a regular or injected group have been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @returns bool. End of conversion flag. */ bool adc_eoc(uint32_t adc) { return ((ADC_SR(adc) & ADC_SR_EOC) != 0); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag for Injected Conversion This flag is set after all channels of an injected group have been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @returns bool. End of conversion flag. */ bool adc_eoc_injected(uint32_t adc) { return ((ADC_SR(adc) & ADC_SR_JEOC) != 0); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register The result read back is 12 bits, right or left aligned within the first 16 bits. For ADC1 only, the higher 16 bits will hold the result from ADC2 if an appropriate dual mode has been set @see adc_set_dual_mode. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @returns Unsigned int32 conversion result. */ uint32_t adc_read_regular(uint32_t adc) { return ADC_DR(adc); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read from an Injected Conversion Result Register The result read back from the selected injected result register (one of four) is 12 bits, right or left aligned within the first 16 bits. The result can have a negative value if the injected channel offset has been set @see adc_set_injected_offset. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] reg Unsigned int8. Register number (1 ... 4). @returns Unsigned int32 conversion result. */ uint32_t adc_read_injected(uint32_t adc, uint8_t reg) { switch (reg) { case 1: return ADC_JDR1(adc); case 2: return ADC_JDR2(adc); case 3: return ADC_JDR3(adc); case 4: return ADC_JDR4(adc); } return 0; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Injected Channel Data Offset This value is subtracted from the injected channel results after conversion is complete, and can result in negative results. A separate value can be specified for each injected data register. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] reg Unsigned int8. Register number (1 ... 4). @param[in] offset Unsigned int32. */ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) { switch (reg) { case 1: ADC_JOFR1(adc) = offset; break; case 2: ADC_JOFR2(adc) = offset; break; case 3: ADC_JOFR3(adc) = offset; break; case 4: ADC_JOFR4(adc) = offset; break; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_analog_watchdog_regular(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_AWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Regular Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_analog_watchdog_regular(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_AWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Injected Conversions The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_analog_watchdog_injected(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_JAWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_analog_watchdog_injected(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the defined regular channel group. The subgroup is defined by the number of consecutive channels to be converted. After a subgroup has been converted the next trigger will start conversion of the immediately following subgroup of the same length or until the whole group has all been converted. When the the whole group has been converted, the next trigger will restart conversion of the subgroup at the beginning of the whole group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum. */ void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length) { if ((length-1) > 7) { return; } ADC_CR1(adc) |= ADC_CR1_DISCEN; ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_discontinuous_mode_regular(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_DISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Injected Conversions In this mode the ADC converts sequentially one channel of the defined group of injected channels, cycling back to the first channel in the group once the entire group has been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_discontinuous_mode_injected(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_JDISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_discontinuous_mode_injected(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Automatic Injected Conversions The ADC converts a defined injected group of channels immediately after the regular channels have been converted. The external trigger on the injected channels is disabled as required. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_automatic_injected_group_conversion(uint32_t adc) { adc_disable_external_trigger_injected(adc); ADC_CR1(adc) |= ADC_CR1_JAUTO; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Automatic Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_automatic_injected_group_conversion(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JAUTO; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. @ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. If both are enabled, the same channel number is monitored. @ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel. */ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel) { uint32_t reg32; reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */ if (channel < 18) { reg32 |= channel; } ADC_CR1(adc) = reg32; ADC_CR1(adc) |= ADC_CR1_AWDSGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Scan Mode In this mode a conversion consists of a scan of the predefined set of channels, regular and injected, each channel conversion immediately following the previous one. It can use single, continuous or discontinuous mode. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_scan_mode(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_SCAN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Scan Mode @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_scan_mode(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_SCAN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Injected End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_eoc_interrupt_injected(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_JEOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Injected End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_eoc_interrupt_injected(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_awd_interrupt(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_AWDIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_awd_interrupt(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_AWDIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_eoc_interrupt(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_EOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_eoc_interrupt(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_EOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor This enables both the sensor and the reference voltage measurements on channels 16 and 17. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_temperature_sensor(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_TSVREFE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor Disabling this will reduce power consumption from the sensor and the reference voltage measurements. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_temperature_sensor(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_TSVREFE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels This starts conversion on a set of defined regular channels if the ADC trigger is set to be a software trigger. It is cleared by hardware once conversion starts. Note this is a software trigger and requires triggering to be enabled and the trigger source to be set appropriately otherwise conversion will not start. This is not the same as the ADC start conversion operation. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_start_conversion_regular(uint32_t adc) { /* Start conversion on regular channels. */ ADC_CR2(adc) |= ADC_CR2_SWSTART; /* Wait until the ADC starts the conversion. */ while (ADC_CR2(adc) & ADC_CR2_SWSTART); } /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Injected Channels This starts conversion on a set of defined injected channels if the ADC trigger is set to be a software trigger. It is cleared by hardware once conversion starts. Note this is a software trigger and requires triggering to be enabled and the trigger source to be set appropriately otherwise conversion will not start. This is not the same as the ADC start conversion operation. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_start_conversion_injected(uint32_t adc) { /* Start conversion on injected channels. */ ADC_CR2(adc) |= ADC_CR2_JSWSTART; /* Wait until the ADC starts the conversion. */ while (ADC_CR2(adc) & ADC_CR2_JSWSTART); } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels This enables an external trigger for set of defined regular channels. For ADC1 and ADC2 @li Timer 1 CC1 event @li Timer 1 CC2 event @li Timer 1 CC3 event @li Timer 2 CC2 event @li Timer 3 TRGO event @li Timer 4 CC4 event @li EXTI (TIM8_TRGO is also possible on some devices, see datasheet) @li Software Start For ADC3 @li Timer 3 CC1 event @li Timer 2 CC3 event @li Timer 1 CC3 event @li Timer 8 CC1 event @li Timer 8 TRGO event @li Timer 5 CC1 event @li Timer 5 CC3 event @li Software Start @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_regular_12 for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3. */ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger) { uint32_t reg32; reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK)); reg32 |= (trigger); ADC_CR2(adc) = reg32; ADC_CR2(adc) |= ADC_CR2_EXTTRIG; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_external_trigger_regular(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Injected Channels This enables an external trigger for set of defined injected channels. For ADC1 and ADC2 @li Timer 1 TRGO event @li Timer 1 CC4 event @li Timer 2 TRGO event @li Timer 2 CC1 event @li Timer 3 CC4 event @li Timer 4 TRGO event @li EXTI (TIM8 CC4 is also possible on some devices, see datasheet) @li Software Start For ADC3 @li Timer 1 TRGO event @li Timer 1 CC4 event @li Timer 4 CC3 event @li Timer 8 CC2 event @li Timer 8 CC4 event @li Timer 5 TRGO event @li Timer 5 CC4 event @li Software Start @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3. */ void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger) { uint32_t reg32; reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14] */ reg32 |= (trigger); ADC_CR2(adc) = reg32; ADC_CR2(adc) |= ADC_CR2_JEXTTRIG; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Injected Channels @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_external_trigger_injected(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_set_left_aligned(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_set_right_aligned(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5. ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer mode. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_enable_dma(uint32_t adc) { if ((adc == ADC1) | (adc == ADC3)) { ADC_CR2(adc) |= ADC_CR2_DMA; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_disable_dma(uint32_t adc) { if ((adc == ADC1) | (adc == ADC3)) { ADC_CR2(adc) &= ~ADC_CR2_DMA; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Initialize Calibration Registers This resets the calibration registers. It is not clear if this is required to be done before every calibration operation. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_reset_calibration(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_RSTCAL; while (ADC_CR2(adc) & ADC_CR2_RSTCAL); } /*---------------------------------------------------------------------------*/ /** @brief ADC Calibration The calibration data for the ADC is recomputed. The hardware clears the calibration status flag when calibration is complete. This function does not return until this happens and the ADC is ready for use. The ADC must have been powered down for at least 2 ADC clock cycles, then powered on. before calibration starts @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_calibration(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_CAL; while (ADC_CR2(adc) & ADC_CR2_CAL); } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode In this mode the ADC starts a new conversion of a single channel or a channel group immediately following completion of the previous channel group conversion. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_set_continuous_conversion_mode(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode In this mode the ADC performs a conversion of one channel or a channel group and stops. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_set_single_conversion_mode(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Power On If the ADC is in power-down mode then it is powered up. The application needs to wait a time of about 3 microseconds for stabilization before using the ADC. If the ADC is already on this function call will initiate a conversion. @deprecated to be removed in a later release @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_on(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_ADON; } /*---------------------------------------------------------------------------*/ /** @brief ADC Off Turn off the ADC to reduce power consumption to a few microamps. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. */ void adc_off(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_ADON; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg. */ void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) { uint32_t reg32; if (channel < 10) { reg32 = ADC_SMPR2(adc); reg32 &= ~(0x7 << (channel * 3)); reg32 |= (time << (channel * 3)); ADC_SMPR2(adc) = reg32; } else { reg32 = ADC_SMPR1(adc); reg32 &= ~(0x7 << ((channel - 10) * 3)); reg32 |= (time << ((channel - 10) * 3)); ADC_SMPR1(adc) = reg32; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for all channels. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg. */ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) { uint8_t i; uint32_t reg32 = 0; for (i = 0; i <= 9; i++) { reg32 |= (time << (i * 3)); } ADC_SMPR2(adc) = reg32; for (i = 10; i <= 17; i++) { reg32 |= (time << ((i - 10) * 3)); } ADC_SMPR1(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] threshold Unsigned int8. Upper threshold value. */ void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold) { uint32_t reg32 = 0; reg32 = (uint32_t)threshold; reg32 &= ~0xfffff000; /* Clear all bits above 11. */ ADC_HTR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] threshold Unsigned int8. Lower threshold value. */ void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold) { uint32_t reg32 = 0; reg32 = (uint32_t)threshold; reg32 &= ~0xfffff000; /* Clear all bits above 11. */ ADC_LTR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence Define a sequence of channels to be converted as a regular group with a length from 1 to 16 channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] length Unsigned int8. Number of channels in the group. @param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18. */ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0; uint8_t i = 0; /* Maximum sequence length is 16 channels. */ if (length > 16) { return; } for (i = 1; i <= length; i++) { if (i <= 6) { reg32_3 |= (channel[i - 1] << ((i - 1) * 5)); } if ((i > 6) & (i <= 12)) { reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5)); } if ((i > 12) & (i <= 16)) { reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5)); } } reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB); ADC_SQR1(adc) = reg32_1; ADC_SQR2(adc) = reg32_2; ADC_SQR3(adc) = reg32_3; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set an Injected Channel Conversion Sequence Defines a sequence of channels to be converted as an injected group with a length from 1 to 4 channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. @param[in] length Unsigned int8. Number of channels in the group. @param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18. */ void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { uint32_t reg32 = 0; uint8_t i = 0; /* Maximum sequence length is 4 channels. */ if (length > 4) { return; } for (i = 1; i <= length; i++) { reg32 |= (channel[4 - i] << ((4 - i) * 5)); } reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /* Aliases */ #ifdef __GNUC__ void adc_set_continous_conversion_mode(uint32_t adc) __attribute__((alias("adc_set_continuous_conversion_mode"))); void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time) __attribute__((alias("adc_set_sample_time"))); void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time) __attribute__((alias("adc_set_sample_time_on_all_channels"))); void adc_enable_jeoc_interrupt(uint32_t adc) __attribute__((alias("adc_enable_eoc_interrupt_injected"))); void adc_disable_jeoc_interrupt(uint32_t adc) __attribute__((alias("adc_disable_eoc_interrupt_injected"))); #endif /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/crc.c000066400000000000000000000017251435536612600204350ustar00rootroot00000000000000/** @defgroup crc_file CRC @ingroup STM32F1xx @brief libopencm3 STM32F1xx CRC @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/dac.c000066400000000000000000000017241435536612600204140ustar00rootroot00000000000000/** @defgroup dac_file DAC @ingroup STM32F1xx @brief libopencm3 STM32F1xx DAC @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/dma.c000066400000000000000000000017271435536612600204310ustar00rootroot00000000000000/** @defgroup dma_file DMA @ingroup STM32F1xx @brief libopencm3 STM32F1xx DMA @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/ethernet.c000066400000000000000000000032041435536612600214760ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data) { /* Set PHY and register addresses for write access. */ ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA); ETH_MACMIIAR |= (phy << 11) | (reg << 6) | ETH_MACMIIAR_MW; /* Set register value. */ ETH_MACMIIDR = data; /* Begin transaction. */ ETH_MACMIIAR |= ETH_MACMIIAR_MB; /* Wait for not busy. */ while (ETH_MACMIIAR & ETH_MACMIIAR_MB); } uint16_t eth_smi_read(uint8_t phy, uint8_t reg) { /* Set PHY and register addresses for write access. */ ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | ETH_MACMIIAR_MW); ETH_MACMIIAR |= (phy << 11) | (reg << 6); /* Begin transaction. */ ETH_MACMIIAR |= ETH_MACMIIAR_MB; /* Wait for not busy. */ while (ETH_MACMIIAR & ETH_MACMIIAR_MB); /* Set register value. */ return (uint16_t)(ETH_MACMIIDR); } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/flash.c000066400000000000000000000105121435536612600207550ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void flash_prefetch_buffer_enable(void) { FLASH_ACR |= FLASH_ACR_PRFTBE; } void flash_prefetch_buffer_disable(void) { FLASH_ACR &= ~FLASH_ACR_PRFTBE; } void flash_halfcycle_enable(void) { FLASH_ACR |= FLASH_ACR_HLFCYA; } void flash_halfcycle_disable(void) { FLASH_ACR &= ~FLASH_ACR_HLFCYA; } void flash_set_ws(uint32_t ws) { uint32_t reg32; reg32 = FLASH_ACR; reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2)); reg32 |= ws; FLASH_ACR = reg32; } void flash_unlock(void) { /* Clear the unlock state. */ FLASH_CR |= FLASH_CR_LOCK; /* Authorize the FPEC access. */ FLASH_KEYR = FLASH_KEYR_KEY1; FLASH_KEYR = FLASH_KEYR_KEY2; } void flash_lock(void) { FLASH_CR |= FLASH_CR_LOCK; } void flash_clear_pgerr_flag(void) { FLASH_SR |= FLASH_SR_PGERR; } void flash_clear_eop_flag(void) { FLASH_SR |= FLASH_SR_EOP; } void flash_clear_wrprterr_flag(void) { FLASH_SR |= FLASH_SR_WRPRTERR; } void flash_clear_bsy_flag(void) { FLASH_SR &= ~FLASH_SR_BSY; } void flash_clear_status_flags(void) { flash_clear_pgerr_flag(); flash_clear_eop_flag(); flash_clear_wrprterr_flag(); flash_clear_bsy_flag(); } uint32_t flash_get_status_flags(void) { return FLASH_SR &= (FLASH_SR_PGERR | FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_BSY); } void flash_unlock_option_bytes(void) { /* F1 uses same keys for flash and option */ FLASH_OPTKEYR = FLASH_KEYR_KEY1; FLASH_OPTKEYR = FLASH_KEYR_KEY2; } void flash_wait_for_last_operation(void) { while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY); } void flash_program_word(uint32_t address, uint32_t data) { /* Ensure that all flash operations are complete. */ flash_wait_for_last_operation(); /* Enable writes to flash. */ FLASH_CR |= FLASH_CR_PG; /* Program the first half of the word. */ MMIO16(address) = (uint16_t)data; /* Wait for the write to complete. */ flash_wait_for_last_operation(); /* Program the second half of the word. */ MMIO16(address + 2) = data >> 16; /* Wait for the write to complete. */ flash_wait_for_last_operation(); /* Disable writes to flash. */ FLASH_CR &= ~FLASH_CR_PG; } void flash_program_half_word(uint32_t address, uint16_t data) { flash_wait_for_last_operation(); FLASH_CR |= FLASH_CR_PG; MMIO16(address) = data; flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */ } void flash_erase_page(uint32_t page_address) { flash_wait_for_last_operation(); FLASH_CR |= FLASH_CR_PER; FLASH_AR = page_address; FLASH_CR |= FLASH_CR_STRT; flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_PER; } void flash_erase_all_pages(void) { flash_wait_for_last_operation(); FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */ flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */ } void flash_erase_option_bytes(void) { flash_wait_for_last_operation(); if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) { flash_unlock_option_bytes(); } FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */ FLASH_CR |= FLASH_CR_STRT; flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */ } void flash_program_option_bytes(uint32_t address, uint16_t data) { flash_wait_for_last_operation(); if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) { flash_unlock_option_bytes(); } FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */ MMIO16(address) = data; flash_wait_for_last_operation(); FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */ } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/gpio.c000066400000000000000000000154431435536612600206260ustar00rootroot00000000000000/** @defgroup gpio_file GPIO @ingroup STM32F1xx @brief libopencm3 STM32F1xx General Purpose I/O @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2012 Ken Sarkies @date 18 August 2012 Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO functionality with a number of alternate functions and must be configured to the alternate function mode if these are to be accessed. A feature is available to remap alternative functions to a limited set of alternative pins in the event of a clash of requirements. The data registers associated with each port for input and output are 32 bit with the upper 16 bits unused. The output buffer must be written as a 32 bit word, but individual bits may be set or reset separately in atomic operations to avoid race conditions during interrupts. Bits may also be individually locked to prevent accidental configuration changes. Once locked the configuration cannot be changed until after the next reset. Each port bit can be configured as analog or digital input, the latter can be floating or pulled up or down. As outputs they can be configured as either push-pull or open drain, digital I/O or alternate function, and with maximum output speeds of 2MHz, 10MHz, or 50MHz. On reset all ports are configured as digital floating input. @section gpio_api_ex Basic GPIO Handling API. Example 1: Push-pull digital output actions on ports C2 and C9 @code gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO2 | GPIO9); gpio_set(GPIOC, GPIO2 | GPIO9); gpio_clear(GPIOC, GPIO2); gpio_toggle(GPIOC, GPIO2 | GPIO9); gpio_port_write(GPIOC, 0x204); @endcode Example 1: Digital input on port C12 @code gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT, GPIO12); reg16 = gpio_port_read(GPIOC); @endcode LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief Set GPIO Pin Mode Sets the mode (input/output) and configuration (analog/digitial and open drain/push pull), for a set of GPIO pins on a given GPIO port. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] mode Unsigned int8. Pin mode @ref gpio_mode @param[in] cnf Unsigned int8. Pin configuration @ref gpio_cnf @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id If multiple pins are to be set, use logical OR '|' to separate them. */ void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint16_t gpios) { uint16_t i, offset = 0; uint32_t crl = 0, crh = 0, tmp32 = 0; /* * We want to set the config only for the pins mentioned in gpios, * but keeping the others, so read out the actual config first. */ crl = GPIO_CRL(gpioport); crh = GPIO_CRH(gpioport); /* Iterate over all bits, use i as the bitnumber. */ for (i = 0; i < 16; i++) { /* Only set the config if the bit is set in gpios. */ if (!((1 << i) & gpios)) { continue; } /* Calculate bit offset. */ offset = (i < 8) ? (i * 4) : ((i - 8) * 4); /* Use tmp32 to either modify crl or crh. */ tmp32 = (i < 8) ? crl : crh; /* Modify bits are needed. */ tmp32 &= ~(0xf << offset); /* Clear the bits first. */ tmp32 |= (mode << offset) | (cnf << (offset + 2)); /* Write tmp32 into crl or crh, leave the other unchanged. */ crl = (i < 8) ? tmp32 : crl; crh = (i >= 8) ? tmp32 : crh; } GPIO_CRL(gpioport) = crl; GPIO_CRH(gpioport) = crh; } /*---------------------------------------------------------------------------*/ /** @brief Map the EVENTOUT signal Enable the EVENTOUT signal and select the port and pin to be used. @param[in] evoutport Unsigned int8. Port for EVENTOUT signal @ref afio_evcr_port @param[in] evoutpin Unsigned int8. Pin for EVENTOUT signal @ref afio_evcr_pin */ void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin) { AFIO_EVCR = AFIO_EVCR_EVOE | evoutport | evoutpin; } /*---------------------------------------------------------------------------*/ /** @brief Map Alternate Function Port Bits (Main Set) A number of alternate function ports can be remapped to defined alternative port bits to avoid clashes in cases where multiple alternate functions are present. Refer to the datasheets for the particular mapping desired. This provides the main set of remap functionality. See @ref gpio_secondary_remap for a number of lesser used remaps. The AFIO remapping feature is used only with the STM32F10x series. @note The Serial Wire JTAG disable controls allow certain GPIO ports to become available in place of some of the SWJ signals. Full SWJ capability is obtained by setting this to zero. The value of this must be specified for every call to this function as its current value cannot be ascertained from the hardware. @param[in] swjdisable Unsigned int8. Disable parts of the SWJ capability @ref afio_swj_disable. @param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap, @ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2, @ref afio_remap_tim1, @ref afio_remap_usart3. For connectivity line devices only @ref afio_remap_cld are also available. */ void gpio_primary_remap(uint32_t swjdisable, uint32_t maps) { AFIO_MAPR |= (swjdisable & AFIO_MAPR_SWJ_MASK) | (maps & 0x1FFFFF); } /*---------------------------------------------------------------------------*/ /** @brief Map Alternate Function Port Bits (Secondary Set) A number of alternate function ports can be remapped to defined alternative port bits to avoid clashes in cases where multiple alternate functions are present. Refer to the datasheets for the particular mapping desired. This provides the second smaller and less used set of remap functionality. See @ref gpio_primary_remap for the main set of remaps. The AFIO remapping feature is used only with the STM32F10x series. @param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap2 */ void gpio_secondary_remap(uint32_t maps) { AFIO_MAPR2 |= maps; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/i2c.c000066400000000000000000000017251435536612600203430ustar00rootroot00000000000000/** @defgroup i2c_file I2C @ingroup STM32F1xx @brief libopencm3 STM32F1xx I2C @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/iwdg.c000066400000000000000000000017571435536612600206250ustar00rootroot00000000000000/** @defgroup iwdg_file IWDG @ingroup STM32F1xx @brief libopencm3 STM32F1xx Independent Watchdog Timer @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/libopencm3_stm32f1.ld000066400000000000000000000047631435536612600233620ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/pwr.c000066400000000000000000000023161435536612600204730ustar00rootroot00000000000000/** @defgroup pwr-file PWR @ingroup STM32F1xx @brief libopencm3 STM32F1xx Power Control @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Ken Sarkies @date 18 August 2012 This library supports the power control system for the STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/rcc.c000066400000000000000000001013571435536612600204370ustar00rootroot00000000000000/** @defgroup STM32F1xx-rcc-file RCC @ingroup STM32F1xx @brief libopencm3 STM32F1xx Reset and Clock Control @version 1.0.0 @author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2010 Thomas Otto @date 18 August 2012 This library supports the Reset and Clock Control System in the STM32F1xx series of ARM Cortex Microcontrollers by ST Microelectronics. @note Full support for connection line devices is not yet provided. Clock settings and resets for many peripherals are given here rather than in the corresponding peripheral library. The library also provides a number of common configurations for the processor system clock. Not all possible configurations are included. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include #include /** Default ppre1 peripheral clock frequency after reset. */ uint32_t rcc_ppre1_frequency = 8000000; /** Default ppre2 peripheral clock frequency after reset. */ uint32_t rcc_ppre2_frequency = 8000000; /*---------------------------------------------------------------------------*/ /** @brief RCC Clear the Oscillator Ready Interrupt Flag Clear the interrupt flag that was set when a clock oscillator became ready to use. @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_ready_int_clear(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; case PLL2: RCC_CIR |= RCC_CIR_PLL2RDYC; break; case PLL3: RCC_CIR |= RCC_CIR_PLL3RDYC; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_ready_int_enable(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; case PLL2: RCC_CIR |= RCC_CIR_PLL2RDYIE; break; case PLL3: RCC_CIR |= RCC_CIR_PLL3RDYIE; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_ready_int_disable(osc_t osc) { switch (osc) { case PLL: RCC_CIR &= ~RCC_CIR_PLLRDYIE; break; case PLL2: RCC_CIR &= ~RCC_CIR_PLL2RDYIE; break; case PLL3: RCC_CIR &= ~RCC_CIR_PLL3RDYIE; break; case HSE: RCC_CIR &= ~RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR &= ~RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR &= ~RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR &= ~RCC_CIR_LSIRDYIE; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag @param[in] osc enum ::osc_t. Oscillator ID @returns int. Boolean value for flag set. */ int rcc_osc_ready_int_flag(osc_t osc) { switch (osc) { case PLL: return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; case PLL2: return ((RCC_CIR & RCC_CIR_PLL2RDYF) != 0); break; case PLL3: return ((RCC_CIR & RCC_CIR_PLL3RDYF) != 0); break; case HSE: return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; case HSI: return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; case LSE: return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; case LSI: return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; } cm3_assert_not_reached(); } /*---------------------------------------------------------------------------*/ /** @brief RCC Clear the Clock Security System Interrupt Flag */ void rcc_css_int_clear(void) { RCC_CIR |= RCC_CIR_CSSC; } /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Clock Security System Interrupt Flag @returns int. Boolean value for flag set. */ int rcc_css_int_flag(void) { return ((RCC_CIR & RCC_CIR_CSSF) != 0); } /*---------------------------------------------------------------------------*/ /** @brief RCC Wait for Oscillator Ready. @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_wait_for_osc_ready(osc_t osc) { switch (osc) { case PLL: while ((RCC_CR & RCC_CR_PLLRDY) == 0); break; case PLL2: while ((RCC_CR & RCC_CR_PLL2RDY) == 0); break; case PLL3: while ((RCC_CR & RCC_CR_PLL3RDY) == 0); break; case HSE: while ((RCC_CR & RCC_CR_HSERDY) == 0); break; case HSI: while ((RCC_CR & RCC_CR_HSIRDY) == 0); break; case LSE: while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); break; case LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Turn on an Oscillator. Enable an oscillator and power on. Each oscillator requires an amount of time to settle to a usable state. Refer to datasheets for time delay information. A status flag is available to indicate when the oscillator becomes ready (see @ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready). @note The LSE clock is in the backup domain and cannot be enabled until the backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect). @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_on(osc_t osc) { switch (osc) { case PLL: RCC_CR |= RCC_CR_PLLON; break; case PLL2: RCC_CR |= RCC_CR_PLL2ON; break; case PLL3: RCC_CR |= RCC_CR_PLL3ON; break; case HSE: RCC_CR |= RCC_CR_HSEON; break; case HSI: RCC_CR |= RCC_CR_HSION; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEON; break; case LSI: RCC_CSR |= RCC_CSR_LSION; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Turn off an Oscillator. Disable an oscillator and power off. @note An oscillator cannot be turned off if it is selected as the system clock. @note The LSE clock is in the backup domain and cannot be disabled until the backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect) or the backup domain has been (see reset @ref rcc_backupdomain_reset). @param[in] osc enum ::osc_t. Oscillator ID */ void rcc_osc_off(osc_t osc) { switch (osc) { case PLL: RCC_CR &= ~RCC_CR_PLLON; break; case PLL2: RCC_CR &= ~RCC_CR_PLL2ON; break; case PLL3: RCC_CR &= ~RCC_CR_PLL3ON; break; case HSE: RCC_CR &= ~RCC_CR_HSEON; break; case HSI: RCC_CR &= ~RCC_CR_HSION; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEON; break; case LSI: RCC_CSR &= ~RCC_CSR_LSION; break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Clock Security System. */ void rcc_css_enable(void) { RCC_CR |= RCC_CR_CSSON; } /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Clock Security System. */ void rcc_css_disable(void) { RCC_CR &= ~RCC_CR_CSSON; } /*---------------------------------------------------------------------------*/ /** @brief RCC Enable Bypass. Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see @ref rcc_osc_on) and the internal clock must be disabled (see @ref rcc_osc_off) for this to have effect. @note The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect). @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect. */ void rcc_osc_bypass_enable(osc_t osc) { switch (osc) { case HSE: RCC_CR |= RCC_CR_HSEBYP; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEBYP; break; case PLL: case PLL2: case PLL3: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Disable Bypass. Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see @ref rcc_osc_off) for this to have effect. @note The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see @ref rcc_backupdomain_reset). @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect. */ void rcc_osc_bypass_disable(osc_t osc) { switch (osc) { case HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEBYP; break; case PLL: case PLL2: case PLL3: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } /*---------------------------------------------------------------------------*/ /** @brief RCC Enable Peripheral Clocks. Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register. @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) @param[in] en Unsigned int32. Logical OR of all enables to be set @li If register is RCC_AHBER, from @ref rcc_ahbenr_en @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en */ void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en) { *reg |= en; } /*---------------------------------------------------------------------------*/ /** @brief RCC Disable Peripheral Clocks. Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register. @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) @param[in] en Unsigned int32. Logical OR of all enables to be used for disabling. @li If register is RCC_AHBER, from @ref rcc_ahbenr_en @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en */ void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en) { *reg &= ~en; } /*---------------------------------------------------------------------------*/ /** @brief RCC Reset Peripherals. Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register. @param[in] *reg Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) @param[in] reset Unsigned int32. Logical OR of all resets. @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst */ void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset) { *reg |= reset; } /*---------------------------------------------------------------------------*/ /** @brief RCC Remove Reset on Peripherals. Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register. @param[in] *reg Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) @param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed: @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst */ void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset) { *reg &= ~clear_reset; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. @param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs */ void rcc_set_sysclk_source(uint32_t clk) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 1) | (1 << 0)); RCC_CFGR = (reg32 | clk); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL Multiplication Factor. @note This only has effect when the PLL is disabled. @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll_multiplication_factor(uint32_t mul) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18)); RCC_CFGR = (reg32 | (mul << 18)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL2 Multiplication Factor. @note This only has effect when the PLL is disabled. @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll2_multiplication_factor(uint32_t mul) { uint32_t reg32; reg32 = RCC_CFGR2; reg32 &= ~((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8)); RCC_CFGR2 = (reg32 | (mul << 8)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL3 Multiplication Factor. @note This only has effect when the PLL is disabled. @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll3_multiplication_factor(uint32_t mul) { uint32_t reg32; reg32 = RCC_CFGR2; reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12)); RCC_CFGR2 = (reg32 | (mul << 12)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL Clock Source. @note This only has effect when the PLL is disabled. @param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs */ void rcc_set_pll_source(uint32_t pllsrc) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~(1 << 16); RCC_CFGR = (reg32 | (pllsrc << 16)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source. @note This only has effect when the PLL is disabled. @param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre */ void rcc_set_pllxtpre(uint32_t pllxtpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~(1 << 17); RCC_CFGR = (reg32 | (pllxtpre << 17)); } /*---------------------------------------------------------------------------*/ /** @brief ADC Setup the A/D Clock The ADC's have a common clock prescale setting. @param[in] adcpre uint32_t. Prescale divider taken from @ref rcc_cfgr_adcpre */ void rcc_set_adcpre(uint32_t adcpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 14) | (1 << 15)); RCC_CFGR = (reg32 | (adcpre << 14)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB2 Prescale Factor. @param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre */ void rcc_set_ppre2(uint32_t ppre2) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13)); RCC_CFGR = (reg32 | (ppre2 << 11)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB1 Prescale Factor. @note The APB1 clock frequency must not exceed 36MHz. @param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre1(uint32_t ppre1) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10)); RCC_CFGR = (reg32 | (ppre1 << 8)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the AHB Prescale Factor. @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre */ void rcc_set_hpre(uint32_t hpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); RCC_CFGR = (reg32 | (hpre << 4)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Set the USB Prescale Factor. The prescale factor can be set to 1 (no prescale) for use when the PLL clock is 48MHz, or 1.5 to generate the 48MHz USB clock from a 64MHz PLL clock. @note This bit cannot be reset while the USB clock is enabled. @param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre */ void rcc_set_usbpre(uint32_t usbpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~(1 << 22); RCC_CFGR = (reg32 | (usbpre << 22)); } void rcc_set_prediv1(uint32_t prediv) { uint32_t reg32; reg32 = RCC_CFGR2; reg32 &= ~(1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); RCC_CFGR2 |= (reg32 | prediv); } void rcc_set_prediv2(uint32_t prediv) { uint32_t reg32; reg32 = RCC_CFGR2; reg32 &= ~(1 << 7) | (1 << 6) | (1 << 5) | (1 << 4); RCC_CFGR2 |= (reg32 | (prediv << 4)); } void rcc_set_prediv1_source(uint32_t rccsrc) { RCC_CFGR2 &= ~(1 << 16); RCC_CFGR2 |= (rccsrc << 16); } void rcc_set_mco(uint32_t mcosrc) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24)); RCC_CFGR |= (reg32 | (mcosrc << 24)); } /*---------------------------------------------------------------------------*/ /** @brief RCC Get the System Clock Source. @returns Unsigned int32. System clock source: @li 00 indicates HSE @li 01 indicates LSE @li 02 indicates PLL */ uint32_t rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ return (RCC_CFGR & 0x000c) >> 2; } /*---------------------------------------------------------------------------*/ /* * These functions are setting up the whole clock system for the most common * input clock and output clock configurations. */ /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 64MHz from HSI */ void rcc_clock_setup_in_hsi_out_64mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */ /* * Sysclk is running with 64MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 16. * 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 32000000; rcc_ppre2_frequency = 64000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 48MHz from HSI */ void rcc_clock_setup_in_hsi_out_48mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /*Set.48MHz Max.72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /*Set. 6MHz Max.14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /*Set.24MHz Max.36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /*Set.48MHz Max.72MHz */ rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /*Set.48MHz Max.48MHz */ /* * Sysclk runs with 48MHz -> 1 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_1WS); /* * Set the PLL multiplication factor to 12. * 8MHz (internal) * 12 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 48MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL12); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 24000000; rcc_ppre2_frequency = 48000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSI */ void rcc_clock_setup_in_hsi_out_24mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 24MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 12MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */ /* * Sysclk is (will be) running with 24MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_0WS); /* * Set the PLL multiplication factor to 6. * 8MHz (internal) * 6 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 24MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 24000000; rcc_ppre2_frequency = 24000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSE at 8MHz */ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 8MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */ /* * Sysclk runs with 24MHz -> 0 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_0WS); /* * Set the PLL multiplication factor to 3. * 8MHz (external) * 3 (multiplier) = 24MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL3); /* Select HSE as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * External frequency undivided before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 24000000; rcc_ppre2_frequency = 24000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 72MHz from HSE at 8MHz */ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 8MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. * 8MHz (external) * 9 (multiplier) = 72MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); /* Select HSE as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * External frequency undivided before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 36000000; rcc_ppre2_frequency = 72000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSE at 12MHz */ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 16MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. * 12MHz (external) * 6 (multiplier) / 1 (PLLXTPRE_HSE_CLK) = 72MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6); /* Select HSI as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * Divide external frequency by 2 before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 36000000; rcc_ppre2_frequency = 72000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSE at 16MHz */ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 16MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. * 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); /* Select HSI as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * Divide external frequency by 2 before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 36000000; rcc_ppre2_frequency = 72000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 72MHz from HSE at 25MHz */ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void) { /* Enable external high-speed oscillator 25MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* Set pll2 prediv and multiplier */ rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5); rcc_set_pll2_multiplication_factor(RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8); /* Enable PLL2 oscillator and wait for it to stabilize */ rcc_osc_on(PLL2); rcc_wait_for_osc_ready(PLL2); /* Set pll1 prediv/multiplier, prediv1 src, and usb predivider */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); rcc_set_prediv1_source(RCC_CFGR2_PREDIV1SRC_PLL2_CLK); rcc_set_prediv1(RCC_CFGR2_PREDIV_DIV5); rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); rcc_set_pll_source(RCC_CFGR_PLLSRC_PREDIV1_CLK); rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3); /* enable PLL1 and wait for it to stabilize */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ppre1_frequency = 36000000; rcc_ppre2_frequency = 72000000; } /*---------------------------------------------------------------------------*/ /** @brief RCC Reset the backup domain The backup domain register is reset to disable all controls. */ void rcc_backupdomain_reset(void) { /* Set the backup domain software reset. */ RCC_BDCR |= RCC_BDCR_BDRST; /* Clear the backup domain software reset. */ RCC_BDCR &= ~RCC_BDCR_BDRST; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/rtc.c000066400000000000000000000153541435536612600204610ustar00rootroot00000000000000/** @defgroup rtc_file RTC @ingroup STM32F1xx @brief libopencm3 STM32F1xx RTC @author @htmlonly © @endhtmlonly 2010 Uwe Hermann @author @htmlonly © @endhtmlonly 2010 Lord James @version 1.0.0 @date 4 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Uwe Hermann * Copyright (C) 2010 Lord James * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include void rtc_awake_from_off(osc_t clock_source) { uint32_t reg32; /* Enable power and backup interface clocks. */ RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* Enable access to the backup registers and the RTC. */ PWR_CR |= PWR_CR_DBP; /* * Reset the backup domain, clears everything RTC related. * If not wanted use the rtc_awake_from_standby() function. */ rcc_backupdomain_reset(); switch (clock_source) { case LSE: /* Turn the LSE on and wait while it stabilises. */ RCC_BDCR |= RCC_BDCR_LSEON; while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0); /* Choose LSE as the RTC clock source. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); RCC_BDCR |= (1 << 8); break; case LSI: /* Turn the LSI on and wait while it stabilises. */ RCC_CSR |= RCC_CSR_LSION; while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0); /* Choose LSI as the RTC clock source. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); RCC_BDCR |= (1 << 9); break; case HSE: /* Turn the HSE on and wait while it stabilises. */ RCC_CR |= RCC_CR_HSEON; while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0); /* Choose HSE as the RTC clock source. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); RCC_BDCR |= (1 << 9) | (1 << 8); break; case PLL: case PLL2: case PLL3: case HSI: /* Unusable clock source, here to prevent warnings. */ /* Turn off clock sources to RTC. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); break; } /* Enable the RTC. */ RCC_BDCR |= RCC_BDCR_RTCEN; /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ RTC_CRL &= ~RTC_CRL_RSF; while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); /* Wait for the last write operation to finish. */ /* TODO: Necessary? */ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); } void rtc_enter_config_mode(void) { uint32_t reg32; /* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); /* Enter configuration mode. */ RTC_CRL |= RTC_CRL_CNF; } void rtc_exit_config_mode(void) { uint32_t reg32; /* Exit configuration mode. */ RTC_CRL &= ~RTC_CRL_CNF; /* Wait until the RTOFF bit is 1 (our RTC register write finished). */ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); } void rtc_set_alarm_time(uint32_t alarm_time) { rtc_enter_config_mode(); RTC_ALRL = (alarm_time & 0x0000ffff); RTC_ALRH = (alarm_time & 0xffff0000) >> 16; rtc_exit_config_mode(); } void rtc_enable_alarm(void) { rtc_enter_config_mode(); RTC_CRH |= RTC_CRH_ALRIE; rtc_exit_config_mode(); } void rtc_disable_alarm(void) { rtc_enter_config_mode(); RTC_CRH &= ~RTC_CRH_ALRIE; rtc_exit_config_mode(); } void rtc_set_prescale_val(uint32_t prescale_val) { rtc_enter_config_mode(); RTC_PRLL = prescale_val & 0x0000ffff; /* PRL[15:0] */ RTC_PRLH = (prescale_val & 0x000f0000) >> 16; /* PRL[19:16] */ rtc_exit_config_mode(); } uint32_t rtc_get_counter_val(void) { return (RTC_CNTH << 16) | RTC_CNTL; } uint32_t rtc_get_prescale_div_val(void) { return (RTC_DIVH << 16) | RTC_DIVL; } uint32_t rtc_get_alarm_val(void) { return (RTC_ALRH << 16) | RTC_ALRL; } void rtc_set_counter_val(uint32_t counter_val) { rtc_enter_config_mode(); RTC_CNTH = (counter_val & 0xffff0000) >> 16; /* CNT[31:16] */ RTC_CNTL = counter_val & 0x0000ffff; /* CNT[15:0] */ rtc_exit_config_mode(); } void rtc_interrupt_enable(rtcflag_t flag_val) { rtc_enter_config_mode(); /* Set the correct interrupt enable. */ switch (flag_val) { case RTC_SEC: RTC_CRH |= RTC_CRH_SECIE; break; case RTC_ALR: RTC_CRH |= RTC_CRH_ALRIE; break; case RTC_OW: RTC_CRH |= RTC_CRH_OWIE; break; } rtc_exit_config_mode(); } void rtc_interrupt_disable(rtcflag_t flag_val) { rtc_enter_config_mode(); /* Disable the correct interrupt enable. */ switch (flag_val) { case RTC_SEC: RTC_CRH &= ~RTC_CRH_SECIE; break; case RTC_ALR: RTC_CRH &= ~RTC_CRH_ALRIE; break; case RTC_OW: RTC_CRH &= ~RTC_CRH_OWIE; break; } rtc_exit_config_mode(); } void rtc_clear_flag(rtcflag_t flag_val) { /* Configuration mode not needed. */ /* Clear the correct flag. */ switch (flag_val) { case RTC_SEC: RTC_CRL &= ~RTC_CRL_SECF; break; case RTC_ALR: RTC_CRL &= ~RTC_CRL_ALRF; break; case RTC_OW: RTC_CRL &= ~RTC_CRL_OWF; break; } } uint32_t rtc_check_flag(rtcflag_t flag_val) { uint32_t reg32; /* Read correct flag. */ switch (flag_val) { case RTC_SEC: reg32 = RTC_CRL & RTC_CRL_SECF; break; case RTC_ALR: reg32 = RTC_CRL & RTC_CRL_ALRF; break; case RTC_OW: reg32 = RTC_CRL & RTC_CRL_OWF; break; default: reg32 = 0; break; } return reg32; } void rtc_awake_from_standby(void) { uint32_t reg32; /* Enable power and backup interface clocks. */ RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* Enable access to the backup registers and the RTC. */ PWR_CR |= PWR_CR_DBP; /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ RTC_CRL &= ~RTC_CRL_RSF; while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); /* Wait for the last write operation to finish. */ /* TODO: Necessary? */ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); } void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val) { uint32_t reg32; /* Enable power and backup interface clocks. */ RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* Enable access to the backup registers and the RTC. */ /* TODO: Not sure if this is necessary to just read the flag. */ PWR_CR |= PWR_CR_DBP; reg32 = RCC_BDCR & RCC_BDCR_RTCEN; if (reg32 != 0) { rtc_awake_from_standby(); } else { rtc_awake_from_off(clock_source); rtc_set_prescale_val(prescale_val); } } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/spi.c000066400000000000000000000017241435536612600204600ustar00rootroot00000000000000/** @defgroup spi_file SPI @ingroup STM32F1xx @brief libopencm3 STM32F1xx SPI @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/stm32f100x4.ld000066400000000000000000000020221435536612600216450ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32F100x4, 16K flash, 4K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 16K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/stm32f100x6.ld000066400000000000000000000020221435536612600216470ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32F100x6, 32K flash, 4K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/stm32f100x8.ld000066400000000000000000000020221435536612600216510ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32F100x8, 64K flash, 8K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/stm32f100xb.ld000066400000000000000000000020231435536612600217240ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32F100xB, 128K flash, 8K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/stm32f100xc.ld000066400000000000000000000020261435536612600217300ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32F100xC, 256K flash, 24K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 24K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/stm32f100xd.ld000066400000000000000000000020261435536612600217310ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32F100xD, 384K flash, 32K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 384K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/stm32f100xe.ld000066400000000000000000000020261435536612600217320ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32F100xE, 512K flash, 32K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/timer.c000066400000000000000000000035261435536612600210070ustar00rootroot00000000000000/* This file is used for documentation purposes. It does not need to be compiled. All source code is in the common area. If there is any device specific code required it can be included here, in which case this file must be added to the compile list. */ /** @defgroup timer_file Timers @ingroup STM32F1xx @brief libopencm3 STM32F1xx Timers @version 1.0.0 @date 18 August 2012 */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /*---------------------------------------------------------------------------*/ /** @brief Set Input Polarity @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. @param[in] pol ::tim_ic_pol. Input Capture polarity. */ void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol) { if (pol) { TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4)); } else { TIM_CCER(timer_peripheral) &= ~(0x2 << (ic * 4)); } } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f1/usart.c000066400000000000000000000017361435536612600210260ustar00rootroot00000000000000/** @defgroup usart_file USART @ingroup STM32F1xx @brief libopencm3 STM32F1xx USART @version 1.0.0 @date 30 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/000077500000000000000000000000001435536612600175165ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/Makefile000066400000000000000000000034041435536612600211570ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_stm32f2 PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F2 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = gpio.o rcc.o OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ gpio_common_all.o gpio_common_f0234.o i2c_common_all.o \ iwdg_common_all.o rtc_common_l1f024.o spi_common_all.o \ spi_common_f124.o timer_common_all.o timer_common_f234.o \ timer_common_f24.o usart_common_all.o usart_common_f124.o \ flash_common_f234.o flash_common_f24.o hash_common_f24.o \ crypto_common_f24.o exti_common_all.o VPATH += ../../usb:../:../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/crc.c000066400000000000000000000017261435536612600204370ustar00rootroot00000000000000/** @defgroup crc_file CRC @ingroup STM32F2xx @brief libopencm3 STM32F2xx CRC @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/dac.c000066400000000000000000000017241435536612600204150ustar00rootroot00000000000000/** @defgroup dac_file DAC @ingroup STM32F2xx @brief libopencm3 STM32F2xx DAC @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/dma.c000066400000000000000000000017261435536612600204310ustar00rootroot00000000000000/** @defgroup dma_file DMA @ingroup STM32F2xx @brief libopencm3 STM32F2xx DMA @version 1.0.0 @date 30 November 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/gpio.c000066400000000000000000000016621435536612600206250ustar00rootroot00000000000000/** @defgroup gpio_file GPIO @ingroup STM32F2xx @brief libopencm3 STM32F2xx General Purpose I/O @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/i2c.c000066400000000000000000000017251435536612600203440ustar00rootroot00000000000000/** @defgroup i2c_file I2C @ingroup STM32F2xx @brief libopencm3 STM32F2xx I2C @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/iwdg.c000066400000000000000000000017571435536612600206260ustar00rootroot00000000000000/** @defgroup iwdg_file IWDG @ingroup STM32F2xx @brief libopencm3 STM32F2xx Independent Watchdog Timer @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/libopencm3_stm32f2.ld000066400000000000000000000047631435536612600233640ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/rcc.c000066400000000000000000000202011435536612600204240ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ uint32_t rcc_ppre1_frequency = 16000000; uint32_t rcc_ppre2_frequency = 16000000; const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = { { /* 120MHz */ .pllm = 8, .plln = 240, .pllp = 2, .pllq = 5, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 30000000, .apb2_frequency = 60000000, }, }; void rcc_osc_ready_int_clear(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; } } void rcc_osc_ready_int_enable(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; } } void rcc_osc_ready_int_disable(osc_t osc) { switch (osc) { case PLL: RCC_CIR &= ~RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR &= ~RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR &= ~RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR &= ~RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR &= ~RCC_CIR_LSIRDYIE; break; } } int rcc_osc_ready_int_flag(osc_t osc) { switch (osc) { case PLL: return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; case HSE: return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; case HSI: return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; case LSE: return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; case LSI: return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; } cm3_assert_not_reached(); } void rcc_css_int_clear(void) { RCC_CIR |= RCC_CIR_CSSC; } int rcc_css_int_flag(void) { return ((RCC_CIR & RCC_CIR_CSSF) != 0); } void rcc_wait_for_osc_ready(osc_t osc) { switch (osc) { case PLL: while ((RCC_CR & RCC_CR_PLLRDY) == 0); break; case HSE: while ((RCC_CR & RCC_CR_HSERDY) == 0); break; case HSI: while ((RCC_CR & RCC_CR_HSIRDY) == 0); break; case LSE: while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); break; case LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); break; } } void rcc_wait_for_sysclk_status(osc_t osc) { switch (osc) { case PLL: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); break; case HSE: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); break; case HSI: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); break; default: /* Shouldn't be reached. */ break; } } void rcc_osc_on(osc_t osc) { switch (osc) { case PLL: RCC_CR |= RCC_CR_PLLON; break; case HSE: RCC_CR |= RCC_CR_HSEON; break; case HSI: RCC_CR |= RCC_CR_HSION; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEON; break; case LSI: RCC_CSR |= RCC_CSR_LSION; break; } } void rcc_osc_off(osc_t osc) { switch (osc) { case PLL: RCC_CR &= ~RCC_CR_PLLON; break; case HSE: RCC_CR &= ~RCC_CR_HSEON; break; case HSI: RCC_CR &= ~RCC_CR_HSION; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEON; break; case LSI: RCC_CSR &= ~RCC_CSR_LSION; break; } } void rcc_css_enable(void) { RCC_CR |= RCC_CR_CSSON; } void rcc_css_disable(void) { RCC_CR &= ~RCC_CR_CSSON; } void rcc_osc_bypass_enable(osc_t osc) { switch (osc) { case HSE: RCC_CR |= RCC_CR_HSEBYP; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_osc_bypass_disable(osc_t osc) { switch (osc) { case HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en) { *reg |= en; } void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en) { *reg &= ~en; } void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset) { *reg |= reset; } void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset) { *reg &= ~clear_reset; } void rcc_set_sysclk_source(uint32_t clk) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 1) | (1 << 0)); RCC_CFGR = (reg32 | clk); } void rcc_set_pll_source(uint32_t pllsrc) { uint32_t reg32; reg32 = RCC_PLLCFGR; reg32 &= ~(1 << 22); RCC_PLLCFGR = (reg32 | (pllsrc << 22)); } void rcc_set_ppre2(uint32_t ppre2) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15)); RCC_CFGR = (reg32 | (ppre2 << 13)); } void rcc_set_ppre1(uint32_t ppre1) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12)); RCC_CFGR = (reg32 | (ppre1 << 10)); } void rcc_set_hpre(uint32_t hpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); RCC_CFGR = (reg32 | (hpre << 4)); } void rcc_set_rtcpre(uint32_t rtcpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); RCC_CFGR = (reg32 | (rtcpre << 16)); } void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq) { RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | (plln << RCC_PLLCFGR_PLLN_SHIFT) | (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | (pllq << RCC_PLLCFGR_PLLQ_SHIFT); } void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq) { RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | (plln << RCC_PLLCFGR_PLLN_SHIFT) | (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | RCC_PLLCFGR_PLLSRC | (pllq << RCC_PLLCFGR_PLLQ_SHIFT); } uint32_t rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ return (RCC_CFGR & 0x000c) >> 2; } void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* Enable external high-speed oscillator 8MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_set_main_pll_hse(clock->pllm, clock->plln, clock->pllp, clock->pllq); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; } void rcc_backupdomain_reset(void) { /* Set the backup domain software reset. */ RCC_BDCR |= RCC_BDCR_BDRST; /* Clear the backup domain software reset. */ RCC_BDCR &= ~RCC_BDCR_BDRST; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/rtc.c000066400000000000000000000017561435536612600204630ustar00rootroot00000000000000/** @defgroup rtc_file RTC * * @ingroup STM32F2xx * * @brief libopencm3 STM32F2xx RTC * * @version 1.0.0 * * @date 4 March 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/spi.c000066400000000000000000000017251435536612600204620ustar00rootroot00000000000000/** @defgroup spi_file SPI @ingroup STM32F2xx @brief libopencm3 STM32F2xx SPI @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/timer.c000066400000000000000000000025001435536612600207770ustar00rootroot00000000000000/* This file is used for documentation purposes. It does not need to be compiled. All source code is in the common area. If there is any device specific code required it can be included here, in which case this file must be added to the compile list. */ /** @defgroup timer_file Timers @ingroup STM32F2xx @brief libopencm3 STM32F2xx Timers @version 1.0.0 @date 18 August 2012 */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f2/usart.c000066400000000000000000000017361435536612600210270ustar00rootroot00000000000000/** @defgroup usart_file USART @ingroup STM32F2xx @brief libopencm3 STM32F2xx USART @version 1.0.0 @date 30 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/000077500000000000000000000000001435536612600175175ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/Makefile000066400000000000000000000032741435536612600211650ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_stm32f3 FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m4 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F3 ARFLAGS = rcs OBJS = rcc.o gpio.o adc.o i2c.o spi.o usart.o dma.o OBJS += gpio_common_all.o gpio_common_f0234.o \ dac_common_all.o usart_common_all.o crc_common_all.o\ iwdg_common_all.o spi_common_all.o dma_common_l1f013.o\ timer_common_all.o timer_common_f234.o flash_common_f234.o \ flash.o exti_common_all.o OBJS += usb.o usb_control.o usb_standard.o usb_f103.o VPATH += ../../usb:../:../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/adc.c000066400000000000000000001045321435536612600204170ustar00rootroot00000000000000/** @defgroup adc_file ADC * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx Analog to Digital Converters * * @author @htmlonly © @endhtmlonly 2012 * Ken Sarkies * * @date 30 August 2012 * * This library supports the A/D Converter Control System in the STM32 series * of ARM Cortex Microcontrollers by ST Microelectronics. * * Devices can have up to three A/D converters each with their own set of * registers. However all the A/D converters share a common clock which is * prescaled from the APB2 clock by default by a minimum factor of 2 to a * maximum of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. * * Each A/D converter has up to 19 channels: * @li On ADC1 the analog channels 16 is internally connected to the * temperature sensor, channel 17 to VREFINT, and channel 18 * to VBATT. * @li On ADC2 and ADC3 the analog channels 16 - 18 are not used. * * The conversions can occur as a one-off conversion whereby the process stops * once conversion is complete. The conversions can also be continuous wherein * a new conversion starts immediately the previous conversion has ended. * * Conversion can occur as a single channel conversion or a scan of a group of * channels in either continuous or one-off mode. If more than one channel is * converted in a scan group, DMA must be used to transfer the data as there is * only one result register available. An interrupt can be set to occur at the * end* * of conversion, which occurs after all channels have been scanned. * * A discontinuous mode allows a subgroup of group of a channels to be * converted in bursts of a given length. * * Injected conversions allow a second group of channels to be converted * separately from the regular group. An interrupt can be set to occur at the * end of conversion, which occurs after all channels have been scanned. * * @section adc_f3_api_ex Basic ADC Handling API. * * Example 1: Simple single channel conversion polled. Enable the peripheral * clock and ADC, reset ADC and set the prescaler divider. Set multiple mode to * independent. * * @code * gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); * rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); * adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2); * adc_disable_scan_mode(ADC1); * adc_set_single_conversion_mode(ADC1); * adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); * uint8_t channels[] = ADC_CHANNEL0; * adc_set_regular_sequence(ADC1, 1, channels); * adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); * adc_power_on(ADC1); * adc_start_conversion_regular(ADC1); * while (! adc_eoc(ADC1)); * reg16 = adc_read_regular(ADC1); * @endcode * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Off * * Turn off the ADC to reduce power consumption to a few microamps. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_off(uint32_t adc) { ADC_CR(adc) &= ~ADC_CR_ADEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions * * The analog watchdog allows the monitoring of an analog signal between two * threshold levels. The thresholds must be preset. Comparison is done before * data alignment takes place, so the thresholds are left-aligned. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_analog_watchdog_regular(uint32_t adc) { ADC_CFGR(adc) |= ADC_CFGR_AWD1EN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions * * The analog watchdog allows the monitoring of an analog signal between two * threshold levels. The thresholds must be preset. Comparison is done before * data alignment takes place, so the thresholds are left-aligned. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_analog_watchdog_regular(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_AWD1EN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Injected Conversions * * The analog watchdog allows the monitoring of an analog signal between two * threshold levels. The thresholds must be preset. Comparison is done before * data alignment takes place, so the thresholds are left-aligned. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_analog_watchdog_injected(uint32_t adc) { ADC_CFGR(adc) |= ADC_CFGR_JAWD1EN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Injected Conversions * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_analog_watchdog_injected(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_JAWD1EN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions * * In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the * defined regular channel group. The subgroup is defined by the number of * consecutive channels to be converted. After a subgroup has been converted * the next trigger will start conversion of the immediately following subgroup * of the same length or until the whole group has all been converted. When the * whole group has been converted, the next trigger will restart conversion of * the subgroup at the beginning of the whole group. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base @param[in] length Unsigned int8. Number of channels in the * group @ref adc_cr1_discnum */ void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length) { if ((length-1) > 7) { return; } ADC_CFGR(adc) |= ADC_CFGR_DISCEN; ADC_CFGR(adc) |= ((length-1) << ADC_CFGR_DISCNUM_SHIFT); } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_discontinuous_mode_regular(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_DISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Injected Conversions * * In this mode the ADC converts sequentially one channel of the defined group * of injected channels, cycling back to the first channel in the group once * the entire group has been converted. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_discontinuous_mode_injected(uint32_t adc) { ADC_CFGR(adc) |= ADC_CFGR_JDISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Injected Conversions * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_discontinuous_mode_injected(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_JDISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Automatic Injected Conversions * * The ADC converts a defined injected group of channels immediately after the * regular channels have been converted. The external trigger on the injected * channels is disabled as required. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_automatic_injected_group_conversion(uint32_t adc) { adc_disable_external_trigger_injected(adc); ADC_CFGR(adc) |= ADC_CFGR_JAUTO; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Automatic Injected Conversions * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_automatic_injected_group_conversion(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_JAUTO; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels * * The analog watchdog allows the monitoring of an analog signal between two * threshold levels. The thresholds must be preset. Comparison is done before * data alignment takes place, so the thresholds are left-aligned. * * @note The analog watchdog must be enabled for either or both of the regular * or injected channels. If neither are enabled, the analog watchdog feature * will be disabled. * * @ref adc_enable_analog_watchdog_injected, @ref * adc_enable_analog_watchdog_regular. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_AWD1SGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel * * The analog watchdog allows the monitoring of an analog signal between two * threshold levels. The thresholds must be preset. Comparison is done before * data alignment takes place, so the thresholds are left-aligned. * * @note The analog watchdog must be enabled for either or both of the regular * or injected channels. If neither are enabled, the analog watchdog feature * will be disabled. If both are enabled, the same channel number is monitored * @ref adc_enable_analog_watchdog_injected, @ref * adc_enable_analog_watchdog_regular. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base * @param[in] channel Unsigned int8. ADC channel numbe * @ref adc_watchdog_channel */ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel) { uint32_t reg32; reg32 = (ADC_CFGR(adc) & ~ADC_CFGR_AWD1CH_MASK); /* Clear bit [4:0]. */ if (channel < 18) { reg32 |= channel; } ADC_CFGR(adc) = reg32; ADC_CFGR(adc) |= ADC_CFGR_AWD1SGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Scan Mode * * In this mode a conversion consists of a scan of the predefined set of * channels, regular and injected, each channel conversion immediately * following the previous one. It can use single, continuous or discontinuous * mode. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ /* void adc_enable_scan_mode(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_SCAN; } */ /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Scan Mode * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ /* void adc_disable_scan_mode(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_SCAN; } */ /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Injected End-Of-Conversion Interrupt * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_eoc_interrupt_injected(uint32_t adc) { ADC_IER(adc) |= ADC_IER_JEOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Injected End-Of-Conversion Interrupt * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_eoc_interrupt_injected(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_JEOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_all_awd_interrupt(uint32_t adc) { ADC_IER(adc) |= ADC_IER_AWD1IE; ADC_IER(adc) |= ADC_IER_AWD2IE; ADC_IER(adc) |= ADC_IER_AWD3IE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog Interrupt * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_all_awd_interrupt(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_AWD1IE; ADC_IER(adc) &= ~ADC_IER_AWD2IE; ADC_IER(adc) &= ~ADC_IER_AWD3IE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_eoc_interrupt(uint32_t adc) { ADC_IER(adc) |= ADC_IER_EOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_eoc_interrupt(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_EOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels * * This starts conversion on a set of defined regular channels. It is cleared * by hardware once conversion starts. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_start_conversion_regular(uint32_t adc) { /* Start conversion on regular channels. */ ADC_CR(adc) |= ADC_CR_ADSTART; /* Wait until the ADC starts the conversion. */ while (ADC_CR(adc) & ADC_CR_ADSTART); } /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Injected Channels * * This starts conversion on a set of defined injected channels. It is cleared * by hardware once conversion starts. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_start_conversion_injected(uint32_t adc) { /* Start conversion on injected channels. */ ADC_CR(adc) |= ADC_CR_JADSTART; /* Wait until the ADC starts the conversion. */ while (ADC_CR(adc) & ADC_CR_JADSTART); } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_set_left_aligned(uint32_t adc) { ADC_CFGR(adc) |= ADC_CFGR_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_set_right_aligned(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base */ void adc_enable_dma(uint32_t adc) { ADC_CFGR(adc) |= ADC_CFGR_DMAEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base */ void adc_disable_dma(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_DMAEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode * * In this mode the ADC starts a new conversion of a single channel or a channel * group immediately following completion of the previous channel group * conversion. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base */ void adc_set_continuous_conversion_mode(uint32_t adc) { ADC_CFGR(adc) |= ADC_CFGR_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode * * In this mode the ADC performs a conversion of one channel or a channel group * and stops. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base */ void adc_set_single_conversion_mode(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel * * The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] channel Unsigned int8. ADC Channel integer 0..18 or from * @ref adc_channel * @param[in] time Unsigned int8. Sampling time selection from * @ref adc_sample_rg */ void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) { uint32_t reg32; if (channel < 10) { reg32 = ADC_SMPR2(adc); reg32 &= ~(0x7 << (channel * 3)); reg32 |= (time << (channel * 3)); ADC_SMPR2(adc) = reg32; } else { reg32 = ADC_SMPR1(adc); reg32 &= ~(0x7 << ((channel - 10) * 3)); reg32 |= (time << ((channel - 10) * 3)); ADC_SMPR1(adc) = reg32; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels * * The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, * same for all channels. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] time Unsigned int8. Sampling time selection from * @ref adc_sample_rg */ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) { uint8_t i; uint32_t reg32 = 0; for (i = 0; i <= 9; i++) { reg32 |= (time << (i * 3)); } ADC_SMPR2(adc) = reg32; for (i = 10; i <= 17; i++) { reg32 |= (time << ((i - 10) * 3)); } ADC_SMPR1(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] threshold Unsigned int8. Upper threshold value */ void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold) { uint32_t reg32 = 0; reg32 |= (threshold << 16); reg32 &= ~0xff00ffff; /* Clear all bits above 8. */ ADC_TR1(adc) = reg32; ADC_TR2(adc) = reg32; ADC_TR3(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] threshold Unsigned int8. Lower threshold value */ void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold) { uint32_t reg32 = 0; reg32 = (uint32_t)threshold; reg32 &= ~0xffffff00; /* Clear all bits above 8. */ ADC_TR1(adc) = reg32; ADC_TR2(adc) = reg32; ADC_TR3(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence * * Define a sequence of channels to be converted as a regular group with a * length from 1 to 16 channels. If this is called during conversion, the * current conversion is reset and conversion begins again with the newly * defined group. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] length Unsigned int8. Number of channels in the group. * @param[in] channel Unsigned int8[]. Set of channels in sequence, integers * 0..18. */ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0, reg32_4 = 0; uint8_t i = 0; /* Maximum sequence length is 16 channels. */ if (length > 16) { return; } for (i = 1; i <= length; i++) { if (i <= 4) { reg32_1 |= (channel[i - 1] << (i * 6)); } if ((i > 4) & (i <= 9)) { reg32_2 |= (channel[i - 1] << ((i - 4 - 1) * 6)); } if ((i > 9) & (i <= 14)) { reg32_3 |= (channel[i - 1] << ((i - 9 - 1) * 6)); } if ((i > 14) & (i <= 16)) { reg32_4 |= (channel[i - 1] << ((i - 14 - 1) * 6)); } } reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB); ADC_SQR1(adc) = reg32_1; ADC_SQR2(adc) = reg32_2; ADC_SQR3(adc) = reg32_3; ADC_SQR4(adc) = reg32_4; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set an Injected Channel Conversion Sequence * * Defines a sequence of channels to be converted as an injected group with a * length from 1 to 4 channels. If this is called during conversion, the current * conversion is reset and conversion begins again with the newly defined group. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] length Unsigned int8. Number of channels in the group. * @param[in] channel Unsigned int8[]. Set of channels in sequence, integers * 0..18 */ void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { uint32_t reg32 = 0; uint8_t i = 0; /* Maximum sequence length is 4 channels. */ if ((length-1) > 3) { return; } for (i = 1; i <= length; i++) { reg32 |= (channel[4 - i] << ((4 - i) * 5)); } reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag * * This flag is set after all channels of a regular or injected group have been * converted. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @returns bool. End of conversion flag. */ bool adc_eoc(uint32_t adc) { return ((ADC_ISR(adc) & ADC_ISR_EOC) != 0); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag for Injected Conversion * * This flag is set after all channels of an injected group have been * converted. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @returns bool. End of conversion flag. */ bool adc_eoc_injected(uint32_t adc) { return ((ADC_ISR(adc) & ADC_ISR_JEOC) != 0); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register * * The result read back is 12 bits, right or left aligned within the first * 16 bits. For ADC1 only, the higher 16 bits will hold the result from ADC2 if * an appropriate dual mode has been set @see adc_set_dual_mode. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @returns Unsigned int32 conversion result. */ uint32_t adc_read_regular(uint32_t adc) { return ADC_DR(adc); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read from an Injected Conversion Result Register * * The result read back from the selected injected result register (one of four) * is 12 bits, right or left aligned within the first 16 bits. The result can * have a negative value if the injected channel offset has been set @see * adc_set_injected_offset. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base * @param[in] reg Unsigned int8. Register number (1 ... 4). * @returns Unsigned int32 conversion result. */ uint32_t adc_read_injected(uint32_t adc, uint8_t reg) { switch (reg) { case 1: return ADC_JDR1(adc); case 2: return ADC_JDR2(adc); case 3: return ADC_JDR3(adc); case 4: return ADC_JDR4(adc); } return 0; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Injected Channel Data Offset * * This value is subtracted from the injected channel results after conversion * is complete, and can result in negative results. A separate value can be * specified for each injected data register. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] reg Unsigned int8. Register number (1 ... 4). * @param[in] offset Unsigned int32. */ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) { switch (reg) { case 1: ADC_OFR1(adc) |= ADC_OFR1_OFFSET1_EN; ADC_OFR1(adc) |= offset; break; case 2: ADC_OFR2(adc) |= ADC_OFR2_OFFSET2_EN; ADC_OFR2(adc) |= offset; break; case 3: ADC_OFR3(adc) |= ADC_OFR3_OFFSET3_EN; ADC_OFR3(adc) |= offset; break; case 4: ADC_OFR4(adc) |= ADC_OFR4_OFFSET4_EN; ADC_OFR4(adc) |= offset; break; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Power On * * If the ADC is in power-down mode then it is powered up. The application * needs to wait a time of about 3 microseconds for stabilization before using * the ADC. If the ADC is already on this function call will have no effect. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_power_on(uint32_t adc) { ADC_CR(adc) |= ADC_CR_ADEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale * * The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. * * @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref * adc_ccr_adcpre */ void adc_set_clk_prescale(uint32_t prescale) { uint32_t reg32 = ((ADC_CCR & ~ADC_CCR_CKMODE_MASK) | prescale); ADC_CCR = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Dual/Triple Mode * * The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave * arrangement. This setting is applied to ADC1 only. * * The various modes possible are described in the reference manual. * * @param[in] mode Unsigned int32. Multiple mode selection from @ref * adc_multi_mode */ void adc_set_multi_mode(uint32_t mode) { ADC_CCR |= mode; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels * * This enables an external trigger for set of defined regular channels, and * sets the polarity of the trigger event: rising or falling edge or both. Note * that if the trigger polarity is zero, triggering is disabled. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base * @param[in] trigger Unsigned int32. Trigger identifier * @ref adc_trigger_regular * @param[in] polarity Unsigned int32. Trigger polarity @ref * adc_trigger_polarity_regular */ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity) { uint32_t reg32 = ADC_CFGR(adc); reg32 &= ~(ADC_CFGR_EXTSEL_MASK | ADC_CFGR_EXTEN_MASK); reg32 |= (trigger | polarity); ADC_CFGR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base */ void adc_disable_external_trigger_regular(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_EXTEN_MASK; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Injected Channels * * This enables an external trigger for set of defined injected channels, and * sets the polarity of the trigger event: rising or falling edge or both. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @param[in] trigger Unsigned int8. Trigger identifier * @ref adc_trigger_injected * @param[in] polarity Unsigned int32. Trigger polarity * @ref adc_trigger_polarity_injected */ void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity) { uint32_t reg32 = ADC_JSQR(adc); reg32 &= ~(ADC_JSQR_JEXTSEL_MASK | ADC_JSQR_JEXTEN_MASK); reg32 |= (trigger | polarity); ADC_JSQR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Injected Channels * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_external_trigger_injected(uint32_t adc) { ADC_JSQR(adc) &= ~ADC_JSQR_JEXTEN_MASK; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Resolution * * ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a * corresponding reduction in conversion time (resolution + 3 ADC clock cycles). * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base * @param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res */ void adc_set_resolution(uint32_t adc, uint16_t resolution) { uint32_t reg32 = ADC_CFGR(adc); reg32 &= ~ADC_CFGR_RES_MASK; reg32 |= resolution; ADC_CFGR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable the Overrun Interrupt * * The overrun interrupt is generated when data is not read from a result * register before the next conversion is written. If DMA is enabled, all * transfers are terminated and any conversion sequence is aborted. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_overrun_interrupt(uint32_t adc) { ADC_IER(adc) |= ADC_IER_OVRIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable the Overrun Interrupt * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_overrun_interrupt(uint32_t adc) { ADC_IER(adc) &= ~ADC_IER_OVRIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Overrun Flag * * The overrun flag is set when data is not read from a result register before * the next conversion is written. If DMA is enabled, all transfers are * terminated and any conversion sequence is aborted. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base * @returns Unsigned int32 conversion result. */ bool adc_get_overrun_flag(uint32_t adc) { return ADC_ISR(adc) & ADC_ISR_OVR; } /*---------------------------------------------------------------------------*/ /** @brief ADC Clear Overrun Flags * * The overrun flag is cleared. Note that if an overrun occurs, DMA is * terminated. * The flag must be cleared and the DMA stream and ADC reinitialised to resume * conversions (see the reference manual). * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @returns Unsigned int32 conversion result. */ void adc_clear_overrun_flag(uint32_t adc) { /* need to write zero to clear this */ ADC_ISR(adc) &= ~ADC_ISR_OVR; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an EOC for Each Conversion * * The EOC is set after each conversion in a sequence rather than at the end of * the sequence. Overrun detection is enabled only if DMA is enabled. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base */ void adc_eoc_after_each(uint32_t adc) { ADC_ISR(adc) |= ADC_ISR_EOS; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable the EOC for Each Conversion * * The EOC is set at the end of each sequence rather than after each conversion * in the sequence. Overrun detection is enabled always. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_eoc_after_group(uint32_t adc) { ADC_ISR(adc) &= ~ADC_ISR_EOS; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Continue * * This must be set to allow DMA to continue to operate after the last * conversion in the DMA sequence. This allows DMA to be used in continuous * circular mode. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ /* void adc_set_dma_continue(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_DDS; } */ /*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Terminate * * This must be set to allow DMA to terminate after the last conversion in the * DMA sequence. This can avoid overrun errors. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base */ /* void adc_set_dma_terminate(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_DDS; } */ /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Analog Watchdog Flag * * This flag is set when the converted voltage crosses the high or low * thresholds. * * @param[in] adc Unsigned int32. ADC block register address base * @ref adc_reg_base * @returns bool. AWD flag. */ bool adc_awd(uint32_t adc) { return (ADC_ISR(adc) & ADC_ISR_AWD1) && (ADC_ISR(adc) & ADC_ISR_AWD2) && (ADC_ISR(adc) & ADC_ISR_AWD3); } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor * * This enables both the sensor and the reference voltage measurements on * channels * 16 and 17. These are only available on ADC1 channel 16 and 17 respectively. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_enable_temperature_sensor() { ADC_CCR |= ADC_CCR_TSEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor * * Disabling this will reduce power consumption from the sensor and the * reference voltage measurements. * * @param[in] adc Unsigned int32. ADC block register address base @ref * adc_reg_base */ void adc_disable_temperature_sensor() { ADC_CCR &= ~ADC_CCR_TSEN; } /*---------------------------------------------------------------------------*/ /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/crc.c000066400000000000000000000016741435536612600204420ustar00rootroot00000000000000/** @defgroup crc_file CRC * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx CRC * * @version 1.0.0 * * @date 15 October 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/dac.c000066400000000000000000000017561435536612600204230ustar00rootroot00000000000000/** @defgroup dac_file DAC * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx DAC * * @version 1.0.0 * * @date 18 August 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/dma.c000066400000000000000000000020001435536612600204140ustar00rootroot00000000000000/** @defgroup dma_file DMA * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx Direct Memory Access * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/flash.c000066400000000000000000000022561435536612600207650ustar00rootroot00000000000000/** @defgroup flash_file FLASH * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx FLASH * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void flash_clear_status_flags(void) { flash_clear_pgperr_flag(); flash_clear_eop_flag(); flash_clear_bsy_flag(); } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/gpio.c000066400000000000000000000076111435536612600206260ustar00rootroot00000000000000/** @defgroup gpio_file GPIO * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx General Purpose I/O * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Fergus Noble * Modified by 2013 Fernando Cortes (stm32f3) * Modified by 2013 Guillermo Rivera (stm32f3) * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios) { uint16_t i; uint32_t moder, pupd; /* * We want to set the config only for the pins mentioned in gpios, * but keeping the others, so read out the actual config first. */ moder = GPIO_MODER(gpioport); pupd = GPIO_PUPDR(gpioport); for (i = 0; i < 16; i++) { if (!((1 << i) & gpios)) { continue; } moder &= ~GPIO_MODE_MASK(i); moder |= GPIO_MODE(i, mode); pupd &= ~GPIO_PUPD_MASK(i); pupd |= GPIO_PUPD(i, pull_up_down); } /* Set mode and pull up/down control registers. */ GPIO_MODER(gpioport) = moder; GPIO_PUPDR(gpioport) = pupd; } void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios) { uint16_t i; uint32_t ospeedr; if (otype == 0x1) { GPIO_OTYPER(gpioport) |= gpios; } else { GPIO_OTYPER(gpioport) &= ~gpios; } ospeedr = GPIO_OSPEEDR(gpioport); for (i = 0; i < 16; i++) { if (!((1 << i) & gpios)) { continue; } ospeedr &= ~GPIO_OSPEED_MASK(i); ospeedr |= GPIO_OSPEED(i, speed); } GPIO_OSPEEDR(gpioport) = ospeedr; } void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios) { uint16_t i; uint32_t afrl, afrh; afrl = GPIO_AFRL(gpioport); afrh = GPIO_AFRH(gpioport); for (i = 0; i < 8; i++) { if (!((1 << i) & gpios)) { continue; } afrl &= ~GPIO_AFR_MASK(i); afrl |= GPIO_AFR(i, alt_func_num); } for (i = 8; i < 16; i++) { if (!((1 << i) & gpios)) { continue; } afrl &= ~GPIO_AFR_MASK(i - 8); afrh |= GPIO_AFR(i - 8, alt_func_num); } GPIO_AFRL(gpioport) = afrl; GPIO_AFRH(gpioport) = afrh; } void gpio_set(uint32_t gpioport, uint16_t gpios) { GPIO_BSRR(gpioport) = gpios; } void gpio_clear(uint32_t gpioport, uint16_t gpios) { GPIO_BSRR(gpioport) = gpios << 16; } uint16_t gpio_get(uint32_t gpioport, uint16_t gpios) { return gpio_port_read(gpioport) & gpios; } void gpio_toggle(uint32_t gpioport, uint16_t gpios) { GPIO_ODR(gpioport) ^= gpios; } uint16_t gpio_port_read(uint32_t gpioport) { return (uint16_t)GPIO_IDR(gpioport); } void gpio_port_write(uint32_t gpioport, uint16_t data) { GPIO_ODR(gpioport) = data; } void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios) { uint32_t reg32; /* Special "Lock Key Writing Sequence", see datasheet. */ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ /* * Tell the compiler the variable is actually used. * It will get optimized out anyways. */ reg32 = reg32; /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/i2c.c000066400000000000000000000274761435536612600203600ustar00rootroot00000000000000/** @defgroup i2c_file I2C * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx I2C * * @version 1.0.0 * * @date 15 October 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief I2C Reset. * * The I2C peripheral and all its associated configuration registers are placed * in the reset condition. The reset is effected via the RCC peripheral reset * system. * * @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. */ void i2c_reset(uint32_t i2c) { switch (i2c) { case I2C1: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST); break; case I2C2: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST); break; } } /*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Enable. * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_peripheral_enable(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_PE; } /*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Disable. * * This must not be reset while in Master mode until a communication has * finished. In Slave mode, the peripheral is disabled only after communication * has ended. * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_peripheral_disable(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_PE; } /*---------------------------------------------------------------------------*/ /** @brief I2C Send Start Condition. * * If in Master mode this will cause a restart condition to occur at the end of * the current transmission. If in Slave mode, this will initiate a start * condition when the current bus activity is completed. * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_send_start(uint32_t i2c) { I2C_CR2(i2c) |= I2C_CR2_START; } /*---------------------------------------------------------------------------*/ /** @brief I2C Send Stop Condition. * * After the current byte transfer this will initiate a stop condition if in * Master mode, or simply release the bus if in Slave mode. * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_send_stop(uint32_t i2c) { I2C_CR2(i2c) |= I2C_CR2_STOP; } /*---------------------------------------------------------------------------*/ /** @brief I2C Clear Stop Flag. * * Clear the "Send Stop" flag in the I2C config register * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_clear_stop(uint32_t i2c) { I2C_ICR(i2c) |= I2C_ICR_STOPCF; } /*---------------------------------------------------------------------------*/ /** @brief I2C Set the 7 bit Slave Address for the Peripheral. * * This sets an address for Slave mode operation, in 7 bit form. * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] slave Unsigned int8. Slave address 0...127. */ void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave) { I2C_OAR1(i2c) = (uint16_t)(slave << 1); I2C_OAR1(i2c) &= ~I2C_OAR1_OA1MODE; I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ } /*---------------------------------------------------------------------------*/ /** @brief I2C Set the 10 bit Slave Address for the Peripheral. * * This sets an address for Slave mode operation, in 10 bit form. * * @todo add "I2C_OAR1(i2c) |= (1 << 14);" as above * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] slave Unsigned int16. Slave address 0...1023. */ void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave) { I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_OA1MODE | slave); } /*---------------------------------------------------------------------------*/ /** @brief I2C Send Data. * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] data Unsigned int8. Byte to send. */ void i2c_send_data(uint32_t i2c, uint8_t data) { I2C_TXDR(i2c) = data; } /*---------------------------------------------------------------------------*/ /** @brief I2C Get Data. * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ uint8_t i2c_get_data(uint32_t i2c) { return I2C_RXDR(i2c) & 0xff; } void i2c_enable_analog_filter(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF; } void i2c_disable_analog_filter(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_ANFOFF; } void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting) { I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting; } /* t_presc= (presc+1)*t_i2cclk */ void i2c_set_prescaler(uint32_t i2c, uint8_t presc) { I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) | (presc << I2C_TIMINGR_PRESC_SHIFT); } void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time) { I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) | (s_time << I2C_TIMINGR_SCLDEL_SHIFT); } void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time) { I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) | (h_time << I2C_TIMINGR_SDADEL_SHIFT); } void i2c_set_scl_high_period(uint32_t i2c, uint8_t period) { I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) | (period << I2C_TIMINGR_SCLH_SHIFT); } void i2c_set_scl_low_period(uint32_t i2c, uint8_t period) { I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) | (period << I2C_TIMINGR_SCLL_SHIFT); } void i2c_enable_stretching(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH; } void i2c_disable_stretching(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH; } void i2c_100khz_i2cclk8mhz(uint32_t i2c) { i2c_set_prescaler(i2c, 1); i2c_set_scl_low_period(i2c, 0x13); i2c_set_scl_high_period(i2c, 0xF); i2c_set_data_hold_time(i2c, 0x2); i2c_set_data_setup_time(i2c, 0x4); } void i2c_set_7bit_addr_mode(uint32_t i2c) { I2C_CR2(i2c) &= ~I2C_CR2_ADD10; } void i2c_set_10bit_addr_mode(uint32_t i2c) { I2C_CR2(i2c) |= I2C_CR2_ADD10; } void i2c_set_7bit_address(uint32_t i2c, uint8_t addr) { I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) | ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT); } void i2c_set_10bit_address(uint32_t i2c, uint16_t addr) { I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) | ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT); } void i2c_set_write_transfer_dir(uint32_t i2c) { I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN; } void i2c_set_read_transfer_dir(uint32_t i2c) { I2C_CR2(i2c) |= I2C_CR2_RD_WRN; } void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes) { I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) | (n_bytes << I2C_CR2_NBYTES_SHIFT); } uint8_t i2c_is_start(uint32_t i2c) { if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) { return 1; } return 0; } void i2c_enable_autoend(uint32_t i2c) { I2C_CR2(i2c) |= I2C_CR2_AUTOEND; } void i2c_disable_autoend(uint32_t i2c) { I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND; } uint8_t i2c_nack(uint32_t i2c) { if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) { return 1; } return 0; } uint8_t i2c_busy(uint32_t i2c) { if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) { return 1; } return 0; } uint8_t i2c_transmit_int_status(uint32_t i2c) { if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) { return 1; } return 0; } uint8_t i2c_transfer_complete(uint32_t i2c) { if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) { return 1; } return 0; } uint8_t i2c_received_data(uint32_t i2c) { if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) { return 1; } return 0; } /*---------------------------------------------------------------------------*/ /** @brief I2C Enable Interrupt * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] interrupt Unsigned int32. Interrupt to enable. */ void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt) { I2C_CR1(i2c) |= interrupt; } /*---------------------------------------------------------------------------*/ /** @brief I2C Disable Interrupt * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] interrupt Unsigned int32. Interrupt to disable. */ void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt) { I2C_CR1(i2c) &= ~interrupt; } /*---------------------------------------------------------------------------*/ /** @brief I2C Enable reception DMA * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_enable_rxdma(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_RXDMAEN; } /*---------------------------------------------------------------------------*/ /** @brief I2C Disable reception DMA * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_disable_rxdma(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN; } /*---------------------------------------------------------------------------*/ /** @brief I2C Enable transmission DMA * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_enable_txdma(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_TXDMAEN; } /*---------------------------------------------------------------------------*/ /** @brief I2C Disable transmission DMA * * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ void i2c_disable_txdma(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN; } void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data) { int wait; int i; while (i2c_busy(i2c) == 1); while (i2c_is_start(i2c) == 1); /*Setting transfer properties*/ i2c_set_bytes_to_transfer(i2c, size + 1); i2c_set_7bit_address(i2c, (i2c_addr & 0x7F)); i2c_set_write_transfer_dir(i2c); i2c_enable_autoend(i2c); /*start transfer*/ i2c_send_start(i2c); wait = true; while (wait) { if (i2c_transmit_int_status(i2c)) { wait = false; } while (i2c_nack(i2c)); } i2c_send_data(i2c, reg); for (i = 0; i < size; i++) { wait = true; while (wait) { if (i2c_transmit_int_status(i2c)) { wait = false; } while (i2c_nack(i2c)); } i2c_send_data(i2c, data[i]); } } void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data) { int wait; int i; while (i2c_busy(i2c) == 1); while (i2c_is_start(i2c) == 1); /*Setting transfer properties*/ i2c_set_bytes_to_transfer(i2c, 1); i2c_set_7bit_address(i2c, i2c_addr); i2c_set_write_transfer_dir(i2c); i2c_disable_autoend(i2c); /*start transfer*/ i2c_send_start(i2c); wait = true; while (wait) { if (i2c_transmit_int_status(i2c)) { wait = false; } while (i2c_nack(i2c)); /* Some error */ } i2c_send_data(i2c, reg); while (i2c_is_start(i2c) == 1); /*Setting transfer properties*/ i2c_set_bytes_to_transfer(i2c, size); i2c_set_7bit_address(i2c, i2c_addr); i2c_set_read_transfer_dir(i2c); i2c_enable_autoend(i2c); /*start transfer*/ i2c_send_start(i2c); for (i = 0; i < size; i++) { while (i2c_received_data(i2c) == 0); data[i] = i2c_get_data(i2c); } } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/iwdg.c000066400000000000000000000020111435536612600206070ustar00rootroot00000000000000/** @defgroup iwdg_file IWDG * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx Independent Watchdog Timer * * @version 1.0.0 * * @date 18 August 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/libopencm3_stm32f3.ld000066400000000000000000000047631435536612600233660ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/pwr.c000066400000000000000000000017031435536612600204740ustar00rootroot00000000000000/** @defgroup pwr_file PWR * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx Power control * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/rcc.c000066400000000000000000000230461435536612600204370ustar00rootroot00000000000000/** @defgroup rcc_file RCC * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx Reset and Clock Control * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2010 Thomas Otto * Modified by 2013 Fernando Cortes (stm32f3) * Modified by 2013 Guillermo Rivera (stm32f3) * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include #include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ uint32_t rcc_ppre1_frequency = 8000000; uint32_t rcc_ppre2_frequency = 8000000; const clock_scale_t hsi_8mhz[CLOCK_END] = { { /* 44MHz */ .pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X11, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .power_save = 1, .flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS, .apb1_frequency = 22000000, .apb2_frequency = 44000000, }, { /* 48MHz */ .pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X12, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .power_save = 1, .flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS, .apb1_frequency = 24000000, .apb2_frequency = 48000000, }, { /* 64MHz */ .pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X16, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .power_save = 1, .flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS, .apb1_frequency = 32000000, .apb2_frequency = 64000000, } }; void rcc_osc_ready_int_clear(enum osc osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; } } void rcc_osc_ready_int_enable(enum osc osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; } } void rcc_osc_ready_int_disable(enum osc osc) { switch (osc) { case PLL: RCC_CIR &= ~RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR &= ~RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR &= ~RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR &= ~RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR &= ~RCC_CIR_LSIRDYIE; break; } } int rcc_osc_ready_int_flag(enum osc osc) { switch (osc) { case PLL: return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; case HSE: return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; case HSI: return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; case LSE: return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; case LSI: return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; } cm3_assert_not_reached(); } void rcc_css_int_clear(void) { RCC_CIR |= RCC_CIR_CSSC; } int rcc_css_int_flag(void) { return ((RCC_CIR & RCC_CIR_CSSF) != 0); } void rcc_wait_for_osc_ready(enum osc osc) { switch (osc) { case PLL: while ((RCC_CR & RCC_CR_PLLRDY) == 0); break; case HSE: while ((RCC_CR & RCC_CR_HSERDY) == 0); break; case HSI: while ((RCC_CR & RCC_CR_HSIRDY) == 0); break; case LSE: while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); break; case LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); break; } } void rcc_wait_for_osc_not_ready(enum osc osc) { switch (osc) { case PLL: while ((RCC_CR & RCC_CR_PLLRDY) != 0); break; case HSE: while ((RCC_CR & RCC_CR_HSERDY) != 0); break; case HSI: while ((RCC_CR & RCC_CR_HSIRDY) != 0); break; case LSE: while ((RCC_BDCR & RCC_BDCR_LSERDY) != 0); break; case LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) != 0); break; } } void rcc_wait_for_sysclk_status(enum osc osc) { switch (osc) { case PLL: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); break; case HSE: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); break; case HSI: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); break; default: /* Shouldn't be reached. */ break; } } void rcc_osc_on(enum osc osc) { switch (osc) { case PLL: RCC_CR |= RCC_CR_PLLON; break; case HSE: RCC_CR |= RCC_CR_HSEON; break; case HSI: RCC_CR |= RCC_CR_HSION; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEON; break; case LSI: RCC_CSR |= RCC_CSR_LSION; break; } } void rcc_osc_off(enum osc osc) { switch (osc) { case PLL: RCC_CR &= ~RCC_CR_PLLON; break; case HSE: RCC_CR &= ~RCC_CR_HSEON; break; case HSI: RCC_CR &= ~RCC_CR_HSION; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEON; break; case LSI: RCC_CSR &= ~RCC_CSR_LSION; break; } } void rcc_css_enable(void) { RCC_CR |= RCC_CR_CSSON; } void rcc_css_disable(void) { RCC_CR &= ~RCC_CR_CSSON; } void rcc_osc_bypass_enable(enum osc osc) { switch (osc) { case HSE: RCC_CR |= RCC_CR_HSEBYP; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_osc_bypass_disable(enum osc osc) { switch (osc) { case HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en) { *reg |= en; } void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en) { *reg &= ~en; } void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset) { *reg |= reset; } void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset) { *reg &= ~clear_reset; } void rcc_set_sysclk_source(uint32_t clk) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 1) | (1 << 0)); RCC_CFGR = (reg32 | clk); } void rcc_set_pll_source(uint32_t pllsrc) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~RCC_CFGR_PLLSRC; RCC_CFGR = (reg32 | (pllsrc << 16)); } void rcc_set_ppre2(uint32_t ppre2) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15)); RCC_CFGR = (reg32 | (ppre2 << 11)); } void rcc_set_ppre1(uint32_t ppre1) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12)); RCC_CFGR = (reg32 | (ppre1 << 8)); } void rcc_set_hpre(uint32_t hpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); RCC_CFGR = (reg32 | (hpre << 4)); } void rcc_set_main_pll_hsi(uint32_t pll) { RCC_CFGR = (~RCC_CFGR_PLLMUL_MASK & RCC_CFGR) | (pll << RCC_CFGR_PLLMUL_SHIFT); } uint32_t rcc_get_system_clock_source(void) { /* Return the clock source which is used as system clock. */ return (RCC_CFGR & 0x000c) >> 2; } void rcc_clock_setup_hsi(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */ rcc_wait_for_sysclk_status(HSI); rcc_osc_off(PLL); rcc_wait_for_osc_not_ready(PLL); rcc_set_pll_source(clock->pllsrc); rcc_set_main_pll_hsi(clock->pll); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre2(clock->ppre2); rcc_set_ppre1(clock->ppre1); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */ /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; } void rcc_backupdomain_reset(void) { /* Set the backup domain software reset. */ RCC_BDCR |= RCC_BDCR_BDRST; /* Clear the backup domain software reset. */ RCC_BDCR &= ~RCC_BDCR_BDRST; } void rcc_set_i2c_clock_hsi(uint32_t i2c) { if (i2c == I2C1) { RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW; } if (i2c == I2C2) { RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW; } } void rcc_set_i2c_clock_sysclk(uint32_t i2c) { if (i2c == I2C1) { RCC_CFGR3 |= RCC_CFGR3_I2C1SW; } if (i2c == I2C2) { RCC_CFGR3 |= RCC_CFGR3_I2C2SW; } } uint32_t rcc_get_i2c_clocks(void) { return RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW); } void rcc_usb_prescale_1_5(void) { RCC_CFGR &= ~RCC_CFGR_USBPRES; } void rcc_usb_prescale_1(void) { RCC_CFGR |= RCC_CFGR_USBPRES; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/spi.c000066400000000000000000000035411435536612600204610ustar00rootroot00000000000000/** @defgroup spi_file SPI * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx Serial Peripheral Interface * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include void spi_send8(uint32_t spi, uint8_t data) { /* Wait for transfer finished. */ while (!(SPI_SR(spi) & SPI_SR_TXE)); /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR8(spi) = data; } uint8_t spi_read8(uint32_t spi) { /* Wait for transfer finished. */ while (!(SPI_SR(spi) & SPI_SR_RXNE)); /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ return SPI_DR8(spi); } void spi_set_data_size(uint32_t spi, uint16_t data_s) { SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | (data_s & SPI_CR2_DS_MASK); } void spi_fifo_reception_threshold_8bit(uint32_t spi) { SPI_CR2(spi) |= SPI_CR2_FRXTH; } void spi_fifo_reception_threshold_16bit(uint32_t spi) { SPI_CR2(spi) &= ~SPI_CR2_FRXTH; } void spi_i2s_mode_spi_mode(uint32_t spi) { SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/timer.c000066400000000000000000000017021435536612600210030ustar00rootroot00000000000000/** @defgroup timer_file TIMER * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx Timers * * @version 1.0.0 * * @date 11 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/usart.c000066400000000000000000000104671435536612600210310ustar00rootroot00000000000000/** @defgroup usart_file USART * * @ingroup STM32F3xx * * @brief libopencm3 STM32F3xx USART * * @version 1.0.0 * * @date 30 August 2012 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include /*---------------------------------------------------------------------------*/ /** @brief USART Send a Data Word. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] data unsigned 16 bit. */ void usart_send(uint32_t usart, uint16_t data) { /* Send data. */ USART_TDR(usart) = (data & USART_TDR_MASK); } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word. * * If parity is enabled the MSB (bit 7 or 8 depending on the word length) is * the parity bit. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @returns unsigned 16 bit data word. */ uint16_t usart_recv(uint32_t usart) { /* Receive data. */ return USART_RDR(usart) & USART_RDR_MASK; } /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Transmit Data Buffer Empty * * Blocks until the transmit data buffer becomes empty and is ready to accept * the next data word. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_wait_send_ready(uint32_t usart) { /* Wait until the data has been transferred into the shift register. */ while ((USART_ISR(usart) & USART_ISR_TXE) == 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Received Data Available * * Blocks until the receive data buffer holds a valid received data word. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base */ void usart_wait_recv_ready(uint32_t usart) { /* Wait until the data is ready to be received. */ while ((USART_ISR(usart) & USART_ISR_RXNE) == 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Read a Status Flag. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. * @returns boolean: flag set. */ bool usart_get_flag(uint32_t usart, uint32_t flag) { return ((USART_ISR(usart) & flag) != 0); } /*---------------------------------------------------------------------------*/ /** @brief USART Return Interrupt Source. * * Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was * set and the interrupt was enabled. If the specified flag is not an interrupt * flag, the function returns false. * * @todo These are the most important interrupts likely to be used. Others * relating to LIN break, and error conditions in multibuffer communication, * need to be added for completeness. * * @param[in] usart unsigned 32 bit. USART block register address base @ref * usart_reg_base * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. * @returns boolean: flag and interrupt enable both set. */ bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) { uint32_t flag_set = (USART_ISR(usart) & flag); /* IDLE, RXNE, TC, TXE interrupts */ if ((flag >= USART_ISR_IDLE) && (flag <= USART_ISR_TXE)) { return ((flag_set & USART_CR1(usart)) != 0); /* Overrun error */ } else if (flag == USART_ISR_ORE) { return flag_set && (USART_CR3(usart) & USART_CR3_CTSIE); } return false; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f3/vector_chipset.c000066400000000000000000000020061435536612600227020ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include static void pre_main(void) { /* Enable access to Floating-Point coprocessor. */ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/000077500000000000000000000000001435536612600175205ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/Makefile000066400000000000000000000040451435536612600211630ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## Copyright (C) 2013 Alexandru Gagniuc ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_stm32f4 FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m4 -mthumb $(FP_FLAGS) \ -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F4 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = adc.o can.o gpio.o pwr.o rcc.o rtc.o crypto.o OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ gpio_common_all.o gpio_common_f0234.o i2c_common_all.o \ iwdg_common_all.o pwr_common_all.o rtc_common_l1f024.o \ spi_common_all.o spi_common_f124.o timer_common_all.o \ timer_common_f234.o timer_common_f24.o usart_common_all.o \ usart_common_f124.o flash_common_f234.o flash_common_f24.o \ hash_common_f24.o crypto_common_f24.o exti_common_all.o OBJS += usb.o usb_standard.o usb_control.o usb_fx07_common.o \ usb_f107.o usb_f207.o VPATH += ../../usb:../:../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/adc.c000066400000000000000000001004171435536612600204160ustar00rootroot00000000000000/** @defgroup STM32F4xx_adc_file ADC @ingroup STM32F4xx @brief libopencm3 STM32F4xx Analog to Digital Converters @author @htmlonly © @endhtmlonly 2012 Ken Sarkies @date 30 August 2012 This library supports the A/D Converter Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics. Devices can have up to three A/D converters each with their own set of registers. However all the A/D converters share a common clock which is prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. Each A/D converter has up to 19 channels: @li On ADC1 the analog channels 16 is internally connected to the temperature sensor, channel 17 to VREFINT, and channel 18 to VBATT. @li On ADC2 and ADC3 the analog channels 16 - 18 are not used. The conversions can occur as a one-off conversion whereby the process stops once conversion is complete. The conversions can also be continuous wherein a new conversion starts immediately the previous conversion has ended. Conversion can occur as a single channel conversion or a scan of a group of channels in either continuous or one-off mode. If more than one channel is converted in a scan group, DMA must be used to transfer the data as there is only one result register available. An interrupt can be set to occur at the end of conversion, which occurs after all channels have been scanned. A discontinuous mode allows a subgroup of group of a channels to be converted in bursts of a given length. Injected conversions allow a second group of channels to be converted separately from the regular group. An interrupt can be set to occur at the end of conversion, which occurs after all channels have been scanned. @section adc_f4_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock and ADC, reset ADC and set the prescaler divider. Set multiple mode to independent. @code gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2); adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); uint8_t channels[] = ADC_CHANNEL0; adc_set_regular_sequence(ADC1, 1, channels); adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); adc_power_on(ADC1); adc_start_conversion_regular(ADC1); while (! adc_eoc(ADC1)); reg16 = adc_read_regular(ADC1); @endcode LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief ADC Off Turn off the ADC to reduce power consumption to a few microamps. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_off(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_ADON; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_analog_watchdog_regular(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_AWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Regular Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_analog_watchdog_regular(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_AWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Injected Conversions The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_analog_watchdog_injected(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_JAWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_analog_watchdog_injected(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the defined regular channel group. The subgroup is defined by the number of consecutive channels to be converted. After a subgroup has been converted the next trigger will start conversion of the immediately following subgroup of the same length or until the whole group has all been converted. When the the whole group has been converted, the next trigger will restart conversion of the subgroup at the beginning of the whole group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum */ void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length) { if ((length-1) > 7) { return; } ADC_CR1(adc) |= ADC_CR1_DISCEN; ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_discontinuous_mode_regular(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_DISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Injected Conversions In this mode the ADC converts sequentially one channel of the defined group of injected channels, cycling back to the first channel in the group once the entire group has been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_discontinuous_mode_injected(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_JDISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_discontinuous_mode_injected(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Automatic Injected Conversions The ADC converts a defined injected group of channels immediately after the regular channels have been converted. The external trigger on the injected channels is disabled as required. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_automatic_injected_group_conversion(uint32_t adc) { adc_disable_external_trigger_injected(adc); ADC_CR1(adc) |= ADC_CR1_JAUTO; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Automatic Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_automatic_injected_group_conversion(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JAUTO; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. @ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. If both are enabled, the same channel number is monitored. @ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel */ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel) { uint32_t reg32; reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */ if (channel < 18) { reg32 |= channel; } ADC_CR1(adc) = reg32; ADC_CR1(adc) |= ADC_CR1_AWDSGL; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Scan Mode In this mode a conversion consists of a scan of the predefined set of channels, regular and injected, each channel conversion immediately following the previous one. It can use single, continuous or discontinuous mode. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_scan_mode(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_SCAN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Scan Mode @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_scan_mode(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_SCAN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Injected End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_eoc_interrupt_injected(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_JEOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Injected End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_eoc_interrupt_injected(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_awd_interrupt(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_AWDIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_awd_interrupt(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_AWDIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_eoc_interrupt(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_EOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_eoc_interrupt(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_EOCIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels This starts conversion on a set of defined regular channels. It is cleared by hardware once conversion starts. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_start_conversion_regular(uint32_t adc) { /* Start conversion on regular channels. */ ADC_CR2(adc) |= ADC_CR2_SWSTART; /* Wait until the ADC starts the conversion. */ while (ADC_CR2(adc) & ADC_CR2_SWSTART); } /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Injected Channels This starts conversion on a set of defined injected channels. It is cleared by hardware once conversion starts. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_start_conversion_injected(uint32_t adc) { /* Start conversion on injected channels. */ ADC_CR2(adc) |= ADC_CR2_JSWSTART; /* Wait until the ADC starts the conversion. */ while (ADC_CR2(adc) & ADC_CR2_JSWSTART); } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_set_left_aligned(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_set_right_aligned(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_ALIGN; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_dma(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_DMA; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_dma(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_DMA; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode In this mode the ADC starts a new conversion of a single channel or a channel group immediately following completion of the previous channel group conversion. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_set_continuous_conversion_mode(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode In this mode the ADC performs a conversion of one channel or a channel group and stops. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_set_single_conversion_mode(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_CONT; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) { uint32_t reg32; if (channel < 10) { reg32 = ADC_SMPR2(adc); reg32 &= ~(0x7 << (channel * 3)); reg32 |= (time << (channel * 3)); ADC_SMPR2(adc) = reg32; } else { reg32 = ADC_SMPR1(adc); reg32 &= ~(0x7 << ((channel - 10) * 3)); reg32 |= (time << ((channel - 10) * 3)); ADC_SMPR1(adc) = reg32; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for all channels. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) { uint8_t i; uint32_t reg32 = 0; for (i = 0; i <= 9; i++) { reg32 |= (time << (i * 3)); } ADC_SMPR2(adc) = reg32; for (i = 10; i <= 17; i++) { reg32 |= (time << ((i - 10) * 3)); } ADC_SMPR1(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] threshold Unsigned int8. Upper threshold value */ void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold) { uint32_t reg32 = 0; reg32 = (uint32_t)threshold; reg32 &= ~0xfffff000; /* Clear all bits above 11. */ ADC_HTR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] threshold Unsigned int8. Lower threshold value */ void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold) { uint32_t reg32 = 0; reg32 = (uint32_t)threshold; reg32 &= ~0xfffff000; /* Clear all bits above 11. */ ADC_LTR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence Define a sequence of channels to be converted as a regular group with a length from 1 to 16 channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] length Unsigned int8. Number of channels in the group. @param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18. */ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0; uint8_t i = 0; /* Maximum sequence length is 16 channels. */ if (length > 16) { return; } for (i = 1; i <= length; i++) { if (i <= 6) { reg32_3 |= (channel[i - 1] << ((i - 1) * 5)); } if ((i > 6) & (i <= 12)) { reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5)); } if ((i > 12) & (i <= 16)) { reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5)); } } reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB); ADC_SQR1(adc) = reg32_1; ADC_SQR2(adc) = reg32_2; ADC_SQR3(adc) = reg32_3; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set an Injected Channel Conversion Sequence Defines a sequence of channels to be converted as an injected group with a length from 1 to 4 channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] length Unsigned int8. Number of channels in the group. @param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18 */ void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { uint32_t reg32 = 0; uint8_t i = 0; /* Maximum sequence length is 4 channels. */ if ((length-1) > 3) { return; } for (i = 1; i <= length; i++) { reg32 |= (channel[4 - i] << ((4 - i) * 5)); } reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag This flag is set after all channels of a regular or injected group have been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @returns bool. End of conversion flag. */ bool adc_eoc(uint32_t adc) { return (ADC_SR(adc) & ADC_SR_EOC) != 0; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag for Injected Conversion This flag is set after all channels of an injected group have been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @returns bool. End of conversion flag. */ bool adc_eoc_injected(uint32_t adc) { return (ADC_SR(adc) & ADC_SR_JEOC) != 0; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register The result read back is 12 bits, right or left aligned within the first 16 bits. For ADC1 only, the higher 16 bits will hold the result from ADC2 if an appropriate dual mode has been set @see adc_set_dual_mode. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @returns Unsigned int32 conversion result. */ uint32_t adc_read_regular(uint32_t adc) { return ADC_DR(adc); } /*---------------------------------------------------------------------------*/ /** @brief ADC Read from an Injected Conversion Result Register The result read back from the selected injected result register (one of four) is 12 bits, right or left aligned within the first 16 bits. The result can have a negative value if the injected channel offset has been set @see adc_set_injected_offset. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] reg Unsigned int8. Register number (1 ... 4). @returns Unsigned int32 conversion result. */ uint32_t adc_read_injected(uint32_t adc, uint8_t reg) { switch (reg) { case 1: return ADC_JDR1(adc); case 2: return ADC_JDR2(adc); case 3: return ADC_JDR3(adc); case 4: return ADC_JDR4(adc); } return 0; } /*----------------------------------------------------------------------------*/ /** @brief ADC Set the Injected Channel Data Offset This value is subtracted from the injected channel results after conversion is complete, and can result in negative results. A separate value can be specified for each injected data register. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] reg Unsigned int8. Register number (1 ... 4). @param[in] offset Unsigned int32. */ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) { switch (reg) { case 1: ADC_JOFR1(adc) = offset; break; case 2: ADC_JOFR2(adc) = offset; break; case 3: ADC_JOFR3(adc) = offset; break; case 4: ADC_JOFR4(adc) = offset; break; } } /*---------------------------------------------------------------------------*/ /** @brief ADC Power On If the ADC is in power-down mode then it is powered up. The application needs to wait a time of about 3 microseconds for stabilization before using the ADC. If the ADC is already on this function call will have no effect. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_power_on(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_ADON; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref adc_ccr_adcpre */ void adc_set_clk_prescale(uint32_t prescale) { uint32_t reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale); ADC_CCR = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Dual/Triple Mode The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave arrangement. This setting is applied to ADC1 only. The various modes possible are described in the reference manual. @param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode */ void adc_set_multi_mode(uint32_t mode) { ADC_CCR |= mode; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels This enables an external trigger for set of defined regular channels, and sets the polarity of the trigger event: rising or falling edge or both. Note that if the trigger polarity is zero, triggering is disabled. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular @param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_regular */ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity) { uint32_t reg32 = ADC_CR2(adc); reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); reg32 |= (trigger | polarity); ADC_CR2(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_external_trigger_regular(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Injected Channels This enables an external trigger for set of defined injected channels, and sets the polarity of the trigger event: rising or falling edge or both. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected @param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_injected */ void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity) { uint32_t reg32 = ADC_CR2(adc); reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); reg32 |= (trigger | polarity); ADC_CR2(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Injected Channels @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_external_trigger_injected(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set Resolution ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding reduction in conversion time (resolution + 3 ADC clock cycles). @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] resolution Unsigned int32. Resolution value @ref adc_cr1_res */ void adc_set_resolution(uint32_t adc, uint32_t resolution) { uint32_t reg32 = ADC_CR1(adc); reg32 &= ~ADC_CR1_RES_MASK; reg32 |= resolution; ADC_CR1(adc) = reg32; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable the Overrun Interrupt The overrun interrupt is generated when data is not read from a result register before the next conversion is written. If DMA is enabled, all transfers are terminated and any conversion sequence is aborted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_overrun_interrupt(uint32_t adc) { ADC_CR1(adc) |= ADC_CR1_OVRIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable the Overrun Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_overrun_interrupt(uint32_t adc) { ADC_CR1(adc) &= ~ADC_CR1_OVRIE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Overrun Flag The overrun flag is set when data is not read from a result register before the next conversion is written. If DMA is enabled, all transfers are terminated and any conversion sequence is aborted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @returns Unsigned int32 conversion result. */ bool adc_get_overrun_flag(uint32_t adc) { return ADC_SR(adc) & ADC_SR_OVR; } /*---------------------------------------------------------------------------*/ /** @brief ADC Clear Overrun Flags The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. The flag must be cleared and the DMA stream and ADC reinitialised to resume conversions (see the reference manual). @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @returns Unsigned int32 conversion result. */ void adc_clear_overrun_flag(uint32_t adc) { /* need to write zero to clear this */ ADC_SR(adc) &= ~ADC_SR_OVR; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an EOC for Each Conversion The EOC is set after each conversion in a sequence rather than at the end of the sequence. Overrun detection is enabled only if DMA is enabled. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_eoc_after_each(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_EOCS; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable the EOC for Each Conversion The EOC is set at the end of each sequence rather than after each conversion in the sequence. Overrun detection is enabled always. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_eoc_after_group(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_EOCS; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Continue This must be set to allow DMA to continue to operate after the last conversion in the DMA sequence. This allows DMA to be used in continuous circular mode. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_set_dma_continue(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_DDS; } /*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Terminate This must be set to allow DMA to terminate after the last conversion in the DMA sequence. This can avoid overrun errors. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_set_dma_terminate(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_DDS; } /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Analog Watchdog Flag This flag is set when the converted voltage crosses the high or low thresholds. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @returns bool. AWD flag. */ bool adc_awd(uint32_t adc) { return ADC_SR(adc) & ADC_SR_AWD; } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor This enables both the sensor and the reference voltage measurements on channels 16 and 17. These are only available on ADC1 channel 16 and 17 respectively. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_enable_temperature_sensor() { ADC_CCR |= ADC_CCR_TSVREFE; } /*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor Disabling this will reduce power consumption from the sensor and the reference voltage measurements. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_disable_temperature_sensor() { ADC_CCR &= ~ADC_CCR_TSVREFE; } /*---------------------------------------------------------------------------*/ /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/crc.c000066400000000000000000000017261435536612600204410ustar00rootroot00000000000000/** @defgroup crc_file CRC @ingroup STM32F4xx @brief libopencm3 STM32F4xx CRC @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/crypto.c000066400000000000000000000031431435536612600212050ustar00rootroot00000000000000/** @defgroup crypto_file CRYPTO * * @ingroup STM32F4xx * * @brief libopencm3 STM32F4xx CRYPTO * * @version 1.0.0 * * @date 18 Jun 2013 * */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include /**@{*/ /*---------------------------------------------------------------------------*/ /** @brief Set the MAC algorithm */ void crypto_set_mac_algorithm(enum crypto_mode_mac mode) { crypto_set_algorithm((enum crypto_mode) mode); } /** * @brief Swap context * *@param[in] buf uint32_t Memory space for swap (16 items length) */ void crypto_context_swap(uint32_t *buf) { int i; /* Apply exact order of ? */ for (i = 0; i < 8; i++) { uint32_t save = *buf; *buf++ = CRYP_CSGCMCCMR(i); CRYP_CSGCMCCMR(i) = save; }; for (i = 0; i < 8; i++) { uint32_t save = *buf; *buf++ = CRYP_CSGCMR(i); CRYP_CSGCMCCMR(i) = save; }; } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/dac.c000066400000000000000000000017241435536612600204170ustar00rootroot00000000000000/** @defgroup dac_file DAC @ingroup STM32F4xx @brief libopencm3 STM32F4xx DAC @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/dma.c000066400000000000000000000017261435536612600204330ustar00rootroot00000000000000/** @defgroup dma_file DMA @ingroup STM32F4xx @brief libopencm3 STM32F4xx DMA @version 1.0.0 @date 30 November 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/gpio.c000066400000000000000000000016621435536612600206270ustar00rootroot00000000000000/** @defgroup gpio_file GPIO @ingroup STM32F4xx @brief libopencm3 STM32F4xx General Purpose I/O @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/i2c.c000066400000000000000000000017251435536612600203460ustar00rootroot00000000000000/** @defgroup i2c_file I2C @ingroup STM32F4xx @brief libopencm3 STM32F4xx I2C @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/iwdg.c000066400000000000000000000017571435536612600206300ustar00rootroot00000000000000/** @defgroup iwdg_file IWDG @ingroup STM32F4xx @brief libopencm3 STM32F4xx Independent Watchdog Timer @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/libopencm3_stm32f4.ld000066400000000000000000000047631435536612600233700ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/pwr.c000066400000000000000000000025121435536612600204740ustar00rootroot00000000000000/** @defgroup pwr-file PWR @ingroup STM32F4xx @brief libopencm3 STM32F4xx Power Control @version 1.0.0 @author @htmlonly © @endhtmlonly 2011 Stephen Caudle @date 4 March 2013 This library supports the power control system for the STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void pwr_set_vos_scale(vos_scale_t scale) { if (scale == SCALE1) { PWR_CR |= PWR_CR_VOS; } else if (scale == SCALE2) { PWR_CR &= PWR_CR_VOS; } } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/rcc.c000066400000000000000000000257771435536612600204550ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2010 Thomas Otto * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include #include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ uint32_t rcc_ppre1_frequency = 16000000; uint32_t rcc_ppre2_frequency = 16000000; const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 8, .plln = 96, .pllp = 2, .pllq = 2, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 12000000, .apb2_frequency = 24000000, }, { /* 120MHz */ .pllm = 8, .plln = 240, .pllp = 2, .pllq = 5, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 30000000, .apb2_frequency = 60000000, }, { /* 168MHz */ .pllm = 8, .plln = 336, .pllp = 2, .pllq = 7, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS, .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, }; const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 12, .plln = 96, .pllp = 2, .pllq = 2, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 12000000, .apb2_frequency = 24000000, }, { /* 120MHz */ .pllm = 12, .plln = 240, .pllp = 2, .pllq = 5, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 30000000, .apb2_frequency = 60000000, }, { /* 168MHz */ .pllm = 12, .plln = 336, .pllp = 2, .pllq = 7, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS, .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, }; const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 16, .plln = 96, .pllp = 2, .pllq = 2, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 12000000, .apb2_frequency = 24000000, }, { /* 120MHz */ .pllm = 16, .plln = 240, .pllp = 2, .pllq = 5, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 30000000, .apb2_frequency = 60000000, }, { /* 168MHz */ .pllm = 16, .plln = 336, .pllp = 2, .pllq = 7, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS, .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, }; void rcc_osc_ready_int_clear(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; } } void rcc_osc_ready_int_enable(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; } } void rcc_osc_ready_int_disable(osc_t osc) { switch (osc) { case PLL: RCC_CIR &= ~RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR &= ~RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR &= ~RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR &= ~RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR &= ~RCC_CIR_LSIRDYIE; break; } } int rcc_osc_ready_int_flag(osc_t osc) { switch (osc) { case PLL: return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; case HSE: return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; case HSI: return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; case LSE: return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; case LSI: return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; } cm3_assert_not_reached(); } void rcc_css_int_clear(void) { RCC_CIR |= RCC_CIR_CSSC; } int rcc_css_int_flag(void) { return ((RCC_CIR & RCC_CIR_CSSF) != 0); } void rcc_wait_for_osc_ready(osc_t osc) { switch (osc) { case PLL: while ((RCC_CR & RCC_CR_PLLRDY) == 0); break; case HSE: while ((RCC_CR & RCC_CR_HSERDY) == 0); break; case HSI: while ((RCC_CR & RCC_CR_HSIRDY) == 0); break; case LSE: while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); break; case LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); break; } } void rcc_wait_for_sysclk_status(osc_t osc) { switch (osc) { case PLL: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); break; case HSE: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); break; case HSI: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); break; default: /* Shouldn't be reached. */ break; } } void rcc_osc_on(osc_t osc) { switch (osc) { case PLL: RCC_CR |= RCC_CR_PLLON; break; case HSE: RCC_CR |= RCC_CR_HSEON; break; case HSI: RCC_CR |= RCC_CR_HSION; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEON; break; case LSI: RCC_CSR |= RCC_CSR_LSION; break; } } void rcc_osc_off(osc_t osc) { switch (osc) { case PLL: RCC_CR &= ~RCC_CR_PLLON; break; case HSE: RCC_CR &= ~RCC_CR_HSEON; break; case HSI: RCC_CR &= ~RCC_CR_HSION; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEON; break; case LSI: RCC_CSR &= ~RCC_CSR_LSION; break; } } void rcc_css_enable(void) { RCC_CR |= RCC_CR_CSSON; } void rcc_css_disable(void) { RCC_CR &= ~RCC_CR_CSSON; } void rcc_osc_bypass_enable(osc_t osc) { switch (osc) { case HSE: RCC_CR |= RCC_CR_HSEBYP; break; case LSE: RCC_BDCR |= RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_osc_bypass_disable(osc_t osc) { switch (osc) { case HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; case LSE: RCC_BDCR &= ~RCC_BDCR_LSEBYP; break; case PLL: case HSI: case LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en) { *reg |= en; } void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en) { *reg &= ~en; } void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset) { *reg |= reset; } void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset) { *reg &= ~clear_reset; } void rcc_set_sysclk_source(uint32_t clk) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 1) | (1 << 0)); RCC_CFGR = (reg32 | clk); } void rcc_set_pll_source(uint32_t pllsrc) { uint32_t reg32; reg32 = RCC_PLLCFGR; reg32 &= ~(1 << 22); RCC_PLLCFGR = (reg32 | (pllsrc << 22)); } void rcc_set_ppre2(uint32_t ppre2) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15)); RCC_CFGR = (reg32 | (ppre2 << 13)); } void rcc_set_ppre1(uint32_t ppre1) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12)); RCC_CFGR = (reg32 | (ppre1 << 10)); } void rcc_set_hpre(uint32_t hpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); RCC_CFGR = (reg32 | (hpre << 4)); } void rcc_set_rtcpre(uint32_t rtcpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); RCC_CFGR = (reg32 | (rtcpre << 16)); } void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq) { RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | (plln << RCC_PLLCFGR_PLLN_SHIFT) | (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | (pllq << RCC_PLLCFGR_PLLQ_SHIFT); } void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq) { RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | (plln << RCC_PLLCFGR_PLLN_SHIFT) | (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | RCC_PLLCFGR_PLLSRC | (pllq << RCC_PLLCFGR_PLLQ_SHIFT); } uint32_t rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ return (RCC_CFGR & 0x000c) >> 2; } void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* Enable external high-speed oscillator 8MHz. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); /* Enable/disable high performance mode */ if (!clock->power_save) { pwr_set_vos_scale(SCALE1); } else { pwr_set_vos_scale(SCALE2); } /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_set_main_pll_hse(clock->pllm, clock->plln, clock->pllp, clock->pllq); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; /* Disable internal high-speed oscillator. */ rcc_osc_off(HSI); } void rcc_backupdomain_reset(void) { /* Set the backup domain software reset. */ RCC_BDCR |= RCC_BDCR_BDRST; /* Clear the backup domain software reset. */ RCC_BDCR &= ~RCC_BDCR_BDRST; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/rtc.c000066400000000000000000000056531435536612600204650ustar00rootroot00000000000000/** @defgroup rtc_file RTC * * @ingroup STM32F4xx * * @brief libopencm3 STM32F4xx RTC * * @version 1.0.0 * * @date 4 March 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include #include /*---------------------------------------------------------------------------*/ /** @brief Enable the wakeup timer @warning You must unlock the registers before using this function */ void rtc_enable_wakeup_timer(void) { RTC_CR |= RTC_CR_WUTE | (RTC_CR_OSEL_WAKEUP << RTC_CR_OSEL_SHIFT); rtc_enable_wakeup_timer_interrupt(); } /*---------------------------------------------------------------------------*/ /** @brief Disable the wakeup timer @warning You must unlock the registers before using this function */ void rtc_disable_wakeup_timer(void) { RTC_CR &= ~RTC_CR_WUTE; rtc_disable_wakeup_timer_interrupt(); } /*---------------------------------------------------------------------------*/ /** @brief Enable the wakeup timer interrupt @warning You must unlock the registers before using this function */ void rtc_enable_wakeup_timer_interrupt(void) { /* FTFM: * To enable the RTC Wakeup interrupt, the following sequence is * required: * 1. Configure and enable the EXTI Line 22 in interrupt mode and * select the rising edge sensitivity. */ exti_enable_request(EXTI22); exti_set_trigger(EXTI22, EXTI_TRIGGER_RISING); /* 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC. */ nvic_enable_irq(NVIC_RTC_WKUP_IRQ); nvic_set_priority(NVIC_RTC_WKUP_IRQ, 1); /* 3. Configure the RTC to generate the RTC wakeup timer event. */ RTC_CR |= RTC_CR_WUTIE; /* Enable the interrupt */ } /*---------------------------------------------------------------------------*/ /** @brief Disable the wakeup timer interrupt @warning You must unlock the registers before using this function */ void rtc_disable_wakeup_timer_interrupt(void) { /* 1. Disable EXTI Line 22 */ exti_disable_request(EXTI22); /* 2. Disable RTC_WKUP IRQ channel in the NVIC. */ nvic_disable_irq(NVIC_RTC_WKUP_IRQ); /* 3. Disable RTC wakeup timer event. */ RTC_CR &= ~RTC_CR_WUTIE; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/spi.c000066400000000000000000000017251435536612600204640ustar00rootroot00000000000000/** @defgroup spi_file SPI @ingroup STM32F4xx @brief libopencm3 STM32F4xx SPI @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/stm32f405x6.ld000066400000000000000000000022301435536612600216630ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2011 Stephen Caudle * Copyright (C) 2013 Sergey Krukowski * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for the STM32F405RGT6 chip (1024K flash, 128K RAM). */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K } /* Include the common ld script. */ INCLUDE libopencm3_stm32f4.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/timer.c000066400000000000000000000025001435536612600210010ustar00rootroot00000000000000/* This file is used for documentation purposes. It does not need to be compiled. All source code is in the common area. If there is any device specific code required it can be included here, in which case this file must be added to the compile list. */ /** @defgroup timer_file Timers @ingroup STM32F4xx @brief libopencm3 STM32F4xx Timers @version 1.0.0 @date 18 August 2012 */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/usart.c000066400000000000000000000017361435536612600210310ustar00rootroot00000000000000/** @defgroup usart_file USART @ingroup STM32F4xx @brief libopencm3 STM32F4xx USART @version 1.0.0 @date 30 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/f4/vector_chipset.c000066400000000000000000000020061435536612600227030ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Piotr Esden-Tempski * Copyright (C) 2011 Fergus Noble * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include static void pre_main(void) { /* Enable access to Floating-Point coprocessor. */ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); } hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/000077500000000000000000000000001435536612600175235ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/Makefile000066400000000000000000000032251435536612600211650ustar00rootroot00000000000000## ## This file is part of the libopencm3 project. ## ## Copyright (C) 2009 Uwe Hermann ## ## This library is free software: you can redistribute it and/or modify ## it under the terms of the GNU Lesser General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## This library is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU Lesser General Public License for more details. ## ## You should have received a copy of the GNU Lesser General Public License ## along with this library. If not, see . ## LIBNAME = libopencm3_stm32l1 PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ -Wundef -Wshadow \ -I../../../include -fno-common \ -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs OBJS = crc.o desig.o flash.o rcc.o usart.o dma.o OBJS += crc_common_all.o dac_common_all.o OBJS += dma_common_l1f013.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_all.o iwdg_common_all.o OBJS += pwr_common_all.o pwr.o rtc_common_l1f024.o OBJS += spi_common_all.o timer_common_all.o OBJS += usart_common_all.o usart_common_f124.o OBJS += exti_common_all.o VPATH += ../../usb:../:../../cm3:../common include ../../Makefile.include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/crc.c000066400000000000000000000017261435536612600204440ustar00rootroot00000000000000/** @defgroup crc_file CRC @ingroup STM32L1xx @brief libopencm3 STM32L1xx CRC @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/dac.c000066400000000000000000000017241435536612600204220ustar00rootroot00000000000000/** @defgroup dac_file DAC @ingroup STM32L1xx @brief libopencm3 STM32L1xx DAC @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/dma.c000066400000000000000000000017571435536612600204420ustar00rootroot00000000000000/** @defgroup dma_file DMA * * @ingroup STM32L1xx * * @brief libopencm3 STM32L1xx DMA * * @version 1.0.0 * * @date 10 July 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/flash.c000066400000000000000000000025031435536612600207640ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2010 Mark Butler * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include void flash_64bit_enable(void) { FLASH_ACR |= FLASH_ACR_ACC64; } void flash_64bit_disable(void) { FLASH_ACR &= ~FLASH_ACR_ACC64; } void flash_prefetch_enable(void) { FLASH_ACR |= FLASH_ACR_PRFTEN; } void flash_prefetch_disable(void) { FLASH_ACR &= ~FLASH_ACR_PRFTEN; } void flash_set_ws(uint32_t ws) { uint32_t reg32; reg32 = FLASH_ACR; reg32 &= ~(1 << 0); reg32 |= ws; FLASH_ACR = reg32; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/gpio.c000066400000000000000000000016621435536612600206320ustar00rootroot00000000000000/** @defgroup gpio_file GPIO @ingroup STM32L1xx @brief libopencm3 STM32L1xx General Purpose I/O @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/i2c.c000066400000000000000000000017251435536612600203510ustar00rootroot00000000000000/** @defgroup i2c_file I2C @ingroup STM32L1xx @brief libopencm3 STM32L1xx I2C @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/iwdg.c000066400000000000000000000017571435536612600206330ustar00rootroot00000000000000/** @defgroup iwdg_file IWDG @ingroup STM32L1xx @brief libopencm3 STM32L1xx Independent Watchdog Timer @version 1.0.0 @date 18 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/libopencm3_stm32l1.ld000066400000000000000000000047631435536612600233760ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Uwe Hermann * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Generic linker script for STM32 targets using libopencm3. */ /* Memory regions must be defined in the ld script which includes this one. */ /* Enforce emmition of the vector table. */ EXTERN (vector_table) /* Define the entry point of the output file. */ ENTRY(reset_handler) /* Define sections. */ SECTIONS { .text : { *(.vectors) /* Vector table */ *(.text*) /* Program code */ . = ALIGN(4); *(.rodata*) /* Read-only data */ . = ALIGN(4); } >rom /* C++ Static constructors/destructors, also used for __attribute__ * ((constructor)) and the likes */ .preinit_array : { . = ALIGN(4); __preinit_array_start = .; KEEP (*(.preinit_array)) __preinit_array_end = .; } >rom .init_array : { . = ALIGN(4); __init_array_start = .; KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array)) __init_array_end = .; } >rom .fini_array : { . = ALIGN(4); __fini_array_start = .; KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) __fini_array_end = .; } >rom /* * Another section used by C++ stuff, appears when using newlib with * 64bit (long long) printf support */ .ARM.extab : { *(.ARM.extab*) } >rom .ARM.exidx : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >rom . = ALIGN(4); _etext = .; .data : { _data = .; *(.data*) /* Read-write initialized data */ . = ALIGN(4); _edata = .; } >ram AT >rom _data_loadaddr = LOADADDR(.data); .bss : { *(.bss*) /* Read-write zero initialized data */ *(COMMON) . = ALIGN(4); _ebss = .; } >ram /* * The .eh_frame section appears to be used for C++ exception handling. * You may need to fix this if you're using C++. */ /DISCARD/ : { *(.eh_frame) } . = ALIGN(4); end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/pwr.c000066400000000000000000000030701435536612600204770ustar00rootroot00000000000000/** @defgroup pwr-file PWR @ingroup STM32L1xx @brief libopencm3 STM32L1xx Power Control @version 1.0.0 @author @htmlonly © @endhtmlonly 2012 Karl Palsson @date 4 March 2013 This library supports the power control system for the STM32L1 series of ARM Cortex Microcontrollers by ST Microelectronics. LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include void pwr_set_vos_scale(vos_scale_t scale) { /* You are not allowed to write zeros here, don't try and optimize! */ uint32_t reg = PWR_CR; reg &= ~(PWR_CR_VOS_MASK); switch (scale) { case RANGE1: reg |= PWR_CR_VOS_RANGE1; break; case RANGE2: reg |= PWR_CR_VOS_RANGE2; break; case RANGE3: reg |= PWR_CR_VOS_RANGE3; break; } PWR_CR = reg; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/rcc.c000066400000000000000000000276031435536612600204460ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Federico Ruiz-Ugalde * Copyright (C) 2009 Uwe Hermann * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * Based on the F4 code... */ #include #include #include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ uint32_t rcc_ppre1_frequency = 2097000; uint32_t rcc_ppre2_frequency = 2097000; const clock_scale_t clock_config[CLOCK_CONFIG_END] = { { /* 24MHz PLL from HSI */ .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, .pll_mul = RCC_CFGR_PLLMUL_MUL3, .pll_div = RCC_CFGR_PLLDIV_DIV2, .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, .voltage_scale = RANGE1, .flash_config = FLASH_ACR_LATENCY_1WS, .apb1_frequency = 24000000, .apb2_frequency = 24000000, }, { /* 32MHz PLL from HSI */ .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, .pll_mul = RCC_CFGR_PLLMUL_MUL6, .pll_div = RCC_CFGR_PLLDIV_DIV3, .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, .voltage_scale = RANGE1, .flash_config = FLASH_ACR_LATENCY_1WS, .apb1_frequency = 32000000, .apb2_frequency = 32000000, }, { /* 16MHz HSI raw */ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, .voltage_scale = RANGE1, .flash_config = FLASH_ACR_LATENCY_0WS, .apb1_frequency = 16000000, .apb2_frequency = 16000000, }, { /* 4MHz HSI raw */ .hpre = RCC_CFGR_HPRE_SYSCLK_DIV4, .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, .voltage_scale = RANGE1, .flash_config = FLASH_ACR_LATENCY_0WS, .apb1_frequency = 4000000, .apb2_frequency = 4000000, }, { /* 4MHz MSI raw */ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, .voltage_scale = RANGE1, .flash_config = FLASH_ACR_LATENCY_0WS, .apb1_frequency = 4194000, .apb2_frequency = 4194000, .msi_range = RCC_ICSCR_MSIRANGE_4MHZ, }, { /* 2MHz MSI raw */ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, .voltage_scale = RANGE1, .flash_config = FLASH_ACR_LATENCY_0WS, .apb1_frequency = 2097000, .apb2_frequency = 2097000, .msi_range = RCC_ICSCR_MSIRANGE_2MHZ, }, }; void rcc_osc_ready_int_clear(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; case MSI: RCC_CIR |= RCC_CIR_MSIRDYC; break; } } void rcc_osc_ready_int_enable(osc_t osc) { switch (osc) { case PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; case MSI: RCC_CIR |= RCC_CIR_MSIRDYIE; break; } } void rcc_osc_ready_int_disable(osc_t osc) { switch (osc) { case PLL: RCC_CIR &= ~RCC_CIR_PLLRDYIE; break; case HSE: RCC_CIR &= ~RCC_CIR_HSERDYIE; break; case HSI: RCC_CIR &= ~RCC_CIR_HSIRDYIE; break; case LSE: RCC_CIR &= ~RCC_CIR_LSERDYIE; break; case LSI: RCC_CIR &= ~RCC_CIR_LSIRDYIE; break; case MSI: RCC_CIR &= ~RCC_CIR_MSIRDYIE; break; } } int rcc_osc_ready_int_flag(osc_t osc) { switch (osc) { case PLL: return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; case HSE: return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; case HSI: return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; case LSE: return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; case LSI: return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; case MSI: return ((RCC_CIR & RCC_CIR_MSIRDYF) != 0); break; } /* Shouldn't be reached. */ return -1; } void rcc_css_int_clear(void) { RCC_CIR |= RCC_CIR_CSSC; } int rcc_css_int_flag(void) { return ((RCC_CIR & RCC_CIR_CSSF) != 0); } void rcc_wait_for_osc_ready(osc_t osc) { switch (osc) { case PLL: while ((RCC_CR & RCC_CR_PLLRDY) == 0); break; case HSE: while ((RCC_CR & RCC_CR_HSERDY) == 0); break; case HSI: while ((RCC_CR & RCC_CR_HSIRDY) == 0); break; case MSI: while ((RCC_CR & RCC_CR_MSIRDY) == 0); break; case LSE: while ((RCC_CSR & RCC_CSR_LSERDY) == 0); break; case LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); break; } } void rcc_wait_for_sysclk_status(osc_t osc) { switch (osc) { case PLL: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_PLLCLK); break; case HSE: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSECLK); break; case HSI: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSICLK); break; case MSI: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_MSICLK); break; default: /* Shouldn't be reached. */ break; } } void rcc_osc_on(osc_t osc) { switch (osc) { case PLL: RCC_CR |= RCC_CR_PLLON; break; case MSI: RCC_CR |= RCC_CR_MSION; break; case HSE: RCC_CR |= RCC_CR_HSEON; break; case HSI: RCC_CR |= RCC_CR_HSION; break; case LSE: RCC_CSR |= RCC_CSR_LSEON; break; case LSI: RCC_CSR |= RCC_CSR_LSION; break; } } void rcc_osc_off(osc_t osc) { switch (osc) { case PLL: RCC_CR &= ~RCC_CR_PLLON; break; case MSI: RCC_CR &= ~RCC_CR_MSION; break; case HSE: RCC_CR &= ~RCC_CR_HSEON; break; case HSI: RCC_CR &= ~RCC_CR_HSION; break; case LSE: RCC_CSR &= ~RCC_CSR_LSEON; break; case LSI: RCC_CSR &= ~RCC_CSR_LSION; break; } } void rcc_css_enable(void) { RCC_CR |= RCC_CR_CSSON; } void rcc_css_disable(void) { RCC_CR &= ~RCC_CR_CSSON; } void rcc_osc_bypass_enable(osc_t osc) { switch (osc) { case HSE: RCC_CR |= RCC_CR_HSEBYP; break; case LSE: RCC_CSR |= RCC_CSR_LSEBYP; break; case PLL: case HSI: case LSI: case MSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_osc_bypass_disable(osc_t osc) { switch (osc) { case HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; case LSE: RCC_CSR &= ~RCC_CSR_LSEBYP; break; case PLL: case HSI: case LSI: case MSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en) { *reg |= en; } void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en) { *reg &= ~en; } void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset) { *reg |= reset; } void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset) { *reg &= ~clear_reset; } void rcc_set_sysclk_source(uint32_t clk) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 1) | (1 << 0)); RCC_CFGR = (reg32 | clk); } void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, uint32_t divisor) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT); reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT); reg32 &= ~(1 << 16); reg32 |= (source << 16); reg32 |= (multiplier << RCC_CFGR_PLLMUL_SHIFT); reg32 |= (divisor << RCC_CFGR_PLLDIV_SHIFT); RCC_CFGR = reg32; } void rcc_set_pll_source(uint32_t pllsrc) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~(1 << 16); RCC_CFGR = (reg32 | (pllsrc << 16)); } void rcc_set_ppre2(uint32_t ppre2) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11)); RCC_CFGR = (reg32 | (ppre2 << 11)); } void rcc_set_ppre1(uint32_t ppre1) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8)); RCC_CFGR = (reg32 | (ppre1 << 8)); } void rcc_set_hpre(uint32_t hpre) { uint32_t reg32; reg32 = RCC_CFGR; reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); RCC_CFGR = (reg32 | (hpre << 4)); } void rcc_set_rtcpre(uint32_t rtcpre) { uint32_t reg32; reg32 = RCC_CR; reg32 &= ~((1 << 30) | (1 << 29)); RCC_CR = (reg32 | (rtcpre << 29)); } uint32_t rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ return (RCC_CFGR & 0x000c) >> 2; } void rcc_rtc_select_clock(uint32_t clock) { RCC_CSR &= ~(RCC_CSR_RTCSEL_MASK << RCC_CSR_RTCSEL_SHIFT); RCC_CSR |= (clock << RCC_CSR_RTCSEL_SHIFT); } void rcc_clock_setup_msi(const clock_scale_t *clock) { /* Enable internal multi-speed oscillator. */ uint32_t reg = RCC_ICSCR; reg &= ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT); reg |= (clock->msi_range << RCC_ICSCR_MSIRANGE_SHIFT); RCC_ICSCR = reg; rcc_osc_on(MSI); rcc_wait_for_osc_ready(MSI); /* Select MSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_MSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN); pwr_set_vos_scale(clock->voltage_scale); /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; } void rcc_clock_setup_hsi(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN); pwr_set_vos_scale(clock->voltage_scale); /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; } void rcc_clock_setup_pll(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN); pwr_set_vos_scale(clock->voltage_scale); /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ flash_set_ws(clock->flash_config); rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; } hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/rtc.c000066400000000000000000000017561435536612600204700ustar00rootroot00000000000000/** @defgroup rtc_file RTC * * @ingroup STM32L1xx * * @brief libopencm3 STM32L1xx RTC * * @version 1.0.0 * * @date 4 March 2013 * * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/spi.c000066400000000000000000000017251435536612600204670ustar00rootroot00000000000000/** @defgroup spi_file SPI @ingroup STM32L1xx @brief libopencm3 STM32L1xx SPI @version 1.0.0 @date 15 October 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/stm32l15xx6.ld000066400000000000000000000021001435536612600217750ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32L15xx6, 32K flash, 10K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K eep (r) : ORIGIN = 0x08080000, LENGTH = 4K } /* Include the common ld script. */ INCLUDE libopencm3_stm32l1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/stm32l15xx8.ld000066400000000000000000000021001435536612600217770ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32L15xx8, 64K flash, 10K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K eep (r) : ORIGIN = 0x08080000, LENGTH = 4K } /* Include the common ld script. */ INCLUDE libopencm3_stm32l1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/stm32l15xxb.ld000066400000000000000000000021021435536612600220530ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32L15xxB, 128K flash, 16K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K eep (r) : ORIGIN = 0x08080000, LENGTH = 4K } /* Include the common ld script. */ INCLUDE libopencm3_stm32l1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/stm32l15xxc.ld000066400000000000000000000021021435536612600220540ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32L15xxC, 256k flash, 32K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K eep (r) : ORIGIN = 0x08080000, LENGTH = 8K } /* Include the common ld script. */ INCLUDE libopencm3_stm32l1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/stm32l15xxd.ld000066400000000000000000000021031435536612600220560ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2013 Karl Palsson * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /* Linker script for STM32L15xxD, 384K flash, 38K RAM. */ /* Define memory regions. */ MEMORY { rom (rx) : ORIGIN = 0x08000000, LENGTH = 384K ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K eep (r) : ORIGIN = 0x08080000, LENGTH = 12K } /* Include the common ld script. */ INCLUDE libopencm3_stm32l1.ld hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/timer.c000066400000000000000000000034141435536612600210110ustar00rootroot00000000000000/** @defgroup timer_file Timers @ingroup STM32L1xx @brief libopencm3 STM32L1xx Timers @version 1.0.0 @date 18 August 2012 */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Edward Cheeseman * Copyright (C) 2011 Stephen Caudle * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include /*---------------------------------------------------------------------------*/ /** @brief Set Timer Option Set timer options register on TIM2 or TIM3, used for trigger remapping. @param[in] timer_peripheral Unsigned int32. Timer register address base @returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3: @ref tim3_opt_trigger_remap. */ void timer_set_option(uint32_t timer_peripheral, uint32_t option) { if (timer_peripheral == TIM2) { TIM_OR(timer_peripheral) &= ~TIM2_OR_ITR1_RMP_MASK; TIM_OR(timer_peripheral) |= option; } else if (timer_peripheral == TIM3) { TIM_OR(timer_peripheral) &= ~TIM3_OR_ITR2_RMP_MASK; TIM_OR(timer_peripheral) |= option; } } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/stm32/l1/usart.c000066400000000000000000000017361435536612600210340ustar00rootroot00000000000000/** @defgroup usart_file USART @ingroup STM32L1xx @brief libopencm3 STM32L1xx USART @version 1.0.0 @date 30 August 2012 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include hackrf-0.0~git20230104.cfc2f34/lib/usb/000077500000000000000000000000001435536612600170305ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/lib/usb/usb.c000066400000000000000000000116251435536612600177720ustar00rootroot00000000000000/** @defgroup usb_drivers_file Generic USB Drivers @ingroup USB @brief Generic USB Drivers @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include #include "usb_private.h" /** * Main initialization entry point. * * Initialize the USB firmware library to implement the USB device described * by the descriptors provided. * * It is required that the 48MHz USB clock is already available. * * @param driver TODO * @param dev Pointer to USB device descriptor. This must not be changed while * the device is in use. * @param conf Pointer to array of USB configuration descriptors. These must * not be changed while the device is in use. The length of this * array is determined by the bNumConfigurations field in the * device descriptor. * @param strings TODO * @param control_buffer Pointer to array that would hold the data * received during control requests with DATA * stage * @param control_buffer_size Size of control_buffer * @return Zero on success (currently cannot fail). */ usbd_device *usbd_init(const usbd_driver *driver, const struct usb_device_descriptor *dev, const struct usb_config_descriptor *conf, const char **strings, int num_strings, uint8_t *control_buffer, uint16_t control_buffer_size) { usbd_device *usbd_dev; usbd_dev = driver->init(); usbd_dev->driver = driver; usbd_dev->desc = dev; usbd_dev->config = conf; usbd_dev->strings = strings; usbd_dev->num_strings = num_strings; usbd_dev->ctrl_buf = control_buffer; usbd_dev->ctrl_buf_len = control_buffer_size; usbd_dev->user_callback_ctr[0][USB_TRANSACTION_SETUP] = _usbd_control_setup; usbd_dev->user_callback_ctr[0][USB_TRANSACTION_OUT] = _usbd_control_out; usbd_dev->user_callback_ctr[0][USB_TRANSACTION_IN] = _usbd_control_in; return usbd_dev; } void usbd_register_reset_callback(usbd_device *usbd_dev, void (*callback)(void)) { usbd_dev->user_callback_reset = callback; } void usbd_register_suspend_callback(usbd_device *usbd_dev, void (*callback)(void)) { usbd_dev->user_callback_suspend = callback; } void usbd_register_resume_callback(usbd_device *usbd_dev, void (*callback)(void)) { usbd_dev->user_callback_resume = callback; } void usbd_register_sof_callback(usbd_device *usbd_dev, void (*callback)(void)) { usbd_dev->user_callback_sof = callback; } void _usbd_reset(usbd_device *usbd_dev) { usbd_dev->current_address = 0; usbd_dev->current_config = 0; usbd_ep_setup(usbd_dev, 0, USB_ENDPOINT_ATTR_CONTROL, 64, NULL); usbd_dev->driver->set_address(usbd_dev, 0); if (usbd_dev->user_callback_reset) { usbd_dev->user_callback_reset(); } } /* Functions to wrap the low-level driver */ void usbd_poll(usbd_device *usbd_dev) { usbd_dev->driver->poll(usbd_dev); } void usbd_disconnect(usbd_device *usbd_dev, bool disconnected) { /* not all drivers support disconnection */ if (usbd_dev->driver->disconnect) { usbd_dev->driver->disconnect(usbd_dev, disconnected); } } void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*callback)(usbd_device *usbd_dev, uint8_t ep)) { usbd_dev->driver->ep_setup(usbd_dev, addr, type, max_size, callback); } uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len) { return usbd_dev->driver->ep_write_packet(usbd_dev, addr, buf, len); } uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len) { return usbd_dev->driver->ep_read_packet(usbd_dev, addr, buf, len); } void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall) { usbd_dev->driver->ep_stall_set(usbd_dev, addr, stall); } uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr) { return usbd_dev->driver->ep_stall_get(usbd_dev, addr); } void usbd_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak) { usbd_dev->driver->ep_nak_set(usbd_dev, addr, nak); } /**@}*/ hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_control.c000066400000000000000000000172421435536612600215330ustar00rootroot00000000000000/** @defgroup usb_control_file Generic USB Control Requests @ingroup USB @brief Generic USB Control Requests @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include #include "usb_private.h" /* * According to the USB 2.0 specification, section 8.5.3, when a control * transfer is stalled, the pipe becomes idle. We provide one utility to stall * a transaction to reduce boilerplate code. */ static void stall_transaction(usbd_device *usbd_dev) { usbd_ep_stall_set(usbd_dev, 0, 1); usbd_dev->control_state.state = IDLE; } /* Register application callback function for handling USB control requests. */ int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type, uint8_t type_mask, usbd_control_callback callback) { int i; for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { if (usbd_dev->user_control_callback[i].cb) { continue; } usbd_dev->user_control_callback[i].type = type; usbd_dev->user_control_callback[i].type_mask = type_mask; usbd_dev->user_control_callback[i].cb = callback; return 0; } return -1; } static void usb_control_send_chunk(usbd_device *usbd_dev) { if (usbd_dev->desc->bMaxPacketSize0 < usbd_dev->control_state.ctrl_len) { /* Data stage, normal transmission */ usbd_ep_write_packet(usbd_dev, 0, usbd_dev->control_state.ctrl_buf, usbd_dev->desc->bMaxPacketSize0); usbd_dev->control_state.state = DATA_IN; usbd_dev->control_state.ctrl_buf += usbd_dev->desc->bMaxPacketSize0; usbd_dev->control_state.ctrl_len -= usbd_dev->desc->bMaxPacketSize0; } else { /* Data stage, end of transmission */ usbd_ep_write_packet(usbd_dev, 0, usbd_dev->control_state.ctrl_buf, usbd_dev->control_state.ctrl_len); usbd_dev->control_state.state = LAST_DATA_IN; usbd_dev->control_state.ctrl_len = 0; usbd_dev->control_state.ctrl_buf = NULL; } } static int usb_control_recv_chunk(usbd_device *usbd_dev) { uint16_t packetsize = MIN(usbd_dev->desc->bMaxPacketSize0, usbd_dev->control_state.req.wLength - usbd_dev->control_state.ctrl_len); uint16_t size = usbd_ep_read_packet(usbd_dev, 0, usbd_dev->control_state.ctrl_buf + usbd_dev->control_state.ctrl_len, packetsize); if (size != packetsize) { stall_transaction(usbd_dev); return -1; } usbd_dev->control_state.ctrl_len += size; return packetsize; } static int usb_control_request_dispatch(usbd_device *usbd_dev, struct usb_setup_data *req) { int i, result = 0; struct user_control_callback *cb = usbd_dev->user_control_callback; /* Call user command hook function. */ for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { if (cb[i].cb == NULL) { break; } if ((req->bmRequestType & cb[i].type_mask) == cb[i].type) { result = cb[i].cb(usbd_dev, req, &(usbd_dev->control_state.ctrl_buf), &(usbd_dev->control_state.ctrl_len), &(usbd_dev->control_state.complete)); if (result == USBD_REQ_HANDLED || result == USBD_REQ_NOTSUPP) { return result; } } } /* Try standard request if not already handled. */ return _usbd_standard_request(usbd_dev, req, &(usbd_dev->control_state.ctrl_buf), &(usbd_dev->control_state.ctrl_len)); } /* Handle commands and read requests. */ static void usb_control_setup_read(usbd_device *usbd_dev, struct usb_setup_data *req) { usbd_dev->control_state.ctrl_buf = usbd_dev->ctrl_buf; usbd_dev->control_state.ctrl_len = req->wLength; if (usb_control_request_dispatch(usbd_dev, req)) { if (usbd_dev->control_state.ctrl_len) { /* Go to data out stage if handled. */ usb_control_send_chunk(usbd_dev); } else { /* Go to status stage if handled. */ usbd_ep_write_packet(usbd_dev, 0, NULL, 0); usbd_dev->control_state.state = STATUS_IN; } } else { /* Stall endpoint on failure. */ stall_transaction(usbd_dev); } } static void usb_control_setup_write(usbd_device *usbd_dev, struct usb_setup_data *req) { if (req->wLength > usbd_dev->ctrl_buf_len) { stall_transaction(usbd_dev); return; } /* Buffer into which to write received data. */ usbd_dev->control_state.ctrl_buf = usbd_dev->ctrl_buf; usbd_dev->control_state.ctrl_len = 0; /* Wait for DATA OUT stage. */ if (req->wLength > usbd_dev->desc->bMaxPacketSize0) { usbd_dev->control_state.state = DATA_OUT; } else { usbd_dev->control_state.state = LAST_DATA_OUT; } } /* Do not appear to belong to the API, so are omitted from docs */ /**@}*/ void _usbd_control_setup(usbd_device *usbd_dev, uint8_t ea) { struct usb_setup_data *req = &usbd_dev->control_state.req; (void)ea; usbd_dev->control_state.complete = NULL; if (usbd_ep_read_packet(usbd_dev, 0, req, 8) != 8) { stall_transaction(usbd_dev); return; } if (req->wLength == 0) { usb_control_setup_read(usbd_dev, req); } else if (req->bmRequestType & 0x80) { usb_control_setup_read(usbd_dev, req); } else { usb_control_setup_write(usbd_dev, req); } } void _usbd_control_out(usbd_device *usbd_dev, uint8_t ea) { (void)ea; switch (usbd_dev->control_state.state) { case DATA_OUT: if (usb_control_recv_chunk(usbd_dev) < 0) { break; } if ((usbd_dev->control_state.req.wLength - usbd_dev->control_state.ctrl_len) <= usbd_dev->desc->bMaxPacketSize0) { usbd_dev->control_state.state = LAST_DATA_OUT; } break; case LAST_DATA_OUT: if (usb_control_recv_chunk(usbd_dev) < 0) { break; } /* * We have now received the full data payload. * Invoke callback to process. */ if (usb_control_request_dispatch(usbd_dev, &(usbd_dev->control_state.req))) { /* Got to status stage on success. */ usbd_ep_write_packet(usbd_dev, 0, NULL, 0); usbd_dev->control_state.state = STATUS_IN; } else { stall_transaction(usbd_dev); } break; case STATUS_OUT: usbd_ep_read_packet(usbd_dev, 0, NULL, 0); usbd_dev->control_state.state = IDLE; if (usbd_dev->control_state.complete) { usbd_dev->control_state.complete(usbd_dev, &(usbd_dev->control_state.req)); } usbd_dev->control_state.complete = NULL; break; default: stall_transaction(usbd_dev); } } void _usbd_control_in(usbd_device *usbd_dev, uint8_t ea) { (void)ea; struct usb_setup_data *req = &(usbd_dev->control_state.req); switch (usbd_dev->control_state.state) { case DATA_IN: usb_control_send_chunk(usbd_dev); break; case LAST_DATA_IN: usbd_dev->control_state.state = STATUS_OUT; break; case STATUS_IN: if (usbd_dev->control_state.complete) { usbd_dev->control_state.complete(usbd_dev, &(usbd_dev->control_state.req)); } /* Exception: Handle SET ADDRESS function here... */ if ((req->bmRequestType == 0) && (req->bRequest == USB_REQ_SET_ADDRESS)) { usbd_dev->driver->set_address(usbd_dev, req->wValue); } usbd_dev->control_state.state = IDLE; break; default: stall_transaction(usbd_dev); } } hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_f103.c000066400000000000000000000213571435536612600205260ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include #include #include #include "usb_private.h" static usbd_device *stm32f103_usbd_init(void); static void stm32f103_set_address(usbd_device *usbd_dev, uint8_t addr); static void stm32f103_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*callback) (usbd_device *usbd_dev, uint8_t ep)); static void stm32f103_endpoints_reset(usbd_device *usbd_dev); static void stm32f103_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall); static uint8_t stm32f103_ep_stall_get(usbd_device *usbd_dev, uint8_t addr); static void stm32f103_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak); static uint16_t stm32f103_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len); static uint16_t stm32f103_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len); static void stm32f103_poll(usbd_device *usbd_dev); static uint8_t force_nak[8]; static struct _usbd_device usbd_dev; const struct _usbd_driver stm32f103_usb_driver = { .init = stm32f103_usbd_init, .set_address = stm32f103_set_address, .ep_setup = stm32f103_ep_setup, .ep_reset = stm32f103_endpoints_reset, .ep_stall_set = stm32f103_ep_stall_set, .ep_stall_get = stm32f103_ep_stall_get, .ep_nak_set = stm32f103_ep_nak_set, .ep_write_packet = stm32f103_ep_write_packet, .ep_read_packet = stm32f103_ep_read_packet, .poll = stm32f103_poll, }; /** Initialize the USB device controller hardware of the STM32. */ static usbd_device *stm32f103_usbd_init(void) { rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN); SET_REG(USB_CNTR_REG, 0); SET_REG(USB_BTABLE_REG, 0); SET_REG(USB_ISTR_REG, 0); /* Enable RESET, SUSPEND, RESUME and CTR interrupts. */ SET_REG(USB_CNTR_REG, USB_CNTR_RESETM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM); return &usbd_dev; } static void stm32f103_set_address(usbd_device *dev, uint8_t addr) { (void)dev; /* Set device address and enable. */ SET_REG(USB_DADDR_REG, (addr & USB_DADDR_ADDR) | USB_DADDR_ENABLE); } /** * Set the receive buffer size for a given USB endpoint. * * @param ep Index of endpoint to configure. * @param size Size in bytes of the RX buffer. */ static void usb_set_ep_rx_bufsize(usbd_device *dev, uint8_t ep, uint32_t size) { (void)dev; if (size > 62) { if (size & 0x1f) { size -= 32; } USB_SET_EP_RX_COUNT(ep, (size << 5) | 0x8000); } else { if (size & 1) { size++; } USB_SET_EP_RX_COUNT(ep, size << 10); } } static void stm32f103_ep_setup(usbd_device *dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*callback) (usbd_device *usbd_dev, uint8_t ep)) { /* Translate USB standard type codes to STM32. */ const uint16_t typelookup[] = { [USB_ENDPOINT_ATTR_CONTROL] = USB_EP_TYPE_CONTROL, [USB_ENDPOINT_ATTR_ISOCHRONOUS] = USB_EP_TYPE_ISO, [USB_ENDPOINT_ATTR_BULK] = USB_EP_TYPE_BULK, [USB_ENDPOINT_ATTR_INTERRUPT] = USB_EP_TYPE_INTERRUPT, }; uint8_t dir = addr & 0x80; addr &= 0x7f; /* Assign address. */ USB_SET_EP_ADDR(addr, addr); USB_SET_EP_TYPE(addr, typelookup[type]); if (dir || (addr == 0)) { USB_SET_EP_TX_ADDR(addr, dev->pm_top); if (callback) { dev->user_callback_ctr[addr][USB_TRANSACTION_IN] = (void *)callback; } USB_CLR_EP_TX_DTOG(addr); USB_SET_EP_TX_STAT(addr, USB_EP_TX_STAT_NAK); dev->pm_top += max_size; } if (!dir) { USB_SET_EP_RX_ADDR(addr, dev->pm_top); usb_set_ep_rx_bufsize(dev, addr, max_size); if (callback) { dev->user_callback_ctr[addr][USB_TRANSACTION_OUT] = (void *)callback; } USB_CLR_EP_RX_DTOG(addr); USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID); dev->pm_top += max_size; } } static void stm32f103_endpoints_reset(usbd_device *dev) { int i; /* Reset all endpoints. */ for (i = 1; i < 8; i++) { USB_SET_EP_TX_STAT(i, USB_EP_TX_STAT_DISABLED); USB_SET_EP_RX_STAT(i, USB_EP_RX_STAT_DISABLED); } dev->pm_top = 0x40 + (2 * dev->desc->bMaxPacketSize0); } static void stm32f103_ep_stall_set(usbd_device *dev, uint8_t addr, uint8_t stall) { (void)dev; if (addr == 0) { USB_SET_EP_TX_STAT(addr, stall ? USB_EP_TX_STAT_STALL : USB_EP_TX_STAT_NAK); } if (addr & 0x80) { addr &= 0x7F; USB_SET_EP_TX_STAT(addr, stall ? USB_EP_TX_STAT_STALL : USB_EP_TX_STAT_NAK); /* Reset to DATA0 if clearing stall condition. */ if (!stall) { USB_CLR_EP_TX_DTOG(addr); } } else { /* Reset to DATA0 if clearing stall condition. */ if (!stall) { USB_CLR_EP_RX_DTOG(addr); } USB_SET_EP_RX_STAT(addr, stall ? USB_EP_RX_STAT_STALL : USB_EP_RX_STAT_VALID); } } static uint8_t stm32f103_ep_stall_get(usbd_device *dev, uint8_t addr) { (void)dev; if (addr & 0x80) { if ((*USB_EP_REG(addr & 0x7F) & USB_EP_TX_STAT) == USB_EP_TX_STAT_STALL) { return 1; } } else { if ((*USB_EP_REG(addr) & USB_EP_RX_STAT) == USB_EP_RX_STAT_STALL) { return 1; } } return 0; } static void stm32f103_ep_nak_set(usbd_device *dev, uint8_t addr, uint8_t nak) { (void)dev; /* It does not make sence to force NAK on IN endpoints. */ if (addr & 0x80) { return; } force_nak[addr] = nak; if (nak) { USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_NAK); } else { USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID); } } /** * Copy a data buffer to packet memory. * * @param vPM Destination pointer into packet memory. * @param buf Source pointer to data buffer. * @param len Number of bytes to copy. */ static void usb_copy_to_pm(volatile void *vPM, const void *buf, uint16_t len) { const uint16_t *lbuf = buf; volatile uint16_t *PM = vPM; for (len = (len + 1) >> 1; len; PM += 2, lbuf++, len--) { *PM = *lbuf; } } static uint16_t stm32f103_ep_write_packet(usbd_device *dev, uint8_t addr, const void *buf, uint16_t len) { (void)dev; addr &= 0x7F; if ((*USB_EP_REG(addr) & USB_EP_TX_STAT) == USB_EP_TX_STAT_VALID) { return 0; } usb_copy_to_pm(USB_GET_EP_TX_BUFF(addr), buf, len); USB_SET_EP_TX_COUNT(addr, len); USB_SET_EP_TX_STAT(addr, USB_EP_TX_STAT_VALID); return len; } /** * Copy a data buffer from packet memory. * * @param buf Source pointer to data buffer. * @param vPM Destination pointer into packet memory. * @param len Number of bytes to copy. */ static void usb_copy_from_pm(void *buf, const volatile void *vPM, uint16_t len) { uint16_t *lbuf = buf; const volatile uint16_t *PM = vPM; uint8_t odd = len & 1; for (len >>= 1; len; PM += 2, lbuf++, len--) { *lbuf = *PM; } if (odd) { *(uint8_t *) lbuf = *(uint8_t *) PM; } } static uint16_t stm32f103_ep_read_packet(usbd_device *dev, uint8_t addr, void *buf, uint16_t len) { (void)dev; if ((*USB_EP_REG(addr) & USB_EP_RX_STAT) == USB_EP_RX_STAT_VALID) { return 0; } len = MIN(USB_GET_EP_RX_COUNT(addr) & 0x3ff, len); usb_copy_from_pm(buf, USB_GET_EP_RX_BUFF(addr), len); USB_CLR_EP_RX_CTR(addr); if (!force_nak[addr]) { USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID); } return len; } static void stm32f103_poll(usbd_device *dev) { uint16_t istr = *USB_ISTR_REG; if (istr & USB_ISTR_RESET) { dev->pm_top = 0x40; _usbd_reset(dev); USB_CLR_ISTR_RESET(); return; } if (istr & USB_ISTR_CTR) { uint8_t ep = istr & USB_ISTR_EP_ID; uint8_t type = (istr & USB_ISTR_DIR) ? 1 : 0; if (type) { /* OUT or SETUP transaction */ type += (*USB_EP_REG(ep) & USB_EP_SETUP) ? 1 : 0; } else { /* IN transaction */ USB_CLR_EP_TX_CTR(ep); } if (dev->user_callback_ctr[ep][type]) { dev->user_callback_ctr[ep][type] (dev, ep); } else { USB_CLR_EP_RX_CTR(ep); } } if (istr & USB_ISTR_SUSP) { USB_CLR_ISTR_SUSP(); if (dev->user_callback_suspend) { dev->user_callback_suspend(); } } if (istr & USB_ISTR_WKUP) { USB_CLR_ISTR_WKUP(); if (dev->user_callback_resume) { dev->user_callback_resume(); } } if (istr & USB_ISTR_SOF) { if (dev->user_callback_sof) { dev->user_callback_sof(); } USB_CLR_ISTR_SOF(); } } hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_f107.c000066400000000000000000000055631435536612600205330ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include #include #include #include "usb_private.h" #include "usb_fx07_common.h" /* Receive FIFO size in 32-bit words. */ #define RX_FIFO_SIZE 128 static usbd_device *stm32f107_usbd_init(void); static struct _usbd_device usbd_dev; const struct _usbd_driver stm32f107_usb_driver = { .init = stm32f107_usbd_init, .set_address = stm32fx07_set_address, .ep_setup = stm32fx07_ep_setup, .ep_reset = stm32fx07_endpoints_reset, .ep_stall_set = stm32fx07_ep_stall_set, .ep_stall_get = stm32fx07_ep_stall_get, .ep_nak_set = stm32fx07_ep_nak_set, .ep_write_packet = stm32fx07_ep_write_packet, .ep_read_packet = stm32fx07_ep_read_packet, .poll = stm32fx07_poll, .disconnect = stm32fx07_disconnect, .base_address = USB_OTG_FS_BASE, .set_address_before_status = 1, .rx_fifo_size = RX_FIFO_SIZE, }; /** Initialize the USB device controller hardware of the STM32. */ static usbd_device *stm32f107_usbd_init(void) { OTG_FS_GINTSTS = OTG_FS_GINTSTS_MMIS; OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_PHYSEL; /* Enable VBUS sensing in device mode and power down the PHY. */ OTG_FS_GCCFG |= OTG_FS_GCCFG_VBUSBSEN | OTG_FS_GCCFG_PWRDWN; /* Wait for AHB idle. */ while (!(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_AHBIDL)); /* Do core soft reset. */ OTG_FS_GRSTCTL |= OTG_FS_GRSTCTL_CSRST; while (OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_CSRST); /* Force peripheral only mode. */ OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_FDMOD | OTG_FS_GUSBCFG_TRDT_MASK; /* Full speed device. */ OTG_FS_DCFG |= OTG_FS_DCFG_DSPD; /* Restart the PHY clock. */ OTG_FS_PCGCCTL = 0; OTG_FS_GRXFSIZ = stm32f107_usb_driver.rx_fifo_size; usbd_dev.fifo_mem_top = stm32f107_usb_driver.rx_fifo_size; /* Unmask interrupts for TX and RX. */ OTG_FS_GAHBCFG |= OTG_FS_GAHBCFG_GINT; OTG_FS_GINTMSK = OTG_FS_GINTMSK_ENUMDNEM | OTG_FS_GINTMSK_RXFLVLM | OTG_FS_GINTMSK_IEPINT | OTG_FS_GINTMSK_USBSUSPM | OTG_FS_GINTMSK_WUIM | OTG_FS_GINTMSK_SOFM; OTG_FS_DAINTMSK = 0xF; OTG_FS_DIEPMSK = OTG_FS_DIEPMSK_XFRCM; return &usbd_dev; } hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_f207.c000066400000000000000000000055631435536612600205340ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include #include #include #include "usb_private.h" #include "usb_fx07_common.h" /* Receive FIFO size in 32-bit words. */ #define RX_FIFO_SIZE 512 static usbd_device *stm32f207_usbd_init(void); static struct _usbd_device usbd_dev; const struct _usbd_driver stm32f207_usb_driver = { .init = stm32f207_usbd_init, .set_address = stm32fx07_set_address, .ep_setup = stm32fx07_ep_setup, .ep_reset = stm32fx07_endpoints_reset, .ep_stall_set = stm32fx07_ep_stall_set, .ep_stall_get = stm32fx07_ep_stall_get, .ep_nak_set = stm32fx07_ep_nak_set, .ep_write_packet = stm32fx07_ep_write_packet, .ep_read_packet = stm32fx07_ep_read_packet, .poll = stm32fx07_poll, .disconnect = stm32fx07_disconnect, .base_address = USB_OTG_HS_BASE, .set_address_before_status = 1, .rx_fifo_size = RX_FIFO_SIZE, }; /** Initialize the USB device controller hardware of the STM32. */ static usbd_device *stm32f207_usbd_init(void) { OTG_HS_GINTSTS = OTG_HS_GINTSTS_MMIS; OTG_HS_GUSBCFG |= OTG_HS_GUSBCFG_PHYSEL; /* Enable VBUS sensing in device mode and power down the PHY. */ OTG_HS_GCCFG |= OTG_HS_GCCFG_VBUSBSEN | OTG_HS_GCCFG_PWRDWN; /* Wait for AHB idle. */ while (!(OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_AHBIDL)); /* Do core soft reset. */ OTG_HS_GRSTCTL |= OTG_HS_GRSTCTL_CSRST; while (OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_CSRST); /* Force peripheral only mode. */ OTG_HS_GUSBCFG |= OTG_HS_GUSBCFG_FDMOD | OTG_HS_GUSBCFG_TRDT_MASK; /* Full speed device. */ OTG_HS_DCFG |= OTG_HS_DCFG_DSPD; /* Restart the PHY clock. */ OTG_HS_PCGCCTL = 0; OTG_HS_GRXFSIZ = stm32f207_usb_driver.rx_fifo_size; usbd_dev.fifo_mem_top = stm32f207_usb_driver.rx_fifo_size; /* Unmask interrupts for TX and RX. */ OTG_HS_GAHBCFG |= OTG_HS_GAHBCFG_GINT; OTG_HS_GINTMSK = OTG_HS_GINTMSK_ENUMDNEM | OTG_HS_GINTMSK_RXFLVLM | OTG_HS_GINTMSK_IEPINT | OTG_HS_GINTMSK_USBSUSPM | OTG_HS_GINTMSK_WUIM | OTG_HS_GINTMSK_SOFM; OTG_HS_DAINTMSK = 0xF; OTG_HS_DIEPMSK = OTG_HS_DIEPMSK_XFRCM; return &usbd_dev; } hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_fx07_common.c000066400000000000000000000221371435536612600222060ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #include #include #include #include #include #include #include "usb_private.h" #include "usb_fx07_common.h" /* The FS core and the HS core have the same register layout. * As the code can be used on both cores, the registers offset is modified * according to the selected cores base address. */ #define dev_base_address (usbd_dev->driver->base_address) #define REBASE(x) MMIO32((x) + (dev_base_address)) #define REBASE_FIFO(x) (&MMIO32((dev_base_address) + (OTG_FIFO(x)))) void stm32fx07_set_address(usbd_device *usbd_dev, uint8_t addr) { REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_FS_DCFG_DAD) | (addr << 4); } void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*callback) (usbd_device *usbd_dev, uint8_t ep)) { /* * Configure endpoint address and type. Allocate FIFO memory for * endpoint. Install callback funciton. */ uint8_t dir = addr & 0x80; addr &= 0x7f; if (addr == 0) { /* For the default control endpoint */ /* Configure IN part. */ if (max_size >= 64) { REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_64; } else if (max_size >= 32) { REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_32; } else if (max_size >= 16) { REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_16; } else { REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_8; } REBASE(OTG_DIEPTSIZ0) = (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); REBASE(OTG_DIEPCTL0) |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK; /* Configure OUT part. */ usbd_dev->doeptsiz[0] = OTG_FS_DIEPSIZ0_STUPCNT_1 | OTG_FS_DIEPSIZ0_PKTCNT | (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); REBASE(OTG_DOEPTSIZ(0)) = usbd_dev->doeptsiz[0]; REBASE(OTG_DOEPCTL(0)) |= OTG_FS_DOEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK; REBASE(OTG_GNPTXFSIZ) = ((max_size / 4) << 16) | usbd_dev->driver->rx_fifo_size; usbd_dev->fifo_mem_top += max_size / 4; usbd_dev->fifo_mem_top_ep0 = usbd_dev->fifo_mem_top; return; } if (dir) { REBASE(OTG_DIEPTXF(addr)) = ((max_size / 4) << 16) | usbd_dev->fifo_mem_top; usbd_dev->fifo_mem_top += max_size / 4; REBASE(OTG_DIEPTSIZ(addr)) = (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK | (type << 18) | OTG_FS_DIEPCTL0_USBAEP | OTG_FS_DIEPCTLX_SD0PID | (addr << 22) | max_size; if (callback) { usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_IN] = (void *)callback; } } if (!dir) { usbd_dev->doeptsiz[addr] = OTG_FS_DIEPSIZ0_PKTCNT | (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); REBASE(OTG_DOEPTSIZ(addr)) = usbd_dev->doeptsiz[addr]; REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_EPENA | OTG_FS_DOEPCTL0_USBAEP | OTG_FS_DIEPCTL0_CNAK | OTG_FS_DOEPCTLX_SD0PID | (type << 18) | max_size; if (callback) { usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_OUT] = (void *)callback; } } } void stm32fx07_endpoints_reset(usbd_device *usbd_dev) { /* The core resets the endpoints automatically on reset. */ usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0; } void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall) { if (addr == 0) { if (stall) { REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_STALL; } else { REBASE(OTG_DIEPCTL(addr)) &= ~OTG_FS_DIEPCTL0_STALL; } } if (addr & 0x80) { addr &= 0x7F; if (stall) { REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_STALL; } else { REBASE(OTG_DIEPCTL(addr)) &= ~OTG_FS_DIEPCTL0_STALL; REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTLX_SD0PID; } } else { if (stall) { REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_STALL; } else { REBASE(OTG_DOEPCTL(addr)) &= ~OTG_FS_DOEPCTL0_STALL; REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTLX_SD0PID; } } } uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr) { /* Return non-zero if STALL set. */ if (addr & 0x80) { return (REBASE(OTG_DIEPCTL(addr & 0x7f)) & OTG_FS_DIEPCTL0_STALL) ? 1 : 0; } else { return (REBASE(OTG_DOEPCTL(addr)) & OTG_FS_DOEPCTL0_STALL) ? 1 : 0; } } void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak) { /* It does not make sence to force NAK on IN endpoints. */ if (addr & 0x80) { return; } usbd_dev->force_nak[addr] = nak; if (nak) { REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_SNAK; } else { REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_CNAK; } } uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len) { const uint32_t *buf32 = buf; int i; addr &= 0x7F; /* Return if endpoint is already enabled. */ if (REBASE(OTG_DIEPTSIZ(addr)) & OTG_FS_DIEPSIZ0_PKTCNT) { return 0; } /* Enable endpoint for transmission. */ REBASE(OTG_DIEPTSIZ(addr)) = OTG_FS_DIEPSIZ0_PKTCNT | len; REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_CNAK; volatile uint32_t *fifo = REBASE_FIFO(addr); /* Copy buffer to endpoint FIFO, note - memcpy does not work */ for (i = len; i > 0; i -= 4) { *fifo++ = *buf32++; } return len; } uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len) { int i; uint32_t *buf32 = buf; uint32_t extra; len = MIN(len, usbd_dev->rxbcnt); usbd_dev->rxbcnt -= len; volatile uint32_t *fifo = REBASE_FIFO(addr); for (i = len; i >= 4; i -= 4) { *buf32++ = *fifo++; } if (i) { extra = *fifo++; memcpy(buf32, &extra, i); } REBASE(OTG_DOEPTSIZ(addr)) = usbd_dev->doeptsiz[addr]; REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_EPENA | (usbd_dev->force_nak[addr] ? OTG_FS_DOEPCTL0_SNAK : OTG_FS_DOEPCTL0_CNAK); return len; } void stm32fx07_poll(usbd_device *usbd_dev) { /* Read interrupt status register. */ uint32_t intsts = REBASE(OTG_GINTSTS); int i; if (intsts & OTG_FS_GINTSTS_ENUMDNE) { /* Handle USB RESET condition. */ REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_ENUMDNE; usbd_dev->fifo_mem_top = usbd_dev->driver->rx_fifo_size; _usbd_reset(usbd_dev); return; } /* Note: RX and TX handled differently in this device. */ if (intsts & OTG_FS_GINTSTS_RXFLVL) { /* Receive FIFO non-empty. */ uint32_t rxstsp = REBASE(OTG_GRXSTSP); uint32_t pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK; if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) && (pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP)) { return; } uint8_t ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK; uint8_t type; if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP) { type = USB_TRANSACTION_SETUP; } else { type = USB_TRANSACTION_OUT; } /* Save packet size for stm32f107_ep_read_packet(). */ usbd_dev->rxbcnt = (rxstsp & OTG_FS_GRXSTSP_BCNT_MASK) >> 4; /* * FIXME: Why is a delay needed here? * This appears to fix a problem where the first 4 bytes * of the DATA OUT stage of a control transaction are lost. */ for (i = 0; i < 1000; i++) { __asm__("nop"); } if (usbd_dev->user_callback_ctr[ep][type]) { usbd_dev->user_callback_ctr[ep][type] (usbd_dev, ep); } /* Discard unread packet data. */ for (i = 0; i < usbd_dev->rxbcnt; i += 4) { (void)*REBASE_FIFO(ep); } usbd_dev->rxbcnt = 0; } /* * There is no global interrupt flag for transmit complete. * The XFRC bit must be checked in each OTG_FS_DIEPINT(x). */ for (i = 0; i < 4; i++) { /* Iterate over endpoints. */ if (REBASE(OTG_DIEPINT(i)) & OTG_FS_DIEPINTX_XFRC) { /* Transfer complete. */ if (usbd_dev->user_callback_ctr[i] [USB_TRANSACTION_IN]) { usbd_dev->user_callback_ctr[i] [USB_TRANSACTION_IN](usbd_dev, i); } REBASE(OTG_DIEPINT(i)) = OTG_FS_DIEPINTX_XFRC; } } if (intsts & OTG_FS_GINTSTS_USBSUSP) { if (usbd_dev->user_callback_suspend) { usbd_dev->user_callback_suspend(); } REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_USBSUSP; } if (intsts & OTG_FS_GINTSTS_WKUPINT) { if (usbd_dev->user_callback_resume) { usbd_dev->user_callback_resume(); } REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_WKUPINT; } if (intsts & OTG_FS_GINTSTS_SOF) { if (usbd_dev->user_callback_sof) { usbd_dev->user_callback_sof(); } REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_SOF; } } void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected) { if (disconnected) { REBASE(OTG_DCTL) |= OTG_FS_DCTL_SDIS; } else { REBASE(OTG_DCTL) &= ~OTG_FS_DCTL_SDIS; } } hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_fx07_common.h000066400000000000000000000032651435536612600222140ustar00rootroot00000000000000/* * This file is part of the libopencm3 project. * * Copyright (C) 2011 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ #ifndef __USB_FX07_COMMON_H_ #define __USB_FX07_COMMON_H_ void stm32fx07_set_address(usbd_device *usbd_dev, uint8_t addr); void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*callback)(usbd_device *usbd_dev, uint8_t ep)); void stm32fx07_endpoints_reset(usbd_device *usbd_dev); void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall); uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr); void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak); uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len); uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len); void stm32fx07_poll(usbd_device *usbd_dev); void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected); #endif /* __USB_FX07_COMMON_H_ */ hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_private.h000066400000000000000000000115111435536612600215230ustar00rootroot00000000000000/** @defgroup usb_private_defines USB Private Structures @brief Defined Constants and Types for the USB Private Structures @ingroup USB_defines @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #ifndef __USB_PRIVATE_H #define __USB_PRIVATE_H #define MAX_USER_CONTROL_CALLBACK 4 #define MIN(a, b) ((a) < (b) ? (a) : (b)) /** Internal collection of device information. */ struct _usbd_device { const struct usb_device_descriptor *desc; const struct usb_config_descriptor *config; const char **strings; int num_strings; uint8_t *ctrl_buf; /**< Internal buffer used for control transfers */ uint16_t ctrl_buf_len; uint8_t current_address; uint8_t current_config; uint16_t pm_top; /**< Top of allocated endpoint buffer memory */ /* User callback functions for various USB events */ void (*user_callback_reset)(void); void (*user_callback_suspend)(void); void (*user_callback_resume)(void); void (*user_callback_sof)(void); struct usb_control_state { enum { IDLE, STALLED, DATA_IN, LAST_DATA_IN, STATUS_IN, DATA_OUT, LAST_DATA_OUT, STATUS_OUT, } state; struct usb_setup_data req __attribute__((aligned(4))); uint8_t *ctrl_buf; uint16_t ctrl_len; void (*complete)(usbd_device *usbd_dev, struct usb_setup_data *req); } control_state; struct user_control_callback { usbd_control_callback cb; uint8_t type; uint8_t type_mask; } user_control_callback[MAX_USER_CONTROL_CALLBACK]; void (*user_callback_ctr[8][3])(usbd_device *usbd_dev, uint8_t ea); /* User callback function for some standard USB function hooks */ void (*user_callback_set_config)(usbd_device *usbd_dev, uint16_t wValue); const struct _usbd_driver *driver; /* private driver data */ uint16_t fifo_mem_top; uint16_t fifo_mem_top_ep0; uint8_t force_nak[4]; /* * We keep a backup copy of the out endpoint size registers to restore * them after a transaction. */ uint32_t doeptsiz[4]; /* * Received packet size for each endpoint. This is assigned in * stm32f107_poll() which reads the packet status push register GRXSTSP * for use in stm32f107_ep_read_packet(). */ uint16_t rxbcnt; }; enum _usbd_transaction { USB_TRANSACTION_IN, USB_TRANSACTION_OUT, USB_TRANSACTION_SETUP, }; /* Do not appear to belong to the API, so are omitted from docs */ /**@}*/ void _usbd_control_in(usbd_device *usbd_dev, uint8_t ea); void _usbd_control_out(usbd_device *usbd_dev, uint8_t ea); void _usbd_control_setup(usbd_device *usbd_dev, uint8_t ea); int _usbd_standard_request_device(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len); int _usbd_standard_request_interface(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len); int _usbd_standard_request_endpoint(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len); int _usbd_standard_request(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len); void _usbd_reset(usbd_device *usbd_dev); /* Functions provided by the hardware abstraction. */ struct _usbd_driver { usbd_device *(*init)(void); void (*set_address)(usbd_device *usbd_dev, uint8_t addr); void (*ep_setup)(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, void (*cb)(usbd_device *usbd_dev, uint8_t ep)); void (*ep_reset)(usbd_device *usbd_dev); void (*ep_stall_set)(usbd_device *usbd_dev, uint8_t addr, uint8_t stall); void (*ep_nak_set)(usbd_device *usbd_dev, uint8_t addr, uint8_t nak); uint8_t (*ep_stall_get)(usbd_device *usbd_dev, uint8_t addr); uint16_t (*ep_write_packet)(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len); uint16_t (*ep_read_packet)(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len); void (*poll)(usbd_device *usbd_dev); void (*disconnect)(usbd_device *usbd_dev, bool disconnected); uint32_t base_address; bool set_address_before_status; uint16_t rx_fifo_size; }; #endif hackrf-0.0~git20230104.cfc2f34/lib/usb/usb_standard.c000066400000000000000000000276561435536612600216650ustar00rootroot00000000000000/** @defgroup usb_standard_file Generic USB Standard Request Interface @ingroup USB @brief Generic USB Standard Request Interface @version 1.0.0 @author @htmlonly © @endhtmlonly 2010 Gareth McMullin @date 10 March 2013 LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Gareth McMullin * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ /**@{*/ #include #include #include "usb_private.h" void usbd_register_set_config_callback(usbd_device *usbd_dev, void (*callback)(usbd_device *usbd_dev, uint16_t wValue)) { usbd_dev->user_callback_set_config = callback; } static uint16_t build_config_descriptor(usbd_device *usbd_dev, uint8_t index, uint8_t *buf, uint16_t len) { uint8_t *tmpbuf = buf; const struct usb_config_descriptor *cfg = &usbd_dev->config[index]; uint16_t count, total = 0, totallen = 0; uint16_t i, j, k; memcpy(buf, cfg, count = MIN(len, cfg->bLength)); buf += count; len -= count; total += count; totallen += cfg->bLength; /* For each interface... */ for (i = 0; i < cfg->bNumInterfaces; i++) { /* Interface Association Descriptor, if any */ if (cfg->interface[i].iface_assoc) { const struct usb_iface_assoc_descriptor *assoc = cfg->interface[i].iface_assoc; memcpy(buf, assoc, count = MIN(len, assoc->bLength)); buf += count; len -= count; total += count; totallen += assoc->bLength; } /* For each alternate setting... */ for (j = 0; j < cfg->interface[i].num_altsetting; j++) { const struct usb_interface_descriptor *iface = &cfg->interface[i].altsetting[j]; /* Copy interface descriptor. */ memcpy(buf, iface, count = MIN(len, iface->bLength)); buf += count; len -= count; total += count; totallen += iface->bLength; /* Copy extra bytes (function descriptors). */ memcpy(buf, iface->extra, count = MIN(len, iface->extralen)); buf += count; len -= count; total += count; totallen += iface->extralen; /* For each endpoint... */ for (k = 0; k < iface->bNumEndpoints; k++) { const struct usb_endpoint_descriptor *ep = &iface->endpoint[k]; memcpy(buf, ep, count = MIN(len, ep->bLength)); buf += count; len -= count; total += count; totallen += ep->bLength; } } } /* Fill in wTotalLength. */ *(uint16_t *)(tmpbuf + 2) = totallen; return total; } static int usb_descriptor_type(uint16_t wValue) { return wValue >> 8; } static int usb_descriptor_index(uint16_t wValue) { return wValue & 0xFF; } static int usb_standard_get_descriptor(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { int i, array_idx, descr_idx; struct usb_string_descriptor *sd; descr_idx = usb_descriptor_index(req->wValue); switch (usb_descriptor_type(req->wValue)) { case USB_DT_DEVICE: *buf = (uint8_t *) usbd_dev->desc; *len = MIN(*len, usbd_dev->desc->bLength); return USBD_REQ_HANDLED; case USB_DT_CONFIGURATION: *buf = usbd_dev->ctrl_buf; *len = build_config_descriptor(usbd_dev, descr_idx, *buf, *len); return USBD_REQ_HANDLED; case USB_DT_STRING: sd = (struct usb_string_descriptor *)usbd_dev->ctrl_buf; if (descr_idx == 0) { /* Send sane Language ID descriptor... */ sd->wData[0] = USB_LANGID_ENGLISH_US; sd->bLength = sizeof(sd->bLength) + sizeof(sd->bDescriptorType) + sizeof(sd->wData[0]); *len = MIN(*len, sd->bLength); } else { array_idx = descr_idx - 1; if (!usbd_dev->strings) { /* Device doesn't support strings. */ return USBD_REQ_NOTSUPP; } /* Check that string index is in range. */ if (array_idx >= usbd_dev->num_strings) { return USBD_REQ_NOTSUPP; } /* Strings with Language ID differnet from * USB_LANGID_ENGLISH_US are not supported */ if (req->wIndex != USB_LANGID_ENGLISH_US) { return USBD_REQ_NOTSUPP; } /* Ths string is returned as UTF16, hence the * multiplication */ sd->bLength = strlen(usbd_dev->strings[array_idx]) * 2 + sizeof(sd->bLength) + sizeof(sd->bDescriptorType); *len = MIN(*len, sd->bLength); for (i = 0; i < (*len / 2) - 1; i++) { sd->wData[i] = usbd_dev->strings[array_idx][i]; } } sd->bDescriptorType = USB_DT_STRING; *buf = (uint8_t *)sd; return USBD_REQ_HANDLED; } return USBD_REQ_NOTSUPP; } static int usb_standard_set_address(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)req; (void)buf; (void)len; /* The actual address is only latched at the STATUS IN stage. */ if ((req->bmRequestType != 0) || (req->wValue >= 128)) { return 0; } usbd_dev->current_address = req->wValue; /* * Special workaround for STM32F10[57] that require the address * to be set here. This is undocumented! */ if (usbd_dev->driver->set_address_before_status) { usbd_dev->driver->set_address(usbd_dev, req->wValue); } return 1; } static int usb_standard_set_configuration(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { int i; (void)req; (void)buf; (void)len; /* Is this correct, or should we reset alternate settings. */ if (req->wValue == usbd_dev->current_config) { return 1; } usbd_dev->current_config = req->wValue; /* Reset all endpoints. */ usbd_dev->driver->ep_reset(usbd_dev); if (usbd_dev->user_callback_set_config) { /* * Flush control callbacks. These will be reregistered * by the user handler. */ for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { usbd_dev->user_control_callback[i].cb = NULL; } usbd_dev->user_callback_set_config(usbd_dev, req->wValue); } return 1; } static int usb_standard_get_configuration(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)req; if (*len > 1) { *len = 1; } (*buf)[0] = usbd_dev->current_config; return 1; } static int usb_standard_set_interface(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)usbd_dev; (void)req; (void)buf; /* FIXME: Adapt if we have more than one interface. */ if (req->wValue != 0) { return 0; } *len = 0; return 1; } static int usb_standard_get_interface(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)usbd_dev; (void)req; (void)buf; /* FIXME: Adapt if we have more than one interface. */ *len = 1; (*buf)[0] = 0; return 1; } static int usb_standard_device_get_status(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)usbd_dev; (void)req; /* bit 0: self powered */ /* bit 1: remote wakeup */ if (*len > 2) { *len = 2; } (*buf)[0] = 0; (*buf)[1] = 0; return 1; } static int usb_standard_interface_get_status(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)usbd_dev; (void)req; /* not defined */ if (*len > 2) { *len = 2; } (*buf)[0] = 0; (*buf)[1] = 0; return 1; } static int usb_standard_endpoint_get_status(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)req; if (*len > 2) { *len = 2; } (*buf)[0] = usbd_ep_stall_get(usbd_dev, req->wIndex) ? 1 : 0; (*buf)[1] = 0; return 1; } static int usb_standard_endpoint_stall(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)buf; (void)len; usbd_ep_stall_set(usbd_dev, req->wIndex, 1); return 1; } static int usb_standard_endpoint_unstall(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { (void)buf; (void)len; usbd_ep_stall_set(usbd_dev, req->wIndex, 0); return 1; } /* Do not appear to belong to the API, so are omitted from docs */ /**@}*/ int _usbd_standard_request_device(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { int (*command)(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) = NULL; switch (req->bRequest) { case USB_REQ_CLEAR_FEATURE: case USB_REQ_SET_FEATURE: if (req->wValue == USB_FEAT_DEVICE_REMOTE_WAKEUP) { /* Device wakeup code goes here. */ } if (req->wValue == USB_FEAT_TEST_MODE) { /* Test mode code goes here. */ } break; case USB_REQ_SET_ADDRESS: /* * SET ADDRESS is an exception. * It is only processed at STATUS stage. */ command = usb_standard_set_address; break; case USB_REQ_SET_CONFIGURATION: command = usb_standard_set_configuration; break; case USB_REQ_GET_CONFIGURATION: command = usb_standard_get_configuration; break; case USB_REQ_GET_DESCRIPTOR: command = usb_standard_get_descriptor; break; case USB_REQ_GET_STATUS: /* * GET_STATUS always responds with zero reply. * The application may override this behaviour. */ command = usb_standard_device_get_status; break; case USB_REQ_SET_DESCRIPTOR: /* SET_DESCRIPTOR is optional and not implemented. */ break; } if (!command) { return 0; } return command(usbd_dev, req, buf, len); } int _usbd_standard_request_interface(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { int (*command)(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) = NULL; switch (req->bRequest) { case USB_REQ_CLEAR_FEATURE: case USB_REQ_SET_FEATURE: /* not defined */ break; case USB_REQ_GET_INTERFACE: command = usb_standard_get_interface; break; case USB_REQ_SET_INTERFACE: command = usb_standard_set_interface; break; case USB_REQ_GET_STATUS: command = usb_standard_interface_get_status; break; } if (!command) { return 0; } return command(usbd_dev, req, buf, len); } int _usbd_standard_request_endpoint(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { int (*command) (usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) = NULL; switch (req->bRequest) { case USB_REQ_CLEAR_FEATURE: if (req->wValue == USB_FEAT_ENDPOINT_HALT) { command = usb_standard_endpoint_unstall; } break; case USB_REQ_SET_FEATURE: if (req->wValue == USB_FEAT_ENDPOINT_HALT) { command = usb_standard_endpoint_stall; } break; case USB_REQ_GET_STATUS: command = usb_standard_endpoint_get_status; break; case USB_REQ_SET_SYNCH_FRAME: /* FIXME: SYNCH_FRAME is not implemented. */ /* * SYNCH_FRAME is used for synchronization of isochronous * endpoints which are not yet implemented. */ break; } if (!command) { return 0; } return command(usbd_dev, req, buf, len); } int _usbd_standard_request(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, uint16_t *len) { /* FIXME: Have class/vendor requests as well. */ if ((req->bmRequestType & USB_REQ_TYPE_TYPE) != USB_REQ_TYPE_STANDARD) { return 0; } switch (req->bmRequestType & USB_REQ_TYPE_RECIPIENT) { case USB_REQ_TYPE_DEVICE: return _usbd_standard_request_device(usbd_dev, req, buf, len); case USB_REQ_TYPE_INTERFACE: return _usbd_standard_request_interface(usbd_dev, req, buf, len); case USB_REQ_TYPE_ENDPOINT: return _usbd_standard_request_endpoint(usbd_dev, req, buf, len); default: return 0; } } hackrf-0.0~git20230104.cfc2f34/locm3.sublime-project000066400000000000000000000007461435536612600215430ustar00rootroot00000000000000{ "folders": [ { "path": ".", "file_exclude_patterns": [ "*.o", "*.a", "*.d", "*.sublime-project", "*.sublime-workspace", "*.swp" ], "folder_exclude_patterns": [ ] } ], "settings": { "tab_size": 8, "translate_tabs_to_spaces": false, "rulers": [80] }, "build_systems": [ { "name": "libopencm3", "working_dir": "${project_path}", "file_regex": "^(..[^:]*):([0-9]+):?([0-9]+)?:? (.*)$", "cmd": ["make"] } ] } hackrf-0.0~git20230104.cfc2f34/scripts/000077500000000000000000000000001435536612600171605ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/scripts/black_magic_probe_debug.scr000066400000000000000000000000571435536612600244440ustar00rootroot00000000000000monitor version monitor swdp_scan attach 1 run hackrf-0.0~git20230104.cfc2f34/scripts/black_magic_probe_flash.scr000066400000000000000000000000601435536612600244450ustar00rootroot00000000000000monitor version monitor swdp_scan attach 1 load hackrf-0.0~git20230104.cfc2f34/scripts/checkpatch.pl000077500000000000000000003123471435536612600216270ustar00rootroot00000000000000#!/usr/bin/perl -w # (c) 2001, Dave Jones. (the file handling bit) # (c) 2005, Joel Schopp (the ugly bit) # (c) 2007,2008, Andy Whitcroft (new conditions, test suite) # (c) 2008-2010 Andy Whitcroft # Licensed under the terms of the GNU GPL License version 2 use strict; my $P = $0; $P =~ s@.*/@@g; my $V = '0.32'; use Getopt::Long qw(:config no_auto_abbrev); my $quiet = 0; my $tree = 1; my $chk_signoff = 1; my $chk_patch = 1; my $tst_only; my $emacs = 0; my $terse = 0; my $file = 0; my $check = 0; my $summary = 1; my $mailback = 0; my $summary_file = 0; my $show_types = 0; my $root; my %debug; my %ignore_type = (); my @ignore = (); my $help = 0; my $configuration_file = ".checkpatch.conf"; my $max_line_length = 80; sub help { my ($exitcode) = @_; print << "EOM"; Usage: $P [OPTION]... [FILE]... Version: $V Options: -q, --quiet quiet --no-tree run without a kernel tree --no-signoff do not check for 'Signed-off-by' line --patch treat FILE as patchfile (default) --emacs emacs compile window format --terse one line per report -f, --file treat FILE as regular source file --subjective, --strict enable more subjective tests --ignore TYPE(,TYPE2...) ignore various comma separated message types --max-line-length=n set the maximum line length, if exceeded, warn --show-types show the message "types" in the output --root=PATH PATH to the kernel tree root --no-summary suppress the per-file summary --mailback only produce a report in case of warnings/errors --summary-file include the filename in summary --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of 'values', 'possible', 'type', and 'attr' (default is all off) --test-only=WORD report only warnings/errors containing WORD literally -h, --help, --version display this help and exit When FILE is - read standard input. EOM exit($exitcode); } my $conf = which_conf($configuration_file); if (-f $conf) { my @conf_args; open(my $conffile, '<', "$conf") or warn "$P: Can't find a readable $configuration_file file $!\n"; while (<$conffile>) { my $line = $_; $line =~ s/\s*\n?$//g; $line =~ s/^\s*//g; $line =~ s/\s+/ /g; next if ($line =~ m/^\s*#/); next if ($line =~ m/^\s*$/); my @words = split(" ", $line); foreach my $word (@words) { last if ($word =~ m/^#/); push (@conf_args, $word); } } close($conffile); unshift(@ARGV, @conf_args) if @conf_args; } GetOptions( 'q|quiet+' => \$quiet, 'tree!' => \$tree, 'signoff!' => \$chk_signoff, 'patch!' => \$chk_patch, 'emacs!' => \$emacs, 'terse!' => \$terse, 'f|file!' => \$file, 'subjective!' => \$check, 'strict!' => \$check, 'ignore=s' => \@ignore, 'show-types!' => \$show_types, 'max-line-length=i' => \$max_line_length, 'root=s' => \$root, 'summary!' => \$summary, 'mailback!' => \$mailback, 'summary-file!' => \$summary_file, 'debug=s' => \%debug, 'test-only=s' => \$tst_only, 'h|help' => \$help, 'version' => \$help ) or help(1); help(0) if ($help); my $exit = 0; if ($#ARGV < 0) { print "$P: no input files\n"; exit(1); } @ignore = split(/,/, join(',',@ignore)); foreach my $word (@ignore) { $word =~ s/\s*\n?$//g; $word =~ s/^\s*//g; $word =~ s/\s+/ /g; $word =~ tr/[a-z]/[A-Z]/; next if ($word =~ m/^\s*#/); next if ($word =~ m/^\s*$/); $ignore_type{$word}++; } my $dbg_values = 0; my $dbg_possible = 0; my $dbg_type = 0; my $dbg_attr = 0; for my $key (keys %debug) { ## no critic eval "\${dbg_$key} = '$debug{$key}';"; die "$@" if ($@); } my $rpt_cleaners = 0; if ($terse) { $emacs = 1; $quiet++; } if ($tree) { if (defined $root) { if (!top_of_kernel_tree($root)) { die "$P: $root: --root does not point at a valid tree\n"; } } else { if (top_of_kernel_tree('.')) { $root = '.'; } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && top_of_kernel_tree($1)) { $root = $1; } } if (!defined $root) { print "Must be run from the top-level dir. of a kernel tree\n"; exit(2); } } my $emitted_corrupt = 0; our $Ident = qr{ [A-Za-z_][A-Za-z\d_]* (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* }x; our $Storage = qr{extern|static|asmlinkage}; our $Sparse = qr{ __user| __kernel| __force| __iomem| __must_check| __init_refok| __kprobes| __ref| __rcu }x; # Notes to $Attribute: # We need \b after 'init' otherwise 'initconst' will cause a false positive in a check our $Attribute = qr{ const| __percpu| __nocast| __safe| __bitwise__| __packed__| __packed2__| __naked| __maybe_unused| __always_unused| __noreturn| __used| __cold| __noclone| __deprecated| __read_mostly| __kprobes| __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)| ____cacheline_aligned| ____cacheline_aligned_in_smp| ____cacheline_internodealigned_in_smp| __weak }x; our $Modifier; our $Inline = qr{inline|__always_inline|noinline}; our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; our $Lval = qr{$Ident(?:$Member)*}; our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; our $Float = qr{$Float_hex|$Float_dec|$Float_int}; our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*}; our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; our $Compare = qr{<=|>=|==|!=|<|>}; our $Operators = qr{ <=|>=|==|!=| =>|->|<<|>>|<|>|!|~| &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|% }x; our $NonptrType; our $Type; our $Declare; our $NON_ASCII_UTF8 = qr{ [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 }x; our $UTF8 = qr{ [\x09\x0A\x0D\x20-\x7E] # ASCII | $NON_ASCII_UTF8 }x; our $typeTypedefs = qr{(?x: (?:__)?(?:u|s|be|le)(?:8|16|32|64)| atomic_t )}; our $logFunctions = qr{(?x: printk(?:_ratelimited|_once|)| [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| WARN(?:_RATELIMIT|_ONCE|)| panic| MODULE_[A-Z_]+ )}; our $signature_tags = qr{(?xi: Signed-off-by:| Acked-by:| Tested-by:| Reviewed-by:| Reported-by:| Suggested-by:| To:| Cc: )}; our @typeList = ( qr{void}, qr{(?:unsigned\s+)?char}, qr{(?:unsigned\s+)?short}, qr{(?:unsigned\s+)?int}, qr{(?:unsigned\s+)?long}, qr{(?:unsigned\s+)?long\s+int}, qr{(?:unsigned\s+)?long\s+long}, qr{(?:unsigned\s+)?long\s+long\s+int}, qr{unsigned}, qr{float}, qr{double}, qr{bool}, qr{struct\s+$Ident}, qr{union\s+$Ident}, qr{enum\s+$Ident}, qr{${Ident}_t}, qr{${Ident}_handler}, qr{${Ident}_handler_fn}, ); our @modifierList = ( qr{fastcall}, ); our $allowed_asm_includes = qr{(?x: irq| memory )}; # memory.h: ARM has a custom one sub build_types { my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; $NonptrType = qr{ (?:$Modifier\s+|const\s+)* (?: (?:typeof|__typeof__)\s*\([^\)]*\)| (?:$typeTypedefs\b)| (?:${all}\b) ) (?:\s+$Modifier|\s+const)* }x; $Type = qr{ $NonptrType (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)? (?:\s+$Inline|\s+$Modifier)* }x; $Declare = qr{(?:$Storage\s+)?$Type}; } build_types(); our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; # Using $balanced_parens, $LvalOrFunc, or $FuncArg # requires at least perl version v5.10.0 # Any use must be runtime checked with $^V our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*}; our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)}; sub deparenthesize { my ($string) = @_; return "" if (!defined($string)); $string =~ s@^\s*\(\s*@@g; $string =~ s@\s*\)\s*$@@g; $string =~ s@\s+@ @g; return $string; } $chk_signoff = 0 if ($file); my @rawlines = (); my @lines = (); my $vname; for my $filename (@ARGV) { my $FILE; if ($file) { open($FILE, '-|', "diff -u /dev/null $filename") || die "$P: $filename: diff failed - $!\n"; } elsif ($filename eq '-') { open($FILE, '<&STDIN'); } else { open($FILE, '<', "$filename") || die "$P: $filename: open failed - $!\n"; } if ($filename eq '-') { $vname = 'Your patch'; } else { $vname = $filename; } while (<$FILE>) { chomp; push(@rawlines, $_); } close($FILE); if (!process($filename)) { $exit = 1; } @rawlines = (); @lines = (); } exit($exit); sub top_of_kernel_tree { my ($root) = @_; my @tree_check = ( "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", "README", "Documentation", "arch", "include", "drivers", "fs", "init", "ipc", "kernel", "lib", "scripts", ); foreach my $check (@tree_check) { if (! -e $root . '/' . $check) { return 0; } } return 1; } sub parse_email { my ($formatted_email) = @_; my $name = ""; my $address = ""; my $comment = ""; if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) { $name = $1; $address = $2; $comment = $3 if defined $3; } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) { $address = $1; $comment = $2 if defined $2; } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { $address = $1; $comment = $2 if defined $2; $formatted_email =~ s/$address.*$//; $name = $formatted_email; $name =~ s/^\s+|\s+$//g; $name =~ s/^\"|\"$//g; # If there's a name left after stripping spaces and # leading quotes, and the address doesn't have both # leading and trailing angle brackets, the address # is invalid. ie: # "joe smith joe@smith.com" bad # "joe smith ]+>$/) { $name = ""; $address = ""; $comment = ""; } } $name =~ s/^\s+|\s+$//g; $name =~ s/^\"|\"$//g; $address =~ s/^\s+|\s+$//g; $address =~ s/^\<|\>$//g; if ($name =~ /[^\w \-]/i) { ##has "must quote" chars $name =~ s/(?"; } return $formatted_email; } sub which_conf { my ($conf) = @_; foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { if (-e "$path/$conf") { return "$path/$conf"; } } return ""; } sub expand_tabs { my ($str) = @_; my $res = ''; my $n = 0; for my $c (split(//, $str)) { if ($c eq "\t") { $res .= ' '; $n++; for (; ($n % 8) != 0; $n++) { $res .= ' '; } next; } $res .= $c; $n++; } return $res; } sub copy_spacing { (my $res = shift) =~ tr/\t/ /c; return $res; } sub line_stats { my ($line) = @_; # Drop the diff line leader and expand tabs $line =~ s/^.//; $line = expand_tabs($line); # Pick the indent from the front of the line. my ($white) = ($line =~ /^(\s*)/); return (length($line), length($white)); } my $sanitise_quote = ''; sub sanitise_line_reset { my ($in_comment) = @_; if ($in_comment) { $sanitise_quote = '*/'; } else { $sanitise_quote = ''; } } sub sanitise_line { my ($line) = @_; my $res = ''; my $l = ''; my $qlen = 0; my $off = 0; my $c; # Always copy over the diff marker. $res = substr($line, 0, 1); for ($off = 1; $off < length($line); $off++) { $c = substr($line, $off, 1); # Comments we are wacking completly including the begin # and end, all to $;. if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { $sanitise_quote = '*/'; substr($res, $off, 2, "$;$;"); $off++; next; } if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { $sanitise_quote = ''; substr($res, $off, 2, "$;$;"); $off++; next; } if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { $sanitise_quote = '//'; substr($res, $off, 2, $sanitise_quote); $off++; next; } # A \ in a string means ignore the next character. if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && $c eq "\\") { substr($res, $off, 2, 'XX'); $off++; next; } # Regular quotes. if ($c eq "'" || $c eq '"') { if ($sanitise_quote eq '') { $sanitise_quote = $c; substr($res, $off, 1, $c); next; } elsif ($sanitise_quote eq $c) { $sanitise_quote = ''; } } #print "c<$c> SQ<$sanitise_quote>\n"; if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { substr($res, $off, 1, $;); } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { substr($res, $off, 1, $;); } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { substr($res, $off, 1, 'X'); } else { substr($res, $off, 1, $c); } } if ($sanitise_quote eq '//') { $sanitise_quote = ''; } # The pathname on a #include may be surrounded by '<' and '>'. if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { my $clean = 'X' x length($1); $res =~ s@\<.*\>@<$clean>@; # The whole of a #error is a string. } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { my $clean = 'X' x length($1); $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; } return $res; } sub get_quoted_string { my ($line, $rawline) = @_; return "" if ($line !~ m/(\"[X]+\")/g); return substr($rawline, $-[0], $+[0] - $-[0]); } sub ctx_statement_block { my ($linenr, $remain, $off) = @_; my $line = $linenr - 1; my $blk = ''; my $soff = $off; my $coff = $off - 1; my $coff_set = 0; my $loff = 0; my $type = ''; my $level = 0; my @stack = (); my $p; my $c; my $len = 0; my $remainder; while (1) { @stack = (['', 0]) if ($#stack == -1); #warn "CSB: blk<$blk> remain<$remain>\n"; # If we are about to drop off the end, pull in more # context. if ($off >= $len) { for (; $remain > 0; $line++) { last if (!defined $lines[$line]); next if ($lines[$line] =~ /^-/); $remain--; $loff = $len; $blk .= $lines[$line] . "\n"; $len = length($blk); $line++; last; } # Bail if there is no further context. #warn "CSB: blk<$blk> off<$off> len<$len>\n"; if ($off >= $len) { last; } if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { $level++; $type = '#'; } } $p = $c; $c = substr($blk, $off, 1); $remainder = substr($blk, $off); #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; # Handle nested #if/#else. if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { push(@stack, [ $type, $level ]); } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { ($type, $level) = @{$stack[$#stack - 1]}; } elsif ($remainder =~ /^#\s*endif\b/) { ($type, $level) = @{pop(@stack)}; } # Statement ends at the ';' or a close '}' at the # outermost level. if ($level == 0 && $c eq ';') { last; } # An else is really a conditional as long as its not else if if ($level == 0 && $coff_set == 0 && (!defined($p) || $p =~ /(?:\s|\}|\+)/) && $remainder =~ /^(else)(?:\s|{)/ && $remainder !~ /^else\s+if\b/) { $coff = $off + length($1) - 1; $coff_set = 1; #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; } if (($type eq '' || $type eq '(') && $c eq '(') { $level++; $type = '('; } if ($type eq '(' && $c eq ')') { $level--; $type = ($level != 0)? '(' : ''; if ($level == 0 && $coff < $soff) { $coff = $off; $coff_set = 1; #warn "CSB: mark coff<$coff>\n"; } } if (($type eq '' || $type eq '{') && $c eq '{') { $level++; $type = '{'; } if ($type eq '{' && $c eq '}') { $level--; $type = ($level != 0)? '{' : ''; if ($level == 0) { if (substr($blk, $off + 1, 1) eq ';') { $off++; } last; } } # Preprocessor commands end at the newline unless escaped. if ($type eq '#' && $c eq "\n" && $p ne "\\") { $level--; $type = ''; $off++; last; } $off++; } # We are truly at the end, so shuffle to the next line. if ($off == $len) { $loff = $len + 1; $line++; $remain--; } my $statement = substr($blk, $soff, $off - $soff + 1); my $condition = substr($blk, $soff, $coff - $soff + 1); #warn "STATEMENT<$statement>\n"; #warn "CONDITION<$condition>\n"; #print "coff<$coff> soff<$off> loff<$loff>\n"; return ($statement, $condition, $line, $remain + 1, $off - $loff + 1, $level); } sub statement_lines { my ($stmt) = @_; # Strip the diff line prefixes and rip blank lines at start and end. $stmt =~ s/(^|\n)./$1/g; $stmt =~ s/^\s*//; $stmt =~ s/\s*$//; my @stmt_lines = ($stmt =~ /\n/g); return $#stmt_lines + 2; } sub statement_rawlines { my ($stmt) = @_; my @stmt_lines = ($stmt =~ /\n/g); return $#stmt_lines + 2; } sub statement_block_size { my ($stmt) = @_; $stmt =~ s/(^|\n)./$1/g; $stmt =~ s/^\s*{//; $stmt =~ s/}\s*$//; $stmt =~ s/^\s*//; $stmt =~ s/\s*$//; my @stmt_lines = ($stmt =~ /\n/g); my @stmt_statements = ($stmt =~ /;/g); my $stmt_lines = $#stmt_lines + 2; my $stmt_statements = $#stmt_statements + 1; if ($stmt_lines > $stmt_statements) { return $stmt_lines; } else { return $stmt_statements; } } sub ctx_statement_full { my ($linenr, $remain, $off) = @_; my ($statement, $condition, $level); my (@chunks); # Grab the first conditional/block pair. ($statement, $condition, $linenr, $remain, $off, $level) = ctx_statement_block($linenr, $remain, $off); #print "F: c<$condition> s<$statement> remain<$remain>\n"; push(@chunks, [ $condition, $statement ]); if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { return ($level, $linenr, @chunks); } # Pull in the following conditional/block pairs and see if they # could continue the statement. for (;;) { ($statement, $condition, $linenr, $remain, $off, $level) = ctx_statement_block($linenr, $remain, $off); #print "C: c<$condition> s<$statement> remain<$remain>\n"; last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); #print "C: push\n"; push(@chunks, [ $condition, $statement ]); } return ($level, $linenr, @chunks); } sub ctx_block_get { my ($linenr, $remain, $outer, $open, $close, $off) = @_; my $line; my $start = $linenr - 1; my $blk = ''; my @o; my @c; my @res = (); my $level = 0; my @stack = ($level); for ($line = $start; $remain > 0; $line++) { next if ($rawlines[$line] =~ /^-/); $remain--; $blk .= $rawlines[$line]; # Handle nested #if/#else. if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { push(@stack, $level); } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { $level = $stack[$#stack - 1]; } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { $level = pop(@stack); } foreach my $c (split(//, $lines[$line])) { ##print "C<$c>L<$level><$open$close>O<$off>\n"; if ($off > 0) { $off--; next; } if ($c eq $close && $level > 0) { $level--; last if ($level == 0); } elsif ($c eq $open) { $level++; } } if (!$outer || $level <= 1) { push(@res, $rawlines[$line]); } last if ($level == 0); } return ($level, @res); } sub ctx_block_outer { my ($linenr, $remain) = @_; my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); return @r; } sub ctx_block { my ($linenr, $remain) = @_; my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); return @r; } sub ctx_statement { my ($linenr, $remain, $off) = @_; my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); return @r; } sub ctx_block_level { my ($linenr, $remain) = @_; return ctx_block_get($linenr, $remain, 0, '{', '}', 0); } sub ctx_statement_level { my ($linenr, $remain, $off) = @_; return ctx_block_get($linenr, $remain, 0, '(', ')', $off); } sub ctx_locate_comment { my ($first_line, $end_line) = @_; # Catch a comment on the end of the line itself. my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); return $current_comment if (defined $current_comment); # Look through the context and try and figure out if there is a # comment. my $in_comment = 0; $current_comment = ''; for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { my $line = $rawlines[$linenr - 1]; #warn " $line\n"; if ($linenr == $first_line and $line =~ m@^.\s*\*@) { $in_comment = 1; } if ($line =~ m@/\*@) { $in_comment = 1; } if (!$in_comment && $current_comment ne '') { $current_comment = ''; } $current_comment .= $line . "\n" if ($in_comment); if ($line =~ m@\*/@) { $in_comment = 0; } } chomp($current_comment); return($current_comment); } sub ctx_has_comment { my ($first_line, $end_line) = @_; my $cmt = ctx_locate_comment($first_line, $end_line); ##print "LINE: $rawlines[$end_line - 1 ]\n"; ##print "CMMT: $cmt\n"; return ($cmt ne ''); } sub raw_line { my ($linenr, $cnt) = @_; my $offset = $linenr - 1; $cnt++; my $line; while ($cnt) { $line = $rawlines[$offset++]; next if (defined($line) && $line =~ /^-/); $cnt--; } return $line; } sub cat_vet { my ($vet) = @_; my ($res, $coded); $res = ''; while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { $res .= $1; if ($2 ne '') { $coded = sprintf("^%c", unpack('C', $2) + 64); $res .= $coded; } } $res =~ s/$/\$/; return $res; } my $av_preprocessor = 0; my $av_pending; my @av_paren_type; my $av_pend_colon; sub annotate_reset { $av_preprocessor = 0; $av_pending = '_'; @av_paren_type = ('E'); $av_pend_colon = 'O'; } sub annotate_values { my ($stream, $type) = @_; my $res; my $var = '_' x length($stream); my $cur = $stream; print "$stream\n" if ($dbg_values > 1); while (length($cur)) { @av_paren_type = ('E') if ($#av_paren_type < 0); print " <" . join('', @av_paren_type) . "> <$type> <$av_pending>" if ($dbg_values > 1); if ($cur =~ /^(\s+)/o) { print "WS($1)\n" if ($dbg_values > 1); if ($1 =~ /\n/ && $av_preprocessor) { $type = pop(@av_paren_type); $av_preprocessor = 0; } } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { print "CAST($1)\n" if ($dbg_values > 1); push(@av_paren_type, $type); $type = 'c'; } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { print "DECLARE($1)\n" if ($dbg_values > 1); $type = 'T'; } elsif ($cur =~ /^($Modifier)\s*/) { print "MODIFIER($1)\n" if ($dbg_values > 1); $type = 'T'; } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { print "DEFINE($1,$2)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $type); if ($2 ne '') { $av_pending = 'N'; } $type = 'E'; } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { print "UNDEF($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $type); } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { print "PRE_START($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $type); push(@av_paren_type, $type); $type = 'E'; } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { print "PRE_RESTART($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; push(@av_paren_type, $av_paren_type[$#av_paren_type]); $type = 'E'; } elsif ($cur =~ /^(\#\s*(?:endif))/o) { print "PRE_END($1)\n" if ($dbg_values > 1); $av_preprocessor = 1; # Assume all arms of the conditional end as this # one does, and continue as if the #endif was not here. pop(@av_paren_type); push(@av_paren_type, $type); $type = 'E'; } elsif ($cur =~ /^(\\\n)/o) { print "PRECONT($1)\n" if ($dbg_values > 1); } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { print "ATTR($1)\n" if ($dbg_values > 1); $av_pending = $type; $type = 'N'; } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { print "SIZEOF($1)\n" if ($dbg_values > 1); if (defined $2) { $av_pending = 'V'; } $type = 'N'; } elsif ($cur =~ /^(if|while|for)\b/o) { print "COND($1)\n" if ($dbg_values > 1); $av_pending = 'E'; $type = 'N'; } elsif ($cur =~/^(case)/o) { print "CASE($1)\n" if ($dbg_values > 1); $av_pend_colon = 'C'; $type = 'N'; } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { print "KEYWORD($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~ /^(\()/o) { print "PAREN('$1')\n" if ($dbg_values > 1); push(@av_paren_type, $av_pending); $av_pending = '_'; $type = 'N'; } elsif ($cur =~ /^(\))/o) { my $new_type = pop(@av_paren_type); if ($new_type ne '_') { $type = $new_type; print "PAREN('$1') -> $type\n" if ($dbg_values > 1); } else { print "PAREN('$1')\n" if ($dbg_values > 1); } } elsif ($cur =~ /^($Ident)\s*\(/o) { print "FUNC($1)\n" if ($dbg_values > 1); $type = 'V'; $av_pending = 'V'; } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { if (defined $2 && $type eq 'C' || $type eq 'T') { $av_pend_colon = 'B'; } elsif ($type eq 'E') { $av_pend_colon = 'L'; } print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); $type = 'V'; } elsif ($cur =~ /^($Ident|$Constant)/o) { print "IDENT($1)\n" if ($dbg_values > 1); $type = 'V'; } elsif ($cur =~ /^($Assignment)/o) { print "ASSIGN($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~/^(;|{|})/) { print "END($1)\n" if ($dbg_values > 1); $type = 'E'; $av_pend_colon = 'O'; } elsif ($cur =~/^(,)/) { print "COMMA($1)\n" if ($dbg_values > 1); $type = 'C'; } elsif ($cur =~ /^(\?)/o) { print "QUESTION($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~ /^(:)/o) { print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); substr($var, length($res), 1, $av_pend_colon); if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { $type = 'E'; } else { $type = 'N'; } $av_pend_colon = 'O'; } elsif ($cur =~ /^(\[)/o) { print "CLOSE($1)\n" if ($dbg_values > 1); $type = 'N'; } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { my $variant; print "OPV($1)\n" if ($dbg_values > 1); if ($type eq 'V') { $variant = 'B'; } else { $variant = 'U'; } substr($var, length($res), 1, $variant); $type = 'N'; } elsif ($cur =~ /^($Operators)/o) { print "OP($1)\n" if ($dbg_values > 1); if ($1 ne '++' && $1 ne '--') { $type = 'N'; } } elsif ($cur =~ /(^.)/o) { print "C($1)\n" if ($dbg_values > 1); } if (defined $1) { $cur = substr($cur, length($1)); $res .= $type x length($1); } } return ($res, $var); } sub possible { my ($possible, $line) = @_; my $notPermitted = qr{(?: ^(?: $Modifier| $Storage| $Type| DEFINE_\S+ )$| ^(?: goto| return| case| else| asm|__asm__| do| \#| \#\#| )(?:\s|$)| ^(?:typedef|struct|enum)\b )}x; warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); if ($possible !~ $notPermitted) { # Check for modifiers. $possible =~ s/\s*$Storage\s*//g; $possible =~ s/\s*$Sparse\s*//g; if ($possible =~ /^\s*$/) { } elsif ($possible =~ /\s/) { $possible =~ s/\s*$Type\s*//g; for my $modifier (split(' ', $possible)) { if ($modifier !~ $notPermitted) { warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); push(@modifierList, $modifier); } } } else { warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); push(@typeList, $possible); } build_types(); } else { warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); } } my $prefix = ''; sub show_type { return !defined $ignore_type{$_[0]}; } sub report { if (!show_type($_[1]) || (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) { return 0; } my $line; if ($show_types) { $line = "$prefix$_[0]:$_[1]: $_[2]\n"; } else { $line = "$prefix$_[0]: $_[2]\n"; } $line = (split('\n', $line))[0] . "\n" if ($terse); push(our @report, $line); return 1; } sub report_dump { our @report; } sub ERROR { if (report("ERROR", $_[0], $_[1])) { our $clean = 0; our $cnt_error++; } } sub WARN { if (report("WARNING", $_[0], $_[1])) { our $clean = 0; our $cnt_warn++; } } sub CHK { if ($check && report("CHECK", $_[0], $_[1])) { our $clean = 0; our $cnt_chk++; } } sub check_absolute_file { my ($absolute, $herecurr) = @_; my $file = $absolute; ##print "absolute<$absolute>\n"; # See if any suffix of this path is a path within the tree. while ($file =~ s@^[^/]*/@@) { if (-f "$root/$file") { ##print "file<$file>\n"; last; } } if (! -f _) { return 0; } # It is, so see if the prefix is acceptable. my $prefix = $absolute; substr($prefix, -length($file)) = ''; ##print "prefix<$prefix>\n"; if ($prefix ne ".../") { WARN("USE_RELATIVE_PATH", "use relative pathname instead of absolute in changelog text\n" . $herecurr); } } sub pos_last_openparen { my ($line) = @_; my $pos = 0; my $opens = $line =~ tr/\(/\(/; my $closes = $line =~ tr/\)/\)/; my $last_openparen = 0; if (($opens == 0) || ($closes >= $opens)) { return -1; } my $len = length($line); for ($pos = 0; $pos < $len; $pos++) { my $string = substr($line, $pos); if ($string =~ /^($FuncArg|$balanced_parens)/) { $pos += length($1) - 1; } elsif (substr($line, $pos, 1) eq '(') { $last_openparen = $pos; } elsif (index($string, '(') == -1) { last; } } return $last_openparen + 1; } sub process { my $filename = shift; my $linenr=0; my $prevline=""; my $prevrawline=""; my $stashline=""; my $stashrawline=""; my $length; my $indent; my $previndent=0; my $stashindent=0; our $clean = 1; my $signoff = 0; my $is_patch = 0; my $in_header_lines = 1; my $in_commit_log = 0; #Scanning lines before patch my $non_utf8_charset = 0; our @report = (); our $cnt_lines = 0; our $cnt_error = 0; our $cnt_warn = 0; our $cnt_chk = 0; # Trace the real file/line as we go. my $realfile = ''; my $realline = 0; my $realcnt = 0; my $here = ''; my $in_comment = 0; my $comment_edge = 0; my $first_line = 0; my $p1_prefix = ''; my $prev_values = 'E'; # suppression flags my %suppress_ifbraces; my %suppress_whiletrailers; my %suppress_export; my $suppress_statement = 0; my %camelcase = (); # Pre-scan the patch sanitizing the lines. # Pre-scan the patch looking for any __setup documentation. # my @setup_docs = (); my $setup_docs = 0; sanitise_line_reset(); my $line; foreach my $rawline (@rawlines) { $linenr++; $line = $rawline; if ($rawline=~/^\+\+\+\s+(\S+)/) { $setup_docs = 0; if ($1 =~ m@Documentation/kernel-parameters.txt$@) { $setup_docs = 1; } #next; } if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { $realline=$1-1; if (defined $2) { $realcnt=$3+1; } else { $realcnt=1+1; } $in_comment = 0; # Guestimate if this is a continuing comment. Run # the context looking for a comment "edge". If this # edge is a close comment then we must be in a comment # at context start. my $edge; my $cnt = $realcnt; for (my $ln = $linenr + 1; $cnt > 0; $ln++) { next if (defined $rawlines[$ln - 1] && $rawlines[$ln - 1] =~ /^-/); $cnt--; #print "RAW<$rawlines[$ln - 1]>\n"; last if (!defined $rawlines[$ln - 1]); if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { ($edge) = $1; last; } } if (defined $edge && $edge eq '*/') { $in_comment = 1; } # Guestimate if this is a continuing comment. If this # is the start of a diff block and this line starts # ' *' then it is very likely a comment. if (!defined $edge && $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) { $in_comment = 1; } ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; sanitise_line_reset($in_comment); } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { # Standardise the strings and chars within the input to # simplify matching -- only bother with positive lines. $line = sanitise_line($rawline); } push(@lines, $line); if ($realcnt > 1) { $realcnt-- if ($line =~ /^(?:\+| |$)/); } else { $realcnt = 0; } #print "==>$rawline\n"; #print "-->$line\n"; if ($setup_docs && $line =~ /^\+/) { push(@setup_docs, $line); } } $prefix = ''; $realcnt = 0; $linenr = 0; foreach my $line (@lines) { $linenr++; my $rawline = $rawlines[$linenr - 1]; #extract the line range in the file after the patch is applied if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { $is_patch = 1; $first_line = $linenr + 1; $realline=$1-1; if (defined $2) { $realcnt=$3+1; } else { $realcnt=1+1; } annotate_reset(); $prev_values = 'E'; %suppress_ifbraces = (); %suppress_whiletrailers = (); %suppress_export = (); $suppress_statement = 0; next; # track the line number as we move through the hunk, note that # new versions of GNU diff omit the leading space on completely # blank context lines so we need to count that too. } elsif ($line =~ /^( |\+|$)/) { $realline++; $realcnt-- if ($realcnt != 0); # Measure the line length and indent. ($length, $indent) = line_stats($rawline); # Track the previous line. ($prevline, $stashline) = ($stashline, $line); ($previndent, $stashindent) = ($stashindent, $indent); ($prevrawline, $stashrawline) = ($stashrawline, $rawline); #warn "line<$line>\n"; } elsif ($realcnt == 1) { $realcnt--; } my $hunk_line = ($realcnt != 0); #make up the handle for any error we report on this line $prefix = "$filename:$realline: " if ($emacs && $file); $prefix = "$filename:$linenr: " if ($emacs && !$file); $here = "#$linenr: " if (!$file); $here = "#$realline: " if ($file); # extract the filename as it passes if ($line =~ /^diff --git.*?(\S+)$/) { $realfile = $1; $realfile =~ s@^([^/]*)/@@; $in_commit_log = 0; } elsif ($line =~ /^\+\+\+\s+(\S+)/) { $realfile = $1; $realfile =~ s@^([^/]*)/@@; $in_commit_log = 0; $p1_prefix = $1; if (!$file && $tree && $p1_prefix ne '' && -e "$root/$p1_prefix") { WARN("PATCH_PREFIX", "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); } if ($realfile =~ m@^include/asm/@) { ERROR("MODIFIED_INCLUDE_ASM", "do not modify files in include/asm, change architecture specific files in include/asm-\n" . "$here$rawline\n"); } next; } $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); my $hereline = "$here\n$rawline\n"; my $herecurr = "$here\n$rawline\n"; my $hereprev = "$here\n$prevrawline\n$rawline\n"; $cnt_lines++ if ($realcnt != 0); # Check for incorrect file permissions if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { my $permhere = $here . "FILE: $realfile\n"; if ($realfile !~ m@scripts/@ && $realfile !~ /\.(py|pl|awk|sh)$/) { ERROR("EXECUTE_PERMISSIONS", "do not set execute permissions for source files\n" . $permhere); } } # Check the patch for a signoff: if ($line =~ /^\s*signed-off-by:/i) { $signoff++; $in_commit_log = 0; } # Check signature styles if (!$in_header_lines && $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { my $space_before = $1; my $sign_off = $2; my $space_after = $3; my $email = $4; my $ucfirst_sign_off = ucfirst(lc($sign_off)); if ($sign_off !~ /$signature_tags/) { WARN("BAD_SIGN_OFF", "Non-standard signature: $sign_off\n" . $herecurr); } if (defined $space_before && $space_before ne "") { WARN("BAD_SIGN_OFF", "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr); } if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { WARN("BAD_SIGN_OFF", "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr); } if (!defined $space_after || $space_after ne " ") { WARN("BAD_SIGN_OFF", "Use a single space after $ucfirst_sign_off\n" . $herecurr); } my ($email_name, $email_address, $comment) = parse_email($email); my $suggested_email = format_email(($email_name, $email_address)); if ($suggested_email eq "") { ERROR("BAD_SIGN_OFF", "Unrecognized email address: '$email'\n" . $herecurr); } else { my $dequoted = $suggested_email; $dequoted =~ s/^"//; $dequoted =~ s/" $comment" ne $email && "$suggested_email$comment" ne $email) { WARN("BAD_SIGN_OFF", "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); } } } # Check for wrappage within a valid hunk of the file if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { ERROR("CORRUPTED_PATCH", "patch seems to be corrupt (line wrapped?)\n" . $herecurr) if (!$emitted_corrupt++); } # Check for absolute kernel paths. if ($tree) { while ($line =~ m{(?:^|\s)(/\S*)}g) { my $file = $1; if ($file =~ m{^(.*?)(?::\d+)+:?$} && check_absolute_file($1, $herecurr)) { # } else { check_absolute_file($file, $herecurr); } } } # UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php if (($realfile =~ /^$/ || $line =~ /^\+/) && $rawline !~ m/^$UTF8*$/) { my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); my $blank = copy_spacing($rawline); my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; my $hereptr = "$hereline$ptr\n"; CHK("INVALID_UTF8", "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); } # Check if it's the start of a commit log # (not a header line and we haven't seen the patch filename) if ($in_header_lines && $realfile =~ /^$/ && $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) { $in_header_lines = 0; $in_commit_log = 1; } # Check if there is UTF-8 in a commit log when a mail header has explicitly # declined it, i.e defined some charset where it is missing. if ($in_header_lines && $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && $1 !~ /utf-8/i) { $non_utf8_charset = 1; } if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && $rawline =~ /$NON_ASCII_UTF8/) { WARN("UTF8_BEFORE_PATCH", "8-bit UTF-8 used in possible commit log\n" . $herecurr); } # ignore non-hunk lines and lines being removed next if (!$hunk_line || $line =~ /^-/); #trailing whitespace if ($line =~ /^\+.*\015/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; ERROR("DOS_LINE_ENDINGS", "DOS line endings\n" . $herevet); } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; ERROR("TRAILING_WHITESPACE", "trailing whitespace\n" . $herevet); $rpt_cleaners = 1; } # check for Kconfig help text having a real description # Only applies when adding the entry originally, after that we do not have # sufficient context to determine whether it is indeed long enough. if ($realfile =~ /Kconfig/ && $line =~ /.\s*config\s+/) { my $length = 0; my $cnt = $realcnt; my $ln = $linenr + 1; my $f; my $is_start = 0; my $is_end = 0; for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { $f = $lines[$ln - 1]; $cnt-- if ($lines[$ln - 1] !~ /^-/); $is_end = $lines[$ln - 1] =~ /^\+/; next if ($f =~ /^-/); if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) { $is_start = 1; } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) { $length = -1; } $f =~ s/^.//; $f =~ s/#.*//; $f =~ s/^\s+//; next if ($f =~ /^$/); if ($f =~ /^\s*config\s/) { $is_end = 1; last; } $length++; } WARN("CONFIG_DESCRIPTION", "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4); #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; } # discourage the addition of CONFIG_EXPERIMENTAL in Kconfig. if ($realfile =~ /Kconfig/ && $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) { WARN("CONFIG_EXPERIMENTAL", "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); } if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { my $flag = $1; my $replacement = { 'EXTRA_AFLAGS' => 'asflags-y', 'EXTRA_CFLAGS' => 'ccflags-y', 'EXTRA_CPPFLAGS' => 'cppflags-y', 'EXTRA_LDFLAGS' => 'ldflags-y', }; WARN("DEPRECATED_VARIABLE", "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); } # check we are in a valid source file if not then ignore this hunk next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); #line length limit if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && $rawline !~ /^.\s*\*\s*\@$Ident\s/ && !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && $length > $max_line_length) { WARN("LONG_LINE", "line over $max_line_length characters\n" . $herecurr); } # Check for user-visible strings broken across lines, which breaks the ability # to grep for the string. Limited to strings used as parameters (those # following an open parenthesis), which almost completely eliminates false # positives, as well as warning only once per parameter rather than once per # line of the string. Make an exception when the previous string ends in a # newline (multiple lines in one string constant) or \n\t (common in inline # assembly to indent the instruction on the following line). if ($line =~ /^\+\s*"/ && $prevline =~ /"\s*$/ && $prevline =~ /\(/ && $prevrawline !~ /\\n(?:\\t)*"\s*$/) { WARN("SPLIT_STRING", "quoted string split across lines\n" . $hereprev); } # check for spaces before a quoted newline if ($rawline =~ /^.*\".*\s\\n/) { WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", "unnecessary whitespace before a quoted newline\n" . $herecurr); } # check for adding lines without a newline. if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { WARN("MISSING_EOF_NEWLINE", "adding a line without newline at end of file\n" . $herecurr); } # Blackfin: use hi/lo macros if ($realfile =~ m@arch/blackfin/.*\.S$@) { if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("LO_MACRO", "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); } if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("HI_MACRO", "use the HI() macro, not (... >> 16)\n" . $herevet); } } # check we are in a valid source file C or perl if not then ignore this hunk next if ($realfile !~ /\.(h|c|pl)$/); # at the beginning of a line any tabs must come first and anything # more than 8 must use tabs. if ($rawline =~ /^\+\s* \t\s*\S/ || $rawline =~ /^\+\s* \s*/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; ERROR("CODE_INDENT", "code indent should use tabs where possible\n" . $herevet); $rpt_cleaners = 1; } # check for space before tabs. if ($rawline =~ /^\+/ && $rawline =~ / \t/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; WARN("SPACE_BEFORE_TAB", "please, no space before tabs\n" . $herevet); } # check for && or || at the start of a line if ($rawline =~ /^\+\s*(&&|\|\|)/) { CHK("LOGICAL_CONTINUATIONS", "Logical continuations should be on the previous line\n" . $hereprev); } # check multi-line statement indentation matches previous line if ($^V && $^V ge 5.10.0 && $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) { $prevline =~ /^\+(\t*)(.*)$/; my $oldindent = $1; my $rest = $2; my $pos = pos_last_openparen($rest); if ($pos >= 0) { $line =~ /^(\+| )([ \t]*)/; my $newindent = $2; my $goodtabindent = $oldindent . "\t" x ($pos / 8) . " " x ($pos % 8); my $goodspaceindent = $oldindent . " " x $pos; if ($newindent ne $goodtabindent && $newindent ne $goodspaceindent) { CHK("PARENTHESIS_ALIGNMENT", "Alignment should match open parenthesis\n" . $hereprev); } } } if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) { CHK("SPACING", "No space is necessary after a cast\n" . $hereprev); } if ($realfile =~ m@^(drivers/net/|net/)@ && $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ && $prevrawline =~ /^\+[ \t]*$/) { WARN("NETWORKING_BLOCK_COMMENT_STYLE", "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); } if ($realfile =~ m@^(drivers/net/|net/)@ && $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ WARN("NETWORKING_BLOCK_COMMENT_STYLE", "networking block comments put the trailing */ on a separate line\n" . $herecurr); } # check for spaces at the beginning of a line. # Exceptions: # 1) within comments # 2) indented preprocessor commands # 3) hanging labels if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; WARN("LEADING_SPACE", "please, no spaces at the start of a line\n" . $herevet); } # check we are in a valid C source file if not then ignore this hunk next if ($realfile !~ /\.(h|c)$/); # discourage the addition of CONFIG_EXPERIMENTAL in #if(def). if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) { WARN("CONFIG_EXPERIMENTAL", "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); } # check for RCS/CVS revision markers if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { WARN("CVS_KEYWORD", "CVS style keyword markers, these will _not_ be updated\n". $herecurr); } # Blackfin: don't use __builtin_bfin_[cs]sync if ($line =~ /__builtin_bfin_csync/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("CSYNC", "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); } if ($line =~ /__builtin_bfin_ssync/) { my $herevet = "$here\n" . cat_vet($line) . "\n"; ERROR("SSYNC", "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); } # check for old HOTPLUG __dev section markings if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { WARN("HOTPLUG_SECTION", "Using $1 is unnecessary\n" . $herecurr); } # Check for potential 'bare' types my ($stat, $cond, $line_nr_next, $remain_next, $off_next, $realline_next); #print "LINE<$line>\n"; if ($linenr >= $suppress_statement && $realcnt && $line =~ /.\s*\S/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0); $stat =~ s/\n./\n /g; $cond =~ s/\n./\n /g; #print "linenr<$linenr> <$stat>\n"; # If this statement has no statement boundaries within # it there is no point in retrying a statement scan # until we hit end of it. my $frag = $stat; $frag =~ s/;+\s*$//; if ($frag !~ /(?:{|;)/) { #print "skip<$line_nr_next>\n"; $suppress_statement = $line_nr_next; } # Find the real next line. $realline_next = $line_nr_next; if (defined $realline_next && (!defined $lines[$realline_next - 1] || substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { $realline_next++; } my $s = $stat; $s =~ s/{.*$//s; # Ignore goto labels. if ($s =~ /$Ident:\*$/s) { # Ignore functions being called } elsif ($s =~ /^.\s*$Ident\s*\(/s) { } elsif ($s =~ /^.\s*else\b/s) { # declarations always start with types } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { my $type = $1; $type =~ s/\s+/ /g; possible($type, "A:" . $s); # definitions in global scope can only start with types } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { possible($1, "B:" . $s); } # any (foo ... *) is a pointer cast, and foo is a type while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { possible($1, "C:" . $s); } # Check for any sort of function declaration. # int foo(something bar, other baz); # void (*store_gdt)(x86_descr_ptr *); if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { my ($name_len) = length($1); my $ctx = $s; substr($ctx, 0, $name_len + 1, ''); $ctx =~ s/\)[^\)]*$//; for my $arg (split(/\s*,\s*/, $ctx)) { if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { possible($1, "D:" . $s); } } } } # # Checks which may be anchored in the context. # # Check for switch () and associated case and default # statements should be at the same indent. if ($line=~/\bswitch\s*\(.*\)/) { my $err = ''; my $sep = ''; my @ctx = ctx_block_outer($linenr, $realcnt); shift(@ctx); for my $ctx (@ctx) { my ($clen, $cindent) = line_stats($ctx); if ($ctx =~ /^\+\s*(case\s+|default:)/ && $indent != $cindent) { $err .= "$sep$ctx\n"; $sep = ''; } else { $sep = "[...]\n"; } } if ($err ne '') { ERROR("SWITCH_CASE_INDENT_LEVEL", "switch and case should be at the same indent\n$hereline$err"); } } # if/while/etc brace do not go on next line, unless defining a do while loop, # or if that brace on the next line is for something else if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { my $pre_ctx = "$1$2"; my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); if ($line =~ /^\+\t{6,}/) { WARN("DEEP_INDENTATION", "Too many leading tabs - consider code refactoring\n" . $herecurr); } my $ctx_cnt = $realcnt - $#ctx - 1; my $ctx = join("\n", @ctx); my $ctx_ln = $linenr; my $ctx_skip = $realcnt; while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && defined $lines[$ctx_ln - 1] && $lines[$ctx_ln - 1] =~ /^-/)) { ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); $ctx_ln++; } #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { ERROR("OPEN_BRACE", "that open brace { should be on the previous line\n" . "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); } if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && $ctx =~ /\)\s*\;\s*$/ && defined $lines[$ctx_ln - 1]) { my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); if ($nindent > $indent) { WARN("TRAILING_SEMICOLON", "trailing semicolon indicates no statements, indent implies otherwise\n" . "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); } } } # Check relative indent for conditionals and blocks. if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0) if (!defined $stat); my ($s, $c) = ($stat, $cond); substr($s, 0, length($c), ''); # Make sure we remove the line prefixes as we have # none on the first line, and are going to readd them # where necessary. $s =~ s/\n./\n/gs; # Find out how long the conditional actually is. my @newlines = ($c =~ /\n/gs); my $cond_lines = 1 + $#newlines; # We want to check the first line inside the block # starting at the end of the conditional, so remove: # 1) any blank line termination # 2) any opening brace { on end of the line # 3) any do (...) { my $continuation = 0; my $check = 0; $s =~ s/^.*\bdo\b//; $s =~ s/^\s*{//; if ($s =~ s/^\s*\\//) { $continuation = 1; } if ($s =~ s/^\s*?\n//) { $check = 1; $cond_lines++; } # Also ignore a loop construct at the end of a # preprocessor statement. if (($prevline =~ /^.\s*#\s*define\s/ || $prevline =~ /\\\s*$/) && $continuation == 0) { $check = 0; } my $cond_ptr = -1; $continuation = 0; while ($cond_ptr != $cond_lines) { $cond_ptr = $cond_lines; # If we see an #else/#elif then the code # is not linear. if ($s =~ /^\s*\#\s*(?:else|elif)/) { $check = 0; } # Ignore: # 1) blank lines, they should be at 0, # 2) preprocessor lines, and # 3) labels. if ($continuation || $s =~ /^\s*?\n/ || $s =~ /^\s*#\s*?/ || $s =~ /^\s*$Ident\s*:/) { $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; if ($s =~ s/^.*?\n//) { $cond_lines++; } } } my (undef, $sindent) = line_stats("+" . $s); my $stat_real = raw_line($linenr, $cond_lines); # Check if either of these lines are modified, else # this is not this patch's fault. if (!defined($stat_real) || $stat !~ /^\+/ && $stat_real !~ /^\+/) { $check = 0; } if (defined($stat_real) && $cond_lines > 1) { $stat_real = "[...]\n$stat_real"; } #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; if ($check && (($sindent % 8) != 0 || ($sindent <= $indent && $s ne ''))) { WARN("SUSPECT_CODE_INDENT", "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); } } # Track the 'values' across context and added lines. my $opline = $line; $opline =~ s/^./ /; my ($curr_values, $curr_vars) = annotate_values($opline . "\n", $prev_values); $curr_values = $prev_values . $curr_values; if ($dbg_values) { my $outline = $opline; $outline =~ s/\t/ /g; print "$linenr > .$outline\n"; print "$linenr > $curr_values\n"; print "$linenr > $curr_vars\n"; } $prev_values = substr($curr_values, -1); #ignore lines not being added if ($line=~/^[^\+]/) {next;} # TEST: allow direct testing of the type matcher. if ($dbg_type) { if ($line =~ /^.\s*$Declare\s*$/) { ERROR("TEST_TYPE", "TEST: is type\n" . $herecurr); } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { ERROR("TEST_NOT_TYPE", "TEST: is not type ($1 is)\n". $herecurr); } next; } # TEST: allow direct testing of the attribute matcher. if ($dbg_attr) { if ($line =~ /^.\s*$Modifier\s*$/) { ERROR("TEST_ATTR", "TEST: is attr\n" . $herecurr); } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { ERROR("TEST_NOT_ATTR", "TEST: is not attr ($1 is)\n". $herecurr); } next; } # check for initialisation to aggregates open brace on the next line if ($line =~ /^.\s*{/ && $prevline =~ /(?:^|[^=])=\s*$/) { ERROR("OPEN_BRACE", "that open brace { should be on the previous line\n" . $hereprev); } # # Checks which are anchored on the added line. # # check for malformed paths in #include statements (uses RAW line) if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { my $path = $1; if ($path =~ m{//}) { ERROR("MALFORMED_INCLUDE", "malformed #include filename\n" . $herecurr); } if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { ERROR("UAPI_INCLUDE", "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); } } # no C99 // comments if ($line =~ m{//}) { ERROR("C99_COMMENTS", "do not use C99 // comments\n" . $herecurr); } # Remove C99 comments. $line =~ s@//.*@@; $opline =~ s@//.*@@; # EXPORT_SYMBOL should immediately follow the thing it is exporting, consider # the whole statement. #print "APW <$lines[$realline_next - 1]>\n"; if (defined $realline_next && exists $lines[$realline_next - 1] && !defined $suppress_export{$realline_next} && ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { # Handle definitions which produce identifiers with # a prefix: # XXX(foo); # EXPORT_SYMBOL(something_foo); my $name = $1; if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && $name =~ /^${Ident}_$2/) { #print "FOO C name<$name>\n"; $suppress_export{$realline_next} = 1; } elsif ($stat !~ /(?: \n.}\s*$| ^.DEFINE_$Ident\(\Q$name\E\)| ^.DECLARE_$Ident\(\Q$name\E\)| ^.LIST_HEAD\(\Q$name\E\)| ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() )/x) { #print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; $suppress_export{$realline_next} = 2; } else { $suppress_export{$realline_next} = 1; } } if (!defined $suppress_export{$linenr} && $prevline =~ /^.\s*$/ && ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { #print "FOO B <$lines[$linenr - 1]>\n"; $suppress_export{$linenr} = 2; } if (defined $suppress_export{$linenr} && $suppress_export{$linenr} == 2) { WARN("EXPORT_SYMBOL", "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); } # check for global initialisers. if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) { ERROR("GLOBAL_INITIALISERS", "do not initialise globals to 0 or NULL\n" . $herecurr); } # check for static initialisers. if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) { ERROR("INITIALISED_STATIC", "do not initialise statics to 0 or NULL\n" . $herecurr); } # check for static const char * arrays. if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { WARN("STATIC_CONST_CHAR_ARRAY", "static const char * array should probably be static const char * const\n" . $herecurr); } # check for static char foo[] = "bar" declarations. if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { WARN("STATIC_CONST_CHAR_ARRAY", "static char array declaration should probably be static const char\n" . $herecurr); } # check for declarations of struct pci_device_id if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) { WARN("DEFINE_PCI_DEVICE_TABLE", "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr); } # check for new typedefs, only function parameters and sparse annotations # make sense. if ($line =~ /\btypedef\s/ && $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && $line !~ /\b$typeTypedefs\b/ && $line !~ /\b__bitwise(?:__|)\b/) { WARN("NEW_TYPEDEFS", "do not add new typedefs\n" . $herecurr); } # * goes on variable not on type # (char*[ const]) while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { #print "AA<$1>\n"; my ($from, $to) = ($2, $2); # Should start with a space. $to =~ s/^(\S)/ $1/; # Should not end with a space. $to =~ s/\s+$//; # '*'s should not have spaces between. while ($to =~ s/\*\s+\*/\*\*/) { } #print "from<$from> to<$to>\n"; if ($from ne $to) { ERROR("POINTER_LOCATION", "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); } } while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { #print "BB<$1>\n"; my ($from, $to, $ident) = ($2, $2, $3); # Should start with a space. $to =~ s/^(\S)/ $1/; # Should not end with a space. $to =~ s/\s+$//; # '*'s should not have spaces between. while ($to =~ s/\*\s+\*/\*\*/) { } # Modifiers should have spaces. $to =~ s/(\b$Modifier$)/$1 /; #print "from<$from> to<$to> ident<$ident>\n"; if ($from ne $to && $ident !~ /^$Modifier$/) { ERROR("POINTER_LOCATION", "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr); } } # # no BUG() or BUG_ON() # if ($line =~ /\b(BUG|BUG_ON)\b/) { # print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; # print "$herecurr"; # $clean = 0; # } if ($line =~ /\bLINUX_VERSION_CODE\b/) { WARN("LINUX_VERSION_CODE", "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); } # check for uses of printk_ratelimit if ($line =~ /\bprintk_ratelimit\s*\(/) { WARN("PRINTK_RATELIMITED", "Prefer printk_ratelimited or pr__ratelimited to printk_ratelimit\n" . $herecurr); } # printk should use KERN_* levels. Note that follow on printk's on the # same line do not need a level, so we use the current block context # to try and find and validate the current printk. In summary the current # printk includes all preceding printk's which have no newline on the end. # we assume the first bad printk is the one to report. if ($line =~ /\bprintk\((?!KERN_)\s*"/) { my $ok = 0; for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { #print "CHECK<$lines[$ln - 1]\n"; # we have a preceding printk if it ends # with "\n" ignore it, else it is to blame if ($lines[$ln - 1] =~ m{\bprintk\(}) { if ($rawlines[$ln - 1] !~ m{\\n"}) { $ok = 1; } last; } } if ($ok == 0) { WARN("PRINTK_WITHOUT_KERN_LEVEL", "printk() should include KERN_ facility level\n" . $herecurr); } } if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { my $orig = $1; my $level = lc($orig); $level = "warn" if ($level eq "warning"); my $level2 = $level; $level2 = "dbg" if ($level eq "debug"); WARN("PREFER_PR_LEVEL", "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); } if ($line =~ /\bpr_warning\s*\(/) { WARN("PREFER_PR_LEVEL", "Prefer pr_warn(... to pr_warning(...\n" . $herecurr); } if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { my $orig = $1; my $level = lc($orig); $level = "warn" if ($level eq "warning"); $level = "dbg" if ($level eq "debug"); WARN("PREFER_DEV_LEVEL", "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); } # function brace can't be on same line, except for #defines of do while, # or if closed on same line if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) { ERROR("OPEN_BRACE", "open brace '{' following function declarations go on the next line\n" . $herecurr); } # open braces for enum, union and struct go on the same line. if ($line =~ /^.\s*{/ && $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { ERROR("OPEN_BRACE", "open brace '{' following $1 go on the same line\n" . $hereprev); } # missing space after union, struct or enum definition if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) { WARN("SPACING", "missing space after $1 definition\n" . $herecurr); } # check for spacing round square brackets; allowed: # 1. with a type on the left -- int [] a; # 2. at the beginning of a line for slice initialisers -- [0...10] = 5, # 3. inside a curly brace -- = { [0...10] = 5 } while ($line =~ /(.*?\s)\[/g) { my ($where, $prefix) = ($-[1], $1); if ($prefix !~ /$Type\s+$/ && ($where != 0 || $prefix !~ /^.\s+$/) && $prefix !~ /[{,]\s+$/) { ERROR("BRACKET_SPACE", "space prohibited before open square bracket '['\n" . $herecurr); } } # check for spaces between functions and their parentheses. while ($line =~ /($Ident)\s+\(/g) { my $name = $1; my $ctx_before = substr($line, 0, $-[1]); my $ctx = "$ctx_before$name"; # Ignore those directives where spaces _are_ permitted. if ($name =~ /^(?: if|for|while|switch|return|case| volatile|__volatile__| __attribute__|format|__extension__| asm|__asm__)$/x) { # cpp #define statements have non-optional spaces, ie # if there is a space between the name and the open # parenthesis it is simply not a parameter group. } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { # cpp #elif statement condition may start with a ( } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { # If this whole things ends with a type its most # likely a typedef for a function. } elsif ($ctx =~ /$Type$/) { } else { WARN("SPACING", "space prohibited between function name and open parenthesis '('\n" . $herecurr); } } # check for whitespace before a non-naked semicolon if ($line =~ /^\+.*\S\s+;/) { WARN("SPACING", "space prohibited before semicolon\n" . $herecurr); } # Check operator spacing. if (!($line=~/\#\s*include/)) { my $ops = qr{ <<=|>>=|<=|>=|==|!=| \+=|-=|\*=|\/=|%=|\^=|\|=|&=| =>|->|<<|>>|<|>|=|!|~| &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| \?|: }x; my @elements = split(/($ops|;)/, $opline); my $off = 0; my $blank = copy_spacing($opline); for (my $n = 0; $n < $#elements; $n += 2) { $off += length($elements[$n]); # Pick up the preceding and succeeding characters. my $ca = substr($opline, 0, $off); my $cc = ''; if (length($opline) >= ($off + length($elements[$n + 1]))) { $cc = substr($opline, $off + length($elements[$n + 1])); } my $cb = "$ca$;$cc"; my $a = ''; $a = 'V' if ($elements[$n] ne ''); $a = 'W' if ($elements[$n] =~ /\s$/); $a = 'C' if ($elements[$n] =~ /$;$/); $a = 'B' if ($elements[$n] =~ /(\[|\()$/); $a = 'O' if ($elements[$n] eq ''); $a = 'E' if ($ca =~ /^\s*$/); my $op = $elements[$n + 1]; my $c = ''; if (defined $elements[$n + 2]) { $c = 'V' if ($elements[$n + 2] ne ''); $c = 'W' if ($elements[$n + 2] =~ /^\s/); $c = 'C' if ($elements[$n + 2] =~ /^$;/); $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); $c = 'O' if ($elements[$n + 2] eq ''); $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); } else { $c = 'E'; } my $ctx = "${a}x${c}"; my $at = "(ctx:$ctx)"; my $ptr = substr($blank, 0, $off) . "^"; my $hereptr = "$hereline$ptr\n"; # Pull out the value of this operator. my $op_type = substr($curr_values, $off + 1, 1); # Get the full operator variant. my $opv = $op . substr($curr_vars, $off, 1); # Ignore operators passed as parameters. if ($op_type ne 'V' && $ca =~ /\s$/ && $cc =~ /^\s*,/) { # # Ignore comments # } elsif ($op =~ /^$;+$/) { # ; should have either the end of line or a space or \ after it } elsif ($op eq ';') { if ($ctx !~ /.x[WEBC]/ && $cc !~ /^\\/ && $cc !~ /^;/) { ERROR("SPACING", "space required after that '$op' $at\n" . $hereptr); } # // is a comment } elsif ($op eq '//') { # No spaces for: # -> # : when part of a bitfield } elsif ($op eq '->' || $opv eq ':B') { if ($ctx =~ /Wx.|.xW/) { ERROR("SPACING", "spaces prohibited around that '$op' $at\n" . $hereptr); } # , must have a space on the right. } elsif ($op eq ',') { if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { ERROR("SPACING", "space required after that '$op' $at\n" . $hereptr); } # '*' as part of a type definition -- reported already. } elsif ($opv eq '*_') { #warn "'*' is part of type\n"; # unary operators should have a space before and # none after. May be left adjacent to another # unary operator, or a cast } elsif ($op eq '!' || $op eq '~' || $opv eq '*U' || $opv eq '-U' || $opv eq '&U' || $opv eq '&&U') { if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { ERROR("SPACING", "space required before that '$op' $at\n" . $hereptr); } if ($op eq '*' && $cc =~/\s*$Modifier\b/) { # A unary '*' may be const } elsif ($ctx =~ /.xW/) { ERROR("SPACING", "space prohibited after that '$op' $at\n" . $hereptr); } # unary ++ and unary -- are allowed no space on one side. } elsif ($op eq '++' or $op eq '--') { if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { ERROR("SPACING", "space required one side of that '$op' $at\n" . $hereptr); } if ($ctx =~ /Wx[BE]/ || ($ctx =~ /Wx./ && $cc =~ /^;/)) { ERROR("SPACING", "space prohibited before that '$op' $at\n" . $hereptr); } if ($ctx =~ /ExW/) { ERROR("SPACING", "space prohibited after that '$op' $at\n" . $hereptr); } # << and >> may either have or not have spaces both sides } elsif ($op eq '<<' or $op eq '>>' or $op eq '&' or $op eq '^' or $op eq '|' or $op eq '+' or $op eq '-' or $op eq '*' or $op eq '/' or $op eq '%') { if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { ERROR("SPACING", "need consistent spacing around '$op' $at\n" . $hereptr); } # A colon needs no spaces before when it is # terminating a case value or a label. } elsif ($opv eq ':C' || $opv eq ':L') { if ($ctx =~ /Wx./) { ERROR("SPACING", "space prohibited before that '$op' $at\n" . $hereptr); } # All the others need spaces both sides. } elsif ($ctx !~ /[EWC]x[CWE]/) { my $ok = 0; # Ignore email addresses if (($op eq '<' && $cc =~ /^\S+\@\S+>/) || ($op eq '>' && $ca =~ /<\S+\@\S+$/)) { $ok = 1; } # Ignore ?: if (($opv eq ':O' && $ca =~ /\?$/) || ($op eq '?' && $cc =~ /^:/)) { $ok = 1; } if ($ok == 0) { ERROR("SPACING", "spaces required around that '$op' $at\n" . $hereptr); } } $off += length($elements[$n + 1]); } } # check for multiple assignments if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { CHK("MULTIPLE_ASSIGNMENTS", "multiple assignments should be avoided\n" . $herecurr); } ## # check for multiple declarations, allowing for a function declaration ## # continuation. ## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && ## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { ## ## # Remove any bracketed sections to ensure we do not ## # falsly report the parameters of functions. ## my $ln = $line; ## while ($ln =~ s/\([^\(\)]*\)//g) { ## } ## if ($ln =~ /,/) { ## WARN("MULTIPLE_DECLARATION", ## "declaring multiple variables together should be avoided\n" . $herecurr); ## } ## } #need space before brace following if, while, etc if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) || $line =~ /do{/) { ERROR("SPACING", "space required before the open brace '{'\n" . $herecurr); } # closing brace should have a space following it when it has anything # on the line if ($line =~ /}(?!(?:,|;|\)))\S/) { ERROR("SPACING", "space required after that close brace '}'\n" . $herecurr); } # check spacing on square brackets if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { ERROR("SPACING", "space prohibited after that open square bracket '['\n" . $herecurr); } if ($line =~ /\s\]/) { ERROR("SPACING", "space prohibited before that close square bracket ']'\n" . $herecurr); } # check spacing on parentheses if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && $line !~ /for\s*\(\s+;/) { ERROR("SPACING", "space prohibited after that open parenthesis '('\n" . $herecurr); } if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && $line !~ /for\s*\(.*;\s+\)/ && $line !~ /:\s+\)/) { ERROR("SPACING", "space prohibited before that close parenthesis ')'\n" . $herecurr); } #goto labels aren't indented, allow a single space however if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { WARN("INDENTED_LABEL", "labels should not be indented\n" . $herecurr); } # Return is not a function. if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) { my $spacing = $1; my $value = $2; # Flatten any parentheses $value =~ s/\(/ \(/g; $value =~ s/\)/\) /g; while ($value =~ s/\[[^\[\]]*\]/1/ || $value !~ /(?:$Ident|-?$Constant)\s* $Compare\s* (?:$Ident|-?$Constant)/x && $value =~ s/\([^\(\)]*\)/1/) { } #print "value<$value>\n"; if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) { ERROR("RETURN_PARENTHESES", "return is not a function, parentheses are not required\n" . $herecurr); } elsif ($spacing !~ /\s+/) { ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); } } # Return of what appears to be an errno should normally be -'ve if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { my $name = $1; if ($name ne 'EOF' && $name ne 'ERROR') { WARN("USE_NEGATIVE_ERRNO", "return of an errno should typically be -ve (return -$1)\n" . $herecurr); } } # Need a space before open parenthesis after if, while etc if ($line=~/\b(if|while|for|switch)\(/) { ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); } # Check for illegal assignment in if conditional -- and check for trailing # statements after the conditional. if ($line =~ /do\s*(?!{)/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0) if (!defined $stat); my ($stat_next) = ctx_statement_block($line_nr_next, $remain_next, $off_next); $stat_next =~ s/\n./\n /g; ##print "stat<$stat> stat_next<$stat_next>\n"; if ($stat_next =~ /^\s*while\b/) { # If the statement carries leading newlines, # then count those as offsets. my ($whitespace) = ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); my $offset = statement_rawlines($whitespace) - 1; $suppress_whiletrailers{$line_nr_next + $offset} = 1; } } if (!defined $suppress_whiletrailers{$linenr} && $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { my ($s, $c) = ($stat, $cond); if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { ERROR("ASSIGN_IN_IF", "do not use assignment in if condition\n" . $herecurr); } # Find out what is on the end of the line after the # conditional. substr($s, 0, length($c), ''); $s =~ s/\n.*//g; $s =~ s/$;//g; # Remove any comments if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && $c !~ /}\s*while\s*/ && !($c =~ /while/ && $s eq ";")) { # Find out how long the conditional actually is. my @newlines = ($c =~ /\n/gs); my $cond_lines = 1 + $#newlines; my $stat_real = ''; $stat_real = raw_line($linenr, $cond_lines) . "\n" if ($cond_lines); if (defined($stat_real) && $cond_lines > 1) { $stat_real = "[...]\n$stat_real"; } ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr . $stat_real); } } # Check for bitwise tests written as boolean if ($line =~ / (?: (?:\[|\(|\&\&|\|\|) \s*0[xX][0-9]+\s* (?:\&\&|\|\|) | (?:\&\&|\|\|) \s*0[xX][0-9]+\s* (?:\&\&|\|\||\)|\]) )/x) { WARN("HEXADECIMAL_BOOLEAN_TEST", "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); } # if and else should not have general statements after it if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { my $s = $1; $s =~ s/$;//g; # Remove any comments if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); } } # if should not continue a brace if ($line =~ /}\s*if\b/) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); } # case and default should not have general statements after them if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && $line !~ /\G(?: (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| \s*return\s+ )/xg) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); } # Check for }else {, these must be at the same # indent level to be relevant to each other. if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and $previndent == $indent) { ERROR("ELSE_AFTER_BRACE", "else should follow close brace '}'\n" . $hereprev); } #if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and # $previndent == $indent) { # my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); # # Find out what is on the end of the line after the # # conditional. # substr($s, 0, length($c), ''); # $s =~ s/\n.*//g; # if ($s =~ /^\s*;/) { # ERROR("WHILE_AFTER_BRACE", # "while should follow close brace '}'\n" . $hereprev); # } #} #CamelCase while ($line =~ m{($Constant|$Lval)}g) { my $var = $1; if ($var !~ /$Constant/ && $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ && $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && !defined $camelcase{$var} && $var !~ /[A-Z][A-Z0-9_]*x[A-Z0-9_]*\b/) { $camelcase{$var} = 1; #print "Camelcase line <<$line>> <<$var>>\n"; WARN("CAMELCASE", "Avoid CamelCase: <$var>\n" . $herecurr); } } #no spaces allowed after \ in define if ($line=~/\#\s*define.*\\\s$/) { WARN("WHITESPACE_AFTER_LINE_CONTINUATION", "Whitepspace after \\ makes next lines useless\n" . $herecurr); } #warn if is #included and is available (uses RAW line) if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\}) { my $file = "$1.h"; my $checkfile = "include/linux/$file"; if (-f "$root/$checkfile" && $realfile ne $checkfile && $1 !~ /$allowed_asm_includes/) { if ($realfile =~ m{^arch/}) { CHK("ARCH_INCLUDE_LINUX", "Consider using #include instead of \n" . $herecurr); } else { WARN("INCLUDE_LINUX", "Use #include instead of \n" . $herecurr); } } } # multi-statement macros should be enclosed in a do while loop, grab the # first statement and ensure its the whole macro if its not enclosed # in a known good container if ($realfile !~ m@/vmlinux.lds.h$@ && $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { my $ln = $linenr; my $cnt = $realcnt; my ($off, $dstat, $dcond, $rest); my $ctx = ''; ($dstat, $dcond, $ln, $cnt, $off) = ctx_statement_block($linenr, $realcnt, 0); $ctx = $dstat; #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//; $dstat =~ s/$;//g; $dstat =~ s/\\\n.//g; $dstat =~ s/^\s*//s; $dstat =~ s/\s*$//s; # Flatten any parentheses and braces while ($dstat =~ s/\([^\(\)]*\)/1/ || $dstat =~ s/\{[^\{\}]*\}/1/ || $dstat =~ s/\[[^\[\]]*\]/1/) { } # Flatten any obvious string concatentation. while ($dstat =~ s/("X*")\s*$Ident/$1/ || $dstat =~ s/$Ident\s*("X*")/$1/) { } my $exceptions = qr{ $Declare| module_param_named| MODULE_PARM_DESC| DECLARE_PER_CPU| DEFINE_PER_CPU| __typeof__\(| union| struct| \.$Ident\s*=\s*| ^\"|\"$ }x; #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; if ($dstat ne '' && $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo $dstat !~ /^'X'$/ && # character constants $dstat !~ /$exceptions/ && $dstat !~ /^\.$Ident\s*=/ && # .foo = $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) $dstat !~ /^for\s*$Constant$/ && # for (...) $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() $dstat !~ /^do\s*{/ && # do {... $dstat !~ /^\({/) # ({... { $ctx =~ s/\n*$//; my $herectx = $here . "\n"; my $cnt = statement_rawlines($ctx); for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } if ($dstat =~ /;/) { ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); } else { ERROR("COMPLEX_MACRO", "Macros with complex values should be enclosed in parenthesis\n" . "$herectx"); } } # check for line continuations outside of #defines, preprocessor #, and asm } else { if ($prevline !~ /^..*\\$/ && $line !~ /^\+\s*\#.*\\$/ && # preprocessor $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm $line =~ /^\+.*\\$/) { WARN("LINE_CONTINUATIONS", "Avoid unnecessary line continuations\n" . $herecurr); } } # do {} while (0) macro tests: # single-statement macros do not need to be enclosed in do while (0) loop, # macro should not end with a semicolon if ($^V && $^V ge 5.10.0 && $realfile !~ m@/vmlinux.lds.h$@ && $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { my $ln = $linenr; my $cnt = $realcnt; my ($off, $dstat, $dcond, $rest); my $ctx = ''; ($dstat, $dcond, $ln, $cnt, $off) = ctx_statement_block($linenr, $realcnt, 0); $ctx = $dstat; $dstat =~ s/\\\n.//g; if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { my $stmts = $2; my $semis = $3; $ctx =~ s/\n*$//; my $cnt = statement_rawlines($ctx); my $herectx = $here . "\n"; for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } if (($stmts =~ tr/;/;/) == 1 && $stmts !~ /^\s*(if|while|for|switch)\b/) { WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); } if (defined $semis && $semis ne "") { WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); } } } # make sure symbols are always wrapped with VMLINUX_SYMBOL() ... # all assignments may have only one of the following with an assignment: # . # ALIGN(...) # VMLINUX_SYMBOL(...) if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { WARN("MISSING_VMLINUX_SYMBOL", "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); } # check for redundant bracing round if etc if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { my ($level, $endln, @chunks) = ctx_statement_full($linenr, $realcnt, 1); #if ($#chunks > 0) { # print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; # my $count = 0; # for my $chunk (@chunks) { # my ($cond, $block) = @{$chunk}; # print "APW: count<$count> <<$cond>><<$block>>\n"; # $count++; # } #} if ($#chunks > 0 && $level == 0) { my @allowed = (); my $allow = 0; my $seen = 0; my $herectx = $here . "\n"; my $ln = $linenr - 1; for my $chunk (@chunks) { my ($cond, $block) = @{$chunk}; # If the condition carries leading newlines, then count those as offsets. my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); my $offset = statement_rawlines($whitespace) - 1; $allowed[$allow] = 0; #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; # We have looked at and allowed this specific line. $suppress_ifbraces{$ln + $offset} = 1; $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; $ln += statement_rawlines($block) - 1; substr($block, 0, length($cond), ''); $seen++ if ($block =~ /^\s*{/); #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; #if (statement_lines($cond) > 1) { # #print "APW: ALLOWED: cond<$cond>\n"; # $allowed[$allow] = 1; #} #if ($block =~/\b(?:if|for|while)\b/) { # #print "APW: ALLOWED: block<$block>\n"; # $allowed[$allow] = 1; #} #if (statement_block_size($block) > 1) { # #print "APW: ALLOWED: lines block<$block>\n"; # $allowed[$allow] = 1; #} #$allow++; } if (!$seen) { ERROR("BRACES", "braces {} are necessary for all arms of this statement\n" . $herectx); } #if ($seen) { # my $sum_allowed = 0; # foreach (@allowed) { # $sum_allowed += $_; # } # if ($sum_allowed == 0) { # WARN("BRACES", # "braces {} are not necessary for any arm of this statement\n" . $herectx); # } elsif ($sum_allowed != $allow && # $seen != $allow) { # CHK("BRACES", # "braces {} should be used on all arms of this statement\n" . $herectx); # } #} } } if (!defined $suppress_ifbraces{$linenr - 1} && $line =~ /\b(if|while|for|else)\b/) { my $allowed = 0; # Check the pre-context. if (substr($line, 0, $-[0]) =~ /(#\s*)$/) { #print "APW: ALLOWED: pre<$1>\n"; $allowed = 1; } my ($level, $endln, @chunks) = ctx_statement_full($linenr, $realcnt, $-[0]); # Check the condition. my ($cond, $block) = @{$chunks[0]}; #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; if (defined $cond) { substr($block, 0, length($cond), ''); } if ($cond =~ /\bwhile/ && $block =~ /^;/) { #print "APW: ALLOWED: block<$block>"; $allowed = 1; } #if ($block =~/\b(?:if|for|while)\b/) { # print "APW: ALLOWED: block<$block>\n"; # $allowed = 1; #} # Check the post-context. if (defined $chunks[1]) { my ($cond, $block) = @{$chunks[1]}; if (defined $cond) { substr($block, 0, length($cond), ''); } if ($block =~ /^\s*\{/) { #print "APW: ALLOWED: chunk-1 block<$block>\n"; #$allowed = 1; } } if ($level == 0 && !($block =~ /^\s*\{/) && !$allowed) { my $herectx = $here . "\n"; my $cnt = statement_rawlines($block); for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } WARN("BRACES", "braces {} are needed for every statement block\n" . $herectx); } } # check for unnecessary blank lines around braces if (($line =~ /^.\s*}\s*$/ && $prevline =~ /^.\s*$/)) { CHK("BRACES", "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); } if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { CHK("BRACES", "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); } # no volatiles please my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { WARN("VOLATILE", "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); } # warn about #if 0 if ($line =~ /^.\s*\#\s*if\s+0\b/) { CHK("REDUNDANT_CODE", "if this code is redundant consider removing it\n" . $herecurr); } # check for needless "if () fn()" uses if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;'; if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) { WARN('NEEDLESS_IF', "$1(NULL) is safe this check is probably not required\n" . $hereprev); } } # prefer usleep_range over udelay if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { # ignore udelay's < 10, however if (! ($1 < 10) ) { CHK("USLEEP_RANGE", "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); } } # warn about unexpectedly long msleep's if ($line =~ /\bmsleep\s*\((\d+)\);/) { if ($1 < 20) { WARN("MSLEEP", "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line); } } # warn about #ifdefs in C files # if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { # print "#ifdef in C files should be avoided\n"; # print "$herecurr"; # $clean = 0; # } # warn about spacing in #ifdefs if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { ERROR("SPACING", "exactly one space required after that #$1\n" . $herecurr); } # check for spinlock_t definitions without a comment. if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { my $which = $1; if (!ctx_has_comment($first_line, $linenr)) { CHK("UNCOMMENTED_DEFINITION", "$1 definition without comment\n" . $herecurr); } } # check for memory barriers without a comment. if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { if (!ctx_has_comment($first_line, $linenr)) { CHK("MEMORY_BARRIER", "memory barrier without comment\n" . $herecurr); } } # check of hardware specific defines if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { CHK("ARCH_DEFINES", "architecture specific defines should be avoided\n" . $herecurr); } # Check that the storage class is at the beginning of a declaration if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { WARN("STORAGE_CLASS", "storage class should be at the beginning of the declaration\n" . $herecurr) } # check the location of the inline attribute, that it is between # storage class and type. if ($line =~ /\b$Type\s+$Inline\b/ || $line =~ /\b$Inline\s+$Storage\b/) { ERROR("INLINE_LOCATION", "inline keyword should sit between storage class and type\n" . $herecurr); } # Check for __inline__ and __inline, prefer inline if ($line =~ /\b(__inline__|__inline)\b/) { WARN("INLINE", "plain inline is preferred over $1\n" . $herecurr); } # Check for __attribute__ format(printf, prefer __printf if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { WARN("PREFER_PRINTF", "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr); } # Check for __attribute__ format(scanf, prefer __scanf if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { WARN("PREFER_SCANF", "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr); } # check for sizeof(&) if ($line =~ /\bsizeof\s*\(\s*\&/) { WARN("SIZEOF_ADDRESS", "sizeof(& should be avoided\n" . $herecurr); } # check for sizeof without parenthesis if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { WARN("SIZEOF_PARENTHESIS", "sizeof $1 should be sizeof($1)\n" . $herecurr); } # check for line continuations in quoted strings with odd counts of " if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { WARN("LINE_CONTINUATIONS", "Avoid line continuations in quoted strings\n" . $herecurr); } # check for struct spinlock declarations if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { WARN("USE_SPINLOCK_T", "struct spinlock should be spinlock_t\n" . $herecurr); } # check for seq_printf uses that could be seq_puts if ($line =~ /\bseq_printf\s*\(/) { my $fmt = get_quoted_string($line, $rawline); if ($fmt !~ /[^\\]\%/) { WARN("PREFER_SEQ_PUTS", "Prefer seq_puts to seq_printf\n" . $herecurr); } } # Check for misused memsets if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) { my $ms_addr = $2; my $ms_val = $7; my $ms_size = $12; if ($ms_size =~ /^(0x|)0$/i) { ERROR("MEMSET", "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); } elsif ($ms_size =~ /^(0x|)1$/i) { WARN("MEMSET", "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); } } # typecasts on min/max could be min_t/max_t if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { if (defined $2 || defined $7) { my $call = $1; my $cast1 = deparenthesize($2); my $arg1 = $3; my $cast2 = deparenthesize($7); my $arg2 = $8; my $cast; if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { $cast = "$cast1 or $cast2"; } elsif ($cast1 ne "") { $cast = $cast1; } else { $cast = $cast2; } WARN("MINMAX", "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); } } # check usleep_range arguments if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { my $min = $1; my $max = $7; if ($min eq $max) { WARN("USLEEP_RANGE", "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && $min > $max) { WARN("USLEEP_RANGE", "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); } } # check for new externs in .c files. if ($realfile =~ /\.c$/ && defined $stat && $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) { my $function_name = $1; my $paren_space = $2; my $s = $stat; if (defined $cond) { substr($s, 0, length($cond), ''); } if ($s =~ /^\s*;/ && $function_name ne 'uninitialized_var') { WARN("AVOID_EXTERNS", "externs should be avoided in .c files\n" . $herecurr); } if ($paren_space =~ /\n/) { WARN("FUNCTION_ARGUMENTS", "arguments for function declarations should follow identifier\n" . $herecurr); } } elsif ($realfile =~ /\.c$/ && defined $stat && $stat =~ /^.\s*extern\s+/) { WARN("AVOID_EXTERNS", "externs should be avoided in .c files\n" . $herecurr); } # checks for new __setup's if ($rawline =~ /\b__setup\("([^"]*)"/) { my $name = $1; if (!grep(/$name/, @setup_docs)) { CHK("UNDOCUMENTED_SETUP", "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); } } # check for pointless casting of kmalloc return if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) { WARN("UNNECESSARY_CASTS", "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); } # check for krealloc arg reuse if ($^V && $^V ge 5.10.0 && $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) { WARN("KREALLOC_ARG_REUSE", "Reusing the krealloc arg is almost always a bug\n" . $herecurr); } # check for alloc argument mismatch if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { WARN("ALLOC_ARRAY_ARGS", "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); } # check for multiple semicolons if ($line =~ /;\s*;\s*$/) { WARN("ONE_SEMICOLON", "Statements terminations use 1 semicolon\n" . $herecurr); } # check for switch/default statements without a break; if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { my $ctx = ''; my $herectx = $here . "\n"; my $cnt = statement_rawlines($stat); for (my $n = 0; $n < $cnt; $n++) { $herectx .= raw_line($linenr, $n) . "\n"; } WARN("DEFAULT_NO_BREAK", "switch default: should use break\n" . $herectx); } # check for gcc specific __FUNCTION__ if ($line =~ /__FUNCTION__/) { WARN("USE_FUNC", "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); } # check for use of yield() if ($line =~ /\byield\s*\(\s*\)/) { WARN("YIELD", "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); } # check for semaphores initialized locked if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { WARN("CONSIDER_COMPLETION", "consider using a completion\n" . $herecurr); } # recommend kstrto* over simple_strto* and strict_strto* if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { WARN("CONSIDER_KSTRTO", "$1 is obsolete, use k$3 instead\n" . $herecurr); } # check for __initcall(), use device_initcall() explicitly please if ($line =~ /^.\s*__initcall\s*\(/) { WARN("USE_DEVICE_INITCALL", "please use device_initcall() instead of __initcall()\n" . $herecurr); } # check for various ops structs, ensure they are const. my $struct_ops = qr{acpi_dock_ops| address_space_operations| backlight_ops| block_device_operations| dentry_operations| dev_pm_ops| dma_map_ops| extent_io_ops| file_lock_operations| file_operations| hv_ops| ide_dma_ops| intel_dvo_dev_ops| item_operations| iwl_ops| kgdb_arch| kgdb_io| kset_uevent_ops| lock_manager_operations| microcode_ops| mtrr_ops| neigh_ops| nlmsvc_binding| pci_raw_ops| pipe_buf_operations| platform_hibernation_ops| platform_suspend_ops| proto_ops| rpc_pipe_ops| seq_operations| snd_ac97_build_ops| soc_pcmcia_socket_ops| stacktrace_ops| sysfs_ops| tty_operations| usb_mon_operations| wd_ops}x; if ($line !~ /\bconst\b/ && $line =~ /\bstruct\s+($struct_ops)\b/) { WARN("CONST_STRUCT", "struct $1 should normally be const\n" . $herecurr); } # use of NR_CPUS is usually wrong # ignore definitions of NR_CPUS and usage to define arrays as likely right if ($line =~ /\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) { WARN("NR_CPUS", "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); } # check for %L{u,d,i} in strings my $string; while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { $string = substr($rawline, $-[1], $+[1] - $-[1]); $string =~ s/%%/__/g; if ($string =~ /(?mutex.\n" . $herecurr); } } if ($line =~ /debugfs_create_file.*S_IWUGO/ || $line =~ /DEVICE_ATTR.*S_IWUGO/ ) { WARN("EXPORTED_WORLD_WRITABLE", "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); } } # If we have no input at all, then there is nothing to report on # so just keep quiet. if ($#rawlines == -1) { exit(0); } # In mailback mode only produce a report in the negative, for # things that appear to be patches. if ($mailback && ($clean == 1 || !$is_patch)) { exit(0); } # This is not a patch, and we are are in 'no-patch' mode so # just keep quiet. if (!$chk_patch && !$is_patch) { exit(0); } if (!$is_patch) { ERROR("NOT_UNIFIED_DIFF", "Does not appear to be a unified-diff format patch\n"); } if ($is_patch && $chk_signoff && $signoff == 0) { ERROR("MISSING_SIGN_OFF", "Missing Signed-off-by: line(s)\n"); } print report_dump(); if ($summary && !($clean == 1 && $quiet == 1)) { print "$filename " if ($summary_file); print "total: $cnt_error errors, $cnt_warn warnings, " . (($check)? "$cnt_chk checks, " : "") . "$cnt_lines lines checked\n"; print "\n" if ($quiet == 0); } if ($quiet == 0) { if ($^V lt 5.10.0) { print("NOTE: perl $^V is not modern enough to detect all possible issues.\n"); print("An upgrade to at least perl v5.10.0 is suggested.\n\n"); } # If there were whitespace errors which cleanpatch can fix # then suggest that. if ($rpt_cleaners) { print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; print " scripts/cleanfile\n\n"; $rpt_cleaners = 0; } } if ($quiet == 0 && keys %ignore_type) { print "NOTE: Ignored message types:"; foreach my $ignore (sort keys %ignore_type) { print " $ignore"; } print "\n\n"; } if ($clean == 1 && $quiet == 0) { print "$vname has no obvious style problems and is ready for submission.\n" } if ($clean == 0 && $quiet == 0) { print << "EOM"; $vname has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. EOM } return $clean; } hackrf-0.0~git20230104.cfc2f34/scripts/data/000077500000000000000000000000001435536612600200715ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/000077500000000000000000000000001435536612600213765ustar00rootroot00000000000000hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/README000066400000000000000000000014221435536612600222550ustar00rootroot00000000000000These files contain information derived from the LPC43xx user manual (UM10503). They are intended to be used by scripts for the generation of header files and functions. Each line describes a field within a register. The comma separated values are: register name (as found in include/lpc43xx/*.h), bit position, length in bits, field name, description/comment (may be empty if not specified in data sheet), reset value (may be empty if not specified in data sheet), access (may be empty if not specified in data sheet) The access field may consist of any of the following codes: r: read only rw: read/write rwc: read/write one to clear rwo: read/write once rws: read/write one to set w: write only ws: write one to set Descriptions containing commas are quoted. hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/adc.csv000066400000000000000000000260161435536612600226470ustar00rootroot00000000000000ADC0_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw ADC0_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw ADC0_CR,16,1,BURST,Controls Burst mode,0,rw ADC0_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw ADC0_CR,21,1,PDN,Power mode,0,rw ADC0_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw ADC0_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw ADC1_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw ADC1_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw ADC1_CR,16,1,BURST,Controls Burst mode,0,rw ADC1_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw ADC1_CR,21,1,PDN,Power mode,0,rw ADC1_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw ADC1_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw ADC0_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r ADC0_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r ADC0_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r ADC0_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r ADC1_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r ADC1_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r ADC1_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r ADC1_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r ADC0_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw ADC0_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw ADC1_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw ADC1_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw ADC0_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r ADC0_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC0_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC1_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r ADC1_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r ADC1_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r ADC0_STAT,0,8,DONE,These bits mirror the DONE status flags that appear in the result register for each A/D channel.,0,r ADC0_STAT,8,8,OVERRUN,These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel.,0,r ADC0_STAT,16,1,ADINT,This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.,0,r hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/adc.yaml000066400000000000000000000460351435536612600230210ustar00rootroot00000000000000!!omap - ADC0_CR: fields: !!omap - SEL: access: rw description: Selects which of the ADCn_[7:0] inputs are to be sampled and converted lsb: 0 reset_value: '0' width: 8 - CLKDIV: access: rw description: The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter lsb: 8 reset_value: '0' width: 8 - BURST: access: rw description: Controls Burst mode lsb: 16 reset_value: '0' width: 1 - CLKS: access: rw description: This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). lsb: 17 reset_value: '0' width: 3 - PDN: access: rw description: Power mode lsb: 21 reset_value: '0' width: 1 - START: access: rw description: Controls the start of an A/D conversion when the BURST bit is 0 lsb: 24 reset_value: '0' width: 3 - EDGE: access: rw description: Controls rising or falling edge on the selected signal for the start of a conversion lsb: 27 reset_value: '0' width: 1 - ADC1_CR: fields: !!omap - SEL: access: rw description: Selects which of the ADCn_[7:0] inputs are to be sampled and converted lsb: 0 reset_value: '0' width: 8 - CLKDIV: access: rw description: The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter lsb: 8 reset_value: '0' width: 8 - BURST: access: rw description: Controls Burst mode lsb: 16 reset_value: '0' width: 1 - CLKS: access: rw description: This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). lsb: 17 reset_value: '0' width: 3 - PDN: access: rw description: Power mode lsb: 21 reset_value: '0' width: 1 - START: access: rw description: Controls the start of an A/D conversion when the BURST bit is 0 lsb: 24 reset_value: '0' width: 3 - EDGE: access: rw description: Controls rising or falling edge on the selected signal for the start of a conversion lsb: 27 reset_value: '0' width: 1 - ADC0_GDR: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - CHN: access: r description: These bits contain the channel from which the LS bits were converted lsb: 24 reset_value: '0' width: 3 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written lsb: 31 reset_value: '0' width: 1 - ADC1_GDR: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - CHN: access: r description: These bits contain the channel from which the LS bits were converted lsb: 24 reset_value: '0' width: 3 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written lsb: 31 reset_value: '0' width: 1 - ADC0_INTEN: fields: !!omap - ADINTEN: access: rw description: These bits allow control over which A/D channels generate interrupts for conversion completion lsb: 0 reset_value: '0' width: 8 - ADGINTEN: access: rw description: When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. lsb: 8 reset_value: '1' width: 1 - ADC1_INTEN: fields: !!omap - ADINTEN: access: rw description: These bits allow control over which A/D channels generate interrupts for conversion completion lsb: 0 reset_value: '0' width: 8 - ADGINTEN: access: rw description: When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. lsb: 8 reset_value: '1' width: 1 - ADC0_DR0: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR0: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_DR1: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR1: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_DR2: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR2: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_DR3: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR3: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_DR4: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR4: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_DR5: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR5: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_DR6: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR6: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_DR7: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC1_DR7: fields: !!omap - V_VREF: access: r description: When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin lsb: 6 reset_value: '0' width: 10 - OVERRUN: access: r description: This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. lsb: 30 reset_value: '0' width: 1 - DONE: access: r description: This bit is set to 1 when an A/D conversion completes. lsb: 31 reset_value: '0' width: 1 - ADC0_STAT: fields: !!omap - DONE: access: r description: These bits mirror the DONE status flags that appear in the result register for each A/D channel. lsb: 0 reset_value: '0' width: 8 - OVERRUN: access: r description: These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. lsb: 8 reset_value: '0' width: 8 - ADINT: access: r description: This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. lsb: 16 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/atimer.csv000066400000000000000000000015511435536612600233760ustar00rootroot00000000000000ATIMER_DOWNCOUNTER,0,16,CVAL,When equal to zero an interrupt is raised,0,rw ATIMER_PRESET,0,16,PRESETVAL,Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero,0,rw ATIMER_CLR_EN,0,1,CLR_EN,Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register,0,w ATIMER_SET_EN,0,1,SET_EN,Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register,0,w ATIMER_STATUS,0,1,STAT,A 1 in this bit shows that the STATUS interrupt has been raised,0,r ATIMER_ENABLE,0,1,ENA,A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register,0,r ATIMER_CLR_STAT,0,1,CSTAT,Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register,0,w ATIMER_SET_STAT,0,1,SSTAT,Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register,0,w hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/atimer.yaml000066400000000000000000000035241435536612600235470ustar00rootroot00000000000000!!omap - ATIMER_DOWNCOUNTER: fields: !!omap - CVAL: access: rw description: When equal to zero an interrupt is raised lsb: 0 reset_value: '0' width: 16 - ATIMER_PRESET: fields: !!omap - PRESETVAL: access: rw description: Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero lsb: 0 reset_value: '0' width: 16 - ATIMER_CLR_EN: fields: !!omap - CLR_EN: access: w description: Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register lsb: 0 reset_value: '0' width: 1 - ATIMER_SET_EN: fields: !!omap - SET_EN: access: w description: Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register lsb: 0 reset_value: '0' width: 1 - ATIMER_STATUS: fields: !!omap - STAT: access: r description: A 1 in this bit shows that the STATUS interrupt has been raised lsb: 0 reset_value: '0' width: 1 - ATIMER_ENABLE: fields: !!omap - ENA: access: r description: A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register lsb: 0 reset_value: '0' width: 1 - ATIMER_CLR_STAT: fields: !!omap - CSTAT: access: w description: Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register lsb: 0 reset_value: '0' width: 1 - ATIMER_SET_STAT: fields: !!omap - SSTAT: access: w description: Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register lsb: 0 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/ccu.csv000066400000000000000000000550651435536612600227000ustar00rootroot00000000000000CCU1_PM,0,1,PD,Initiate power-down mode,0,rw CCU1_BASE_STAT,0,1,BASE_APB3_CLK_IND,Base clock indicator for BASE_APB3_CLK,1,r CCU1_BASE_STAT,1,1,BASE_APB1_CLK_IND,Base clock indicator for BASE_APB1_CLK,1,r CCU1_BASE_STAT,2,1,BASE_SPIFI_CLK_IND,Base clock indicator for BASE_SPIFI_CLK,1,r CCU1_BASE_STAT,3,1,BASE_M4_CLK_IND,Base clock indicator for BASE_M4_CLK,1,r CCU1_BASE_STAT,6,1,BASE_PERIPH_CLK_IND,Base clock indicator for BASE_PERIPH_CLK,1,r CCU1_BASE_STAT,7,1,BASE_USB0_CLK_IND,Base clock indicator for BASE_USB0_CLK,1,r CCU1_BASE_STAT,8,1,BASE_USB1_CLK_IND,Base clock indicator for BASE_USB1_CLK,1,r CCU1_BASE_STAT,9,1,BASE_SPI_CLK_IND,Base clock indicator for BASE_SPI_CLK,1,r CCU1_CLK_APB3_BUS_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB3_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB3_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB3_BUS_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB3_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB3_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB3_I2C1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB3_I2C1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB3_I2C1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB3_I2C1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB3_I2C1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB3_I2C1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB3_DAC_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB3_DAC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB3_DAC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB3_DAC_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB3_DAC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB3_DAC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB3_ADC0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB3_ADC0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB3_ADC0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB3_ADC0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB3_ADC0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB3_ADC0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB3_ADC1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB3_ADC1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB3_ADC1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB3_ADC1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB3_ADC1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB3_ADC1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB3_CAN0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB3_CAN0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB3_CAN0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB3_CAN0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB3_CAN0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB3_CAN0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB1_BUS_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB1_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB1_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB1_BUS_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB1_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB1_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB1_MOTOCONPWM_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB1_MOTOCONPWM_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB1_MOTOCONPWM_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB1_MOTOCONPWM_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB1_MOTOCONPWM_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB1_MOTOCONPWM_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB1_I2C0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB1_I2C0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB1_I2C0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB1_I2C0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB1_I2C0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB1_I2C0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB1_I2S_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB1_I2S_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB1_I2S_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB1_I2S_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB1_I2S_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB1_I2S_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_APB1_CAN1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_APB1_CAN1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_APB1_CAN1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_APB1_CAN1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_APB1_CAN1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_APB1_CAN1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_SPIFI_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_SPIFI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_SPIFI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_SPIFI_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_SPIFI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_SPIFI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_BUS_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_BUS_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_SPIFI_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_SPIFI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_SPIFI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_SPIFI_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_SPIFI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_SPIFI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_GPIO_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_GPIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_GPIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_GPIO_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_GPIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_GPIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_LCD_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_LCD_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_LCD_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_LCD_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_LCD_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_LCD_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_ETHERNET_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_ETHERNET_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_ETHERNET_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_ETHERNET_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_ETHERNET_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_ETHERNET_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_USB0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_USB0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_USB0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_USB0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_USB0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_USB0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_EMC_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_EMC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_EMC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_EMC_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_EMC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_EMC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_SDIO_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_SDIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_SDIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_SDIO_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_SDIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_SDIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_DMA_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_DMA_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_DMA_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_DMA_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_DMA_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_DMA_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_M4CORE_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_M4CORE_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_M4CORE_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_M4CORE_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_M4CORE_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_M4CORE_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_SCT_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_SCT_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_SCT_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_SCT_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_SCT_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_SCT_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_USB1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_USB1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_USB1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_USB1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_USB1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_USB1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_EMCDIV_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_EMCDIV_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_EMCDIV_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_EMCDIV_CFG,5,3,DIV,Clock divider value,0,rw CCU1_CLK_M4_EMCDIV_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_EMCDIV_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_EMCDIV_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_M0APP_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_M0APP_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_M0APP_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_M0APP_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_M0APP_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_M0APP_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_VADC_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_VADC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_VADC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_VADC_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_VADC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_VADC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_WWDT_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_WWDT_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_WWDT_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_WWDT_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_WWDT_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_WWDT_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_USART0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_USART0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_USART0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_USART0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_USART0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_USART0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_UART1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_UART1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_UART1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_UART1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_UART1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_UART1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_SSP0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_SSP0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_SSP0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_SSP0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_SSP0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_SSP0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_TIMER0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_TIMER0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_TIMER0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_TIMER0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_TIMER0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_TIMER0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_TIMER1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_TIMER1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_TIMER1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_TIMER1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_TIMER1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_TIMER1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_SCU_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_SCU_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_SCU_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_SCU_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_SCU_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_SCU_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_CREG_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_CREG_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_CREG_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_CREG_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_CREG_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_CREG_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_RITIMER_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_RITIMER_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_RITIMER_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_RITIMER_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_RITIMER_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_RITIMER_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_USART2_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_USART2_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_USART2_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_USART2_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_USART2_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_USART2_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_USART3_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_USART3_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_USART3_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_USART3_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_USART3_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_USART3_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_TIMER2_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_TIMER2_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_TIMER2_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_TIMER2_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_TIMER2_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_TIMER2_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_TIMER3_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_TIMER3_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_TIMER3_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_TIMER3_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_TIMER3_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_TIMER3_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_SSP1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_SSP1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_SSP1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_SSP1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_SSP1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_SSP1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_M4_QEI_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_M4_QEI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_M4_QEI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_M4_QEI_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_M4_QEI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_M4_QEI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_PERIPH_BUS_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_PERIPH_BUS_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_PERIPH_BUS_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_PERIPH_BUS_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_PERIPH_BUS_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_PERIPH_BUS_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_PERIPH_CORE_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_PERIPH_CORE_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_PERIPH_CORE_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_PERIPH_CORE_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_PERIPH_CORE_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_PERIPH_CORE_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_PERIPH_SGPIO_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_PERIPH_SGPIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_PERIPH_SGPIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_PERIPH_SGPIO_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_PERIPH_SGPIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_PERIPH_SGPIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_USB0_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_USB0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_USB0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_USB0_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_USB0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_USB0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_USB1_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_USB1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_USB1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_USB1_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_USB1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_USB1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_SPI_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_SPI_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_SPI_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_SPI_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_SPI_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_SPI_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU1_CLK_VADC_CFG,0,1,RUN,Run enable,1,rw CCU1_CLK_VADC_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU1_CLK_VADC_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU1_CLK_VADC_STAT,0,1,RUN,Run enable status,1,r CCU1_CLK_VADC_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU1_CLK_VADC_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_PM,0,1,PD,Initiate power-down mode,0,rw CCU2_BASE_STAT,1,1,BASE_UART3_CLK_IND,Base clock indicator for BASE_UART3_CLK,1,r CCU2_BASE_STAT,2,1,BASE_UART2_CLK_IND,Base clock indicator for BASE_UART2_CLK,1,r CCU2_BASE_STAT,3,1,BASE_UART1_CLK_IND,Base clock indicator for BASE_UART1_CLK,1,r CCU2_BASE_STAT,4,1,BASE_UART0_CLK_IND,Base clock indicator for BASE_UART0_CLK,1,r CCU2_BASE_STAT,5,1,BASE_SSP1_CLK_IND,Base clock indicator for BASE_SSP1_CLK,1,r CCU2_BASE_STAT,6,1,BASE_SSP0_CLK_IND,Base clock indicator for BASE_SSP0_CLK,1,r CCU2_CLK_APLL_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_APLL_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_APLL_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_APLL_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_APLL_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_APLL_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_CLK_APB2_USART3_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_APB2_USART3_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_APB2_USART3_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_APB2_USART3_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_APB2_USART3_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_APB2_USART3_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_CLK_APB2_USART2_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_APB2_USART2_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_APB2_USART2_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_APB2_USART2_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_APB2_USART2_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_APB2_USART2_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_CLK_APB0_UART1_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_APB0_UART1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_APB0_UART1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_APB0_UART1_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_APB0_UART1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_APB0_UART1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_CLK_APB0_USART0_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_APB0_USART0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_APB0_USART0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_APB0_USART0_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_APB0_USART0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_APB0_USART0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_CLK_APB2_SSP1_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_APB2_SSP1_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_APB2_SSP1_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_APB2_SSP1_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_APB2_SSP1_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_APB2_SSP1_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_CLK_APB0_SSP0_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_APB0_SSP0_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_APB0_SSP0_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_APB0_SSP0_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_APB0_SSP0_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_APB0_SSP0_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r CCU2_CLK_SDIO_CFG,0,1,RUN,Run enable,1,rw CCU2_CLK_SDIO_CFG,1,1,AUTO,Auto (AHB disable mechanism) enable,0,rw CCU2_CLK_SDIO_CFG,2,1,WAKEUP,Wake-up mechanism enable,0,rw CCU2_CLK_SDIO_STAT,0,1,RUN,Run enable status,1,r CCU2_CLK_SDIO_STAT,1,1,AUTO,Auto (AHB disable mechanism) enable status,0,r CCU2_CLK_SDIO_STAT,2,1,WAKEUP,Wake-up mechanism enable status,0,r hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/ccu.yaml000066400000000000000000001523141435536612600230420ustar00rootroot00000000000000!!omap - CCU1_PM: fields: !!omap - PD: access: rw description: Initiate power-down mode lsb: 0 reset_value: '0' width: 1 - CCU1_BASE_STAT: fields: !!omap - BASE_APB3_CLK_IND: access: r description: Base clock indicator for BASE_APB3_CLK lsb: 0 reset_value: '1' width: 1 - BASE_APB1_CLK_IND: access: r description: Base clock indicator for BASE_APB1_CLK lsb: 1 reset_value: '1' width: 1 - BASE_SPIFI_CLK_IND: access: r description: Base clock indicator for BASE_SPIFI_CLK lsb: 2 reset_value: '1' width: 1 - BASE_M4_CLK_IND: access: r description: Base clock indicator for BASE_M4_CLK lsb: 3 reset_value: '1' width: 1 - BASE_PERIPH_CLK_IND: access: r description: Base clock indicator for BASE_PERIPH_CLK lsb: 6 reset_value: '1' width: 1 - BASE_USB0_CLK_IND: access: r description: Base clock indicator for BASE_USB0_CLK lsb: 7 reset_value: '1' width: 1 - BASE_USB1_CLK_IND: access: r description: Base clock indicator for BASE_USB1_CLK lsb: 8 reset_value: '1' width: 1 - BASE_SPI_CLK_IND: access: r description: Base clock indicator for BASE_SPI_CLK lsb: 9 reset_value: '1' width: 1 - CCU1_CLK_APB3_BUS_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_BUS_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_I2C1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_I2C1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_DAC_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_DAC_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_ADC0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_ADC0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_ADC1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_ADC1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_CAN0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB3_CAN0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_BUS_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_BUS_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_MOTOCONPWM_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_MOTOCONPWM_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_I2C0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_I2C0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_I2S_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_I2S_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_CAN1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_APB1_CAN1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_SPIFI_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_SPIFI_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_BUS_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_BUS_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SPIFI_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SPIFI_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_GPIO_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_GPIO_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_LCD_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_LCD_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_ETHERNET_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_ETHERNET_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USB0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USB0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_EMC_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_EMC_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SDIO_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SDIO_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_DMA_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_DMA_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_M4CORE_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_M4CORE_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SCT_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SCT_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USB1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USB1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_EMCDIV_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - DIV: access: rw description: Clock divider value lsb: 5 reset_value: '0' width: 3 - CCU1_CLK_M4_EMCDIV_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_M0APP_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_M0APP_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_VADC_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_VADC_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_WWDT_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_WWDT_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USART0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USART0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_UART1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_UART1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SSP0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SSP0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SCU_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SCU_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_CREG_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_CREG_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_RITIMER_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_RITIMER_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USART2_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USART2_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USART3_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_USART3_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER2_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER2_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER3_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_TIMER3_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SSP1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_SSP1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_QEI_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_M4_QEI_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_PERIPH_BUS_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_PERIPH_BUS_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_PERIPH_CORE_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_PERIPH_CORE_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_PERIPH_SGPIO_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_PERIPH_SGPIO_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_USB0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_USB0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_USB1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_USB1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_SPI_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_SPI_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_VADC_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU1_CLK_VADC_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_PM: fields: !!omap - PD: access: rw description: Initiate power-down mode lsb: 0 reset_value: '0' width: 1 - CCU2_BASE_STAT: fields: !!omap - BASE_UART3_CLK_IND: access: r description: Base clock indicator for BASE_UART3_CLK lsb: 1 reset_value: '1' width: 1 - BASE_UART2_CLK_IND: access: r description: Base clock indicator for BASE_UART2_CLK lsb: 2 reset_value: '1' width: 1 - BASE_UART1_CLK_IND: access: r description: Base clock indicator for BASE_UART1_CLK lsb: 3 reset_value: '1' width: 1 - BASE_UART0_CLK_IND: access: r description: Base clock indicator for BASE_UART0_CLK lsb: 4 reset_value: '1' width: 1 - BASE_SSP1_CLK_IND: access: r description: Base clock indicator for BASE_SSP1_CLK lsb: 5 reset_value: '1' width: 1 - BASE_SSP0_CLK_IND: access: r description: Base clock indicator for BASE_SSP0_CLK lsb: 6 reset_value: '1' width: 1 - CCU2_CLK_APLL_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APLL_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB2_USART3_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB2_USART3_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB2_USART2_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB2_USART2_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB0_UART1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB0_UART1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB0_USART0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB0_USART0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB2_SSP1_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB2_SSP1_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB0_SSP0_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_APB0_SSP0_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_SDIO_CFG: fields: !!omap - RUN: access: rw description: Run enable lsb: 0 reset_value: '1' width: 1 - AUTO: access: rw description: Auto (AHB disable mechanism) enable lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: rw description: Wake-up mechanism enable lsb: 2 reset_value: '0' width: 1 - CCU2_CLK_SDIO_STAT: fields: !!omap - RUN: access: r description: Run enable status lsb: 0 reset_value: '1' width: 1 - AUTO: access: r description: Auto (AHB disable mechanism) enable status lsb: 1 reset_value: '0' width: 1 - WAKEUP: access: r description: Wake-up mechanism enable status lsb: 2 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/cgu.csv000066400000000000000000000223051435536612600226730ustar00rootroot00000000000000CGU_FREQ_MON,0,9,RCNT,9-bit reference clock-counter value,0,rw CGU_FREQ_MON,9,14,FCNT,14-bit selected clock-counter value,0,r CGU_FREQ_MON,23,1,MEAS,Measure frequency,0,rw CGU_FREQ_MON,24,5,CLK_SEL,Clock-source selection for the clock to be measured,0,rw CGU_XTAL_OSC_CTRL,0,1,ENABLE,Oscillator-pad enable,1,rw CGU_XTAL_OSC_CTRL,1,1,BYPASS,Configure crystal operation or external-clock input pin XTAL1,0,rw CGU_XTAL_OSC_CTRL,2,1,HF,Select frequency range,1,rw CGU_PLL0USB_STAT,0,1,LOCK,PLL0 lock indicator,0,r CGU_PLL0USB_STAT,1,1,FR,PLL0 free running indicator,0,r CGU_PLL0USB_CTRL,0,1,PD,PLL0 power down,1,rw CGU_PLL0USB_CTRL,1,1,BYPASS,Input clock bypass control,1,rw CGU_PLL0USB_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw CGU_PLL0USB_CTRL,3,1,DIRECTO,PLL0 direct output,0,rw CGU_PLL0USB_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw CGU_PLL0USB_CTRL,6,1,FRM,Free running mode,0,rw CGU_PLL0USB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_PLL0USB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_PLL0USB_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw CGU_PLL0USB_MDIV,17,5,SELP,Bandwidth select P value,0x1C,rw CGU_PLL0USB_MDIV,22,6,SELI,Bandwidth select I value,0x17,rw CGU_PLL0USB_MDIV,28,4,SELR,Bandwidth select R value,0x0,rw CGU_PLL0USB_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw CGU_PLL0USB_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw CGU_PLL0AUDIO_STAT,0,1,LOCK,PLL0 lock indicator,0,r CGU_PLL0AUDIO_STAT,1,1,FR,PLL0 free running indicator,0,r CGU_PLL0AUDIO_CTRL,0,1,PD,PLL0 power down,1,rw CGU_PLL0AUDIO_CTRL,1,1,BYPASS,Input clock bypass control,1,rw CGU_PLL0AUDIO_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw CGU_PLL0AUDIO_CTRL,3,1,DIRECTO,PLL0 direct output,0,rw CGU_PLL0AUDIO_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw CGU_PLL0AUDIO_CTRL,6,1,FRM,Free running mode,0,rw CGU_PLL0AUDIO_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_PLL0AUDIO_CTRL,12,1,PLLFRACT_REQ,Fractional PLL word write request,0,rw CGU_PLL0AUDIO_CTRL,13,1,SEL_EXT,Select fractional divider,0,rw CGU_PLL0AUDIO_CTRL,14,1,MOD_PD,Sigma-Delta modulator power-down,1,rw CGU_PLL0AUDIO_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_PLL0AUDIO_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw CGU_PLL0AUDIO_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw CGU_PLL0AUDIO_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw CGU_PLL0AUDIO_FRAC,0,22,PLLFRACT_CTRL,PLL fractional divider control word,0x00,rw CGU_PLL1_STAT,0,1,LOCK,PLL1 lock indicator,0,r CGU_PLL1_CTRL,0,1,PD,PLL1 power down,1,rw CGU_PLL1_CTRL,1,1,BYPASS,Input clock bypass control,1,rw CGU_PLL1_CTRL,6,1,FBSEL,PLL feedback select,0,rw CGU_PLL1_CTRL,7,1,DIRECT,PLL direct CCO output,0,rw CGU_PLL1_CTRL,8,2,PSEL,Post-divider division ratio P,0x1,rw CGU_PLL1_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_PLL1_CTRL,12,2,NSEL,Pre-divider division ratio N,0x2,rw CGU_PLL1_CTRL,16,8,MSEL,Feedback-divider division ratio (M),0x18,rw CGU_PLL1_CTRL,24,5,CLK_SEL,Clock-source selection,0x01,rw CGU_IDIVA_CTRL,0,1,PD,Integer divider power down,0,rw CGU_IDIVA_CTRL,2,2,IDIV,Integer divider A divider value (1/(IDIV + 1)),0x0,rw CGU_IDIVA_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_IDIVA_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_IDIVB_CTRL,0,1,PD,Integer divider power down,0,rw CGU_IDIVB_CTRL,2,4,IDIV,Integer divider B divider value (1/(IDIV + 1)),0x0,rw CGU_IDIVB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_IDIVB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_IDIVC_CTRL,0,1,PD,Integer divider power down,0,rw CGU_IDIVC_CTRL,2,4,IDIV,Integer divider C divider value (1/(IDIV + 1)),0x0,rw CGU_IDIVC_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_IDIVC_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_IDIVD_CTRL,0,1,PD,Integer divider power down,0,rw CGU_IDIVD_CTRL,2,4,IDIV,Integer divider D divider value (1/(IDIV + 1)),0x0,rw CGU_IDIVD_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_IDIVD_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_IDIVE_CTRL,0,1,PD,Integer divider power down,0,rw CGU_IDIVE_CTRL,2,8,IDIV,Integer divider E divider value (1/(IDIV + 1)),0x00,rw CGU_IDIVE_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_IDIVE_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_SAFE_CLK,0,1,PD,Output stage power down,0,r CGU_BASE_SAFE_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,r CGU_BASE_SAFE_CLK,24,5,CLK_SEL,Clock source selection,0x01,r CGU_BASE_USB0_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_USB0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_USB0_CLK,24,5,CLK_SEL,Clock source selection,0x07,rw CGU_BASE_PERIPH_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_PERIPH_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_PERIPH_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_USB1_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_USB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_USB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_M4_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_M4_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_M4_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_SPIFI_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_SPIFI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_SPIFI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_SPI_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_SPI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_SPI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_PHY_RX_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_PHY_RX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_PHY_RX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_PHY_TX_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_PHY_TX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_PHY_TX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_APB1_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_APB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_APB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_APB3_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_APB3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_APB3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_LCD_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_LCD_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_LCD_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_VADC_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_VADC_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_VADC_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_SDIO_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_SDIO_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_SDIO_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_SSP0_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_SSP0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_SSP0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_SSP1_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_SSP1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_SSP1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_UART0_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_UART0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_UART0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_UART1_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_UART1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_UART1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_UART2_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_UART2_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_UART2_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_UART3_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_UART3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_UART3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_OUT_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_OUT_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_OUT_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_AUDIO_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_AUDIO_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_AUDIO_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_CGU_OUT0_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_CGU_OUT0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_CGU_OUT0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw CGU_BASE_CGU_OUT1_CLK,0,1,PD,Output stage power down,0,rw CGU_BASE_CGU_OUT1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw CGU_BASE_CGU_OUT1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/cgu.yaml000066400000000000000000000531141435536612600230440ustar00rootroot00000000000000!!omap - CGU_FREQ_MON: fields: !!omap - RCNT: access: rw description: 9-bit reference clock-counter value lsb: 0 reset_value: '0' width: 9 - FCNT: access: r description: 14-bit selected clock-counter value lsb: 9 reset_value: '0' width: 14 - MEAS: access: rw description: Measure frequency lsb: 23 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock-source selection for the clock to be measured lsb: 24 reset_value: '0' width: 5 - CGU_XTAL_OSC_CTRL: fields: !!omap - ENABLE: access: rw description: Oscillator-pad enable lsb: 0 reset_value: '1' width: 1 - BYPASS: access: rw description: Configure crystal operation or external-clock input pin XTAL1 lsb: 1 reset_value: '0' width: 1 - HF: access: rw description: Select frequency range lsb: 2 reset_value: '1' width: 1 - CGU_PLL0USB_STAT: fields: !!omap - LOCK: access: r description: PLL0 lock indicator lsb: 0 reset_value: '0' width: 1 - FR: access: r description: PLL0 free running indicator lsb: 1 reset_value: '0' width: 1 - CGU_PLL0USB_CTRL: fields: !!omap - PD: access: rw description: PLL0 power down lsb: 0 reset_value: '1' width: 1 - BYPASS: access: rw description: Input clock bypass control lsb: 1 reset_value: '1' width: 1 - DIRECTI: access: rw description: PLL0 direct input lsb: 2 reset_value: '0' width: 1 - DIRECTO: access: rw description: PLL0 direct output lsb: 3 reset_value: '0' width: 1 - CLKEN: access: rw description: PLL0 clock enable lsb: 4 reset_value: '0' width: 1 - FRM: access: rw description: Free running mode lsb: 6 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_PLL0USB_MDIV: fields: !!omap - MDEC: access: rw description: Decoded M-divider coefficient value lsb: 0 reset_value: '0x5B6A' width: 17 - SELP: access: rw description: Bandwidth select P value lsb: 17 reset_value: '0x1C' width: 5 - SELI: access: rw description: Bandwidth select I value lsb: 22 reset_value: '0x17' width: 6 - SELR: access: rw description: Bandwidth select R value lsb: 28 reset_value: '0x0' width: 4 - CGU_PLL0USB_NP_DIV: fields: !!omap - PDEC: access: rw description: Decoded P-divider coefficient value lsb: 0 reset_value: '0x02' width: 7 - NDEC: access: rw description: Decoded N-divider coefficient value lsb: 12 reset_value: '0xB1' width: 10 - CGU_PLL0AUDIO_STAT: fields: !!omap - LOCK: access: r description: PLL0 lock indicator lsb: 0 reset_value: '0' width: 1 - FR: access: r description: PLL0 free running indicator lsb: 1 reset_value: '0' width: 1 - CGU_PLL0AUDIO_CTRL: fields: !!omap - PD: access: rw description: PLL0 power down lsb: 0 reset_value: '1' width: 1 - BYPASS: access: rw description: Input clock bypass control lsb: 1 reset_value: '1' width: 1 - DIRECTI: access: rw description: PLL0 direct input lsb: 2 reset_value: '0' width: 1 - DIRECTO: access: rw description: PLL0 direct output lsb: 3 reset_value: '0' width: 1 - CLKEN: access: rw description: PLL0 clock enable lsb: 4 reset_value: '0' width: 1 - FRM: access: rw description: Free running mode lsb: 6 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - PLLFRACT_REQ: access: rw description: Fractional PLL word write request lsb: 12 reset_value: '0' width: 1 - SEL_EXT: access: rw description: Select fractional divider lsb: 13 reset_value: '0' width: 1 - MOD_PD: access: rw description: Sigma-Delta modulator power-down lsb: 14 reset_value: '1' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_PLL0AUDIO_MDIV: fields: !!omap - MDEC: access: rw description: Decoded M-divider coefficient value lsb: 0 reset_value: '0x5B6A' width: 17 - CGU_PLL0AUDIO_NP_DIV: fields: !!omap - PDEC: access: rw description: Decoded P-divider coefficient value lsb: 0 reset_value: '0x02' width: 7 - NDEC: access: rw description: Decoded N-divider coefficient value lsb: 12 reset_value: '0xB1' width: 10 - CGU_PLL0AUDIO_FRAC: fields: !!omap - PLLFRACT_CTRL: access: rw description: PLL fractional divider control word lsb: 0 reset_value: '0x00' width: 22 - CGU_PLL1_STAT: fields: !!omap - LOCK: access: r description: PLL1 lock indicator lsb: 0 reset_value: '0' width: 1 - CGU_PLL1_CTRL: fields: !!omap - PD: access: rw description: PLL1 power down lsb: 0 reset_value: '1' width: 1 - BYPASS: access: rw description: Input clock bypass control lsb: 1 reset_value: '1' width: 1 - FBSEL: access: rw description: PLL feedback select lsb: 6 reset_value: '0' width: 1 - DIRECT: access: rw description: PLL direct CCO output lsb: 7 reset_value: '0' width: 1 - PSEL: access: rw description: Post-divider division ratio P lsb: 8 reset_value: '0x1' width: 2 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - NSEL: access: rw description: Pre-divider division ratio N lsb: 12 reset_value: '0x2' width: 2 - MSEL: access: rw description: Feedback-divider division ratio (M) lsb: 16 reset_value: '0x18' width: 8 - CLK_SEL: access: rw description: Clock-source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_IDIVA_CTRL: fields: !!omap - PD: access: rw description: Integer divider power down lsb: 0 reset_value: '0' width: 1 - IDIV: access: rw description: Integer divider A divider value (1/(IDIV + 1)) lsb: 2 reset_value: '0x0' width: 2 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_IDIVB_CTRL: fields: !!omap - PD: access: rw description: Integer divider power down lsb: 0 reset_value: '0' width: 1 - IDIV: access: rw description: Integer divider B divider value (1/(IDIV + 1)) lsb: 2 reset_value: '0x0' width: 4 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_IDIVC_CTRL: fields: !!omap - PD: access: rw description: Integer divider power down lsb: 0 reset_value: '0' width: 1 - IDIV: access: rw description: Integer divider C divider value (1/(IDIV + 1)) lsb: 2 reset_value: '0x0' width: 4 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_IDIVD_CTRL: fields: !!omap - PD: access: rw description: Integer divider power down lsb: 0 reset_value: '0' width: 1 - IDIV: access: rw description: Integer divider D divider value (1/(IDIV + 1)) lsb: 2 reset_value: '0x0' width: 4 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_IDIVE_CTRL: fields: !!omap - PD: access: rw description: Integer divider power down lsb: 0 reset_value: '0' width: 1 - IDIV: access: rw description: Integer divider E divider value (1/(IDIV + 1)) lsb: 2 reset_value: '0x00' width: 8 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_SAFE_CLK: fields: !!omap - PD: access: r description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: r description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: r description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_USB0_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x07' width: 5 - CGU_BASE_PERIPH_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_USB1_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_M4_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_SPIFI_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_SPI_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_PHY_RX_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_PHY_TX_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_APB1_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_APB3_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_LCD_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_VADC_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_SDIO_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_SSP0_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_SSP1_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_UART0_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_UART1_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_UART2_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_UART3_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_OUT_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_AUDIO_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_CGU_OUT0_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 - CGU_BASE_CGU_OUT1_CLK: fields: !!omap - PD: access: rw description: Output stage power down lsb: 0 reset_value: '0' width: 1 - AUTOBLOCK: access: rw description: Block clock automatically during frequency change lsb: 11 reset_value: '0' width: 1 - CLK_SEL: access: rw description: Clock source selection lsb: 24 reset_value: '0x01' width: 5 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/creg.csv000066400000000000000000000070161435536612600230370ustar00rootroot00000000000000CREG_CREG0,0,1,EN1KHZ,Enable 1 kHz output,0,rw CREG_CREG0,1,1,EN32KHZ,Enable 32 kHz output,0,rw CREG_CREG0,2,1,RESET32KHZ,32 kHz oscillator reset,1,rw CREG_CREG0,3,1,PD32KHZ,32 kHz power control,1,rw CREG_CREG0,5,1,USB0PHY,USB0 PHY power control,1,rw CREG_CREG0,6,2,ALARMCTRL,RTC_ALARM pin output control,0,rw CREG_CREG0,8,2,BODLVL1,BOD trip level to generate an interrupt,0x3,rw CREG_CREG0,10,2,BODLVL2,BOD trip level to generate a reset,0x3,rw CREG_CREG0,12,2,SAMPLECTRL,SAMPLE pin input/output control,0,rw CREG_CREG0,14,2,WAKEUP0CTRL,WAKEUP0 pin input/output control,0,rw CREG_CREG0,16,2,WAKEUP1CTRL,WAKEUP1 pin input/output control,0,rw CREG_M4MEMMAP,12,20,M4MAP,Shadow address when accessing memory at address 0x00000000,0x10400000,rw CREG_CREG5,6,1,M4TAPSEL,JTAG debug select for M4 core,1,rw CREG_CREG5,9,1,M0APPTAPSEL,JTAG debug select for M0 co-processor,1,rw CREG_DMAMUX,0,2,DMAMUXPER0,Select DMA to peripheral connection for DMA peripheral 0,0,rw CREG_DMAMUX,2,2,DMAMUXPER1,Select DMA to peripheral connection for DMA peripheral 1,0,rw CREG_DMAMUX,4,2,DMAMUXPER2,Select DMA to peripheral connection for DMA peripheral 2,0,rw CREG_DMAMUX,6,2,DMAMUXPER3,Select DMA to peripheral connection for DMA peripheral 3,0,rw CREG_DMAMUX,8,2,DMAMUXPER4,Select DMA to peripheral connection for DMA peripheral 4,0,rw CREG_DMAMUX,10,2,DMAMUXPER5,Select DMA to peripheral connection for DMA peripheral 5,0,rw CREG_DMAMUX,12,2,DMAMUXPER6,Select DMA to peripheral connection for DMA peripheral 6,0,rw CREG_DMAMUX,14,2,DMAMUXPER7,Select DMA to peripheral connection for DMA peripheral 7,0,rw CREG_DMAMUX,16,2,DMAMUXPER8,Select DMA to peripheral connection for DMA peripheral 8,0,rw CREG_DMAMUX,18,2,DMAMUXPER9,Select DMA to peripheral connection for DMA peripheral 9,0,rw CREG_DMAMUX,20,2,DMAMUXPER10,Select DMA to peripheral connection for DMA peripheral 10,0,rw CREG_DMAMUX,22,2,DMAMUXPER11,Select DMA to peripheral connection for DMA peripheral 11,0,rw CREG_DMAMUX,24,2,DMAMUXPER12,Select DMA to peripheral connection for DMA peripheral 12,0,rw CREG_DMAMUX,26,2,DMAMUXPER13,Select DMA to peripheral connection for DMA peripheral 13,0,rw CREG_DMAMUX,28,2,DMAMUXPER14,Select DMA to peripheral connection for DMA peripheral 14,0,rw CREG_DMAMUX,30,2,DMAMUXPER15,Select DMA to peripheral connection for DMA peripheral 15,0,rw CREG_FLASHCFGA,12,4,FLASHTIM,Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access,,rw CREG_FLASHCFGA,31,1,POW,Flash bank A power control,1,rw CREG_FLASHCFGB,12,4,FLASHTIM,Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access,,rw CREG_FLASHCFGB,31,1,POW,Flash bank B power control,1,rw CREG_ETBCFG,0,1,ETB,Select SRAM interface,1,rw CREG_CREG6,0,3,ETHMODE,Selects the Ethernet mode. Reset the ethernet after changing the PHY interface,,rw CREG_CREG6,4,1,CTOUTCTRL,Selects the functionality of the SCT outputs,0,rw CREG_CREG6,12,1,I2S0_TX_SCK_IN_SEL,I2S0_TX_SCK input select,0,rw CREG_CREG6,13,1,I2S0_RX_SCK_IN_SEL,I2S0_RX_SCK input select,0,rw CREG_CREG6,14,1,I2S1_TX_SCK_IN_SEL,I2S1_TX_SCK input select,0,rw CREG_CREG6,15,1,I2S1_RX_SCK_IN_SEL,I2S1_RX_SCK input select,0,rw CREG_CREG6,16,1,EMC_CLK_SEL,EMC_CLK divided clock select,0,rw CREG_M4TXEVENT,0,1,TXEVCLR,Cortex-M4 TXEV event,0,rw CREG_M0TXEVENT,0,1,TXEVCLR,Cortex-M0 TXEV event,0,rw CREG_M0APPMEMMAP,12,20,M0APPMAP,Shadow address when accessing memory at address 0x00000000,0x20000000,rw CREG_USB0FLADJ,0,6,FLTV,Frame length timing value,0x20,rw CREG_USB1FLADJ,0,6,FLTV,Frame length timing value,0x20,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/creg.yaml000066400000000000000000000174651435536612600232170ustar00rootroot00000000000000!!omap - CREG_CREG0: fields: !!omap - EN1KHZ: access: rw description: Enable 1 kHz output lsb: 0 reset_value: '0' width: 1 - EN32KHZ: access: rw description: Enable 32 kHz output lsb: 1 reset_value: '0' width: 1 - RESET32KHZ: access: rw description: 32 kHz oscillator reset lsb: 2 reset_value: '1' width: 1 - PD32KHZ: access: rw description: 32 kHz power control lsb: 3 reset_value: '1' width: 1 - USB0PHY: access: rw description: USB0 PHY power control lsb: 5 reset_value: '1' width: 1 - ALARMCTRL: access: rw description: RTC_ALARM pin output control lsb: 6 reset_value: '0' width: 2 - BODLVL1: access: rw description: BOD trip level to generate an interrupt lsb: 8 reset_value: '0x3' width: 2 - BODLVL2: access: rw description: BOD trip level to generate a reset lsb: 10 reset_value: '0x3' width: 2 - SAMPLECTRL: access: rw description: SAMPLE pin input/output control lsb: 12 reset_value: '0' width: 2 - WAKEUP0CTRL: access: rw description: WAKEUP0 pin input/output control lsb: 14 reset_value: '0' width: 2 - WAKEUP1CTRL: access: rw description: WAKEUP1 pin input/output control lsb: 16 reset_value: '0' width: 2 - CREG_M4MEMMAP: fields: !!omap - M4MAP: access: rw description: Shadow address when accessing memory at address 0x00000000 lsb: 12 reset_value: '0x10400000' width: 20 - CREG_CREG5: fields: !!omap - M4TAPSEL: access: rw description: JTAG debug select for M4 core lsb: 6 reset_value: '1' width: 1 - M0APPTAPSEL: access: rw description: JTAG debug select for M0 co-processor lsb: 9 reset_value: '1' width: 1 - CREG_DMAMUX: fields: !!omap - DMAMUXPER0: access: rw description: Select DMA to peripheral connection for DMA peripheral 0 lsb: 0 reset_value: '0' width: 2 - DMAMUXPER1: access: rw description: Select DMA to peripheral connection for DMA peripheral 1 lsb: 2 reset_value: '0' width: 2 - DMAMUXPER2: access: rw description: Select DMA to peripheral connection for DMA peripheral 2 lsb: 4 reset_value: '0' width: 2 - DMAMUXPER3: access: rw description: Select DMA to peripheral connection for DMA peripheral 3 lsb: 6 reset_value: '0' width: 2 - DMAMUXPER4: access: rw description: Select DMA to peripheral connection for DMA peripheral 4 lsb: 8 reset_value: '0' width: 2 - DMAMUXPER5: access: rw description: Select DMA to peripheral connection for DMA peripheral 5 lsb: 10 reset_value: '0' width: 2 - DMAMUXPER6: access: rw description: Select DMA to peripheral connection for DMA peripheral 6 lsb: 12 reset_value: '0' width: 2 - DMAMUXPER7: access: rw description: Select DMA to peripheral connection for DMA peripheral 7 lsb: 14 reset_value: '0' width: 2 - DMAMUXPER8: access: rw description: Select DMA to peripheral connection for DMA peripheral 8 lsb: 16 reset_value: '0' width: 2 - DMAMUXPER9: access: rw description: Select DMA to peripheral connection for DMA peripheral 9 lsb: 18 reset_value: '0' width: 2 - DMAMUXPER10: access: rw description: Select DMA to peripheral connection for DMA peripheral 10 lsb: 20 reset_value: '0' width: 2 - DMAMUXPER11: access: rw description: Select DMA to peripheral connection for DMA peripheral 11 lsb: 22 reset_value: '0' width: 2 - DMAMUXPER12: access: rw description: Select DMA to peripheral connection for DMA peripheral 12 lsb: 24 reset_value: '0' width: 2 - DMAMUXPER13: access: rw description: Select DMA to peripheral connection for DMA peripheral 13 lsb: 26 reset_value: '0' width: 2 - DMAMUXPER14: access: rw description: Select DMA to peripheral connection for DMA peripheral 14 lsb: 28 reset_value: '0' width: 2 - DMAMUXPER15: access: rw description: Select DMA to peripheral connection for DMA peripheral 15 lsb: 30 reset_value: '0' width: 2 - CREG_FLASHCFGA: fields: !!omap - FLASHTIM: access: rw description: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access lsb: 12 reset_value: '' width: 4 - POW: access: rw description: Flash bank A power control lsb: 31 reset_value: '1' width: 1 - CREG_FLASHCFGB: fields: !!omap - FLASHTIM: access: rw description: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access lsb: 12 reset_value: '' width: 4 - POW: access: rw description: Flash bank B power control lsb: 31 reset_value: '1' width: 1 - CREG_ETBCFG: fields: !!omap - ETB: access: rw description: Select SRAM interface lsb: 0 reset_value: '1' width: 1 - CREG_CREG6: fields: !!omap - ETHMODE: access: rw description: Selects the Ethernet mode. Reset the ethernet after changing the PHY interface lsb: 0 reset_value: '' width: 3 - CTOUTCTRL: access: rw description: Selects the functionality of the SCT outputs lsb: 4 reset_value: '0' width: 1 - I2S0_TX_SCK_IN_SEL: access: rw description: I2S0_TX_SCK input select lsb: 12 reset_value: '0' width: 1 - I2S0_RX_SCK_IN_SEL: access: rw description: I2S0_RX_SCK input select lsb: 13 reset_value: '0' width: 1 - I2S1_TX_SCK_IN_SEL: access: rw description: I2S1_TX_SCK input select lsb: 14 reset_value: '0' width: 1 - I2S1_RX_SCK_IN_SEL: access: rw description: I2S1_RX_SCK input select lsb: 15 reset_value: '0' width: 1 - EMC_CLK_SEL: access: rw description: EMC_CLK divided clock select lsb: 16 reset_value: '0' width: 1 - CREG_M4TXEVENT: fields: !!omap - TXEVCLR: access: rw description: Cortex-M4 TXEV event lsb: 0 reset_value: '0' width: 1 - CREG_M0TXEVENT: fields: !!omap - TXEVCLR: access: rw description: Cortex-M0 TXEV event lsb: 0 reset_value: '0' width: 1 - CREG_M0APPMEMMAP: fields: !!omap - M0APPMAP: access: rw description: Shadow address when accessing memory at address 0x00000000 lsb: 12 reset_value: '0x20000000' width: 20 - CREG_USB0FLADJ: fields: !!omap - FLTV: access: rw description: Frame length timing value lsb: 0 reset_value: '0x20' width: 6 - CREG_USB1FLADJ: fields: !!omap - FLTV: access: rw description: Frame length timing value lsb: 0 reset_value: '0x20' width: 6 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/csv2yaml.py000077500000000000000000000021351435536612600235140ustar00rootroot00000000000000#!/usr/bin/env python import sys import yaml import csv from collections import OrderedDict import yaml_odict def convert_file(fname): reader = csv.reader(open(fname, 'r')) registers = OrderedDict() for register_name, lsb, width, field_name, description, reset_value, access in reader: if register_name not in registers: registers[register_name] = { 'fields': OrderedDict(), } register = registers[register_name] fields = register['fields'] if field_name in fields: raise RuntimeError('Duplicate field name "%s" in register "%s"' % field_name, register_name) else: fields[field_name] = { 'lsb': int(lsb), 'width': int(width), 'description': description, 'reset_value': reset_value, 'access': access, } with open(fname.replace('.csv', '.yaml'), 'w') as out_file: yaml.dump(registers, out_file, default_flow_style=False) for fname in sys.argv[1:]: convert_file(fname) hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/eventrouter.csv000066400000000000000000000344021435536612600245000ustar00rootroot00000000000000EVENTROUTER_HILO,0,1,WAKEUP0_L,Level detect mode for WAKEUP0 event,0,rw EVENTROUTER_HILO,1,1,WAKEUP1_L,Level detect mode for WAKEUP1 event,0,rw EVENTROUTER_HILO,2,1,WAKEUP2_L,Level detect mode for WAKEUP2 event,0,rw EVENTROUTER_HILO,3,1,WAKEUP3_L,Level detect mode for WAKEUP3 event,0,rw EVENTROUTER_HILO,4,1,ATIMER_L,Level detect mode for alarm timer event,0,rw EVENTROUTER_HILO,5,1,RTC_L,Level detect mode for RTC event,0,rw EVENTROUTER_HILO,6,1,BOD_L,Level detect mode for BOD event,0,rw EVENTROUTER_HILO,7,1,WWDT_L,Level detect mode for WWDT event,0,rw EVENTROUTER_HILO,8,1,ETH_L,Level detect mode for Ethernet event,0,rw EVENTROUTER_HILO,9,1,USB0_L,Level detect mode for USB0 event,0,rw EVENTROUTER_HILO,10,1,USB1_L,Level detect mode for USB1 event,0,rw EVENTROUTER_HILO,11,1,SDMMC_L,Level detect mode for SD/MMC event,0,rw EVENTROUTER_HILO,12,1,CAN_L,Level detect mode for C_CAN event,0,rw EVENTROUTER_HILO,13,1,TIM2_L,Level detect mode for combined timer output 2 event,0,rw EVENTROUTER_HILO,14,1,TIM6_L,Level detect mode for combined timer output 6 event,0,rw EVENTROUTER_HILO,15,1,QEI_L,Level detect mode for QEI event,0,rw EVENTROUTER_HILO,16,1,TIM14_L,Level detect mode for combined timer output 14 event,0,rw EVENTROUTER_HILO,19,1,RESET_L,Level detect mode for Reset,0,rw EVENTROUTER_EDGE,0,1,WAKEUP0_E,Edge/Level detect mode for WAKEUP0 event,0,rw EVENTROUTER_EDGE,1,1,WAKEUP1_E,Edge/Level detect mode for WAKEUP1 event,0,rw EVENTROUTER_EDGE,2,1,WAKEUP2_E,Edge/Level detect mode for WAKEUP2 event,0,rw EVENTROUTER_EDGE,3,1,WAKEUP3_E,Edge/Level detect mode for WAKEUP3 event,0,rw EVENTROUTER_EDGE,4,1,ATIMER_E,Edge/Level detect mode for alarm timer event,0,rw EVENTROUTER_EDGE,5,1,RTC_E,Edge/Level detect mode for RTC event,0,rw EVENTROUTER_EDGE,6,1,BOD_E,Edge/Level detect mode for BOD event,0,rw EVENTROUTER_EDGE,7,1,WWDT_E,Edge/Level detect mode for WWDT event,0,rw EVENTROUTER_EDGE,8,1,ETH_E,Edge/Level detect mode for Ethernet event,0,rw EVENTROUTER_EDGE,9,1,USB0_E,Edge/Level detect mode for USB0 event,0,rw EVENTROUTER_EDGE,10,1,USB1_E,Edge/Level detect mode for USB1 event,0,rw EVENTROUTER_EDGE,11,1,SDMMC_E,Edge/Level detect mode for SD/MMC event,0,rw EVENTROUTER_EDGE,12,1,CAN_E,Edge/Level detect mode for C_CAN event,0,rw EVENTROUTER_EDGE,13,1,TIM2_E,Edge/Level detect mode for combined timer output 2 event,0,rw EVENTROUTER_EDGE,14,1,TIM6_E,Edge/Level detect mode for combined timer output 6 event,0,rw EVENTROUTER_EDGE,15,1,QEI_E,Edge/Level detect mode for QEI event,0,rw EVENTROUTER_EDGE,16,1,TIM14_E,Edge/Level detect mode for combined timer output 14 event,0,rw EVENTROUTER_EDGE,19,1,RESET_E,Edge/Level detect mode for Reset,0,rw EVENTROUTER_CLR_EN,0,1,WAKEUP0_CLREN,Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register,0,w EVENTROUTER_CLR_EN,1,1,WAKEUP1_CLREN,Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register,0,w EVENTROUTER_CLR_EN,2,1,WAKEUP2_CLREN,Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register,0,w EVENTROUTER_CLR_EN,3,1,WAKEUP3_CLREN,Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register,0,w EVENTROUTER_CLR_EN,4,1,ATIMER_CLREN,Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register,0,w EVENTROUTER_CLR_EN,5,1,RTC_CLREN,Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register,0,w EVENTROUTER_CLR_EN,6,1,BOD_CLREN,Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register,0,w EVENTROUTER_CLR_EN,7,1,WWDT_CLREN,Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register,0,w EVENTROUTER_CLR_EN,8,1,ETH_CLREN,Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register,0,w EVENTROUTER_CLR_EN,9,1,USB0_CLREN,Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register,0,w EVENTROUTER_CLR_EN,10,1,USB1_CLREN,Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register,0,w EVENTROUTER_CLR_EN,11,1,SDMCC_CLREN,Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register,0,w EVENTROUTER_CLR_EN,12,1,CAN_CLREN,Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register,0,w EVENTROUTER_CLR_EN,13,1,TIM2_CLREN,Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register,0,w EVENTROUTER_CLR_EN,14,1,TIM6_CLREN,Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register,0,w EVENTROUTER_CLR_EN,15,1,QEI_CLREN,Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register,0,w EVENTROUTER_CLR_EN,16,1,TIM14_CLREN,Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register,0,w EVENTROUTER_CLR_EN,19,1,RESET_CLREN,Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register,0,w EVENTROUTER_SET_EN,0,1,WAKEUP0_SETEN,Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register,0,w EVENTROUTER_SET_EN,1,1,WAKEUP1_SETEN,Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register,0,w EVENTROUTER_SET_EN,2,1,WAKEUP2_SETEN,Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register,0,w EVENTROUTER_SET_EN,3,1,WAKEUP3_SETEN,Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register,0,w EVENTROUTER_SET_EN,4,1,ATIMER_SETEN,Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register,0,w EVENTROUTER_SET_EN,5,1,RTC_SETEN,Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register,0,w EVENTROUTER_SET_EN,6,1,BOD_SETEN,Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register,0,w EVENTROUTER_SET_EN,7,1,WWDT_SETEN,Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register,0,w EVENTROUTER_SET_EN,8,1,ETH_SETEN,Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register,0,w EVENTROUTER_SET_EN,9,1,USB0_SETEN,Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register,0,w EVENTROUTER_SET_EN,10,1,USB1_SETEN,Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register,0,w EVENTROUTER_SET_EN,11,1,SDMCC_SETEN,Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register,0,w EVENTROUTER_SET_EN,12,1,CAN_SETEN,Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register,0,w EVENTROUTER_SET_EN,13,1,TIM2_SETEN,Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register,0,w EVENTROUTER_SET_EN,14,1,TIM6_SETEN,Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register,0,w EVENTROUTER_SET_EN,15,1,QEI_SETEN,Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register,0,w EVENTROUTER_SET_EN,16,1,TIM14_SETEN,Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register,0,w EVENTROUTER_SET_EN,19,1,RESET_SETEN,Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register,0,w EVENTROUTER_STATUS,0,1,WAKEUP0_ST,A 1 in this bit shows that the WAKEUP0 event has been raised,1,r EVENTROUTER_STATUS,1,1,WAKEUP1_ST,A 1 in this bit shows that the WAKEUP1 event has been raised,1,r EVENTROUTER_STATUS,2,1,WAKEUP2_ST,A 1 in this bit shows that the WAKEUP2 event has been raised,1,r EVENTROUTER_STATUS,3,1,WAKEUP3_ST,A 1 in this bit shows that the WAKEUP3 event has been raised,1,r EVENTROUTER_STATUS,4,1,ATIMER_ST,A 1 in this bit shows that the ATIMER event has been raised,1,r EVENTROUTER_STATUS,5,1,RTC_ST,A 1 in this bit shows that the RTC event has been raised,1,r EVENTROUTER_STATUS,6,1,BOD_ST,A 1 in this bit shows that the BOD event has been raised,1,r EVENTROUTER_STATUS,7,1,WWDT_ST,A 1 in this bit shows that the WWDT event has been raised,1,r EVENTROUTER_STATUS,8,1,ETH_ST,A 1 in this bit shows that the ETH event has been raised,1,r EVENTROUTER_STATUS,9,1,USB0_ST,A 1 in this bit shows that the USB0 event has been raised,1,r EVENTROUTER_STATUS,10,1,USB1_ST,A 1 in this bit shows that the USB1 event has been raised,1,r EVENTROUTER_STATUS,11,1,SDMMC_ST,A 1 in this bit shows that the SDMMC event has been raised,1,r EVENTROUTER_STATUS,12,1,CAN_ST,A 1 in this bit shows that the CAN event has been raised,1,r EVENTROUTER_STATUS,13,1,TIM2_ST,A 1 in this bit shows that the combined timer 2 output event has been raised,1,r EVENTROUTER_STATUS,14,1,TIM6_ST,A 1 in this bit shows that the combined timer 6 output event has been raised,1,r EVENTROUTER_STATUS,15,1,QEI_ST,A 1 in this bit shows that the QEI event has been raised,1,r EVENTROUTER_STATUS,16,1,TIM14_ST,A 1 in this bit shows that the combined timer 14 output event has been raised,1,r EVENTROUTER_STATUS,19,1,RESET_ST,A 1 in this bit shows that the reset event has been raised,1,r EVENTROUTER_ENABLE,0,1,WAKEUP0_EN,A 1 in this bit shows that the WAKEUP0 event has been enabled,0,r EVENTROUTER_ENABLE,1,1,WAKEUP1_EN,A 1 in this bit shows that the WAKEUP1 event has been enabled,0,r EVENTROUTER_ENABLE,2,1,WAKEUP2_EN,A 1 in this bit shows that the WAKEUP2 event has been enabled,0,r EVENTROUTER_ENABLE,3,1,WAKEUP3_EN,A 1 in this bit shows that the WAKEUP3 event has been enabled,0,r EVENTROUTER_ENABLE,4,1,ATIMER_EN,A 1 in this bit shows that the ATIMER event has been enabled,0,r EVENTROUTER_ENABLE,5,1,RTC_EN,A 1 in this bit shows that the RTC event has been enabled,0,r EVENTROUTER_ENABLE,6,1,BOD_EN,A 1 in this bit shows that the BOD event has been enabled,0,r EVENTROUTER_ENABLE,7,1,WWDT_EN,A 1 in this bit shows that the WWDT event has been enabled,0,r EVENTROUTER_ENABLE,8,1,ETH_EN,A 1 in this bit shows that the ETH event has been enabled,0,r EVENTROUTER_ENABLE,9,1,USB0_EN,A 1 in this bit shows that the USB0 event has been enabled,0,r EVENTROUTER_ENABLE,10,1,USB1_EN,A 1 in this bit shows that the USB1 event has been enabled,0,r EVENTROUTER_ENABLE,11,1,SDMMC_EN,A 1 in this bit shows that the SDMMC event has been enabled,0,r EVENTROUTER_ENABLE,12,1,CAN_EN,A 1 in this bit shows that the CAN event has been enabled,0,r EVENTROUTER_ENABLE,13,1,TIM2_EN,A 1 in this bit shows that the combined timer 2 output event has been enabled,0,r EVENTROUTER_ENABLE,14,1,TIM6_EN,A 1 in this bit shows that the combined timer 6 output event has been enabled,0,r EVENTROUTER_ENABLE,15,1,QEI_EN,A 1 in this bit shows that the QEI event has been enabled,0,r EVENTROUTER_ENABLE,16,1,TIM14_EN,A 1 in this bit shows that the combined timer 14 output event has been enabled,0,r EVENTROUTER_ENABLE,19,1,RESET_EN,A 1 in this bit shows that the reset event has been enabled,0,r EVENTROUTER_CLR_STAT,0,1,WAKEUP0_CLRST,Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register,0,w EVENTROUTER_CLR_STAT,1,1,WAKEUP1_CLRST,Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register,0,w EVENTROUTER_CLR_STAT,2,1,WAKEUP2_CLRST,Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register,0,w EVENTROUTER_CLR_STAT,3,1,WAKEUP3_CLRST,Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register,0,w EVENTROUTER_CLR_STAT,4,1,ATIMER_CLRST,Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register,0,w EVENTROUTER_CLR_STAT,5,1,RTC_CLRST,Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register,0,w EVENTROUTER_CLR_STAT,6,1,BOD_CLRST,Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register,0,w EVENTROUTER_CLR_STAT,7,1,WWDT_CLRST,Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register,0,w EVENTROUTER_CLR_STAT,8,1,ETH_CLRST,Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register,0,w EVENTROUTER_CLR_STAT,9,1,USB0_CLRST,Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register,0,w EVENTROUTER_CLR_STAT,10,1,USB1_CLRST,Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register,0,w EVENTROUTER_CLR_STAT,11,1,SDMCC_CLRST,Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register,0,w EVENTROUTER_CLR_STAT,12,1,CAN_CLRST,Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register,0,w EVENTROUTER_CLR_STAT,13,1,TIM2_CLRST,Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register,0,w EVENTROUTER_CLR_STAT,14,1,TIM6_CLRST,Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register,0,w EVENTROUTER_CLR_STAT,15,1,QEI_CLRST,Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register,0,w EVENTROUTER_CLR_STAT,16,1,TIM14_CLRST,Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register,0,w EVENTROUTER_CLR_STAT,19,1,RESET_CLRST,Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register,0,w EVENTROUTER_SET_STAT,0,1,WAKEUP0_SETST,Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register,0,w EVENTROUTER_SET_STAT,1,1,WAKEUP1_SETST,Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register,0,w EVENTROUTER_SET_STAT,2,1,WAKEUP2_SETST,Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register,0,w EVENTROUTER_SET_STAT,3,1,WAKEUP3_SETST,Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register,0,w EVENTROUTER_SET_STAT,4,1,ATIMER_SETST,Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register,0,w EVENTROUTER_SET_STAT,5,1,RTC_SETST,Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register,0,w EVENTROUTER_SET_STAT,6,1,BOD_SETST,Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register,0,w EVENTROUTER_SET_STAT,7,1,WWDT_SETST,Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register,0,w EVENTROUTER_SET_STAT,8,1,ETH_SETST,Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register,0,w EVENTROUTER_SET_STAT,9,1,USB0_SETST,Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register,0,w EVENTROUTER_SET_STAT,10,1,USB1_SETST,Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register,0,w EVENTROUTER_SET_STAT,11,1,SDMCC_SETST,Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register,0,w EVENTROUTER_SET_STAT,12,1,CAN_SETST,Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register,0,w EVENTROUTER_SET_STAT,13,1,TIM2_SETST,Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register,0,w EVENTROUTER_SET_STAT,14,1,TIM6_SETST,Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register,0,w EVENTROUTER_SET_STAT,15,1,QEI_SETST,Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register,0,w EVENTROUTER_SET_STAT,16,1,TIM14_SETST,Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register,0,w EVENTROUTER_SET_STAT,19,1,RESET_SETST,Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register,0,w hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/eventrouter.yaml000066400000000000000000000640351435536612600246540ustar00rootroot00000000000000!!omap - EVENTROUTER_HILO: fields: !!omap - WAKEUP0_L: access: rw description: Level detect mode for WAKEUP0 event lsb: 0 reset_value: '0' width: 1 - WAKEUP1_L: access: rw description: Level detect mode for WAKEUP1 event lsb: 1 reset_value: '0' width: 1 - WAKEUP2_L: access: rw description: Level detect mode for WAKEUP2 event lsb: 2 reset_value: '0' width: 1 - WAKEUP3_L: access: rw description: Level detect mode for WAKEUP3 event lsb: 3 reset_value: '0' width: 1 - ATIMER_L: access: rw description: Level detect mode for alarm timer event lsb: 4 reset_value: '0' width: 1 - RTC_L: access: rw description: Level detect mode for RTC event lsb: 5 reset_value: '0' width: 1 - BOD_L: access: rw description: Level detect mode for BOD event lsb: 6 reset_value: '0' width: 1 - WWDT_L: access: rw description: Level detect mode for WWDT event lsb: 7 reset_value: '0' width: 1 - ETH_L: access: rw description: Level detect mode for Ethernet event lsb: 8 reset_value: '0' width: 1 - USB0_L: access: rw description: Level detect mode for USB0 event lsb: 9 reset_value: '0' width: 1 - USB1_L: access: rw description: Level detect mode for USB1 event lsb: 10 reset_value: '0' width: 1 - SDMMC_L: access: rw description: Level detect mode for SD/MMC event lsb: 11 reset_value: '0' width: 1 - CAN_L: access: rw description: Level detect mode for C_CAN event lsb: 12 reset_value: '0' width: 1 - TIM2_L: access: rw description: Level detect mode for combined timer output 2 event lsb: 13 reset_value: '0' width: 1 - TIM6_L: access: rw description: Level detect mode for combined timer output 6 event lsb: 14 reset_value: '0' width: 1 - QEI_L: access: rw description: Level detect mode for QEI event lsb: 15 reset_value: '0' width: 1 - TIM14_L: access: rw description: Level detect mode for combined timer output 14 event lsb: 16 reset_value: '0' width: 1 - RESET_L: access: rw description: Level detect mode for Reset lsb: 19 reset_value: '0' width: 1 - EVENTROUTER_EDGE: fields: !!omap - WAKEUP0_E: access: rw description: Edge/Level detect mode for WAKEUP0 event lsb: 0 reset_value: '0' width: 1 - WAKEUP1_E: access: rw description: Edge/Level detect mode for WAKEUP1 event lsb: 1 reset_value: '0' width: 1 - WAKEUP2_E: access: rw description: Edge/Level detect mode for WAKEUP2 event lsb: 2 reset_value: '0' width: 1 - WAKEUP3_E: access: rw description: Edge/Level detect mode for WAKEUP3 event lsb: 3 reset_value: '0' width: 1 - ATIMER_E: access: rw description: Edge/Level detect mode for alarm timer event lsb: 4 reset_value: '0' width: 1 - RTC_E: access: rw description: Edge/Level detect mode for RTC event lsb: 5 reset_value: '0' width: 1 - BOD_E: access: rw description: Edge/Level detect mode for BOD event lsb: 6 reset_value: '0' width: 1 - WWDT_E: access: rw description: Edge/Level detect mode for WWDT event lsb: 7 reset_value: '0' width: 1 - ETH_E: access: rw description: Edge/Level detect mode for Ethernet event lsb: 8 reset_value: '0' width: 1 - USB0_E: access: rw description: Edge/Level detect mode for USB0 event lsb: 9 reset_value: '0' width: 1 - USB1_E: access: rw description: Edge/Level detect mode for USB1 event lsb: 10 reset_value: '0' width: 1 - SDMMC_E: access: rw description: Edge/Level detect mode for SD/MMC event lsb: 11 reset_value: '0' width: 1 - CAN_E: access: rw description: Edge/Level detect mode for C_CAN event lsb: 12 reset_value: '0' width: 1 - TIM2_E: access: rw description: Edge/Level detect mode for combined timer output 2 event lsb: 13 reset_value: '0' width: 1 - TIM6_E: access: rw description: Edge/Level detect mode for combined timer output 6 event lsb: 14 reset_value: '0' width: 1 - QEI_E: access: rw description: Edge/Level detect mode for QEI event lsb: 15 reset_value: '0' width: 1 - TIM14_E: access: rw description: Edge/Level detect mode for combined timer output 14 event lsb: 16 reset_value: '0' width: 1 - RESET_E: access: rw description: Edge/Level detect mode for Reset lsb: 19 reset_value: '0' width: 1 - EVENTROUTER_CLR_EN: fields: !!omap - WAKEUP0_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register lsb: 0 reset_value: '0' width: 1 - WAKEUP1_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register lsb: 1 reset_value: '0' width: 1 - WAKEUP2_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register lsb: 2 reset_value: '0' width: 1 - WAKEUP3_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register lsb: 3 reset_value: '0' width: 1 - ATIMER_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register lsb: 4 reset_value: '0' width: 1 - RTC_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register lsb: 5 reset_value: '0' width: 1 - BOD_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register lsb: 6 reset_value: '0' width: 1 - WWDT_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register lsb: 7 reset_value: '0' width: 1 - ETH_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register lsb: 8 reset_value: '0' width: 1 - USB0_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register lsb: 9 reset_value: '0' width: 1 - USB1_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register lsb: 10 reset_value: '0' width: 1 - SDMCC_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register lsb: 11 reset_value: '0' width: 1 - CAN_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register lsb: 12 reset_value: '0' width: 1 - TIM2_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register lsb: 13 reset_value: '0' width: 1 - TIM6_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register lsb: 14 reset_value: '0' width: 1 - QEI_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register lsb: 15 reset_value: '0' width: 1 - TIM14_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register lsb: 16 reset_value: '0' width: 1 - RESET_CLREN: access: w description: Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register lsb: 19 reset_value: '0' width: 1 - EVENTROUTER_SET_EN: fields: !!omap - WAKEUP0_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register lsb: 0 reset_value: '0' width: 1 - WAKEUP1_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register lsb: 1 reset_value: '0' width: 1 - WAKEUP2_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register lsb: 2 reset_value: '0' width: 1 - WAKEUP3_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register lsb: 3 reset_value: '0' width: 1 - ATIMER_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register lsb: 4 reset_value: '0' width: 1 - RTC_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register lsb: 5 reset_value: '0' width: 1 - BOD_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register lsb: 6 reset_value: '0' width: 1 - WWDT_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register lsb: 7 reset_value: '0' width: 1 - ETH_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register lsb: 8 reset_value: '0' width: 1 - USB0_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register lsb: 9 reset_value: '0' width: 1 - USB1_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register lsb: 10 reset_value: '0' width: 1 - SDMCC_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register lsb: 11 reset_value: '0' width: 1 - CAN_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register lsb: 12 reset_value: '0' width: 1 - TIM2_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register lsb: 13 reset_value: '0' width: 1 - TIM6_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register lsb: 14 reset_value: '0' width: 1 - QEI_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register lsb: 15 reset_value: '0' width: 1 - TIM14_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register lsb: 16 reset_value: '0' width: 1 - RESET_SETEN: access: w description: Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register lsb: 19 reset_value: '0' width: 1 - EVENTROUTER_STATUS: fields: !!omap - WAKEUP0_ST: access: r description: A 1 in this bit shows that the WAKEUP0 event has been raised lsb: 0 reset_value: '1' width: 1 - WAKEUP1_ST: access: r description: A 1 in this bit shows that the WAKEUP1 event has been raised lsb: 1 reset_value: '1' width: 1 - WAKEUP2_ST: access: r description: A 1 in this bit shows that the WAKEUP2 event has been raised lsb: 2 reset_value: '1' width: 1 - WAKEUP3_ST: access: r description: A 1 in this bit shows that the WAKEUP3 event has been raised lsb: 3 reset_value: '1' width: 1 - ATIMER_ST: access: r description: A 1 in this bit shows that the ATIMER event has been raised lsb: 4 reset_value: '1' width: 1 - RTC_ST: access: r description: A 1 in this bit shows that the RTC event has been raised lsb: 5 reset_value: '1' width: 1 - BOD_ST: access: r description: A 1 in this bit shows that the BOD event has been raised lsb: 6 reset_value: '1' width: 1 - WWDT_ST: access: r description: A 1 in this bit shows that the WWDT event has been raised lsb: 7 reset_value: '1' width: 1 - ETH_ST: access: r description: A 1 in this bit shows that the ETH event has been raised lsb: 8 reset_value: '1' width: 1 - USB0_ST: access: r description: A 1 in this bit shows that the USB0 event has been raised lsb: 9 reset_value: '1' width: 1 - USB1_ST: access: r description: A 1 in this bit shows that the USB1 event has been raised lsb: 10 reset_value: '1' width: 1 - SDMMC_ST: access: r description: A 1 in this bit shows that the SDMMC event has been raised lsb: 11 reset_value: '1' width: 1 - CAN_ST: access: r description: A 1 in this bit shows that the CAN event has been raised lsb: 12 reset_value: '1' width: 1 - TIM2_ST: access: r description: A 1 in this bit shows that the combined timer 2 output event has been raised lsb: 13 reset_value: '1' width: 1 - TIM6_ST: access: r description: A 1 in this bit shows that the combined timer 6 output event has been raised lsb: 14 reset_value: '1' width: 1 - QEI_ST: access: r description: A 1 in this bit shows that the QEI event has been raised lsb: 15 reset_value: '1' width: 1 - TIM14_ST: access: r description: A 1 in this bit shows that the combined timer 14 output event has been raised lsb: 16 reset_value: '1' width: 1 - RESET_ST: access: r description: A 1 in this bit shows that the reset event has been raised lsb: 19 reset_value: '1' width: 1 - EVENTROUTER_ENABLE: fields: !!omap - WAKEUP0_EN: access: r description: A 1 in this bit shows that the WAKEUP0 event has been enabled lsb: 0 reset_value: '0' width: 1 - WAKEUP1_EN: access: r description: A 1 in this bit shows that the WAKEUP1 event has been enabled lsb: 1 reset_value: '0' width: 1 - WAKEUP2_EN: access: r description: A 1 in this bit shows that the WAKEUP2 event has been enabled lsb: 2 reset_value: '0' width: 1 - WAKEUP3_EN: access: r description: A 1 in this bit shows that the WAKEUP3 event has been enabled lsb: 3 reset_value: '0' width: 1 - ATIMER_EN: access: r description: A 1 in this bit shows that the ATIMER event has been enabled lsb: 4 reset_value: '0' width: 1 - RTC_EN: access: r description: A 1 in this bit shows that the RTC event has been enabled lsb: 5 reset_value: '0' width: 1 - BOD_EN: access: r description: A 1 in this bit shows that the BOD event has been enabled lsb: 6 reset_value: '0' width: 1 - WWDT_EN: access: r description: A 1 in this bit shows that the WWDT event has been enabled lsb: 7 reset_value: '0' width: 1 - ETH_EN: access: r description: A 1 in this bit shows that the ETH event has been enabled lsb: 8 reset_value: '0' width: 1 - USB0_EN: access: r description: A 1 in this bit shows that the USB0 event has been enabled lsb: 9 reset_value: '0' width: 1 - USB1_EN: access: r description: A 1 in this bit shows that the USB1 event has been enabled lsb: 10 reset_value: '0' width: 1 - SDMMC_EN: access: r description: A 1 in this bit shows that the SDMMC event has been enabled lsb: 11 reset_value: '0' width: 1 - CAN_EN: access: r description: A 1 in this bit shows that the CAN event has been enabled lsb: 12 reset_value: '0' width: 1 - TIM2_EN: access: r description: A 1 in this bit shows that the combined timer 2 output event has been enabled lsb: 13 reset_value: '0' width: 1 - TIM6_EN: access: r description: A 1 in this bit shows that the combined timer 6 output event has been enabled lsb: 14 reset_value: '0' width: 1 - QEI_EN: access: r description: A 1 in this bit shows that the QEI event has been enabled lsb: 15 reset_value: '0' width: 1 - TIM14_EN: access: r description: A 1 in this bit shows that the combined timer 14 output event has been enabled lsb: 16 reset_value: '0' width: 1 - RESET_EN: access: r description: A 1 in this bit shows that the reset event has been enabled lsb: 19 reset_value: '0' width: 1 - EVENTROUTER_CLR_STAT: fields: !!omap - WAKEUP0_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register lsb: 0 reset_value: '0' width: 1 - WAKEUP1_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register lsb: 1 reset_value: '0' width: 1 - WAKEUP2_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register lsb: 2 reset_value: '0' width: 1 - WAKEUP3_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register lsb: 3 reset_value: '0' width: 1 - ATIMER_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register lsb: 4 reset_value: '0' width: 1 - RTC_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register lsb: 5 reset_value: '0' width: 1 - BOD_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register lsb: 6 reset_value: '0' width: 1 - WWDT_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register lsb: 7 reset_value: '0' width: 1 - ETH_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register lsb: 8 reset_value: '0' width: 1 - USB0_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register lsb: 9 reset_value: '0' width: 1 - USB1_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register lsb: 10 reset_value: '0' width: 1 - SDMCC_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register lsb: 11 reset_value: '0' width: 1 - CAN_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register lsb: 12 reset_value: '0' width: 1 - TIM2_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register lsb: 13 reset_value: '0' width: 1 - TIM6_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register lsb: 14 reset_value: '0' width: 1 - QEI_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register lsb: 15 reset_value: '0' width: 1 - TIM14_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register lsb: 16 reset_value: '0' width: 1 - RESET_CLRST: access: w description: Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register lsb: 19 reset_value: '0' width: 1 - EVENTROUTER_SET_STAT: fields: !!omap - WAKEUP0_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register lsb: 0 reset_value: '0' width: 1 - WAKEUP1_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register lsb: 1 reset_value: '0' width: 1 - WAKEUP2_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register lsb: 2 reset_value: '0' width: 1 - WAKEUP3_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register lsb: 3 reset_value: '0' width: 1 - ATIMER_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register lsb: 4 reset_value: '0' width: 1 - RTC_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register lsb: 5 reset_value: '0' width: 1 - BOD_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register lsb: 6 reset_value: '0' width: 1 - WWDT_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register lsb: 7 reset_value: '0' width: 1 - ETH_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register lsb: 8 reset_value: '0' width: 1 - USB0_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register lsb: 9 reset_value: '0' width: 1 - USB1_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register lsb: 10 reset_value: '0' width: 1 - SDMCC_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register lsb: 11 reset_value: '0' width: 1 - CAN_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register lsb: 12 reset_value: '0' width: 1 - TIM2_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register lsb: 13 reset_value: '0' width: 1 - TIM6_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register lsb: 14 reset_value: '0' width: 1 - QEI_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register lsb: 15 reset_value: '0' width: 1 - TIM14_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register lsb: 16 reset_value: '0' width: 1 - RESET_SETST: access: w description: Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register lsb: 19 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/gen.py000077500000000000000000000017751435536612600225360ustar00rootroot00000000000000#!/usr/bin/env python import sys import yaml import yaml_odict from collections import OrderedDict from pprint import pprint registers = yaml.load(open(sys.argv[1], 'r')) for register_name, register in registers.iteritems(): print('/* --- %s values %s */' % (register_name, '-' * (50 - len(register_name)))) print fields = register['fields'] #for field_name, field in sorted(fields.items(), lambda x, y: cmp(x[1]['lsb'], y[1]['lsb'])): for field_name, field in fields.items(): mask_bits = (1 << field['width']) - 1 print('/* %s: %s */' % (field_name, field['description'])) print('#define %s_%s_SHIFT (%d)' % ( register_name, field_name, field['lsb'], )) print('#define %s_%s_MASK (0x%x << %s_%s_SHIFT)' % ( register_name, field_name, mask_bits, register_name, field_name, )) print('#define %s_%s(x) ((x) << %s_%s_SHIFT)' % ( register_name, field_name, register_name, field_name, )) print hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/gima.csv000066400000000000000000000173221435536612600230350ustar00rootroot00000000000000GIMA_CAP0_0_IN,0,1,INV,Invert input,0,rw GIMA_CAP0_0_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP0_0_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP0_0_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP0_0_IN,4,4,SELECT,Select input,0,rw GIMA_CAP0_1_IN,0,1,INV,Invert input,0,rw GIMA_CAP0_1_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP0_1_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP0_1_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP0_1_IN,4,4,SELECT,Select input,0,rw GIMA_CAP0_2_IN,0,1,INV,Invert input,0,rw GIMA_CAP0_2_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP0_2_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP0_2_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP0_2_IN,4,4,SELECT,Select input,0,rw GIMA_CAP0_3_IN,0,1,INV,Invert input,0,rw GIMA_CAP0_3_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP0_3_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP0_3_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP0_3_IN,4,4,SELECT,Select input,0,rw GIMA_CAP1_0_IN,0,1,INV,Invert input,0,rw GIMA_CAP1_0_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP1_0_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP1_0_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP1_0_IN,4,4,SELECT,Select input,0,rw GIMA_CAP1_1_IN,0,1,INV,Invert input,0,rw GIMA_CAP1_1_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP1_1_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP1_1_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP1_1_IN,4,4,SELECT,Select input,0,rw GIMA_CAP1_2_IN,0,1,INV,Invert input,0,rw GIMA_CAP1_2_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP1_2_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP1_2_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP1_2_IN,4,4,SELECT,Select input,0,rw GIMA_CAP1_3_IN,0,1,INV,Invert input,0,rw GIMA_CAP1_3_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP1_3_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP1_3_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP1_3_IN,4,4,SELECT,Select input,0,rw GIMA_CAP2_0_IN,0,1,INV,Invert input,0,rw GIMA_CAP2_0_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP2_0_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP2_0_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP2_0_IN,4,4,SELECT,Select input,0,rw GIMA_CAP2_1_IN,0,1,INV,Invert input,0,rw GIMA_CAP2_1_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP2_1_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP2_1_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP2_1_IN,4,4,SELECT,Select input,0,rw GIMA_CAP2_2_IN,0,1,INV,Invert input,0,rw GIMA_CAP2_2_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP2_2_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP2_2_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP2_2_IN,4,4,SELECT,Select input,0,rw GIMA_CAP2_3_IN,0,1,INV,Invert input,0,rw GIMA_CAP2_3_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP2_3_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP2_3_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP2_3_IN,4,4,SELECT,Select input,0,rw GIMA_CAP3_0_IN,0,1,INV,Invert input,0,rw GIMA_CAP3_0_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP3_0_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP3_0_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP3_0_IN,4,4,SELECT,Select input,0,rw GIMA_CAP3_1_IN,0,1,INV,Invert input,0,rw GIMA_CAP3_1_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP3_1_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP3_1_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP3_1_IN,4,4,SELECT,Select input,0,rw GIMA_CAP3_2_IN,0,1,INV,Invert input,0,rw GIMA_CAP3_2_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP3_2_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP3_2_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP3_2_IN,4,4,SELECT,Select input,0,rw GIMA_CAP3_3_IN,0,1,INV,Invert input,0,rw GIMA_CAP3_3_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CAP3_3_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CAP3_3_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CAP3_3_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_0_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_0_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_0_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_0_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_0_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_1_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_1_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_1_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_1_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_1_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_2_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_2_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_2_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_2_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_2_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_3_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_3_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_3_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_3_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_3_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_4_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_4_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_4_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_4_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_4_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_5_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_5_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_5_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_5_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_5_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_6_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_6_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_6_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_6_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_6_IN,4,4,SELECT,Select input,0,rw GIMA_CTIN_7_IN,0,1,INV,Invert input,0,rw GIMA_CTIN_7_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_CTIN_7_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_CTIN_7_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_CTIN_7_IN,4,4,SELECT,Select input,0,rw GIMA_VADC_TRIGGER_IN,0,1,INV,Invert input,0,rw GIMA_VADC_TRIGGER_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_VADC_TRIGGER_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_VADC_TRIGGER_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_VADC_TRIGGER_IN,4,4,SELECT,Select input,0,rw GIMA_EVENTROUTER_13_IN,0,1,INV,Invert input,0,rw GIMA_EVENTROUTER_13_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_EVENTROUTER_13_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_EVENTROUTER_13_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_EVENTROUTER_13_IN,4,4,SELECT,Select input,0,rw GIMA_EVENTROUTER_14_IN,0,1,INV,Invert input,0,rw GIMA_EVENTROUTER_14_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_EVENTROUTER_14_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_EVENTROUTER_14_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_EVENTROUTER_14_IN,4,4,SELECT,Select input,0,rw GIMA_EVENTROUTER_16_IN,0,1,INV,Invert input,0,rw GIMA_EVENTROUTER_16_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_EVENTROUTER_16_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_EVENTROUTER_16_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_EVENTROUTER_16_IN,4,4,SELECT,Select input,0,rw GIMA_ADCSTART0_IN,0,1,INV,Invert input,0,rw GIMA_ADCSTART0_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_ADCSTART0_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_ADCSTART0_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_ADCSTART0_IN,4,4,SELECT,Select input,0,rw GIMA_ADCSTART1_IN,0,1,INV,Invert input,0,rw GIMA_ADCSTART1_IN,1,1,EDGE,Enable rising edge detection,0,rw GIMA_ADCSTART1_IN,2,1,SYNCH,Enable synchronization,0,rw GIMA_ADCSTART1_IN,3,1,PULSE,Enable single pulse generation,0,rw GIMA_ADCSTART1_IN,4,4,SELECT,Select input,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/gima.yaml000066400000000000000000000505771435536612600232150ustar00rootroot00000000000000!!omap - GIMA_CAP0_0_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP0_1_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP0_2_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP0_3_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP1_0_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP1_1_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP1_2_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP1_3_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP2_0_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP2_1_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP2_2_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP2_3_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP3_0_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP3_1_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP3_2_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CAP3_3_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_0_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_1_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_2_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_3_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_4_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_5_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_6_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_CTIN_7_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_VADC_TRIGGER_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_EVENTROUTER_13_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_EVENTROUTER_14_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_EVENTROUTER_16_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_ADCSTART0_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 - GIMA_ADCSTART1_IN: fields: !!omap - INV: access: rw description: Invert input lsb: 0 reset_value: '0' width: 1 - EDGE: access: rw description: Enable rising edge detection lsb: 1 reset_value: '0' width: 1 - SYNCH: access: rw description: Enable synchronization lsb: 2 reset_value: '0' width: 1 - PULSE: access: rw description: Enable single pulse generation lsb: 3 reset_value: '0' width: 1 - SELECT: access: rw description: Select input lsb: 4 reset_value: '0' width: 4 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/gpdma.csv000066400000000000000000000365441435536612600232170ustar00rootroot00000000000000GPDMA_NTSTAT,0,8,INTSTAT,Status of DMA channel interrupts after masking,0x00,r GPDMA_INTTCSTAT,0,8,INTTCSTAT,Terminal count interrupt request status for DMA channels,0x00,r GPDMA_INTTCCLEAR,0,8,INTTCCLEAR,Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels,0x00,w GPDMA_INTERRSTAT,0,8,INTERRSTAT,Interrupt error status for DMA channels,0x00,r GPDMA_INTERRCLR,0,8,INTERRCLR,Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels,0x00,w GPDMA_RAWINTTCSTAT,0,8,RAWINTTCSTAT,Status of the terminal count interrupt for DMA channels prior to masking,0x00,r GPDMA_RAWINTERRSTAT,0,8,RAWINTERRSTAT,Status of the error interrupt for DMA channels prior to masking,0x00,r GPDMA_ENBLDCHNS,0,8,ENABLEDCHANNELS,Enable status for DMA channels,0x00,r GPDMA_SOFTBREQ,0,16,SOFTBREQ,Software burst request flags for each of 16 possible sources,0x00,rw GPDMA_SOFTSREQ,0,16,SOFTSREQ,Software single transfer request flags for each of 16 possible sources,0x00,rw GPDMA_SOFTLBREQ,0,16,SOFTLBREQ,Software last burst request flags for each of 16 possible sources,0x00,rw GPDMA_SOFTLSREQ,0,16,SOFTLSREQ,Software last single transfer request flags for each of 16 possible sources,0x00,rw GPDMA_CONFIG,0,1,E,DMA Controller enable,0,rw GPDMA_CONFIG,1,1,M0,AHB Master 0 endianness configuration,0,rw GPDMA_CONFIG,2,1,M1,AHB Master 1 endianness configuration,0,rw GPDMA_SYNC,0,16,DMACSYNC,Controls the synchronization logic for DMA request signals,0x00,rw GPDMA_C0SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C1SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C2SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C3SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C4SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C5SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C6SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C7SRCADDR,0,32,SRCADDR,DMA source address,0x00000000,rw GPDMA_C0DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C1DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C2DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C3DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C4DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C5DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C6DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C7DESTADDR,0,32,DESTADDR,DMA source address,0x00000000,rw GPDMA_C0LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C0LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C1LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C1LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C2LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C2LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C3LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C3LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C4LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C4LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C5LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C5LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C6LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C6LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C7LLI,0,1,LM,AHB master select for loading the next LLI,0,rw GPDMA_C7LLI,2,30,LLI,Linked list item,0x00000000,rw GPDMA_C0CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C0CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C0CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C0CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C0CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C0CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C0CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C0CONTROL,26,1,SI,Source increment,0,rw GPDMA_C0CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C0CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C0CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C0CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C0CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C1CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C1CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C1CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C1CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C1CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C1CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C1CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C1CONTROL,26,1,SI,Source increment,0,rw GPDMA_C1CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C1CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C1CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C1CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C1CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C2CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C2CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C2CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C2CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C2CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C2CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C2CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C2CONTROL,26,1,SI,Source increment,0,rw GPDMA_C2CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C2CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C2CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C2CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C2CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C3CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C3CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C3CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C3CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C3CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C3CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C3CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C3CONTROL,26,1,SI,Source increment,0,rw GPDMA_C3CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C3CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C3CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C3CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C3CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C4CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C4CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C4CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C4CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C4CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C4CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C4CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C4CONTROL,26,1,SI,Source increment,0,rw GPDMA_C4CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C4CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C4CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C4CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C4CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C5CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C5CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C5CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C5CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C5CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C5CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C5CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C5CONTROL,26,1,SI,Source increment,0,rw GPDMA_C5CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C5CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C5CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C5CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C5CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C6CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C6CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C6CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C6CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C6CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C6CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C6CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C6CONTROL,26,1,SI,Source increment,0,rw GPDMA_C6CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C6CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C6CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C6CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C6CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C7CONTROL,0,12,TRANSFERSIZE,Transfer size in number of transfers,0x00,rw GPDMA_C7CONTROL,12,3,SBSIZE,Source burst size,0x0,rw GPDMA_C7CONTROL,15,3,DBSIZE,Destination burst size,0x0,rw GPDMA_C7CONTROL,18,3,SWIDTH,Source transfer width,0x0,rw GPDMA_C7CONTROL,21,3,DWIDTH,Destination transfer width,0x0,rw GPDMA_C7CONTROL,24,1,S,Source AHB master select,0,rw GPDMA_C7CONTROL,25,1,D,Destination AHB master select,0,rw GPDMA_C7CONTROL,26,1,SI,Source increment,0,rw GPDMA_C7CONTROL,27,1,DI,Destination increment,0,rw GPDMA_C7CONTROL,28,1,PROT1,This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode,0,rw GPDMA_C7CONTROL,29,1,PROT2,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable,0,rw GPDMA_C7CONTROL,30,1,PROT3,This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable,0,rw GPDMA_C7CONTROL,31,1,I,Terminal count interrupt enable bit,0,rw GPDMA_C0CONFIG,0,1,E,Channel enable,0,rw GPDMA_C0CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C0CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C0CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C0CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C0CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C0CONFIG,16,1,L,Lock,,rw GPDMA_C0CONFIG,17,1,A,Active,,r GPDMA_C0CONFIG,18,1,H,Halt,,rw GPDMA_C1CONFIG,0,1,E,Channel enable,0,rw GPDMA_C1CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C1CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C1CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C1CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C1CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C1CONFIG,16,1,L,Lock,,rw GPDMA_C1CONFIG,17,1,A,Active,,r GPDMA_C1CONFIG,18,1,H,Halt,,rw GPDMA_C2CONFIG,0,1,E,Channel enable,0,rw GPDMA_C2CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C2CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C2CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C2CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C2CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C2CONFIG,16,1,L,Lock,,rw GPDMA_C2CONFIG,17,1,A,Active,,r GPDMA_C2CONFIG,18,1,H,Halt,,rw GPDMA_C3CONFIG,0,1,E,Channel enable,0,rw GPDMA_C3CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C3CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C3CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C3CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C3CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C3CONFIG,16,1,L,Lock,,rw GPDMA_C3CONFIG,17,1,A,Active,,r GPDMA_C3CONFIG,18,1,H,Halt,,rw GPDMA_C4CONFIG,0,1,E,Channel enable,0,rw GPDMA_C4CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C4CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C4CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C4CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C4CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C4CONFIG,16,1,L,Lock,,rw GPDMA_C4CONFIG,17,1,A,Active,,r GPDMA_C4CONFIG,18,1,H,Halt,,rw GPDMA_C5CONFIG,0,1,E,Channel enable,0,rw GPDMA_C5CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C5CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C5CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C5CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C5CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C5CONFIG,16,1,L,Lock,,rw GPDMA_C5CONFIG,17,1,A,Active,,r GPDMA_C5CONFIG,18,1,H,Halt,,rw GPDMA_C6CONFIG,0,1,E,Channel enable,0,rw GPDMA_C6CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C6CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C6CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C6CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C6CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C6CONFIG,16,1,L,Lock,,rw GPDMA_C6CONFIG,17,1,A,Active,,r GPDMA_C6CONFIG,18,1,H,Halt,,rw GPDMA_C7CONFIG,0,1,E,Channel enable,0,rw GPDMA_C7CONFIG,1,5,SRCPERIPHERAL,Source peripheral,,rw GPDMA_C7CONFIG,6,5,DESTPERIPHERAL,Destination peripheral,,rw GPDMA_C7CONFIG,11,3,FLOWCNTRL,Flow control and transfer type,,rw GPDMA_C7CONFIG,14,1,IE,Interrupt error mask,,rw GPDMA_C7CONFIG,15,1,ITC,Terminal count interrupt mask,,rw GPDMA_C7CONFIG,16,1,L,Lock,,rw GPDMA_C7CONFIG,17,1,A,Active,,r GPDMA_C7CONFIG,18,1,H,Halt,,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/gpdma.yaml000066400000000000000000001062701435536612600233600ustar00rootroot00000000000000!!omap - GPDMA_INTSTAT: fields: !!omap - INTSTAT: access: r description: Status of DMA channel interrupts after masking lsb: 0 reset_value: '0x00' width: 8 - GPDMA_INTTCSTAT: fields: !!omap - INTTCSTAT: access: r description: Terminal count interrupt request status for DMA channels lsb: 0 reset_value: '0x00' width: 8 - GPDMA_INTTCCLEAR: fields: !!omap - INTTCCLEAR: access: w description: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels lsb: 0 reset_value: '0x00' width: 8 - GPDMA_INTERRSTAT: fields: !!omap - INTERRSTAT: access: r description: Interrupt error status for DMA channels lsb: 0 reset_value: '0x00' width: 8 - GPDMA_INTERRCLR: fields: !!omap - INTERRCLR: access: w description: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels lsb: 0 reset_value: '0x00' width: 8 - GPDMA_RAWINTTCSTAT: fields: !!omap - RAWINTTCSTAT: access: r description: Status of the terminal count interrupt for DMA channels prior to masking lsb: 0 reset_value: '0x00' width: 8 - GPDMA_RAWINTERRSTAT: fields: !!omap - RAWINTERRSTAT: access: r description: Status of the error interrupt for DMA channels prior to masking lsb: 0 reset_value: '0x00' width: 8 - GPDMA_ENBLDCHNS: fields: !!omap - ENABLEDCHANNELS: access: r description: Enable status for DMA channels lsb: 0 reset_value: '0x00' width: 8 - GPDMA_SOFTBREQ: fields: !!omap - SOFTBREQ: access: rw description: Software burst request flags for each of 16 possible sources lsb: 0 reset_value: '0x00' width: 16 - GPDMA_SOFTSREQ: fields: !!omap - SOFTSREQ: access: rw description: Software single transfer request flags for each of 16 possible sources lsb: 0 reset_value: '0x00' width: 16 - GPDMA_SOFTLBREQ: fields: !!omap - SOFTLBREQ: access: rw description: Software last burst request flags for each of 16 possible sources lsb: 0 reset_value: '0x00' width: 16 - GPDMA_SOFTLSREQ: fields: !!omap - SOFTLSREQ: access: rw description: Software last single transfer request flags for each of 16 possible sources lsb: 0 reset_value: '0x00' width: 16 - GPDMA_CONFIG: fields: !!omap - E: access: rw description: DMA Controller enable lsb: 0 reset_value: '0' width: 1 - M0: access: rw description: AHB Master 0 endianness configuration lsb: 1 reset_value: '0' width: 1 - M1: access: rw description: AHB Master 1 endianness configuration lsb: 2 reset_value: '0' width: 1 - GPDMA_SYNC: fields: !!omap - DMACSYNC: access: rw description: Controls the synchronization logic for DMA request signals lsb: 0 reset_value: '0x00' width: 16 - GPDMA_C0SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C1SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C2SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C3SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C4SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C5SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C6SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C7SRCADDR: fields: !!omap - SRCADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C0DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C1DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C2DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C3DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C4DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C5DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C6DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C7DESTADDR: fields: !!omap - DESTADDR: access: rw description: DMA source address lsb: 0 reset_value: '0x00000000' width: 32 - GPDMA_C0LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C1LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C2LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C3LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C4LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C5LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C6LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C7LLI: fields: !!omap - LM: access: rw description: AHB master select for loading the next LLI lsb: 0 reset_value: '0' width: 1 - LLI: access: rw description: Linked list item lsb: 2 reset_value: '0x00000000' width: 30 - GPDMA_C0CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C1CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C2CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C3CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C4CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C5CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C6CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C7CONTROL: fields: !!omap - TRANSFERSIZE: access: rw description: Transfer size in number of transfers lsb: 0 reset_value: '0x00' width: 12 - SBSIZE: access: rw description: Source burst size lsb: 12 reset_value: '0x0' width: 3 - DBSIZE: access: rw description: Destination burst size lsb: 15 reset_value: '0x0' width: 3 - SWIDTH: access: rw description: Source transfer width lsb: 18 reset_value: '0x0' width: 3 - DWIDTH: access: rw description: Destination transfer width lsb: 21 reset_value: '0x0' width: 3 - S: access: rw description: Source AHB master select lsb: 24 reset_value: '0' width: 1 - D: access: rw description: Destination AHB master select lsb: 25 reset_value: '0' width: 1 - SI: access: rw description: Source increment lsb: 26 reset_value: '0' width: 1 - DI: access: rw description: Destination increment lsb: 27 reset_value: '0' width: 1 - PROT1: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode lsb: 28 reset_value: '0' width: 1 - PROT2: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable lsb: 29 reset_value: '0' width: 1 - PROT3: access: rw description: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable lsb: 30 reset_value: '0' width: 1 - I: access: rw description: Terminal count interrupt enable bit lsb: 31 reset_value: '0' width: 1 - GPDMA_C0CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 - GPDMA_C1CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 - GPDMA_C2CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 - GPDMA_C3CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 - GPDMA_C4CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 - GPDMA_C5CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 - GPDMA_C6CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 - GPDMA_C7CONFIG: fields: !!omap - E: access: rw description: Channel enable lsb: 0 reset_value: '0' width: 1 - SRCPERIPHERAL: access: rw description: Source peripheral lsb: 1 reset_value: '' width: 5 - DESTPERIPHERAL: access: rw description: Destination peripheral lsb: 6 reset_value: '' width: 5 - FLOWCNTRL: access: rw description: Flow control and transfer type lsb: 11 reset_value: '' width: 3 - IE: access: rw description: Interrupt error mask lsb: 14 reset_value: '' width: 1 - ITC: access: rw description: Terminal count interrupt mask lsb: 15 reset_value: '' width: 1 - L: access: rw description: Lock lsb: 16 reset_value: '' width: 1 - A: access: r description: Active lsb: 17 reset_value: '' width: 1 - H: access: rw description: Halt lsb: 18 reset_value: '' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/gpio.csv000066400000000000000000001024011435536612600230470ustar00rootroot00000000000000GPIO_PIN_INTERRUPT_ISEL,0,8,PMODE,Selects the interrupt mode for each pin interrupt,0,rw GPIO_PIN_INTERRUPT_IENR,0,8,ENRL,Enables the rising edge or level interrupt for each pin interrupt,0,rw GPIO_PIN_INTERRUPT_SIENR,0,8,SETENRL,"Ones written to this address set bits in the IENR, thus enabling interrupts",,w GPIO_PIN_INTERRUPT_CIENR,0,8,CENRL,"Ones written to this address clear bits in the IENR, thus disabling the interrupts",,w GPIO_PIN_INTERRUPT_IENF,0,8,ENAF,Enables the falling edge or configures the active level interrupt for each pin interrupt,0,rw GPIO_PIN_INTERRUPT_SIENF,0,8,SETENAF,"Ones written to this address set bits in the IENF, thus enabling interrupts",,w GPIO_PIN_INTERRUPT_CIENF,0,8,CENAF,"Ones written to this address clears bits in the IENF, thus disabling interrupts",,w GPIO_PIN_INTERRUPT_RISE,0,8,RDET,Rising edge detect,0,rw GPIO_PIN_INTERRUPT_FALL,0,8,FDET,Falling edge detect,0,rw GPIO_PIN_INTERRUPT_IST,0,8,PSTAT,Pin interrupt status,0,rw GPIO_GROUP0_INTERRUPT_CTRL,0,1,INT,Group interrupt status,0,rw GPIO_GROUP0_INTERRUPT_CTRL,1,1,COMB,Combine enabled inputs for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_CTRL,2,1,TRIG,Group interrupt trigger,0,rw GPIO_GROUP0_INTERRUPT_PORT_POL0,0,32,POL,Configure pin polarity of port 0 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_POL1,0,32,POL,Configure pin polarity of port 1 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_POL2,0,32,POL,Configure pin polarity of port 2 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_POL3,0,32,POL,Configure pin polarity of port 3 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_POL4,0,32,POL,Configure pin polarity of port 4 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_POL5,0,32,POL,Configure pin polarity of port 5 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_POL6,0,32,POL,Configure pin polarity of port 6 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_POL7,0,32,POL,Configure pin polarity of port 7 pins for group interrupt,1,rw GPIO_GROUP0_INTERRUPT_PORT_ENA0,0,32,ENA,Enable port 0 pin for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_PORT_ENA1,0,32,ENA,Enable port 1 pin for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_PORT_ENA2,0,32,ENA,Enable port 2 pin for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_PORT_ENA3,0,32,ENA,Enable port 3 pin for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_PORT_ENA4,0,32,ENA,Enable port 4 pin for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_PORT_ENA5,0,32,ENA,Enable port 5 pin for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_PORT_ENA6,0,32,ENA,Enable port 6 pin for group interrupt,0,rw GPIO_GROUP0_INTERRUPT_PORT_ENA7,0,32,ENA,Enable port 7 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_CTRL,0,1,INT,Group interrupt status,0,rw GPIO_GROUP1_INTERRUPT_CTRL,1,1,COMB,Combine enabled inputs for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_CTRL,2,1,TRIG,Group interrupt trigger,0,rw GPIO_GROUP1_INTERRUPT_PORT_POL0,0,32,POL,Configure pin polarity of port 0 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_POL1,0,32,POL,Configure pin polarity of port 1 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_POL2,0,32,POL,Configure pin polarity of port 2 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_POL3,0,32,POL,Configure pin polarity of port 3 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_POL4,0,32,POL,Configure pin polarity of port 4 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_POL5,0,32,POL,Configure pin polarity of port 5 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_POL6,0,32,POL,Configure pin polarity of port 6 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_POL7,0,32,POL,Configure pin polarity of port 7 pins for group interrupt,1,rw GPIO_GROUP1_INTERRUPT_PORT_ENA0,0,32,ENA,Enable port 0 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_PORT_ENA1,0,32,ENA,Enable port 1 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_PORT_ENA2,0,32,ENA,Enable port 2 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_PORT_ENA3,0,32,ENA,Enable port 3 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_PORT_ENA4,0,32,ENA,Enable port 4 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_PORT_ENA5,0,32,ENA,Enable port 5 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_PORT_ENA6,0,32,ENA,Enable port 6 pin for group interrupt,0,rw GPIO_GROUP1_INTERRUPT_PORT_ENA7,0,32,ENA,Enable port 7 pin for group interrupt,0,rw GPIO_B0,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B1,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B2,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B3,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B4,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B5,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B6,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B7,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B8,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B9,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B10,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B11,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B12,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B13,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B14,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B15,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B16,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B17,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B18,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B19,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B20,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B21,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B22,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B23,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B24,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B25,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B26,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B27,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B28,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B29,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B30,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B31,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B32,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B33,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B34,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B35,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B36,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B37,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B38,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B39,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B40,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B41,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B42,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B43,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B44,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B45,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B46,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B47,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B48,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B49,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B50,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B51,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B52,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B53,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B54,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B55,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B56,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B57,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B58,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B59,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B60,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B61,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B62,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B63,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B64,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B65,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B66,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B67,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B68,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B69,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B70,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B71,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B72,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B73,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B74,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B75,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B76,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B77,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B78,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B79,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B80,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B81,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B82,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B83,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B84,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B85,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B86,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B87,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B88,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B89,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B90,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B91,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B92,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B93,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B94,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B95,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B96,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B97,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B98,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B99,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B100,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B101,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B102,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B103,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B104,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B105,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B106,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B107,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B108,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B109,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B110,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B111,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B112,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B113,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B114,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B115,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B116,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B117,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B118,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B119,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B120,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B121,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B122,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B123,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B124,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B125,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B126,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B127,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B128,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B129,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B130,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B131,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B132,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B133,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B134,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B135,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B136,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B137,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B138,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B139,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B140,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B141,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B142,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B143,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B144,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B145,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B146,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B147,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B148,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B149,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B150,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B151,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B152,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B153,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B154,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B155,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B156,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B157,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B158,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B159,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B160,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B161,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B162,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B163,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B164,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B165,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B166,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B167,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B168,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B169,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B170,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B171,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B172,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B173,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B174,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B175,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B176,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B177,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B178,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B179,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B180,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B181,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B182,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B183,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B184,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B185,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B186,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B187,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B188,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B189,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B190,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B191,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B192,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B193,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B194,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B195,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B196,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B197,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B198,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B199,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B200,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B201,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B202,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B203,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B204,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B205,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B206,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B207,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B208,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B209,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B210,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B211,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B212,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B213,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B214,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B215,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B216,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B217,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B218,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B219,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B220,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B221,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B222,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B223,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B224,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B225,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B226,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B227,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B228,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B229,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B230,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B231,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B232,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B233,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B234,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B235,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B236,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B237,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B238,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B239,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B240,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B241,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B242,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B243,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B244,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B245,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B246,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B247,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B248,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B249,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B250,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B251,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B252,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B253,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B254,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_B255,0,1,PBYTE,GPIO port byte pin register,,rw GPIO_W0,0,32,PWORD,GPIO port word pin register,,rw GPIO_W1,0,32,PWORD,GPIO port word pin register,,rw GPIO_W2,0,32,PWORD,GPIO port word pin register,,rw GPIO_W3,0,32,PWORD,GPIO port word pin register,,rw GPIO_W4,0,32,PWORD,GPIO port word pin register,,rw GPIO_W5,0,32,PWORD,GPIO port word pin register,,rw GPIO_W6,0,32,PWORD,GPIO port word pin register,,rw GPIO_W7,0,32,PWORD,GPIO port word pin register,,rw GPIO_W8,0,32,PWORD,GPIO port word pin register,,rw GPIO_W9,0,32,PWORD,GPIO port word pin register,,rw GPIO_W10,0,32,PWORD,GPIO port word pin register,,rw GPIO_W11,0,32,PWORD,GPIO port word pin register,,rw GPIO_W12,0,32,PWORD,GPIO port word pin register,,rw GPIO_W13,0,32,PWORD,GPIO port word pin register,,rw GPIO_W14,0,32,PWORD,GPIO port word pin register,,rw GPIO_W15,0,32,PWORD,GPIO port word pin register,,rw GPIO_W16,0,32,PWORD,GPIO port word pin register,,rw GPIO_W17,0,32,PWORD,GPIO port word pin register,,rw GPIO_W18,0,32,PWORD,GPIO port word pin register,,rw GPIO_W19,0,32,PWORD,GPIO port word pin register,,rw GPIO_W20,0,32,PWORD,GPIO port word pin register,,rw GPIO_W21,0,32,PWORD,GPIO port word pin register,,rw GPIO_W22,0,32,PWORD,GPIO port word pin register,,rw GPIO_W23,0,32,PWORD,GPIO port word pin register,,rw GPIO_W24,0,32,PWORD,GPIO port word pin register,,rw GPIO_W25,0,32,PWORD,GPIO port word pin register,,rw GPIO_W26,0,32,PWORD,GPIO port word pin register,,rw GPIO_W27,0,32,PWORD,GPIO port word pin register,,rw GPIO_W28,0,32,PWORD,GPIO port word pin register,,rw GPIO_W29,0,32,PWORD,GPIO port word pin register,,rw GPIO_W30,0,32,PWORD,GPIO port word pin register,,rw GPIO_W31,0,32,PWORD,GPIO port word pin register,,rw GPIO_W32,0,32,PWORD,GPIO port word pin register,,rw GPIO_W33,0,32,PWORD,GPIO port word pin register,,rw GPIO_W34,0,32,PWORD,GPIO port word pin register,,rw GPIO_W35,0,32,PWORD,GPIO port word pin register,,rw GPIO_W36,0,32,PWORD,GPIO port word pin register,,rw GPIO_W37,0,32,PWORD,GPIO port word pin register,,rw GPIO_W38,0,32,PWORD,GPIO port word pin register,,rw GPIO_W39,0,32,PWORD,GPIO port word pin register,,rw GPIO_W40,0,32,PWORD,GPIO port word pin register,,rw GPIO_W41,0,32,PWORD,GPIO port word pin register,,rw GPIO_W42,0,32,PWORD,GPIO port word pin register,,rw GPIO_W43,0,32,PWORD,GPIO port word pin register,,rw GPIO_W44,0,32,PWORD,GPIO port word pin register,,rw GPIO_W45,0,32,PWORD,GPIO port word pin register,,rw GPIO_W46,0,32,PWORD,GPIO port word pin register,,rw GPIO_W47,0,32,PWORD,GPIO port word pin register,,rw GPIO_W48,0,32,PWORD,GPIO port word pin register,,rw GPIO_W49,0,32,PWORD,GPIO port word pin register,,rw GPIO_W50,0,32,PWORD,GPIO port word pin register,,rw GPIO_W51,0,32,PWORD,GPIO port word pin register,,rw GPIO_W52,0,32,PWORD,GPIO port word pin register,,rw GPIO_W53,0,32,PWORD,GPIO port word pin register,,rw GPIO_W54,0,32,PWORD,GPIO port word pin register,,rw GPIO_W55,0,32,PWORD,GPIO port word pin register,,rw GPIO_W56,0,32,PWORD,GPIO port word pin register,,rw GPIO_W57,0,32,PWORD,GPIO port word pin register,,rw GPIO_W58,0,32,PWORD,GPIO port word pin register,,rw GPIO_W59,0,32,PWORD,GPIO port word pin register,,rw GPIO_W60,0,32,PWORD,GPIO port word pin register,,rw GPIO_W61,0,32,PWORD,GPIO port word pin register,,rw GPIO_W62,0,32,PWORD,GPIO port word pin register,,rw GPIO_W63,0,32,PWORD,GPIO port word pin register,,rw GPIO_W64,0,32,PWORD,GPIO port word pin register,,rw GPIO_W65,0,32,PWORD,GPIO port word pin register,,rw GPIO_W66,0,32,PWORD,GPIO port word pin register,,rw GPIO_W67,0,32,PWORD,GPIO port word pin register,,rw GPIO_W68,0,32,PWORD,GPIO port word pin register,,rw GPIO_W69,0,32,PWORD,GPIO port word pin register,,rw GPIO_W70,0,32,PWORD,GPIO port word pin register,,rw GPIO_W71,0,32,PWORD,GPIO port word pin register,,rw GPIO_W72,0,32,PWORD,GPIO port word pin register,,rw GPIO_W73,0,32,PWORD,GPIO port word pin register,,rw GPIO_W74,0,32,PWORD,GPIO port word pin register,,rw GPIO_W75,0,32,PWORD,GPIO port word pin register,,rw GPIO_W76,0,32,PWORD,GPIO port word pin register,,rw GPIO_W77,0,32,PWORD,GPIO port word pin register,,rw GPIO_W78,0,32,PWORD,GPIO port word pin register,,rw GPIO_W79,0,32,PWORD,GPIO port word pin register,,rw GPIO_W80,0,32,PWORD,GPIO port word pin register,,rw GPIO_W81,0,32,PWORD,GPIO port word pin register,,rw GPIO_W82,0,32,PWORD,GPIO port word pin register,,rw GPIO_W83,0,32,PWORD,GPIO port word pin register,,rw GPIO_W84,0,32,PWORD,GPIO port word pin register,,rw GPIO_W85,0,32,PWORD,GPIO port word pin register,,rw GPIO_W86,0,32,PWORD,GPIO port word pin register,,rw GPIO_W87,0,32,PWORD,GPIO port word pin register,,rw GPIO_W88,0,32,PWORD,GPIO port word pin register,,rw GPIO_W89,0,32,PWORD,GPIO port word pin register,,rw GPIO_W90,0,32,PWORD,GPIO port word pin register,,rw GPIO_W91,0,32,PWORD,GPIO port word pin register,,rw GPIO_W92,0,32,PWORD,GPIO port word pin register,,rw GPIO_W93,0,32,PWORD,GPIO port word pin register,,rw GPIO_W94,0,32,PWORD,GPIO port word pin register,,rw GPIO_W95,0,32,PWORD,GPIO port word pin register,,rw GPIO_W96,0,32,PWORD,GPIO port word pin register,,rw GPIO_W97,0,32,PWORD,GPIO port word pin register,,rw GPIO_W98,0,32,PWORD,GPIO port word pin register,,rw GPIO_W99,0,32,PWORD,GPIO port word pin register,,rw GPIO_W100,0,32,PWORD,GPIO port word pin register,,rw GPIO_W101,0,32,PWORD,GPIO port word pin register,,rw GPIO_W102,0,32,PWORD,GPIO port word pin register,,rw GPIO_W103,0,32,PWORD,GPIO port word pin register,,rw GPIO_W104,0,32,PWORD,GPIO port word pin register,,rw GPIO_W105,0,32,PWORD,GPIO port word pin register,,rw GPIO_W106,0,32,PWORD,GPIO port word pin register,,rw GPIO_W107,0,32,PWORD,GPIO port word pin register,,rw GPIO_W108,0,32,PWORD,GPIO port word pin register,,rw GPIO_W109,0,32,PWORD,GPIO port word pin register,,rw GPIO_W110,0,32,PWORD,GPIO port word pin register,,rw GPIO_W111,0,32,PWORD,GPIO port word pin register,,rw GPIO_W112,0,32,PWORD,GPIO port word pin register,,rw GPIO_W113,0,32,PWORD,GPIO port word pin register,,rw GPIO_W114,0,32,PWORD,GPIO port word pin register,,rw GPIO_W115,0,32,PWORD,GPIO port word pin register,,rw GPIO_W116,0,32,PWORD,GPIO port word pin register,,rw GPIO_W117,0,32,PWORD,GPIO port word pin register,,rw GPIO_W118,0,32,PWORD,GPIO port word pin register,,rw GPIO_W119,0,32,PWORD,GPIO port word pin register,,rw GPIO_W120,0,32,PWORD,GPIO port word pin register,,rw GPIO_W121,0,32,PWORD,GPIO port word pin register,,rw GPIO_W122,0,32,PWORD,GPIO port word pin register,,rw GPIO_W123,0,32,PWORD,GPIO port word pin register,,rw GPIO_W124,0,32,PWORD,GPIO port word pin register,,rw GPIO_W125,0,32,PWORD,GPIO port word pin register,,rw GPIO_W126,0,32,PWORD,GPIO port word pin register,,rw GPIO_W127,0,32,PWORD,GPIO port word pin register,,rw GPIO_W128,0,32,PWORD,GPIO port word pin register,,rw GPIO_W129,0,32,PWORD,GPIO port word pin register,,rw GPIO_W130,0,32,PWORD,GPIO port word pin register,,rw GPIO_W131,0,32,PWORD,GPIO port word pin register,,rw GPIO_W132,0,32,PWORD,GPIO port word pin register,,rw GPIO_W133,0,32,PWORD,GPIO port word pin register,,rw GPIO_W134,0,32,PWORD,GPIO port word pin register,,rw GPIO_W135,0,32,PWORD,GPIO port word pin register,,rw GPIO_W136,0,32,PWORD,GPIO port word pin register,,rw GPIO_W137,0,32,PWORD,GPIO port word pin register,,rw GPIO_W138,0,32,PWORD,GPIO port word pin register,,rw GPIO_W139,0,32,PWORD,GPIO port word pin register,,rw GPIO_W140,0,32,PWORD,GPIO port word pin register,,rw GPIO_W141,0,32,PWORD,GPIO port word pin register,,rw GPIO_W142,0,32,PWORD,GPIO port word pin register,,rw GPIO_W143,0,32,PWORD,GPIO port word pin register,,rw GPIO_W144,0,32,PWORD,GPIO port word pin register,,rw GPIO_W145,0,32,PWORD,GPIO port word pin register,,rw GPIO_W146,0,32,PWORD,GPIO port word pin register,,rw GPIO_W147,0,32,PWORD,GPIO port word pin register,,rw GPIO_W148,0,32,PWORD,GPIO port word pin register,,rw GPIO_W149,0,32,PWORD,GPIO port word pin register,,rw GPIO_W150,0,32,PWORD,GPIO port word pin register,,rw GPIO_W151,0,32,PWORD,GPIO port word pin register,,rw GPIO_W152,0,32,PWORD,GPIO port word pin register,,rw GPIO_W153,0,32,PWORD,GPIO port word pin register,,rw GPIO_W154,0,32,PWORD,GPIO port word pin register,,rw GPIO_W155,0,32,PWORD,GPIO port word pin register,,rw GPIO_W156,0,32,PWORD,GPIO port word pin register,,rw GPIO_W157,0,32,PWORD,GPIO port word pin register,,rw GPIO_W158,0,32,PWORD,GPIO port word pin register,,rw GPIO_W159,0,32,PWORD,GPIO port word pin register,,rw GPIO_W160,0,32,PWORD,GPIO port word pin register,,rw GPIO_W161,0,32,PWORD,GPIO port word pin register,,rw GPIO_W162,0,32,PWORD,GPIO port word pin register,,rw GPIO_W163,0,32,PWORD,GPIO port word pin register,,rw GPIO_W164,0,32,PWORD,GPIO port word pin register,,rw GPIO_W165,0,32,PWORD,GPIO port word pin register,,rw GPIO_W166,0,32,PWORD,GPIO port word pin register,,rw GPIO_W167,0,32,PWORD,GPIO port word pin register,,rw GPIO_W168,0,32,PWORD,GPIO port word pin register,,rw GPIO_W169,0,32,PWORD,GPIO port word pin register,,rw GPIO_W170,0,32,PWORD,GPIO port word pin register,,rw GPIO_W171,0,32,PWORD,GPIO port word pin register,,rw GPIO_W172,0,32,PWORD,GPIO port word pin register,,rw GPIO_W173,0,32,PWORD,GPIO port word pin register,,rw GPIO_W174,0,32,PWORD,GPIO port word pin register,,rw GPIO_W175,0,32,PWORD,GPIO port word pin register,,rw GPIO_W176,0,32,PWORD,GPIO port word pin register,,rw GPIO_W177,0,32,PWORD,GPIO port word pin register,,rw GPIO_W178,0,32,PWORD,GPIO port word pin register,,rw GPIO_W179,0,32,PWORD,GPIO port word pin register,,rw GPIO_W180,0,32,PWORD,GPIO port word pin register,,rw GPIO_W181,0,32,PWORD,GPIO port word pin register,,rw GPIO_W182,0,32,PWORD,GPIO port word pin register,,rw GPIO_W183,0,32,PWORD,GPIO port word pin register,,rw GPIO_W184,0,32,PWORD,GPIO port word pin register,,rw GPIO_W185,0,32,PWORD,GPIO port word pin register,,rw GPIO_W186,0,32,PWORD,GPIO port word pin register,,rw GPIO_W187,0,32,PWORD,GPIO port word pin register,,rw GPIO_W188,0,32,PWORD,GPIO port word pin register,,rw GPIO_W189,0,32,PWORD,GPIO port word pin register,,rw GPIO_W190,0,32,PWORD,GPIO port word pin register,,rw GPIO_W191,0,32,PWORD,GPIO port word pin register,,rw GPIO_W192,0,32,PWORD,GPIO port word pin register,,rw GPIO_W193,0,32,PWORD,GPIO port word pin register,,rw GPIO_W194,0,32,PWORD,GPIO port word pin register,,rw GPIO_W195,0,32,PWORD,GPIO port word pin register,,rw GPIO_W196,0,32,PWORD,GPIO port word pin register,,rw GPIO_W197,0,32,PWORD,GPIO port word pin register,,rw GPIO_W198,0,32,PWORD,GPIO port word pin register,,rw GPIO_W199,0,32,PWORD,GPIO port word pin register,,rw GPIO_W200,0,32,PWORD,GPIO port word pin register,,rw GPIO_W201,0,32,PWORD,GPIO port word pin register,,rw GPIO_W202,0,32,PWORD,GPIO port word pin register,,rw GPIO_W203,0,32,PWORD,GPIO port word pin register,,rw GPIO_W204,0,32,PWORD,GPIO port word pin register,,rw GPIO_W205,0,32,PWORD,GPIO port word pin register,,rw GPIO_W206,0,32,PWORD,GPIO port word pin register,,rw GPIO_W207,0,32,PWORD,GPIO port word pin register,,rw GPIO_W208,0,32,PWORD,GPIO port word pin register,,rw GPIO_W209,0,32,PWORD,GPIO port word pin register,,rw GPIO_W210,0,32,PWORD,GPIO port word pin register,,rw GPIO_W211,0,32,PWORD,GPIO port word pin register,,rw GPIO_W212,0,32,PWORD,GPIO port word pin register,,rw GPIO_W213,0,32,PWORD,GPIO port word pin register,,rw GPIO_W214,0,32,PWORD,GPIO port word pin register,,rw GPIO_W215,0,32,PWORD,GPIO port word pin register,,rw GPIO_W216,0,32,PWORD,GPIO port word pin register,,rw GPIO_W217,0,32,PWORD,GPIO port word pin register,,rw GPIO_W218,0,32,PWORD,GPIO port word pin register,,rw GPIO_W219,0,32,PWORD,GPIO port word pin register,,rw GPIO_W220,0,32,PWORD,GPIO port word pin register,,rw GPIO_W221,0,32,PWORD,GPIO port word pin register,,rw GPIO_W222,0,32,PWORD,GPIO port word pin register,,rw GPIO_W223,0,32,PWORD,GPIO port word pin register,,rw GPIO_W224,0,32,PWORD,GPIO port word pin register,,rw GPIO_W225,0,32,PWORD,GPIO port word pin register,,rw GPIO_W226,0,32,PWORD,GPIO port word pin register,,rw GPIO_W227,0,32,PWORD,GPIO port word pin register,,rw GPIO_W228,0,32,PWORD,GPIO port word pin register,,rw GPIO_W229,0,32,PWORD,GPIO port word pin register,,rw GPIO_W230,0,32,PWORD,GPIO port word pin register,,rw GPIO_W231,0,32,PWORD,GPIO port word pin register,,rw GPIO_W232,0,32,PWORD,GPIO port word pin register,,rw GPIO_W233,0,32,PWORD,GPIO port word pin register,,rw GPIO_W234,0,32,PWORD,GPIO port word pin register,,rw GPIO_W235,0,32,PWORD,GPIO port word pin register,,rw GPIO_W236,0,32,PWORD,GPIO port word pin register,,rw GPIO_W237,0,32,PWORD,GPIO port word pin register,,rw GPIO_W238,0,32,PWORD,GPIO port word pin register,,rw GPIO_W239,0,32,PWORD,GPIO port word pin register,,rw GPIO_W240,0,32,PWORD,GPIO port word pin register,,rw GPIO_W241,0,32,PWORD,GPIO port word pin register,,rw GPIO_W242,0,32,PWORD,GPIO port word pin register,,rw GPIO_W243,0,32,PWORD,GPIO port word pin register,,rw GPIO_W244,0,32,PWORD,GPIO port word pin register,,rw GPIO_W245,0,32,PWORD,GPIO port word pin register,,rw GPIO_W246,0,32,PWORD,GPIO port word pin register,,rw GPIO_W247,0,32,PWORD,GPIO port word pin register,,rw GPIO_W248,0,32,PWORD,GPIO port word pin register,,rw GPIO_W249,0,32,PWORD,GPIO port word pin register,,rw GPIO_W250,0,32,PWORD,GPIO port word pin register,,rw GPIO_W251,0,32,PWORD,GPIO port word pin register,,rw GPIO_W252,0,32,PWORD,GPIO port word pin register,,rw GPIO_W253,0,32,PWORD,GPIO port word pin register,,rw GPIO_W254,0,32,PWORD,GPIO port word pin register,,rw GPIO_W255,0,32,PWORD,GPIO port word pin register,,rw GPIO0_DIR,0,32,DIR,Selects pin direction for GPIO0,0,rw GPIO1_DIR,0,32,DIR,Selects pin direction for GPIO1,0,rw GPIO2_DIR,0,32,DIR,Selects pin direction for GPIO2,0,rw GPIO3_DIR,0,32,DIR,Selects pin direction for GPIO3,0,rw GPIO4_DIR,0,32,DIR,Selects pin direction for GPIO4,0,rw GPIO5_DIR,0,32,DIR,Selects pin direction for GPIO5,0,rw GPIO6_DIR,0,32,DIR,Selects pin direction for GPIO6,0,rw GPIO7_DIR,0,32,DIR,Selects pin direction for GPIO7,0,rw GPIO0_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO1_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO2_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO3_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO4_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO5_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO6_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO7_MASK,0,32,MASK,Controls which pins are active in the MPORT register,0,rw GPIO0_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO1_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO2_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO3_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO4_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO5_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO6_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO7_PIN,0,32,PORT,Reads pin states or loads output bits,,rw GPIO0_MPIN,0,32,MPORT,Masked port register,,rw GPIO1_MPIN,0,32,MPORT,Masked port register,,rw GPIO2_MPIN,0,32,MPORT,Masked port register,,rw GPIO3_MPIN,0,32,MPORT,Masked port register,,rw GPIO4_MPIN,0,32,MPORT,Masked port register,,rw GPIO5_MPIN,0,32,MPORT,Masked port register,,rw GPIO6_MPIN,0,32,MPORT,Masked port register,,rw GPIO7_MPIN,0,32,MPORT,Masked port register,,rw GPIO0_SET,0,32,SET,Read or set output bits,0,rw GPIO1_SET,0,32,SET,Read or set output bits,0,rw GPIO2_SET,0,32,SET,Read or set output bits,0,rw GPIO3_SET,0,32,SET,Read or set output bits,0,rw GPIO4_SET,0,32,SET,Read or set output bits,0,rw GPIO5_SET,0,32,SET,Read or set output bits,0,rw GPIO6_SET,0,32,SET,Read or set output bits,0,rw GPIO7_SET,0,32,SET,Read or set output bits,0,rw GPIO0_CLR,0,32,CLR,Clear output bits,,w GPIO1_CLR,0,32,CLR,Clear output bits,,w GPIO2_CLR,0,32,CLR,Clear output bits,,w GPIO3_CLR,0,32,CLR,Clear output bits,,w GPIO4_CLR,0,32,CLR,Clear output bits,,w GPIO5_CLR,0,32,CLR,Clear output bits,,w GPIO6_CLR,0,32,CLR,Clear output bits,,w GPIO7_CLR,0,32,CLR,Clear output bits,,w GPIO0_NOT,0,32,NOT,Toggle output bits,,w GPIO1_NOT,0,32,NOT,Toggle output bits,,w GPIO2_NOT,0,32,NOT,Toggle output bits,,w GPIO3_NOT,0,32,NOT,Toggle output bits,,w GPIO4_NOT,0,32,NOT,Toggle output bits,,w GPIO5_NOT,0,32,NOT,Toggle output bits,,w GPIO6_NOT,0,32,NOT,Toggle output bits,,w GPIO7_NOT,0,32,NOT,Toggle output bits,,w hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/gpio.yaml000066400000000000000000003167661435536612600232430ustar00rootroot00000000000000!!omap - GPIO_PIN_INTERRUPT_ISEL: fields: !!omap - PMODE: access: rw description: Selects the interrupt mode for each pin interrupt lsb: 0 reset_value: '0' width: 8 - GPIO_PIN_INTERRUPT_IENR: fields: !!omap - ENRL: access: rw description: Enables the rising edge or level interrupt for each pin interrupt lsb: 0 reset_value: '0' width: 8 - GPIO_PIN_INTERRUPT_SIENR: fields: !!omap - SETENRL: access: w description: Ones written to this address set bits in the IENR, thus enabling interrupts lsb: 0 reset_value: '' width: 8 - GPIO_PIN_INTERRUPT_CIENR: fields: !!omap - CENRL: access: w description: Ones written to this address clear bits in the IENR, thus disabling the interrupts lsb: 0 reset_value: '' width: 8 - GPIO_PIN_INTERRUPT_IENF: fields: !!omap - ENAF: access: rw description: Enables the falling edge or configures the active level interrupt for each pin interrupt lsb: 0 reset_value: '0' width: 8 - GPIO_PIN_INTERRUPT_SIENF: fields: !!omap - SETENAF: access: w description: Ones written to this address set bits in the IENF, thus enabling interrupts lsb: 0 reset_value: '' width: 8 - GPIO_PIN_INTERRUPT_CIENF: fields: !!omap - CENAF: access: w description: Ones written to this address clears bits in the IENF, thus disabling interrupts lsb: 0 reset_value: '' width: 8 - GPIO_PIN_INTERRUPT_RISE: fields: !!omap - RDET: access: rw description: Rising edge detect lsb: 0 reset_value: '0' width: 8 - GPIO_PIN_INTERRUPT_FALL: fields: !!omap - FDET: access: rw description: Falling edge detect lsb: 0 reset_value: '0' width: 8 - GPIO_PIN_INTERRUPT_IST: fields: !!omap - PSTAT: access: rw description: Pin interrupt status lsb: 0 reset_value: '0' width: 8 - GPIO_GROUP0_INTERRUPT_CTRL: fields: !!omap - INT: access: rw description: Group interrupt status lsb: 0 reset_value: '0' width: 1 - COMB: access: rw description: Combine enabled inputs for group interrupt lsb: 1 reset_value: '0' width: 1 - TRIG: access: rw description: Group interrupt trigger lsb: 2 reset_value: '0' width: 1 - GPIO_GROUP0_INTERRUPT_PORT_POL0: fields: !!omap - POL: access: rw description: Configure pin polarity of port 0 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_POL1: fields: !!omap - POL: access: rw description: Configure pin polarity of port 1 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_POL2: fields: !!omap - POL: access: rw description: Configure pin polarity of port 2 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_POL3: fields: !!omap - POL: access: rw description: Configure pin polarity of port 3 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_POL4: fields: !!omap - POL: access: rw description: Configure pin polarity of port 4 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_POL5: fields: !!omap - POL: access: rw description: Configure pin polarity of port 5 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_POL6: fields: !!omap - POL: access: rw description: Configure pin polarity of port 6 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_POL7: fields: !!omap - POL: access: rw description: Configure pin polarity of port 7 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA0: fields: !!omap - ENA: access: rw description: Enable port 0 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA1: fields: !!omap - ENA: access: rw description: Enable port 1 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA2: fields: !!omap - ENA: access: rw description: Enable port 2 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA3: fields: !!omap - ENA: access: rw description: Enable port 3 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA4: fields: !!omap - ENA: access: rw description: Enable port 4 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA5: fields: !!omap - ENA: access: rw description: Enable port 5 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA6: fields: !!omap - ENA: access: rw description: Enable port 6 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP0_INTERRUPT_PORT_ENA7: fields: !!omap - ENA: access: rw description: Enable port 7 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_CTRL: fields: !!omap - INT: access: rw description: Group interrupt status lsb: 0 reset_value: '0' width: 1 - COMB: access: rw description: Combine enabled inputs for group interrupt lsb: 1 reset_value: '0' width: 1 - TRIG: access: rw description: Group interrupt trigger lsb: 2 reset_value: '0' width: 1 - GPIO_GROUP1_INTERRUPT_PORT_POL0: fields: !!omap - POL: access: rw description: Configure pin polarity of port 0 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_POL1: fields: !!omap - POL: access: rw description: Configure pin polarity of port 1 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_POL2: fields: !!omap - POL: access: rw description: Configure pin polarity of port 2 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_POL3: fields: !!omap - POL: access: rw description: Configure pin polarity of port 3 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_POL4: fields: !!omap - POL: access: rw description: Configure pin polarity of port 4 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_POL5: fields: !!omap - POL: access: rw description: Configure pin polarity of port 5 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_POL6: fields: !!omap - POL: access: rw description: Configure pin polarity of port 6 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_POL7: fields: !!omap - POL: access: rw description: Configure pin polarity of port 7 pins for group interrupt lsb: 0 reset_value: '1' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA0: fields: !!omap - ENA: access: rw description: Enable port 0 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA1: fields: !!omap - ENA: access: rw description: Enable port 1 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA2: fields: !!omap - ENA: access: rw description: Enable port 2 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA3: fields: !!omap - ENA: access: rw description: Enable port 3 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA4: fields: !!omap - ENA: access: rw description: Enable port 4 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA5: fields: !!omap - ENA: access: rw description: Enable port 5 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA6: fields: !!omap - ENA: access: rw description: Enable port 6 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_GROUP1_INTERRUPT_PORT_ENA7: fields: !!omap - ENA: access: rw description: Enable port 7 pin for group interrupt lsb: 0 reset_value: '0' width: 32 - GPIO_B0: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B1: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B2: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B3: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B4: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B5: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B6: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B7: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B8: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B9: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B10: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B11: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B12: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B13: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B14: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B15: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B16: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B17: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B18: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B19: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B20: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B21: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B22: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B23: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B24: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B25: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B26: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B27: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B28: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B29: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B30: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B31: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B32: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B33: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B34: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B35: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B36: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B37: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B38: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B39: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B40: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B41: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B42: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B43: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B44: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B45: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B46: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B47: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B48: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B49: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B50: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B51: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B52: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B53: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B54: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B55: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B56: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B57: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B58: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B59: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B60: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B61: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B62: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B63: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B64: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B65: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B66: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B67: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B68: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B69: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B70: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B71: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B72: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B73: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B74: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B75: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B76: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B77: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B78: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B79: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B80: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B81: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B82: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B83: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B84: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B85: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B86: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B87: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B88: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B89: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B90: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B91: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B92: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B93: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B94: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B95: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B96: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B97: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B98: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B99: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B100: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B101: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B102: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B103: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B104: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B105: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B106: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B107: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B108: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B109: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B110: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B111: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B112: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B113: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B114: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B115: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B116: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B117: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B118: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B119: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B120: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B121: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B122: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B123: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B124: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B125: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B126: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B127: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B128: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B129: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B130: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B131: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B132: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B133: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B134: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B135: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B136: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B137: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B138: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B139: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B140: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B141: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B142: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B143: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B144: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B145: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B146: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B147: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B148: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B149: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B150: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B151: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B152: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B153: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B154: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B155: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B156: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B157: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B158: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B159: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B160: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B161: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B162: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B163: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B164: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B165: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B166: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B167: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B168: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B169: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B170: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B171: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B172: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B173: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B174: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B175: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B176: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B177: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B178: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B179: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B180: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B181: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B182: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B183: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B184: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B185: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B186: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B187: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B188: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B189: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B190: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B191: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B192: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B193: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B194: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B195: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B196: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B197: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B198: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B199: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B200: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B201: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B202: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B203: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B204: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B205: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B206: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B207: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B208: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B209: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B210: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B211: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B212: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B213: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B214: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B215: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B216: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B217: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B218: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B219: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B220: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B221: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B222: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B223: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B224: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B225: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B226: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B227: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B228: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B229: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B230: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B231: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B232: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B233: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B234: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B235: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B236: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B237: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B238: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B239: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B240: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B241: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B242: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B243: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B244: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B245: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B246: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B247: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B248: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B249: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B250: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B251: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B252: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B253: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B254: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_B255: fields: !!omap - PBYTE: access: rw description: GPIO port byte pin register lsb: 0 reset_value: '' width: 1 - GPIO_W0: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W1: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W2: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W3: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W4: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W5: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W6: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W7: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W8: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W9: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W10: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W11: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W12: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W13: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W14: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W15: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W16: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W17: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W18: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W19: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W20: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W21: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W22: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W23: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W24: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W25: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W26: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W27: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W28: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W29: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W30: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W31: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W32: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W33: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W34: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W35: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W36: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W37: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W38: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W39: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W40: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W41: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W42: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W43: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W44: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W45: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W46: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W47: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W48: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W49: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W50: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W51: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W52: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W53: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W54: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W55: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W56: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W57: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W58: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W59: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W60: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W61: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W62: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W63: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W64: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W65: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W66: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W67: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W68: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W69: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W70: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W71: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W72: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W73: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W74: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W75: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W76: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W77: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W78: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W79: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W80: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W81: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W82: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W83: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W84: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W85: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W86: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W87: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W88: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W89: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W90: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W91: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W92: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W93: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W94: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W95: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W96: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W97: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W98: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W99: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W100: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W101: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W102: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W103: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W104: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W105: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W106: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W107: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W108: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W109: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W110: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W111: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W112: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W113: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W114: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W115: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W116: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W117: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W118: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W119: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W120: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W121: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W122: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W123: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W124: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W125: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W126: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W127: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W128: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W129: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W130: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W131: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W132: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W133: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W134: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W135: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W136: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W137: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W138: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W139: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W140: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W141: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W142: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W143: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W144: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W145: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W146: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W147: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W148: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W149: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W150: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W151: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W152: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W153: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W154: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W155: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W156: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W157: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W158: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W159: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W160: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W161: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W162: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W163: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W164: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W165: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W166: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W167: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W168: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W169: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W170: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W171: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W172: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W173: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W174: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W175: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W176: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W177: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W178: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W179: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W180: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W181: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W182: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W183: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W184: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W185: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W186: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W187: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W188: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W189: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W190: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W191: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W192: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W193: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W194: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W195: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W196: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W197: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W198: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W199: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W200: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W201: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W202: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W203: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W204: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W205: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W206: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W207: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W208: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W209: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W210: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W211: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W212: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W213: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W214: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W215: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W216: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W217: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W218: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W219: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W220: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W221: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W222: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W223: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W224: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W225: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W226: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W227: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W228: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W229: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W230: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W231: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W232: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W233: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W234: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W235: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W236: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W237: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W238: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W239: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W240: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W241: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W242: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W243: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W244: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W245: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W246: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W247: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W248: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W249: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W250: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W251: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W252: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W253: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W254: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO_W255: fields: !!omap - PWORD: access: rw description: GPIO port word pin register lsb: 0 reset_value: '' width: 32 - GPIO0_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO0 lsb: 0 reset_value: '0' width: 32 - GPIO1_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO1 lsb: 0 reset_value: '0' width: 32 - GPIO2_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO2 lsb: 0 reset_value: '0' width: 32 - GPIO3_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO3 lsb: 0 reset_value: '0' width: 32 - GPIO4_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO4 lsb: 0 reset_value: '0' width: 32 - GPIO5_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO5 lsb: 0 reset_value: '0' width: 32 - GPIO6_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO6 lsb: 0 reset_value: '0' width: 32 - GPIO7_DIR: fields: !!omap - DIR: access: rw description: Selects pin direction for GPIO7 lsb: 0 reset_value: '0' width: 32 - GPIO0_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO1_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO2_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO3_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO4_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO5_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO6_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO7_MASK: fields: !!omap - MASK: access: rw description: Controls which pins are active in the MPORT register lsb: 0 reset_value: '0' width: 32 - GPIO0_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO1_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO2_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO3_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO4_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO5_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO6_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO7_PIN: fields: !!omap - PORT: access: rw description: Reads pin states or loads output bits lsb: 0 reset_value: '' width: 32 - GPIO0_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO1_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO2_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO3_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO4_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO5_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO6_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO7_MPIN: fields: !!omap - MPORT: access: rw description: Masked port register lsb: 0 reset_value: '' width: 32 - GPIO0_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO1_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO2_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO3_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO4_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO5_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO6_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO7_SET: fields: !!omap - SET: access: rw description: Read or set output bits lsb: 0 reset_value: '0' width: 32 - GPIO0_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO1_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO2_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO3_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO4_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO5_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO6_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO7_CLR: fields: !!omap - CLR: access: w description: Clear output bits lsb: 0 reset_value: '' width: 32 - GPIO0_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 - GPIO1_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 - GPIO2_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 - GPIO3_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 - GPIO4_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 - GPIO5_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 - GPIO6_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 - GPIO7_NOT: fields: !!omap - NOT: access: w description: Toggle output bits lsb: 0 reset_value: '' width: 32 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/i2c.csv000066400000000000000000000062521435536612600225750ustar00rootroot00000000000000I2C0_CONSET,2,1,AA,Assert acknowledge flag,0,rw I2C0_CONSET,3,1,SI,I2C interrupt flag,0,rw I2C0_CONSET,4,1,STO,STOP flag,0,rw I2C0_CONSET,5,1,STA,START flag,0,rw I2C0_CONSET,6,1,I2EN,I2C interface enable,0,rw I2C1_CONSET,2,1,AA,Assert acknowledge flag,0,rw I2C1_CONSET,3,1,SI,I2C interrupt flag,0,rw I2C1_CONSET,4,1,STO,STOP flag,0,rw I2C1_CONSET,5,1,STA,START flag,0,rw I2C1_CONSET,6,1,I2EN,I2C interface enable,0,rw I2C0_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r I2C1_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r I2C0_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw I2C1_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw I2C0_ADR0,0,1,GC,General Call enable bit,0,rw I2C0_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C1_ADR0,0,1,GC,General Call enable bit,0,rw I2C1_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C0_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw I2C1_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw I2C0_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw I2C1_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw I2C0_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w I2C0_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w I2C0_CONCLR,5,1,STAC,START flag Clear bit,0,w I2C0_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w I2C1_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w I2C1_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w I2C1_CONCLR,5,1,STAC,START flag Clear bit,0,w I2C1_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w I2C0_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw I2C0_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw I2C0_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw I2C1_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw I2C1_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw I2C1_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw I2C0_ADR1,0,1,GC,General Call enable bit,0,rw I2C0_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C1_ADR1,0,1,GC,General Call enable bit,0,rw I2C1_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C0_ADR2,0,1,GC,General Call enable bit,0,rw I2C0_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C1_ADR2,0,1,GC,General Call enable bit,0,rw I2C1_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C0_ADR3,0,1,GC,General Call enable bit,0,rw I2C0_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C1_ADR3,0,1,GC,General Call enable bit,0,rw I2C1_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw I2C0_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r I2C1_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r I2C0_MASK0,1,7,MASK,Mask bits,0,rw I2C1_MASK0,1,7,MASK,Mask bits,0,rw I2C0_MASK1,1,7,MASK,Mask bits,0,rw I2C1_MASK1,1,7,MASK,Mask bits,0,rw I2C0_MASK2,1,7,MASK,Mask bits,0,rw I2C1_MASK2,1,7,MASK,Mask bits,0,rw I2C0_MASK3,1,7,MASK,Mask bits,0,rw I2C1_MASK3,1,7,MASK,Mask bits,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/i2c.yaml000066400000000000000000000216511435536612600227440ustar00rootroot00000000000000!!omap - I2C0_CONSET: fields: !!omap - AA: access: rw description: Assert acknowledge flag lsb: 2 reset_value: '0' width: 1 - SI: access: rw description: I2C interrupt flag lsb: 3 reset_value: '0' width: 1 - STO: access: rw description: STOP flag lsb: 4 reset_value: '0' width: 1 - STA: access: rw description: START flag lsb: 5 reset_value: '0' width: 1 - I2EN: access: rw description: I2C interface enable lsb: 6 reset_value: '0' width: 1 - I2C1_CONSET: fields: !!omap - AA: access: rw description: Assert acknowledge flag lsb: 2 reset_value: '0' width: 1 - SI: access: rw description: I2C interrupt flag lsb: 3 reset_value: '0' width: 1 - STO: access: rw description: STOP flag lsb: 4 reset_value: '0' width: 1 - STA: access: rw description: START flag lsb: 5 reset_value: '0' width: 1 - I2EN: access: rw description: I2C interface enable lsb: 6 reset_value: '0' width: 1 - I2C0_STAT: fields: !!omap - STATUS: access: r description: These bits give the actual status information about the I2C interface lsb: 3 reset_value: '0x1f' width: 5 - I2C1_STAT: fields: !!omap - STATUS: access: r description: These bits give the actual status information about the I2C interface lsb: 3 reset_value: '0x1f' width: 5 - I2C0_DAT: fields: !!omap - DATA: access: rw description: This register holds data values that have been received or are to be transmitted lsb: 0 reset_value: '0' width: 8 - I2C1_DAT: fields: !!omap - DATA: access: rw description: This register holds data values that have been received or are to be transmitted lsb: 0 reset_value: '0' width: 8 - I2C0_ADR0: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C1_ADR0: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C0_SCLH: fields: !!omap - SCLH: access: rw description: Count for SCL HIGH time period selection lsb: 0 reset_value: '0x0004' width: 16 - I2C1_SCLH: fields: !!omap - SCLH: access: rw description: Count for SCL HIGH time period selection lsb: 0 reset_value: '0x0004' width: 16 - I2C0_SCLL: fields: !!omap - SCLL: access: rw description: Count for SCL LOW time period selection lsb: 0 reset_value: '0x0004' width: 16 - I2C1_SCLL: fields: !!omap - SCLL: access: rw description: Count for SCL LOW time period selection lsb: 0 reset_value: '0x0004' width: 16 - I2C0_CONCLR: fields: !!omap - AAC: access: w description: Assert acknowledge Clear bit lsb: 2 reset_value: '0' width: 1 - SIC: access: w description: I2C interrupt Clear bit lsb: 3 reset_value: '0' width: 1 - STAC: access: w description: START flag Clear bit lsb: 5 reset_value: '0' width: 1 - I2ENC: access: w description: I2C interface Disable bit lsb: 6 reset_value: '0' width: 1 - I2C1_CONCLR: fields: !!omap - AAC: access: w description: Assert acknowledge Clear bit lsb: 2 reset_value: '0' width: 1 - SIC: access: w description: I2C interrupt Clear bit lsb: 3 reset_value: '0' width: 1 - STAC: access: w description: START flag Clear bit lsb: 5 reset_value: '0' width: 1 - I2ENC: access: w description: I2C interface Disable bit lsb: 6 reset_value: '0' width: 1 - I2C0_MMCTRL: fields: !!omap - MM_ENA: access: rw description: Monitor mode enable lsb: 0 reset_value: '0' width: 1 - ENA_SCL: access: rw description: SCL output enable lsb: 1 reset_value: '0' width: 1 - MATCH_ALL: access: rw description: Select interrupt register match lsb: 2 reset_value: '0' width: 1 - I2C1_MMCTRL: fields: !!omap - MM_ENA: access: rw description: Monitor mode enable lsb: 0 reset_value: '0' width: 1 - ENA_SCL: access: rw description: SCL output enable lsb: 1 reset_value: '0' width: 1 - MATCH_ALL: access: rw description: Select interrupt register match lsb: 2 reset_value: '0' width: 1 - I2C0_ADR1: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C1_ADR1: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C0_ADR2: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C1_ADR2: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C0_ADR3: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C1_ADR3: fields: !!omap - GC: access: rw description: General Call enable bit lsb: 0 reset_value: '0' width: 1 - ADDRESS: access: rw description: The I2C device address for slave mode lsb: 1 reset_value: '0' width: 7 - I2C0_DATA_BUFFER: fields: !!omap - DATA: access: r description: This register holds contents of the 8 MSBs of the DAT shift register lsb: 0 reset_value: '0' width: 8 - I2C1_DATA_BUFFER: fields: !!omap - DATA: access: r description: This register holds contents of the 8 MSBs of the DAT shift register lsb: 0 reset_value: '0' width: 8 - I2C0_MASK0: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 - I2C1_MASK0: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 - I2C0_MASK1: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 - I2C1_MASK1: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 - I2C0_MASK2: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 - I2C1_MASK2: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 - I2C0_MASK3: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 - I2C1_MASK3: fields: !!omap - MASK: access: rw description: Mask bits lsb: 1 reset_value: '0' width: 7 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/i2s.csv000066400000000000000000000160041435536612600226110ustar00rootroot00000000000000I2S0_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw I2S0_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw I2S0_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw I2S0_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw I2S0_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw I2S0_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw I2S0_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw I2S1_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw I2S1_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw I2S1_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw I2S1_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw I2S1_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw I2S1_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw I2S1_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw I2S0_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw I2S0_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw I2S0_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw I2S0_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw I2S0_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw I2S0_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw I2S1_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw I2S1_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw I2S1_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw I2S1_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw I2S1_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw I2S1_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw I2S0_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w I2S1_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w I2S0_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r I2S1_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r I2S0_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r I2S0_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r I2S0_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r I2S0_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r I2S0_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r I2S1_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r I2S1_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r I2S1_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r I2S1_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r I2S1_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r I2S0_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw I2S0_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw I2S0_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw I2S0_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw I2S1_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw I2S1_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw I2S1_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw I2S1_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw I2S0_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw I2S0_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw I2S0_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw I2S0_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw I2S1_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw I2S1_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw I2S1_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw I2S1_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw I2S0_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw I2S0_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw I2S0_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw I2S0_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw I2S1_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw I2S1_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw I2S1_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw I2S1_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw I2S0_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw I2S0_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw I2S1_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw I2S1_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw I2S0_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw I2S0_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw I2S1_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw I2S1_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw I2S0_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw I2S1_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw I2S0_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw I2S1_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw I2S0_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw I2S0_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw I2S0_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw I2S1_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw I2S1_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw I2S1_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw I2S0_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw I2S0_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw I2S0_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw I2S1_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw I2S1_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw I2S1_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/i2s.yaml000066400000000000000000000363771435536612600227770ustar00rootroot00000000000000!!omap - I2S0_DAO: fields: !!omap - WORDWIDTH: access: rw description: Selects the number of bytes in data lsb: 0 reset_value: '1' width: 2 - MONO: access: rw description: When 1, data is of monaural format. When 0, the data is in stereo format lsb: 2 reset_value: '0' width: 1 - STOP: access: rw description: When 1, disables accesses on FIFOs, places the transmit channel in mute mode lsb: 3 reset_value: '0' width: 1 - RESET: access: rw description: When 1, asynchronously resets the transmit channel and FIFO lsb: 4 reset_value: '0' width: 1 - WS_SEL: access: rw description: When 0, the interface is in master mode. When 1, the interface is in slave mode lsb: 5 reset_value: '1' width: 1 - WS_HALFPERIOD: access: rw description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. lsb: 6 reset_value: '0x1f' width: 9 - MUTE: access: rw description: When 1, the transmit channel sends only zeroes lsb: 15 reset_value: '1' width: 1 - I2S1_DAO: fields: !!omap - WORDWIDTH: access: rw description: Selects the number of bytes in data lsb: 0 reset_value: '1' width: 2 - MONO: access: rw description: When 1, data is of monaural format. When 0, the data is in stereo format lsb: 2 reset_value: '0' width: 1 - STOP: access: rw description: When 1, disables accesses on FIFOs, places the transmit channel in mute mode lsb: 3 reset_value: '0' width: 1 - RESET: access: rw description: When 1, asynchronously resets the transmit channel and FIFO lsb: 4 reset_value: '0' width: 1 - WS_SEL: access: rw description: When 0, the interface is in master mode. When 1, the interface is in slave mode lsb: 5 reset_value: '1' width: 1 - WS_HALFPERIOD: access: rw description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. lsb: 6 reset_value: '0x1f' width: 9 - MUTE: access: rw description: When 1, the transmit channel sends only zeroes lsb: 15 reset_value: '1' width: 1 - I2S0_DAI: fields: !!omap - WORDWIDTH: access: rw description: Selects the number of bytes in data lsb: 0 reset_value: '1' width: 2 - MONO: access: rw description: When 1, data is of monaural format. When 0, the data is in stereo format lsb: 2 reset_value: '0' width: 1 - STOP: access: rw description: When 1, disables accesses on FIFOs, places the transmit channel in mute mode lsb: 3 reset_value: '0' width: 1 - RESET: access: rw description: When 1, asynchronously resets the transmit channel and FIFO lsb: 4 reset_value: '0' width: 1 - WS_SEL: access: rw description: When 0, the interface is in master mode. When 1, the interface is in slave mode lsb: 5 reset_value: '1' width: 1 - WS_HALFPERIOD: access: rw description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. lsb: 6 reset_value: '0x1f' width: 9 - I2S1_DAI: fields: !!omap - WORDWIDTH: access: rw description: Selects the number of bytes in data lsb: 0 reset_value: '1' width: 2 - MONO: access: rw description: When 1, data is of monaural format. When 0, the data is in stereo format lsb: 2 reset_value: '0' width: 1 - STOP: access: rw description: When 1, disables accesses on FIFOs, places the transmit channel in mute mode lsb: 3 reset_value: '0' width: 1 - RESET: access: rw description: When 1, asynchronously resets the transmit channel and FIFO lsb: 4 reset_value: '0' width: 1 - WS_SEL: access: rw description: When 0, the interface is in master mode. When 1, the interface is in slave mode lsb: 5 reset_value: '1' width: 1 - WS_HALFPERIOD: access: rw description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. lsb: 6 reset_value: '0x1f' width: 9 - I2S0_TXFIFO: fields: !!omap - I2STXFIFO: access: w description: 8 x 32-bit transmit FIFO lsb: 0 reset_value: '0' width: 32 - I2S1_TXFIFO: fields: !!omap - I2STXFIFO: access: w description: 8 x 32-bit transmit FIFO lsb: 0 reset_value: '0' width: 32 - I2S0_RXFIFO: fields: !!omap - I2SRXFIFO: access: r description: 8 x 32-bit receive FIFO lsb: 0 reset_value: '0' width: 32 - I2S1_RXFIFO: fields: !!omap - I2SRXFIFO: access: r description: 8 x 32-bit receive FIFO lsb: 0 reset_value: '0' width: 32 - I2S0_STATE: fields: !!omap - IRQ: access: r description: This bit reflects the presence of Receive Interrupt or Transmit Interrupt lsb: 0 reset_value: '1' width: 1 - DMAREQ1: access: r description: This bit reflects the presence of Receive or Transmit DMA Request 1 lsb: 1 reset_value: '1' width: 1 - DMAREQ2: access: r description: This bit reflects the presence of Receive or Transmit DMA Request 2 lsb: 2 reset_value: '1' width: 1 - RX_LEVEL: access: r description: Reflects the current level of the Receive FIFO lsb: 8 reset_value: '0' width: 4 - TX_LEVEL: access: r description: Reflects the current level of the Transmit FIFO lsb: 16 reset_value: '0' width: 4 - I2S1_STATE: fields: !!omap - IRQ: access: r description: This bit reflects the presence of Receive Interrupt or Transmit Interrupt lsb: 0 reset_value: '1' width: 1 - DMAREQ1: access: r description: This bit reflects the presence of Receive or Transmit DMA Request 1 lsb: 1 reset_value: '1' width: 1 - DMAREQ2: access: r description: This bit reflects the presence of Receive or Transmit DMA Request 2 lsb: 2 reset_value: '1' width: 1 - RX_LEVEL: access: r description: Reflects the current level of the Receive FIFO lsb: 8 reset_value: '0' width: 4 - TX_LEVEL: access: r description: Reflects the current level of the Transmit FIFO lsb: 16 reset_value: '0' width: 4 - I2S0_DMA1: fields: !!omap - RX_DMA1_ENABLE: access: rw description: When 1, enables DMA1 for I2S receive lsb: 0 reset_value: '0' width: 1 - TX_DMA1_ENABLE: access: rw description: When 1, enables DMA1 for I2S transmit lsb: 1 reset_value: '0' width: 1 - RX_DEPTH_DMA1: access: rw description: Set the FIFO level that triggers a receive DMA request on DMA1 lsb: 8 reset_value: '0' width: 4 - TX_DEPTH_DMA1: access: rw description: Set the FIFO level that triggers a transmit DMA request on DMA1 lsb: 16 reset_value: '0' width: 4 - I2S1_DMA1: fields: !!omap - RX_DMA1_ENABLE: access: rw description: When 1, enables DMA1 for I2S receive lsb: 0 reset_value: '0' width: 1 - TX_DMA1_ENABLE: access: rw description: When 1, enables DMA1 for I2S transmit lsb: 1 reset_value: '0' width: 1 - RX_DEPTH_DMA1: access: rw description: Set the FIFO level that triggers a receive DMA request on DMA1 lsb: 8 reset_value: '0' width: 4 - TX_DEPTH_DMA1: access: rw description: Set the FIFO level that triggers a transmit DMA request on DMA1 lsb: 16 reset_value: '0' width: 4 - I2S0_DMA2: fields: !!omap - RX_DMA2_ENABLE: access: rw description: When 1, enables DMA2 for I2S receive lsb: 0 reset_value: '0' width: 1 - TX_DMA2_ENABLE: access: rw description: When 1, enables DMA2 for I2S transmit lsb: 1 reset_value: '0' width: 1 - RX_DEPTH_DMA2: access: rw description: Set the FIFO level that triggers a receive DMA request on DMA2 lsb: 8 reset_value: '0' width: 4 - TX_DEPTH_DMA2: access: rw description: Set the FIFO level that triggers a transmit DMA request on DMA2 lsb: 16 reset_value: '0' width: 4 - I2S1_DMA2: fields: !!omap - RX_DMA2_ENABLE: access: rw description: When 1, enables DMA2 for I2S receive lsb: 0 reset_value: '0' width: 1 - TX_DMA2_ENABLE: access: rw description: When 1, enables DMA2 for I2S transmit lsb: 1 reset_value: '0' width: 1 - RX_DEPTH_DMA2: access: rw description: Set the FIFO level that triggers a receive DMA request on DMA2 lsb: 8 reset_value: '0' width: 4 - TX_DEPTH_DMA2: access: rw description: Set the FIFO level that triggers a transmit DMA request on DMA2 lsb: 16 reset_value: '0' width: 4 - I2S0_IRQ: fields: !!omap - RX_IRQ_ENABLE: access: rw description: When 1, enables I2S receive interrupt lsb: 0 reset_value: '0' width: 1 - TX_IRQ_ENABLE: access: rw description: When 1, enables I2S transmit interrupt lsb: 1 reset_value: '0' width: 1 - RX_DEPTH_IRQ: access: rw description: Set the FIFO level on which to create an irq request. lsb: 8 reset_value: '0' width: 4 - TX_DEPTH_IRQ: access: rw description: Set the FIFO level on which to create an irq request. lsb: 16 reset_value: '0' width: 4 - I2S1_IRQ: fields: !!omap - RX_IRQ_ENABLE: access: rw description: When 1, enables I2S receive interrupt lsb: 0 reset_value: '0' width: 1 - TX_IRQ_ENABLE: access: rw description: When 1, enables I2S transmit interrupt lsb: 1 reset_value: '0' width: 1 - RX_DEPTH_IRQ: access: rw description: Set the FIFO level on which to create an irq request. lsb: 8 reset_value: '0' width: 4 - TX_DEPTH_IRQ: access: rw description: Set the FIFO level on which to create an irq request. lsb: 16 reset_value: '0' width: 4 - I2S0_TXRATE: fields: !!omap - Y_DIVIDER: access: rw description: I2S transmit MCLK rate denominator lsb: 0 reset_value: '0' width: 8 - X_DIVIDER: access: rw description: I2S transmit MCLK rate numerator lsb: 8 reset_value: '0' width: 8 - I2S1_TXRATE: fields: !!omap - Y_DIVIDER: access: rw description: I2S transmit MCLK rate denominator lsb: 0 reset_value: '0' width: 8 - X_DIVIDER: access: rw description: I2S transmit MCLK rate numerator lsb: 8 reset_value: '0' width: 8 - I2S0_RXRATE: fields: !!omap - Y_DIVIDER: access: rw description: I2S receive MCLK rate denominator lsb: 0 reset_value: '0' width: 8 - X_DIVIDER: access: rw description: I2S receive MCLK rate numerator lsb: 8 reset_value: '0' width: 8 - I2S1_RXRATE: fields: !!omap - Y_DIVIDER: access: rw description: I2S receive MCLK rate denominator lsb: 0 reset_value: '0' width: 8 - X_DIVIDER: access: rw description: I2S receive MCLK rate numerator lsb: 8 reset_value: '0' width: 8 - I2S0_TXBITRATE: fields: !!omap - TX_BITRATE: access: rw description: I2S transmit bit rate lsb: 0 reset_value: '0' width: 6 - I2S1_TXBITRATE: fields: !!omap - TX_BITRATE: access: rw description: I2S transmit bit rate lsb: 0 reset_value: '0' width: 6 - I2S0_RXBITRATE: fields: !!omap - RX_BITRATE: access: rw description: I2S receive bit rate lsb: 0 reset_value: '0' width: 6 - I2S1_RXBITRATE: fields: !!omap - RX_BITRATE: access: rw description: I2S receive bit rate lsb: 0 reset_value: '0' width: 6 - I2S0_TXMODE: fields: !!omap - TXCLKSEL: access: rw description: Clock source selection for the transmit bit clock divider lsb: 0 reset_value: '0' width: 2 - TX4PIN: access: rw description: Transmit 4-pin mode selection lsb: 2 reset_value: '0' width: 1 - TXMCENA: access: rw description: Enable for the TX_MCLK output lsb: 3 reset_value: '0' width: 1 - I2S1_TXMODE: fields: !!omap - TXCLKSEL: access: rw description: Clock source selection for the transmit bit clock divider lsb: 0 reset_value: '0' width: 2 - TX4PIN: access: rw description: Transmit 4-pin mode selection lsb: 2 reset_value: '0' width: 1 - TXMCENA: access: rw description: Enable for the TX_MCLK output lsb: 3 reset_value: '0' width: 1 - I2S0_RXMODE: fields: !!omap - RXCLKSEL: access: rw description: Clock source selection for the receive bit clock divider lsb: 0 reset_value: '0' width: 2 - RX4PIN: access: rw description: Receive 4-pin mode selection lsb: 2 reset_value: '0' width: 1 - RXMCENA: access: rw description: Enable for the RX_MCLK output lsb: 3 reset_value: '0' width: 1 - I2S1_RXMODE: fields: !!omap - RXCLKSEL: access: rw description: Clock source selection for the receive bit clock divider lsb: 0 reset_value: '0' width: 2 - RX4PIN: access: rw description: Receive 4-pin mode selection lsb: 2 reset_value: '0' width: 1 - RXMCENA: access: rw description: Enable for the RX_MCLK output lsb: 3 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/rgu.csv000066400000000000000000000323731435536612600227200ustar00rootroot00000000000000RESET_CTRL0,0,1,CORE_RST,Writing a one activates the reset,0,w RESET_CTRL0,1,1,PERIPH_RST,Writing a one activates the reset,0,w RESET_CTRL0,2,1,MASTER_RST,Writing a one activates the reset,0,w RESET_CTRL0,4,1,WWDT_RST,Writing a one to this bit has no effect,0, RESET_CTRL0,5,1,CREG_RST,Writing a one to this bit has no effect,0, RESET_CTRL0,8,1,BUS_RST,Writing a one activates the reset,0,w RESET_CTRL0,9,1,SCU_RST,Writing a one activates the reset,0,w RESET_CTRL0,13,1,M4_RST,Writing a one activates the reset,0,w RESET_CTRL0,16,1,LCD_RST,Writing a one activates the reset,0,w RESET_CTRL0,17,1,USB0_RST,Writing a one activates the reset,0,w RESET_CTRL0,18,1,USB1_RST,Writing a one activates the reset,0,w RESET_CTRL0,19,1,DMA_RST,Writing a one activates the reset,0,w RESET_CTRL0,20,1,SDIO_RST,Writing a one activates the reset,0,w RESET_CTRL0,21,1,EMC_RST,Writing a one activates the reset,0,w RESET_CTRL0,22,1,ETHERNET_RST,Writing a one activates the reset,0,w RESET_CTRL0,25,1,FLASHA_RST,Writing a one activates the reset,0,w RESET_CTRL0,27,1,EEPROM_RST,Writing a one activates the reset,0,w RESET_CTRL0,28,1,GPIO_RST,Writing a one activates the reset,0,w RESET_CTRL0,29,1,FLASHB_RST,Writing a one activates the reset,0,w RESET_CTRL1,0,1,TIMER0_RST,Writing a one activates the reset,0,w RESET_CTRL1,1,1,TIMER1_RST,Writing a one activates the reset,0,w RESET_CTRL1,2,1,TIMER2_RST,Writing a one activates the reset,0,w RESET_CTRL1,3,1,TIMER3_RST,Writing a one activates the reset,0,w RESET_CTRL1,4,1,RTIMER_RST,Writing a one activates the reset,0,w RESET_CTRL1,5,1,SCT_RST,Writing a one activates the reset,0,w RESET_CTRL1,6,1,MOTOCONPWM_RST,Writing a one activates the reset,0,w RESET_CTRL1,7,1,QEI_RST,Writing a one activates the reset,0,w RESET_CTRL1,8,1,ADC0_RST,Writing a one activates the reset,0,w RESET_CTRL1,9,1,ADC1_RST,Writing a one activates the reset,0,w RESET_CTRL1,10,1,DAC_RST,Writing a one activates the reset,0,w RESET_CTRL1,12,1,UART0_RST,Writing a one activates the reset,0,w RESET_CTRL1,13,1,UART1_RST,Writing a one activates the reset,0,w RESET_CTRL1,14,1,UART2_RST,Writing a one activates the reset,0,w RESET_CTRL1,15,1,UART3_RST,Writing a one activates the reset,0,w RESET_CTRL1,16,1,I2C0_RST,Writing a one activates the reset,0,w RESET_CTRL1,17,1,I2C1_RST,Writing a one activates the reset,0,w RESET_CTRL1,18,1,SSP0_RST,Writing a one activates the reset,0,w RESET_CTRL1,19,1,SSP1_RST,Writing a one activates the reset,0,w RESET_CTRL1,20,1,I2S_RST,Writing a one activates the reset,0,w RESET_CTRL1,21,1,SPIFI_RST,Writing a one activates the reset,0,w RESET_CTRL1,22,1,CAN1_RST,Writing a one activates the reset,0,w RESET_CTRL1,23,1,CAN0_RST,Writing a one activates the reset,0,w RESET_CTRL1,24,1,M0APP_RST,Writing a one activates the reset,1,w RESET_CTRL1,25,1,SGPIO_RST,Writing a one activates the reset,0,w RESET_CTRL1,26,1,SPI_RST,Writing a one activates the reset,0,w RESET_STATUS0,0,2,CORE_RST,Status of the CORE_RST reset generator output,0x0,rw RESET_STATUS0,2,2,PERIPH_RST,Status of the PERIPH_RST reset generator output,0x0,rw RESET_STATUS0,4,2,MASTER_RST,Status of the MASTER_RST reset generator output,0x1,rw RESET_STATUS0,8,2,WWDT_RST,Status of the WWDT_RST reset generator output,0x0,rw RESET_STATUS0,10,2,CREG_RST,Status of the CREG_RST reset generator output,0x0,rw RESET_STATUS0,16,2,BUS_RST,Status of the BUS_RST reset generator output,0x1,rw RESET_STATUS0,18,2,SCU_RST,Status of the SCU_RST reset generator output,0x1,rw RESET_STATUS0,26,2,M4_RST,Status of the M4_RST reset generator output,0x1,rw RESET_STATUS1,0,2,LCD_RST,Status of the LCD_RST reset generator output,0x1,rw RESET_STATUS1,2,2,USB0_RST,Status of the USB0_RST reset generator output,0x1,rw RESET_STATUS1,4,2,USB1_RST,Status of the USB1_RST reset generator output,0x1,rw RESET_STATUS1,6,2,DMA_RST,Status of the DMA_RST reset generator output,0x1,rw RESET_STATUS1,8,2,SDIO_RST,Status of the SDIO_RST reset generator output,0x1,rw RESET_STATUS1,10,2,EMC_RST,Status of the EMC_RST reset generator output,0x1,rw RESET_STATUS1,12,2,ETHERNET_RST,Status of the ETHERNET_RST reset generator output,0x1,rw RESET_STATUS1,18,2,FLASHA_RST,Status of the FLASHA_RST reset generator output,0x1, RESET_STATUS1,22,2,EEPROM_RST,Status of the EEPROM_RST reset generator output,0x1, RESET_STATUS1,24,2,GPIO_RST,Status of the GPIO_RST reset generator output,0x1,rw RESET_STATUS1,26,2,FLASHB_RST,Status of the FLASHB_RST reset generator output,0x1,rw RESET_STATUS2,0,2,TIMER0_RST,Status of the TIMER0_RST reset generator output,0x1,rw RESET_STATUS2,2,2,TIMER1_RST,Status of the TIMER1_RST reset generator output,0x1,rw RESET_STATUS2,4,2,TIMER2_RST,Status of the TIMER2_RST reset generator output,0x1,rw RESET_STATUS2,6,2,TIMER3_RST,Status of the TIMER3_RST reset generator output,0x1,rw RESET_STATUS2,8,2,RITIMER_RST,Status of the RITIMER_RST reset generator output,0x1,rw RESET_STATUS2,10,2,SCT_RST,Status of the SCT_RST reset generator output,0x1,rw RESET_STATUS2,12,2,MOTOCONPWM_RST,Status of the MOTOCONPWM_RST reset generator output,0x1,rw RESET_STATUS2,14,2,QEI_RST,Status of the QEI_RST reset generator output,0x1,rw RESET_STATUS2,16,2,ADC0_RST,Status of the ADC0_RST reset generator output,0x1,rw RESET_STATUS2,18,2,ADC1_RST,Status of the ADC1_RST reset generator output,0x1,rw RESET_STATUS2,20,2,DAC_RST,Status of the DAC_RST reset generator output,0x1,rw RESET_STATUS2,24,2,UART0_RST,Status of the UART0_RST reset generator output,0x1,rw RESET_STATUS2,26,2,UART1_RST,Status of the UART1_RST reset generator output,0x1,rw RESET_STATUS2,28,2,UART2_RST,Status of the UART2_RST reset generator output,0x1,rw RESET_STATUS2,30,2,UART3_RST,Status of the UART3_RST reset generator output,0x1,rw RESET_STATUS3,0,2,I2C0_RST,Status of the I2C0_RST reset generator output,0x1,rw RESET_STATUS3,2,2,I2C1_RST,Status of the I2C1_RST reset generator output,0x1,rw RESET_STATUS3,4,2,SSP0_RST,Status of the SSP0_RST reset generator output,0x1,rw RESET_STATUS3,6,2,SSP1_RST,Status of the SSP1_RST reset generator output,0x1,rw RESET_STATUS3,8,2,I2S_RST,Status of the I2S_RST reset generator output,0x1,rw RESET_STATUS3,10,2,SPIFI_RST,Status of the SPIFI_RST reset generator output,0x1,rw RESET_STATUS3,12,2,CAN1_RST,Status of the CAN1_RST reset generator output,0x1,rw RESET_STATUS3,14,2,CAN0_RST,Status of the CAN0_RST reset generator output,0x1,rw RESET_STATUS3,16,2,M0APP_RST,Status of the M0APP_RST reset generator output,0x3,rw RESET_STATUS3,18,2,SGPIO_RST,Status of the SGPIO_RST reset generator output,0x1,rw RESET_STATUS3,20,2,SPI_RST,Status of the SPI_RST reset generator output,0x1,rw RESET_ACTIVE_STATUS0,0,1,CORE_RST,Current status of the CORE_RST,0,r RESET_ACTIVE_STATUS0,1,1,PERIPH_RST,Current status of the PERIPH_RST,0,r RESET_ACTIVE_STATUS0,2,1,MASTER_RST,Current status of the MASTER_RST,0,r RESET_ACTIVE_STATUS0,4,1,WWDT_RST,Current status of the WWDT_RST,0,r RESET_ACTIVE_STATUS0,5,1,CREG_RST,Current status of the CREG_RST,0,r RESET_ACTIVE_STATUS0,8,1,BUS_RST,Current status of the BUS_RST,0,r RESET_ACTIVE_STATUS0,9,1,SCU_RST,Current status of the SCU_RST,0,r RESET_ACTIVE_STATUS0,13,1,M4_RST,Current status of the M4_RST,0,r RESET_ACTIVE_STATUS0,16,1,LCD_RST,Current status of the LCD_RST,0,r RESET_ACTIVE_STATUS0,17,1,USB0_RST,Current status of the USB0_RST,0,r RESET_ACTIVE_STATUS0,18,1,USB1_RST,Current status of the USB1_RST,0,r RESET_ACTIVE_STATUS0,19,1,DMA_RST,Current status of the DMA_RST,0,r RESET_ACTIVE_STATUS0,20,1,SDIO_RST,Current status of the SDIO_RST,0,r RESET_ACTIVE_STATUS0,21,1,EMC_RST,Current status of the EMC_RST,0,r RESET_ACTIVE_STATUS0,22,1,ETHERNET_RST,Current status of the ETHERNET_RST,0,r RESET_ACTIVE_STATUS0,25,1,FLASHA_RST,Current status of the FLASHA_RST,0,r RESET_ACTIVE_STATUS0,27,1,EEPROM_RST,Current status of the EEPROM_RST,0,r RESET_ACTIVE_STATUS0,28,1,GPIO_RST,Current status of the GPIO_RST,0,r RESET_ACTIVE_STATUS0,29,1,FLASHB_RST,Current status of the FLASHB_RST,0,r RESET_ACTIVE_STATUS1,0,1,TIMER0_RST,Current status of the TIMER0_RST,0,r RESET_ACTIVE_STATUS1,1,1,TIMER1_RST,Current status of the TIMER1_RST,0,r RESET_ACTIVE_STATUS1,2,1,TIMER2_RST,Current status of the TIMER2_RST,0,r RESET_ACTIVE_STATUS1,3,1,TIMER3_RST,Current status of the TIMER3_RST,0,r RESET_ACTIVE_STATUS1,4,1,RITIMER_RST,Current status of the RITIMER_RST,0,r RESET_ACTIVE_STATUS1,5,1,SCT_RST,Current status of the SCT_RST,0,r RESET_ACTIVE_STATUS1,6,1,MOTOCONPWM_RST,Current status of the MOTOCONPWM_RST,0,r RESET_ACTIVE_STATUS1,7,1,QEI_RST,Current status of the QEI_RST,0,r RESET_ACTIVE_STATUS1,8,1,ADC0_RST,Current status of the ADC0_RST,0,r RESET_ACTIVE_STATUS1,9,1,ADC1_RST,Current status of the ADC1_RST,0,r RESET_ACTIVE_STATUS1,10,1,DAC_RST,Current status of the DAC_RST,0,r RESET_ACTIVE_STATUS1,12,1,UART0_RST,Current status of the UART0_RST,0,r RESET_ACTIVE_STATUS1,13,1,UART1_RST,Current status of the UART1_RST,0,r RESET_ACTIVE_STATUS1,14,1,UART2_RST,Current status of the UART2_RST,0,r RESET_ACTIVE_STATUS1,15,1,UART3_RST,Current status of the UART3_RST,0,r RESET_ACTIVE_STATUS1,16,1,I2C0_RST,Current status of the I2C0_RST,0,r RESET_ACTIVE_STATUS1,17,1,I2C1_RST,Current status of the I2C1_RST,0,r RESET_ACTIVE_STATUS1,18,1,SSP0_RST,Current status of the SSP0_RST,0,r RESET_ACTIVE_STATUS1,19,1,SSP1_RST,Current status of the SSP1_RST,0,r RESET_ACTIVE_STATUS1,20,1,I2S_RST,Current status of the I2S_RST,0,r RESET_ACTIVE_STATUS1,21,1,SPIFI_RST,Current status of the SPIFI_RST,0,r RESET_ACTIVE_STATUS1,22,1,CAN1_RST,Current status of the CAN1_RST,0,r RESET_ACTIVE_STATUS1,23,1,CAN0_RST,Current status of the CAN0_RST,0,r RESET_ACTIVE_STATUS1,24,1,M0APP_RST,Current status of the M0APP_RST,0,r RESET_ACTIVE_STATUS1,25,1,SGPIO_RST,Current status of the SGPIO_RST,0,r RESET_ACTIVE_STATUS1,26,1,SPI_RST,Current status of the SPI_RST,0,r RESET_EXT_STAT0,0,1,EXT_RESET,Reset activated by external reset from reset pin,0,rw RESET_EXT_STAT0,4,1,BOD_RESET,Reset activated by BOD reset,0,rw RESET_EXT_STAT0,5,1,WWDT_RESET,Reset activated by WWDT time-out,0,rw RESET_EXT_STAT1,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw RESET_EXT_STAT2,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT4,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw RESET_EXT_STAT5,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw RESET_EXT_STAT8,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT9,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT13,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT16,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT17,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT18,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT19,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT20,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT21,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT22,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw RESET_EXT_STAT25,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT27,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT28,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT29,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT32,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT33,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT34,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT35,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT36,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT37,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT38,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT39,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT40,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT41,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT42,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT44,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT45,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT46,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT47,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT48,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT49,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT50,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT51,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT52,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT53,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT54,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT55,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT56,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,,rw RESET_EXT_STAT57,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw RESET_EXT_STAT58,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/rgu.yaml000066400000000000000000000724711435536612600230720ustar00rootroot00000000000000!!omap - RESET_CTRL0: fields: !!omap - CORE_RST: access: w description: Writing a one activates the reset lsb: 0 reset_value: '0' width: 1 - PERIPH_RST: access: w description: Writing a one activates the reset lsb: 1 reset_value: '0' width: 1 - MASTER_RST: access: w description: Writing a one activates the reset lsb: 2 reset_value: '0' width: 1 - WWDT_RST: access: '' description: Writing a one to this bit has no effect lsb: 4 reset_value: '0' width: 1 - CREG_RST: access: '' description: Writing a one to this bit has no effect lsb: 5 reset_value: '0' width: 1 - BUS_RST: access: w description: Writing a one activates the reset lsb: 8 reset_value: '0' width: 1 - SCU_RST: access: w description: Writing a one activates the reset lsb: 9 reset_value: '0' width: 1 - M4_RST: access: w description: Writing a one activates the reset lsb: 13 reset_value: '0' width: 1 - LCD_RST: access: w description: Writing a one activates the reset lsb: 16 reset_value: '0' width: 1 - USB0_RST: access: w description: Writing a one activates the reset lsb: 17 reset_value: '0' width: 1 - USB1_RST: access: w description: Writing a one activates the reset lsb: 18 reset_value: '0' width: 1 - DMA_RST: access: w description: Writing a one activates the reset lsb: 19 reset_value: '0' width: 1 - SDIO_RST: access: w description: Writing a one activates the reset lsb: 20 reset_value: '0' width: 1 - EMC_RST: access: w description: Writing a one activates the reset lsb: 21 reset_value: '0' width: 1 - ETHERNET_RST: access: w description: Writing a one activates the reset lsb: 22 reset_value: '0' width: 1 - FLASHA_RST: access: w description: Writing a one activates the reset lsb: 25 reset_value: '0' width: 1 - EEPROM_RST: access: w description: Writing a one activates the reset lsb: 27 reset_value: '0' width: 1 - GPIO_RST: access: w description: Writing a one activates the reset lsb: 28 reset_value: '0' width: 1 - FLASHB_RST: access: w description: Writing a one activates the reset lsb: 29 reset_value: '0' width: 1 - RESET_CTRL1: fields: !!omap - TIMER0_RST: access: w description: Writing a one activates the reset lsb: 0 reset_value: '0' width: 1 - TIMER1_RST: access: w description: Writing a one activates the reset lsb: 1 reset_value: '0' width: 1 - TIMER2_RST: access: w description: Writing a one activates the reset lsb: 2 reset_value: '0' width: 1 - TIMER3_RST: access: w description: Writing a one activates the reset lsb: 3 reset_value: '0' width: 1 - RTIMER_RST: access: w description: Writing a one activates the reset lsb: 4 reset_value: '0' width: 1 - SCT_RST: access: w description: Writing a one activates the reset lsb: 5 reset_value: '0' width: 1 - MOTOCONPWM_RST: access: w description: Writing a one activates the reset lsb: 6 reset_value: '0' width: 1 - QEI_RST: access: w description: Writing a one activates the reset lsb: 7 reset_value: '0' width: 1 - ADC0_RST: access: w description: Writing a one activates the reset lsb: 8 reset_value: '0' width: 1 - ADC1_RST: access: w description: Writing a one activates the reset lsb: 9 reset_value: '0' width: 1 - DAC_RST: access: w description: Writing a one activates the reset lsb: 10 reset_value: '0' width: 1 - UART0_RST: access: w description: Writing a one activates the reset lsb: 12 reset_value: '0' width: 1 - UART1_RST: access: w description: Writing a one activates the reset lsb: 13 reset_value: '0' width: 1 - UART2_RST: access: w description: Writing a one activates the reset lsb: 14 reset_value: '0' width: 1 - UART3_RST: access: w description: Writing a one activates the reset lsb: 15 reset_value: '0' width: 1 - I2C0_RST: access: w description: Writing a one activates the reset lsb: 16 reset_value: '0' width: 1 - I2C1_RST: access: w description: Writing a one activates the reset lsb: 17 reset_value: '0' width: 1 - SSP0_RST: access: w description: Writing a one activates the reset lsb: 18 reset_value: '0' width: 1 - SSP1_RST: access: w description: Writing a one activates the reset lsb: 19 reset_value: '0' width: 1 - I2S_RST: access: w description: Writing a one activates the reset lsb: 20 reset_value: '0' width: 1 - SPIFI_RST: access: w description: Writing a one activates the reset lsb: 21 reset_value: '0' width: 1 - CAN1_RST: access: w description: Writing a one activates the reset lsb: 22 reset_value: '0' width: 1 - CAN0_RST: access: w description: Writing a one activates the reset lsb: 23 reset_value: '0' width: 1 - M0APP_RST: access: w description: Writing a one activates the reset lsb: 24 reset_value: '1' width: 1 - SGPIO_RST: access: w description: Writing a one activates the reset lsb: 25 reset_value: '0' width: 1 - SPI_RST: access: w description: Writing a one activates the reset lsb: 26 reset_value: '0' width: 1 - RESET_STATUS0: fields: !!omap - CORE_RST: access: rw description: Status of the CORE_RST reset generator output lsb: 0 reset_value: '0x0' width: 2 - PERIPH_RST: access: rw description: Status of the PERIPH_RST reset generator output lsb: 2 reset_value: '0x0' width: 2 - MASTER_RST: access: rw description: Status of the MASTER_RST reset generator output lsb: 4 reset_value: '0x1' width: 2 - WWDT_RST: access: rw description: Status of the WWDT_RST reset generator output lsb: 8 reset_value: '0x0' width: 2 - CREG_RST: access: rw description: Status of the CREG_RST reset generator output lsb: 10 reset_value: '0x0' width: 2 - BUS_RST: access: rw description: Status of the BUS_RST reset generator output lsb: 16 reset_value: '0x1' width: 2 - SCU_RST: access: rw description: Status of the SCU_RST reset generator output lsb: 18 reset_value: '0x1' width: 2 - M4_RST: access: rw description: Status of the M4_RST reset generator output lsb: 26 reset_value: '0x1' width: 2 - RESET_STATUS1: fields: !!omap - LCD_RST: access: rw description: Status of the LCD_RST reset generator output lsb: 0 reset_value: '0x1' width: 2 - USB0_RST: access: rw description: Status of the USB0_RST reset generator output lsb: 2 reset_value: '0x1' width: 2 - USB1_RST: access: rw description: Status of the USB1_RST reset generator output lsb: 4 reset_value: '0x1' width: 2 - DMA_RST: access: rw description: Status of the DMA_RST reset generator output lsb: 6 reset_value: '0x1' width: 2 - SDIO_RST: access: rw description: Status of the SDIO_RST reset generator output lsb: 8 reset_value: '0x1' width: 2 - EMC_RST: access: rw description: Status of the EMC_RST reset generator output lsb: 10 reset_value: '0x1' width: 2 - ETHERNET_RST: access: rw description: Status of the ETHERNET_RST reset generator output lsb: 12 reset_value: '0x1' width: 2 - FLASHA_RST: access: '' description: Status of the FLASHA_RST reset generator output lsb: 18 reset_value: '0x1' width: 2 - EEPROM_RST: access: '' description: Status of the EEPROM_RST reset generator output lsb: 22 reset_value: '0x1' width: 2 - GPIO_RST: access: rw description: Status of the GPIO_RST reset generator output lsb: 24 reset_value: '0x1' width: 2 - FLASHB_RST: access: rw description: Status of the FLASHB_RST reset generator output lsb: 26 reset_value: '0x1' width: 2 - RESET_STATUS2: fields: !!omap - TIMER0_RST: access: rw description: Status of the TIMER0_RST reset generator output lsb: 0 reset_value: '0x1' width: 2 - TIMER1_RST: access: rw description: Status of the TIMER1_RST reset generator output lsb: 2 reset_value: '0x1' width: 2 - TIMER2_RST: access: rw description: Status of the TIMER2_RST reset generator output lsb: 4 reset_value: '0x1' width: 2 - TIMER3_RST: access: rw description: Status of the TIMER3_RST reset generator output lsb: 6 reset_value: '0x1' width: 2 - RITIMER_RST: access: rw description: Status of the RITIMER_RST reset generator output lsb: 8 reset_value: '0x1' width: 2 - SCT_RST: access: rw description: Status of the SCT_RST reset generator output lsb: 10 reset_value: '0x1' width: 2 - MOTOCONPWM_RST: access: rw description: Status of the MOTOCONPWM_RST reset generator output lsb: 12 reset_value: '0x1' width: 2 - QEI_RST: access: rw description: Status of the QEI_RST reset generator output lsb: 14 reset_value: '0x1' width: 2 - ADC0_RST: access: rw description: Status of the ADC0_RST reset generator output lsb: 16 reset_value: '0x1' width: 2 - ADC1_RST: access: rw description: Status of the ADC1_RST reset generator output lsb: 18 reset_value: '0x1' width: 2 - DAC_RST: access: rw description: Status of the DAC_RST reset generator output lsb: 20 reset_value: '0x1' width: 2 - UART0_RST: access: rw description: Status of the UART0_RST reset generator output lsb: 24 reset_value: '0x1' width: 2 - UART1_RST: access: rw description: Status of the UART1_RST reset generator output lsb: 26 reset_value: '0x1' width: 2 - UART2_RST: access: rw description: Status of the UART2_RST reset generator output lsb: 28 reset_value: '0x1' width: 2 - UART3_RST: access: rw description: Status of the UART3_RST reset generator output lsb: 30 reset_value: '0x1' width: 2 - RESET_STATUS3: fields: !!omap - I2C0_RST: access: rw description: Status of the I2C0_RST reset generator output lsb: 0 reset_value: '0x1' width: 2 - I2C1_RST: access: rw description: Status of the I2C1_RST reset generator output lsb: 2 reset_value: '0x1' width: 2 - SSP0_RST: access: rw description: Status of the SSP0_RST reset generator output lsb: 4 reset_value: '0x1' width: 2 - SSP1_RST: access: rw description: Status of the SSP1_RST reset generator output lsb: 6 reset_value: '0x1' width: 2 - I2S_RST: access: rw description: Status of the I2S_RST reset generator output lsb: 8 reset_value: '0x1' width: 2 - SPIFI_RST: access: rw description: Status of the SPIFI_RST reset generator output lsb: 10 reset_value: '0x1' width: 2 - CAN1_RST: access: rw description: Status of the CAN1_RST reset generator output lsb: 12 reset_value: '0x1' width: 2 - CAN0_RST: access: rw description: Status of the CAN0_RST reset generator output lsb: 14 reset_value: '0x1' width: 2 - M0APP_RST: access: rw description: Status of the M0APP_RST reset generator output lsb: 16 reset_value: '0x3' width: 2 - SGPIO_RST: access: rw description: Status of the SGPIO_RST reset generator output lsb: 18 reset_value: '0x1' width: 2 - SPI_RST: access: rw description: Status of the SPI_RST reset generator output lsb: 20 reset_value: '0x1' width: 2 - RESET_ACTIVE_STATUS0: fields: !!omap - CORE_RST: access: r description: Current status of the CORE_RST lsb: 0 reset_value: '0' width: 1 - PERIPH_RST: access: r description: Current status of the PERIPH_RST lsb: 1 reset_value: '0' width: 1 - MASTER_RST: access: r description: Current status of the MASTER_RST lsb: 2 reset_value: '0' width: 1 - WWDT_RST: access: r description: Current status of the WWDT_RST lsb: 4 reset_value: '0' width: 1 - CREG_RST: access: r description: Current status of the CREG_RST lsb: 5 reset_value: '0' width: 1 - BUS_RST: access: r description: Current status of the BUS_RST lsb: 8 reset_value: '0' width: 1 - SCU_RST: access: r description: Current status of the SCU_RST lsb: 9 reset_value: '0' width: 1 - M4_RST: access: r description: Current status of the M4_RST lsb: 13 reset_value: '0' width: 1 - LCD_RST: access: r description: Current status of the LCD_RST lsb: 16 reset_value: '0' width: 1 - USB0_RST: access: r description: Current status of the USB0_RST lsb: 17 reset_value: '0' width: 1 - USB1_RST: access: r description: Current status of the USB1_RST lsb: 18 reset_value: '0' width: 1 - DMA_RST: access: r description: Current status of the DMA_RST lsb: 19 reset_value: '0' width: 1 - SDIO_RST: access: r description: Current status of the SDIO_RST lsb: 20 reset_value: '0' width: 1 - EMC_RST: access: r description: Current status of the EMC_RST lsb: 21 reset_value: '0' width: 1 - ETHERNET_RST: access: r description: Current status of the ETHERNET_RST lsb: 22 reset_value: '0' width: 1 - FLASHA_RST: access: r description: Current status of the FLASHA_RST lsb: 25 reset_value: '0' width: 1 - EEPROM_RST: access: r description: Current status of the EEPROM_RST lsb: 27 reset_value: '0' width: 1 - GPIO_RST: access: r description: Current status of the GPIO_RST lsb: 28 reset_value: '0' width: 1 - FLASHB_RST: access: r description: Current status of the FLASHB_RST lsb: 29 reset_value: '0' width: 1 - RESET_ACTIVE_STATUS1: fields: !!omap - TIMER0_RST: access: r description: Current status of the TIMER0_RST lsb: 0 reset_value: '0' width: 1 - TIMER1_RST: access: r description: Current status of the TIMER1_RST lsb: 1 reset_value: '0' width: 1 - TIMER2_RST: access: r description: Current status of the TIMER2_RST lsb: 2 reset_value: '0' width: 1 - TIMER3_RST: access: r description: Current status of the TIMER3_RST lsb: 3 reset_value: '0' width: 1 - RITIMER_RST: access: r description: Current status of the RITIMER_RST lsb: 4 reset_value: '0' width: 1 - SCT_RST: access: r description: Current status of the SCT_RST lsb: 5 reset_value: '0' width: 1 - MOTOCONPWM_RST: access: r description: Current status of the MOTOCONPWM_RST lsb: 6 reset_value: '0' width: 1 - QEI_RST: access: r description: Current status of the QEI_RST lsb: 7 reset_value: '0' width: 1 - ADC0_RST: access: r description: Current status of the ADC0_RST lsb: 8 reset_value: '0' width: 1 - ADC1_RST: access: r description: Current status of the ADC1_RST lsb: 9 reset_value: '0' width: 1 - DAC_RST: access: r description: Current status of the DAC_RST lsb: 10 reset_value: '0' width: 1 - UART0_RST: access: r description: Current status of the UART0_RST lsb: 12 reset_value: '0' width: 1 - UART1_RST: access: r description: Current status of the UART1_RST lsb: 13 reset_value: '0' width: 1 - UART2_RST: access: r description: Current status of the UART2_RST lsb: 14 reset_value: '0' width: 1 - UART3_RST: access: r description: Current status of the UART3_RST lsb: 15 reset_value: '0' width: 1 - I2C0_RST: access: r description: Current status of the I2C0_RST lsb: 16 reset_value: '0' width: 1 - I2C1_RST: access: r description: Current status of the I2C1_RST lsb: 17 reset_value: '0' width: 1 - SSP0_RST: access: r description: Current status of the SSP0_RST lsb: 18 reset_value: '0' width: 1 - SSP1_RST: access: r description: Current status of the SSP1_RST lsb: 19 reset_value: '0' width: 1 - I2S_RST: access: r description: Current status of the I2S_RST lsb: 20 reset_value: '0' width: 1 - SPIFI_RST: access: r description: Current status of the SPIFI_RST lsb: 21 reset_value: '0' width: 1 - CAN1_RST: access: r description: Current status of the CAN1_RST lsb: 22 reset_value: '0' width: 1 - CAN0_RST: access: r description: Current status of the CAN0_RST lsb: 23 reset_value: '0' width: 1 - M0APP_RST: access: r description: Current status of the M0APP_RST lsb: 24 reset_value: '0' width: 1 - SGPIO_RST: access: r description: Current status of the SGPIO_RST lsb: 25 reset_value: '0' width: 1 - SPI_RST: access: r description: Current status of the SPI_RST lsb: 26 reset_value: '0' width: 1 - RESET_EXT_STAT0: fields: !!omap - EXT_RESET: access: rw description: Reset activated by external reset from reset pin lsb: 0 reset_value: '0' width: 1 - BOD_RESET: access: rw description: Reset activated by BOD reset lsb: 4 reset_value: '0' width: 1 - WWDT_RESET: access: rw description: Reset activated by WWDT time-out lsb: 5 reset_value: '0' width: 1 - RESET_EXT_STAT1: fields: !!omap - CORE_RESET: access: rw description: Reset activated by CORE_RST output lsb: 1 reset_value: '0' width: 1 - RESET_EXT_STAT2: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT4: fields: !!omap - CORE_RESET: access: rw description: Reset activated by CORE_RST output lsb: 1 reset_value: '0' width: 1 - RESET_EXT_STAT5: fields: !!omap - CORE_RESET: access: rw description: Reset activated by CORE_RST output lsb: 1 reset_value: '0' width: 1 - RESET_EXT_STAT8: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT9: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT13: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT16: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT17: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT18: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT19: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT20: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT21: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT22: fields: !!omap - MASTER_RESET: access: rw description: Reset activated by MASTER_RST output lsb: 3 reset_value: '0' width: 1 - RESET_EXT_STAT25: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT27: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT28: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT29: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT32: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT33: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT34: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT35: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT36: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT37: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT38: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT39: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT40: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT41: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT42: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT44: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT45: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT46: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT47: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT48: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT49: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT50: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT51: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT52: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT53: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT54: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT55: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT56: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '' width: 1 - RESET_EXT_STAT57: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 - RESET_EXT_STAT58: fields: !!omap - PERIPHERAL_RESET: access: rw description: Reset activated by PERIPHERAL_RST output lsb: 2 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/ritimer.csv000066400000000000000000000005311435536612600235650ustar00rootroot00000000000000RITIMER_COMPVAL,0,32,RICOMP,Compare register,0xFFFFFFFF,rw RITIMER_MASK,0,32,RIMASK,Mask register,0,rw RITIMER_CTRL,0,1,RITINT,Interrupt flag,0,rw RITIMER_CTRL,1,1,RITENCLR,Timer enable clear,0,rw RITIMER_CTRL,2,1,RITENBR,Timer enable for debug,1,rw RITIMER_CTRL,3,1,RITEN,Timer enable,1,rw RITIMER_COUNTER,0,32,RICOUNTER,32-bit up counter,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/ritimer.yaml000066400000000000000000000020521435536612600237340ustar00rootroot00000000000000!!omap - RITIMER_COMPVAL: fields: !!omap - RICOMP: access: rw description: Compare register lsb: 0 reset_value: '0xFFFFFFFF' width: 32 - RITIMER_MASK: fields: !!omap - RIMASK: access: rw description: Mask register lsb: 0 reset_value: '0' width: 32 - RITIMER_CTRL: fields: !!omap - RITINT: access: rw description: Interrupt flag lsb: 0 reset_value: '0' width: 1 - RITENCLR: access: rw description: Timer enable clear lsb: 1 reset_value: '0' width: 1 - RITENBR: access: rw description: Timer enable for debug lsb: 2 reset_value: '1' width: 1 - RITEN: access: rw description: Timer enable lsb: 3 reset_value: '1' width: 1 - RITIMER_COUNTER: fields: !!omap - RICOUNTER: access: rw description: 32-bit up counter lsb: 0 reset_value: '0' width: 32 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/rtc.csv000066400000000000000000000037201435536612600227050ustar00rootroot00000000000000RTC_ILR,0,1,RTCCIF,Counter increment interrupt block interrupted,0,w RTC_ILR,1,1,RTCALF,Alarm interrupted,0,w RTC_CCR,0,1,CLKEN,Clock enable,,rw RTC_CCR,1,1,CTCRST,CTC reset,0,rw RTC_CCR,4,1,CCALEN,Calibration counter enable,,rw RTC_CIIR,0,1,IMSEC,Second interrupt enable,0,rw RTC_CIIR,1,1,IMMIN,Minute interrupt enable,0,rw RTC_CIIR,2,1,IMHOUR,Hour interrupt enable,0,rw RTC_CIIR,3,1,IMDOM,Day of month interrupt enable,0,rw RTC_CIIR,4,1,IMDOW,Day of week interrupt enable,0,rw RTC_CIIR,5,1,IMDOY,Day of year interrupt enable,0,rw RTC_CIIR,6,1,IMMON,Month interrupt enable,0,rw RTC_CIIR,7,1,IMYEAR,Year interrupt enable,0,rw RTC_AMR,0,1,AMRSEC,Second not compared for alarm,0,rw RTC_AMR,1,1,AMRMIN,Minute not compared for alarm,0,rw RTC_AMR,2,1,AMRHOUR,Hour not compared for alarm,0,rw RTC_AMR,3,1,AMRDOM,Day of month not compared for alarm,0,rw RTC_AMR,4,1,AMRDOW,Day of week not compared for alarm,0,rw RTC_AMR,5,1,AMRDOY,Day of year not compared for alarm,0,rw RTC_AMR,6,1,AMRMON,Month not compared for alarm,0,rw RTC_AMR,7,1,AMRYEAR,Year not compared for alarm,0,rw RTC_CTIME0,0,6,SECONDS,Seconds,,r RTC_CTIME0,8,6,MINUTES,Minutes,,r RTC_CTIME0,16,5,HOURS,Hours,,r RTC_CTIME0,24,3,DOW,Day of week,,r RTC_CTIME1,0,5,DOM,Day of month,,r RTC_CTIME1,8,4,MONTH,Month,,r RTC_CTIME1,16,12,YEAR,Year,,r RTC_CTIME2,0,12,DOY,Day of year,,r RTC_SEC,0,6,SECONDS,Seconds,,rw RTC_MIN,0,6,MINUTES,Minutes,,rw RTC_HRS,0,5,HOURS,Hours,,rw RTC_DOM,0,5,DOM,Day of month,,rw RTC_DOW,0,3,DOW,Day of week,,rw RTC_DOY,0,9,DOY,Day of year,,rw RTC_MONTH,0,4,MONTH,Month,,rw RTC_YEAR,0,12,YEAR,Year,,rw RTC_CALIBRATION,0,17,CALVAL,Calibration counter max,,rw RTC_CALIBRATION,17,1,CALDIR,Calibration counter direction,,rw RTC_ASEC,0,6,SECONDS,Alarm seconds,,rw RTC_AMIN,0,6,MINUTES,Alarm minutes,,rw RTC_AHRS,0,5,HOURS,Alarm hours,,rw RTC_ADOM,0,5,DOM,Alarm day of month,,rw RTC_ADOW,0,3,DOW,Alarm day of week,,rw RTC_ADOY,0,9,DOY,Alarm day of year,,rw RTC_AMON,0,4,MONTH,Alarm month,,rw RTC_AYRS,0,12,YEAR,Alarm year,,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/rtc.yaml000066400000000000000000000152021435536612600230520ustar00rootroot00000000000000!!omap - RTC_ILR: fields: !!omap - RTCCIF: access: w description: Counter increment interrupt block interrupted lsb: 0 reset_value: '0' width: 1 - RTCALF: access: w description: Alarm interrupted lsb: 1 reset_value: '0' width: 1 - RTC_CCR: fields: !!omap - CLKEN: access: rw description: Clock enable lsb: 0 reset_value: '' width: 1 - CTCRST: access: rw description: CTC reset lsb: 1 reset_value: '0' width: 1 - CCALEN: access: rw description: Calibration counter enable lsb: 4 reset_value: '' width: 1 - RTC_CIIR: fields: !!omap - IMSEC: access: rw description: Second interrupt enable lsb: 0 reset_value: '0' width: 1 - IMMIN: access: rw description: Minute interrupt enable lsb: 1 reset_value: '0' width: 1 - IMHOUR: access: rw description: Hour interrupt enable lsb: 2 reset_value: '0' width: 1 - IMDOM: access: rw description: Day of month interrupt enable lsb: 3 reset_value: '0' width: 1 - IMDOW: access: rw description: Day of week interrupt enable lsb: 4 reset_value: '0' width: 1 - IMDOY: access: rw description: Day of year interrupt enable lsb: 5 reset_value: '0' width: 1 - IMMON: access: rw description: Month interrupt enable lsb: 6 reset_value: '0' width: 1 - IMYEAR: access: rw description: Year interrupt enable lsb: 7 reset_value: '0' width: 1 - RTC_AMR: fields: !!omap - AMRSEC: access: rw description: Second not compared for alarm lsb: 0 reset_value: '0' width: 1 - AMRMIN: access: rw description: Minute not compared for alarm lsb: 1 reset_value: '0' width: 1 - AMRHOUR: access: rw description: Hour not compared for alarm lsb: 2 reset_value: '0' width: 1 - AMRDOM: access: rw description: Day of month not compared for alarm lsb: 3 reset_value: '0' width: 1 - AMRDOW: access: rw description: Day of week not compared for alarm lsb: 4 reset_value: '0' width: 1 - AMRDOY: access: rw description: Day of year not compared for alarm lsb: 5 reset_value: '0' width: 1 - AMRMON: access: rw description: Month not compared for alarm lsb: 6 reset_value: '0' width: 1 - AMRYEAR: access: rw description: Year not compared for alarm lsb: 7 reset_value: '0' width: 1 - RTC_CTIME0: fields: !!omap - SECONDS: access: r description: Seconds lsb: 0 reset_value: '' width: 6 - MINUTES: access: r description: Minutes lsb: 8 reset_value: '' width: 6 - HOURS: access: r description: Hours lsb: 16 reset_value: '' width: 5 - DOW: access: r description: Day of week lsb: 24 reset_value: '' width: 3 - RTC_CTIME1: fields: !!omap - DOM: access: r description: Day of month lsb: 0 reset_value: '' width: 5 - MONTH: access: r description: Month lsb: 8 reset_value: '' width: 4 - YEAR: access: r description: Year lsb: 16 reset_value: '' width: 12 - RTC_CTIME2: fields: !!omap - DOY: access: r description: Day of year lsb: 0 reset_value: '' width: 12 - RTC_SEC: fields: !!omap - SECONDS: access: rw description: Seconds lsb: 0 reset_value: '' width: 6 - RTC_MIN: fields: !!omap - MINUTES: access: rw description: Minutes lsb: 0 reset_value: '' width: 6 - RTC_HRS: fields: !!omap - HOURS: access: rw description: Hours lsb: 0 reset_value: '' width: 5 - RTC_DOM: fields: !!omap - DOM: access: rw description: Day of month lsb: 0 reset_value: '' width: 5 - RTC_DOW: fields: !!omap - DOW: access: rw description: Day of week lsb: 0 reset_value: '' width: 3 - RTC_DOY: fields: !!omap - DOY: access: rw description: Day of year lsb: 0 reset_value: '' width: 9 - RTC_MONTH: fields: !!omap - MONTH: access: rw description: Month lsb: 0 reset_value: '' width: 4 - RTC_YEAR: fields: !!omap - YEAR: access: rw description: Year lsb: 0 reset_value: '' width: 12 - RTC_CALIBRATION: fields: !!omap - CALVAL: access: rw description: Calibration counter max lsb: 0 reset_value: '' width: 17 - CALDIR: access: rw description: Calibration counter direction lsb: 17 reset_value: '' width: 1 - RTC_ASEC: fields: !!omap - SECONDS: access: rw description: Alarm seconds lsb: 0 reset_value: '' width: 6 - RTC_AMIN: fields: !!omap - MINUTES: access: rw description: Alarm minutes lsb: 0 reset_value: '' width: 6 - RTC_AHRS: fields: !!omap - HOURS: access: rw description: Alarm hours lsb: 0 reset_value: '' width: 5 - RTC_ADOM: fields: !!omap - DOM: access: rw description: Alarm day of month lsb: 0 reset_value: '' width: 5 - RTC_ADOW: fields: !!omap - DOW: access: rw description: Alarm day of week lsb: 0 reset_value: '' width: 3 - RTC_ADOY: fields: !!omap - DOY: access: rw description: Alarm day of year lsb: 0 reset_value: '' width: 9 - RTC_AMON: fields: !!omap - MONTH: access: rw description: Alarm month lsb: 0 reset_value: '' width: 4 - RTC_AYRS: fields: !!omap - YEAR: access: rw description: Alarm year lsb: 0 reset_value: '' width: 12 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/scu.csv000066400000000000000000001537131435536612600227170ustar00rootroot00000000000000SCU_SFSP0_0,0,3,MODE,Select pin function,0,rw SCU_SFSP0_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP0_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP0_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP0_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP0_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP0_1,0,3,MODE,Select pin function,0,rw SCU_SFSP0_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP0_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP0_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP0_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP0_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_0,0,3,MODE,Select pin function,0,rw SCU_SFSP1_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_1,0,3,MODE,Select pin function,0,rw SCU_SFSP1_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_2,0,3,MODE,Select pin function,0,rw SCU_SFSP1_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_3,0,3,MODE,Select pin function,0,rw SCU_SFSP1_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_4,0,3,MODE,Select pin function,0,rw SCU_SFSP1_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_5,0,3,MODE,Select pin function,0,rw SCU_SFSP1_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_6,0,3,MODE,Select pin function,0,rw SCU_SFSP1_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_7,0,3,MODE,Select pin function,0,rw SCU_SFSP1_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_8,0,3,MODE,Select pin function,0,rw SCU_SFSP1_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_9,0,3,MODE,Select pin function,0,rw SCU_SFSP1_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_10,0,3,MODE,Select pin function,0,rw SCU_SFSP1_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_11,0,3,MODE,Select pin function,0,rw SCU_SFSP1_11,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_11,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_11,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_11,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_11,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_12,0,3,MODE,Select pin function,0,rw SCU_SFSP1_12,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_12,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_12,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_12,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_12,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_13,0,3,MODE,Select pin function,0,rw SCU_SFSP1_13,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_13,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_13,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_13,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_13,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_14,0,3,MODE,Select pin function,0,rw SCU_SFSP1_14,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_14,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_14,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_14,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_14,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_15,0,3,MODE,Select pin function,0,rw SCU_SFSP1_15,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_15,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_15,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_15,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_15,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_16,0,3,MODE,Select pin function,0,rw SCU_SFSP1_16,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_16,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_16,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_16,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_16,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_18,0,3,MODE,Select pin function,0,rw SCU_SFSP1_18,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_18,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_18,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_18,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_18,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_19,0,3,MODE,Select pin function,0,rw SCU_SFSP1_19,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_19,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_19,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_19,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_19,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_20,0,3,MODE,Select pin function,0,rw SCU_SFSP1_20,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_20,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_20,5,1,EHS,Select Slew rate,0,rw SCU_SFSP1_20,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_20,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_0,0,3,MODE,Select pin function,0,rw SCU_SFSP2_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_1,0,3,MODE,Select pin function,0,rw SCU_SFSP2_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_2,0,3,MODE,Select pin function,0,rw SCU_SFSP2_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_6,0,3,MODE,Select pin function,0,rw SCU_SFSP2_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_7,0,3,MODE,Select pin function,0,rw SCU_SFSP2_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_8,0,3,MODE,Select pin function,0,rw SCU_SFSP2_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_9,0,3,MODE,Select pin function,0,rw SCU_SFSP2_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_10,0,3,MODE,Select pin function,0,rw SCU_SFSP2_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_11,0,3,MODE,Select pin function,0,rw SCU_SFSP2_11,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_11,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_11,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_11,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_11,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_12,0,3,MODE,Select pin function,0,rw SCU_SFSP2_12,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_12,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_12,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_12,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_12,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_13,0,3,MODE,Select pin function,0,rw SCU_SFSP2_13,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_13,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_13,5,1,EHS,Select Slew rate,0,rw SCU_SFSP2_13,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_13,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_0,0,3,MODE,Select pin function,0,rw SCU_SFSP3_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_1,0,3,MODE,Select pin function,0,rw SCU_SFSP3_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_2,0,3,MODE,Select pin function,0,rw SCU_SFSP3_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_4,0,3,MODE,Select pin function,0,rw SCU_SFSP3_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_5,0,3,MODE,Select pin function,0,rw SCU_SFSP3_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_6,0,3,MODE,Select pin function,0,rw SCU_SFSP3_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_7,0,3,MODE,Select pin function,0,rw SCU_SFSP3_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP3_8,0,3,MODE,Select pin function,0,rw SCU_SFSP3_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_0,0,3,MODE,Select pin function,0,rw SCU_SFSP4_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_1,0,3,MODE,Select pin function,0,rw SCU_SFSP4_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_2,0,3,MODE,Select pin function,0,rw SCU_SFSP4_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_3,0,3,MODE,Select pin function,0,rw SCU_SFSP4_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_4,0,3,MODE,Select pin function,0,rw SCU_SFSP4_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_5,0,3,MODE,Select pin function,0,rw SCU_SFSP4_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_6,0,3,MODE,Select pin function,0,rw SCU_SFSP4_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_7,0,3,MODE,Select pin function,0,rw SCU_SFSP4_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_8,0,3,MODE,Select pin function,0,rw SCU_SFSP4_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_9,0,3,MODE,Select pin function,0,rw SCU_SFSP4_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP4_10,0,3,MODE,Select pin function,0,rw SCU_SFSP4_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP4_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP4_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSP4_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSP4_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_0,0,3,MODE,Select pin function,0,rw SCU_SFSP5_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_1,0,3,MODE,Select pin function,0,rw SCU_SFSP5_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_2,0,3,MODE,Select pin function,0,rw SCU_SFSP5_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_3,0,3,MODE,Select pin function,0,rw SCU_SFSP5_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_4,0,3,MODE,Select pin function,0,rw SCU_SFSP5_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_5,0,3,MODE,Select pin function,0,rw SCU_SFSP5_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_6,0,3,MODE,Select pin function,0,rw SCU_SFSP5_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP5_7,0,3,MODE,Select pin function,0,rw SCU_SFSP5_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP5_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP5_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP5_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP5_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_0,0,3,MODE,Select pin function,0,rw SCU_SFSP6_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_1,0,3,MODE,Select pin function,0,rw SCU_SFSP6_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_2,0,3,MODE,Select pin function,0,rw SCU_SFSP6_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_3,0,3,MODE,Select pin function,0,rw SCU_SFSP6_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_4,0,3,MODE,Select pin function,0,rw SCU_SFSP6_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_5,0,3,MODE,Select pin function,0,rw SCU_SFSP6_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_6,0,3,MODE,Select pin function,0,rw SCU_SFSP6_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_7,0,3,MODE,Select pin function,0,rw SCU_SFSP6_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_8,0,3,MODE,Select pin function,0,rw SCU_SFSP6_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_9,0,3,MODE,Select pin function,0,rw SCU_SFSP6_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_10,0,3,MODE,Select pin function,0,rw SCU_SFSP6_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_11,0,3,MODE,Select pin function,0,rw SCU_SFSP6_11,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_11,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_11,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_11,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_11,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP6_12,0,3,MODE,Select pin function,0,rw SCU_SFSP6_12,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP6_12,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP6_12,5,1,EHS,Select Slew rate,0,rw SCU_SFSP6_12,6,1,EZI,Input buffer enable,0,rw SCU_SFSP6_12,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_0,0,3,MODE,Select pin function,0,rw SCU_SFSP7_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_1,0,3,MODE,Select pin function,0,rw SCU_SFSP7_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_2,0,3,MODE,Select pin function,0,rw SCU_SFSP7_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_3,0,3,MODE,Select pin function,0,rw SCU_SFSP7_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_4,0,3,MODE,Select pin function,0,rw SCU_SFSP7_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_5,0,3,MODE,Select pin function,0,rw SCU_SFSP7_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_6,0,3,MODE,Select pin function,0,rw SCU_SFSP7_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP7_7,0,3,MODE,Select pin function,0,rw SCU_SFSP7_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP7_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP7_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP7_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP7_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_3,0,3,MODE,Select pin function,0,rw SCU_SFSP8_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP8_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_4,0,3,MODE,Select pin function,0,rw SCU_SFSP8_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP8_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_5,0,3,MODE,Select pin function,0,rw SCU_SFSP8_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP8_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_6,0,3,MODE,Select pin function,0,rw SCU_SFSP8_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP8_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_7,0,3,MODE,Select pin function,0,rw SCU_SFSP8_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSP8_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_8,0,3,MODE,Select pin function,0,rw SCU_SFSP8_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSP8_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP9_0,0,3,MODE,Select pin function,0,rw SCU_SFSP9_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP9_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP9_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSP9_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP9_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP9_1,0,3,MODE,Select pin function,0,rw SCU_SFSP9_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP9_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP9_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSP9_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP9_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP9_2,0,3,MODE,Select pin function,0,rw SCU_SFSP9_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP9_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP9_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSP9_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP9_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP9_3,0,3,MODE,Select pin function,0,rw SCU_SFSP9_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP9_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP9_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP9_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP9_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP9_4,0,3,MODE,Select pin function,0,rw SCU_SFSP9_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP9_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP9_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSP9_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP9_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP9_5,0,3,MODE,Select pin function,0,rw SCU_SFSP9_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP9_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP9_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSP9_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP9_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP9_6,0,3,MODE,Select pin function,0,rw SCU_SFSP9_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP9_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP9_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSP9_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSP9_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPA_0,0,3,MODE,Select pin function,0,rw SCU_SFSPA_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPA_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPA_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSPA_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSPA_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPA_4,0,3,MODE,Select pin function,0,rw SCU_SFSPA_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPA_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPA_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSPA_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSPA_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPB_0,0,3,MODE,Select pin function,0,rw SCU_SFSPB_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPB_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPB_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSPB_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSPB_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPB_1,0,3,MODE,Select pin function,0,rw SCU_SFSPB_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPB_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPB_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSPB_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSPB_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPB_2,0,3,MODE,Select pin function,0,rw SCU_SFSPB_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPB_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPB_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSPB_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSPB_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPB_3,0,3,MODE,Select pin function,0,rw SCU_SFSPB_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPB_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPB_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSPB_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSPB_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPB_4,0,3,MODE,Select pin function,0,rw SCU_SFSPB_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPB_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPB_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSPB_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSPB_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPB_5,0,3,MODE,Select pin function,0,rw SCU_SFSPB_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPB_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPB_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSPB_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSPB_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPB_6,0,3,MODE,Select pin function,0,rw SCU_SFSPB_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPB_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPB_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSPB_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSPB_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_0,0,3,MODE,Select pin function,0,rw SCU_SFSPC_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_1,0,3,MODE,Select pin function,0,rw SCU_SFSPC_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_2,0,3,MODE,Select pin function,0,rw SCU_SFSPC_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_3,0,3,MODE,Select pin function,0,rw SCU_SFSPC_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_4,0,3,MODE,Select pin function,0,rw SCU_SFSPC_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_5,0,3,MODE,Select pin function,0,rw SCU_SFSPC_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_6,0,3,MODE,Select pin function,0,rw SCU_SFSPC_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_7,0,3,MODE,Select pin function,0,rw SCU_SFSPC_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_8,0,3,MODE,Select pin function,0,rw SCU_SFSPC_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_9,0,3,MODE,Select pin function,0,rw SCU_SFSPC_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_10,0,3,MODE,Select pin function,0,rw SCU_SFSPC_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_11,0,3,MODE,Select pin function,0,rw SCU_SFSPC_11,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_11,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_11,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_11,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_11,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_12,0,3,MODE,Select pin function,0,rw SCU_SFSPC_12,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_12,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_12,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_12,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_12,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_13,0,3,MODE,Select pin function,0,rw SCU_SFSPC_13,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_13,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_13,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_13,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_13,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPC_14,0,3,MODE,Select pin function,0,rw SCU_SFSPC_14,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPC_14,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPC_14,5,1,EHS,Select Slew rate,0,rw SCU_SFSPC_14,6,1,EZI,Input buffer enable,0,rw SCU_SFSPC_14,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_0,0,3,MODE,Select pin function,0,rw SCU_SFSPD_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_1,0,3,MODE,Select pin function,0,rw SCU_SFSPD_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_2,0,3,MODE,Select pin function,0,rw SCU_SFSPD_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_3,0,3,MODE,Select pin function,0,rw SCU_SFSPD_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_4,0,3,MODE,Select pin function,0,rw SCU_SFSPD_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_5,0,3,MODE,Select pin function,0,rw SCU_SFSPD_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_6,0,3,MODE,Select pin function,0,rw SCU_SFSPD_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_7,0,3,MODE,Select pin function,0,rw SCU_SFSPD_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_8,0,3,MODE,Select pin function,0,rw SCU_SFSPD_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_9,0,3,MODE,Select pin function,0,rw SCU_SFSPD_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_10,0,3,MODE,Select pin function,0,rw SCU_SFSPD_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_11,0,3,MODE,Select pin function,0,rw SCU_SFSPD_11,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_11,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_11,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_11,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_11,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_12,0,3,MODE,Select pin function,0,rw SCU_SFSPD_12,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_12,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_12,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_12,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_12,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_13,0,3,MODE,Select pin function,0,rw SCU_SFSPD_13,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_13,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_13,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_13,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_13,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_14,0,3,MODE,Select pin function,0,rw SCU_SFSPD_14,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_14,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_14,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_14,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_14,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_15,0,3,MODE,Select pin function,0,rw SCU_SFSPD_15,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_15,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_15,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_15,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_15,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPD_16,0,3,MODE,Select pin function,0,rw SCU_SFSPD_16,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPD_16,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPD_16,5,1,EHS,Select Slew rate,0,rw SCU_SFSPD_16,6,1,EZI,Input buffer enable,0,rw SCU_SFSPD_16,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_0,0,3,MODE,Select pin function,0,rw SCU_SFSPE_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_1,0,3,MODE,Select pin function,0,rw SCU_SFSPE_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_2,0,3,MODE,Select pin function,0,rw SCU_SFSPE_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_3,0,3,MODE,Select pin function,0,rw SCU_SFSPE_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_4,0,3,MODE,Select pin function,0,rw SCU_SFSPE_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_5,0,3,MODE,Select pin function,0,rw SCU_SFSPE_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_6,0,3,MODE,Select pin function,0,rw SCU_SFSPE_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_7,0,3,MODE,Select pin function,0,rw SCU_SFSPE_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_8,0,3,MODE,Select pin function,0,rw SCU_SFSPE_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_9,0,3,MODE,Select pin function,0,rw SCU_SFSPE_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_10,0,3,MODE,Select pin function,0,rw SCU_SFSPE_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_11,0,3,MODE,Select pin function,0,rw SCU_SFSPE_11,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_11,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_11,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_11,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_11,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_12,0,3,MODE,Select pin function,0,rw SCU_SFSPE_12,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_12,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_12,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_12,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_12,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_13,0,3,MODE,Select pin function,0,rw SCU_SFSPE_13,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_13,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_13,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_13,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_13,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_14,0,3,MODE,Select pin function,0,rw SCU_SFSPE_14,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_14,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_14,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_14,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_14,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPE_15,0,3,MODE,Select pin function,0,rw SCU_SFSPE_15,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPE_15,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPE_15,5,1,EHS,Select Slew rate,0,rw SCU_SFSPE_15,6,1,EZI,Input buffer enable,0,rw SCU_SFSPE_15,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_0,0,3,MODE,Select pin function,0,rw SCU_SFSPF_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_0,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_1,0,3,MODE,Select pin function,0,rw SCU_SFSPF_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_1,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_2,0,3,MODE,Select pin function,0,rw SCU_SFSPF_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_2,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_3,0,3,MODE,Select pin function,0,rw SCU_SFSPF_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_4,0,3,MODE,Select pin function,0,rw SCU_SFSPF_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_4,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_5,0,3,MODE,Select pin function,0,rw SCU_SFSPF_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_5,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_6,0,3,MODE,Select pin function,0,rw SCU_SFSPF_6,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_6,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_6,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_6,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_6,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_7,0,3,MODE,Select pin function,0,rw SCU_SFSPF_7,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_7,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_7,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_7,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_7,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_8,0,3,MODE,Select pin function,0,rw SCU_SFSPF_8,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_8,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_8,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_8,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_8,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_9,0,3,MODE,Select pin function,0,rw SCU_SFSPF_9,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_9,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_9,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_9,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_9,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_10,0,3,MODE,Select pin function,0,rw SCU_SFSPF_10,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_10,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_10,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_10,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_10,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPF_11,0,3,MODE,Select pin function,0,rw SCU_SFSPF_11,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPF_11,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPF_11,5,1,EHS,Select Slew rate,0,rw SCU_SFSPF_11,6,1,EZI,Input buffer enable,0,rw SCU_SFSPF_11,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_17,0,3,MODE,Select pin function,0,rw SCU_SFSP1_17,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP1_17,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP1_17,6,1,EZI,Input buffer enable,0,rw SCU_SFSP1_17,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP1_17,8,2,EHD,Select drive strength,0,rw SCU_SFSP2_3,0,3,MODE,Select pin function,0,rw SCU_SFSP2_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_3,8,2,EHD,Select drive strength,0,rw SCU_SFSP2_4,0,3,MODE,Select pin function,0,rw SCU_SFSP2_4,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_4,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_4,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_4,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_4,8,2,EHD,Select drive strength,0,rw SCU_SFSP2_5,0,3,MODE,Select pin function,0,rw SCU_SFSP2_5,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP2_5,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP2_5,6,1,EZI,Input buffer enable,0,rw SCU_SFSP2_5,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP2_5,8,2,EHD,Select drive strength,0,rw SCU_SFSP8_0,0,3,MODE,Select pin function,0,rw SCU_SFSP8_0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_0,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_0,8,2,EHD,Select drive strength,0,rw SCU_SFSP8_1,0,3,MODE,Select pin function,0,rw SCU_SFSP8_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_1,8,2,EHD,Select drive strength,0,rw SCU_SFSP8_2,0,3,MODE,Select pin function,0,rw SCU_SFSP8_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP8_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP8_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSP8_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSP8_2,8,2,EHD,Select drive strength,0,rw SCU_SFSPA_1,0,3,MODE,Select pin function,0,rw SCU_SFSPA_1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPA_1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPA_1,6,1,EZI,Input buffer enable,0,rw SCU_SFSPA_1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPA_1,8,2,EHD,Select drive strength,0,rw SCU_SFSPA_2,0,3,MODE,Select pin function,0,rw SCU_SFSPA_2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPA_2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPA_2,6,1,EZI,Input buffer enable,0,rw SCU_SFSPA_2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPA_2,8,2,EHD,Select drive strength,0,rw SCU_SFSPA_3,0,3,MODE,Select pin function,0,rw SCU_SFSPA_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSPA_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSPA_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSPA_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSPA_3,8,2,EHD,Select drive strength,0,rw SCU_SFSP3_3,0,3,MODE,Select pin function,0,rw SCU_SFSP3_3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSP3_3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSP3_3,5,1,EHS,Select Slew rate,0,rw SCU_SFSP3_3,6,1,EZI,Input buffer enable,0,rw SCU_SFSP3_3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSCLK0,0,3,MODE,Select pin function,0,rw SCU_SFSCLK0,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSCLK0,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSCLK0,5,1,EHS,Select Slew rate,0,rw SCU_SFSCLK0,6,1,EZI,Input buffer enable,0,rw SCU_SFSCLK0,7,1,ZIF,Input glitch filter,0,rw SCU_SFSCLK1,0,3,MODE,Select pin function,0,rw SCU_SFSCLK1,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSCLK1,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSCLK1,5,1,EHS,Select Slew rate,0,rw SCU_SFSCLK1,6,1,EZI,Input buffer enable,0,rw SCU_SFSCLK1,7,1,ZIF,Input glitch filter,0,rw SCU_SFSCLK2,0,3,MODE,Select pin function,0,rw SCU_SFSCLK2,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSCLK2,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSCLK2,5,1,EHS,Select Slew rate,0,rw SCU_SFSCLK2,6,1,EZI,Input buffer enable,0,rw SCU_SFSCLK2,7,1,ZIF,Input glitch filter,0,rw SCU_SFSCLK3,0,3,MODE,Select pin function,0,rw SCU_SFSCLK3,3,1,EPD,Enable pull-down resistor at pad,0,rw SCU_SFSCLK3,4,1,EPUN,Disable pull-up resistor at pad,0,rw SCU_SFSCLK3,5,1,EHS,Select Slew rate,0,rw SCU_SFSCLK3,6,1,EZI,Input buffer enable,0,rw SCU_SFSCLK3,7,1,ZIF,Input glitch filter,0,rw SCU_SFSUSB,0,1,USB_AIM,Differential data input AIP/AIM,0,rw SCU_SFSUSB,1,1,USB_ESEA,Control signal for differential input or single input,1,rw SCU_SFSUSB,2,1,USB_EPD,Enable pull-down connect,0,rw SCU_SFSUSB,4,1,USB_EPWR,Power mode,0,rw SCU_SFSUSB,5,1,USB_VBUS,Enable the vbus_valid signal,0,rw SCU_SFSI2C0,0,1,SCL_EFP,Select input glitch filter time constant for the SCL pin,0,rw SCU_SFSI2C0,2,1,SCL_EHD,Select I2C mode for the SCL pin,0,rw SCU_SFSI2C0,3,1,SCL_EZI,Enable the input receiver for the SCL pin,0,rw SCU_SFSI2C0,7,1,SCL_ZIF,Enable or disable input glitch filter for the SCL pin,0,rw SCU_SFSI2C0,8,1,SDA_EFP,Select input glitch filter time constant for the SDA pin,0,rw SCU_SFSI2C0,10,1,SDA_EHD,Select I2C mode for the SDA pin,0,rw SCU_SFSI2C0,11,1,SDA_EZI,Enable the input receiver for the SDA pin,0,rw SCU_SFSI2C0,15,1,SDA_ZIF,Enable or disable input glitch filter for the SDA pin,0,rw SCU_ENAIO0,0,1,ADC0_0,Select ADC0_0,0,rw SCU_ENAIO0,1,1,ADC0_1,Select ADC0_1,0,rw SCU_ENAIO0,2,1,ADC0_2,Select ADC0_2,0,rw SCU_ENAIO0,3,1,ADC0_3,Select ADC0_3,0,rw SCU_ENAIO0,4,1,ADC0_4,Select ADC0_4,0,rw SCU_ENAIO0,5,1,ADC0_5,Select ADC0_5,0,rw SCU_ENAIO0,6,1,ADC0_6,Select ADC0_6,0,rw SCU_ENAIO1,0,1,ADC1_0,Select ADC1_0,0,rw SCU_ENAIO1,1,1,ADC1_1,Select ADC1_1,0,rw SCU_ENAIO1,2,1,ADC1_2,Select ADC1_2,0,rw SCU_ENAIO1,3,1,ADC1_3,Select ADC1_3,0,rw SCU_ENAIO1,4,1,ADC1_4,Select ADC1_4,0,rw SCU_ENAIO1,5,1,ADC1_5,Select ADC1_5,0,rw SCU_ENAIO1,6,1,ADC1_6,Select ADC1_6,0,rw SCU_ENAIO1,7,1,ADC1_7,Select ADC1_7,0,rw SCU_ENAIO2,0,1,DAC,Select DAC,0,rw SCU_ENAIO2,4,1,BG,Select band gap output,0,rw SCU_EMCDELAYCLK,0,16,CLK_DELAY,EMC_CLKn SDRAM clock output delay,0,rw SCU_PINTSEL0,0,5,INTPIN0,pin number for interrupt 0 source,0, SCU_PINTSEL0,5,3,PORTSEL0,port for interrupt 0 source,0, SCU_PINTSEL0,8,5,INTPIN1,pin number for interrupt 1 source,0, SCU_PINTSEL0,13,3,PORTSEL1,port for interrupt 1 source,0, SCU_PINTSEL0,16,5,INTPIN2,pin number for interrupt 2 source,0, SCU_PINTSEL0,21,3,PORTSEL2,port for interrupt 2 source,0, SCU_PINTSEL0,24,5,INTPIN3,pin number for interrupt 3 source,0, SCU_PINTSEL0,29,3,PORTSEL3,port for interrupt 3 source,0, SCU_PINTSEL1,0,5,INTPIN4,pin number for interrupt 4 source,0, SCU_PINTSEL1,5,3,PORTSEL4,port for interrupt 4 source,0, SCU_PINTSEL1,8,5,INTPIN5,pin number for interrupt 5 source,0, SCU_PINTSEL1,13,3,PORTSEL5,port for interrupt 5 source,0, SCU_PINTSEL1,16,5,INTPIN6,pin number for interrupt 6 source,0, SCU_PINTSEL1,21,3,PORTSEL6,port for interrupt 6 source,0, SCU_PINTSEL1,24,5,INTPIN7,pin number for interrupt 7 source,0, SCU_PINTSEL1,29,3,PORTSEL7,port for interrupt 7 source,0, hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/scu.yaml000066400000000000000000004545501435536612600230710ustar00rootroot00000000000000!!omap - SCU_SFSP0_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP0_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_11: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_12: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_13: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_14: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_15: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_16: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_18: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_19: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_20: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_11: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_12: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP2_13: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP3_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP4_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP5_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_11: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP6_12: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP7_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP8_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP8_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP8_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP8_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP8_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP8_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP9_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP9_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP9_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP9_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP9_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP9_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP9_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPA_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPA_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPB_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPB_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPB_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPB_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPB_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPB_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPB_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_11: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_12: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_13: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPC_14: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_11: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_12: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_13: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_14: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_15: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPD_16: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_11: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_12: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_13: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_14: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPE_15: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_6: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_7: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_8: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_9: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_10: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSPF_11: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSP1_17: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSP2_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSP2_4: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSP2_5: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSP8_0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSP8_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSP8_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSPA_1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSPA_2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSPA_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - EHD: access: rw description: Select drive strength lsb: 8 reset_value: '0' width: 2 - SCU_SFSP3_3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSCLK0: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSCLK1: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSCLK2: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSCLK3: fields: !!omap - MODE: access: rw description: Select pin function lsb: 0 reset_value: '0' width: 3 - EPD: access: rw description: Enable pull-down resistor at pad lsb: 3 reset_value: '0' width: 1 - EPUN: access: rw description: Disable pull-up resistor at pad lsb: 4 reset_value: '0' width: 1 - EHS: access: rw description: Select Slew rate lsb: 5 reset_value: '0' width: 1 - EZI: access: rw description: Input buffer enable lsb: 6 reset_value: '0' width: 1 - ZIF: access: rw description: Input glitch filter lsb: 7 reset_value: '0' width: 1 - SCU_SFSUSB: fields: !!omap - USB_AIM: access: rw description: Differential data input AIP/AIM lsb: 0 reset_value: '0' width: 1 - USB_ESEA: access: rw description: Control signal for differential input or single input lsb: 1 reset_value: '1' width: 1 - USB_EPD: access: rw description: Enable pull-down connect lsb: 2 reset_value: '0' width: 1 - USB_EPWR: access: rw description: Power mode lsb: 4 reset_value: '0' width: 1 - USB_VBUS: access: rw description: Enable the vbus_valid signal lsb: 5 reset_value: '0' width: 1 - SCU_SFSI2C0: fields: !!omap - SCL_EFP: access: rw description: Select input glitch filter time constant for the SCL pin lsb: 0 reset_value: '0' width: 1 - SCL_EHD: access: rw description: Select I2C mode for the SCL pin lsb: 2 reset_value: '0' width: 1 - SCL_EZI: access: rw description: Enable the input receiver for the SCL pin lsb: 3 reset_value: '0' width: 1 - SCL_ZIF: access: rw description: Enable or disable input glitch filter for the SCL pin lsb: 7 reset_value: '0' width: 1 - SDA_EFP: access: rw description: Select input glitch filter time constant for the SDA pin lsb: 8 reset_value: '0' width: 1 - SDA_EHD: access: rw description: Select I2C mode for the SDA pin lsb: 10 reset_value: '0' width: 1 - SDA_EZI: access: rw description: Enable the input receiver for the SDA pin lsb: 11 reset_value: '0' width: 1 - SDA_ZIF: access: rw description: Enable or disable input glitch filter for the SDA pin lsb: 15 reset_value: '0' width: 1 - SCU_ENAIO0: fields: !!omap - ADC0_0: access: rw description: Select ADC0_0 lsb: 0 reset_value: '0' width: 1 - ADC0_1: access: rw description: Select ADC0_1 lsb: 1 reset_value: '0' width: 1 - ADC0_2: access: rw description: Select ADC0_2 lsb: 2 reset_value: '0' width: 1 - ADC0_3: access: rw description: Select ADC0_3 lsb: 3 reset_value: '0' width: 1 - ADC0_4: access: rw description: Select ADC0_4 lsb: 4 reset_value: '0' width: 1 - ADC0_5: access: rw description: Select ADC0_5 lsb: 5 reset_value: '0' width: 1 - ADC0_6: access: rw description: Select ADC0_6 lsb: 6 reset_value: '0' width: 1 - SCU_ENAIO1: fields: !!omap - ADC1_0: access: rw description: Select ADC1_0 lsb: 0 reset_value: '0' width: 1 - ADC1_1: access: rw description: Select ADC1_1 lsb: 1 reset_value: '0' width: 1 - ADC1_2: access: rw description: Select ADC1_2 lsb: 2 reset_value: '0' width: 1 - ADC1_3: access: rw description: Select ADC1_3 lsb: 3 reset_value: '0' width: 1 - ADC1_4: access: rw description: Select ADC1_4 lsb: 4 reset_value: '0' width: 1 - ADC1_5: access: rw description: Select ADC1_5 lsb: 5 reset_value: '0' width: 1 - ADC1_6: access: rw description: Select ADC1_6 lsb: 6 reset_value: '0' width: 1 - ADC1_7: access: rw description: Select ADC1_7 lsb: 7 reset_value: '0' width: 1 - SCU_ENAIO2: fields: !!omap - DAC: access: rw description: Select DAC lsb: 0 reset_value: '0' width: 1 - BG: access: rw description: Select band gap output lsb: 4 reset_value: '0' width: 1 - SCU_EMCDELAYCLK: fields: !!omap - CLK_DELAY: access: rw description: EMC_CLKn SDRAM clock output delay lsb: 0 reset_value: '0' width: 16 - SCU_PINTSEL0: fields: !!omap - INTPIN0: access: '' description: pin number for interrupt 0 source lsb: 0 reset_value: '0' width: 5 - PORTSEL0: access: '' description: port for interrupt 0 source lsb: 5 reset_value: '0' width: 3 - INTPIN1: access: '' description: pin number for interrupt 1 source lsb: 8 reset_value: '0' width: 5 - PORTSEL1: access: '' description: port for interrupt 1 source lsb: 13 reset_value: '0' width: 3 - INTPIN2: access: '' description: pin number for interrupt 2 source lsb: 16 reset_value: '0' width: 5 - PORTSEL2: access: '' description: port for interrupt 2 source lsb: 21 reset_value: '0' width: 3 - INTPIN3: access: '' description: pin number for interrupt 3 source lsb: 24 reset_value: '0' width: 5 - PORTSEL3: access: '' description: port for interrupt 3 source lsb: 29 reset_value: '0' width: 3 - SCU_PINTSEL1: fields: !!omap - INTPIN4: access: '' description: pin number for interrupt 4 source lsb: 0 reset_value: '0' width: 5 - PORTSEL4: access: '' description: port for interrupt 4 source lsb: 5 reset_value: '0' width: 3 - INTPIN5: access: '' description: pin number for interrupt 5 source lsb: 8 reset_value: '0' width: 5 - PORTSEL5: access: '' description: port for interrupt 5 source lsb: 13 reset_value: '0' width: 3 - INTPIN6: access: '' description: pin number for interrupt 6 source lsb: 16 reset_value: '0' width: 5 - PORTSEL6: access: '' description: port for interrupt 6 source lsb: 21 reset_value: '0' width: 3 - INTPIN7: access: '' description: pin number for interrupt 7 source lsb: 24 reset_value: '0' width: 5 - PORTSEL7: access: '' description: port for interrupt 7 source lsb: 29 reset_value: '0' width: 3 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/sdio.csv000066400000000000000000000201221435536612600230460ustar00rootroot00000000000000SDIO_CTRL,0,1,CONTROLLER_RESET,Controller reset,0,rw SDIO_CTRL,1,1,FIFO_RESET,FIFO reset,0,rw SDIO_CTRL,2,1,DMA_RESET,DMA reset,0,rw SDIO_CTRL,4,1,INT_ENABLE,Global interrupt enable/disable,0,rw SDIO_CTRL,6,1,READ_WAIT,Read/wait send,0,rw SDIO_CTRL,7,1,SEND_IRQ_RESPONSE,Send IRQ response,0,rw SDIO_CTRL,8,1,ABORT_READ_DATA,Abort read data,0,rw SDIO_CTRL,9,1,SEND_CCSD,Send CCSD,0,rw SDIO_CTRL,10,1,SEND_AUTO_STOP_CCSD,Send auto stop CCSD,0,rw SDIO_CTRL,11,1,CEATA_DEVICE_INTERRUPT_STATUS,CEATA device interrupt status,0,rw SDIO_CTRL,16,1,CARD_VOLTAGE_A0,SD_VOLT0 pin control,0,rw SDIO_CTRL,17,1,CARD_VOLTAGE_A1,SD_VOLT1 pin control,0,rw SDIO_CTRL,18,1,CARD_VOLTAGE_A2,SD_VOLT2 pin control,0,rw SDIO_CTRL,25,1,USE_INTERNAL_DMAC,SD/MMC DMA use,0,rw SDIO_PWREN,0,1,POWER_ENABLE,Power on/off switch for card,0,rw SDIO_CLKDIV,0,8,CLK_DIVIDER0,Clock divider-0 value,0,rw SDIO_CLKDIV,8,8,CLK_DIVIDER1,Clock divider-1 value,0,rw SDIO_CLKDIV,16,8,CLK_DIVIDER2,Clock divider-2 value,0,rw SDIO_CLKDIV,24,8,CLK_DIVIDER3,Clock divider-3 value,0,rw SDIO_CLKSRC,0,2,CLK_SOURCE,Clock divider source for SD card,0,rw SDIO_CLKENA,0,1,CCLK_ENABLE,Clock-enable control for SD card clock,0,rw SDIO_CLKENA,16,1,CCLK_LOW_POWER,Low-power control for SD card clock,0,rw SDIO_TMOUT,0,8,RESPONSE_TIMEOUT,Response time-out value,0x40,rw SDIO_TMOUT,8,24,DATA_TIMEOUT,Value for card data read time-out,0xffffff,rw SDIO_CTYPE,0,1,CARD_WIDTH0,Indicates if card is 1-bit or 4-bit,0,rw SDIO_CTYPE,16,1,CARD_WIDTH1,Indicates if card is 8-bit,0,rw SDIO_BLKSIZ,0,16,BLOCK_SIZE,Block size,0x200,rw SDIO_BYTCNT,0,32,BYTE_COUNT,Number of bytes to be transferred,0x200,rw SDIO_INTMASK,0,1,CDET,Card detect,0,rw SDIO_INTMASK,1,1,RE,Response error,0,rw SDIO_INTMASK,2,1,CDONE,Command done,0,rw SDIO_INTMASK,3,1,DTO,Data transfer over,0,rw SDIO_INTMASK,4,1,TXDR,Transmit FIFO data request,0,rw SDIO_INTMASK,5,1,RXDR,Receive FIFO data request,0,rw SDIO_INTMASK,6,1,RCRC,Response CRC error,0,rw SDIO_INTMASK,7,1,DCRC,Data CRC error,0,rw SDIO_INTMASK,8,1,RTO,Response time-out,0,rw SDIO_INTMASK,9,1,DRTO,Data read time-out,0,rw SDIO_INTMASK,10,1,HTO,Data starvation-by-host time-out/volt_switch_int,0,rw SDIO_INTMASK,11,1,FRUN,FIFO underrun/overrun error,0,rw SDIO_INTMASK,12,1,HLE,Hardware locked write error,0,rw SDIO_INTMASK,13,1,SBE,Start-bit error,0,rw SDIO_INTMASK,14,1,ACD,Auto command done,0,rw SDIO_INTMASK,15,1,EBE,End-bit error (read)/Write no CRC,0,rw SDIO_INTMASK,16,1,SDIO_INT_MASK,Mask SDIO interrupt,0,rw SDIO_CMDARG,0,32,CMD_ARG,Value indicates command argument to be passed to card,0,rw SDIO_CMD,0,6,CMD_INDEX,Command index,0,rw SDIO_CMD,6,1,RESPONSE_EXPECT,Response expect,0,rw SDIO_CMD,7,1,RESPONSE_LENGTH,Response length,0,rw SDIO_CMD,8,1,CHECK_RESPONSE_CRC,Check response CRC,0,rw SDIO_CMD,9,1,DATA_EXPECTED,Data expected,0,rw SDIO_CMD,10,1,READ_WRITE,Read/write,0,rw SDIO_CMD,11,1,TRANSFER_MODE,Transfer mode,0,rw SDIO_CMD,12,1,SEND_AUTO_STOP,Send auto stop,0,rw SDIO_CMD,13,1,WAIT_PRVDATA_COMPLETE,Wait prvdata complete,0,rw SDIO_CMD,14,1,STOP_ABORT_CMD,Stop abort command,0,rw SDIO_CMD,15,1,SEND_INITIALIZATION,Send initialization,0,rw SDIO_CMD,21,1,UPDATE_CLOCK_REGISTERS_ONLY,Update clock registers only,0,rw SDIO_CMD,22,1,READ_CEATA_DEVICE,Read CEATA device,0,rw SDIO_CMD,23,1,CCS_EXPECTED,CCS expected,0,rw SDIO_CMD,24,1,ENABLE_BOOT,Enable boot,0,rw SDIO_CMD,25,1,EXPECT_BOOT_ACK,Expect boot acknowledge,0,rw SDIO_CMD,26,1,DISABLE_BOOT,Disable boot,0,rw SDIO_CMD,27,1,BOOT_MODE,Boot mode,0,rw SDIO_CMD,28,1,VOLT_SWITCH,Voltage switch bit,0,rw SDIO_CMD,31,1,START_CMD,Start command,0,rw SDIO_RESP0,0,32,RESPONSE0,Bit[31:0] of response,0,rw SDIO_RESP1,0,32,RESPONSE1,Bit[63:32] of long response,0,rw SDIO_RESP2,0,32,RESPONSE2,Bit[95:64] of long response,0,rw SDIO_RESP3,0,32,RESPONSE3,Bit[127:96] of long response,0,rw SDIO_MINTSTS,0,1,CDET,Card detect,0,rw SDIO_MINTSTS,1,1,RE,Response error,0,rw SDIO_MINTSTS,2,1,CDONE,Command done,0,rw SDIO_MINTSTS,3,1,DTO,Data transfer over,0,rw SDIO_MINTSTS,4,1,TXDR,Transmit FIFO data request,0,rw SDIO_MINTSTS,5,1,RXDR,Receive FIFO data request,0,rw SDIO_MINTSTS,6,1,RCRC,Response CRC error,0,rw SDIO_MINTSTS,7,1,DCRC,Data CRC error,0,rw SDIO_MINTSTS,8,1,RTO,Response time-out,0,rw SDIO_MINTSTS,9,1,DRTO,Data read time-out,0,rw SDIO_MINTSTS,10,1,HTO,Data starvation-by-host time-out,0,rw SDIO_MINTSTS,11,1,FRUN,FIFO underrun/overrun error,0,rw SDIO_MINTSTS,12,1,HLE,Hardware locked write error,0,rw SDIO_MINTSTS,13,1,SBE,Start-bit error,0,rw SDIO_MINTSTS,14,1,ACD,Auto command done,0,rw SDIO_MINTSTS,15,1,EBE,End-bit error (read)/write no CRC,0,rw SDIO_MINTSTS,16,1,SDIO_INTERRUPT,Interrupt from SDIO card,0,rw SDIO_RINTSTS,0,1,CDET,Card detect,0,rw SDIO_RINTSTS,1,1,RE,Response error,0,rw SDIO_RINTSTS,2,1,CDONE,Command done,0,rw SDIO_RINTSTS,3,1,DTO,Data transfer over,0,rw SDIO_RINTSTS,4,1,TXDR,Transmit FIFO data request,0,rw SDIO_RINTSTS,5,1,RXDR,Receive FIFO data request,0,rw SDIO_RINTSTS,6,1,RCRC,Response CRC error,0,rw SDIO_RINTSTS,7,1,DCRC,Data CRC error,0,rw SDIO_RINTSTS,8,1,RTO_BAR,Response time-out (RTO)/boot ack received (BAR),0,rw SDIO_RINTSTS,9,1,DRTO_BDS,Data read time-out (DRTO)/boot data start (BDS),0,rw SDIO_RINTSTS,10,1,HTO,Data starvation-by-host time-out,0,rw SDIO_RINTSTS,11,1,FRUN,FIFO underrun/overrun error,0,rw SDIO_RINTSTS,12,1,HLE,Hardware locked write error,0,rw SDIO_RINTSTS,13,1,SBE,Start-bit error,0,rw SDIO_RINTSTS,14,1,ACD,Auto command done,0,rw SDIO_RINTSTS,15,1,EBE,End-bit error (read)/write no CRC,0,rw SDIO_RINTSTS,16,1,SDIO_INTERRUPT,Interrupt from SDIO card,0,rw SDIO_STATUS,0,1,FIFO_RX_WATERMARK,FIFO reached receive watermark level,0,rw SDIO_STATUS,1,1,FIFO_TX_WATERMARK,FIFO reached transmit watermark level,1,rw SDIO_STATUS,2,1,FIFO_EMPTY,FIFO is empty,1,rw SDIO_STATUS,3,1,FIFO_FULL,FIFO is full,0,rw SDIO_STATUS,4,4,CMDFSMSTATES,Command FSM states,0,rw SDIO_STATUS,8,1,DATA_3_STATUS,Raw selected card_data[3],,rw SDIO_STATUS,9,1,DATA_BUSY,Inverted version of raw selected card_data[0],,rw SDIO_STATUS,10,1,DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy,1,rw SDIO_STATUS,11,6,RESPONSE_INDEX,Index of previous response,0,rw SDIO_STATUS,17,13,FIFO_COUNT,Number of filled locations in FIFO,0,rw SDIO_STATUS,30,1,DMA_ACK,DMA acknowledge signal,0,rw SDIO_STATUS,31,1,DMA_REQ,DMA request signal,0,rw SDIO_FIFOTH,0,12,TX_WMARK,FIFO threshold watermark level when transmitting data to card,0,rw SDIO_FIFOTH,16,12,RX_WMARK,FIFO threshold watermark level when receiving data from card,0x1f,rw SDIO_FIFOTH,28,3,DMA_MTS,Burst size of multiple transaction,0,rw SDIO_CDETECT,0,1,CARD_DETECT,Card detect - 0 represents presence of card,0,rw SDIO_WRTPRT,0,1,WRITE_PROTECT,Write protect - 1 represents write protection,0,rw SDIO_TCBCNT,0,32,TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card,0,rw SDIO_TBBCNT,0,32,TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between host/DMA memory and BIU FIFO,0,rw SDIO_DEBNCE,0,24,DEBOUNCE_COUNT,Number of host clocks used by debounce filter logic for card detect,0xffffff,rw SDIO_RST_N,0,1,CARD_RESET,Hardware reset,1,rw SDIO_BMOD,0,1,SWR,Software reset,0,rw SDIO_BMOD,1,1,FB,Fixed burst,0,rw SDIO_BMOD,2,5,DSL,Descriptor skip length,0,rw SDIO_BMOD,7,1,DE,SD/MMC DMA enable,0,rw SDIO_BMOD,8,3,PBL,Programmable burst length,0,rw SDIO_PLDMND,0,32,PD,Poll demand,,rw SDIO_DBADDR,0,32,SDL,Start of descriptor list,0,rw SDIO_IDSTS,0,1,TI,Transmit interrupt,0,rw SDIO_IDSTS,1,1,RI,Receive interrupt,0,rw SDIO_IDSTS,2,1,FBE,Fatal bus error interrupt,0,rw SDIO_IDSTS,4,1,DU,Descriptor unavailable interrupt,0,rw SDIO_IDSTS,5,1,CES,Card error summary,0,rw SDIO_IDSTS,8,1,NIS,Normal interrupt summary,0,rw SDIO_IDSTS,9,1,AIS,Abnormal interrupt summary,0,rw SDIO_IDSTS,10,3,EB,Error bits,0,rw SDIO_IDSTS,13,4,FSM,DMAC state machine present state,0,rw SDIO_IDINTEN,0,1,TI,Transmit interrupt enable,0,rw SDIO_IDINTEN,1,1,RI,Receive interrupt enable,0,rw SDIO_IDINTEN,2,1,FBE,Fatal bus error enable,0,rw SDIO_IDINTEN,4,1,DU,Descriptor unavailable interrupt,0,rw SDIO_IDINTEN,5,1,CES,Card error summary interrupt,0,rw SDIO_IDINTEN,8,1,NIS,Normal interrupt summary enable,0,rw SDIO_IDINTEN,9,1,AIS,Abnormal interrupt summary enable,0,rw SDIO_DSCADDR,0,32,HDA,Host descriptor address pointer,0,rw SDIO_BUFADDR,0,32,HBA,Host buffer address pointer,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/sdio.yaml000066400000000000000000000526261435536612600232330ustar00rootroot00000000000000!!omap - SDIO_CTRL: fields: !!omap - CONTROLLER_RESET: access: rw description: Controller reset lsb: 0 reset_value: '0' width: 1 - FIFO_RESET: access: rw description: FIFO reset lsb: 1 reset_value: '0' width: 1 - DMA_RESET: access: rw description: DMA reset lsb: 2 reset_value: '0' width: 1 - INT_ENABLE: access: rw description: Global interrupt enable/disable lsb: 4 reset_value: '0' width: 1 - READ_WAIT: access: rw description: Read/wait send lsb: 6 reset_value: '0' width: 1 - SEND_IRQ_RESPONSE: access: rw description: Send IRQ response lsb: 7 reset_value: '0' width: 1 - ABORT_READ_DATA: access: rw description: Abort read data lsb: 8 reset_value: '0' width: 1 - SEND_CCSD: access: rw description: Send CCSD lsb: 9 reset_value: '0' width: 1 - SEND_AUTO_STOP_CCSD: access: rw description: Send auto stop CCSD lsb: 10 reset_value: '0' width: 1 - CEATA_DEVICE_INTERRUPT_STATUS: access: rw description: CEATA device interrupt status lsb: 11 reset_value: '0' width: 1 - CARD_VOLTAGE_A0: access: rw description: SD_VOLT0 pin control lsb: 16 reset_value: '0' width: 1 - CARD_VOLTAGE_A1: access: rw description: SD_VOLT1 pin control lsb: 17 reset_value: '0' width: 1 - CARD_VOLTAGE_A2: access: rw description: SD_VOLT2 pin control lsb: 18 reset_value: '0' width: 1 - USE_INTERNAL_DMAC: access: rw description: SD/MMC DMA use lsb: 25 reset_value: '0' width: 1 - SDIO_PWREN: fields: !!omap - POWER_ENABLE: access: rw description: Power on/off switch for card lsb: 0 reset_value: '0' width: 1 - SDIO_CLKDIV: fields: !!omap - CLK_DIVIDER0: access: rw description: Clock divider-0 value lsb: 0 reset_value: '0' width: 8 - CLK_DIVIDER1: access: rw description: Clock divider-1 value lsb: 8 reset_value: '0' width: 8 - CLK_DIVIDER2: access: rw description: Clock divider-2 value lsb: 16 reset_value: '0' width: 8 - CLK_DIVIDER3: access: rw description: Clock divider-3 value lsb: 24 reset_value: '0' width: 8 - SDIO_CLKSRC: fields: !!omap - CLK_SOURCE: access: rw description: Clock divider source for SD card lsb: 0 reset_value: '0' width: 2 - SDIO_CLKENA: fields: !!omap - CCLK_ENABLE: access: rw description: Clock-enable control for SD card clock lsb: 0 reset_value: '0' width: 1 - CCLK_LOW_POWER: access: rw description: Low-power control for SD card clock lsb: 16 reset_value: '0' width: 1 - SDIO_TMOUT: fields: !!omap - RESPONSE_TIMEOUT: access: rw description: Response time-out value lsb: 0 reset_value: '0x40' width: 8 - DATA_TIMEOUT: access: rw description: Value for card data read time-out lsb: 8 reset_value: '0xffffff' width: 24 - SDIO_CTYPE: fields: !!omap - CARD_WIDTH0: access: rw description: Indicates if card is 1-bit or 4-bit lsb: 0 reset_value: '0' width: 1 - CARD_WIDTH1: access: rw description: Indicates if card is 8-bit lsb: 16 reset_value: '0' width: 1 - SDIO_BLKSIZ: fields: !!omap - BLOCK_SIZE: access: rw description: Block size lsb: 0 reset_value: '0x200' width: 16 - SDIO_BYTCNT: fields: !!omap - BYTE_COUNT: access: rw description: Number of bytes to be transferred lsb: 0 reset_value: '0x200' width: 32 - SDIO_INTMASK: fields: !!omap - CDET: access: rw description: Card detect lsb: 0 reset_value: '0' width: 1 - RE: access: rw description: Response error lsb: 1 reset_value: '0' width: 1 - CDONE: access: rw description: Command done lsb: 2 reset_value: '0' width: 1 - DTO: access: rw description: Data transfer over lsb: 3 reset_value: '0' width: 1 - TXDR: access: rw description: Transmit FIFO data request lsb: 4 reset_value: '0' width: 1 - RXDR: access: rw description: Receive FIFO data request lsb: 5 reset_value: '0' width: 1 - RCRC: access: rw description: Response CRC error lsb: 6 reset_value: '0' width: 1 - DCRC: access: rw description: Data CRC error lsb: 7 reset_value: '0' width: 1 - RTO: access: rw description: Response time-out lsb: 8 reset_value: '0' width: 1 - DRTO: access: rw description: Data read time-out lsb: 9 reset_value: '0' width: 1 - HTO: access: rw description: Data starvation-by-host time-out/volt_switch_int lsb: 10 reset_value: '0' width: 1 - FRUN: access: rw description: FIFO underrun/overrun error lsb: 11 reset_value: '0' width: 1 - HLE: access: rw description: Hardware locked write error lsb: 12 reset_value: '0' width: 1 - SBE: access: rw description: Start-bit error lsb: 13 reset_value: '0' width: 1 - ACD: access: rw description: Auto command done lsb: 14 reset_value: '0' width: 1 - EBE: access: rw description: End-bit error (read)/Write no CRC lsb: 15 reset_value: '0' width: 1 - SDIO_INT_MASK: access: rw description: Mask SDIO interrupt lsb: 16 reset_value: '0' width: 1 - SDIO_CMDARG: fields: !!omap - CMD_ARG: access: rw description: Value indicates command argument to be passed to card lsb: 0 reset_value: '0' width: 32 - SDIO_CMD: fields: !!omap - CMD_INDEX: access: rw description: Command index lsb: 0 reset_value: '0' width: 6 - RESPONSE_EXPECT: access: rw description: Response expect lsb: 6 reset_value: '0' width: 1 - RESPONSE_LENGTH: access: rw description: Response length lsb: 7 reset_value: '0' width: 1 - CHECK_RESPONSE_CRC: access: rw description: Check response CRC lsb: 8 reset_value: '0' width: 1 - DATA_EXPECTED: access: rw description: Data expected lsb: 9 reset_value: '0' width: 1 - READ_WRITE: access: rw description: Read/write lsb: 10 reset_value: '0' width: 1 - TRANSFER_MODE: access: rw description: Transfer mode lsb: 11 reset_value: '0' width: 1 - SEND_AUTO_STOP: access: rw description: Send auto stop lsb: 12 reset_value: '0' width: 1 - WAIT_PRVDATA_COMPLETE: access: rw description: Wait prvdata complete lsb: 13 reset_value: '0' width: 1 - STOP_ABORT_CMD: access: rw description: Stop abort command lsb: 14 reset_value: '0' width: 1 - SEND_INITIALIZATION: access: rw description: Send initialization lsb: 15 reset_value: '0' width: 1 - UPDATE_CLOCK_REGISTERS_ONLY: access: rw description: Update clock registers only lsb: 21 reset_value: '0' width: 1 - READ_CEATA_DEVICE: access: rw description: Read CEATA device lsb: 22 reset_value: '0' width: 1 - CCS_EXPECTED: access: rw description: CCS expected lsb: 23 reset_value: '0' width: 1 - ENABLE_BOOT: access: rw description: Enable boot lsb: 24 reset_value: '0' width: 1 - EXPECT_BOOT_ACK: access: rw description: Expect boot acknowledge lsb: 25 reset_value: '0' width: 1 - DISABLE_BOOT: access: rw description: Disable boot lsb: 26 reset_value: '0' width: 1 - BOOT_MODE: access: rw description: Boot mode lsb: 27 reset_value: '0' width: 1 - VOLT_SWITCH: access: rw description: Voltage switch bit lsb: 28 reset_value: '0' width: 1 - START_CMD: access: rw description: Start command lsb: 31 reset_value: '0' width: 1 - SDIO_RESP0: fields: !!omap - RESPONSE0: access: rw description: Bit[31:0] of response lsb: 0 reset_value: '0' width: 32 - SDIO_RESP1: fields: !!omap - RESPONSE1: access: rw description: Bit[63:32] of long response lsb: 0 reset_value: '0' width: 32 - SDIO_RESP2: fields: !!omap - RESPONSE2: access: rw description: Bit[95:64] of long response lsb: 0 reset_value: '0' width: 32 - SDIO_RESP3: fields: !!omap - RESPONSE3: access: rw description: Bit[127:96] of long response lsb: 0 reset_value: '0' width: 32 - SDIO_MINTSTS: fields: !!omap - CDET: access: rw description: Card detect lsb: 0 reset_value: '0' width: 1 - RE: access: rw description: Response error lsb: 1 reset_value: '0' width: 1 - CDONE: access: rw description: Command done lsb: 2 reset_value: '0' width: 1 - DTO: access: rw description: Data transfer over lsb: 3 reset_value: '0' width: 1 - TXDR: access: rw description: Transmit FIFO data request lsb: 4 reset_value: '0' width: 1 - RXDR: access: rw description: Receive FIFO data request lsb: 5 reset_value: '0' width: 1 - RCRC: access: rw description: Response CRC error lsb: 6 reset_value: '0' width: 1 - DCRC: access: rw description: Data CRC error lsb: 7 reset_value: '0' width: 1 - RTO: access: rw description: Response time-out lsb: 8 reset_value: '0' width: 1 - DRTO: access: rw description: Data read time-out lsb: 9 reset_value: '0' width: 1 - HTO: access: rw description: Data starvation-by-host time-out lsb: 10 reset_value: '0' width: 1 - FRUN: access: rw description: FIFO underrun/overrun error lsb: 11 reset_value: '0' width: 1 - HLE: access: rw description: Hardware locked write error lsb: 12 reset_value: '0' width: 1 - SBE: access: rw description: Start-bit error lsb: 13 reset_value: '0' width: 1 - ACD: access: rw description: Auto command done lsb: 14 reset_value: '0' width: 1 - EBE: access: rw description: End-bit error (read)/write no CRC lsb: 15 reset_value: '0' width: 1 - SDIO_INTERRUPT: access: rw description: Interrupt from SDIO card lsb: 16 reset_value: '0' width: 1 - SDIO_RINTSTS: fields: !!omap - CDET: access: rw description: Card detect lsb: 0 reset_value: '0' width: 1 - RE: access: rw description: Response error lsb: 1 reset_value: '0' width: 1 - CDONE: access: rw description: Command done lsb: 2 reset_value: '0' width: 1 - DTO: access: rw description: Data transfer over lsb: 3 reset_value: '0' width: 1 - TXDR: access: rw description: Transmit FIFO data request lsb: 4 reset_value: '0' width: 1 - RXDR: access: rw description: Receive FIFO data request lsb: 5 reset_value: '0' width: 1 - RCRC: access: rw description: Response CRC error lsb: 6 reset_value: '0' width: 1 - DCRC: access: rw description: Data CRC error lsb: 7 reset_value: '0' width: 1 - RTO_BAR: access: rw description: Response time-out (RTO)/boot ack received (BAR) lsb: 8 reset_value: '0' width: 1 - DRTO_BDS: access: rw description: Data read time-out (DRTO)/boot data start (BDS) lsb: 9 reset_value: '0' width: 1 - HTO: access: rw description: Data starvation-by-host time-out lsb: 10 reset_value: '0' width: 1 - FRUN: access: rw description: FIFO underrun/overrun error lsb: 11 reset_value: '0' width: 1 - HLE: access: rw description: Hardware locked write error lsb: 12 reset_value: '0' width: 1 - SBE: access: rw description: Start-bit error lsb: 13 reset_value: '0' width: 1 - ACD: access: rw description: Auto command done lsb: 14 reset_value: '0' width: 1 - EBE: access: rw description: End-bit error (read)/write no CRC lsb: 15 reset_value: '0' width: 1 - SDIO_INTERRUPT: access: rw description: Interrupt from SDIO card lsb: 16 reset_value: '0' width: 1 - SDIO_STATUS: fields: !!omap - FIFO_RX_WATERMARK: access: rw description: FIFO reached receive watermark level lsb: 0 reset_value: '0' width: 1 - FIFO_TX_WATERMARK: access: rw description: FIFO reached transmit watermark level lsb: 1 reset_value: '1' width: 1 - FIFO_EMPTY: access: rw description: FIFO is empty lsb: 2 reset_value: '1' width: 1 - FIFO_FULL: access: rw description: FIFO is full lsb: 3 reset_value: '0' width: 1 - CMDFSMSTATES: access: rw description: Command FSM states lsb: 4 reset_value: '0' width: 4 - DATA_3_STATUS: access: rw description: Raw selected card_data[3] lsb: 8 reset_value: '' width: 1 - DATA_BUSY: access: rw description: Inverted version of raw selected card_data[0] lsb: 9 reset_value: '' width: 1 - DATA_STATE_MC_BUSY: access: rw description: Data transmit or receive state-machine is busy lsb: 10 reset_value: '1' width: 1 - RESPONSE_INDEX: access: rw description: Index of previous response lsb: 11 reset_value: '0' width: 6 - FIFO_COUNT: access: rw description: Number of filled locations in FIFO lsb: 17 reset_value: '0' width: 13 - DMA_ACK: access: rw description: DMA acknowledge signal lsb: 30 reset_value: '0' width: 1 - DMA_REQ: access: rw description: DMA request signal lsb: 31 reset_value: '0' width: 1 - SDIO_FIFOTH: fields: !!omap - TX_WMARK: access: rw description: FIFO threshold watermark level when transmitting data to card lsb: 0 reset_value: '0' width: 12 - RX_WMARK: access: rw description: FIFO threshold watermark level when receiving data from card lsb: 16 reset_value: '0x1f' width: 12 - DMA_MTS: access: rw description: Burst size of multiple transaction lsb: 28 reset_value: '0' width: 3 - SDIO_CDETECT: fields: !!omap - CARD_DETECT: access: rw description: Card detect - 0 represents presence of card lsb: 0 reset_value: '0' width: 1 - SDIO_WRTPRT: fields: !!omap - WRITE_PROTECT: access: rw description: Write protect - 1 represents write protection lsb: 0 reset_value: '0' width: 1 - SDIO_TCBCNT: fields: !!omap - TRANS_CARD_BYTE_COUNT: access: rw description: Number of bytes transferred by CIU unit to card lsb: 0 reset_value: '0' width: 32 - SDIO_TBBCNT: fields: !!omap - TRANS_FIFO_BYTE_COUNT: access: rw description: Number of bytes transferred between host/DMA memory and BIU FIFO lsb: 0 reset_value: '0' width: 32 - SDIO_DEBNCE: fields: !!omap - DEBOUNCE_COUNT: access: rw description: Number of host clocks used by debounce filter logic for card detect lsb: 0 reset_value: '0xffffff' width: 24 - SDIO_RST_N: fields: !!omap - CARD_RESET: access: rw description: Hardware reset lsb: 0 reset_value: '1' width: 1 - SDIO_BMOD: fields: !!omap - SWR: access: rw description: Software reset lsb: 0 reset_value: '0' width: 1 - FB: access: rw description: Fixed burst lsb: 1 reset_value: '0' width: 1 - DSL: access: rw description: Descriptor skip length lsb: 2 reset_value: '0' width: 5 - DE: access: rw description: SD/MMC DMA enable lsb: 7 reset_value: '0' width: 1 - PBL: access: rw description: Programmable burst length lsb: 8 reset_value: '0' width: 3 - SDIO_PLDMND: fields: !!omap - PD: access: rw description: Poll demand lsb: 0 reset_value: '' width: 32 - SDIO_DBADDR: fields: !!omap - SDL: access: rw description: Start of descriptor list lsb: 0 reset_value: '0' width: 32 - SDIO_IDSTS: fields: !!omap - TI: access: rw description: Transmit interrupt lsb: 0 reset_value: '0' width: 1 - RI: access: rw description: Receive interrupt lsb: 1 reset_value: '0' width: 1 - FBE: access: rw description: Fatal bus error interrupt lsb: 2 reset_value: '0' width: 1 - DU: access: rw description: Descriptor unavailable interrupt lsb: 4 reset_value: '0' width: 1 - CES: access: rw description: Card error summary lsb: 5 reset_value: '0' width: 1 - NIS: access: rw description: Normal interrupt summary lsb: 8 reset_value: '0' width: 1 - AIS: access: rw description: Abnormal interrupt summary lsb: 9 reset_value: '0' width: 1 - EB: access: rw description: Error bits lsb: 10 reset_value: '0' width: 3 - FSM: access: rw description: DMAC state machine present state lsb: 13 reset_value: '0' width: 4 - SDIO_IDINTEN: fields: !!omap - TI: access: rw description: Transmit interrupt enable lsb: 0 reset_value: '0' width: 1 - RI: access: rw description: Receive interrupt enable lsb: 1 reset_value: '0' width: 1 - FBE: access: rw description: Fatal bus error enable lsb: 2 reset_value: '0' width: 1 - DU: access: rw description: Descriptor unavailable interrupt lsb: 4 reset_value: '0' width: 1 - CES: access: rw description: Card error summary interrupt lsb: 5 reset_value: '0' width: 1 - NIS: access: rw description: Normal interrupt summary enable lsb: 8 reset_value: '0' width: 1 - AIS: access: rw description: Abnormal interrupt summary enable lsb: 9 reset_value: '0' width: 1 - SDIO_DSCADDR: fields: !!omap - HDA: access: rw description: Host descriptor address pointer lsb: 0 reset_value: '0' width: 32 - SDIO_BUFADDR: fields: !!omap - HBA: access: rw description: Host buffer address pointer lsb: 0 reset_value: '0' width: 32 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/sgpio.csv000066400000000000000000000467621435536612600232530ustar00rootroot00000000000000SGPIO_OUT_MUX_CFG0,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG0,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG1,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG1,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG2,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG2,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG3,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG3,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG4,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG4,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG5,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG5,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG6,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG6,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG7,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG7,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG8,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG8,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG9,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG9,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG10,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG10,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG11,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG11,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG12,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG12,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG13,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG13,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG14,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG14,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_OUT_MUX_CFG15,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw SGPIO_OUT_MUX_CFG15,4,3,P_OE_CFG,Output enable source,0,rw SGPIO_MUX_CFG0,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG0,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG0,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG0,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG0,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG0,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG0,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG0,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG1,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG1,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG1,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG1,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG1,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG1,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG1,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG1,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG2,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG2,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG2,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG2,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG2,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG2,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG2,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG2,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG3,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG3,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG3,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG3,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG3,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG3,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG3,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG3,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG4,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG4,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG4,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG4,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG4,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG4,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG4,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG4,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG5,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG5,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG5,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG5,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG5,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG5,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG5,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG5,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG6,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG6,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG6,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG6,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG6,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG6,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG6,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG6,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG7,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG7,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG7,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG7,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG7,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG7,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG7,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG7,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG8,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG8,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG8,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG8,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG8,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG8,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG8,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG8,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG9,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG9,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG9,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG9,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG9,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG9,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG9,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG9,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG10,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG10,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG10,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG10,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG10,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG10,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG10,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG10,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG11,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG11,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG11,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG11,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG11,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG11,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG11,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG11,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG12,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG12,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG12,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG12,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG12,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG12,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG12,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG12,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG13,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG13,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG13,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG13,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG13,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG13,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG13,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG13,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG14,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG14,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG14,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG14,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG14,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG14,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG14,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG14,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_MUX_CFG15,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw SGPIO_MUX_CFG15,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw SGPIO_MUX_CFG15,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw SGPIO_MUX_CFG15,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw SGPIO_MUX_CFG15,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw SGPIO_MUX_CFG15,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw SGPIO_MUX_CFG15,11,1,CONCAT_ENABLE,Enable concatenation,0,rw SGPIO_MUX_CFG15,12,2,CONCAT_ORDER,Select concatenation order,0,rw SGPIO_SLICE_MUX_CFG0,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG0,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG0,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG0,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG0,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG0,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG0,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG1,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG1,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG1,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG1,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG1,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG1,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG1,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG2,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG2,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG2,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG2,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG2,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG2,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG2,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG3,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG3,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG3,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG3,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG3,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG3,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG3,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG4,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG4,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG4,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG4,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG4,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG4,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG4,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG5,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG5,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG5,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG5,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG5,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG5,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG5,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG6,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG6,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG6,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG6,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG6,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG6,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG6,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG7,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG7,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG7,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG7,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG7,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG7,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG7,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG8,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG8,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG8,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG8,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG8,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG8,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG8,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG9,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG9,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG9,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG9,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG9,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG9,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG9,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG10,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG10,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG10,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG10,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG10,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG10,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG10,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG11,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG11,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG11,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG11,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG11,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG11,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG11,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG12,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG12,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG12,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG12,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG12,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG12,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG12,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG13,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG13,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG13,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG13,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG13,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG13,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG13,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG14,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG14,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG14,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG14,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG14,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG14,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG14,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_SLICE_MUX_CFG15,0,1,MATCH_MODE,Match mode,0,rw SGPIO_SLICE_MUX_CFG15,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw SGPIO_SLICE_MUX_CFG15,2,1,CLKGEN_MODE,Clock generation mode,0,rw SGPIO_SLICE_MUX_CFG15,3,1,INV_OUT_CLK,Invert output clock,0,rw SGPIO_SLICE_MUX_CFG15,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw SGPIO_SLICE_MUX_CFG15,6,2,PARALLEL_MODE,Parallel mode,0,rw SGPIO_SLICE_MUX_CFG15,8,1,INV_QUALIFIER,Inversion qualifier,0,rw SGPIO_POS0,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS0,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS1,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS1,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS2,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS2,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS3,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS3,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS4,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS4,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS5,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS5,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS6,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS6,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS7,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS7,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS8,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS8,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS9,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS9,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS10,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS10,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS11,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS11,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS12,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS12,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS13,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS13,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS14,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS14,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw SGPIO_POS15,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw SGPIO_POS15,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/sgpio.yaml000066400000000000000000001316371435536612600234160ustar00rootroot00000000000000!!omap - SGPIO_OUT_MUX_CFG0: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG1: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG2: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG3: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG4: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG5: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG6: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG7: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG8: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG9: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG10: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG11: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG12: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG13: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG14: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_OUT_MUX_CFG15: fields: !!omap - P_OUT_CFG: access: rw description: Output control of output SGPIOn lsb: 0 reset_value: '0' width: 4 - P_OE_CFG: access: rw description: Output enable source lsb: 4 reset_value: '0' width: 3 - SGPIO_MUX_CFG0: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG1: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG2: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG3: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG4: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG5: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG6: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG7: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG8: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG9: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG10: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG11: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG12: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG13: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG14: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_MUX_CFG15: fields: !!omap - EXT_CLK_ENABLE: access: rw description: Select clock signal lsb: 0 reset_value: '0' width: 1 - CLK_SOURCE_PIN_MODE: access: rw description: Select source clock pin lsb: 1 reset_value: '0' width: 2 - CLK_SOURCE_SLICE_MODE: access: rw description: Select clock source slice lsb: 3 reset_value: '0' width: 2 - QUALIFIER_MODE: access: rw description: Select qualifier mode lsb: 5 reset_value: '0' width: 2 - QUALIFIER_PIN_MODE: access: rw description: Select qualifier pin lsb: 7 reset_value: '0' width: 2 - QUALIFIER_SLICE_MODE: access: rw description: Select qualifier slice lsb: 9 reset_value: '0' width: 2 - CONCAT_ENABLE: access: rw description: Enable concatenation lsb: 11 reset_value: '0' width: 1 - CONCAT_ORDER: access: rw description: Select concatenation order lsb: 12 reset_value: '0' width: 2 - SGPIO_SLICE_MUX_CFG0: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG1: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG2: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG3: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG4: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG5: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG6: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG7: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG8: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG9: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG10: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG11: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG12: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG13: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG14: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_SLICE_MUX_CFG15: fields: !!omap - MATCH_MODE: access: rw description: Match mode lsb: 0 reset_value: '0' width: 1 - CLK_CAPTURE_MODE: access: rw description: Capture clock mode lsb: 1 reset_value: '0' width: 1 - CLKGEN_MODE: access: rw description: Clock generation mode lsb: 2 reset_value: '0' width: 1 - INV_OUT_CLK: access: rw description: Invert output clock lsb: 3 reset_value: '0' width: 1 - DATA_CAPTURE_MODE: access: rw description: Condition for input bit match interrupt lsb: 4 reset_value: '0' width: 2 - PARALLEL_MODE: access: rw description: Parallel mode lsb: 6 reset_value: '0' width: 2 - INV_QUALIFIER: access: rw description: Inversion qualifier lsb: 8 reset_value: '0' width: 1 - SGPIO_POS0: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS1: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS2: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS3: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS4: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS5: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS6: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS7: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS8: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS9: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS10: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS11: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS12: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS13: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS14: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 - SGPIO_POS15: fields: !!omap - POS: access: rw description: Each time COUNT reaches 0x0 POS counts down lsb: 0 reset_value: '0' width: 8 - POS_RESET: access: rw description: Reload value for POS after POS reaches 0x0 lsb: 8 reset_value: '0' width: 8 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/spi.csv000066400000000000000000000014461435536612600227130ustar00rootroot00000000000000SPI_CR,2,1,BITENABLE,Bit length enable,0,rw SPI_CR,3,1,CPHA,Clock phase control,0,rw SPI_CR,4,1,CPOL,Clock polarity control,0,rw SPI_CR,5,1,MSTR,Master mode select,0,rw SPI_CR,6,1,LSBF,LSB first,0,rw SPI_CR,7,1,SPIE,Serial peripheral interrupt enable,0,rw SPI_CR,8,4,BITS,Bits per transfer,0,rw SPI_SR,3,1,ABRT,Slave abort,0,ro SPI_SR,4,1,MODF,Mode fault,0,ro SPI_SR,5,1,ROVR,Read overrun,0,ro SPI_SR,6,1,WCOL,Write collision,0,ro SPI_SR,7,1,SPIF,Transfer complete,0,ro SPI_DR,0,16,DATA,Bi-directional data port,0,rw SPI_CCR,0,8,COUNTER,Clock counter setting,0,rw SPI_TCR,1,7,TEST,Test mode,0,rw SPI_TSR,3,1,ABRT,Slave abort,0,rw SPI_TSR,4,1,MODF,Mode fault,0,rw SPI_TSR,5,1,ROVR,Read overrun,0,rw SPI_TSR,6,1,WCOL,Write collision,0,rw SPI_TSR,7,1,SPIF,Transfer complete,0,rw SPI_CR,0,1,SPIF,Interrupt,0,rwhackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/spi.yaml000066400000000000000000000054201435536612600230560ustar00rootroot00000000000000!!omap - SPI_CR: fields: !!omap - BITENABLE: access: rw description: Bit length enable lsb: 2 reset_value: '0' width: 1 - CPHA: access: rw description: Clock phase control lsb: 3 reset_value: '0' width: 1 - CPOL: access: rw description: Clock polarity control lsb: 4 reset_value: '0' width: 1 - MSTR: access: rw description: Master mode select lsb: 5 reset_value: '0' width: 1 - LSBF: access: rw description: LSB first lsb: 6 reset_value: '0' width: 1 - SPIE: access: rw description: Serial peripheral interrupt enable lsb: 7 reset_value: '0' width: 1 - BITS: access: rw description: Bits per transfer lsb: 8 reset_value: '0' width: 4 - SPIF: access: rw description: Interrupt lsb: 0 reset_value: '0' width: 1 - SPI_SR: fields: !!omap - ABRT: access: ro description: Slave abort lsb: 3 reset_value: '0' width: 1 - MODF: access: ro description: Mode fault lsb: 4 reset_value: '0' width: 1 - ROVR: access: ro description: Read overrun lsb: 5 reset_value: '0' width: 1 - WCOL: access: ro description: Write collision lsb: 6 reset_value: '0' width: 1 - SPIF: access: ro description: Transfer complete lsb: 7 reset_value: '0' width: 1 - SPI_DR: fields: !!omap - DATA: access: rw description: Bi-directional data port lsb: 0 reset_value: '0' width: 16 - SPI_CCR: fields: !!omap - COUNTER: access: rw description: Clock counter setting lsb: 0 reset_value: '0' width: 8 - SPI_TCR: fields: !!omap - TEST: access: rw description: Test mode lsb: 1 reset_value: '0' width: 7 - SPI_TSR: fields: !!omap - ABRT: access: rw description: Slave abort lsb: 3 reset_value: '0' width: 1 - MODF: access: rw description: Mode fault lsb: 4 reset_value: '0' width: 1 - ROVR: access: rw description: Read overrun lsb: 5 reset_value: '0' width: 1 - WCOL: access: rw description: Write collision lsb: 6 reset_value: '0' width: 1 - SPIF: access: rw description: Transfer complete lsb: 7 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/spifi.csv000066400000000000000000000032361435536612600232310ustar00rootroot00000000000000SPIFI_CTRL,0,16,TIMEOUT,Memory mode idle timeout,0xffff,rw SPIFI_CTRL,16,4,CSHIGH,Minimum CS# high time,15,rw SPIFI_CTRL,21,1,D_PRFTCH_DIS,Disable speculative prefetch,0,rw SPIFI_CTRL,22,1,INTEN,Enable command end interrupt,0,rw SPIFI_CTRL,23,1,MODE3,SPI mode 3 select,0,rw SPIFI_CTRL,27,1,PRFTCH_DIS,Disable prefetching of cache lines,0,rw SPIFI_CTRL,28,1,DUAL,Select dual protocol,0,rw SPIFI_CTRL,29,1,RFCLK,Read data on falling edge,0,rw SPIFI_CTRL,30,1,FBCLK,Feedback clock select,1,rw SPIFI_CTRL,31,1,DMAEN,DMA request output enable,0,rw SPIFI_CMD,0,14,DATALEN,Data bytes in command,0,rw SPIFI_CMD,14,1,POLL,Poll at end of command,0,rw SPIFI_CMD,15,1,DOUT,Data output to serial flash,0,rw SPIFI_CMD,16,3,INTLEN,Intermediate bytes before data,0,rw SPIFI_CMD,19,2,FIELDFORM,Form of command fields,0,rw SPIFI_CMD,21,3,FRAMEFORM,Form of the opcode/address fields,0,rw SPIFI_CMD,24,8,OPCODE,Command opcode,0,rw SPIFI_ADDR,0,32,ADDRESS,Address field value,0,rw SPIFI_IDATA,0,32,IDATA,Intermediate bytes value,0,rw SPIFI_CLIMIT,0,32,CLIMIT,Upper limit of cacheable memory,0x08000000,rw SPIFI_DATA,0,32,DATA,Input or output data,0,rw SPIFI_MCMD,14,1,POLL,Must be zero,0,rw SPIFI_MCMD,15,1,DOUT,Must be zero,0,rw SPIFI_MCMD,16,3,INTLEN,Intermediate bytes before data,0,rw SPIFI_MCMD,19,2,FIELDFORM,Form of command fields,0,rw SPIFI_MCMD,21,3,FRAMEFORM,Form of the opcode/address fields,0,rw SPIFI_MCMD,24,8,OPCODE,Command opcode,0,rw SPIFI_STAT,0,1,MCINIT,Memory command initialized,0,rw SPIFI_STAT,1,1,CMD,Command active,0,rw SPIFI_STAT,4,1,RESET,Abort current command/memory mode,0,rw SPIFI_STAT,5,1,INTRQ,Interrupt request status,0,rw SPIFI_STAT,24,8,VERSION,Peripheral hardware version,0x02,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/spifi.yaml000066400000000000000000000110631435536612600233750ustar00rootroot00000000000000!!omap - SPIFI_CTRL: fields: !!omap - TIMEOUT: access: rw description: Memory mode idle timeout lsb: 0 reset_value: '0xffff' width: 16 - CSHIGH: access: rw description: Minimum CS# high time lsb: 16 reset_value: '15' width: 4 - D_PRFTCH_DIS: access: rw description: Disable speculative prefetch lsb: 21 reset_value: '0' width: 1 - INTEN: access: rw description: Enable command end interrupt lsb: 22 reset_value: '0' width: 1 - MODE3: access: rw description: SPI mode 3 select lsb: 23 reset_value: '0' width: 1 - PRFTCH_DIS: access: rw description: Disable prefetching of cache lines lsb: 27 reset_value: '0' width: 1 - DUAL: access: rw description: Select dual protocol lsb: 28 reset_value: '0' width: 1 - RFCLK: access: rw description: Read data on falling edge lsb: 29 reset_value: '0' width: 1 - FBCLK: access: rw description: Feedback clock select lsb: 30 reset_value: '1' width: 1 - DMAEN: access: rw description: DMA request output enable lsb: 31 reset_value: '0' width: 1 - SPIFI_CMD: fields: !!omap - DATALEN: access: rw description: Data bytes in command lsb: 0 reset_value: '0' width: 14 - POLL: access: rw description: Poll at end of command lsb: 14 reset_value: '0' width: 1 - DOUT: access: rw description: Data output to serial flash lsb: 15 reset_value: '0' width: 1 - INTLEN: access: rw description: Intermediate bytes before data lsb: 16 reset_value: '0' width: 3 - FIELDFORM: access: rw description: Form of command fields lsb: 19 reset_value: '0' width: 2 - FRAMEFORM: access: rw description: Form of the opcode/address fields lsb: 21 reset_value: '0' width: 3 - OPCODE: access: rw description: Command opcode lsb: 24 reset_value: '0' width: 8 - SPIFI_ADDR: fields: !!omap - ADDRESS: access: rw description: Address field value lsb: 0 reset_value: '0' width: 32 - SPIFI_IDATA: fields: !!omap - IDATA: access: rw description: Intermediate bytes value lsb: 0 reset_value: '0' width: 32 - SPIFI_CLIMIT: fields: !!omap - CLIMIT: access: rw description: Upper limit of cacheable memory lsb: 0 reset_value: '0x08000000' width: 32 - SPIFI_DATA: fields: !!omap - DATA: access: rw description: Input or output data lsb: 0 reset_value: '0' width: 32 - SPIFI_MCMD: fields: !!omap - POLL: access: rw description: Must be zero lsb: 14 reset_value: '0' width: 1 - DOUT: access: rw description: Must be zero lsb: 15 reset_value: '0' width: 1 - INTLEN: access: rw description: Intermediate bytes before data lsb: 16 reset_value: '0' width: 3 - FIELDFORM: access: rw description: Form of command fields lsb: 19 reset_value: '0' width: 2 - FRAMEFORM: access: rw description: Form of the opcode/address fields lsb: 21 reset_value: '0' width: 3 - OPCODE: access: rw description: Command opcode lsb: 24 reset_value: '0' width: 8 - SPIFI_STAT: fields: !!omap - MCINIT: access: rw description: Memory command initialized lsb: 0 reset_value: '0' width: 1 - CMD: access: rw description: Command active lsb: 1 reset_value: '0' width: 1 - RESET: access: rw description: Abort current command/memory mode lsb: 4 reset_value: '0' width: 1 - INTRQ: access: rw description: Interrupt request status lsb: 5 reset_value: '0' width: 1 - VERSION: access: rw description: Peripheral hardware version lsb: 24 reset_value: '0x02' width: 8 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/ssp.csv000066400000000000000000000111421435536612600227170ustar00rootroot00000000000000SSP0_CR0,0,4,DSS,Data Size Select,0,rw SSP0_CR0,4,2,FRF,Frame Format,0,rw SSP0_CR0,6,1,CPOL,Clock Out Polarity,0,rw SSP0_CR0,7,1,CPHA,Clock Out Phase,0,rw SSP0_CR0,8,8,SCR,Serial Clock Rate,0,rw SSP1_CR0,0,4,DSS,Data Size Select,0,rw SSP1_CR0,4,2,FRF,Frame Format,0,rw SSP1_CR0,6,1,CPOL,Clock Out Polarity,0,rw SSP1_CR0,7,1,CPHA,Clock Out Phase,0,rw SSP1_CR0,8,8,SCR,Serial Clock Rate,0,rw SSP0_CR1,0,1,LBM,Loop Back Mode,0,rw SSP0_CR1,1,1,SSE,SSP Enable,0,rw SSP0_CR1,2,1,MS,Master/Slave Mode,0,rw SSP0_CR1,3,1,SOD,Slave Output Disable,0,rw SSP1_CR1,1,1,SSE,SSP Enable,0,rw SSP1_CR1,2,1,MS,Master/Slave Mode,0,rw SSP1_CR1,3,1,SOD,Slave Output Disable,0,rw SSP0_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw SSP1_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw SSP0_SR,0,1,TFE,Transmit FIFO Empty,1,r SSP0_SR,1,1,TNF,Transmit FIFO Not Full,1,r SSP0_SR,2,1,RNE,Receive FIFO Not Empty,0,r SSP0_SR,3,1,RFF,Receive FIFO Full,0,r SSP0_SR,4,1,BSY,Busy.,0,r SSP1_SR,0,1,TFE,Transmit FIFO Empty,1,r SSP1_SR,1,1,TNF,Transmit FIFO Not Full,1,r SSP1_SR,2,1,RNE,Receive FIFO Not Empty,0,r SSP1_SR,3,1,RFF,Receive FIFO Full,0,r SSP1_SR,4,1,BSY,Busy.,0,r SSP0_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw SSP1_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw SSP0_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw SSP0_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw SSP0_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw SSP0_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw SSP1_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw SSP1_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw SSP1_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw SSP1_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw SSP0_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r SSP0_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r SSP0_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r SSP0_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r SSP1_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r SSP1_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r SSP1_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r SSP1_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r SSP0_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r SSP0_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r SSP0_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r SSP0_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r SSP1_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r SSP1_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r SSP1_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r SSP1_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r SSP0_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w SSP0_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w SSP1_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w SSP1_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w SSP0_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw SSP0_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw SSP1_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw SSP1_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/ssp.yaml000066400000000000000000000252521435536612600230750ustar00rootroot00000000000000!!omap - SSP0_CR0: fields: !!omap - DSS: access: rw description: Data Size Select lsb: 0 reset_value: '0' width: 4 - FRF: access: rw description: Frame Format lsb: 4 reset_value: '0' width: 2 - CPOL: access: rw description: Clock Out Polarity lsb: 6 reset_value: '0' width: 1 - CPHA: access: rw description: Clock Out Phase lsb: 7 reset_value: '0' width: 1 - SCR: access: rw description: Serial Clock Rate lsb: 8 reset_value: '0' width: 8 - SSP1_CR0: fields: !!omap - DSS: access: rw description: Data Size Select lsb: 0 reset_value: '0' width: 4 - FRF: access: rw description: Frame Format lsb: 4 reset_value: '0' width: 2 - CPOL: access: rw description: Clock Out Polarity lsb: 6 reset_value: '0' width: 1 - CPHA: access: rw description: Clock Out Phase lsb: 7 reset_value: '0' width: 1 - SCR: access: rw description: Serial Clock Rate lsb: 8 reset_value: '0' width: 8 - SSP0_CR1: fields: !!omap - LBM: access: rw description: Loop Back Mode lsb: 0 reset_value: '0' width: 1 - SSE: access: rw description: SSP Enable lsb: 1 reset_value: '0' width: 1 - MS: access: rw description: Master/Slave Mode lsb: 2 reset_value: '0' width: 1 - SOD: access: rw description: Slave Output Disable lsb: 3 reset_value: '0' width: 1 - SSP1_CR1: fields: !!omap - SSE: access: rw description: SSP Enable lsb: 1 reset_value: '0' width: 1 - MS: access: rw description: Master/Slave Mode lsb: 2 reset_value: '0' width: 1 - SOD: access: rw description: Slave Output Disable lsb: 3 reset_value: '0' width: 1 - SSP0_DR: fields: !!omap - DATA: access: rw description: Software can write data to be transmitted to this register, and read data that has been lsb: 0 reset_value: '0' width: 16 - SSP1_DR: fields: !!omap - DATA: access: rw description: Software can write data to be transmitted to this register, and read data that has been lsb: 0 reset_value: '0' width: 16 - SSP0_SR: fields: !!omap - TFE: access: r description: Transmit FIFO Empty lsb: 0 reset_value: '1' width: 1 - TNF: access: r description: Transmit FIFO Not Full lsb: 1 reset_value: '1' width: 1 - RNE: access: r description: Receive FIFO Not Empty lsb: 2 reset_value: '0' width: 1 - RFF: access: r description: Receive FIFO Full lsb: 3 reset_value: '0' width: 1 - BSY: access: r description: Busy. lsb: 4 reset_value: '0' width: 1 - SSP1_SR: fields: !!omap - TFE: access: r description: Transmit FIFO Empty lsb: 0 reset_value: '1' width: 1 - TNF: access: r description: Transmit FIFO Not Full lsb: 1 reset_value: '1' width: 1 - RNE: access: r description: Receive FIFO Not Empty lsb: 2 reset_value: '0' width: 1 - RFF: access: r description: Receive FIFO Full lsb: 3 reset_value: '0' width: 1 - BSY: access: r description: Busy. lsb: 4 reset_value: '0' width: 1 - SSP0_CPSR: fields: !!omap - CPSDVSR: access: rw description: SSP Clock Prescale Register lsb: 0 reset_value: '0' width: 8 - SSP1_CPSR: fields: !!omap - CPSDVSR: access: rw description: SSP Clock Prescale Register lsb: 0 reset_value: '0' width: 8 - SSP0_IMSC: fields: !!omap - RORIM: access: rw description: Software should set this bit to enable interrupt when a Receive Overrun occurs lsb: 0 reset_value: '0' width: 1 - RTIM: access: rw description: Software should set this bit to enable interrupt when a Receive Time-out condition occurs lsb: 1 reset_value: '0' width: 1 - RXIM: access: rw description: Software should set this bit to enable interrupt when the Rx FIFO is at least half full lsb: 2 reset_value: '0' width: 1 - TXIM: access: rw description: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty lsb: 3 reset_value: '0' width: 1 - SSP1_IMSC: fields: !!omap - RORIM: access: rw description: Software should set this bit to enable interrupt when a Receive Overrun occurs lsb: 0 reset_value: '0' width: 1 - RTIM: access: rw description: Software should set this bit to enable interrupt when a Receive Time-out condition occurs lsb: 1 reset_value: '0' width: 1 - RXIM: access: rw description: Software should set this bit to enable interrupt when the Rx FIFO is at least half full lsb: 2 reset_value: '0' width: 1 - TXIM: access: rw description: Software should set this bit to enable interrupt when the Tx FIFO is at least half empty lsb: 3 reset_value: '0' width: 1 - SSP0_RIS: fields: !!omap - RORRIS: access: r description: This bit is 1 if another frame was completely received while the RxFIFO was full lsb: 0 reset_value: '0' width: 1 - RTRIS: access: r description: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period lsb: 1 reset_value: '0' width: 1 - RXRIS: access: r description: This bit is 1 if the Rx FIFO is at least half full lsb: 2 reset_value: '0' width: 1 - TXRIS: access: r description: This bit is 1 if the Tx FIFO is at least half empty lsb: 3 reset_value: '1' width: 1 - SSP1_RIS: fields: !!omap - RORRIS: access: r description: This bit is 1 if another frame was completely received while the RxFIFO was full lsb: 0 reset_value: '0' width: 1 - RTRIS: access: r description: This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period lsb: 1 reset_value: '0' width: 1 - RXRIS: access: r description: This bit is 1 if the Rx FIFO is at least half full lsb: 2 reset_value: '0' width: 1 - TXRIS: access: r description: This bit is 1 if the Tx FIFO is at least half empty lsb: 3 reset_value: '1' width: 1 - SSP0_MIS: fields: !!omap - RORMIS: access: r description: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled lsb: 0 reset_value: '0' width: 1 - RTMIS: access: r description: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled lsb: 1 reset_value: '0' width: 1 - RXMIS: access: r description: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled lsb: 2 reset_value: '0' width: 1 - TXMIS: access: r description: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled lsb: 3 reset_value: '0' width: 1 - SSP1_MIS: fields: !!omap - RORMIS: access: r description: This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled lsb: 0 reset_value: '0' width: 1 - RTMIS: access: r description: This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled lsb: 1 reset_value: '0' width: 1 - RXMIS: access: r description: This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled lsb: 2 reset_value: '0' width: 1 - TXMIS: access: r description: This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled lsb: 3 reset_value: '0' width: 1 - SSP0_ICR: fields: !!omap - RORIC: access: w description: Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt lsb: 0 reset_value: '' width: 1 - RTIC: access: w description: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt lsb: 1 reset_value: '' width: 1 - SSP1_ICR: fields: !!omap - RORIC: access: w description: Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt lsb: 0 reset_value: '' width: 1 - RTIC: access: w description: Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt lsb: 1 reset_value: '' width: 1 - SSP0_DMACR: fields: !!omap - RXDMAE: access: rw description: Receive DMA Enable lsb: 0 reset_value: '0' width: 1 - TXDMAE: access: rw description: Transmit DMA Enable lsb: 1 reset_value: '0' width: 1 - SSP1_DMACR: fields: !!omap - RXDMAE: access: rw description: Receive DMA Enable lsb: 0 reset_value: '0' width: 1 - TXDMAE: access: rw description: Transmit DMA Enable lsb: 1 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/usb.csv000066400000000000000000000275711435536612600227200ustar00rootroot00000000000000USB0_CAPLENGTH,0,8,CAPLENGTH,Indicates offset to add to the register base address at the beginning of the Operational Register,0x40,r USB0_CAPLENGTH,8,16,HCIVERSION,BCD encoding of the EHCI revision number supported by this host controller,0x100,r USB0_HCSPARAMS,0,4,N_PORTS,Number of downstream ports,0x1,r USB0_HCSPARAMS,4,1,PPC,Port Power Control,0x1,r USB0_HCSPARAMS,8,4,N_PCC,Number of Ports per Companion Controller,0x0,r USB0_HCSPARAMS,12,4,N_CC,Number of Companion Controller,0x0,r USB0_HCSPARAMS,16,1,PI,Port indicators,0x1,r USB0_HCSPARAMS,20,4,N_PTT,Number of Ports per Transaction Translator,0x0,r USB0_HCSPARAMS,24,4,N_TT,Number of Transaction Translators,0x0,r USB0_HCCPARAMS,0,1,ADC,64-bit Addressing Capability,0,r USB0_HCCPARAMS,1,1,PFL,Programmable Frame List Flag,1,r USB0_HCCPARAMS,2,1,ASP,Asynchronous Schedule Park Capability,1,r USB0_HCCPARAMS,4,4,IST,Isochronous Scheduling Threshold,0,r USB0_HCCPARAMS,8,4,EECP,EHCI Extended Capabilities Pointer,0,r USB0_DCCPARAMS,0,5,DEN,Device Endpoint Number,0x4,r USB0_DCCPARAMS,7,1,DC,Device Capable,0x1,r USB0_DCCPARAMS,8,1,HC,Host Capable,0x1,r USB0_USBCMD_D,0,1,RS,Run/Stop,0,rw USB0_USBCMD_D,1,1,RST,Controller reset,0,rw USB0_USBCMD_D,13,1,SUTW,Setup trip wire,0,rw USB0_USBCMD_D,14,1,ATDTW,Add dTD trip wire,0,rw USB0_USBCMD_D,16,8,ITC,Interrupt threshold control,0x8,rw USB0_USBCMD_H,0,1,RS,Run/Stop,0,rw USB0_USBCMD_H,1,1,RST,Controller reset,0,rw USB0_USBCMD_H,2,1,FS0,Bit 0 of the Frame List Size bits,0, USB0_USBCMD_H,3,1,FS1,Bit 1 of the Frame List Size bits,0, USB0_USBCMD_H,4,1,PSE,This bit controls whether the host controller skips processing the periodic schedule,0,rw USB0_USBCMD_H,5,1,ASE,This bit controls whether the host controller skips processing the asynchronous schedule,0,rw USB0_USBCMD_H,6,1,IAA,This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule,0,rw USB0_USBCMD_H,8,2,ASP1_0,Asynchronous schedule park mode,0x3,rw USB0_USBCMD_H,11,1,ASPE,Asynchronous Schedule Park Mode Enable,1,rw USB0_USBCMD_H,15,1,FS2,Bit 2 of the Frame List Size bits,0, USB0_USBCMD_H,16,8,ITC,Interrupt threshold control,0x8,rw USB0_USBSTS_D,0,1,UI,USB interrupt,0,rwc USB0_USBSTS_D,1,1,UEI,USB error interrupt,0,rwc USB0_USBSTS_D,2,1,PCI,Port change detect,0,rwc USB0_USBSTS_D,6,1,URI,USB reset received,0,rwc USB0_USBSTS_D,7,1,SRI,SOF received,0,rwc USB0_USBSTS_D,8,1,SLI,DCSuspend,0,rwc USB0_USBSTS_D,16,1,NAKI,NAK interrupt bit,0,r USB0_USBSTS_H,0,1,UI,USB interrupt,0,rwc USB0_USBSTS_H,1,1,UEI,USB error interrupt,0,rwc USB0_USBSTS_H,2,1,PCI,Port change detect,0,rwc USB0_USBSTS_H,3,1,FRI,Frame list roll-over,0,rwc USB0_USBSTS_H,5,1,AAI,Interrupt on async advance,0,rwc USB0_USBSTS_H,7,1,SRI,SOF received,0,rwc USB0_USBSTS_H,12,1,HCH,HCHalted,1,r USB0_USBSTS_H,13,1,RCL,Reclamation,0,r USB0_USBSTS_H,14,1,PS,Periodic schedule status,0,r USB0_USBSTS_H,15,1,AS,Asynchronous schedule status,0, USB0_USBSTS_H,18,1,UAI,USB host asynchronous interrupt (USBHSTASYNCINT),0,rwc USB0_USBSTS_H,19,1,UPI,USB host periodic interrupt (USBHSTPERINT),0,rwc USB0_USBINTR_D,0,1,UE,USB interrupt enable,0,rw USB0_USBINTR_D,1,1,UEE,USB error interrupt enable,0,rw USB0_USBINTR_D,2,1,PCE,Port change detect enable,0,rw USB0_USBINTR_D,6,1,URE,USB reset enable,0,rw USB0_USBINTR_D,7,1,SRE,SOF received enable,0,rw USB0_USBINTR_D,8,1,SLE,Sleep enable,0,rw USB0_USBINTR_D,16,1,NAKE,NAK interrupt enable,0,rw USB0_USBINTR_H,0,1,UE,USB interrupt enable,0,rw USB0_USBINTR_H,1,1,UEE,USB error interrupt enable,0,rw USB0_USBINTR_H,2,1,PCE,Port change detect enable,0,rw USB0_USBINTR_H,3,1,FRE,Frame list rollover enable,0,rw USB0_USBINTR_H,5,1,AAE,Interrupt on asynchronous advance enable,0,rw USB0_USBINTR_H,7,1,SRE,SOF received enable,0, USB0_USBINTR_H,18,1,UAIE,USB host asynchronous interrupt enable,0,rw USB0_USBINTR_H,19,1,UPIA,USB host periodic interrupt enable,0,rw USB0_FRINDEX_D,0,3,FRINDEX2_0,Current micro frame number,,r USB0_FRINDEX_D,3,11,FRINDEX13_3,Current frame number of the last frame transmitted,,r USB0_FRINDEX_H,0,3,FRINDEX2_0,Current micro frame number,,rw USB0_FRINDEX_H,3,10,FRINDEX12_3,Frame list current index,,rw USB0_DEVICEADDR,24,1,USBADRA,Device address advance,0, USB0_DEVICEADDR,25,7,USBADR,USB device address,0,rw USB0_PERIODICLISTBASE,12,20,PERBASE31_12,Base Address (Low),,rw USB0_ENDPOINTLISTADDR,11,21,EPBASE31_11,Endpoint list pointer (low),,rw USB0_ASYNCLISTADDR,5,27,ASYBASE31_5,Link pointer (Low) LPL,,rw USB0_TTCTRL,24,7,TTHA,Hub address when FS or LS device are connected directly,,rw USB0_BURSTSIZE,0,8,RXPBURST,Programmable RX burst length,0x10,rw USB0_BURSTSIZE,8,8,TXPBURST,Programmable TX burst length,0x10,rw USB0_TXFILLTUNING,0,8,TXSCHOH,FIFO burst threshold,0x2,rw USB0_TXFILLTUNING,8,5,TXSCHEATLTH,Scheduler health counter,0x0,rw USB0_TXFILLTUNING,16,6,TXFIFOTHRES,Scheduler overhead,0x0,rw USB0_BINTERVAL,0,4,BINT,bInterval value,0x00,rw USB0_ENDPTNAK,0,6,EPRN,Rx endpoint NAK,0x00,rwc USB0_ENDPTNAK,16,6,EPTN,Tx endpoint NAK,0x00,rwc USB0_ENDPTNAKEN,0,6,EPRNE,Rx endpoint NAK enable,0x00,rw USB0_ENDPTNAKEN,16,6,EPTNE,Tx endpoint NAK,0x00,rw USB0_PORTSC1_D,0,1,CCS,Current connect status,0,r USB0_PORTSC1_D,2,1,PE,Port enable,1,r USB0_PORTSC1_D,3,1,PEC,Port enable/disable change,0,r USB0_PORTSC1_D,6,1,FPR,Force port resume,0,rw USB0_PORTSC1_D,7,1,SUSP,Suspend,0,r USB0_PORTSC1_D,8,1,PR,Port reset,0,r USB0_PORTSC1_D,9,1,HSP,High-speed status,0,r USB0_PORTSC1_D,14,2,PIC1_0,Port indicator control,0,rw USB0_PORTSC1_D,16,4,PTC3_0,Port test control,0,rw USB0_PORTSC1_D,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw USB0_PORTSC1_D,24,1,PFSC,Port force full speed connect,0,rw USB0_PORTSC1_D,26,2,PSPD,Port speed,0,r USB0_PORTSC1_H,0,1,CCS,Current connect status,0,rwc USB0_PORTSC1_H,1,1,CSC,Connect status change,0,rwc USB0_PORTSC1_H,2,1,PE,Port enable,0,rw USB0_PORTSC1_H,3,1,PEC,Port disable/enable change,0,rwc USB0_PORTSC1_H,4,1,OCA,Over-current active,0,r USB0_PORTSC1_H,5,1,OCC,Over-current change,0,rwc USB0_PORTSC1_H,6,1,FPR,Force port resume,0,rw USB0_PORTSC1_H,7,1,SUSP,Suspend,0,rw USB0_PORTSC1_H,8,1,PR,Port reset,0,rw USB0_PORTSC1_H,9,1,HSP,High-speed status,0,r USB0_PORTSC1_H,10,2,LS,Line status,0x3,r USB0_PORTSC1_H,12,1,PP,Port power control,0,rw USB0_PORTSC1_H,14,2,PIC1_0,Port indicator control,0,rw USB0_PORTSC1_H,16,4,PTC3_0,Port test control,0,rw USB0_PORTSC1_H,20,1,WKCN,Wake on connect enable (WKCNNT_E),0,rw USB0_PORTSC1_H,21,1,WKDC,Wake on disconnect enable (WKDSCNNT_E),0,rw USB0_PORTSC1_H,22,1,WKOC,Wake on over-current enable (WKOC_E),0,rw USB0_PORTSC1_H,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw USB0_PORTSC1_H,24,1,PFSC,Port force full speed connect,0,rw USB0_PORTSC1_H,26,2,PSPD,Port speed,0,r USB0_OTGSC,0,1,VD,VBUS_Discharge,0,rw USB0_OTGSC,1,1,VC,VBUS_Charge,0,rw USB0_OTGSC,2,1,HAAR,Hardware assist auto_reset,0,rw USB0_OTGSC,3,1,OT,OTG termination,0,rw USB0_OTGSC,4,1,DP,Data pulsing,0,rw USB0_OTGSC,5,1,IDPU,ID pull-up,1,rw USB0_OTGSC,6,1,HADP,Hardware assist data pulse,0,rw USB0_OTGSC,7,1,HABA,Hardware assist B-disconnect to A-connect,0,rw USB0_OTGSC,8,1,ID,USB ID,0,r USB0_OTGSC,9,1,AVV,A-VBUS valid,0,r USB0_OTGSC,10,1,ASV,A-session valid,0,r USB0_OTGSC,11,1,BSV,B-session valid,0,r USB0_OTGSC,12,1,BSE,B-session end,0,r USB0_OTGSC,13,1,MS1T,1 millisecond timer toggle,0,r USB0_OTGSC,14,1,DPS,Data bus pulsing status,0,r USB0_OTGSC,16,1,IDIS,USB ID interrupt status,0,rwc USB0_OTGSC,17,1,AVVIS,A-VBUS valid interrupt status,0,rwc USB0_OTGSC,18,1,ASVIS,A-Session valid interrupt status,0,rwc USB0_OTGSC,19,1,BSVIS,B-Session valid interrupt status,0,rwc USB0_OTGSC,20,1,BSEIS,B-Session end interrupt status,0,rwc USB0_OTGSC,21,1,MS1S,1 millisecond timer interrupt status,0,rwc USB0_OTGSC,22,1,DPIS,Data pulse interrupt status,0,rwc USB0_OTGSC,24,1,IDIE,USB ID interrupt enable,0,rw USB0_OTGSC,25,1,AVVIE,A-VBUS valid interrupt enable,0,rw USB0_OTGSC,26,1,ASVIE,A-session valid interrupt enable,0,rw USB0_OTGSC,27,1,BSVIE,B-session valid interrupt enable,0,rw USB0_OTGSC,28,1,BSEIE,B-session end interrupt enable,0,rw USB0_OTGSC,29,1,MS1E,1 millisecond timer interrupt enable,0,rw USB0_OTGSC,30,1,DPIE,Data pulse interrupt enable,0,rw USB0_USBMODE_D,0,2,CM1_0,Controller mode,0,rwo USB0_USBMODE_D,2,1,ES,Endian select,0,rw USB0_USBMODE_D,3,1,SLOM,Setup Lockout mode,0,rw USB0_USBMODE_D,4,1,SDIS,Setup Lockout mode,0,rw USB0_USBMODE_H,0,2,CM,Controller mode,0,rwo USB0_USBMODE_H,2,1,ES,Endian select,0,rw USB0_USBMODE_H,4,1,SDIS,Stream disable mode,0,rw USB0_USBMODE_H,5,1,VBPS,VBUS power select,0,rwo USB0_ENDPTSETUPSTAT,0,6,ENDPTSETUPSTAT,Setup endpoint status for logical endpoints 0 to 5,0,rwc USB0_ENDPTPRIME,0,6,PERB,Prime endpoint receive buffer for physical OUT endpoints 5 to 0,0,rws USB0_ENDPTPRIME,16,6,PETB,Prime endpoint transmit buffer for physical IN endpoints 5 to 0,0,rws USB0_ENDPTFLUSH,0,6,FERB,Flush endpoint receive buffer for physical OUT endpoints 5 to 0,0,rwc USB0_ENDPTFLUSH,16,6,FETB,Flush endpoint transmit buffer for physical IN endpoints 5 to 0,0,rwc USB0_ENDPTSTAT,0,6,ERBR,Endpoint receive buffer ready for physical OUT endpoints 5 to 0,0,r USB0_ENDPTSTAT,16,6,ETBR,Endpoint transmit buffer ready for physical IN endpoints 3 to 0,0,r USB0_ENDPTCOMPLETE,0,6,ERCE,Endpoint receive complete event for physical OUT endpoints 5 to 0,0,rwc USB0_ENDPTCOMPLETE,16,6,ETCE,Endpoint transmit complete event for physical IN endpoints 5 to 0,0,rwc USB0_ENDPTCTRL0,0,1,RXS,Rx endpoint stall,0,rw USB0_ENDPTCTRL0,2,2,RXT1_0,Endpoint type,0,rw USB0_ENDPTCTRL0,7,1,RXE,Rx endpoint enable,1,r USB0_ENDPTCTRL0,16,1,TXS,Tx endpoint stall,,rw USB0_ENDPTCTRL0,18,2,TXT1_0,Endpoint type,0,r USB0_ENDPTCTRL0,23,1,TXE,Tx endpoint enable,1,r USB0_ENDPTCTRL1,0,1,RXS,Rx endpoint stall,0,rw USB0_ENDPTCTRL1,2,2,RXT,Endpoint type,0,rw USB0_ENDPTCTRL1,5,1,RXI,Rx data toggle inhibit,0,rw USB0_ENDPTCTRL1,6,1,RXR,Rx data toggle reset,0,ws USB0_ENDPTCTRL1,7,1,RXE,Rx endpoint enable,0,rw USB0_ENDPTCTRL1,16,1,TXS,Tx endpoint stall,0,rw USB0_ENDPTCTRL1,18,2,TXT1_0,Tx Endpoint type,0,r USB0_ENDPTCTRL1,21,1,TXI,Tx data toggle inhibit,0,rw USB0_ENDPTCTRL1,22,1,TXR,Tx data toggle reset,1,ws USB0_ENDPTCTRL1,23,1,TXE,Tx endpoint enable,0,r USB0_ENDPTCTRL2,0,1,RXS,Rx endpoint stall,0,rw USB0_ENDPTCTRL2,2,2,RXT,Endpoint type,0,rw USB0_ENDPTCTRL2,5,1,RXI,Rx data toggle inhibit,0,rw USB0_ENDPTCTRL2,6,1,RXR,Rx data toggle reset,0,ws USB0_ENDPTCTRL2,7,1,RXE,Rx endpoint enable,0,rw USB0_ENDPTCTRL2,16,1,TXS,Tx endpoint stall,0,rw USB0_ENDPTCTRL2,18,2,TXT1_0,Tx Endpoint type,0,r USB0_ENDPTCTRL2,21,1,TXI,Tx data toggle inhibit,0,rw USB0_ENDPTCTRL2,22,1,TXR,Tx data toggle reset,1,ws USB0_ENDPTCTRL2,23,1,TXE,Tx endpoint enable,0,r USB0_ENDPTCTRL3,0,1,RXS,Rx endpoint stall,0,rw USB0_ENDPTCTRL3,2,2,RXT,Endpoint type,0,rw USB0_ENDPTCTRL3,5,1,RXI,Rx data toggle inhibit,0,rw USB0_ENDPTCTRL3,6,1,RXR,Rx data toggle reset,0,ws USB0_ENDPTCTRL3,7,1,RXE,Rx endpoint enable,0,rw USB0_ENDPTCTRL3,16,1,TXS,Tx endpoint stall,0,rw USB0_ENDPTCTRL3,18,2,TXT1_0,Tx Endpoint type,0,r USB0_ENDPTCTRL3,21,1,TXI,Tx data toggle inhibit,0,rw USB0_ENDPTCTRL3,22,1,TXR,Tx data toggle reset,1,ws USB0_ENDPTCTRL3,23,1,TXE,Tx endpoint enable,0,r USB0_ENDPTCTRL4,0,1,RXS,Rx endpoint stall,0,rw USB0_ENDPTCTRL4,2,2,RXT,Endpoint type,0,rw USB0_ENDPTCTRL4,5,1,RXI,Rx data toggle inhibit,0,rw USB0_ENDPTCTRL4,6,1,RXR,Rx data toggle reset,0,ws USB0_ENDPTCTRL4,7,1,RXE,Rx endpoint enable,0,rw USB0_ENDPTCTRL4,16,1,TXS,Tx endpoint stall,0,rw USB0_ENDPTCTRL4,18,2,TXT1_0,Tx Endpoint type,0,r USB0_ENDPTCTRL4,21,1,TXI,Tx data toggle inhibit,0,rw USB0_ENDPTCTRL4,22,1,TXR,Tx data toggle reset,1,ws USB0_ENDPTCTRL4,23,1,TXE,Tx endpoint enable,0,r USB0_ENDPTCTRL5,0,1,RXS,Rx endpoint stall,0,rw USB0_ENDPTCTRL5,2,2,RXT,Endpoint type,0,rw USB0_ENDPTCTRL5,5,1,RXI,Rx data toggle inhibit,0,rw USB0_ENDPTCTRL5,6,1,RXR,Rx data toggle reset,0,ws USB0_ENDPTCTRL5,7,1,RXE,Rx endpoint enable,0,rw USB0_ENDPTCTRL5,16,1,TXS,Tx endpoint stall,0,rw USB0_ENDPTCTRL5,18,2,TXT1_0,Tx Endpoint type,0,r USB0_ENDPTCTRL5,21,1,TXI,Tx data toggle inhibit,0,rw USB0_ENDPTCTRL5,22,1,TXR,Tx data toggle reset,1,ws USB0_ENDPTCTRL5,23,1,TXE,Tx endpoint enable,0,r hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/usb.yaml000066400000000000000000000753541435536612600230710ustar00rootroot00000000000000!!omap - USB0_CAPLENGTH: fields: !!omap - CAPLENGTH: access: r description: Indicates offset to add to the register base address at the beginning of the Operational Register lsb: 0 reset_value: '0x40' width: 8 - HCIVERSION: access: r description: BCD encoding of the EHCI revision number supported by this host controller lsb: 8 reset_value: '0x100' width: 16 - USB0_HCSPARAMS: fields: !!omap - N_PORTS: access: r description: Number of downstream ports lsb: 0 reset_value: '0x1' width: 4 - PPC: access: r description: Port Power Control lsb: 4 reset_value: '0x1' width: 1 - N_PCC: access: r description: Number of Ports per Companion Controller lsb: 8 reset_value: '0x0' width: 4 - N_CC: access: r description: Number of Companion Controller lsb: 12 reset_value: '0x0' width: 4 - PI: access: r description: Port indicators lsb: 16 reset_value: '0x1' width: 1 - N_PTT: access: r description: Number of Ports per Transaction Translator lsb: 20 reset_value: '0x0' width: 4 - N_TT: access: r description: Number of Transaction Translators lsb: 24 reset_value: '0x0' width: 4 - USB0_HCCPARAMS: fields: !!omap - ADC: access: r description: 64-bit Addressing Capability lsb: 0 reset_value: '0' width: 1 - PFL: access: r description: Programmable Frame List Flag lsb: 1 reset_value: '1' width: 1 - ASP: access: r description: Asynchronous Schedule Park Capability lsb: 2 reset_value: '1' width: 1 - IST: access: r description: Isochronous Scheduling Threshold lsb: 4 reset_value: '0' width: 4 - EECP: access: r description: EHCI Extended Capabilities Pointer lsb: 8 reset_value: '0' width: 4 - USB0_DCCPARAMS: fields: !!omap - DEN: access: r description: Device Endpoint Number lsb: 0 reset_value: '0x4' width: 5 - DC: access: r description: Device Capable lsb: 7 reset_value: '0x1' width: 1 - HC: access: r description: Host Capable lsb: 8 reset_value: '0x1' width: 1 - USB0_USBCMD_D: fields: !!omap - RS: access: rw description: Run/Stop lsb: 0 reset_value: '0' width: 1 - RST: access: rw description: Controller reset lsb: 1 reset_value: '0' width: 1 - SUTW: access: rw description: Setup trip wire lsb: 13 reset_value: '0' width: 1 - ATDTW: access: rw description: Add dTD trip wire lsb: 14 reset_value: '0' width: 1 - ITC: access: rw description: Interrupt threshold control lsb: 16 reset_value: '0x8' width: 8 - USB0_USBCMD_H: fields: !!omap - RS: access: rw description: Run/Stop lsb: 0 reset_value: '0' width: 1 - RST: access: rw description: Controller reset lsb: 1 reset_value: '0' width: 1 - FS0: access: '' description: Bit 0 of the Frame List Size bits lsb: 2 reset_value: '0' width: 1 - FS1: access: '' description: Bit 1 of the Frame List Size bits lsb: 3 reset_value: '0' width: 1 - PSE: access: rw description: This bit controls whether the host controller skips processing the periodic schedule lsb: 4 reset_value: '0' width: 1 - ASE: access: rw description: This bit controls whether the host controller skips processing the asynchronous schedule lsb: 5 reset_value: '0' width: 1 - IAA: access: rw description: This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule lsb: 6 reset_value: '0' width: 1 - ASP1_0: access: rw description: Asynchronous schedule park mode lsb: 8 reset_value: '0x3' width: 2 - ASPE: access: rw description: Asynchronous Schedule Park Mode Enable lsb: 11 reset_value: '1' width: 1 - FS2: access: '' description: Bit 2 of the Frame List Size bits lsb: 15 reset_value: '0' width: 1 - ITC: access: rw description: Interrupt threshold control lsb: 16 reset_value: '0x8' width: 8 - USB0_USBSTS_D: fields: !!omap - UI: access: rwc description: USB interrupt lsb: 0 reset_value: '0' width: 1 - UEI: access: rwc description: USB error interrupt lsb: 1 reset_value: '0' width: 1 - PCI: access: rwc description: Port change detect lsb: 2 reset_value: '0' width: 1 - URI: access: rwc description: USB reset received lsb: 6 reset_value: '0' width: 1 - SRI: access: rwc description: SOF received lsb: 7 reset_value: '0' width: 1 - SLI: access: rwc description: DCSuspend lsb: 8 reset_value: '0' width: 1 - NAKI: access: r description: NAK interrupt bit lsb: 16 reset_value: '0' width: 1 - USB0_USBSTS_H: fields: !!omap - UI: access: rwc description: USB interrupt lsb: 0 reset_value: '0' width: 1 - UEI: access: rwc description: USB error interrupt lsb: 1 reset_value: '0' width: 1 - PCI: access: rwc description: Port change detect lsb: 2 reset_value: '0' width: 1 - FRI: access: rwc description: Frame list roll-over lsb: 3 reset_value: '0' width: 1 - AAI: access: rwc description: Interrupt on async advance lsb: 5 reset_value: '0' width: 1 - SRI: access: rwc description: SOF received lsb: 7 reset_value: '0' width: 1 - HCH: access: r description: HCHalted lsb: 12 reset_value: '1' width: 1 - RCL: access: r description: Reclamation lsb: 13 reset_value: '0' width: 1 - PS: access: r description: Periodic schedule status lsb: 14 reset_value: '0' width: 1 - AS: access: '' description: Asynchronous schedule status lsb: 15 reset_value: '0' width: 1 - UAI: access: rwc description: USB host asynchronous interrupt (USBHSTASYNCINT) lsb: 18 reset_value: '0' width: 1 - UPI: access: rwc description: USB host periodic interrupt (USBHSTPERINT) lsb: 19 reset_value: '0' width: 1 - USB0_USBINTR_D: fields: !!omap - UE: access: rw description: USB interrupt enable lsb: 0 reset_value: '0' width: 1 - UEE: access: rw description: USB error interrupt enable lsb: 1 reset_value: '0' width: 1 - PCE: access: rw description: Port change detect enable lsb: 2 reset_value: '0' width: 1 - URE: access: rw description: USB reset enable lsb: 6 reset_value: '0' width: 1 - SRE: access: rw description: SOF received enable lsb: 7 reset_value: '0' width: 1 - SLE: access: rw description: Sleep enable lsb: 8 reset_value: '0' width: 1 - NAKE: access: rw description: NAK interrupt enable lsb: 16 reset_value: '0' width: 1 - USB0_USBINTR_H: fields: !!omap - UE: access: rw description: USB interrupt enable lsb: 0 reset_value: '0' width: 1 - UEE: access: rw description: USB error interrupt enable lsb: 1 reset_value: '0' width: 1 - PCE: access: rw description: Port change detect enable lsb: 2 reset_value: '0' width: 1 - FRE: access: rw description: Frame list rollover enable lsb: 3 reset_value: '0' width: 1 - AAE: access: rw description: Interrupt on asynchronous advance enable lsb: 5 reset_value: '0' width: 1 - SRE: access: '' description: SOF received enable lsb: 7 reset_value: '0' width: 1 - UAIE: access: rw description: USB host asynchronous interrupt enable lsb: 18 reset_value: '0' width: 1 - UPIA: access: rw description: USB host periodic interrupt enable lsb: 19 reset_value: '0' width: 1 - USB0_FRINDEX_D: fields: !!omap - FRINDEX2_0: access: r description: Current micro frame number lsb: 0 reset_value: '' width: 3 - FRINDEX13_3: access: r description: Current frame number of the last frame transmitted lsb: 3 reset_value: '' width: 11 - USB0_FRINDEX_H: fields: !!omap - FRINDEX2_0: access: rw description: Current micro frame number lsb: 0 reset_value: '' width: 3 - FRINDEX12_3: access: rw description: Frame list current index lsb: 3 reset_value: '' width: 10 - USB0_DEVICEADDR: fields: !!omap - USBADRA: access: '' description: Device address advance lsb: 24 reset_value: '0' width: 1 - USBADR: access: rw description: USB device address lsb: 25 reset_value: '0' width: 7 - USB0_PERIODICLISTBASE: fields: !!omap - PERBASE31_12: access: rw description: Base Address (Low) lsb: 12 reset_value: '' width: 20 - USB0_ENDPOINTLISTADDR: fields: !!omap - EPBASE31_11: access: rw description: Endpoint list pointer (low) lsb: 11 reset_value: '' width: 21 - USB0_ASYNCLISTADDR: fields: !!omap - ASYBASE31_5: access: rw description: Link pointer (Low) LPL lsb: 5 reset_value: '' width: 27 - USB0_TTCTRL: fields: !!omap - TTHA: access: rw description: Hub address when FS or LS device are connected directly lsb: 24 reset_value: '' width: 7 - USB0_BURSTSIZE: fields: !!omap - RXPBURST: access: rw description: Programmable RX burst length lsb: 0 reset_value: '0x10' width: 8 - TXPBURST: access: rw description: Programmable TX burst length lsb: 8 reset_value: '0x10' width: 8 - USB0_TXFILLTUNING: fields: !!omap - TXSCHOH: access: rw description: FIFO burst threshold lsb: 0 reset_value: '0x2' width: 8 - TXSCHEATLTH: access: rw description: Scheduler health counter lsb: 8 reset_value: '0x0' width: 5 - TXFIFOTHRES: access: rw description: Scheduler overhead lsb: 16 reset_value: '0x0' width: 6 - USB0_BINTERVAL: fields: !!omap - BINT: access: rw description: bInterval value lsb: 0 reset_value: '0x00' width: 4 - USB0_ENDPTNAK: fields: !!omap - EPRN: access: rwc description: Rx endpoint NAK lsb: 0 reset_value: '0x00' width: 6 - EPTN: access: rwc description: Tx endpoint NAK lsb: 16 reset_value: '0x00' width: 6 - USB0_ENDPTNAKEN: fields: !!omap - EPRNE: access: rw description: Rx endpoint NAK enable lsb: 0 reset_value: '0x00' width: 6 - EPTNE: access: rw description: Tx endpoint NAK lsb: 16 reset_value: '0x00' width: 6 - USB0_PORTSC1_D: fields: !!omap - CCS: access: r description: Current connect status lsb: 0 reset_value: '0' width: 1 - PE: access: r description: Port enable lsb: 2 reset_value: '1' width: 1 - PEC: access: r description: Port enable/disable change lsb: 3 reset_value: '0' width: 1 - FPR: access: rw description: Force port resume lsb: 6 reset_value: '0' width: 1 - SUSP: access: r description: Suspend lsb: 7 reset_value: '0' width: 1 - PR: access: r description: Port reset lsb: 8 reset_value: '0' width: 1 - HSP: access: r description: High-speed status lsb: 9 reset_value: '0' width: 1 - PIC1_0: access: rw description: Port indicator control lsb: 14 reset_value: '0' width: 2 - PTC3_0: access: rw description: Port test control lsb: 16 reset_value: '0' width: 4 - PHCD: access: rw description: PHY low power suspend - clock disable (PLPSCD) lsb: 23 reset_value: '0' width: 1 - PFSC: access: rw description: Port force full speed connect lsb: 24 reset_value: '0' width: 1 - PSPD: access: r description: Port speed lsb: 26 reset_value: '0' width: 2 - USB0_PORTSC1_H: fields: !!omap - CCS: access: rwc description: Current connect status lsb: 0 reset_value: '0' width: 1 - CSC: access: rwc description: Connect status change lsb: 1 reset_value: '0' width: 1 - PE: access: rw description: Port enable lsb: 2 reset_value: '0' width: 1 - PEC: access: rwc description: Port disable/enable change lsb: 3 reset_value: '0' width: 1 - OCA: access: r description: Over-current active lsb: 4 reset_value: '0' width: 1 - OCC: access: rwc description: Over-current change lsb: 5 reset_value: '0' width: 1 - FPR: access: rw description: Force port resume lsb: 6 reset_value: '0' width: 1 - SUSP: access: rw description: Suspend lsb: 7 reset_value: '0' width: 1 - PR: access: rw description: Port reset lsb: 8 reset_value: '0' width: 1 - HSP: access: r description: High-speed status lsb: 9 reset_value: '0' width: 1 - LS: access: r description: Line status lsb: 10 reset_value: '0x3' width: 2 - PP: access: rw description: Port power control lsb: 12 reset_value: '0' width: 1 - PIC1_0: access: rw description: Port indicator control lsb: 14 reset_value: '0' width: 2 - PTC3_0: access: rw description: Port test control lsb: 16 reset_value: '0' width: 4 - WKCN: access: rw description: Wake on connect enable (WKCNNT_E) lsb: 20 reset_value: '0' width: 1 - WKDC: access: rw description: Wake on disconnect enable (WKDSCNNT_E) lsb: 21 reset_value: '0' width: 1 - WKOC: access: rw description: Wake on over-current enable (WKOC_E) lsb: 22 reset_value: '0' width: 1 - PHCD: access: rw description: PHY low power suspend - clock disable (PLPSCD) lsb: 23 reset_value: '0' width: 1 - PFSC: access: rw description: Port force full speed connect lsb: 24 reset_value: '0' width: 1 - PSPD: access: r description: Port speed lsb: 26 reset_value: '0' width: 2 - USB0_OTGSC: fields: !!omap - VD: access: rw description: VBUS_Discharge lsb: 0 reset_value: '0' width: 1 - VC: access: rw description: VBUS_Charge lsb: 1 reset_value: '0' width: 1 - HAAR: access: rw description: Hardware assist auto_reset lsb: 2 reset_value: '0' width: 1 - OT: access: rw description: OTG termination lsb: 3 reset_value: '0' width: 1 - DP: access: rw description: Data pulsing lsb: 4 reset_value: '0' width: 1 - IDPU: access: rw description: ID pull-up lsb: 5 reset_value: '1' width: 1 - HADP: access: rw description: Hardware assist data pulse lsb: 6 reset_value: '0' width: 1 - HABA: access: rw description: Hardware assist B-disconnect to A-connect lsb: 7 reset_value: '0' width: 1 - ID: access: r description: USB ID lsb: 8 reset_value: '0' width: 1 - AVV: access: r description: A-VBUS valid lsb: 9 reset_value: '0' width: 1 - ASV: access: r description: A-session valid lsb: 10 reset_value: '0' width: 1 - BSV: access: r description: B-session valid lsb: 11 reset_value: '0' width: 1 - BSE: access: r description: B-session end lsb: 12 reset_value: '0' width: 1 - MS1T: access: r description: 1 millisecond timer toggle lsb: 13 reset_value: '0' width: 1 - DPS: access: r description: Data bus pulsing status lsb: 14 reset_value: '0' width: 1 - IDIS: access: rwc description: USB ID interrupt status lsb: 16 reset_value: '0' width: 1 - AVVIS: access: rwc description: A-VBUS valid interrupt status lsb: 17 reset_value: '0' width: 1 - ASVIS: access: rwc description: A-Session valid interrupt status lsb: 18 reset_value: '0' width: 1 - BSVIS: access: rwc description: B-Session valid interrupt status lsb: 19 reset_value: '0' width: 1 - BSEIS: access: rwc description: B-Session end interrupt status lsb: 20 reset_value: '0' width: 1 - MS1S: access: rwc description: 1 millisecond timer interrupt status lsb: 21 reset_value: '0' width: 1 - DPIS: access: rwc description: Data pulse interrupt status lsb: 22 reset_value: '0' width: 1 - IDIE: access: rw description: USB ID interrupt enable lsb: 24 reset_value: '0' width: 1 - AVVIE: access: rw description: A-VBUS valid interrupt enable lsb: 25 reset_value: '0' width: 1 - ASVIE: access: rw description: A-session valid interrupt enable lsb: 26 reset_value: '0' width: 1 - BSVIE: access: rw description: B-session valid interrupt enable lsb: 27 reset_value: '0' width: 1 - BSEIE: access: rw description: B-session end interrupt enable lsb: 28 reset_value: '0' width: 1 - MS1E: access: rw description: 1 millisecond timer interrupt enable lsb: 29 reset_value: '0' width: 1 - DPIE: access: rw description: Data pulse interrupt enable lsb: 30 reset_value: '0' width: 1 - USB0_USBMODE_D: fields: !!omap - CM1_0: access: rwo description: Controller mode lsb: 0 reset_value: '0' width: 2 - ES: access: rw description: Endian select lsb: 2 reset_value: '0' width: 1 - SLOM: access: rw description: Setup Lockout mode lsb: 3 reset_value: '0' width: 1 - SDIS: access: rw description: Setup Lockout mode lsb: 4 reset_value: '0' width: 1 - USB0_USBMODE_H: fields: !!omap - CM: access: rwo description: Controller mode lsb: 0 reset_value: '0' width: 2 - ES: access: rw description: Endian select lsb: 2 reset_value: '0' width: 1 - SDIS: access: rw description: Stream disable mode lsb: 4 reset_value: '0' width: 1 - VBPS: access: rwo description: VBUS power select lsb: 5 reset_value: '0' width: 1 - USB0_ENDPTSETUPSTAT: fields: !!omap - ENDPTSETUPSTAT: access: rwc description: Setup endpoint status for logical endpoints 0 to 5 lsb: 0 reset_value: '0' width: 6 - USB0_ENDPTPRIME: fields: !!omap - PERB: access: rws description: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 lsb: 0 reset_value: '0' width: 6 - PETB: access: rws description: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 lsb: 16 reset_value: '0' width: 6 - USB0_ENDPTFLUSH: fields: !!omap - FERB: access: rwc description: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 lsb: 0 reset_value: '0' width: 6 - FETB: access: rwc description: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 lsb: 16 reset_value: '0' width: 6 - USB0_ENDPTSTAT: fields: !!omap - ERBR: access: r description: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 lsb: 0 reset_value: '0' width: 6 - ETBR: access: r description: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 lsb: 16 reset_value: '0' width: 6 - USB0_ENDPTCOMPLETE: fields: !!omap - ERCE: access: rwc description: Endpoint receive complete event for physical OUT endpoints 5 to 0 lsb: 0 reset_value: '0' width: 6 - ETCE: access: rwc description: Endpoint transmit complete event for physical IN endpoints 5 to 0 lsb: 16 reset_value: '0' width: 6 - USB0_ENDPTCTRL0: fields: !!omap - RXS: access: rw description: Rx endpoint stall lsb: 0 reset_value: '0' width: 1 - RXT1_0: access: rw description: Endpoint type lsb: 2 reset_value: '0' width: 2 - RXE: access: r description: Rx endpoint enable lsb: 7 reset_value: '1' width: 1 - TXS: access: rw description: Tx endpoint stall lsb: 16 reset_value: '' width: 1 - TXT1_0: access: r description: Endpoint type lsb: 18 reset_value: '0' width: 2 - TXE: access: r description: Tx endpoint enable lsb: 23 reset_value: '1' width: 1 - USB0_ENDPTCTRL1: fields: !!omap - RXS: access: rw description: Rx endpoint stall lsb: 0 reset_value: '0' width: 1 - RXT: access: rw description: Endpoint type lsb: 2 reset_value: '0' width: 2 - RXI: access: rw description: Rx data toggle inhibit lsb: 5 reset_value: '0' width: 1 - RXR: access: ws description: Rx data toggle reset lsb: 6 reset_value: '0' width: 1 - RXE: access: rw description: Rx endpoint enable lsb: 7 reset_value: '0' width: 1 - TXS: access: rw description: Tx endpoint stall lsb: 16 reset_value: '0' width: 1 - TXT1_0: access: r description: Tx Endpoint type lsb: 18 reset_value: '0' width: 2 - TXI: access: rw description: Tx data toggle inhibit lsb: 21 reset_value: '0' width: 1 - TXR: access: ws description: Tx data toggle reset lsb: 22 reset_value: '1' width: 1 - TXE: access: r description: Tx endpoint enable lsb: 23 reset_value: '0' width: 1 - USB0_ENDPTCTRL2: fields: !!omap - RXS: access: rw description: Rx endpoint stall lsb: 0 reset_value: '0' width: 1 - RXT: access: rw description: Endpoint type lsb: 2 reset_value: '0' width: 2 - RXI: access: rw description: Rx data toggle inhibit lsb: 5 reset_value: '0' width: 1 - RXR: access: ws description: Rx data toggle reset lsb: 6 reset_value: '0' width: 1 - RXE: access: rw description: Rx endpoint enable lsb: 7 reset_value: '0' width: 1 - TXS: access: rw description: Tx endpoint stall lsb: 16 reset_value: '0' width: 1 - TXT1_0: access: r description: Tx Endpoint type lsb: 18 reset_value: '0' width: 2 - TXI: access: rw description: Tx data toggle inhibit lsb: 21 reset_value: '0' width: 1 - TXR: access: ws description: Tx data toggle reset lsb: 22 reset_value: '1' width: 1 - TXE: access: r description: Tx endpoint enable lsb: 23 reset_value: '0' width: 1 - USB0_ENDPTCTRL3: fields: !!omap - RXS: access: rw description: Rx endpoint stall lsb: 0 reset_value: '0' width: 1 - RXT: access: rw description: Endpoint type lsb: 2 reset_value: '0' width: 2 - RXI: access: rw description: Rx data toggle inhibit lsb: 5 reset_value: '0' width: 1 - RXR: access: ws description: Rx data toggle reset lsb: 6 reset_value: '0' width: 1 - RXE: access: rw description: Rx endpoint enable lsb: 7 reset_value: '0' width: 1 - TXS: access: rw description: Tx endpoint stall lsb: 16 reset_value: '0' width: 1 - TXT1_0: access: r description: Tx Endpoint type lsb: 18 reset_value: '0' width: 2 - TXI: access: rw description: Tx data toggle inhibit lsb: 21 reset_value: '0' width: 1 - TXR: access: ws description: Tx data toggle reset lsb: 22 reset_value: '1' width: 1 - TXE: access: r description: Tx endpoint enable lsb: 23 reset_value: '0' width: 1 - USB0_ENDPTCTRL4: fields: !!omap - RXS: access: rw description: Rx endpoint stall lsb: 0 reset_value: '0' width: 1 - RXT: access: rw description: Endpoint type lsb: 2 reset_value: '0' width: 2 - RXI: access: rw description: Rx data toggle inhibit lsb: 5 reset_value: '0' width: 1 - RXR: access: ws description: Rx data toggle reset lsb: 6 reset_value: '0' width: 1 - RXE: access: rw description: Rx endpoint enable lsb: 7 reset_value: '0' width: 1 - TXS: access: rw description: Tx endpoint stall lsb: 16 reset_value: '0' width: 1 - TXT1_0: access: r description: Tx Endpoint type lsb: 18 reset_value: '0' width: 2 - TXI: access: rw description: Tx data toggle inhibit lsb: 21 reset_value: '0' width: 1 - TXR: access: ws description: Tx data toggle reset lsb: 22 reset_value: '1' width: 1 - TXE: access: r description: Tx endpoint enable lsb: 23 reset_value: '0' width: 1 - USB0_ENDPTCTRL5: fields: !!omap - RXS: access: rw description: Rx endpoint stall lsb: 0 reset_value: '0' width: 1 - RXT: access: rw description: Endpoint type lsb: 2 reset_value: '0' width: 2 - RXI: access: rw description: Rx data toggle inhibit lsb: 5 reset_value: '0' width: 1 - RXR: access: ws description: Rx data toggle reset lsb: 6 reset_value: '0' width: 1 - RXE: access: rw description: Rx endpoint enable lsb: 7 reset_value: '0' width: 1 - TXS: access: rw description: Tx endpoint stall lsb: 16 reset_value: '0' width: 1 - TXT1_0: access: r description: Tx Endpoint type lsb: 18 reset_value: '0' width: 2 - TXI: access: rw description: Tx data toggle inhibit lsb: 21 reset_value: '0' width: 1 - TXR: access: ws description: Tx data toggle reset lsb: 22 reset_value: '1' width: 1 - TXE: access: r description: Tx endpoint enable lsb: 23 reset_value: '0' width: 1 hackrf-0.0~git20230104.cfc2f34/scripts/data/lpc43xx/yaml_odict.py000066400000000000000000000057651435536612600241110ustar00rootroot00000000000000import yaml from collections import OrderedDict def construct_odict(load, node): """This is the same as SafeConstructor.construct_yaml_omap(), except the data type is changed to OrderedDict() and setitem is used instead of append in the loop. >>> yaml.load(''' ... !!omap ... - foo: bar ... - mumble: quux ... - baz: gorp ... ''') OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')]) >>> yaml.load('''!!omap [ foo: bar, mumble: quux, baz : gorp ]''') OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')]) """ omap = OrderedDict() yield omap if not isinstance(node, yaml.SequenceNode): raise yaml.constructor.ConstructorError( "while constructing an ordered map", node.start_mark, "expected a sequence, but found %s" % node.id, node.start_mark ) for subnode in node.value: if not isinstance(subnode, yaml.MappingNode): raise yaml.constructor.ConstructorError( "while constructing an ordered map", node.start_mark, "expected a mapping of length 1, but found %s" % subnode.id, subnode.start_mark ) if len(subnode.value) != 1: raise yaml.constructor.ConstructorError( "while constructing an ordered map", node.start_mark, "expected a single mapping item, but found %d items" % len(subnode.value), subnode.start_mark ) key_node, value_node = subnode.value[0] key = load.construct_object(key_node) value = load.construct_object(value_node) omap[key] = value yaml.add_constructor(u'tag:yaml.org,2002:omap', construct_odict) def repr_pairs(dump, tag, sequence, flow_style=None): """This is the same code as BaseRepresenter.represent_sequence(), but the value passed to dump.represent_data() in the loop is a dictionary instead of a tuple.""" value = [] node = yaml.SequenceNode(tag, value, flow_style=flow_style) if dump.alias_key is not None: dump.represented_objects[dump.alias_key] = node best_style = True for (key, val) in sequence: item = dump.represent_data({key: val}) if not (isinstance(item, yaml.ScalarNode) and not item.style): best_style = False value.append(item) if flow_style is None: if dump.default_flow_style is not None: node.flow_style = dump.default_flow_style else: node.flow_style = best_style return node def repr_odict(dumper, data): """ >>> data = OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')]) >>> yaml.dump(data, default_flow_style=False) '!!omap\\n- foo: bar\\n- mumble: quux\\n- baz: gorp\\n' >>> yaml.dump(data, default_flow_style=True) '!!omap [foo: bar, mumble: quux, baz: gorp]\\n' """ return repr_pairs(dumper, u'tag:yaml.org,2002:omap', data.iteritems()) yaml.add_representer(OrderedDict, repr_odict) hackrf-0.0~git20230104.cfc2f34/scripts/genlink.awk000066400000000000000000000007701435536612600213170ustar00rootroot00000000000000# This program converts chip name to the series of definitions for make of # automatic linker script. # # Copyright (C) 2013 Frantisek Burian # Copyright (C) 2013 Werner Almesberger # BEGIN { PAT = tolower(PAT); } !/^#/{ tmp = "^"$1"$"; gsub(/?/, ".", tmp); gsub(/*/, ".*", tmp); gsub(/+/, ".+", tmp); tolower(tmp); if (PAT ~ tmp) { if ($2 != "+") PAT=$2; $1=""; $2=""; for (i = 3; i <= NF; i = i + 1) $i = "-D"$i; print; if (PAT=="END") exit; } } hackrf-0.0~git20230104.cfc2f34/scripts/irq2nvic_h000077500000000000000000000127051435536612600211570ustar00rootroot00000000000000#!/usr/bin/env python3 # This file is part of the libopencm3 project. # # Copyright (C) 2012 chrysn # # This library is free software: you can redistribute it and/or modify # it under the terms of the GNU Lesser General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # This library is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public License # along with this library. If not, see . """Generate an nvic.h header from a small YAML file describing the interrupt numbers. Code generation is chosen here because the resulting C code needs to be very repetetive (definition of the IRQ numbers, function prototypes, weak fallback definition and vector table definition), all being very repetitive. No portable method to achive the same thing with C preprocessor is known to the author. (Neither is any non-portable method, for that matter.)""" import sys import os import os.path import yaml template_nvic_h = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. */ #ifndef {includeguard} #define {includeguard} #include /** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} @ingroup CM3_nvic_defines @{{*/ {irqdefinitions} #define NVIC_IRQ_COUNT {irqcount} /**@}}*/ /** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} @ingroup CM3_nvic_isrprototypes @{{*/ BEGIN_DECLS {isrprototypes} END_DECLS /**@}}*/ #endif /* {includeguard} */ ''' template_vector_nvic_c = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. * * This part needs to get included in the compilation unit where * blocking_handler gets defined due to the way #pragma works. */ /** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} @ingroup CM3_nvic_isrpragmas @{{*/ {isrpragmas} /**@}}*/ /* Initialization template for the interrupt vector table. This definition is * used by the startup code generator (vector.c) to set the initial values for * the interrupt handling routines to the chip family specific _isr weak * symbols. */ #define IRQ_HANDLERS \\ {vectortableinitialization} ''' template_cmsis_h = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. * * These definitions bend every interrupt handler that is defined CMSIS style * to the weak symbol exported by libopenmc3. */ {cmsisbends} ''' def convert(infile, outfile_nvic, outfile_vectornvic, outfile_cmsis): data = yaml.safe_load(infile) irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) irqnames = [v for (k,v) in irq2name] if isinstance(data['irqs'], list): data['irqcount'] = len(irq2name) else: data['irqcount'] = max(data['irqs'].keys()) + 1 data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) data['cmsisbends'] = "\n".join("#define %s_IRQHandler %s_isr"%(name.upper(), name.lower()) for name in irqnames) outfile_nvic.write(template_nvic_h.format(**data)) outfile_vectornvic.write(template_vector_nvic_c.format(**data)) outfile_cmsis.write(template_cmsis_h.format(**data)) def makeparentdir(filename): try: os.makedirs(os.path.dirname(filename)) except OSError: # where is my 'mkdir -p'? pass def needs_update(infiles, outfiles): timestamp = lambda filename: os.stat(filename).st_mtime return any(not os.path.exists(o) for o in outfiles) or max(map(timestamp, infiles)) > min(map(timestamp, outfiles)) def main(): if sys.argv[1] == '--remove': remove = True del sys.argv[1] else: remove = False infile = sys.argv[1] if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'): raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml") nvic_h = infile.replace('irq.yaml', 'nvic.h') vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c') cmsis = infile.replace('irq.yaml', 'irqhandlers.h').replace('/libopencm3/', '/libopencmsis/') if remove: if os.path.exists(nvic_h): os.unlink(nvic_h) if os.path.exists(vector_nvic_c): os.unlink(vector_nvic_c) sys.exit(0) if not needs_update([__file__, infile], [nvic_h, vector_nvic_c]): sys.exit(0) makeparentdir(nvic_h) makeparentdir(vector_nvic_c) makeparentdir(cmsis) convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w'), open(cmsis, 'w')) if __name__ == "__main__": main() hackrf-0.0~git20230104.cfc2f34/scripts/lpcvtcksum000077500000000000000000000032441435536612600213040ustar00rootroot00000000000000#!/usr/bin/python # # Compute and insert the vector table checksum required for booting the # LPC43xx and some other NXP ARM microcontrollers. # # usage: lpcvtcksum firmware.bin # # This file is part of the libopencm3 project. # # Copyright (C) 2012 Michael Ossmann # # This library is free software: you can redistribute it and/or modify # it under the terms of the GNU Lesser General Public License as published by # the Free Software Foundation, either version 3 of the License, or # (at your option) any later version. # # This library is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU Lesser General Public License for more details. # # You should have received a copy of the GNU Lesser General Public License # along with this library. If not, see . import sys, struct binfile = open(sys.argv[1], 'r+b') rawvectors = binfile.read(32) vectors = list(struct.unpack('